M74HC652B1R [STMICROELECTRONICS]
HC652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HC651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.; HC652八路总线收发器/寄存器3 -STATE HC651八路总线收发器/寄存器3 -STATE , INV 。型号: | M74HC652B1R |
厂家: | ST |
描述: | HC652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HC651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV. |
文件: | 总12页 (文件大小:204K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M74HC651
M74HC652
HC651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
HC652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
.
HIGH SPEED
fMAX = 73 MHz (TYP.) AT VCC = 5V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 6 mA (mIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
.
.
.
.
.
.
.
B1R
M1R
(Plastic Package)
(Micro Package)
ORDER CODES :
M74HCXXXM1R
M74HCXXXB1R
VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS651/652
PIN CONNECTIONS (top view)
DESCRIPTION
M74HC651/652 are high speed CMOS OCTAL
BUS TRANSCEIVERS AND REGISTERS (3-
STATE), fabricated in silicon gate C2MOS technol-
ogy. They have the same high speed performance
of LSTTL combined with trueCMOS low power con-
sumption. These devices consist of bus transceiver
circuits, D-type flip-flops, and control circuitry ar-
ranged for multiplexed transmission of data directly
from the input bus or from the internal storage reg-
isters. Enable GABand GBA are provided to control
the transceiver functions.
Select AB and Select BA control pins are provided
to select whether real-time or stored data is trans-
fered. A low input level selects real-time data, and
a high selects stored data.
Data on the A or B bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the
appropriate clock pins (CLOCK AB or CLOCK BA)
regardless oftheselect or enable control pins. When
select AB and select BA are in the real-time transfer
mode, it is also possible to store data without using
the internal D-type flip-flops by simultaneously en-
abling GAB and GBA. In this configuration each out-
put reinforces its input. Thus, when all other data
sources to the two sets of bus lines are at high im-
pedance, each set of bus lines will remain at its last
state. All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
GAB, GAB, CAB,
SAB, SBA, CBA
A, B
October 1993
1/12
M74HC651/652
LOGIC DIAGRAM (HC652)
Note : In case of M74HC652 output inverter marked * at A bus and B bus are eliminated.
TIMING CHART
2/12
M74HC651/652
TRUTH TABLE
HC652 (The truth table for HC651 is the same as this, but with the outputs inverted)
GAB GBA CAB CBA SAB SBA
A
B
FUNCTION
INPUTS
Z
INPUTS
Z
Both the A bus and the B bus are inputs
The output functions of the A and B bus are disabled
X
X
X
X
X
X
L
H
INPUTS
INPUTS
Both the A and B buz are used for inputs to the
internal flip-flops. Data at the bus will be stored on
low to high transition of the clock inputs
OUTPUTS INPUTS
The A bus are outputs and the B bus are inputs
The data at the B bus are displayed at the A bus
X*
X*
X
X
X
L
L
L
H
L
L
H
L
The data at the B bus ar displayed at the A bus.
The data of the B bus are stored to the internal
flip-flop on low to high transition of th clock pulse
H
H
L
L
X*
X*
X
X
X
H
H
Qn
X
The data stored to the internal flip-flop are dispayed
at the A bus
L
L
The data at the B bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
A bus
H
H
INPUTS OUTPUTS The A bus are inputs and the B bus are outputs
L
H
L
L
H
L
The data at the A bus are displayed at the B bus
X
X
X*
X*
L
L
X
X
The data at the A bus are displayed at the B bus.
The data of the A bus are stored to the internal flip-
flop on low to high transition of the clock pulse
H
H
H
H
X*
X*
H
H
X
X
X
Qn
The data stored to the internal flip-flops are
displayed at the B bus
L
L
the data at the A bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
B bus
H
H
OUTPUTS OUTPUTS Both the A bus and the B bus are outputs
X
X
H
H
H
H
Qn
Qn
The data stored to the internal flip-flops are
displayed at the A and B bus respectively
H
L
Qn
Qn
The output at the A bus are displayed at the B bus,
the output at the B bus are displayed at the A bus
respectively
X
Z
: DON’T CARE
: HIGH IMPEDANCE
Qn : THE DATA STOREDTO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF
THE CLOCK INPUTS
3/12
M74HC651/652
PIN DESCRIPTION
PIN No
SYMBOL
CLOCK AB
SELECT AB
GAB
NAME AND FUNCTION
A to B Clock Input (LOW to HIGH, Edge-Trigged)
Select A to B Source Input
1
2
3
Direction Control Input
4, 5, 6, 7, 8, 9, 10, 11
A1 to A8
B1 to B8
GBA
A data Inputs/Outputs
20, 19, 18, 17, 16, 15, 14, 13
B Data Inputs/Outputs
21
22
23
12
24
Output Enable Input (Active LOW)
Select B to A Source Input
SELECT BA
CLOCK BA
GND
B to A Clock Input (LOW to HIGH, Edge-Triggered)
Ground (0V)
VCC
Positive Supply Voltage
IEC LOGIC SYMBOLS
HC651
HC652
4/12
M74HC651/652
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
Unit
Supply Voltage
-0.5 to +7
V
DC Input Voltage
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
V
V
VO
DC Output Voltage
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 35
ICC or IGND DC VCC or Ground Current
± 70
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
0 to VCC
0 to VCC
-40 to +85
0 to 1000
0 to 500
0 to 400
V
VO
Output Voltage
V
oC
Top
Operating Temperature:
tr, tf
Input Rise and Fall Time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
ns
5/12
M74HC651/652
DC SPECIFICATIONS
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
-40 to 85 oC
Symbol
Parameter
Unit
V
VIH
High Level Input Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
High Level Output Voltage
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
VI =
VIH
or
IO=-20 µA
V
V
5.9
VIL
IO=-6.0 mA 4.18 4.31
4.13
5.63
IO=-7.8 mA 5.68
5.8
0.0
0.0
0.0
VOL
Low Level Output Voltage
0.1
0.1
0.1
0.1
0.1
VI =
VIH
or
IO= 20 µA
0.1
VIL
IO= 6.0 mA
IO= 7.8 mA
0.17 0.26
0.18 0.26
±0.1
0.37
0.37
±1
II
Input Leakage Current
6.0 VI = VCC or GND
µA
µA
IOZ
3 State Output Off State Current
6.0
VI = VIH or VIL
±0.5
±5.0
VO = VCC or GND
ICC
Quiescent Supply Current
6.0 VI = VCC or GND
4
40
µA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 6 ns)
Test Conditions
Value
TA = 25 oC
-40 to 85 oC
Symbol
Parameter
Unit
ns
VCC CL
(V) (pF)
Min. Typ. Max. Min. Max.
tTLH
tTHL
Output Transition Time
2.0
25
7
60
12
75
15
50
4.5
6.0
2.0
6
10
13
tPLH
tPHL
Propagation Delay Time
(BUS - BUS)
74
21
18
91
26
22
98
28
24
116
33
28
150
30
190
38
50
ns
4.5
6.0
26
32
2.0
150
4.5
190
38
240
48
ns
6.0
2.0
32
41
tPLH
tPHL
Propagation Delay Time
(CLOCK - BUS)
210
42
265
53
50
ns
4.5
6.0
2.0
36
45
250
50
315
63
150
ns
4.5
6.0
43
54
6/12
M74HC651/652
AC ELECTRICAL CHARACTERISTICS (Continued)
Test Conditions
Value
TA = 25 oC
-40 to 85 oC
Unit
Symbol
Parameter
VCC CL
(V) (pF)
Min. Typ. Max. Min. Max.
tPLH
tPHL
Propagation Delay Time
(SELECT - BUS)
2.0
81
23
20
98
28
24
74
21
18
91
26
22
50
21
18
19
67
79
30
7
170
34
215
43
50
ns
ns
4.5
6.0
2.0
29
37
210
42
265
53
150
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
36
45
tPZL
tPZH
3-State Output Enable Time
175
35
220
44
50 RL = 1 KΩ
ns
30
37
215
43
270
54
150 RL = 1 KΩ
ns
37
46
tPLZ
tPHZ
Output Disable Time
175
35
220
44
50 RL = 1 KΩ
ns
30
37
fMAX
Maximum Clock Frequency
Minimum Clock Pulse Width
Minimum Set-up Time
Minimum Hold Time
6
4.8
24
28
50
50
50
50
MHz
ns
30
35
tW(H)
tW(L)
75
15
13
50
10
9
95
19
16
65
13
11
5
6
ts
16
4
ns
3
th
5
ns
5
5
5
5
CIN
Input Capacitance
5
10
10
pF
pF
CI/O
Bus Terminal Capacitance
10
CPD (*) Power Dissipation Capacitance
for HC651
for HC652
39
38
pF
(*) CPD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the followingequation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Channel)
7/12
M74HC651/652
SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM
WAVEFORM 1
WAVEFORM 2
WAVEFORM 3
WAVEFORM 5
WAVEFORM 4
GAB= ”L”
GBA = ”H”
8/12
M74HC651/652
TEST WAVEFORM ICC (Opr.)
INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.
9/12
M74HC651/652
Plastic DIP24 (0.25) MECHANICAL DATA
mm
inch
TYP.
0.025
0.018
DIM.
MIN.
0.23
15.2
TYP.
0.63
0.45
MAX.
MIN.
0.009
0.598
MAX.
a1
b
b1
b2
D
E
0.31
0.012
1.27
0.050
32.2
1.268
0.657
16.68
e
2.54
0.100
1.100
e3
F
27.94
14.1
0.555
I
4.445
3.3
0.175
0.130
L
P043A
10/12
M74HC651/652
SO24 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45° (typ.)
15.20
10.00
15.60
10.65
0.598
0.393
0.614
0.420
E
e
1.27
0.05
0.55
e3
F
13.97
7.40
0.50
7.60
1.27
0.291
0.19
0.299
0.050
L
S
8° (max.)
L
c1
b
e
s
e3
E
D
24
13
1
12
11/12
M74HC651/652
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
12/12
相关型号:
M74HC652M1
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, MICRO, PLASTIC, DIP-24
STMICROELECTR
M74HC652M1R
HC652 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE HC651 OCTAL BUS TRANSCEIVER/REGISTER 3-STATE, INV.
STMICROELECTR
M74HC652RM13TR
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, SOP-24
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明