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M74HCT573TTR [STMICROELECTRONICS]

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING; 八D型具有三态输出的非反相锁存
M74HCT573TTR
型号： M74HCT573TTR
厂家： ST    ST
描述：

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
八D型具有三态输出的非反相锁存

输出元件
文件： 总11页 (文件大小：231K)
中文：  中文翻译
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M74HCT573  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
■
■
■
■
■
■
HIGH SPEED:  
= 21ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 573  
TUBE  
T & R  
DIP  
SOP  
M74HCT573B1R  
M74HCT573M1R M74HCT573RM13TR  
M74HCT573TTR  
DESCRIPTION  
The M74HCT573 is an high speed CMOS OCTAL  
LATCH WITH 3-STATE OUTPUTS fabricated  
TSSOP  
2
with silicon gate C MOS technology.  
The 3-State output configuration and the wide  
choice of outline make bus organized system  
simple.  
The M74HCT573 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
This 8-BIT D-Type latches is controlled by a latch  
enable input (LE) and output enable input (OE).  
While the LE input is held at a high level, the Q  
outputs will follow the data input precisely. When  
the LE is taken low, the Q outputs will be latched  
precisely at the logic level of D input data.  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and while OE is at high level the outputs will  
be in a high impedance state.  
2
components.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  
M74HCT573  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
SYMBOL  
NAME AND FUNCTION  
1
OE  
3 State Output Enable  
Input (Active LOW)  
2, 3, 4, 5, 6,  
7, 8, 9  
D0 to D7  
Q0 to Q7  
Data Inputs  
12, 13, 14,  
15, 16, 17,  
18, 19  
3 State Latch Outputs  
11  
10  
20  
LE  
Latch Enable Input  
Ground (0V)  
GND  
V
Positive Supply Voltage  
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
Q
OE  
LE  
D
H
L
L
L
X
L
X
X
L
Z
NO CHANGE (*)  
H
H
L
H
H
X: Don’t Care  
Z: High Impedance  
(*): Q Outputs are latched at the time when the LE input is taken low logic level.  
LOGIC DIAGRAM  
2/11  
M74HCT573  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7  
V
V
CC  
V
DC Input Voltage  
-0.5 to V + 0.5  
I
CC  
V
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
-0.5 to V + 0.5  
V
O
CC  
I
± 20  
± 20  
mA  
mA  
mA  
mA  
mW  
°C  
IK  
I
OK  
I
± 35  
O
I
or I  
DC V  
or Ground Current  
CC  
± 70  
CC  
GND  
P
Power Dissipation  
500(*)  
-65 to +150  
300  
D
T
Storage Temperature  
Lead Temperature (10 sec)  
stg  
T
°C  
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is  
not implied  
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
4.5 to 5.5  
V
V
CC  
V
Input Voltage  
0 to V  
I
CC  
V
Output Voltage  
0 to V  
V
O
CC  
T
Operating Temperature  
-55 to 125  
0 to 500  
°C  
ns  
op  
t , t  
Input Rise and Fall Time (V = 4.5 to 5.5V)  
CC  
r
f
3/11  
M74HCT573  
DC SPECIFICATIONS  
Test Condition  
Value  
T
= 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
V
High Level Input  
Voltage  
4.5  
to  
IH  
2.0  
2.0  
2.0  
V
5.5  
V
Low Level Input  
Voltage  
4.5  
to  
IL  
0.8  
0.1  
0.8  
0.8  
V
V
5.5  
V
High Level Output  
Voltage  
I =-20 µA  
4.4  
4.5  
4.4  
4.4  
OH  
O
4.5  
I =-6.0 mA  
4.18 4.31  
0.0  
4.13  
4.10  
O
V
Low Level Output  
Voltage  
I =20 µA  
0.1  
0.1  
OL  
O
4.5  
5.5  
V
I =6.0 mA  
0.17 0.26  
0.33  
0.40  
O
I
Input Leakage  
Current  
I
V = V  
or GND  
CC  
± 0.1  
± 1  
± 1  
µA  
I
I
I
High Impedance  
Output Leakage  
Current  
OZ  
V = V or V  
IL  
I
IH  
5.5  
± 0.5  
± 5  
± 10  
µA  
V
= V or GND  
CC  
O
Quiescent Supply  
Current  
CC  
V = V  
or GND  
CC  
5.5  
5.5  
4
40  
80  
µA  
I
∆ I  
Additional Worst  
Case Supply  
Current  
Per Input pin  
V = 0.5V or  
2.0  
2.9  
3.0  
mA  
CC  
I
V = 2.4V  
I
Other Inputs at  
V
or GND  
CC  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)  
L
r
f
Test Condition  
Value  
T
= 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
C
L
CC  
(V) (pF)  
Min. Typ. Max. Min. Max. Min. Max.  
t
t
Output Transition  
Time  
TLH THL  
4.5  
50  
7
12  
15  
18  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
Propagation Delay  
Time (LE - Q,Q)  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
50  
150  
50  
21  
25  
19  
23  
19  
23  
33  
39  
30  
36  
30  
36  
41  
49  
38  
45  
38  
45  
50  
59  
45  
54  
45  
54  
PLH PHL  
t
Propagation Delay  
Time (D - Q,Q)  
PLH PHL  
150  
50  
t
t
Output Enable  
Time  
PZL PZH  
R = 1 KΩ  
L
150  
t
t
Output Disable  
Time  
PLZ PHZ  
R = 1 KΩ  
4.5  
4.5  
50  
50  
18  
7
25  
15  
31  
19  
38  
22  
L
t
t
Minimum Pulse  
Width (LE)  
W(L)  
W(H)  
t
t
Minimum Set-Up  
Time  
s
4.5  
4.5  
50  
50  
4
10  
5
13  
5
15  
5
ns  
ns  
Minimum Hold  
Time  
h
4/11  
M74HCT573  
CAPACITIVE CHARACTERISTICS  
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
T
= 25°C  
Symbol  
Parameter  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
C
Input Capacitance  
5
10  
10  
10  
pF  
pF  
IN  
Output  
Capacitance  
C
10  
OUT  
C
Power Dissipation  
Capacitance (note  
1)  
PD  
51  
pF  
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without  
PD  
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I  
Flop)  
= C x V x f + I /8 (per Flip  
CC(opr)  
PD CC IN CC  
TEST CIRCUIT  
TEST  
SWITCH  
t
t
t
, t  
Open  
PLH PHL  
, t  
V
CC  
PZL PLZ  
, t  
GND  
PZH PHZ  
C
R
R
= 50pF/150pF or equivalent (includes jig and probe capacitance)  
L
1
T
= 1KΩ or equivalent  
= Z  
of pulse generator (typically 50Ω)  
OUT  
5/11  
M74HCT573  
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP  
AND HOLD TIMES (f=1MHz; 50% duty cycle)  
6/11  
M74HCT573  
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)  
WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)  
7/11  
M74HCT573  
Plastic DIP-20 (0.25) MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
0.254  
1.39  
MAX.  
MIN.  
0.010  
0.055  
MAX.  
a1  
B
b
1.65  
0.065  
0.45  
0.25  
0.018  
0.010  
b1  
D
E
e
25.4  
1.000  
8.5  
2.54  
22.86  
0.335  
0.100  
0.900  
e3  
F
7.1  
0.280  
0.155  
I
3.93  
L
3.3  
0.130  
Z
1.34  
0.053  
P001J  
8/11  
M74HCT573  
SO-20 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
2.65  
0.2  
MIN.  
MAX.  
0.104  
0.008  
0.096  
0.019  
0.012  
A
a1  
a2  
b
0.1  
0.004  
2.45  
0.49  
0.32  
0.35  
0.23  
0.014  
0.009  
b1  
C
0.5  
0.020  
c1  
D
45° (typ.)  
12.60  
10.00  
13.00  
10.65  
0.496  
0.393  
0.512  
0.419  
E
e
1.27  
0.050  
0.450  
e3  
F
11.43  
7.40  
0.50  
7.60  
1.27  
0.75  
0.291  
0.020  
0.300  
0.050  
0.029  
L
M
S
8° (max.)  
PO13L  
9/11  
M74HCT573  
TSSOP20 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.2  
MIN.  
MAX.  
0.047  
0.006  
0.041  
0.012  
0.0089  
0.260  
0.260  
0.176  
A
A1  
A2  
b
0.05  
0.8  
0.15  
1.05  
0.30  
0.20  
6.6  
0.002  
0.031  
0.007  
0.004  
0.252  
0.244  
0.169  
0.004  
0.039  
1
0.19  
0.09  
6.4  
c
D
6.5  
6.4  
0.256  
0.252  
E
6.2  
6.6  
E1  
e
4.3  
4.4  
4.48  
0.173  
0.65 BSC  
0.0256 BSC  
K
0°  
8°  
0°  
8°  
L
0.45  
0.60  
0.75  
0.018  
0.024  
0.030  
A2  
A
K
L
b
e
A1  
E
c
D
E1  
PIN 1 IDENTIFICATION  
1
0087225C  
10/11  
M74HCT573  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
© The ST logo is a registered trademark of STMicroelectronics  
© 2000 STMicroelectronics - Printed in Italy - All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
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Singapore - Spain - Sweden - Switzerland - United Kingdom  
© http://www.st.com  
11/11  

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