M76DW63000A-70ZT [STMICROELECTRONICS]
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product; 64Mbit的（ X8 / X16 ，多个银行，引导块）快闪记忆体和8Mbit的/ 4Mbit的SRAM ， 3V电源，多个存储产品
| 型号： | M76DW63000A-70ZT |
| 厂家： | 
ST |
| 描述： | 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product |
| 文件： | 总27页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M76DW63000A
M76DW62000A
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and
8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product
PRELIMINARY DATA
FEATURES SUMMARY
■ MULTIPLE MEMORY PRODUCT
Figure 1. Package
– 64 Mbit (8Mb x8 or 4Mb x16), Multiple Bank,
Page, Boot Block, Flash Memory
– SRAM: 8Mbit (512K x 16) for
M76DW63000A, or 4Mbit (256K x 16) for
M76DW62000A
■ SUPPLY VOLTAGE
FBGA
– V
– V
= V
= 2.7V to 3.3V
CCF
PPF
CCS
= 12V for Fast Program (optional)
■ ACCESS TIME: 70, 90ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
LFBGA73 (ZA)
8 x 11.6mm
– Device Code: 227Eh + 2202h + 2201h
FLASH MEMORY
■ ASYNCHRONOUS PAGE READ MODE
– Page Width: 4 Words
– Page Access: 25, 30ns
■ V /WP PIN for FAST PROGRAM and WRITE
– Random Access: 70, 90ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
– 4 Words/ 8 Bytes at-a-time Program
■ MEMORY BLOCKS
PP
PROTECT
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
– 64 bit Security Code
– Quadruple Bank Memory Array:
8Mbits + 24Mbits + 24Mbits + 8Mbits
■ EXTENDED MEMORY BLOCK
– Extra block used as security block or to store
additional information
– Parameter Blocks (at both Top and Bottom)
■ DUAL OPERATIONS
■ 100,000 PROGRAM/ERASE CYCLES per
– While Program or Erase in a group of banks
(from 1 to 3), Read in any of the other banks
BLOCK
SRAM
■ PROGRAM/ERASE SUSPEND and RESUME
■ 8Mbit (512K x 16) or 4Mbit (256K x 16)
MODES
■ ACCESS TIME: 70ns
– Read from any Block during Program
Suspend
■ LOW V
DATA RETENTION: 1.5V
CCS
– Read and Program another Block during
Erase Suspend
■ POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
September 2003
1/27
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M76DW63000A, M76DW62000A
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
Write Protect (V WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PP/ PP/
Reset/Block Temporary Unprotect (RPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
V
V
Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CCF
CCS
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Flash Memory DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline14
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . . 15
2/27
M76DW63000A, M76DW62000A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. SRAM Write AC Waveforms, W Controlled with G Low. . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . 23
Table 11. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. SRAM Low V
Data Retention AC Waveforms, E1 or UB / LB Controlled . . 25
S S S
CCS
CCS
Table 12. SRAM Low V
Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
M76DW63000A, M76DW62000A
SUMMARY DESCRIPTION
The M76DW62000A is a low voltage Multiple
Memory Product which combines two memory de-
vices; a 64 Mbit Multiple Bank, Boot Block Flash
memory (M29DW640D) and an 8 or 4Mbit SRAM.
This document should be read in conjunction with
the M29DW640D datasheet.
Recommended operating conditions do not allow
both the Flash and SRAM devices to be active at
the same time.
Table 1. Signal Names
1
Address Inputs
A0-A21
DQ0-DQ7
DQ8-DQ14
DQ15A–1
G
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Output Enable input
The memory is offered in an LFBGA73
(8 x 11.6mm, 0.8 mm pitch) package and is sup-
plied with all the bits erased (set to ‘1’).
W
Write Enable input
V
CCF
Flash Power Supply
Figure 2. Logic Diagram
V
V
/WP
V
/Write Protect
PP
PP
Ground
SS
V
/WP
V
PP
V
CCS
V
SSS
SRAM Power Supply
SRAM Ground
V
CCF
CCS
22
NC
Not Connected Internally
A0-A21
Flash Memory Control Functions
15
E
F
E
Chip Enable input
F
DQ0-DQ14
DQ15A–1
G
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
F
W
RB
RP
M76DW63000A
M76DW62000A
F
BYTE
Byte/Word Organization Select
RB
BYTE
SRAM Control Functions
E1 , E2
Chip Enable inputs
E1
E2
S
S
S
UB
Upper Byte Enable input
Lower Byte Enable input
S
S
LB
S
UB
LB
S
Note: 1. A21-A19 are not connected to the SRAM component of
the M76DW63000A, and A21-A18 are not connected to
the SRAM component of the M76DW62000A.
S
V
SS
AI08188B
4/27
M76DW63000A, M76DW62000A
Figure 3. LFBGA Connections (Top view through package)
9
10
1
2
3
4
5
6
7
8
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
V
/WP
PP
A8
A19
A9
A7
A6
A5
A4
A11
A12
A13
A14
NC
W
LB
S
A3
A2
A1
A0
UB
RP
F
E2S
A20
A15
A21
S
A18
A17
DQ1
RB
NC
NC
A10
DQ6
NC
NC
NC
G
H
J
V
A16
SS
DQ15
/A-1
E
F
G
DQ9
DQ10
DQ2
DQ3
DQ4
DQ13
DQ12
DQ5
BYTE
E1
V
V
V
DQ0
DQ8
DQ7
S
CCF
DQ11
NC
CCS
SS
K
M
N
NC
DQ14
NC
NC
NC
NC
NC
AI08189
5/27
M76DW63000A, M76DW62000A
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
Address Inputs (A0-A21). Addresses A0-A18
(for
M76DW63000A),
or
A0-A17
(for
M76DW62000A), are common inputs for the Flash
Memory and the SRAM components. The other
lines (A19-A21, or A18-21, respectively) are inputs
for the Flash Memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the
internal state machine. The Flash memory is ac-
When V /Write Protect is Low, V , the memory
PP
IL
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V /Write Protect is Low, even when RP is
PP
F
at V .
ID
When V /Write Protect is High, V , the memory
PP
IH
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
cessed through the Chip Enable (E ) and Write
F
Enable (W) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (W).
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
When V /Write Protect is raised to V the mem-
PP
PP
ory automatically enters the Unlock Bypass mode.
When V /Write Protect returns to V or V nor-
PP
IH
IL
mal operation resumes. During Unlock Bypass
Program operations the memory draws I from
PP
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
than t
to V
VHVPP
and from V
. See the M29DW640D datasheet for
to V must be slower
IH
PP
PP IH
V . When BYTE is Low, V , these pins are not
IH
IL
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
more details.
Never raise V /Write Protect to V
from any
PP
PP
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
Data Input/Output or Address Input (DQ15A–
1). When BYTE is High, V , this pin behaves as
a Data Input/Output pin (as DQ8-DQ14). When
The V /Write Protect pin must not be left floating
or unconnected or the device may become unreli-
IH
PP
BYTE is Low, V , this pin behaves as an address
able. A 0.1µF capacitor should be connected be-
tween the V /Write Protect pin and the V
PP SS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
IL
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Unlock Bypass Program, I
.
PP
Reset/Block Temporary Unprotect (RP ). The
F
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Flash Chip Enable (E ). The Chip Enable input
F
activates the memory, allowing Bus Read and Bus
Write operations to be performed. When Chip En-
able is High, V , all other pins are ignored.
IH
Note that if V /WP is at V , then the two outer-
PP
IL
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the device.
most boot blocks will remain protected even if RP
is at V .
ID
F
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the device.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V , for at least
IL
t
. After Reset/Block Temporary Unprotect
PLPX
V
Write Protect (V /WP). The
V
/Write
PP
PP/
PP
PP
goes High, V , the memory will be ready for Bus
Read and Bus Write operations after t
IH
Protect pin provides two functions. The V func-
or
PHEL
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
quired for Program operations. This is achieved
t
,
whichever occurs last. See the
RHEL
M29DW640D datasheet for more details.
6/27
M76DW63000A, M76DW62000A
Holding RP at V will temporarily unprotect the
protected Blocks in the memory. Program and
not allowed to set E at V E1 at V and E2 at
F
ID
F
IL,
S
IL
S
V
at the same time.
IH
Erase operations on all blocks will be possible.
SRAM Upper Byte Enable (UB ). The Upper
Byte Enable enables the upper bytes for SRAM
S
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
(DQ8-DQ15). UB is active low.
S
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
SRAM Lower Byte Enable (LB ). The
Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LB is active low.
S
S
V
Supply Voltage (2.7V to 3.3V). V
pro-
CCF
CCF
erations Ready/Busy is Low, V . Ready/Busy is
OL
vides the power supply for all operations (Read,
Program and Erase).
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
The Command Interface is disabled when the
V
Supply Voltage is less than the Lockout Volt-
CCF
age, V
. This prevents Bus Write operations
LKO
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CCF
SS
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
lect is Low, V , the Flash memory is in x8 mode,
IL
when it is High, V , the Flash memory is in x16
IH
Erase operations, I
.
CC3
mode.
V
Supply Voltage (2.7V to 3.3V). V
pro-
CCS
CCS
SRAM Chip Enable (E1 , E2 ). The Chip En-
S
S
vides the power supply for the SRAM control pins.
able inputs activate the SRAM memory control
V
Ground. V is the ground reference for all
SS
SS
logic, input buffers and decoders. E1 at V or
S
IH
voltage measurements in the Flash and SRAM
E2 at V deselects the memory and reduces the
S
IL
chips. The device features two V pins both of
SS
power consumption to the standby level. E1 and
S
which must be connected to the system ground.
E2 can also be used to control writing to the
S
SRAM memory array, while W remains at V It is
IL.
7/27
M76DW63000A, M76DW62000A
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies. They are distinguished by three
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
chip enable inputs: E for the Flash memory and,
F
E1 and E2 for the SRAM.
S
S
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
Figure 4. Functional Block Diagram
V
/WP
V
PP
CCF
E
F
F
RB
RP
BYTE
Flash Memory
64 Mbit (x8 or x16)
A[n]-A21
A0-A[m]
G
V
DQ0-DQ15/A-1
CCS
W
SRAM
8Mbit or 4Mbit (x16)
E1
E2
S
S
UB
LB
S
S
V
SS
AI08190B
Note: Where n=19 and m=18 for M76DW63000A, and n=18 and m=17 for M76DW62000A.
8/27
M76DW63000A, M76DW62000A
Table 2. Main Operation Modes
Operation
E
RP
E1
E2
UB
LB
S
G
W
DQ15-DQ8
DQ7-DQ0
F
F
S
S
S
(2)
Mode
V
V
V
V
IH
Read
Write
SRAM must be disabled
SRAM must be disabled
Data Output
IL
IH
IL
V
V
V
IH
V
IH
V
IL
Data Input
Hi-Z
IL
V
CC
Standby
X
X
Any SRAM mode is allowed
IH
±0.3
Output
Disable
V
V
V
X
Any SRAM mode is allowed
Any SRAM mode is allowed
Hi-Z
IH
IH
IH
V
Reset
X
X
X
Hi-Z
IL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Data out Word Read
IL
IL
IL
IH
IH
IH
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
IL
IL
Flash Memory must be
disabled
Read
Data out
Hi-Z
Hi-Z
IL
IH
V
IL
Data out
IH
V
V
V
V
V
V
X
Data in Word Write
IL
IL
IL
IL
IL
IL
Flash Memory must be
disabled
V
V
Write
X
X
X
X
X
Data in
Hi-Z
Hi-Z
IH
V
IL
Data in
IH
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
Standby/
Power
Down
Any Flash Memory
mode is allowable
V
IH
V
IH
X
X
X
X
V
X
X
X
IL
IH
IH
IH
V
V
V
V
V
V
V
V
V
V
IL
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
Output
Disable
Any Flash Memory
mode is allowable
V
V
V
V
V
V
V
IH
IL
V
IL
IH
Note: 1. X = Don’t Care = V or V
.
IH
IL
2. This table is valid when BYTE = V . This table is also valid when BYTE = V , with the only difference that DQ15-DQ8 are always
IH
IL
high impedance when the Flash Memory component is being accessed.
3. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
the stacked product.
4. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
9/27
M76DW63000A, M76DW62000A
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–40
Max
85
(1)
T
°C
°C
°C
V
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Flash Supply Voltage
Identification Voltage
Program Voltage
T
–50
125
150
BIAS
T
–65
STG
V
IO
V
+0.3
–0.5
–0.6
–0.6
–0.6
–0.5
CCF
V
4
V
CCF
V
ID
13.5
13.5
3.8
V
V
PPF
V
V
SRAM Supply Voltage
V
CCS
Note: 1. Depends on range.
10/27
M76DW63000A, M76DW62000A
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
The operating and AC measurement parameters
given in this section (see Table 4 below) corre-
spond to those of the stand-alone Flash and
SRAM devices. For compatibility purposes, the
M29DW640D voltage range is restricted to V
in the stacked product.
CCS
Table 4. Operating and AC Measurement Conditions
Flash Memory
SRAM
70
Parameter
70
Units
Min
2.7
–
Max
3.6
–
Min
–
Max
–
V
V
Supply Voltage
V
V
CCF
Supply Voltage
2.7
–40
3.3
85
CCS
Ambient Operating Temperature
–40
85
°C
pF
ns
V
Load Capacitance (C )
30
30
L
Input Rise and Fall Times
10
3.3
0 to V
0 to V
Input Pulse Voltages
CCF
CCF
V
CCF
/2
V
/2
CCF
Input and Output Timing Ref. Voltages
V
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
CCF
V
CCF
V
/2
CCF
V
PP
0V
V
CCF
25kΩ
AI08186
DEVICE
UNDER
TEST
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI08187
L
Table 5. Device Capacitance
Symbol
Parameter
Test Condition
Typ
Max
12
Unit
C
V
= 0V, f=1 MHz
= 0V, f=1 MHz
Input Capacitance
Output Capacitance
pF
pF
IN
IN
C
OUT
V
OUT
15
Note: Sampled only, not 100% tested.
11/27
M76DW63000A, M76DW62000A
Table 6. Flash Memory DC Characteristics
M76DW63000A,
M76DW62000A
Symbol
Parameter
Test Condition
Unit
Min
Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±1
±1
µA
µA
LI
IN
CC
I
LO
0V ≤ V ≤ V
OUT CC
E = V , G = V ,
F
IL
IH
(2)
Supply Current (Read)
10
100
20
mA
µA
mA
I
CC1
f = 6MHz
E = V ±0.2V,
F
CC
I
Supply Current (Standby)
CC2
RP = V ±0.2V
F
CC
V
V
/WP =
or V
PP
Supply Current (Program/
Erase)
Program/Erase
Controller active
(1,2)
IL
IH
I
CC3
V
/WP = V
PP
20
mA
V
PP
V
V
Input Low Voltage
Input High Voltage
–0.5
0.8
IL
0.7V
V
+0.3
CC
V
IH
CC
Voltage for V /WP Program
PP
Acceleration
V
V
= 3.0V ±10%
11.5
12.5
V
V
I
CC
CC
PP
Current for V /WP Program
PP
Acceleration
= 3.0V ±10%
= 1.8mA
15
mA
PP
V
OL
I
I
Output Low Voltage
Output High Voltage
Identification Voltage
0.45
V
V
V
OL
V
OH
V
–0.4
= –100µA
CC
OH
V
11.5
1.8
12.5
2.3
ID
Program/Erase Lockout Supply
Voltage
V
LKO
V
Note: 1. Sampled only, not 100% tested.
2. In Dual operations the Supply Current will be the sum of I
(read) and I
CC1
(program/erase).
CC3
12/27
M76DW63000A, M76DW62000A
Table 7. SRAM DC Characteristics
M76DW63000A
M76DW62000A
Symbol
Parameter
Test Condition
Unit
Min
Typ
Max Min
Typ Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±1
±1
±1
µA
µA
LI
IN
CCS
0V ≤ V
≤ V
CCS,
OUT
I
LO
±1
SRAM Outputs Hi-Z
E1 ≥ V – 0.2V
S
CCS
V
V
≥ V
– 0.2V or V ≤ 0.2V
IN
CCS
IN
2
8
8
25
7
7
15
µA
f = fmax (A0-A18 and DQ0-
DQ15 only)
f = 0 (G , W , UB and LB )
I
V
Standby Current
CCS
CC
S
S
S
S
E1 ≥ V
– 0.2V
S
CCS
≥ V
– 0.2V or V ≤ 0.2V,
25
12
15
12
µA
IN
CCS
IN
f = 0
f = fmax = 1/
,
AVAV
5.5
1.5
5.5
1.5
mA
V
CCS
= 3.3V, I
= 0 mA
OUT
I
Supply Current
CC
f = 1MHz,
= 3.3V, I
3
3
mA
V
V
CCS
= 0 mA
OUT
V
V
Input Low Voltage
Input High Voltage
–0.3
2.2
0.8
–0.3
2.2
0.8
IL
V
V
CCS
+0.3
CCS
V
IH
+0.3
V
= V min
= 2.1mA
CCS
CC
V
Output Low Voltage
Output High Voltage
0.4
0.4
V
V
OL
I
OL
V
CCS
= V min
CC
= –1.0mA
V
OH
2.4
2.4
I
OH
Note: 1. Sampled only, not 100% tested.
2. A0-A18 for the M76DW63000A, A0-A17 for the M76DW62000A.
13/27
M76DW63000A, M76DW62000A
PACKAGE MECHANICAL
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
e
b
ddd
A
A2
A1
BGA-Z50
Note: Drawing is not to scale.
14/27
M76DW63000A, M76DW62000A
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.400
0.0551
0.250
0.0098
0.910
0.400
8.000
7.200
0.0358
0.0157
0.3150
0.2835
0.350
7.900
0.450
8.100
0.0138
0.3110
0.0177
0.3189
D
D1
ddd
E
0.100
0.0039
0.4606
11.600
8.800
0.800
0.400
1.400
0.400
0.400
11.500
–
11.700
0.4567
0.3465
0.0315
0.0157
0.0551
0.0157
0.0157
0.4528
–
E1
e
–
–
FD
FE
SD
SE
–
–
–
–
–
–
–
–
15/27
M76DW63000A, M76DW62000A
PART NUMBERING
Table 9. Ordering Information Scheme
Example:
M76DW 6 2 0 0 0
A
70 Z T
Device Type
M76 = MMP (Flash + SRAM)
Architecture
D = Dual Operation
Operating Voltage
W = V
= V
= 2.7V to 3.3V
CCS
CCF
Flash Device Size (Die1 Density)
6 = 64 Mbit
SRAM Device Size (Die2 Density)
2 = 4 Mbit
3 = 8 Mbit
Die3
0 = Die3 Density
Die4
0 = Die4 Density
Flash Specification Details
0 = Multiple Bank
Stacked Specification Details
A = 0.15µm Flash & SRAM
Speed
70 = 70ns
90 = 90ns
Package and Temperature Range
Z = LFBGA73: 8 x 11.6mm, 0.8mm pitch
Option
T = Tape & Reel packing
Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
16/27
M76DW63000A, M76DW62000A
FLASH MEMORY DEVICE
The M76DW62000A contains one 64 Mbit Flash
memory. For detailed information on how to use
the Flash memory refer to the M29DW640D
datasheet, which is available on the STMicroelec-
tronics web site, www.st.com.
SRAM DEVICE
SRAM SUMMARY DESCRIPTION
The SRAM is an 8Mbit or 4Mbit asynchronous ran-
dom access memory which features a super low
voltage operation and low current consumption
with an access time of 70ns under all conditions.
The memory operations can be performed using a
single low voltage supply, 2.7V to 3.3V, which is
the same as the Flash voltage supply.
Figure 8. SRAM Logic Diagram
DATA IN DRIVERS
A0-A10
256Kb x 16
RAM Array
DQ0-DQ7
2048 x 2048
DQ8-DQ15
COLUMN DECODER
UB
S
W
S
A11-A18 or A11-A17
G
S
LB
S
E1
S
POWER-DOWN
CIRCUIT
E2
S
UB
LB
S
S
AI07939B
17/27
M76DW63000A, M76DW62000A
SRAM OPERATIONS
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
If the Output is enabled (E1 =V , E2 =V and
S IL S IH
G =V ), then W will return the outputs to high im-
S
IL
pedance within t
of its falling edge. Care must
WLQZ
be taken to avoid bus contention in this type of op-
eration. The Data input must be valid for t
be-
DVWH
fore the rising edge of Write Enable, for t
DVE1H
before the rising edge of E1 or for t
before
S
DVE2L
the falling edge of E2 , whichever occurs first, and
S
mode whenever Write Enable, W , is at V , Out-
S
IH
remain valid for t
, t
or t
(see Table
WHDX E1HAX
E2LAX
put Enable, G , is at V , Chip Enable, E1 , is at
S
IL
S
11, SRAM Write AC Characteristics, Figures 12,
13, 14 and 15).
V , Chip Enable, E2 , is at V , and Byte Enable
IL
S
IH
inputs, UB and LB are at V .
S
S
IL
Standby/Power-Down. The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 10,
SRAM Read AC Characteristics, Figure 11, SRAM
Standby AC Waveforms). The SRAM is in Standby
mode whenever either Chip Enable is deasserted,
Valid data will be available on the output pins after
a time of t after the last stable address. If the
Chip Enable or Output Enable access times are
AVQV
not met, data access will be measured from the
limiting parameter (t
, t
, or t
) rath-
E1LQV E2HQV
GLQV
er than the address. Data out may be indetermi-
nate at t , t and t , but data lines
E1 at V or E2 at V . It is also possible when
S
IH
S
IL
E1LQX E2HQX
GLQX
UB and LB are at V .
S
S
IH
will always be valid at t
(see Table 10, Table
AVQV
10, Figures 9 and 10, SRAM Read AC Character-
istics).
Write. Write operations are used to write data to
Data Retention. The SRAM data retention per-
formance as V goes down to V are de-
CCS
DR
scribed in Table 12, SRAM Low V
Data
CCS
Retention Characteristic, and Figure 16, SRAM
Low V Data Retention AC Waveforms, E1 or
the SRAM. The SRAM is in Write mode whenever
CCS
S
W and E1 are at V , and E2 is at V . Either the
S
IL
S
IH
UB / LB Controlled. In E1 controlled data reten-
S
S
S
Chip Enable inputs, E1 and E2 , or the Write En-
S
S
tion mode, the minimum standby current mode is
entered when E1 ≥ V – 0.2V and E2 ≤ 0.2V
able input, W , must be deasserted during ad-
S
S
CCS
S
dress transitions for subsequent write cycles.
or E2 ≥ V
– 0.2V. In E2 controlled data re-
S
CCS
S
A Write operation is initiated when E1 is at V ,
S
IL
tention mode, minimum standby current mode is
E2 is at V and W is at V . The data is latched
S
IH
IL
entered when E2 ≤ 0.2V.
S
on the falling edge of E1 , the rising edge of E2
S
S
Output Disable. The data outputs are high im-
or the falling edge of W , whichever occurs last.
S
pedance when the Output Enable, G , is at V
S
IH
The Write cycle is terminated on the rising edge of
with Write Enable, W , at V .
S
IH
E1 , the rising edge of W or the falling edge of
S
E2 , whichever occurs first.
S
18/27
M76DW63000A, M76DW62000A
Figure 9. SRAM Read Mode AC Waveforms, Address Controlled
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DATA VALID
DQ0-DQ15
DATA VALID
AI07942
Note: E1 = Low, E2 = High, G = Low, UB and/or LB = High, W = High.
S
S
S
S
Figure 10. SRAM Read AC Waveforms, G Controlled
tAVAV
A0-A17
E1S
VALID
tE1LQV
tE1HQZ
tE1LQX
tE2HQV
tE2LQZ
E2S
tE2HQX
tBLQV
tBHQZ
UBS, LBS
tBLQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
DATA VALID
AI07943b
Note: Write Enable (W) = High. Address Valid prior to or at the same time as E1 , UB and LB going Low.
S
S
S
Figure 11. SRAM Standby AC Waveforms
E1S
E2S
tPU
tPD
ICC
50%
AI07913b
19/27
M76DW63000A, M76DW62000A
Table 10. SRAM Read AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
Max
t
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
AVAV
RC
t
t
ACC
Address Valid to Output Valid
70
AVQV
t
t
OH
Address Transition to Output Transition
UB , LB Disable to Hi-Z Output
10
AXQX
t
t
BHZ
25
70
BHQZ
S
S
t
t
UB , LB Access Time
S S
BLQV
AB
t
t
UB , LB Enable to Low-Z Output
S S
5
BLQX
BLZ
t
E1LQV
t
Chip Enable 1 Low or Chip Enable 2 High to Output Valid
70
ns
ns
ns
ACS1
t
E2HQV
t
Chip Enable 1 Low or Chip Enable 2 High to Output
Transition
E1LQX
t
10
CLZ1
t
E2HQX
t
E1HQZ
t
Chip Enable High or Chip Enable 2 Low to Output Hi-Z
25
HZCE
t
E2LQZ
t
t
OHZ
Output Enable High to Output Hi-Z
25
35
ns
ns
ns
ns
GHQZ
t
t
Output Enable Low to Output Valid
GLQV
OE
t
t
OLZ
Output Enable Low to Output Transition
Chip Enable 1 High or Chip Enable 2 Low to Power Down
5
0
GLQX
(1)
70
t
t
PD
(1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
ns
PU
Note: 1. Sampled only. Not 100% tested.
20/27
M76DW63000A, M76DW62000A
Figure 12. SRAM Write AC Waveforms, W Controlled
tAVAV
A0-A17
VALID
tAVWH
tE1LWH
tE2HWH
tWHAX
E1S
E2S
tAVWL
tWLWH
W
tBLWH
UBS, LBS
G
tGHQZ
tDVWH
INPUT VALID
tWHDZ
Note 2
DQ0-DQ15
AI07944b
Note: 1. W, E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G) = Low (otherwise, DQ0-DQ15 are high
S
S
S
S
impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
2. The I/O pins are in output mode and input signals must not be applied.
21/27
M76DW63000A, M76DW62000A
Figure 13. SRAM Write AC Waveforms, E1 Controlled
S
tAVAV
A0-A17
VALID
tAVE1H
tAVE2L
tE1LE1H
tE2HE2L
tAVE1L
tAVE2H
tE1HAX
tE2LAX
E1S
E2S
tWLE1H
tWLE2L
W
tBLE1H
tBLE2L
UBS, LBS
G
tDVE1H
tDVE2L
tE1HDZ
tE2LDZ
tGHQZ
DQ0-DQ15
INPUT VALID
Note 3
AI07945b
Note: 1. W , E1 , E2 , UB and/or LB must be asserted to initiate a write cycle. Output Enable (G ) = Low (otherwise, DQ0-DQ15 are high
S
S
S
S
S
S
impedance). If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
2. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
3. The I/O pins are in output mode and input signals must not be applied.
22/27
M76DW63000A, M76DW62000A
Figure 14. SRAM Write AC Waveforms, W Controlled with G Low
tAVAV
VALID
A0-A17
tAVWH
tE1LWH
tE2HWH
tWHAX
E1S
E2S
tBLWH
UBS, LBS
tAVWL
tWLWH
W
tWHQX
tWHDZ
tWLQZ
tDVWH
INPUT VALID
DQ0-DQ15
AI07946b
Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
Figure 15. SRAM Write Cycle Waveform, UB and LB Controlled, G Low
S
S
tAVAV
VALID
A0-A17
tAVBH
tE1LBH
tE2HBH
E1S
E2S
tAVBL
tBLBH
tBHAX
UBS, LBS
tWLBH
W
tDVBH
INPUT VALID
tBHDZ
DQ0-DQ15
AI07947b
Note: 1. If E1 , E2 and W are deasserted at the same time, DQ0-DQ15 remain high impedance.
S
S
23/27
M76DW63000A, M76DW62000A
Table 11. SRAM Write AC Characteristics
SRAM
Symbol
Alt
Parameter
Unit
Min
Max
t
t
WC
Write Cycle Time
70
ns
AVAV
t
,
AVE1L
t
t
,
AVE2H
t
AS
Address Valid to Beginning of Write
0
ns
AVWL,
t
AVBL
t
t
,
Address Valid to Chip Enable 1 Low or Chip Enable 2
High
AVE1H
t
t
60
60
ns
ns
AW
AVE2L
t
Address Valid to Write Enable High
AVWH
AW
t
BLWH
t
t
t
BLE1H
t
UB , LB Valid to End of Write
60
60
30
ns
ns
ns
BW
BW
DW
S
S
BLE2L
AVBH
t
t
t
UB , LB Low to UB , LB High
S S S S
BLBH
t
,
,
DVE1H
t
DVE2L
Input Valid to End of Write
t
DVWH
t
DVBH
t
,
E1HAX
t
t
t
,
E2LAX
t
End of Write to Address Change
Address Transition to End of Write
0
0
ns
ns
WR
WHAX
BHAX
t
,
,
E1HDZ
t
E2LDZ
t
HD
t
WHDZ
t
BHDZ
t
,
E1LE1H
t
t
Chip Enable 1 Low to End of Write
Chip Enable 2 High to End of Write
60
60
ns
ns
E1LBH
CW1
t
E1LWH
t
E2HE2L,
t
t
t
E2HBH,
E2HWH
CW2
t
t
Output Enable High to Output Hi-Z
Write Enable High to Input Transition
Write Enable Low to UB , LB High
25
25
ns
ns
ns
ns
GHQZ
GHZ
t
t
5
WHQX
DH
t
t
WP
50
WLBH
S
S
t
t
Write Enable Low to Output Hi-Z
WLQZ
WHZ
t
WLWH
t
t
Write Enable Pulse Width
50
ns
WLE1H
WP
t
WLE2L
24/27
M76DW63000A, M76DW62000A
Figure 16. SRAM Low V
Data Retention AC Waveforms, E1 or UB / LB Controlled
S S S
CCS
DATA RETENTION MODE
VCCS
VCCS (min)
VCCS (min)
tCDR
tR
E1S or
UBS, LBS
AI07918b
Table 12. SRAM Low V
Data Retention Characteristic
CCS
M76DW63000A
M76DW62000A
Symbol
Parameter
Test Condition
Unit
Min
Typ Max
Min
Typ
Max
V
CCS
= 1.5V,
E1 ≥ V
– 0.2V,
– 0.2V
S
CCS
I
Supply Current (Data Retention)
4
12
3
10
µA
CCDR
V
IN
≥ V
CCS
or V ≤ 0.2V
IN
V
Supply Voltage (Data Retention)
Chip Disable to Power Down
Operation Recovery Time
1.5
0
3.3
1.5
0
3.3
V
DR
t
ns
ns
CDR
t
70
70
R
2. Sampled only. Not 100% tested.
25/27
M76DW63000A, M76DW62000A
REVISION HISTORY
Table 13. Document Revision History
Date
Version
1.0
Revision Details
16-Apr-2003
19-May-2003
12-Jun-2003
24-Sep-2003
First Issue
1.1
M76DW63000A, 8Mbit SRAM, added
1.2
M76DW63000A, 8Mbit SRAM, corrected to 512Kx16 on first page
Voltage supply range extended 2.7V working at all speed options
1.3
26/27
M76DW63000A, M76DW62000A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
27/27
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明