M87C257-10F7 [STMICROELECTRONICS]
IC,EPROM,32KX8,CMOS,DIP,28PIN,CERAMIC;
| 型号： | M87C257-10F7 |
| 厂家： | 
ST |
| 描述： | IC,EPROM,32KX8,CMOS,DIP,28PIN,CERAMIC 可编程只读存储器 电动程控只读存储器 |
| 文件： | 总13页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M87C257
ADDRESS LATCHED
256K (32K x 8) UV EPROM and OTP EPROM
INTEGRATED ADDRESS LATCH
FAST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA
– Standby Current 100µA
28
PROGRAMMING VOLTAGE: 12.75V
1
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
FDIP28W (F)
PLCC32 (C)
PROGRAMMING TIMES of AROUND 3sec.
(PRESTO II ALGORITHM)
Figure 1. Logic Diagram
DESCRIPTION
The M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line pack-
age has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
V
CC
15
8
A0-A14
Q0-Q7
For applications where the content is programmed
only one time and erasure is not required, the
M87C257 is offered in Plastic Leaded Chip Carrier,
package.
E
M87C257
G
Table 1. Signal Names
ASV
PP
A0 - A14
Q0 - Q7
E
Address Inputs
Data Outputs
V
SS
Chip Enable
AI00928B
G
Output Enable
ASVPP
VCC
Address Strobe / Program Supply
Supply Voltage
Ground
VSS
June 1996
1/13
M87C257
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
ASV
1
2
3
4
5
6
7
8
9
28
V
CC
PP
A12
A7
A6
A5
A4
A3
A2
A1
27 A14
26 A13
25 A8
24 A9
23 A11
1 32
A6
A8
A9
A11
NC
G
A5
A4
A3
22
G
M87C257
21 A10
20
A2
A1
A0
NC
Q0
9
M87C257
25
E
A10
E
A0 10
Q0 11
Q1 12
Q2 13
19 Q7
18 Q6
17 Q5
16 Q4
15 Q3
Q7
Q6
17
V
14
SS
AI00929
AI00930
Warning: NC = Not Connected, DU = Dont’t Use.
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
TBIAS
TSTG
Temperature Under Bias
Storage Temperature
Input or Output Voltages (except A9)
Supply Voltage
(2)
VIO
VCC
–2 to 7
V
(2)
VA9
A9 Voltage
–2 to 13.5
–2 to 14
V
VPP
Program Supply Voltage
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
DEVICE OPERATION
Read Mode
The modes of operation of the M87C257 are listed
in the Operating Modes. A single power supply is
required in the read mode. Allinputs are TTLlevels
except for VPP and 12V on A9 for Electronic Signa-
ture.
The M87C257 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
2/13
M87C257
Table 3. Operating Modes
Mode
Read (Latched Address)
Read (Applied Address)
Output Disable
Program
E
VIL
G
A9
X
ASVPP
VIL
Q0 - Q7
Data Out
Data Out
Hi-Z
VIL
VIL
VIH
VIH
VIL
VIH
X
VIL
X
VIH
X
VIL
X
V
IL Pulse
X
VPP
VPP
VPP
X
Data In
Data Out
Hi-Z
Verify
VIH
X
Program Inhibit
Standby
VIH
X
VIH
X
Hi-Z
Electronic Signature
VIL
VIL
VID
VIL
Codes
Note: X = VIH or VIL, VID = 12V ± 0.5V
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
Q7
0
Q6
0
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
0
Hex Data
20h
1
0
0
0
0
0
0
0
80h
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = VIH) or latched (AS =
VIL), the address access time (tAVQV) is equal to the
delay from E to output (tELQV). Data is available at
the output after delay of tGLQV from the falling edge
of G, assuming that E has been low and the ad-
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
dresses have been stable for at least tAVQV-tGLQV
.
a. the lowest possible memory power dissipation,
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100µA (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
3/13
M87C257
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
= 30pF or 100pF
Standard
C
2.4V
L
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
output control and by properly selected decoupling
capacitors. It isrecommended thata0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between VCC and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive andinductive loadingof the deviceatthe
output. The associated transient voltage peaks can
be suppressed by complying with the two line
4/13
M87C257
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
Symbol
ILI
Parameter
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Min
Max
±10
±10
Unit
µA
Input Leakage Current
Output Leakage Current
ILO
µA
E = VIL, G = VIL,
OUT = 0mA, f = 5MHz
ICC
Supply Current
30
mA
I
E = VIH, ASVPP = VIH, Address Switching
E = VIH, ASVPP = VIL, Address Stable
10
1
mA
mA
Supply Current
(Standby) TTL
ICC1
E ≥ VCC – 0.2V, ASVPP ≥ VCC – 0.2V,
6
mA
Address Switching
Supply Current (Standby)
CMOS
ICC2
E ≥ VCC – 0.2V, ASVPP = VSS
,
100
µA
Address Stable
IPP
VIL
Program Current
VPP = VCC
100
0.8
µA
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2
(2)
VIH
VCC + 1
0.4
V
VOL
VOH
IOL = 2.1mA
IOH = –1mA
V
VCC – 0.8V
V
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M87C257
Test
Condition
-45 (3)
-60
-70
-80
Symbol
Alt
Parameter
Unit
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
tAVQV
tAVASL
tASHASL
tASLAX
tASLGL
tELQV
tACC
tAL
E = VIL, G = VIL
45
60
70
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to
Address Strobe Low
7
7
7
7
Address Strobe High
to Address Strobe Low
tLL
35
20
20
45
25
25
25
35
20
20
60
30
30
30
35
20
20
35
20
20
Address Strobe Low to
Address Transition
tLA
Address Strobe Low to
Output Enable Low
tLOE
tCE
tOE
tDF
tDF
tOH
Chip Enable Low to
Output Valid
G = VIL
E = VIL
G = VIL
E = VIL
70
35
30
30
80
40
40
40
Output Enable Low to
Output Valid
tGLQV
Chip Enable High to
Output Hi-Z
(2)
tEHQZ
0
0
0
0
0
0
0
0
0
0
0
0
Output Enable High to
Output Hi-Z
(2)
tGHQZ
Address Transition to
Output Transition
E = VIL,
G = VIL
tAXQX
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
2. Sampled only, not 100% tested.
.
3. In case of 45ns speed see High Speed AC measurement conditions.
5/13
M87C257
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M87C257
Test
Symbol
Alt
Parameter
Unit
-90
-10
-12
-15/-20
Condition
Min Max Min Max Min Max Min Max
Address Valid to
Output Valid
tAVQV
tAVASL
tASHASL
tASLAX
tASLGL
tELQV
tACC
tAL
E = VIL, G = VIL
90
100
120
150 ns
Address Valid to
Address Strobe Low
7
7
7
7
ns
ns
Address Strobe High
to Address Strobe Low
tLL
35
20
20
35
20
20
35
20
20
35
20
20
Address Strobe Low to
Address Transition
tLA
ns
Address Strobe Low
to Output Enable Low
tLOE
tCE
tOE
tDF
tDF
tOH
ns
Chip Enable Low to
Output Valid
G = VIL
E = VIL
90
40
40
40
100
40
120
50
150 ns
Output Enable Low to
Output Valid
tGLQV
60
40
40
ns
ns
ns
ns
Chip Enable High to
Output Hi-Z
(2)
tEHQZ
G = VIL
0
0
0
0
0
0
30
0
0
0
40
0
0
0
Output Enable High to
Output Hi-Z
(2)
tGHQZ
E = VIL
30
40
Address Transition to
Output Transition
tAXQX
E = VIL, G = VIL
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A14
VALID
tASLAX
tAXQX
tAVASL
ASV
PP
tASHASL
tASLGL
tAVQV
E
tGLQV
tEHQZ
G
tELQV
tGHQZ
Hi-Z
Q0-Q7
DATA OUT
AI00931
6/13
M87C257
Table 9. Programming Mode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
ILI
Parameter
Input Leakage Current
Supply Current
Test Condition
Min
Max
±10
Unit
µA
mA
mA
V
VIL ≤ VIN ≤ VIH
ICC
50
IPP
Program Current
E = VIL
50
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
–0.3
2
0.8
VIH
VCC + 0.5
0.4
V
VOL
VOH
VID
IOL = 2.1mA
IOH = –1mA
V
VCC -0.8V
11.5
V
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
Table 10. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
tAVEL
Alt
tAS
Parameter
Test Condition
Min
2
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
VPP High to Chip Enable Low
tQVEL
tDS
2
tVPHEL
tVCHEL
tELEH
tVPS
tVCS
tPW
tDH
2
VCC High to Chip Enable Low
2
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
Output Enable High to Address Transition
95
2
105
tEHQX
tQXGL
tGLQV
tGHQZ
tGHAX
tOES
tOE
tDFP
tAH
2
100
130
0
0
ns
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
Programming
change a "0" to a "1" is by die exposition to ultra-
violet light (UV EPROM). The M87C257 is in the
programming mode when VPP input is at 12.75V, G
is at VIH and E is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25 V ± 0.25 V.
When delivered (and after each erasure for UV
EPROM), all bits of the M87C257 are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
7/13
M87C257
Figure 6. Programming and Verify Modes AC Waveforms
VALID
A0-A14
tAVEL
Q0-Q7
ASV
DATA IN
tQVEL
DATA OUT
tEHQX
PP
tVPHEL
tVCHEL
tGLQV
tGHQZ
tGHAX
V
CC
E
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00557
Figure 7. Programming Flowchart
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of100µs programpulsestoeachbyteuntilacorrect
verify occurs (see Figure 7). During programming
and verify operation, a MARGIN MODE circuit is
automatically activated in order to guarantee that
each cell is programmed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides necessary margin to
each programmed cell.
V
= 6.25V, V
= 12.75V
PP
CC
n = 0
E = 100µs Pulse
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
YES
Programming of multiple M87C257s in parallel with
different data is also easily accomplished. Except
for E, all like inputs including G of the parallel
M87C257 may be common. A TTL low level pulse
appliedto aM87C257’s E input, with VPP at 12.75V,
will program that M87C257. A high level E input
inhibits the other M87C257s from being pro-
grammed.
Last
Addr
NO
FAIL
YES
CHECK ALL BYTES
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correctly
programmed. The verify is accomplished with G at
VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
AI00760B
8/13
M87C257
Electronic Signature
ERASURE OPERATION (applies for UV EPROM)
TheerasurecharacteristicsoftheM87C257issuch
that erasure begins when the cells are exposed to
light with wavelengths shorter than approximately
4000 Å. It should be noted that sunlight and some
type of fluorescent lamps have wavelengths in the
3000-4000 Årange. Research shows that constant
exposure to room level fluorescent lighting could
erase a typical M87C257 in about 3 years, while it
would take approximately 1 week to cause erasure
when exposed to direct sunlight. If the M87C257 is
to be exposed to these types of lighting conditions
for extended periods of time, it is suggested that
opaque labels be put over the M87C257 window to
prevent unintentional erasure. The recommended
erasure procedure for the M87C257 is exposure to
short wave ultraviolet light which has wavelength
2537Å. The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dos-
age is approximately 15 to 20 minutes using an
ultraviolet lamp with 12000 µW/cm2 power rating.
The M87C257 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its correspondingprogramming algorithm. The
ES mode is functional in the 25°C ± 5°C ambient
temperature range that is required when program-
ming the M87C257.
To activate the ES mode, the programming equip-
ment must force 11.5V to 12.5V on address line A9
of the M87C257, withVCC = VPP = 5V. Twoidentifier
bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH.
All other address lines must be held at VIL during
Electronic Signature mode. Byte 0 (A0=VIL) repre-
sents the manufacturer code and byte 1 (A0=VIH)
the device identifier code. When A9 = VID, ASneed
not be toggled to latch each identifier address. For
the SGS-THOMSON M87C257, these two identi-
fier bytes are given in Table 4 and can be read-out
on outputs Q0 to Q7.
9/13
M87C257
ORDERING INFORMATION SCHEME
Example:
M87C257 -70 X
C
1
X
Speed
45 ns
VCC Tolerance
Package
FDIP28W
PLCC32
Temperature Range
Option
-45 (1)
-60
-70
-80
-90
-10
-12
-15
-20
X
± 5%
F
1
6
7
3
0 to 70 °C
X
Additional
Burn-in
60 ns
70 ns
blank
± 10%
C
–40 to 85 °C
–40 to 105 °C
–40 to 125 °C
TR
Tape & Reel
Packing
80 ns
90 ns
100 ns
120 ns
150 ns
200 ns
Note: 1. High Speed, see AC Characteristics section for further information.
Fora list ofavailable options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform
catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.
10/13
M87C257
FDIP28W - 28 pin Ceramic Frit-seal DIP, with window
mm
Min
inches
Min
Symb
Typ
Max
5.71
1.78
5.08
0.55
1.42
0.31
38.10
15.80
13.36
–
Typ
Max
0.225
0.070
0.200
0.022
0.056
0.012
1.500
0.622
0.526
–
A
A1
A2
B
0.50
3.90
0.40
1.17
0.22
0.020
0.154
0.016
0.046
0.009
B1
C
D
E
15.40
13.05
–
0.606
0.514
–
E1
e1
e3
eA
L
2.54
0.100
1.300
33.02
–
–
–
–
16.17
3.18
1.52
–
18.32
4.10
2.49
–
0.637
0.125
0.060
–
0.721
0.161
0.098
–
S
7.11
0.280
α
4°
15°
4°
15°
N
28
28
FDIP28W
A2
A
A1
e1
L
B1
B
α
C
eA
e3
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale
11/13
M87C257
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
B
0.100
0.060
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.050
N
32
32
Nd
Ne
7
7
9
9
CP
0.10
0.004
PLCC32
D
D1
A1
1 N
B1
e
Ne
E1 E
D2/E2
B
Nd
A
CP
PLCC
Drawing is not to scale
12/13
M87C257
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproducts are not authorized for use as critical components in life support devices or systems withoutexpress
written approval of SGS-THOMSON Microelectronics.
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13/13
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