M93C66RDW8P/K [STMICROELECTRONICS]
EEPROM;
| 型号： | M93C66RDW8P/K |
| 厂家： | 
ST |
| 描述： | EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总32页 (文件大小：1083K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M93Cx6-DRE
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide)
MICROWIRE™ serial EEPROM 105 °C operation
Datasheet - production data
Features
• Industry standard MICROWIRE™ bus
• Memory array: 1 Kb, 2 Kb, 4 Kb, 8 Kb or 16 Kb
• Dual organization: by word (x16) or byte (x8)
• Write
SO8 (MN)
150 mil width
– Byte within 4 ms
– Word within 4 ms
• READY/BUSY signal during programming
• 2 MHz clock rate
• Sequential read operation
• Single supply voltage: 1.7 V to 5.5 V
TSSOP8 (DW)
169 mil width
• Extended temperature range: -40 °C up to 105
°C
• Enhanced ESD protection
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 900 k Write cycle at 105°C
WFDFPN8 (MF)
DFN8 - 2 x 3 mm
• Data retention
– more than 50 years at 105 °C
– 200 years at 55 °C
• Packages
– RoHS-compliant and Halogen-free
(ECOPACK2®)
Table 1. Device summary
Reference
Part number
M93C46-DRE
M93C56-DRE
M93C66-DRE
M93C76-DRE
M93C86-DRE
M93Cx6-DRE
February 2017
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1/32
This is information on a product in full production.
www.st.com
Contents
M93Cx6-DRE
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1
3.1.2
3.1.3
3.1.4
Operating supply voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 15
Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
8
9
10
11
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Contents
12
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.3 WFDFPN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13
14
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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3
List of tables
M93Cx6-DRE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Instruction set for the M93Cx6-DRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (voltage range R, temperature range 8) . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
Table 16.
Table 17.
dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18.
Table 19.
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M93Cx6-DRE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M93Cx6-DRE ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine
pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Description
M93Cx6-DRE
1
Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
The M93Cx6-DRE devices operate within a voltage supply range from 1.7 V to 5.5 V
The M93Cx6-DRE devices are guaranteed over the -40 °C/+105 °C temperature range and
are compliant with the level of reliability defined by the AEC-Q100 grade 2.
Table 2. Memory size versus organization
Device
Number of bits
Number of 8-bit bytes
Number of 16-bit words
M93C86
M93C76
M93C66
M93C56
M93C46
16384
8192
4096
2048
1024
2048
1024
512
1024
512
256
128
64
256
128
Figure 1. Logic diagram
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Table 3. Signal names
Function
Signal name
Direction
S
D
Q
C
Chip Select
Input
Input
Output
Input
Input
-
Serial Data input
Serial Data output
Serial Clock
ORG
VCC
VSS
Organization Select
Supply voltage
Ground
-
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M93Cx6-DRE
Description
The M93Cx6-DRE is accessed by a set of instructions, as summarized in Table 4, and in
more detail in Table 5: Instruction set for the M93C46 to Table 7: Instruction set for the
M93C76 and M93C86).
Table 4. Instruction set for the M93Cx6-DRE
Instruction
READ
Description
Read Data from Memory
Data
Byte or Word
WRITE
WEN
Write Data to Memory
Write Enable
Byte or Word
-
WDS
Write Disable
-
ERASE
ERAL
WRAL
Erase Byte or Word
Erase All Memory
Byte or Word
-
-
Write All Memory with same Data
A Read Data from Memory (READ) instruction loads the address of the first byte or word to
be read in an internal address register. The data at this address is then clocked out serially.
The address register is automatically incremented after the data is output and, if Chip Select
Input (S) is held High, the M93Cx6-DRE can output a sequential stream of data bytes or
words. In this way, the memory can be read as a data stream from eight to 16384 bits long
(in the case of the M93C86), or continuously (the address counter automatically rolls over to
00h when the highest address is reached).
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an Erase cycle
prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the
byte or word locations of the M93Cx6-DRE. After the start of the programming cycle, a
Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is
driven High. An internal Power-on Data Protection mechanism in the M93Cx6-DRE inhibits
the device when the supply is too low.
Figure 2. 8-pin package connections (top view)
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1. See Section 12: Package information for package dimensions, and how to identify pin-1.
2. DU = Don't Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS
.
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31
Connecting to the serial bus
M93Cx6-DRE
2
Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the t
requirement is met. The typical value of R is 100 kΩ.
SLCH
Figure 3. Bus master and memory devices on the serial bus
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M93Cx6-DRE
Operating features
3
Operating features
3.1
Supply voltage (VCC)
3.1.1
Operating supply voltage (V
)
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied. In order to secure a stable
CC
CC
DC supply voltage, it is recommended to decouple the V line with a suitable capacitor
CC
(usually of the order of 10 nF to 100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
3.1.2
3.1.3
Power-up conditions
When the power supply is turned on, V rises from V to V . During this time, the Chip
Select (S) line is not allowed to float and should be driven to V , it is therefore
recommended to connect the S line to V via a suitable pull-down resistor. The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined
CC
SS
CC
SS
SS
CC
in Table 13.
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V ), the device does not respond to any
CC
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Operating conditions, in
CC
Section 11: DC and AC parameters).
When V passes the POR threshold, the device is reset and is in the following state:
CC
•
•
Standby Power mode
deselected (assuming that there is a pull-down resistor on the S line)
As soon as the V voltage has reached a stable value within [V (min), V (max)] range,
CC
CC
CC
the device is ready for operation.
In a similar way, during power-down (continuous decrease in V ), the device must not be
CC
accessed when V drops below V (min).
CC
CC
3.1.4
Power-down
At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the
reached the internal threshold voltage.
V
CC
At power-down (continuous decrease in V ), as soon as V drops from the normal
CC
CC
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).
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Memory organization
M93Cx6-DRE
4
Memory organization
The M93Cx6-DRE memory is organized either as bytes (x8) or as words (x16). If
Organization Select (ORG) is left unconnected (or connected to V ) the x16 organization is
CC
selected; when Organization Select (ORG) is connected to Ground (V ) the x8
SS
organization is selected. When the M93Cx6-DRE is in Standby mode, Organization Select
(ORG) should be set either to V or V to reach the device minimum power consumption
SS
CC
(as any voltage between V and V applied to ORG input may increase the device
SS
CC
Standby current).
Figure 4. M93Cx6-DRE ORG input connection
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M93Cx6-DRE
Instructions
5
Instructions
The instruction set of the M93Cx6-DRE devices contains seven instructions, as summarized
in Table 5 to Table 7. Each instruction consists of the following parts, as shown in Figure 5:
READ, WRITE, WEN, WDS sequences:
•
•
•
•
Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low.
A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C).
Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code).
The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 5). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 6). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table 7).
The M93Cx6-DRE devices are fabricated in CMOS technology and are therefore able to run
as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 11: DC and AC parameters.
Table 5. Instruction set for the M93C46
x8 origination (ORG = 0)
x16 origination (ORG = 1)
Start Op-
Required
clock
Required
Address
Instruction
Description
Address
bit
code
Data
Data
clock
(1)
(1)
cycles
cycles
Read Data from
Memory
READ
1
10
A6-A0
Q7-Q0
-
A5-A0
Q15-Q0
-
Write Data to
Memory
WRITE
WEN
1
1
1
01
00
00
A6-A0
D7-D0
18
10
10
A5-A0
D15-D0
25
9
Write Enable
Write Disable
11X XXXX
-
-
11 XXXX
00 XXXX
-
-
00X
XXXX
WDS
9
Erase Byte or
Word
ERASE
ERAL
1
1
1
11
00
00
A6-A0
-
-
10
10
18
A5-A0
-
-
9
9
10X
XXXX
Erase All Memory
10 XXXX
Write All Memory
with same Data
01X
XXXX
WRAL
D7-D0
01 XXXX D15-D0
25
1. X = Don't Care bit.
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Instructions
Instruction
M93Cx6-DRE
Table 6. Instruction set for the M93C56 and M93C66
x8 origination (ORG = 0)
x16 origination (ORG = 1)
Start Op-
bit code
Required
Address
Required
Address
Description
Data
clock
Data
clock
(1) (2)
(1) (3)
cycles
cycles
Q7-
Q0
Q15-
Q0
READ
WRITE
WEN
Read Data from Memory
Write Data to Memory
Write Enable
1
1
1
10
01
00
A8-A0
A8-A0
-
A7-A0
-
D7-
D0
20
12
A7-A0 D15-D0
27
11
1 1XXX
XXXX
11XX
-
-
XXXX
0 0XXX
XXXX
00XX
-
WDS
Write Disable
1
1
1
00
11
00
-
-
-
12
12
12
11
11
11
XXXX
ERASE
ERAL
Erase Byte or Word
Erase All Memory
A8-A0
A7-A0
-
-
1 0XXX
XXXX
10XX
XXXX
Write All Memory with
same Data
0 1XXX
XXXX
D7-
D0
01XX
XXXX
WRAL
1
00
20
D15-D0
27
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 7. Instruction set for the M93C76 and M93C86
x8 Origination (ORG = 0)
x16 Origination (ORG = 1)
Start Op-
bit code
Required
clock
Required
Address
Instruction
Description
Address
Data
Data
clock
(1)(2)
(1) (3)
cycles
cycles
Read Data from
Memory
READ
WRITE
WEN
1
1
1
10
01
00
A10-A0
A10-A0
Q7-Q0
D7-D0
-
-
A9-A0 Q15-Q0
A9-A0 D15-D0
-
Write Data to
Memory
22
14
29
13
11X XXXX
XXXX
11 XXXX
-
Write Enable
XXXX
00X XXXX
XXXX
00 XXXX
-
WDS
Write Disable
1
1
1
00
11
00
-
-
-
14
14
14
13
13
13
XXXX
ERASE
ERAL
Erase Byte or Word
Erase All Memory
A10-A0
A9-A0
-
-
10X XXXX
XXXX
10 XXXX
XXXX
Write All Memory
with same Data
01X XXXX
XXXX
01 XXXX
XXXX
WRAL
1
00
D7-D0
22
D15-D0
29
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
12/32
DocID028496 Rev 2
M93Cx6-DRE
Instructions
5.1
Read Data from Memory
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6-DRE automatically increments
the internal address register and clocks out the next byte (or word) as long as the Chip
Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or
words) and a continuous stream of data can be read (the address counter automatically rolls
over to 00h when the highest address is reached).
5.2
Erase and Write data
5.2.1
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6-DRE initializes itself so that erase and write instructions are disabled.
After a Write Enable (WEN) instruction has been executed, erasing and writing remains
enabled until a Write Disable (WDS) instruction is executed, or until V falls below the
CC
power-on reset threshold voltage. To protect the memory contents from accidental
corruption, it is advisable to issue the Write Disable (WDS) instruction after every write
cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable
(WEN) or Write Disable (WDS) instructions.
5.2.2
Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
DocID028496 Rev 2
13/32
31
Instructions
M93Cx6-DRE
Figure 5. READ, WRITE, WEN, WDS sequences
2EAD
3
$
1
ꢁ ꢁ ꢀ !N
!ꢀ
1N
1ꢀ
!$$2
$!4! /54
/0
#/$%
7RITE
3
$
1
#(%#+
34!453
ꢁ ꢀ ꢁ !N
!ꢀ $N
$ꢀ
!$$2
$!4! ).
7RITE
"539
2%!$9
/0
#/$%
7RITE
%NABLE
3
$
3
$ISABLE
ꢁ ꢀ ꢀ ꢁ ꢁ 8N 8ꢀ
$
ꢁ ꢀ ꢀ ꢀ ꢀ 8N 8ꢀ
/0
/0
#/$%
#/$%
!)ꢀꢀꢄꢈꢄD
1. For the meanings of An, Xn, Qn and Dn, see Table 5, Table 6 and Table 7.
14/32
DocID028496 Rev 2
M93Cx6-DRE
Instructions
5.2.3
Write All
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.
Figure 6. WRAL sequence
72)4%
!,,
3
$
1
#(%#+
34!453
ꢁ ꢀ ꢀ ꢀ ꢁ 8N 8ꢀ $N
$ꢀ
!$$2
/0
$!4! ).
"539
2%!$9
#/$%
!)ꢀꢀꢄꢄꢀ#
1. For the meanings of Xn and Dn, please see Table 5, Table 6 and Table 7.
5.2.4
ECC (Error Correction Code) and Write cycling
The devices identified with the Process letter “K” embed an Error Correction Code (ECC)
internal logic function which is transparent for the Microwire communication protocol.
The ECC logic is implemented on each byte.
DocID028496 Rev 2
15/32
31
Instructions
M93Cx6-DRE
5.2.5
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences
%2!3%
3
$
1
#(%#+
34!453
ꢁ ꢁ ꢁ !N
!ꢀ
!$$2
"539
2%!$9
/0
#/$%
%2!3%
!,,
3
$
1
#(%#+
34!453
ꢁ ꢀ ꢀ ꢁ ꢀ 8N 8ꢀ
!$$2
/0
"539
2%!$9
#/$%
!)ꢀꢀꢄꢈꢂ"
1. For the meanings of An and Xn, please see Table 5, Table 6 and Table 7.
5.2.6
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
16/32
DocID028496 Rev 2
M93Cx6-DRE
READY/BUSY status
6
READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of t , before this status information
SLSH
becomes available). In this state, the M93Cx6-DRE ignores any data on the bus. When the
Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6-DRE is ready to receive the next instruction. Serial Data Output
(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7
8
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
Common I/O operation
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a
current limiting resistor, to form a common, single-wire data bus. Some precautions must be
taken when operating the memory in this way, mostly to prevent a short circuit current from
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output
(Q). Please see the application note AN394 for details.
DocID028496 Rev 2
17/32
31
Clock pulse counter
M93Cx6-DRE
9
Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this problem, the M93Cx6-DRE has an on-chip counter that counts the clock
pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of
clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL
instruction is aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6-DRE family, are summarized in Table 5: Instruction set for the M93C46 to Table 7:
Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 8. Write sequence with one clock glitch
3
#
$
!N
!Nꢊꢁ
'LITCH
!Nꢊꢃ
34!24
ꢋꢀꢋ
ꢋꢁꢋ
$ꢀ
!$$2%33 !.$ $!4!
!2% 3()&4%$ "9 /.% ")4
72)4%
!)ꢀꢁꢅꢂꢉ
18/32
DocID028496 Rev 2
M93Cx6-DRE
Maximum ratings
10
Maximum ratings
Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 8. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD Lead temperature during soldering
See note (1)
VOUT
VIN
Output range (Q = VOH or Hi-Z)
Input range
–0.50
–0.50
–0.50
-
VCC+0.5
VCC+1
6.5
V
VCC
VESD
Supply voltage
V
Electrostatic discharge voltage (human body model)(2)
4000
V
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
DocID028496 Rev 2
19/32
31
DC and AC parameters
M93Cx6-DRE
11
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 9. Operating conditions (voltage range R, temperature range 8)
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.7
5.5
V
- 40
105
°C
Table 10. AC measurement conditions
Symbol
Parameter
Min.
Max.
Unit
CL
Load capacitance
100
pF
ns
V
-
-
-
-
Input rise and fall times
-
50
Input voltage levels
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
0.3 VCC to 0.7 VCC
Input timing reference voltages
Output timing reference voltages
V
V
Figure 9. AC testing input output waveforms
-ꢂꢅ#88
ꢄꢇꢆ9
&&
&&
ꢄꢇꢉ9
ꢄꢇꢀ9
&&
&&
)NPUT AND OUTPUT
TIMING REFERENCE LEVELS
)NPUT VOLTAGE LEVELS
ꢄꢇꢈ9
-3ꢁꢂꢈꢄꢄ6ꢅ
Table 11. Input and output capacitance
Symbol
Parameter
Test condition(1)
Min
Max
Unit
COUT
CIN
Output capacitance
Input capacitance
VOUT = 0V
VIN = 0V
-
-
8
6
pF
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.
Table 12. Cycling performance by byte
Symbol
Parameter
Test condition
Min.
Max.
Unit
TA ≤ 25 °C, 1.7 V < VCC < 5.5 V
TA = 85 °C, 1.7 V < VCC < 5.5 V
TA = 105 °C, 1.7 V < VCC < 5.5 V
-
-
-
4,000,000
1,200,000
900,000
Write cycle
endurance
Write
Ncycle
cycle(1)
1. A Write cycle is executed when either a Write, a Write All, an Erase or an Erase All instruction is decoded.
20/32
DocID028496 Rev 2
M93Cx6-DRE
Symbol
DC and AC parameters
Table 13. DC characteristics
Test conditions
(in addition to conditions specified
in Table 9)
Parameter
Min.
Max.
Unit
ILI
Input leakage current
Output leakage current
VIN = VSS or VCC
-
-
2
2
µA
ILO
S = VCC, VOUT = VSS or VCC
VCC = 1.7 V, C = 0.1 VCC/0.9 VCC
Q = open, fC = 2 MHz
,
,
-
-
-
1
1
V
CC = 2.5 V, C = 0.1 VCC/0.9 VCC
ICC
Supply current (Read)
Supply current (Write)
mA
mA
Q = open, fC = 2 MHz
VCC = 5.5 V, fC = 2 MHz
1.5
C = 0.1 VCC/0.9 VCC, Q = open
1.7 V ≤ VCC < 5.5 V during tW,
S = VCC
(1)
ICC0
-
-
-
-
-
-
-
1.5
1
t° = 25 °C, VCC = 1.7V,
S = VCC, VIN = VSS or VCC
t° = 25 °C, VCC = 2.5 V,
S = VCC, VIN = VSS or VCC
2
t° = 25 °C, VCC = 5.5 V,
S = VCC, VIN = VSS or VCC
3
ICC1
Supply current (Standby mode)
µA
t° = 105 °C, VCC = 1.7V,
S = VCC, VIN = VSS or VCC
1
t° = 105 °C, VCC = 2.5 V,
S = VCC, VIN = VSS or VCC
2
t° = 105 °C, VCC = 5.5 V,
S = VCC, VIN = VSS or VCC
3
1.7V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
1.7V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
–0.45
–0.45
0.75 VCC
0.7 VCC
-
0.25 VCC
0.3 VCC
VCC+1
VCC+1
0.3
VIL
VIH
VOL
Input low voltage (D, C, S)
Input high voltage (D, C, S)
Output low voltage
V
V
V
VCC = 1.7 V, IOL = 1 mA
VCC ≥ 2.5 V, IOL = 2.1 mA
VCC = 1.7 V, IOH = 1 mA
VCC ≥ 2.5 V, IOH = -2.1 mA
-
-
0.4
0.8 VCC
0.8 VCC
0.5
-
VOH
Output high voltage
V
V
-
VRES
Internal reset threshold voltage
1.5
1. Average value during the Write cycle (tW)
DocID028496 Rev 2
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31
DC and AC parameters
M93Cx6-DRE
Table 14. AC characteristics
Test conditions specified in Table 9 and Table 10
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSK
Clock frequency
D.C.
50
50
200
200
200
50
50
50
0
2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
Chip Select low to Clock high
Chip Select set-up time
-
tCSS
tCS
-
(1)
tSLSH
Chip Select low to Chip Select high
Clock high time
-
(2)
tCHCL
tSKH
tSKL
tDIS
tDIH
tSKS
tCSH
tSV
-
-
(2)
tCLCH
Clock low time
tDVCH
tCHDX
tCLSH
tCLSL
tSHQV
Data in set-up time
-
Data in hold time
-
Clock set-up time (relative to S)
Chip Select hold time
-
-
Chip Select to READY/BUSY status
Chip Select low to output Hi-Z (VCC>2.5 V)
Chip Select low to output Hi-Z (VCC<2.5 V)
Delay to output low
-
200
100
200
200
200
4
-
(3)
tSLQZ
tDF
-
tCHQL
tCHQV
tW
tPD0
tPD1
tWP
-
Delay to output valid
-
Erase or Write cycle time
-
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.
2. tCHCL + tCLCH ≥ 1 / fC.
3. Value defined from characterization, not tested in production.
22/32
DocID028496 Rev 2
M93Cx6-DRE
DC and AC parameters
Figure 10. Synchronous timing (Start and op-code input)
W&/6+
W&+&/
#
3
$
W6+&+
W&/&+
W'9&+
67$57
W&+';
23ꢅ&2'(
23ꢅ&2'(
67$57
23ꢅ&2'(ꢅ,1387
AIꢀꢁꢇꢃꢄ
Figure 11. Synchronous timing (Read)
&
6
'
4
W&/6/
W'9&+
W&+';
W&+49
W6/6+
$ꢄ
$Q
W6/4=
W&+4/
+Lꢊ=
4ꢁꢋꢌ4ꢉ
4ꢄ
$''5(66ꢅ,1387
'$7$ꢅ287387
$,ꢄꢄꢆꢈꢄ&
Figure 12. Synchronous timing (Write)
W6/&+
#
3
$
1
W&/6/
W'9&+
W&+';
$ꢄꢌ'ꢄ
W6/6+
$Q
W6+49
%86<
W6/4=
5($'<
+Lꢊ=
W:
$''5(66ꢌ'$7$ꢅ,1387
:5,7(ꢅ&<&/(
AIꢀꢁꢇꢃꢂ
DocID028496 Rev 2
23/32
31
Package information
M93Cx6-DRE
12
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
12.1
SO8N package information
Figure 13. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width,
package outline
H X ꢂꢃ
!ꢄ
!
C
CCC
B
E
ꢀꢁꢂꢃꢄPP
*$8*(ꢄ3/$1(
$
K
ꢁ
%ꢀ
%
,
ꢀ
!ꢀ
,ꢀ
62ꢊ$B9ꢈ
1. Drawing is not to scale.
Table 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.750
0.250
-
-
-
0.0689
0.0098
-
0.100
1.250
0.280
0.170
4.800
5.800
3.800
-
-
0.0039
0.0492
0.0110
0.0067
0.1890
0.2283
0.1496
-
-
-
-
-
0.480
0.230
5.000
6.200
4.000
-
-
0.0189
0.0091
0.1969
0.2441
0.1575
-
c
-
4.900
6.000
3.900
1.270
-
-
D
E
0.1929
0.2362
E1
e
0.1535
0.0500
h
0.250
0°
0.500
8°
0.0098
0°
-
-
-
0.0197
8°
k
-
L
0.400
-
1.270
0.0157
0.0500
24/32
DocID028496 Rev 2
M93Cx6-DRE
Package information
Table 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data (continued)
millimeters
inches(1)
Typ.
Symbol
Min.
Typ.
Max.
Min.
Max.
L1
-
-
1.040
-
-
-
-
0.0409
-
-
ccc
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint
ꢄꢇꢂꢅꢍ[ꢆꢎ
ꢁꢇꢈꢉ
2ꢉB62ꢆ1B)3B9ꢁ
1. Dimensions are expressed in millimeters.
DocID028496 Rev 2
25/32
31
Package information
M93Cx6-DRE
12.2
TSSOP8 package information
Figure 15.TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline
ꢂ
ϴ
ϱ
Đ
ꢁϭ
ꢁ
ϭ
ϰ
ɲ
>
ꢃϭ
ꢃϮ
ꢃ
>ϭ
ꢀW
ď
Ğ
76623ꢆ$0B9ꢈ
1. Drawing is not to scale.
Table 16. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
0.100
3.100
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
-
0.050
0.800
0.190
0.090
-
-
0.0020
0.0315
0.0075
0.0035
-
-
1.000
-
0.0394
-
c
-
-
CP
D
-
-
2.900
-
3.000
0.650
6.400
4.400
0.600
1.000
-
0.1142
-
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
-
e
E
6.200
4.300
0.450
-
6.600
4.500
0.750
-
0.2441
0.1693
0.0177
-
0.2598
0.1772
0.0295
-
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
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DocID028496 Rev 2
M93Cx6-DRE
Package information
12.3
WFDFPN8 package information
Figure 16. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine
pitch dual flat package outline
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-
-
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1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating
(not connected) in the end application.
DocID028496 Rev 2
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31
Package information
M93Cx6-DRE
Table 17. WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch
dual flat package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
b
0.700
0.025
0.200
1.900
2.900
-
0.750
0.800
0.065
0.300
2.100
3.100
-
0.0276
0.0010
0.0079
0.0748
0.1142
-
0.0295
0.0315
0.0026
0.0118
0.0827
0.1220
-
0.045
0.0018
0.250
0.0098
D
2.000
0.0787
E
3.000
0.1181
e
0.500
0.0197
L1
-
-
-
-
-
-
-
0.150
-
-
-
-
-
-
-
-
0.0059
-
L3
0.300
1.050
1.050
0.400
0.300
0.0118
0.0413
0.0413
0.0157
0.0118
D2
E2
K
1.650
1.450
-
0.0650
0.0571
-
L
0.500
0.0197
NX(2)
ND(3)
aaa
bbb
ccc
ddd
eee(4)
8
4
-
-
-
-
-
-
-
-
-
-
0.150
0.100
0.100
0.050
0.080
-
-
-
-
-
-
-
-
-
-
0.0059
0.0039
0.0039
0.0020
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. NX is the number of terminals.
3. ND is the number of terminals on “D” sides.
4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
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M93Cx6-DRE
Part numbering
13
Part numbering
Table 18. Ordering information scheme
Example:
M93C 86
R
MN
8
T
P
/K
Device type
M93 = MICROWIRE serial EEPROM
Device function
86 = 16 Kbit (2048 x 8)
76 = 8 Kbit (1024 x 8)
66 = 4 Kbit (512 x 8)
56 = 2 Kbit (256 x 8)
46 = 1 Kbit (128 x 8)
Operating voltage
R = VCC = 1.7 to 5.5 V
Package(1)
MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MF = WFDFPN8 (2 x 3 mm)
Device grade
8 = - 40 to 105 °C
Packing
T = tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK2®
Process
/K = Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony-oxide
flame retardants).
DocID028496 Rev 2
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31
Part numbering
M93Cx6-DRE
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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DocID028496 Rev 2
M93Cx6-DRE
Revision history
14
Revision history
Table 19. Document revision history
Changes
Date
Revision
09-Nov-2015
1
Initial release.
Updated:
– Features
– Section 1: Description
– Section 3.1.4: Power-down
23-Feb-2017
2
– Table 9: Operating conditions (voltage range R, temperature range 8)
– Table 12: Cycling performance by byte
– Table 13: DC characteristics
– Table 18: Ordering information scheme
DocID028496 Rev 2
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31
M93Cx6-DRE
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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