M93S46-WMN3P/W [STMICROELECTRONICS]
IC,SERIAL EEPROM,64X16,CMOS,SOP,8PIN,PLASTIC;
| 型号： | M93S46-WMN3P/W |
| 厂家： | 
ST |
| 描述： | IC,SERIAL EEPROM,64X16,CMOS,SOP,8PIN,PLASTIC 存储 内存集成电路 光电二极管 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 |
| 文件： | 总34页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M93S66, M93S56
M93S46
4Kbit, 2Kbit and 1Kbit (16-bit wide)
MICROWIRE Serial Access EEPROM with Block Protection
FEATURES SUMMARY
■
Industry Standard MICROWIRE Bus
Figure 1. Packages
■
Single Supply Voltage:
–
–
–
4.5 to 5.5V for M93Sx6
2.5 to 5.5V for M93Sx6-W
1.8 to 5.5V for M93Sx6-R
8
■
■
Single Organization: by Word (x16)
Programming Instructions that work on: Word
or Entire Memory
1
■
Self-timed Programming Cycle with Auto-
Erase
PDIP8 (BN)
■
■
■
■
User Defined Write Protected Area
Page Write Mode (4 words)
Ready/Busy Signal During Programming
Speed:
8
–
1MHz Clock Rate, 10ms Write Time
(Current product, identified by process
identification letter F or M)
1
SO8 (MN)
150 mil width
–
2MHz Clock Rate, 5ms Write Time (New
Product, identified by process
identification letter W or G)
■
■
■
■
Sequential Read Operation
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
TSSOP8 (DS)
3x3mm body size
TSSOP8 (DW)
169 mil width
April 2004
1/34
M93S66, M93S56, M93S46
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17
2/34
M93S66, M93S56, M93S46
Figure 9. AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10.Synchronous Timing (Start and Op-Code Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 28
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 28
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
29
Figure 15.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
30
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
30
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
M93S66, M93S56, M93S46
SUMMARY DESCRIPTION
This specification covers a range of 4K, 2K, 1K bit
serial Electrically Erasable Programmable Memo-
ry (EEPROM) products (respectively for M93S66,
M93S56, M93S46). In this text, these products are
collectively referred to as M93Sx6.
and instructions used to set the memory protec-
tion. These are summarized in Table 2. and Table
3.).
A Read Data from Memory (READ) instruction
loads the address of the first word to be read into
an internal address pointer. The data contained at
this address is then clocked out serially. The ad-
dress pointer is automatically incremented after
the data is output and, if the Chip Select Input (S)
is held High, the M93Sx6 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream from 16 to 4096 bits (for
the M93S66), or continuously as the address
counter automatically rolls over to 00h when the
highest address is reached.
Figure 2. Logic Diagram
V
CC
D
C
Within the time required by a programming cycle
(t ), up to 4 words may be written with help of the
W
Q
Page Write instruction. the whole memory may
also be erased, or set to a predetermined pattern,
by using the Write All instruction.
M93Sx6
S
PRE
W
Within the memory, a user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a Pro-
tection Register, located outside of the memory ar-
ray. As a final protection step, data may be
permanently protected by programming a One
Time Programming bit (OTP bit) which locks the
Protection Register content.
V
SS
AI02020
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an erase cycle prior to the Write
instruction. The Write instruction writes 16 bits at a
time into one of the word locations of the M93Sx6,
the Page Write instruction writes up to 4 words of
16 bits to sequential locations, assuming in both
cases that all addresses are outside the Write Pro-
tected area. After the start of the programming cy-
cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
en High.
Table 1. Signal Names
S
Chip Select Input
D
Serial Data Input
Serial Data Output
Serial Clock
Q
C
PRE
W
Protection Register Enable
Write Enable
Figure 3. DIP, SO and TSSOP Connections
V
Supply Voltage
Ground
M93Sx6
CC
S
C
D
Q
1
2
3
4
8
V
CC
PRE
V
SS
7
6
The M93Sx6 is accessed through a serial input (D)
and output (Q) using the MICROWIRE bus proto-
col. The memory is divided into 256, 128, 64 x16
bit words (respectively for M93S66, M93S56,
M93S46).
W
5
V
SS
AI02021
The M93Sx6 is accessed by a set of instructions
which includes Read, Write, Page Write, Write All
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
4/34
M93S66, M93S56, M93S46
An internal Power-on Data Protection mechanism
in the M93Sx6 inhibits the device when the supply
is too low.
INSTRUCTIONS
The instruction set of the M93Sx6 devices con-
tains seven instructions, as summarized in Table
2. to Table 3.. Each instruction consists of the fol-
lowing parts, as shown in Figure 4.:
■
■
■
Each instruction is preceded by a rising edge
on Chip Select Input (S) with Serial Clock (C)
being held Low.
A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C).
Two op-code bits, read on Serial Data Input
(D) during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code).
POWER-ON DATA PROTECTION
To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode.
–
At Power-up and Power-down, the device
must not be selected (that is, Chip Select Input
(S) must be driven Low) until the supply
voltage reaches the operating value V
specified in Table 5. to Table 6..
CC
■
The address bits of the byte or word that is to
be accessed. For the M93S46, the address is
made up of 6 bits (see Table 2.). For the
M93S56 and M93S66, the address is made up
of 8 bits (see Table 3.).
–
When V reaches its valid level, the device is
CC
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming
instructions.
The M93Sx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in Table 16. to Table 19..
For the M93Sx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Sx6-
W (3V range) and M93Sx6-R (2V range) the POR
threshold voltage is around 1.5V.
5/34
M93S66, M93S56, M93S46
Table 2. Instruction Set for the M93S46
Required
Clock
Cycles
Start Op-
Additional
Comments
1
Instruction
Description
W
PRE
Data
Address
bit
Code
Read Data
from Memory
READ
X
0
1
10
A5-A0
Q15-Q0
Write is executed if
the address is not
inside the Protected
area
Write Data to
Memory
WRITE
PAWRITE
WRAL
1
1
1
0
0
0
1
1
1
01
11
00
A5-A0
A5-A0
D15-D0
25
9 + N x 16
25
Write is executed if
all the N addresses
are not inside the
Protected area
Page Write to
Memory
N x
D15-D0
Write All
Memory
with same
Data
Write all data if the
Protection Register
is cleared
01 XXXX
D15-D0
WEN
WDS
Write Enable
Write Disable
1
0
0
1
1
00
00
11 XXXX
00 XXXX
9
9
X
Data Output =
Protection Register
content + Protection
Flag bit
Protection
Register Read
Q5-Q0
+ Flag
PRREAD
X
1
1
10
XXXXXX
Data above specified
address A5-A0 are
protected
Protection
Register Write
PRWRITE
PRCLEAR
PREN
1
1
1
1
1
1
1
1
1
1
1
1
01
11
00
00
A5-A0
111111
11XXXX
000000
9
9
9
9
Protect Flag is also
cleared (cleared
Flag = 1)
Protection
Register Clear
Protection
Register
Enable
Protection
Register
Disable
OTP bit is set
permanently
PRDS
Note: 1. X = Don’t Care bit.
6/34
M93S66, M93S56, M93S46
Table 3. Instruction Set for the M93S66, M93S56
Start Op-
Required
Additional
Clock
1,2
Instruction
Description
W
PRE
Data
Address
bit
Code
Comments
Cycles
Read Data
from Memory
READ
X
0
1
10
A7-A0
Q15-Q0
Write is executed if
Write Data to
Memory
the address is not
inside the
Protected area
WRITE
PAWRITE
WRAL
1
1
1
0
0
0
1
1
1
01
11
00
A7-A0
A7-A0
D15-D0
27
Write is executed if
all the N
11 + N x 16 addresses are not
Page Write to
Memory
N x
D15-D0
inside the
Protected area
Write All
Memory
with same
Data
Write all data if the
Protection
Register is cleared
01XXXXXX D15-D0
27
WEN
WDS
Write Enable
Write Disable
1
0
0
1
1
00
00
11XXXXXX
00XXXXXX
11
11
X
Data Output =
Protection
Register content +
Protection
Register Read
Q7-Q0
XXXXXXXX
PRREAD
PRWRITE
X
1
1
1
1
1
10
01
+ Flag
Protection Flag bit
Data above
specified address
A7-A0 are
Protection
Register Write
A7-A0
11
protected
Protect Flag is also
cleared (cleared
Flag = 1)
Protection
Register Clear
PRCLEAR
PREN
1
1
1
1
1
1
1
1
1
11
00
00
11111111
11XXXXXX
00000000
11
11
11
Protection
Register
Enable
Protection
Register
Disable
OTP bit is set
permanently
PRDS
Note: 1. X = Don’t Care bit.
2. Address bit A7 is not decoded by the M93S56.
7/34
M93S66, M93S56, M93S46
Figure 4. READ, WRITE, WEN and WDS Sequences
READ
PRE
S
D
1 1 0 An
A0
Q
Qn
Q0
ADDR
DATA OUT
OP
CODE
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ENABLE
PRE
W
WRITE
DISABLE
PRE
S
S
D
1 0 0 0 0 Xn X0
D
1 0 0 1 1 Xn X0
OP
CODE
OP
CODE
AI00889D
Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3..
8/34
M93S66, M93S56, M93S46
Read
Write
The Read Data from Memory (READ) instruction
outputs serial data on Serial Data Output (Q).
When the instruction is received, the op-code and
address are decoded, and the data from the mem-
ory is transferred to an output shift register. A dum-
my 0 bit is output first, followed by the 16-bit word,
with the most significant bit first. Output data
changes are triggered by the rising edge of Serial
Clock (C). The M93Sx6 automatically increments
the internal address register and clocks out the
next byte (or word) as long as the Chip Select In-
put (S) is held High. In this case, the dummy 0 bit
is not output between bytes (or words) and a con-
tinuous stream of data can be read.
The Write Data to Memory (WRITE) instruction is
composed of the Start bit plus the op-code fol-
lowed by the address and the 16 data bits to be
written.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the
future execution of write instructions, and the Write
Disable (WDS) instruction disables it. When power
is first applied, the M93Sx6 initializes itself so that
write instructions are disabled. After an Write En-
able (WEN) instruction has been executed, writing
remains enabled until an Write Disable (WDS) in-
While the M93Sx6 is performing a write cycle, but
after a delay (t
) before the status information
SLSH
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
struction is executed, or until V
falls below the
CC
power-on reset threshold voltage. To protect the
memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) in-
struction after every write cycle. The Read Data
from Memory (READ) instruction is not affected by
the Write Enable (WEN) or Write Disable (WDS)
instructions.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
9/34
M93S66, M93S56, M93S46
Figure 5. PAWRITE and WRAL Sequence
PAGE
WRITE
PRE
W
S
CHECK
STATUS
D
1 1 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ALL
PRE
W
S
CHECK
STATUS
D
1 0 0 0 1 Xn X0 Dn
D0
Q
ADDR
OP
DATA IN
BUSY
READY
CODE
AI00890C
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
Page Write
The Page Write to Memory (PAWRITE) instruction
will not be executed if any of the 4 words address-
es the protected area.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
A Page Write to Memory (PAWRITE) instruction
contains the first address to be written, followed by
up to 4 data words.
After the receipt of each data word, bits A1-A0 of
the internal address register are incremented, the
high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users
must take care, in the software, to ensure that the
last word address has the same upper order ad-
dress bits as the initial address transmitted to
avoid address roll-over.
10/34
M93S66, M93S56, M93S46
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
after a delay (t
) before the status information
SLSH
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
) before the status information
SLSH
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
Write All
The Write All Memory with same Data (WRAL) in-
struction is valid only after the Protection Register
has been cleared by executing a Protection Reg-
ister Clear (PRCLEAR) instruction. The Write All
Memory with same Data (WRAL) instruction simul-
taneously writes the whole memory with the same
data word given in the instruction.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
11/34
M93S66, M93S56, M93S46
Figure 6. PREAD, PRWRITE and PREN Sequences
Protect
Register
READ
PRE
S
D
1 1 0 Xn
X0
Q
An
A0 F
ADDR
DATA
OUT
F = Protect Flag
OP
CODE
Protect
Register
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP
CODE
AI00891D
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
12/34
M93S66, M93S56, M93S46
Figure 7. PRCLEAR and PRDS Sequences
Protect
Register
CLEAR
PRE
W
S
CHECK
STATUS
D
1 1 1
1 1 1
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
DISABLE
PRE
W
S
CHECK
STATUS
D
1 0 0
0 0 0
Q
ADDR
BUSY
READY
OP
CODE
AI00892C
Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3..
13/34
M93S66, M93S56, M93S46
WRITE PROTECTION AND THE PROTECTION REGISTER
The Protection Register on the M93Sx6 is used to
adjust the amount of memory that is to be write
protected. The write protected area extends from
the address given in the Protection Register, up to
the top address in the M93Sx6 device.
Two flag bits are used to indicate the Protection
Register status:
able (PREN) instruction does not modify the Pro-
tection Flag bit value.
Note: A Write Enable (WEN) instruction must be
executed before the Protection Register Enable
(PREN) instruction. Both the Protection Enable
(PRE) and Write Enable (W) signals must be driv-
en High during the instruction execution.
–
Protection Flag: this is used to enable/disable
protection of the write-protected area of the
M93Sx6 memory
OTP bit: when set, this disables access to the
Protection Register, and thus prevents any
further modifications to the value in the
Protection Register.
Protection Register Clear
The Protection Register Clear (PRCLEAR) in-
struction clears the address stored in the Protec-
tion Register to all 1s, so that none of the memory
is write-protected by the Protection Register. How-
ever, it should be noted that all the memory re-
mains protected, in the normal way, using the
Write Enable (WEN) and Write Disable (WDS) in-
structions.
The Protection Register Clear (PRCLEAR) in-
struction clears the Protection Flag to 1. Both the
Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution.
–
The lower-bound memory address is written to the
Protection Register using the Protection Register
Write (PRWRITE) instruction. It can be read using
the Protection Register Read (PRREAD) instruc-
tion.
The Protection Register Enable (PREN) instruc-
tion must be executed before any PRCLEAR,
PRWRITE or PRDS instruction, and with appropri-
ate levels applied to the Protection Enable (PRE)
and Write Enable (W) signals.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Clear (PRCLEAR) instruction.
Write-access to the Protection Register is
achieved by executing the following sequence:
Protection Register Write
The Protection Register Write (PRWRITE) instruc-
tion is used to write an address into the Protection
Register. This is the address of the first word to be
protected. After the Protection Register Write
(PRWRITE) instruction has been executed, all
memory locations equal to and above the speci-
fied address are protected from writing.
The Protection Flag bit is set to 0, and can be read
with Protection Register Read (PRREAD) instruc-
tion. Both the Protection Enable (PRE) and Write
Enable (W) signals must be driven High during the
instruction execution.
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Write (PRWRITE) instruction, but it is not
necessary to execute first a Protection Register
Clear (PRCLEAR).
–
–
Execute the Write Enable (WEN) instruction
Execute the Protection Register Enable
(PREN) instruction
–
Execute one PRWRITE, PRCLEAR or PRDS
instructions, to set a new boundary address in
the Protection Register, to clear the protection
address (to all 1s), or permanently to freeze
the value held in the Protection Register.
Protection Register Read
The Protection Register Read (PRREAD) instruc-
tion outputs, on Serial Data Output (Q), the con-
tent of the Protection Register, followed by the
Protection Flag bit. The Protection Enable (PRE)
signal must be driven High before and during the
instruction.
As with the Read Data from Memory (READ) in-
struction, a dummy 0 bit is output first. Since it is
not possible to distinguish between the Protection
Register being cleared (all 1s) or having been writ-
ten with all 1s, the user must check the Protection
Flag status (and not the Protection Register con-
tent) to ascertain the setting of the memory protec-
tion.
Protection Register Disable
The Protection Register Disable (PRDS) instruc-
tion sets the One Time Programmable (OTP) bit.
This instruction is a ONE TIME ONLY instruction
which latches the Protection Register content, this
content is therefore unalterable in the future. Both
the Protection Enable (PRE) and Write Enable (W)
signals must be driven High during the instruction
execution. The OTP bit cannot be directly read, it
can be checked by reading the content of the Pro-
tection Register, using the Protection Register
Read (PRREAD) instruction, then by writing this
same value back into the Protection Register, us-
Protection Register Enable
The Protection Register Enable (PREN) instruc-
tion is used to authorize the use of instructions that
modify the Protection Register (PRWRITE,
PRCLEAR, PRDS). The Protection Register En-
14/34
M93S66, M93S56, M93S46
ing the Protection Register Write (PRWRITE) in-
struction. When the OTP bit is set, the Ready/Busy
status cannot appear on Serial Data Output (Q).
When the OTP bit is not set, the Busy status ap-
pears on Serial Data Output (Q).
Note: A Protection Register Enable (PREN) in-
struction must immediately precede the Protection
Register Disable (PRDS) instruction.
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
Figure 8. Write Sequence with One Clock Glitch
S
C
D
An
An-1
Glitch
An-2
START
"0"
"1"
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
WRITE
AI01395
aborted, and the contents of the memory are not
modified.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the Bus Master (the micro-
controller). This can lead to a misalignment of the
instruction of one or more bits (as shown in Figure
8.) and may lead to the writing of erroneous data
at an erroneous address.
To combat this problem, the M93Sx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, PAWRITE,
WRALL, PRWRITE or PRCLEAR instruction is
The number of clock cycles expected for each in-
struction, and for each member of the M93Sx6
family, are summarized in Table 2. to Table 3.. For
example, a Write Data to Memory (WRITE) in-
struction on the M93S56 (or M93S66) expects 27
clock cycles from the start bit to the falling edge of
Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
15/34
M93S66, M93S56, M93S46
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
T
Storage Temperature
–65
150
STG
1
TLEAD
VOUT
VIN
Lead Temperature during Soldering
See note
Output range (Q = V or Hi-Z)
–0.50
–0.50
–0.50
–4000
VCC+0.5
VCC+1
6.5
OH
Input range
V
V
Supply Voltage
V
CC
2
VESD
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
16/34
M93S66, M93S56, M93S46
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M93Sx6)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 6. Operating Conditions (M93Sx6-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
TA
–40
85
°C
Table 7. Operating Conditions (M93Sx6-R)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
TA
–40
85
°C
Table 8. AC Measurement Conditions (M93Sx6)
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
50
Input Pulse Voltages
0.4 V to 2.4 V
1.0 V and 2.0 V
0.8 V and 2.0 V
Input Timing Reference Voltages
Output Timing Reference Voltages
V
V
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R)
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
50
CC
CC
CC
0.2V to 0.8V
Input Pulse Voltages
CC
0.3V to 0.7V
Input Timing Reference Voltages
Output Timing Reference Voltages
V
CC
0.3V to 0.7V
V
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
17/34
M93S66, M93S56, M93S46
Figure 9. AC Testing Input Output Waveforms
M93SXX
2.4V
2V
2.0V
0.8V
1V
0.4V
INPUT
OUTPUT
M93SXX-W & M93SXX-R
0.8V
0.2V
CC
0.7V
0.3V
CC
CC
CC
AI02791
Table 10. Capacitance
Symbol
Parameter
Test Condition
Min
Max
Unit
COUT
Output
Capacitance
5
pF
V
OUT
= 0V
CIN
Input
Capacitance
5
pF
V
= 0V
IN
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 1 MHz.
A
18/34
M93S66, M93S56, M93S46
Table 11. DC Characteristics (M93Sx6, Device Grade 6)
Symbol
ILI
Parameter
Test Condition
Min.
Max.
±2.5
±2.5
Unit
µA
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
IN
CC
0V ≤ V
≤ V , Q in Hi-Z
CC
ILO
µA
OUT
V
= 5V, S = V , f = 1 MHz, Current
CC
IH
1.5
2
mA
mA
µA
1
Product
ICC
Supply Current
V
= 5V, S = V , f = 2 MHz, New
CC
IH
2
Product
V
= 5V, S = V , C = V
,
SS
CC
CC
SS
50
1
Current Product
ICC1
Supply Current (Stand-by)
V
= 5V, S = V , C = V
,
SS
SS
15
µA
2
New Product
V
V
= 5V ± 10%
= 5V ± 10%
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
2
0.8
V
V
V
V
CC
CC
V
+ 1
CC
V
V
= 5V, I = 2.1mA
OL
VOL
VOH
0.4
CC
= 5V, I
= –400µA
2.4
CC
OH
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.
Table 12. DC Characteristics (M93Sx6, Device Grade 3)
Symbol
ILI
Parameter
Test Condition
0V ≤ V ≤ V
Min.
Max.
±2.5
±2.5
Unit
µA
Input Leakage Current
Output Leakage Current
IN
CC
0V ≤ V
≤ V , Q in Hi-Z
CC
ILO
µA
OUT
V
= 5V, S = V , f = 1 MHz, Current
CC
IH
1.5
2
mA
mA
µA
1
Product
ICC
Supply Current
V
= 5V, S = V , f = 2 MHz, New
CC
IH
2
Product
V
= 5V, S = V , C = V
,
SS
CC
CC
SS
50
1
Current Product
ICC1
Supply Current (Stand-by)
V
= 5V, S = V , C = V
,
SS
SS
15
µA
2
New Product
V
V
= 5V ± 10%
= 5V ± 10%
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.45
2
0.8
V
V
V
V
CC
CC
V
+ 1
CC
V
V
= 5V, I = 2.1mA
OL
VOL
VOH
0.4
CC
= 5V, I
= –400µA
2.4
CC
OH
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.
19/34
M93S66, M93S56, M93S46
Table 13. DC Characteristics (M93Sx6-W, Device Grade 6)
Symbol
ILI
Parameter
Test Condition
Min.
Max.
±2.5
±2.5
Unit
µA
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
IN
CC
0V ≤ V
≤ V , Q in Hi-Z
CC
ILO
µA
OUT
V
= 5V, S = V , f = 1 MHz, Current
CC
IH
1.5
1
mA
mA
mA
mA
µA
1
Product
V
= 2.5V, S = V , f = 1 MHz, Current
CC
IH
1
Product
Supply Current (CMOS
Inputs)
ICC
V
= 5V, S = V , f = 2 MHz, New
CC
IH
2
2
Product
V
= 2.5V, S = V , f = 2 MHz, New
CC
IH
1
2
Product
V
CC
= 2.5V, S = V , C = V
,
SS
SS
10
1
Current Product
ICC1
Supply Current (Stand-by)
V
CC
= 2.5V, S = V , C = V
,
SS
SS
5
µA
2
New Product
0.2 V
VIL
VIH
Input Low Voltage (D, C, S)
Input High Voltage (D, C, S)
–0.45
0.7 V
V
V
V
V
V
V
CC
V
CC
+ 1
CC
V
= 5V, I = 2.1mA
OL
0.4
0.2
CC
VOL
Output Low Voltage (Q)
Output High Voltage (Q)
V
V
= 2.5V, I = 100µA
OL
CC
= 5V, I
= –400µA
2.4
–0.2
CC
OH
VOH
V
= 2.5V, I
= –100µA
V
CC
OH
CC
Note: 1. Current product: identified by Process Identification letter F or M.
2. New product: identified by Process Identification letter W or G.
20/34
M93S66, M93S56, M93S46
Table 14. DC Characteristics (M93Sx6-W, Device Grade 3)
1
1
Symbol
ILI
Parameter
Test Condition
Unit
µA
µA
mA
mA
µA
V
Min .
Max.
±2.5
±2.5
2
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
IN
CC
0V ≤ V
≤ V , Q in Hi-Z
CC
ILO
OUT
V
= 5V, S = V , f = 2 MHz
IH
CC
Supply Current (CMOS
Inputs)
ICC
V
= 2.5V, S = V , f = 2 MHz
1
CC
IH
V
CC
= 2.5V, S = V , C = V
SS
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage (D, C, S)
Input High Voltage (D, C, S)
5
SS
0.2 V
–0.45
0.7 V
CC
V
CC
+ 1
VIH
V
CC
V
= 5V, I = 2.1mA
0.4
0.2
V
CC
OL
VOL
Output Low Voltage (Q)
Output High Voltage (Q)
V
CC
= 2.5V, I = 100µA
OL
V
V
= 5V, I
= –400µA
2.4
–0.2
V
CC
OH
VOH
V
= 2.5V, I
= –100µA
V
V
CC
OH
CC
Note: 1. New product: identified by Process Identification letter W or G.
Table 15. DC Characteristics (M93Sx6-R)
1
1
Symbol
ILI
Parameter
Test Condition
Unit
µA
µA
mA
mA
µA
V
Min.
Max.
±2.5
±2.5
2
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
IN
CC
0V ≤ V
≤ V , Q in Hi-Z
CC
ILO
OUT
V
= 5V, S = V , f = 2 MHz
IH
CC
Supply Current (CMOS
Inputs)
ICC
V
= 1.8V, S = V , f = 1 MHz
1
CC
IH
V
CC
= 1.8V, S = V , C = V
SS
ICC1
VIL
Supply Current (Stand-by)
Input Low Voltage (D, C, S)
Input High Voltage (D, C, S)
Output Low Voltage (Q)
Output High Voltage (Q)
2
SS
0.2 V
–0.45
0.8 V
CC
V
CC
+ 1
VIH
VOL
VOH
V
CC
V
V
= 1.8V, I = 100µA
0.2
V
CC
OL
= 1.8V, I
= –100µA
V
–0.2
CC
V
CC
OH
Note: 1. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
21/34
M93S66, M93S56, M93S46
Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3)
Test conditions specified in Table 8. and Table 5.
3
3
4
4
Symbol
Alt.
Parameter
Clock Frequency
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
SK
D.C.
50
50
0
1
D.C.
50
50
0
2
t
t
t
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Clock Low to Protect Enable Transition
PRVCH
PRES
t
t
ns
WVCH
PES
t
ns
CLPRX
PREH
Chip Select Low to Write Enable
Transition
t
t
250
250
50
250
50
ns
ns
ns
SLWX
PEH
t
Chip Select Low to Clock High
SLCH
Chip Select Set-up Time
M93C46, M93C56, M93C66
50
t
t
t
SHCH
CSS
Chip Select Set-up time
M93C76, M93C86
100
50
ns
2
t
Chip Select Low to Chip Select High
Clock High Time
250
250
200
200
ns
ns
t
CS
SLSH
CHCL
CLCH
1
1
t
t
SKH
t
Clock Low Time
250
100
100
100
0
200
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SKL
t
t
Data In Set-up Time
DVCH
DIS
DIH
SKS
t
t
Data In Hold Time
CHDX
t
t
t
Clock Set-up Time (relative to S)
Chip Select Hold Time
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Delay to Output Low
CLSH
t
CLSL
CSH
t
t
SV
400
200
400
400
10
200
100
200
200
5
SHQV
t
t
DF
SLQZ
CHQL
t
t
t
PD0
t
Delay to Output Valid
CHQV
PD1
t
t
Erase/Write Cycle time
W
WP
Note: 1. t
+ t
CLCH
≥ 1 / f .
C
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W or G.
22/34
M93S66, M93S56, M93S46
Table 17. AC Characteristics (M93Sx6-W, Device Grade 6)
Test conditions specified in Table 9. and Table 6.
3
3
4
4
Symbol
Alt.
Parameter
Clock Frequency
Unit
MHz
ns
Min.
Max.
Min.
Max.
f
C
f
SK
D.C.
50
50
0
1
D.C.
50
50
0
2
t
t
t
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Clock Low to Protect Enable Transition
PRVCH
PRES
t
t
ns
WVCH
PES
t
ns
CLPRX
PREH
Chip Select Low to Write Enable
Transition
t
t
250
250
ns
SLWX
PEH
t
Chip Select Low to Clock High
Chip Select Set-up Time
250
100
50
50
ns
ns
ns
SLCH
t
t
SHCH
CSS
2
t
Chip Select Low to Chip Select High
1000
200
t
CS
SLSH
1
t
Clock High Time
350
200
ns
t
SKH
CHCL
1
t
Clock Low Time
250
100
100
100
0
200
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
t
SKL
CLCH
t
t
Data In Set-up Time
DVCH
DIS
t
t
Data In Hold Time
CHDX
DIH
t
t
Clock Set-up Time (relative to S)
Chip Select Hold Time
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Delay to Output Low
CLSH
SKS
t
t
CLSL
CSH
t
t
400
200
100
200
200
5
SHQV
SV
t
t
200
400
400
10
SLQZ
DF
t
t
CHQL
PD0
t
t
Delay to Output Valid
CHQV
PD1
t
t
Erase/Write Cycle time
W
WP
Note: 1. t
+ t ≥ 1 / f .
CLCH C
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Current product: identified by Process Identification letter F or M.
4. New product: identified by Process Identification letter W or G.
23/34
M93S66, M93S56, M93S46
Table 18. AC Characteristics (M93Sx6-W, Device Grade 3)
Test conditions specified in Table 9. and Table 6.
3
3
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
D.C.
50
Max.
f
f
SK
Clock Frequency
2
C
t
t
t
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Clock Low to Protect Enable Transition
Chip Select Low to Write Enable Transition
Chip Select Low to Clock High
Chip Select Set-up Time
PRVCH
PRES
t
t
50
ns
WVCH
PES
t
0
ns
CLPRX
PREH
t
t
250
50
ns
SLWX
PEH
t
ns
SLCH
t
t
50
ns
SHCH
CSS
2
t
Chip Select Low to Chip Select High
200
200
200
ns
t
CS
SLSH
CHCL
CLCH
1
1
t
Clock High Time
Clock Low Time
ns
ns
t
t
SKH
t
SKL
t
t
t
Data In Set-up Time
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ms
DVCH
DIS
t
Data In Hold Time
CHDX
DIH
t
t
Clock Set-up Time (relative to S)
Chip Select Hold Time
CLSH
SKS
t
t
CLSL
CSH
t
t
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Delay to Output Low
200
100
200
200
5
SHQV
SV
t
t
SLQZ
CHQL
DF
t
t
t
PD0
t
Delay to Output Valid
CHQV
PD1
t
W
t
Erase/Write Cycle time
WP
Note: 1. t
+ t ≥ 1 / f .
CLCH C
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. New product: identified by Process Identification letter W or G.
24/34
M93S66, M93S56, M93S46
Table 19. AC Characteristics (M93Sx6-R)
Test conditions specified in Table 9. and Table 7.
3
3
Symbol
Alt.
Parameter
Unit
MHz
ns
Min.
Max.
f
f
SK
Clock Frequency
D.C.
50
1
C
t
t
t
Protect Enable Valid to Clock High
Write Enable Valid to Clock High
Clock Low to Protect Enable Transition
Chip Select Low to Write Enable Transition
Chip Select Low to Clock High
PRVCH
PRES
t
t
50
ns
WVCH
PES
t
0
ns
CLPRX
PREH
t
t
250
250
50
ns
SLWX
PEH
t
ns
SLCH
t
t
Chip Select Set-up Time
ns
SHCH
CSS
2
t
Chip Select Low to Chip Select High
250
ns
t
CS
SLSH
CHCL
CLCH
1
1
t
Clock High Time
Clock Low Time
250
250
ns
ns
t
t
SKH
t
SKL
t
t
t
Data In Set-up Time
100
100
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ms
DVCH
DIS
t
Data In Hold Time
CHDX
DIH
t
t
Clock Set-up Time (relative to S)
Chip Select Hold Time
CLSH
SKS
t
t
CLSL
CSH
t
t
Chip Select to Ready/Busy Status
Chip Select Low to Output Hi-Z
Delay to Output Low
400
200
400
400
10
SHQV
SV
t
t
SLQZ
CHQL
DF
t
t
t
PD0
t
Delay to Output Valid
CHQV
PD1
t
W
t
Erase/Write Cycle time
WP
Note: 1. t
+ t ≥ 1 / f .
CLCH C
CHCL
2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles.
3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office.
25/34
M93S66, M93S56, M93S46
Figure 10. Synchronous Timing (Start and Op-Code Input)
PRE
tPRVCH
W
tWVCH
tCHCL
C
tCLSH
tSHCH
tDVCH
tCLCH
S
D
tCHDX
OP CODE
START
OP CODE
OP CODE INPUT
START
AI02025
Figure 11. Synchronous Timing (Read or Write)
C
tCLSL
S
tDVCH
tCHDX
tCHQV
tSLSH
A0
D
Q
An
tSLQZ
tCHQL
Hi-Z
Q15
Q0
ADDRESS INPUT
DATA OUTPUT
AI002026
26/34
M93S66, M93S56, M93S46
Figure 12. Synchronous Timing (Read or Write)
PRE
tCLPRX
W
C
tSLWX
tSLCH
tCLSL
S
tSLSH
tDVCH
tCHDX
A0/D0
An
D
Q
tSHQV
BUSY
tW
tSLQZ
Hi-Z
READY
ADDRESS/DATA INPUT
WRITE CYCLE
AI02027
27/34
M93S66, M93S56, M93S46
PACKAGE MECHANICAL
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Note: Drawing is not to scale.
Table 20. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
28/34
M93S66, M93S56, M93S46
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
29/34
M93S66, M93S56, M93S46
Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.100
0.150
0.950
0.400
0.230
3.100
5.150
3.100
–
Typ.
Max.
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
0.2028
0.1220
–
A
A1
A2
b
0.050
0.750
0.250
0.130
2.900
4.650
2.900
–
0.0020
0.0295
0.0098
0.0051
0.1142
0.1831
0.1142
–
0.850
0.0335
c
D
3.000
4.900
3.000
0.650
0.1181
0.1929
0.1181
0.0256
E
E1
e
CP
L
0.100
0.700
0.0039
0.0276
0.550
0.950
0.400
0°
0.0217
0.0374
0.0157
0°
L1
α
6°
6°
30/34
M93S66, M93S56, M93S46
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 23. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
31/34
M93S66, M93S56, M93S46
PART NUMBERING
Table 24. Ordering Information Scheme
Example:
M93S66
–
W MN
6
T
P
Device Type
M93 = MICROWIRE serial access EEPROM (x16) with
Block Protection
Device Function
66 = 4 Kbit (256 x 16)
56 = 2 Kbit (128 x 16)
46 = 1 Kbit (64 x 16)
Operating Voltage
blank = V = 4.5 to 5.5V
CC
W = V = 2.5 to 5.5V
CC
R = V = 1.8 to 5.5V
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
2
DS = TSSOP8 (3x3mm body size)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
1
3 = Automotive: device tested with High Reliability Certified Flow over –40 to 125 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free
2
3
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Available only on new products: identified by the Process Identification letter W or G.
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
Table 25. How to Identify Current and New Products by the Process Identification Letter
1
1
Markings on Current Products
Markings on New Products
M93S46W6
M93S46W6
AYWWF (or AYWWM)
AYWWW (or AYWWG)
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST
Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059).
32/34
M93S66, M93S56, M93S46
REVISION HISTORY
Table 26. Document Revision History
Date
Rev.
Description of Revision
Document reformatted, and reworded, using the new template. Temperature range 1 removed.
TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added,
with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and
corresponding parameters adjusted).
07-Mar-2002
2.0
Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges
26-Mar-2003
14-Apr-2003
2.1
2.2
V
OUT
and V separated from V in the Absolute Maximum Ratings table
IN IO
Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices
with Process Identification Letter W.
Standby current corrected for -R range. Four missing parameters restored to all AC
Characteristics tables
23-May-2003
24-Nov-2003
2.3
3.0
Table of contents, and Pb-free options added. V (min) improved to -0.45V.
IL
Absolute Maximum Ratings for V (min) and V (min) changed. Soldering temperature
IO
CC
19-Apr-2004
4.0
information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to
HRCF and automotive environments. Process identification letter “G” information added
33/34
M93S66, M93S56, M93S46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
34/34
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