M95080-DF [STMICROELECTRONICS]
8 Kbit SPI总线EEPROM，带高速时钟;
| 型号： | M95080-DF |
| 厂家： | 
ST |
| 描述： | 8 Kbit SPI总线EEPROM，带高速时钟 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 |
| 文件： | 总45页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M95160
M95080
16 Kbit and 8 Kbit serial SPI bus EEPROM
with high speed clock
Figure 1.
Packages
Features
■ Compatible with SPI bus serial interface
(positive clock SPI modes)
■ Single supply voltage:
– 4.5 V to 5.5 V for M95xxx
– 2.5 V to 5.5 V for M95xxx-W
– 1.8 V to 5.5 V for M95xxx-R
SO8 (MN)
150 mil width
■ High Speed: 10 MHz
■ Status Register
■ Hardware Protection of the Status Register
■ Byte and page write (up to 32 bytes)
■ Self-timed programming cycle
■ Adjustable size read-only EEPROM area
■ Enhanced ESD protection
TSSOP8 (DW)
169 mil width
■ More than 1 million Erase/Write cycles
■ More than 40-year data retention
■ Packages
UFDFPN8 (MB)
2 x 3 mm (MLP)
– ECOPACK® (RoHS compliant)
Table 1.
Device summary
Part number
Reference
M95160
M95160
M95080
M95160-W
M95160-R
M95080
M95080-W
M95080-R
May 2007
Rev 6
1/45
www.st.com
1
Contents
M95160, M95080
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
4.1.3
4.1.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
4.3
4.4
4.5
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
6.2
6.3
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/45
M95160, M95080
Contents
6.3.2
6.3.3
6.3.4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
6.5
6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
10
11
12
3/45
List of tables
M95160, M95080
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-Protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160 and M95080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-W and M95080-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating conditions (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
Table 25.
2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 40
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Available M95160 products (package, voltage range, temperature grade) . . . . . . . . . . . . 42
Available M95080 products (package, voltage range, temperature grade) . . . . . . . . . . . . 42
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/45
M95160, M95080
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 38
Figure 19. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm², package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 40
5/45
Description
M95160, M95080
1
Description
These electrically erasable programmable memory (EEPROM) devices are accessed by a
high speed SPI-compatible bus. The memory array is organized as 2048 x 8 bit (M95160),
and 1024 x 8 bit (M95080).
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 2. and Figure 2.
The device is selected when Chip Select (S) is taken Low. Communications with the device
can be interrupted using Hold (HOLD).
In order to meet environmental requirements, ST offers the M95xxx in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2.
Logic diagram
V
CC
D
C
S
Q
M95xxx
W
HOLD
V
SS
AI01789C
Table 2.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
Input
Output
Input
Input
Input
D
Serial Data input
Serial Data output
Chip Select
Write Protect
Hold
Q
S
W
HOLD
VCC
VSS
Supply voltage
Ground
6/45
M95160, M95080
Description
Figure 3.
8-pin package connections (top view)
M95xxx
S
Q
1
2
3
4
8
V
CC
HOLD
7
W
6
5
C
D
V
SS
AI01790D
1. See Package mechanical section for package dimensions, and how to identify pin-1.
7/45
Signal description
M95160, M95080
2
Signal description
During all operations, V must be held stable and within the specified valid range:
CC
V
(min) to V (max).
CC
CC
All of the input and output signals must be held High or Low (according to voltages of V ,
IH
V
, V or V , as specified in Table 13. to Table 18.). These signals are described next.
OH
IL OL
2.1
2.2
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
2.4
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
8/45
M95160, M95080
Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and must be stable during all write instructions.
2.7
2.8
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for the V supply voltage.
CC
SS
9/45
Connecting to the SPI bus
M95160, M95080
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 4. shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
VCC
VCC
C
Q
D
C
Q
D
C Q D
VSS
VSS
VSS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data Output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low
(while the S line is pulled High): this ensures that S and C do not become High at the same
time, and so, that the t
requirement is met. The typical value of R is 100 kΩ.
SHCH
10/45
M95160, M95080
Connecting to the SPI bus
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
■
■
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5., is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
■
■
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
SPI modes supported
CPOL CPHA
C
0
1
0
1
C
D
MSB
Q
MSB
AI01438B
11/45
Operating features
M95160, M95080
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 9, Table 10 and
CC
CC
Table 11). In order to secure a stable dc supply voltage, it is recommended to decouple the
V
V
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
CC
/V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
4.1.2
Power-up conditions
When the power supply is turned on, V rises from V to V . During this time, the Chip
CC
SS
CC
Select (S) line is not allowed to float but should follow the V voltage, it is therefore
CC
recommended to connect the S line to V via a suitable pull-up resistor.
CC
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The V rise time must not vary faster than 1 V/µs.
CC
4.1.3
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V ), the device does not respond to any
CC
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Table 9, Table 10 and Table 11).
CC
Once V has passed the POR threshold, the device is reset and is in the following state:
CC
■
■
Standby Power mode
deselected (at next power-up, a falling edge is required on Chip Select (S) before any
instructions can be started)
■
not in the Hold condition
Status Register state:
■
■
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are unchanged from the previous power-down (they are non-volatile bits).
12/45
M95160, M95080
Operating features
4.1.4
Power-down
At Power-down (continuous decrease of V ), as soon as V drops from the normal
CC
CC
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in Standby Power mode (that is
there should be no internal Write cycle in progress). Chip Select (S) should be allowed to
follow the voltage applied on V
.
CC
4.2
4.3
Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. The
device consumes I , as specified in Table 13. to Table 18.
CC
When Chip Select (S) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
.
CC1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as
Serial Clock (C) already being Low.
The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as
Serial Clock (C) already being Low.
4.4
Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
13/45
Operating features
M95160, M95080
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
■
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
■
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
■
■
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
■
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
■
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 3.
Write-Protected block size
Status Register Bits
Array Addresses Protected
Protected Block
BP1
BP0
M95160
M95080
0
0
1
1
0
1
0
1
none
none
none
Upper quarter
Upper half
0600h - 07FFh
0400h - 07FFh
0000h - 07FFh
0300h - 03FFh
0200h - 03FFh
0000h - 03FFh
Whole memory
14/45
M95160, M95080
Memory organization
5
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
High Voltage
Generator
W
S
Control Logic
C
D
Q
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Register
Size of the
Read only
EEPROM
area
1 Page
X Decoder
AI01272C
15/45
Instructions
M95160, M95080
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4.), the device automatically
deselects itself.
Table 4.
Instruction set
Instruction
Description
Write Enable
Instruction Format
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Write Disable
RDSR
WRSR
READ
WRITE
Read Status Register
Write Status Register
Read from Memory Array
Write to Memory Array
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
High.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
16/45
M95160, M95080
Instructions
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven Low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
■
■
■
■
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
17/45
Instructions
M95160, M95080
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1
6.3.2
6.3.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
18/45
M95160, M95080
Instructions
Figure 9.
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
19/45
Instructions
M95160, M95080
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D). The instruction is
terminated by driving Chip Select (S) High at a byte boundary of the input data. The self-
timed Write cycle then starts, and continues for a period t (as specified in Table 19,
W
Table 20, Table 21, Table 22 and Table 23), at the end of which the Write in Progress (WIP)
bit is reset to 0. The instruction sequence is shown in Figure 10.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is t ) is initiated.
W
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 5.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
20/45
M95160, M95080
Instructions
Table 6.
Protection modes
Memory content
W
Signal
SRWD
Bit
Write Protection of the
Mode
Status Register
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
Software
Protected
(SPM)
Ready to accept
Write Protected
Write instructions
The values in the BP1
and BP0 bits can be
changed
1
1
Status Register is
Hardware write
protected
Hardware
Protected
(HPM)
Ready to accept
Write Protected
0
1
Write instructions
The values in the BP1
and BP0 bits cannot be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.
The protection features of the device are summarized in Table 3.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
■
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
■
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
■
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
■
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
21/45
Instructions
M95160, M95080
(1)
Table 7.
Address range bits
Device
M95160
M95080
Address Bits
A10-A0
A9-A0
1. b15 to b11 are Don’t Care on the M95160.
b15 to b10 are Don’t Care on the M95080.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
22/45
M95160, M95080
Instructions
6.5
Read from Memory Array (READ)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI01793D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
23/45
Instructions
M95160, M95080
6.6
Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of Figure 12., this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
(as specified in Table 20. to Table 23.), at
WC
the end of which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in Figure 13., the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
■
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
■
■
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
■
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
Q
High Impedance
AI01795D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
24/45
M95160, M95080
Instructions
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
Data Byte 1
15 14 13
3
2
1
0
7
6
5
4
3
2
0
1
D
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
0
7
6
5
4
3
2
0
6
5
4
3
2
0
1
1
1
D
AI01796D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
25/45
Delivery state
M95160, M95080
7
Delivery state
7.1
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8
Maximum rating
Stressing the device outside the ratings listed in Table 8. may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 8.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TA
TSTG
TLEAD
VO
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
V
Lead temperature during soldering
Output voltage
See note (1)
–0.50
–0.50
–0.50
–4000
VCC+0.6
6.5
VI
Input voltage
V
VCC
VESD
Supply voltage
6.5
V
Electrostatic discharge voltage (human body model)(2)
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100 pF, R1=1500 Ω, R2=500 Ω)
26/45
M95160, M95080
DC and AC parameters
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 9.
Symbol
Operating conditions (M95160 and M95080)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
4.5
–40
–40
5.5
85
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
°C
°C
125
Table 10. Operating conditions (M95160-W and M95080-W)
Symbol
Parameter
Min.
Max.
Unit
VCC
Supply voltage
2.5
–40
–40
5.5
85
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
°C
°C
TA
125
Table 11. Operating conditions (M95160-R and M95080-R)
Symbol
Parameter
Min.(1)
Max.(1)
Unit
VCC
TA
Supply voltage
Ambient operating temperature
1.8
5.5
85
V
–40
°C
1. This product is under development. For more information, please contact your nearest ST sales office.
(1)
Table 12. AC measurement conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
CL
Load capacitance
30
pF
ns
V
Input rise and fall times
50
Input pulse voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and output timing reference voltages
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 14. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI00825B
27/45
DC and AC parameters
M95160, M95080
(1)
Table 13. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
Output capacitance (Q)
Input capacitance (D)
VOUT = 0 V
VIN = 0 V
VIN = 0 V
8
8
6
pF
pF
pF
CIN
Input capacitance (other pins)
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 14.
Symbol
DC characteristics (M95160 and M95080, device grade 3)
Parameter
Test condition
VIN = VSS or VCC
Min.
Max.
Unit
ILI
Input leakage current
± 2
± 2
µA
µA
ILO
Output leakage current S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
Supply current
ICC
3
5
mA
µA
VCC = 5 V, Q = open
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
ICC1
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.45
0.3 VCC
V
V
V
V
0.7 VCC VCC+1
0.4
(1)
VOL
IOL = 2 mA, VCC = 5 V
IOH = –2 mA, VCC = 5 V
(1)
VOH
0.8 VCC
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
Table 15.
Symbol
DC characteristics (M95160 and M95080, device grade 6)
Parameter
Test condition
Min.
Max.
Unit
Input leakage
current
ILI
ILO
ICC
ICC1
V
IN = VSS or VCC
± 2
µA
Output leakage
current
S = VCC, VOUT = VSS or VCC
± 2
5
µA
mA
µA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 5 V, Q = open
Supply current
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
2
VIL
VIH
Input low voltage
Input high voltage
–0.45
0.3 VCC
VCC+1
0.4
V
V
V
0.7 VCC
(1)
VOL
Output low voltage IOL = 2 mA, VCC = 5 V
Output high
(1)
VOH
IOH = –2 mA, VCC = 5 V
voltage
0.8 VCC
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
28/45
M95160, M95080
DC and AC parameters
Table 16. DC characteristics (M95160-W and M95080-W, device grade 3)
Symbol
Parameter
Test condition
Min.
Max.
Unit
Input leakage
current
ILI
ILO
ICC
ICC1
VIN = VSS or VCC
± 2
µA
Output leakage
current
S = VCC, VOUT = VSS or VCC
± 2
2
µA
mA
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
Supply current
Supply current
(Standby)
S = VCC, VCC = 2.5 V, VIN = VSS or VCC
2
VIL
VIH
Input low voltage
Input high voltage
–0.45
0.3 VCC
V
V
V
V
0.7 VCC VCC+1
0.4
VOL
VOH
Output low voltage IOL = 1.5 mA, VCC = 2.5 V
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
Table 17. DC characteristics (M95160-W and M95080-W, device grade 6)
Symbol
Parameter
Test condition
Min.
Max.
Unit
Input leakage
current
ILI
VIN = VSS or VCC
± 2
µA
Output leakage
current
ILO
S = VCC, VOUT = VSS or VCC
± 2
2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5V, Q = open, Process SA
mA
ICC
Supply current
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 2.5 V, Q = open, Process GB or
SB
5
2
mA
µA
Supply current
(Standby)
S = VCC, 2.5 V <VCC < 5.5 V
VIN = VSS or VCC
ICC1
VIL
VIH
Input low voltage
Input high voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
0.4
V
V
V
V
VOL
VOH
Output low voltage IOL = 1.5 mA, VCC = 2.5 V
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
29/45
DC and AC parameters
M95160, M95080
Table 18. DC characteristics (M95160-R and M95080-R)
Symbol
Parameter
Test Condition
VIN = VSS or VCC
Min.
Max.
Unit
ILI
Input leakage current
± 2
± 2
µA
µA
ILO
Output leakage current S = VCC, VOUT = VSS or VCC
C = 0.1VCC/0.9VCC at 5 MHz,
Supply current
ICC
3
1
mA
µA
VCC = 1.8 V, Q = open
Supply current
(Standby)
S = VCC, VIN = VSS or VCC,
1.8 < VCC < 2.5 V
ICC1
VIL
VIH
Input low voltage
Input high voltage
Output low voltage
Output high voltage
–0.45 0.3 VCC
0.7 VCC VCC+1
0.3
V
V
V
V
VOL
VOH
IOL = 0.15 mA, VCC = 1.8 V
IOH = –0.1 mA, VCC = 1.8 V
0.8 VCC
30/45
M95160, M95080
DC and AC parameters
Table 19.
AC characteristics (M95160 and M95080, device grade 3)
Test conditions specified in Table 12. and Table 9.
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK
tCSS1
tCSS2
tCS
Clock frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
S active setup time
S not active setup time
S deselect time
90
100
90
tCSH
S active hold time
S not active hold time
Clock high time
90
(1)
tCH
tCLH
tCLL
tRC
90
(1))
tCL
Clock low time
90
(2)
tCLCH
Clock rise time
1
1
(2)
tCHCL
tFC
Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU
tDH
Data in setup time
20
30
70
40
0
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
100
60
tCLQV
tCLQX
Clock low to output valid
Output hold time
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
50
50
50
100
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
Write time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
31/45
DC and AC parameters
Table 20.
M95160, M95080
AC characteristics (M95160 and M95080, device grade 6)
Test conditions specified in Table 12. and Table 9.
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCK
Clock frequency
D.C.
15
15
40
25
15
40
40
10
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
tCSH S active hold time
S not active hold time
(1)
tCH
tCLH
tCLL
tRC
Clock high time
Clock low time
Clock rise time
Clock fall time
(1)
tCL
(2)
tCLCH
1
1
(2)
tCHCL
tFC
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
15
15
15
20
0
tDH
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
25
35
tCLQV
tCLQX
Clock low to output valid
Output hold time
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
20
20
25
35
5
(2)
tQHQL
Output Fall Time
tHHQV
HOLD High to Output Valid
HOLD Low to Output High-Z
Write Time
((2))
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
32/45
M95160, M95080
DC and AC parameters
Table 21. AC characteristics (M95160-W and M95080-W, device grade 3)
Test conditions specified in Table 12. and Table 10.
Symbol
Alt.
Parameter
Min.
Max. Unit
fC
fSCK
Clock frequency
D.C.
90
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCSS1 S active setup time
tCSS2 S not active setup time
90
tCS
S deselect time
100
90
tCSH
S active hold time
S not active hold time
Clock high time
90
(1)
tCH
tCLH
tCLL
tRC
90
(1)
tCL
Clock low time
90
(2)
tCLCH
Clock rise time
1
1
(2)
tCHCL
tFC
Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU
tDH
Data in setup time
20
30
70
40
0
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
Output disable time
0
(2)
tSHQZ
tDIS
tV
100
60
tCLQV
tCLQX
Clock low to output valid
Output hold time
tHO
tRO
tFO
tLZ
0
(2)
tQLQH
Output rise time
50
50
50
100
5
(2)
tQHQL
Output fall time
tHHQV
HOLD high to output valid
HOLD low to output High-Z
Write time
(2)
tHLQZ
tHZ
tWC
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
33/45
DC and AC parameters
M95160, M95080
Table 22. AC characteristics (M95160-W and M95080-W, device grade 6)
Test conditions specified in Table 12. and Table 10.
Process GB or SB (1)
Process SA
Symbol
Alt.
Parameter
Unit
Min.
Max.
Min.
Max.
fC
fSCK Clock frequency
tCSS1 S active setup time
tCSS2 S not active setup time
tCS S deselect time
tCSH S active hold time
S not active hold time
tCLH Clock high time
tCLL Clock low time
D.C.
90
5
D.C.
30
30
40
30
30
40
40
10
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
90
100
90
90
(2)
tCH
90
(2)
tCL
90
(3)
tCLCH
tRC Clock rise time
1
1
2
2
(3)
tCHCL
tFC Clock fall time
tDVCH
tCHDX
tDSU Data in setup time
tDH Data in hold time
20
30
10
10
Clock low hold time after
HOLD not active
tHHCH
tHLCH
tCLHL
tCLHH
70
40
0
30
30
0
ns
ns
ns
ns
Clock low hold time after
HOLD active
Clock low set-up time before
HOLD active
Clock low set-up time before
HOLD not active
0
0
(3)
tSHQZ
tDIS Output disable time
100
60
40
40
ns
ns
ns
ns
ns
ns
ns
ms
tCLQV
tCLQX
tV
Clock low to output valid
tHO Output hold time
tRO Output rise time
0
0
(3)
tQLQH
50
50
50
100
5
40
40
40
40
5
(3)
tQHQL
tFO Output fall time
tHHQV
tLZ HOLD high to output valid
tHZ HOLD low to output High-Z
tWC Write time
(3)
tHLQZ
tW
1. Preliminary data
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Value guaranteed by characterization, not 100% tested in production.
34/45
M95160, M95080
DC and AC parameters
Table 23. AC characteristics (M95160-R and M95080-R)
Test conditions specified in Table 12. and Table 11.
Symbol Alt.
Parameter
Min.
Max.
Unit
fC
fSCK Clock frequency
D.C.
60
60
90
60
60
80
80
5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
0
tSLCH tCSS1 S active setup time
tSHCH tCSS2 S not active setup time
tSHSL
tCHSH
tCHSL
tCS S deselect time
tCSH S active hold time
S not active hold time
(1)
tCH
tCLH Clock high time
(1)
tCL
tCLL Clock low time
(2)
tCLCH
tRC Clock rise time
2
2
(2)
tCHCL
tFC Clock fall time
tDVCH
tCHDX
tHHCH
tHLCH
tCLHL
tCLHH
tDSU Data in setup time
tDH Data in hold time
20
20
60
60
0
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock low set-up time before HOLD active
Clock low set-up time before HOLD not active
tDIS Output disable time
tV Clock low to output valid
tHO Output hold time
0
0
(2)
tSHQZ
tCLQV
tCLQX
80
80
ns
ns
ns
ns
ns
ns
ns
ms
0
(2)
tQLQH
tRO Output rise time
80
80
80
80
5
(2)
tQHQL
tHHQV
tFO Output fall time
tLZ HOLD high to output valid
tHZ HOLD low to output High-Z
tWC Write time
(2)
tHLQZ
tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
35/45
DC and AC parameters
M95160, M95080
Figure 15. Serial input timing
tSHSL
S
C
tCHSL
tSLCH
tCHSH
tSHCH
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 16. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHHQV
tHLQZ
Q
D
HOLD
AI01448B
36/45
M95160, M95080
DC and AC parameters
Figure 17. Output timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449e
37/45
Package mechanical
M95160, M95080
10
Package mechanical
Figure 18. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
0.069
A
1.75
0.25
A1
A2
b
0.10
1.25
0.28
0.17
0.004
0.010
0.049
0.011
0.007
0.48
0.23
0.10
5.00
6.20
4.00
–
0.019
0.009
0.004
0.197
0.244
0.157
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.193
0.189
0.228
0.150
–
E
0.236
0.154
0.050
E1
e
h
0.25
0°
0.50
8°
0.010
0°
0.020
8°
k
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
38/45
M95160, M95080
Package mechanical
Figure 19. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm², package outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
Table 25. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
0.022
Max
0.024
A
0.55
0.02
0.25
2.00
1.60
0.50
0.00
0.20
1.90
1.50
0.60
0.05
0.30
2.10
1.70
0.08
3.10
0.30
–
0.020
A1
b
0.001
0.010
0.079
0.063
0.000
0.008
0.075
0.059
0.002
0.012
0.083
0.067
0.003
0.122
0.012
–
D
D2
ddd
E
3.00
0.20
0.50
0.45
2.90
0.10
–
0.118
0.008
0.020
0.018
0.114
0.004
–
E2
e
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
0.30
0.012
39/45
Package mechanical
M95160, M95080
Figure 20. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 26. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
40/45
M95160, M95080
Part numbering
11
Part numbering
Table 27. Ordering information scheme
Example:
M95160
–
W MN 6
T
P /S
Device type
M95 = SPI serial access EEPROM
Device function
160 = 16 Kbit (2048 x 8)
080 = 8 Kbit (1024 x 8)
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
MN = SO8 (150 mil width)
DW = TSSOP8
MB = MLP8 (UFDFPN8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1)
Automotive temperature range (–40 to 125 °C)
.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
G or P = ECOPACK® (RoHS compliant)
Process(2)
/G or /S = F6SP36%
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. The Process letter (/G or /S) applies only to Range 3 devices. For Range 6 devices, the process letters do
not appear in the Ordering Information but only appear on the device package (marking) and on the
shipment box. Please contact your nearest ST Sales Office. For more information on how to identify
products by the Process Identification Letter, please refer to AN2043: Serial EEPROM Device Marking.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
41/45
Part numbering
M95160, M95080
Table 28. Available M95160 products (package, voltage range, temperature grade)
M95160
4.5 V to 5.5 V
M95160-W
2.5 V to 5.5 V
M95160-R
1.8 V to 5.5 V
Package
SO8 (MN)
Range 6
Range3
Range 6
Range3
Range 6
Range 6
Range3
TSSOP (DW)
NA(1)
NA(1)
Range 6
Range 6
MLP 2x3mm (MB)
NA(1)
1. NA = Not available
Table 29. Available M95080 products (package, voltage range, temperature grade)
M95080
4.5 V to 5.5 V
M95080-W
2.5 V to 5.5 V
M95080-R
1.8 V to 5.5 V
Package
SO8 (MN)
Range 6
Range3
Range 6
Range3
Range 6
Range 6
Range3
TSSOP (DW)
NA(1)
NA(1)
Range 6
Range 6
MLP 2x3mm (MB)
Range 6
1. NA = Not available
42/45
M95160, M95080
Revision history
12
Revision history
Table 30. Document revision history
Date
Revision
Changes
19-Jul-2001
1.0
Document written from previous M95640/320/160/080 datasheet
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range
06-Feb-2002
1.1
18-Oct-2002
04-Nov-2002
13-Nov-2002
1.2
1.3
1.4
TSSOP8 (3x3mm body size, MSOP8) package added
New products, identified by the process letter W, added
Correction to footnote in Ordering Information table
Table of contents, and Pb-free options added. VIL(min) improved to –
0.45V
21-Nov-2003
2.0
MLP8 package added. Absolute Maximum Ratings for VIO(min) and
VCC(min) improved. Soldering temperature information clarified for RoHS
compliant devices. Device Grade 3 clarified, with reference to HRCF and
automotive environments. Process identification letter “G” information
added. SO8 narrow and TSSOP8 Package mechanical specifications
updated.
08-Jun-2004
3.0
Product List summary table added. AEC-Q100-002 compliance. tHHQX
corrected to tHHQV.
07-Oct-2004
21-Sep-2005
4.0
5.0
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint
clarified
Added 20MHz and -S product information. Removed DIP package. Info on
Pull-up resistors, VCC lines and Note 2. added to Figure 4.: Bus master
and memory devices on the SPI bus. Device internal reset paragraph
clarified. Packages compliant with the JEDEC Std J-STD-020C. Process
info updated in DC and AC parameters and Table 27.: Ordering
information scheme.
43/45
Revision history
M95160, M95080
Table 30. Document revision history
Date
Revision
Changes
Document reformatted. Small text changes.
TSSOP8 3 x 3 mm (DS) package removed, 1.65 V to 5.5 V operating
voltage range removed (M95080-S and M95160-S removed).
Figure 4: Bus master and memory devices on the SPI bus updated, note 2
removed and explanatory paragraph added (see Section 3: Connecting to
the SPI bus).
Section 2.7: VCC supply voltage and Section 2.8: VSS ground added.
Power-up, Device Internal Reset and Power-down replaced by
Section 4.1: Supply voltage (VCC).
Command termination specified in Section 6.4: Write Status Register
(WRSR).
Blank process no longer available for M95160, M95080, M95160-W and
M95080-W in the device grade 3 range.
24-May-2007
6
L, GB and SB processes no longer available for M95160 and M95080, in
the device grade 6 range.
L process no longer available for M95160-W and M95080-W in the device
grade 6 range.
ICC1 value and test conditions modified in Table 18: DC characteristics
(M95160-R and M95080-R).
End timing line of tSHQZ modified in Figure 17: Output timing.
SO8N and UFDFPN8 package specifications updated. All packages are
ECOPACK® compliant.
Blank option removed below Plating technology and Note 2 modified in
Table 27: Ordering information scheme.
Table 28: Available M95160 products (package, voltage range,
temperature grade) and Table 29: Available M95080 products (package,
voltage range, temperature grade) added.
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M95160, M95080
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