M95512-WMN6TP/K_技术文档

M95512-DR

M95512-R M95512-W

512 Kbit serial SPI bus EEPROM

with high-speed clock

Features

■ Compatible with the Serial Peripheral Interface

(SPI) bus

■ Memory array

– 512 Kb (64 Kbytes) of EEPROM

– Page size: 128 bytes

■ Additional Write lockable Page (Identification

SO8 (MN)

150 mils width

page)

■ Write

– Byte Write within 5 ms

– Page Write within 5 ms

■ Write Protect: quarter, half or whole memory

array

TSSOP8 (DW)

169 mils width

■ High-speed clock frequency (20 MHz)

■ Single supply voltage: 1.8 V to 5.5 V

■ More than 1 Million Write cycles

■ More than 40-year data retention

■ Enhanced ESD Protection

■ Packages

UFDFPN8 (MB)

2 × 3 mm (MLP)

– ECOPACK2® (RoHS compliant and

Halogen-free)

WLCSP (CS)

September 2010

Doc ID 11124 Rev 13

1/48

www.st.com

1

Contents

M95512-W, M95512-R

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_CCsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_SSground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3

4

Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1

Supply voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1

4.1.2

4.1.3

4.1.4

Operating supply voltage V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2

4.3

4.4

4.5

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13

Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5

6

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1

6.2

6.3

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.1

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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6.3.2

Contents

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.3

6.3.4

6.4

6.5

6.6

6.7

6.8

6.9

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Identification Page (available only in M95512-DR devices) . . . . . . 25

Write Identification Page (available only in M95512-DR devices) . . . . . . 26

Read Lock Status (available only in M95512-DR devices) . . . . . . . . . . . . 27

6.10 Lock ID (available only in M95512-DR devices) . . . . . . . . . . . . . . . . . . . . 27

ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . 29

Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7

8

8.1

8.2

Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10

11

12

13

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List of tables

M95512-W, M95512-R

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M95512-W and M95512-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

M95512-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Operating conditions (M95512-W device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Operating conditions (M95512-W device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Operating conditions (M95512-R and M95512-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC characteristics (current M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC characteristics (new M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 33

AC characteristics (current M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AC characteristics (New M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 36

SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 40

UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

Table 20.

Table 21.

2 × 3 .mm, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

WLCSP-R – 8-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . 42

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Available M95512 products (package, voltage range, temperature grade) . . . . . . . . . . . . 44

Available M95512-DR products (package, voltage range, temperature grade) . . . . . . . . . 44

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

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M95512-W, M95512-R

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7

Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17. Read Lock Status sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 21. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 22. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 23. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39

Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 26. WLCSP-R – 8-bump wafer-length chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . 42

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Description

M95512-W, M95512-R

1

Description

The M95512-W, M95512-R and M95512-DR are electrically erasable programmable

memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of

the document these devices are referred to as M95512, unless otherwise specified.

The M95512-DR also offers an additional page, named the Identification Page (128 bytes)

which can be written and (later) permanently locked in Read-only mode. This Identification

Page offers flexibility in the application board production line, as it can be used to store

unique identification parameters and/or parameters specific to the production line.

Figure 1.

Logic diagram

6

##

$

#

3

1

-ꢂꢁꢁꢀꢄ

7

(/,$

6

33

AIꢀꢁꢂꢃꢁ

The memory array is organized as 65536 × 8 bit. The device is accessed by a simple serial

interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and

Figure 1.

The device is selected when Chip Select (S) is taken low. Communications with the device

can be interrupted using Hold (HOLD).

6/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Table 1.

Description

Signal names

Signal name

Function

Serial Clock

Direction

C

Input

Output

Input

D

Serial Data Input

Serial Data Output

Chip Select

Write Protect

Hold

Q

S

W

HOLD

V_CC

V_SS

Supply voltage

Ground

Caution:

As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet

(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by

STMicroelectronics must never be exposed to UV light.

Figure 2.

SO8, TSSOP8 and UFDFPN8 connections

-ꢂꢁꢁꢀꢄ

3

1

ꢀ

ꢄ

ꢆ

ꢅ

ꢇ

ꢈ

ꢃ

ꢁ

6

##

(/,$

7

#

$

6

33

AIꢀꢁꢂꢃꢅ

1. See Section 11: Package mechanical data for package dimensions, not and how to identify pin-1.

Figure 3.

WLCSP connections (top view, marking side, with balls on the underside)

6_##

$

#

1

7

(/,$

3

6₃₃

AIꢀꢈꢄꢇꢈ

Doc ID 11124 Rev 13

7/48

Signal description

M95512-W, M95512-R

2

Signal description

During all operations, V must be held stable and within the specified valid range:

CC

V

(min) to V (max).

CC

All of the input and output signals must be held high or low (according to voltages of V ,

IH

V

, V or V , as specified in Table 13 and Table 15). These signals are described next.

OH

IL OL

2.1

2.2

Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

2.3

2.4

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Write cycle is in progress, the device will be in the Standby

Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power

mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

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Doc ID 11124 Rev 13

M95512-W, M95512-R

Signal description

2.6

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either high or low, and must be stable during all write instructions.

2.7

2.8

V_CCsupply voltage

V

is the supply voltage.

CC

V_SSground

V

is the reference for the V supply voltage.

SS

CC

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Connecting to the SPI bus

M95512-W, M95512-R

3

Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S) goes low.

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction

(such as the Read from Memory Array and Read Status Register instructions) have been

clocked into the device.

Figure 4.

Bus master and memory devices on the SPI bus

V_SS

V_CC

R

SDO

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDI

SCK

V_CC

C

Q

D

C

Q

D

C Q D

V_SS

SPI Bus Master

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

R

CS3 CS2 CS1

S

W

HOLD

W

HOLD

W

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.

Only one device is selected at a time, so only one device drives the Serial Data Output (Q)

line at a time, the other devices are high impedance.

The pull-up resistor R (represented in Figure 4) ensures that no device is selected if the Bus

Master leaves the S line in the high impedance state.

In applications where the Bus Master might enter a state where all inputs/outputs SPI lines

are in high impedance at the same time (for example, if the Bus Master is reset during the

transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high). This ensures that S and C do not become high at the same

time, and so, that the t

requirement is met.

SHCH

The typical value of R is 100 k,.

10/48

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M95512-W, M95512-R

Connecting to the SPI bus

3.1

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

●

CPOL=0, CPHA=0

CPOL=1, CPHA=1

●

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 5, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

●

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

●

Figure 5.

SPI modes supported

CPOL CPHA

C

0

1

0

1

C

D

Q

MSB

AI01438B

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Operating features

M95512-W, M95512-R

4

Operating features

4.1

Supply voltage (V_CC)

4.1.1

Operating supply voltage V

CC

Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage

CC

within the specified [V (min), V (max)] range must be applied (see Table 8 and

CC

Table 10.). This voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (t ). In

W

order to secure a stable DC supply voltage, it is recommended to decouple the V line with

CC

a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V package

CC SS

pins.

4.1.2

Device reset

In order to prevent inadvertent Write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up, the device does not respond to any instruction until V has

CC

reached the POR threshold voltage (this threshold is lower than the minimum V operating

CC

voltage defined in Table 8 and Table 10).

When V passes over the POR threshold, the device is reset and in the following state:

CC

●

in the Standby Power mode

●

deselected (note that when the device is deselected it is necessary to apply a falling

edge on Chip Select (S) prior to issuing any new instruction, otherwise the instruction is

not executed)

●

Status register values:

–

the Write Enable Latch (WEL) bit is reset to 0

the Write In Progress (WIP) bit is reset to 0

the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

When V passes over the POR threshold, the device is reset and enters the Standby

CC

Power mode, however, the device must not be accessed until V reaches a valid and

CC

stable V voltage within the specified [V (min), V (max)] range defined in Table 8 and

CC

Table 10.

4.1.3

Power-up conditions

When the power supply is turned on, V rises continuously from V to V . During this

CC

SS

CC

time, the Chip Select (S) line is not allowed to float but should follow the V voltage. It is

CC

therefore recommended to connect the S line to V via a suitable pull-up resistor (see

CC

Figure 4).

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been high, prior to going low to start the first operation.

The V voltage has to rise continuously from 0 V up to the minimum V operating voltage

CC

defined in Table 8 and Table 10 and the rise time must not vary faster than 1 V/µs.

12/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Operating features

4.1.4

Power-down

During power-down (continuous decrease in V below the minimum V operating voltage

CC

defined in Table 8 and Table 10), the device must be:

●

deselected (Chip Select (S) should be allowed to follow the voltage applied on V

)

CC

●

in Standby Power mode (that is there should not be any internal write cycle in

progress).

4.2

Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The

device consumes I , as specified in Table 15.

CC

When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in

progress, the device then goes in to the Standby Power mode, and the device consumption

drops to I

.

CC1

4.3

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 6).

The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 6 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Figure 6.

Hold condition activation

C

HOLD

Hold

Condition

AI02029D

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Operating features

M95512-W, M95512-R

4.4

Status register

Figure 7 shows the position of the Status register in the control logic of the device. The

Status register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status register bits

4.5

Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

●

Write and Write Status register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Write (WRITE) instruction completion

●

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S) must be driven high after

the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising

edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

●

The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register

(RDSR) and Read (READ) instructions).

●

The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2.

Write-protected block size

Status register bits

Protected array

addresses

Protected block

BP1

BP0

0

1

0

1

0

1

none

Upper quarter

Upper half

C000h - FFFFh

8000h - FFFFh

0000h - FFFFh

Whole memory

14/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Memory organization

5

Memory organization

The memory is organized as shown in Figure 7.

Figure 7.

Block diagram

HOLD

W

High Voltage

Generator

Control Logic

S

C

D

Q

I/O Shift Register

Address Register

and Counter

Data

Register

Status

Register

Size of the

Read only

EEPROM

area

1 Page

X Decoder

AI01272C

Doc ID 11124 Rev 13

15/48

Instructions

M95512-W, M95512-R

6

Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically

deselects itself.

Table 3.

M95512-W and M95512-R instruction set

Description

Instruction

Instruction format

WREN

WRDI

Write Enable

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Write Disable

RDSR

WRSR

READ

WRITE

Read Status Register

Write Status Register

Read from Memory Array

Write to Memory Array

Table 4.

M95512-DR instruction set

Instruction

format

Instruction

Description

WREN

WRDI

Write Enable

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Write Disable

RDSR

WRSR

READ

WRITE

Read Status Register

Write Status Register

Read from Memory Array

Write to Memory Array

Read Identification

Page

Reads the page dedicated to identification.

Writes the page dedicated to identification.

1000 0011⁽¹⁾

1000 0010⁽¹⁾

Write Identification

Page

Read Lock Status Reads the lock status of the Identification Page.

Lock ID Locks the Identification page in read-only mode.

1000 0011⁽²⁾

1000 0010⁽²⁾

1. Address bit A10 must be 0, all other address bits are Don't Care.

2. Address bit A10 must be 1, all other address bits are Don't Care.

16/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Instructions

6.1

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.

The only way to do this is to send a Write Enable instruction to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then

enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven

high.

Figure 8.

Write Enable (WREN) sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI02281E

6.2

Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction

to the device.

As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select

(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

●

Power-up

WRDI instruction execution

WRSR instruction completion

WRITE instruction completion.

Figure 9.

Write Disable (WRDI) sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI03750D

Doc ID 11124 Rev 13

17/48

Instructions

M95512-W, M95512-R

6.3

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Write or Write Status Register cycle

is in progress. When one of these cycles is in progress, it is recommended to check the

Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible

to read the Status Register continuously, as shown in Figure 10.

The status and control bits of the Status Register are as follows:

6.3.1

6.3.2

6.3.3

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write

Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such

cycle is in progress.

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write or Write Status Register instruction is accepted.

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Write instructions. These bits are written with the Write Status

Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to

1, the relevant memory area (as defined in Table 5) becomes protected against Write

(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the

Hardware Protected mode has not been set.

6.3.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5.

Status register format

b7

b0

SRWD

0

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

18/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Figure 10. Read Status Register (RDSR) sequence

Instructions

S

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C

D

Instruction

Status Register Out

High Impedance

Q

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

AI02031E

Doc ID 11124 Rev 13

19/48

Instructions

M95512-W, M95512-R

6.4

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

Register. Before a WRSR instruction can be accepted, a Write Enable (WREN) instruction

must have been executed.

The Write Status Register (WRSR) instruction is issued by driving Chip Select (S) low,

sending the instruction code and the data byte on Serial Data input (D) and driving Chip

Select (S) high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C)

that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock

(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.

Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed Write

cycle whose duration is t (specified in Table 16 and Table 18). The instruction sequence is

W

shown in Figure 11.

While the Write Status Register cycle is in progress, the Status Register may still be read to

check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the self-timed

Write cycle t , and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is

W

also reset when the Write cycle t is complete.

W

The Write Status Register (WRSR) instruction allows the user to change the values of the

BP1, BP0 and SRWD bits:

●

The Block Protect (BP1, BP0) bits define the size of the area to be treated as read-only,

as defined in Table 6.

●

The SRWD bit (Status Register Write Disable bit), depending on the signal applied on

the Write Protect pin (W), allows the user to set or reset the write protection mode of

the Status Register. When the Status Register is in the Write-protected mode, the Write

Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated upon completion of the WRSR

instruction (after t ).

W

The Write Status Register (WRSR) instruction has no effect on Status Register bits b6, b5,

b4, b1, b0. They are always read as 0.

Figure 11. Write Status Register (WRSR) sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

C

Instruction

Status

Register In

7

6

5

4

3

2

0

1

D

Q

High Impedance

MSB

AI02282D

20/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Table 6.

Instructions

Protection modes

Memory content

W

Signal

SRWD

Bit

Write Protection of the

Mode

Status Register

Protected area⁽¹⁾Unprotected area⁽¹⁾

1

0

Status Register is Writable

(if the WREN instruction

has set the WEL bit)

Software

Protected

(SPM)

Ready to accept

Write Protected

Write instructions

The values in the BP1 and

BP0 bits can be changed

1

Status Register is

Hardware write protected

Hardware

Protected

(HPM)

Ready to accept

Write Protected

0

1

The values in the BP1 and

BP0 bits cannot be

changed

Write instructions

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register (provided that the WEL bit has

previously been set by a WREN instruction), regardless of the logic level applied on the

Write Protect (W) input pin.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W) input pin:

●

If Write Protect (W) is driven high, it is possible to write to the Status Register (provided

that the WEL bit has previously been set by a WREN instruction.

●

If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the WEL bit has previously been set by a WREN instruction (attempts to write to the

Status Register are rejected, and are not accepted for execution). As a consequence,

all the data bytes in the memory area that are software-protected (SPM) by the Block

Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against

data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be

entered either:

●

by setting the SRWD bit after driving the Write Protect (W) input pin low

or by driving the Write Protect (W) input pin low after setting the SRWD bit

●

Once entered, the Hardware-protected mode (HPM) can only be exited by pulling Write

Protect (W) high.

If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can

never be activated, and only the Software-protected mode (SPM) using the Block Protect

(BP1, BP0) bits in the Status Register, can be used.

Doc ID 11124 Rev 13

21/48

Instructions

M95512-W, M95512-R

6.5

Read from Memory Array (READ)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at

that address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 12. Read from Memory Array (READ) sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

15 14 13

MSB

3

2

1

0

D

Q

Data Out 1

Data Out 2

High Impedance

2

7

6

5

4

3

1

7

0

MSB

AI01793D

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Doc ID 11124 Rev 13

M95512-W, M95512-R

Instructions

6.6

Write to Memory Array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. The self-timed Write cycle triggered by the rising edge of Chip Select (S) continues for

a period t (as specified in Table 16 and Table 18), at the end of which the Write in Progress

W

(WIP) bit is reset to 0.

In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte. If,

though, Chip Select (S) continues to be driven low, as shown in Figure 14., the next byte of

input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address

counter are incremented. If the number of data bytes sent to the device exceeds the page

boundary, the internal address counter rolls over to the beginning of the page, and the

previous data there are overwritten with the incoming data. (The page size of these devices

is 128 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

●

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

●

if a Write cycle is already in progress

if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

●

if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note:

The self-timed write cycle t is internally executed as a sequence of two consecutive

W

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is

read as “0” and a programmed bit is read as “1”.

Figure 13. Byte Write (WRITE) sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

Instruction

16-Bit Address

Data Byte

15 14 13

3

2

1

0

7

6

5

4

3

2

0

1

D

Q

High Impedance

AI01795D

Doc ID 11124 Rev 13

23/48

Instructions

M95512-W, M95512-R

Figure 14. Page Write (WRITE) sequence

S

0

1

2

3

4

5

6

7

8

9

10

20 21 22 23 24 25 26 27 28 29 30 31

C

D

Instruction

16-Bit Address

Data Byte 1

15 14 13

3

2

1

0

7

6

5

4

3

2

0

1

S

C

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte N

7

6

5

4

3

2

0

7

6

5

4

3

2

0

6

5

4

3

2

0

1

D

AI01796D

24/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Instructions

6.7

Read Identification Page (available only in M95512-DR

devices)

The Identification Page (128 bytes) is an additional page which can be written and (later)

permanently locked in Read-only mode.

Reading this page is achieved with the Read Identification Page instruction (see Table 4).

The Chip Select signal (S) is first driven low, the bits of the instruction byte and address

bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits

[A15:A11] and [A9:A7] are Don't Care, and the data byte pointed to by [A6:A0] is shifted out

on Serial Data output (Q).

If Chip Select (S) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out. The number of bytes to

read in the ID page must not exceed the page boundary (e.g.: when reading the ID page

from location 90d, the number of bytes should be less than or equal to 38d, as the ID page

boundary is 128 bytes).

The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle. The first byte addressed can be any

byte within any page.

The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 15. Read Identification Page sequence

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Doc ID 11124 Rev 13

25/48

Instructions

M95512-W, M95512-R

6.8

Write Identification Page (available only in M95512-DR

devices)

The Identification Page (128 bytes) is an additional page which can be written and (later)

permanently locked in Read-only mode. Writing this page is achieved with the Write

Identification Page instruction (see Table 4), the Chip Select signal (S) is first driven low. The

bits of the instruction byte, address byte, and at least one data byte are then shifted in on

Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are

Don't Care, the [A6:A0] address bits define the byte address inside the identification page.

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for

a period t (as specified in Table 17 and Table 18), at the end of which the Write in Progress

W

(WIP) bit is reset to 0.

In the case of Figure 16, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte.

However, if Chip Select (S) continues to be driven low, as shown in Figure 16, the next byte

of input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal write cycle. Each time

a new data byte is shifted in, the least significant bits of the internal address counter are

incremented. If the number of data bytes sent to the device exceeds the page boundary, the

internal address counter rolls over to the beginning of the page, and the previous data there

are overwritten with the incoming data. (The page size of these devices is 128 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

●

if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a

Write Enable instruction)

●

if Status register bits (BP1, BP0) = (1, 1)

if a write cycle is already in progress

if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that was latched in)

●

if the Identification page is locked by the Lock Status bit

Figure 16. Write Identification Page sequence

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Doc ID 11124 Rev 13

M95512-W, M95512-R

Instructions

6.9

Read Lock Status (available only in M95512-DR devices)

The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is

locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip

Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted

in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.

The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is

at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)

continues to be driven low, the same data byte is shifted out. The read cycle is terminated by

driving Chip Select (S) high.

The instruction sequence is shown in Figure 17.

Figure 17. Read Lock Status sequence

3

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6.10

Lock ID (available only in M95512-DR devices)

The Lock ID instruction permanently locks the Identification Page in read-only mode. Before

this instruction can be accepted, a Write Enable (WREN) instruction must have been

executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the

instruction code, the address and a data byte on Serial Data input (D), and driving Chip

Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't

Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.

Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in

the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,

the Lock ID instruction is not executed.

Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write

cycle whose duration is t (specified in Table 17 and Table 18). The instruction sequence is

W

shown in Figure 18.

Doc ID 11124 Rev 13

27/48

Instructions

M95512-W, M95512-R

The instruction is not accepted, and so not executed, under the following conditions:

●

if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a

Write Enable instruction)

●

if Status register bits (BP1,BP0) = (1,1)

if a write cycle is already in progress

if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that was latched in)

●

if the Identification page is locked by the Lock Status bit

Figure 18. Lock ID sequence

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Doc ID 11124 Rev 13

M95512-W, M95512-R

ECC (error correction code) and write cycling

7

ECC (error correction code) and write cycling

The M95512-W, M95512-R and M95512-DR devices offer an ECC (error correction code)

logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a

result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation,

the ECC detects it and replaces it by the correct value. The read reliability is therefore much

improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes

making up the word. It is therefore recommended to write by words of 4 bytes in order to

benefit from the larger amount of Write cycles.

The M95512-W, M95512-R and M95512-DR devices are qualified at 1 million (1 000 000)

Write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.

8

Power-up and delivery state

8.1

Power-up state

After power-up, the device is in the following state:

●

Standby Power mode

●

Deselected (after Power-up, a falling edge is required on Chip Select (S) before any

instructions can be started).

●

Not in the Hold Condition

Write Enable Latch (WEL) is reset to 0

Write In Progress (WIP) is reset to 0

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous

power-down (they are non-volatile bits).

8.2

Initial delivery state

The device is delivered with the memory array set at all 1s (FFh). The Status Register Write

Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

Doc ID 11124 Rev 13

29/48

Maximum rating

M95512-W, M95512-R

9

Maximum rating

Stressing the device outside the ratings listed in Table 7 may cause permanent damage to

the device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 7.

Symbol

Absolute maximum ratings

Parameter

Min.

Max.

Unit

Ambient temperature with power applied

Storage temperature

–40

–65

130

150

°C

V

T_STG

T_LEAD

V_O

Lead temperature during soldering

Output voltage

see note ⁽¹⁾

–0.50

-

V_CC+0.6

V_I

Input voltage

6.5

5

V

I_OL

DC output current (Q = 0)

DC output current (Q = 1)

Supply voltage

mA

V

I_OH

–5

-

V_CC

–0.50

6.5

Electrostatic discharge voltage (human

body model)⁽²⁾

V_ESD

–3000

+3000

V

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 )

30/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

DC and AC parameters

10

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristic tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Table 8.

Symbol

Operating conditions (M95512-W device grade 6)

Parameter Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature (device grade 6)

2.5

5.5

85

V

–40

°C

Table 9.

Symbol

Operating conditions (M95512-W device grade 3)

Parameter Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature (device grade 6)

2.5

5.5

V

–40

125

°C

Table 10. Operating conditions (M95512-R and M95512-DR)

Symbol

Parameter

Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature

1.8

5.5

85

V

–40

°C

Table 11. AC measurement conditions

Symbol

Parameter

Min.

Max.

Unit

C_L

Load capacitance

30

pF

ns

V

Input Rise and Fall times

50

Input Pulse voltages

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

Input and output timing reference voltages

V

Figure 19. AC measurement I/O waveform

Input Levels

Input and Output

Timing Reference Levels

0.8V

CC

0.7V

CC

0.3V

CC

0.2V

CC

AI00825B

Doc ID 11124 Rev 13

31/48

DC and AC parameters

M95512-W, M95512-R

(1)

Table 12. Capacitance

Symbol

Parameter

Test condition

Min.

Max.

Unit

C_OUT

Output capacitance (Q)

Input capacitance (D)

V_OUT= 0 V

V_IN= 0 V

8

6

pF

C_IN

Input capacitance (other pins)

1. Not 100% tested.

(1)

Table 13. DC characteristics (current M95512-W products)

Test conditions: V_CC= 2.5 to 5.5 V at

Symbol

Parameter

T_A= –40 to 85 °C (device grade 6)

Min.

Max.

Unit

or T_A= –40 to 125 °C (device grade 3)

I_LI

Input leakage current

Output leakage current

V_IN= V_SSor V_CC

2

µA

I_LO

S = V_CC, V_OUT= V_SSor V_CC

C = 0.1V_CC/0.9V_CCat 5 MHz,

V_CC= 2.5 V, Q = open

3

5

6

5

mA

µA

I_CC

Supply current (Read)

Supply current (Write)

C = 0.1V_CC/0.9V_CCat 5 MHz, V_CC= 5

V, Q = open

During t_W, S = V_CC

,

(2)

I_CC0

2.5 V < V_CC< 5.5 V

Supply current

(Standby Power mode)

S = V_CC, V_IN= V_SSor V_CC

,

I_CC1

2.5 V < V_CC< 5.5 V

V_IL

Input low voltage

Input high voltage

–0.45 0.3 V_CC

0.7 V_CCV_CC+1

V

V_IH

V

_CC= 2.5 V and I_OL= 1.5 mA or

V_CC= 5 V and I_OL= 2 mA

V_OL

V_OH

Output low voltage

Output high voltage

0.4

V

V_CC= 2.5 V and I_OH= –0.4 mA or

V_CC= 5 V and I_OH= –2 mA

0.8 V_CC

1. Current products are identified by AB process letters AB.

2. Characterized value, not tested in production.

32/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

DC and AC parameters

(1)

Table 14. DC characteristics (new M95512-W products)

Test conditions: V_CC= 2.5 to 5.5 V,

Symbol

Parameter

Min.

Max.

Unit

T_A= –40 to 85 °C

I_LI

Input leakage current

Output leakage current

V_IN= V_SSor V_CC

2

µA

I_LO

S = V_CC, V_OUT= V_SSor V_CC

C = 0.1V_CC/0.9V_CCat 10 MHz,

V_CC= 2.5 V, Q = open

4

mA

I_CC

Supply current (Read)

C = 0.1V_CC/0.9V_CCat 20 MHz, V_CC= 5 V,

Q = open

8

6

5

mA

µA

(2)

I_CC0

Supply current (Write)

During t_W, S = V_CC, 2.5 V < V_CC< 5.5 V

Supply current

(Standby Power mode)

S = V_CC, V_IN= V_SSor V_CC,

I_CC1

2.5 V < V_CC< 5.5 V

V_IL

V_IH

Input low voltage

Input high voltage

–0.45

0.3 V_CC

V_CC+1

V

0.7 V_CC

V

_CC= 2.5 V and I_OL= 1.5 mA or

V_OL

V_OH

Output low voltage

Output high voltage

0.4

V

V_CC= 5 V and I_OL= 2 mA

V_CC= 2.5 V and I_OH= –0.4 mA or

V_CC= 5 V and I_OH= –2 mA

0.8 V_CC

1. New products are identified by process letter K.

2. Characterized value, not tested in production.

Table 15. DC characteristics (current and new M95512-R and M95512-DR products)

Test conditions:

Symbol

Parameter

Min

Max

Unit

V_CC= 1.8 to 5.5 V, T_A= –40 to 85 °C

I_LI

Input leakage current

Output leakage current

V_IN= V_SSor V_CC

2

µA

I_LO

S = V_CC, V_OUT= V_SSor V_CC

C = 0.1V_CC/0.9V_CCat 2 MHz, V_CC= 1.8 V,

Q = open⁽¹⁾

1

mA

I_CC

Supply current (Read)

C = 0.1V_CC/0.9V_CCat 5 MHz, V_CC= 1.8 V,

Q = open⁽²⁾

2.5

3

mA

µA

(3)

I_CC0

Supply current (Write)

During t_W, S = V_CC, 1.8 V < V_CC< 2.5 V

Supply current (Standby

Power mode)

S = V_CC, V_IN= V_SSor V_CC,

I_CC1

3

1.8 V < V_CC< 2.5 V

V_IL

V_IH

Input low voltage

Input high voltage

Output low voltage

Output high voltage

–0.45

0.3 V_CC

V_CC+1

0.3

V

0.7 V_CC

V_OL

V_OH

I_OL= 0.15 mA, V_CC= 1.8 V

I_OH= –0.1 mA, V_CC= 1.8 V

0.8 V_CC

1. Current products are identified by process letters AB.

2. New products are identified by process letter K.

3. Characterized value, not tested in production.

Doc ID 11124 Rev 13

33/48

DC and AC parameters

M95512-W, M95512-R

(1)

Table 16. AC characteristics (current M95512-W products)

Test conditions:

V_CC= 2.5 to 5.5 V at T_A= –40 to 85 °C (device grade 6) or T_A= –40 to 125 °C (device grade 3)

Symbol

Alt.

Parameter

Min.

Max.

Unit

f_C

f_SCKClock frequency

D.C.

90

5

MHz

ns

µs

ns

ms

t_SLCH

t_SHCH

t_SHSL

t_CHSH

t_CHSL

t_CSS1S active setup time

t_CSS2S not active setup time

t_CSS deselect time

90

100

90

t_CSHS active hold time

S not active hold time

t_CLHClock high time

t_CLLClock low time

90

(2)

t_CH

90

(2)

t_CL

90

(3)

t_CLCH

t_RC

t_FC

Clock rise time

Clock fall time

1

(3)

t_CHCL

t_DVCH

t_CHDX

t_HHCH

t_HLCH

t_CLHL

t_CLHH

t_DSUData in setup time

20

30

70

40

0

t_DH

Data in hold time

Clock low hold time after HOLD not active

Clock low hold time after HOLD active

Clock low setup time before HOLD active

Clock low setup time before HOLD not active

0

(3)

t_SHQZ

t_DISOutput disable time

100

60

t_CLQV

t_CLQX

t_V

Clock low to output valid

Output hold time

t_HO

t_RO

t_FO

t_LZ

0

(3)

t_QLQH

Output rise time

50

100

5

(3)

t_QHQL

Output fall time

t_HHQV

HOLD high to output valid

HOLD low to output High-Z

(3)

t_HLQZ

t_HZ

t_W

t_WCWrite time

1. Current products are identified by process letters AB.

2. t_CH+ t_CLmust never be less than the shortest possible clock period, 1 / f_C(max)

3. Value guaranteed by characterization, not 100% tested in production.

34/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

DC and AC parameters

(1)

Table 17. AC characteristics (New M95512-W products)

Test conditions: V_CC= 2.5 to 5.5 V, T_A= –40 to 85 °C

Min.

Max.

Min.

Max.

Symbol

Alt.

Parameter

Unit

2.5 V to 5.5 V

4.5 V to 5.5 V

f_C

f_SCKClock frequency

D.C.

30

40

30

45

10

D.C.

15

20

15

20

MHz

ns

µs

ns

ms

t_SLCH

t_SHCH

t_SHSL

t_CHSH

t_CHSL

t_CSS1S active setup time

t_CSS2S not active setup time

t_CS

S deselect time

t_CSHS active hold time

S not active hold time

t_CLHClock high time

t_CLLClock low time

(2)

t_CH

(2)

t_CL

(3)

t_CLCH

t_RC

t_FC

Clock rise time

Clock fall time

2

(3)

t_CHCL

t_DVCH

t_CHDX

t_HHCH

t_HLCH

t_CLHL

t_CLHH

t_DSUData in setup time

10

30

0

5

10

15

0

t_DH

Data in hold time

Clock low hold time after HOLD not active

Clock low hold time after HOLD active

Clock low setup time before HOLD active

Clock low setup time before HOLD not active

0

(3)

t_SHQZ

t_DISOutput disable time

40

20

t_CLQV

t_V

Clock low to output valid

Output hold time

t_CLQX

t_HO

t_RO

t_FO

t_LZ

0

(3)

t_QLQH

Output rise time

40

5

20

5

(3)

t_QHQL

Output fall time

t_HHQV

HOLD high to output valid

HOLD low to output High-Z

(3)

t_HLQZ

t_HZ

t_W

t_WCWrite time

1. New products are identified by process letter K.

2. t_CH+ t_CLmust never be less than the shortest possible clock period, 1 / f_C(max)

3. Value guaranteed by characterization, not 100% tested in production.

Doc ID 11124 Rev 13

35/48

DC and AC parameters

M95512-W, M95512-R

Table 18. AC characteristics (current and new M95512-R and M95512-DR products)

Test conditions: V_CC= 1.8 to 5.5 V, T_A= –40 to 85 °C

Min.

Max.

Min.

Max.

Symbol

Alt.

Parameter

Unit

Current⁽¹⁾products New products⁽²⁾

f_C

f_SCKClock frequency

D.C.

200

2

D.C.

60

90

60

80

5

MHz

ns

µs

ns

ms

t_SLCH

t_SHCH

t_SHSL

t_CHSH

t_CHSL

t_CSS1S active setup time

t_CSS2S not active setup time

t_CS

S deselect time

t_CSHS active hold time

S not active hold time

t_CLHClock high time

t_CLLClock low time

(3)

t_CH

(3)

t_CL

(4)

t_CLCH

t_RC

t_FC

Clock rise time

Clock fall time

1

2

(4)

t_CHCL

t_DVCH

t_CHDX

t_HHCH

t_HLCH

t_CLHL

t_CLHH

t_DSUData in setup time

40

50

140

90

0

20

60

0

t_DH

Data in hold time

Clock low hold time after HOLD not active

Clock low hold time after HOLD active

Clock low setup time before HOLD active

Clock low setup time before HOLD not active

0

(4)

t_SHQZ

t_DISOutput disable time

t_VClock low to output valid

t_HOOutput hold time

250

150

80

t_CLQV

t_CLQX

0

(4)

t_QLQH

t_RO

t_FO

t_LZ

Output rise time

100

250

5

80

5

(4)

t_QHQL

Output fall time

t_HHQV

HOLD high to output valid

HOLD low to output High-Z

(4)

t_HLQZ

t_HZ

t_W

t_WCWrite time

1. Current products are identified by process letters “AB”.

2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values

defined in this table (when V_CC= 1.8 V) and the AC parameter values defined in Table 17 (when V_CC= 2.5 V or V_CC

5.0 V).

=

3. t_CH+ t_CLmust never be less than the shortest possible clock period, 1 / f_C(max)

4. Value guaranteed by characterization, not 100% tested in production.

36/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Figure 20. Serial input timing

DC and AC parameters

tSHSL

tSHCH

S

C

tCHSL

tSLCH

tCH

tCHSH

tDVCH

tCHCL

tCHDX

tCL

tCLCH

MSB IN

LSB IN

D

Q

High impedance

AI01447d

Figure 21. Hold timing

S

tHLCH

tCLHL

tHHCH

C

tCLHH

tHHQV

tHLQZ

Q

HOLD

AI01448c

Doc ID 11124 Rev 13

37/48

DC and AC parameters

M95512-W, M95512-R

Figure 22. Serial output timing

S

tCH

tSHSL

C

tCLQV

tCLQX

tCLCH

tCHCL

tCL

tSHQZ

Q

D

tQLQH

tQHQL

ADDR

LSB IN

AI01449f

38/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Package mechanical data

11

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 23. SO8N – 8 lead plastic small outline, 150 mils body width, package outline

h x 45˚

A2

A

c

ccc

b

e

0.25 mm

D

GAUGE PLANE

k

8

1

E1

E

L

A1

L1

SO-A

1. Drawing is not to scale.

Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

1.75

0.25

0.0689

0.0098

0.10

1.25

0.28

0.17

0.0039

0.0492

0.011

0.48

0.23

0.10

5.00

6.20

4.00

–

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

-

c

0.0067

ccc

D

4.90

6.00

3.90

1.27

4.80

5.80

3.80

–

0.1929

0.2362

0.1535

0.05

0.189

0.2283

0.1496

-

E

E1

e

h

0.25

0°

0.50

8°

0.0098

0°

0.0197

8°

k

L

0.40

1.27

0.0157

0.05

L1

1.04

0.0409

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 11124 Rev 13

39/48

Package mechanical data

M95512-W, M95512-R

Figure 24. TSSOP8 – 8 lead thin shrink small outline, package outline

D

8

5

c

E1

E

1

4

α

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

1. Drawing is not to scale.

2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

A2

b

1.200

0.150

1.050

0.300

0.200

0.100

3.100

–

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.1220

–

0.050

0.800

0.190

0.090

0.0020

0.0315

0.0075

0.0035

1.000

0.0394

c

CP

D

3.000

0.650

6.400

4.400

0.600

1.000

2.900

–

0.1181

0.0256

0.2520

0.1732

0.0236

0.0394

0.1142

–

e

E

6.200

4.300

0.450

6.600

4.500

0.750

0.2441

0.1693

0.0177

0.2598

0.1772

0.0295

E1

L

L1



0°

8

8°

0°

8

8°

N

1. Values in inches are converted from mm and rounded to 4 decimal digits.

40/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Package mechanical data

Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3 mm, package outline

e

b

D

L1

L3

E

E2

L

A

D2

ddd

A1

UFDFPN-01

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be

connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 21. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3 .mm, package mechanical data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

A1

b

0.55

0.02

0.25

2.00

1.60

0.50

0.00

0.20

1.90

1.50

0.60

0.05

0.30

2.10

1.70

0.08

3.10

0.30

–

0.0217

0.0008

0.0098

0.0787

0.0630

0.0197

0

0.0236

0.0020

0.0118

0.0827

0.0669

0.0031

0.1220

0.0118

–

0.0079

0.0748

0.0591

D

D2

ddd

E

3.00

0.20

0.50

0.45

2.90

0.10

–

0.1181

0.0079

0.0197

0.0177

0.1142

0.0039

–

E2

e

L

0.40

0.50

0.15

0.0157

0.0197

0.0059

L1

L3

0.30

0.0118

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 11124 Rev 13

41/48

Package mechanical data

M95512-W, M95512-R

Figure 26. WLCSP-R – 8-bump wafer-length chip-scale package outline

e1

e3

D

X

Y

Orientation reference

e2

G

A

B

C

D

E

Detail A

Orientation reference

e

E

aaa

1

2

3

Wafer back side

A2

A

F

Bump side

Side view

Bump

A1

Detail A

rotated by 90 °C

eee Z

Z

b

Seating plane

ME_1Cc

1. Drawing is not to scale.

Table 22. WLCSP-R – 8-bump wafer-length chip-scale package mechanical data

millimeters

inches⁽¹⁾

Symbol

Typ

Min

Max

Typ

Min

Max

A

0.580

0.230

0.350

0.322

1.433

1.901

1.000

0.866

0.500

0.433

0.284

0.453

8

0.490

0.670

0.0228

0.0091

0.0138

0.0127

0.0564

0.0748

0.0394

0.0341

0.0197

0.0170

0.0112

0.0178

8

0.0193

0.0264

A1

A2

b⁽²⁾

D

1.548

2.016

0.0609

0.0794

E

e

e1

e2

e3

F

G

N (number of terminals)

aaa

eee

0.110

0.060

0.0043

0.0024

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Measured at the maximum bump diameter parallel to primary datum Z.

42/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Part numbering

12

Part numbering

Table 23. Ordering information scheme

Example:

M95512

–

W MN

6

T

P /AB

Device type

M95 = SPI serial access EEPROM

Device function

512 = 512 Kbit (65536 × 8)

512-D = 512 Kbit (65536 × 8) plus Identification page

Operating voltage

W = V_CC= 2.5 V to 5.5 V

R = V_CC= 1.8 V to 5.5 V

Package

MN = SO8 (150 mil width)

DW = TSSOP8 (169 mil width)

MB = UFDFPN8 (MLP8)

CS = WLCSP

Device grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3 = Device tested with high reliability certified flow⁽¹⁾

Automotive temperature range (–40 to 125 °C)

.

Option

blank = Standard packing

T = Tape and reel packing

Plating technology

P or G = ECOPACK^®(RoHS compliant)

Process⁽²⁾

/AB = F8L

/K = F8H

1. ST strongly recommends the use of the automotive grade devices for use in an automotive environment.

The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

Doc ID 11124 Rev 13

43/48

Part numbering

M95512-W, M95512-R

2. The process letters only appear in the product ordering codes of device grade 3 devices. For other

devices, it is only given here as an indication of how to differentiate current from new products.

To identify current from new devices, please contact your nearest ST sales office.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

Table 24. Available M95512 products (package, voltage range, temperature grade)

M95512-W

2.5 V to 5.5 V

M95512-R

1.8 V to 5.5 V

Package

SO8 (MN)

Range 6, range 3

Range 6

TSSOP (DW)

UFDFPN8 (MB)

WLCSP (CS)

Range 6

-

Table 25. Available M95512-DR products (package, voltage range, temperature

grade)

M95512-DR

1.8 V to 5.5 V

Package

SO8 (MN)

Range 6

TSSOP (DW)

44/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Revision history

13

Revision history

Table 26. Document revision history

Date

Revision

Changes

Jan-1999

1.0

Document written

Document reformatted using the new template

Voltage range -S added, and -R removed

Instruction Sequence illustrations updated

13-Feb-2002

2.0

Announcement made of planned upgrade to 10 MHz clock for the 5V, –40

to 85°C, range

Table of contents, and Pb-free options added. V_IL(min) improved to -

0.45V. Voltage range -R added, and -S removed

05-Dec-2003

02-Apr-2004

3.0

4.0

Old versions of document completely replaced by one rewritten from

M95256

AC and DC characteristics tables updated with the performance data of

the new device identified with the process letter “A”.

Table 1., Product List added. AEC-Q100-002 compliance. Device Grade

information clarified. t_HHQX, t_CHHLand t_CHHHcorrected to t_HHQV, t_CLHLand

t_CLHH, respectively.

03-Jan-2005

30-Jun-2005

5.0

6.0

M95512 part number with 4.5V to 5.5V operating voltage range removed

(related tables removed). Document status changed to Preliminary Data.

Updated Figure 4: Bus master and memory devices on the SPI bus and

Figure 21: Hold timing. Power On Reset information clarified. Protected

Array Addresses modified in Table 2: Write-protected block size. Ambient

Operating Temperature value added in Table 7: Absolute maximum

ratings. Supply Current (I_CC) value modified for 10 MHz in Table 13: DC

characteristics (current M95512-W products). All values modified in

Table 18: AC characteristics (current and new M95512-R and M95512-DR

products). Document status changed to Datasheet.

Doc ID 11124 Rev 13

45/48

Revision history

Table 26. Document revision history (continued)

M95512-W, M95512-R

Date

Revision

Changes

Document reformatted. Packages are ECOPACK® compliant.

10 MHz frequency removed. VCC supply voltage and VSS ground

descriptions added. Figure 4: Bus master and memory devices on the SPI

bus modified and explanatory paragraph added. Power-up and Power On

Reset paragraphs replaced by Section 4.1: Supply voltage (VCC).

Section 7: ECC (error correction code) and write cycling added.

T_Amax modified in Table 8: Operating conditions (M95512-W device

grade 6).

Note modified below Table 12: Capacitance.

C_Lmodified in and Table 11: AC measurement conditions.

V_ILmax and I_CC0test conditions modified in Table 15: DC characteristics

(current and new M95512-R and M95512-DR products).

06-Feb-2007

7

I_CCmodified in Table 13: DC characteristics (current M95512-W

products), I_CC0added to Table 13 and Table 15: DC characteristics

(current and new M95512-R and M95512-DR products) modified.

Table 18: AC characteristics (current and new M95512-R and M95512-DR

products) modified.

t_SHQZend timing line moved back in Figure 22: Serial output timing.

SO8N package specifications updated (see Figure 23 and Table 19).

Blank removed below Plating technology in Table 23: Ordering information

scheme.

The device endurance is specified at more than 1 000 000 (1 million)

cycles (corrected on cover page).

05-Jun-2007

8

M95512-W is now available in the device grade 3 (automotive temperature

range), see Table 8 on page 31).

Section 4.1: Supply voltage (VCC) on page 12 updated.

Section 6.4: Write Status Register (WRSR) on page 20 and Section 6.6:

Write to Memory Array (WRITE) on page 23 clarified.

I_CC0modified in Table 13: DC characteristics (current M95512-W

products).

03-Jul-2008

9

Figure 20: Serial input timing, Figure 21: Hold timing and Figure 22: Serial

output timing updated.

Package mechanical data values in inches are calculated from the

millimeter values and rounded to four decimal digits (see Section 11:

Package mechanical data).

Table 24: Available M95512 products (package, voltage range,

temperature grade) added. Small text changes.

M95512-DR part number added (see Table 25: Available M95512-DR

products (package, voltage range, temperature grade)).

14-Apr-2009

10

New M95512-W, M95512-R and M95512-DR products operating at up to

20 MHz added (preliminary data).

UFDFPN8 package added (see Section 11: Package mechanical data).

46/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

Table 26. Document revision history (continued)

Revision history

Date

Revision

Changes

V_ESDmodified in Table 7: Absolute maximum ratings.

Updated:

– Section 6.7: Read Identification Page (available only in M95512-DR

devices)

11-May-2009

11

– Section 6.8: Write Identification Page (available only in M95512-DR

devices)

– Section 6.9: Read Lock Status (available only in M95512-DR devices)

– Section 6.10: Lock ID (available only in M95512-DR devices)

Data related to new products are no longer preliminary.

28-Aug-2009

12

Note 2 updated in Table 18: AC characteristics (current and new M95512-

R and M95512-DR products).

WLCSP package added.

M95512-DR added.

Updated:

– Section 1: Description

– Section 6.7: Read Identification Page (available only in M95512-DR

devices)

14-Sep-2010

13

– Section 6.8: Write Identification Page (available only in M95512-DR

devices)

– Section 6.9: Read Lock Status (available only in M95512-DR devices),

Table 7: Absolute maximum ratings

Inserted Caution under Table 1: Signal names

Added Note under Figure 24: TSSOP8 – 8 lead thin shrink small outline,

package outline

Doc ID 11124 Rev 13

47/48

M95512-W, M95512-R

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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48/48

Doc ID 11124 Rev 13


型号：	M95512-WMN6TP/K
厂家：	ST
描述：	512 Kbit serial SPI bus EEPROM with high-speed clock 512 Kbit的串行SPI总线的EEPROM与高速时钟存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件：	总48页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M95512-WMN6TP/K [STMICROELECTRONICS]

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