MM24164BN3T [STMICROELECTRONICS]

16 Kbit Serial I2C BUS EEPROM; 16 Kbit的串行I²C总线EEPROM


型号：	MM24164BN3T
厂家：	ST
描述：	16 Kbit Serial I2C BUS EEPROM 16 Kbit的串行I²C总线EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总21页 (文件大小：137K)
中文：	中文翻译
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M24164

16 Kbit Serial I²C Bus EEPROM

with 1 Inverting and 2 Non-Inverting Chip Enable Lines

FEATURES SUMMARY

■ Two Wire I C Serial Interface

Figure 1. Packages

Supports 400 kHz Protocol

■ Single Supply Voltage:

– 4.5V to 5.5V for M24164

– 2.5V to 5.5V for M24164-W

■ Write Control Input

■ BYTE and PAGE WRITE (up to 16 Bytes)

■ RANDOM and SEQUENTIAL READ Modes

■ Self-Timed Programming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ More than 1 Million Erase/Write Cycles

■ More than 40 Year Data Retention

PDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

October 2001

1/21

M24164

SUMMARY DESCRIPTION

The M24164 is a 16 Kbit (2048 x 8) electrically

erasable programmable memory (EEPROM) ac-

cessed by an I C-compatible bus.

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Figure 2. Logic Diagram

Figure 3. DIP Connections

M24164

E0-E2

SDA

M24164

SCL

SDA

AI02265B

AI02264

Figure 4. SO Connections

Table 1. Signal Names

E0, E1, E2

SDA

Chip Enable

Serial Data

Serial Clock

Write Control

Supply Voltage

Ground

M24164

SCL

SDA

AI02266B

These devices are compatible with a two-wire se-

rial interface that uses a bi-directional data bus

and serial clock. By setting the three chip enables

(E0, E1, E2) appropriately, up to eight 16 Kbit de-

vices can be attached to the same I C bus, and

selected individually.

These devices behave as slave devices, with all

memory operations synchronized by the serial

clock. Read and Write operations are initiated by a

Start condition, generated by the bus master. The

Start condition is followed by a Device Select

Code and RW bit (as described in Table 2), termi-

nated by an acknowledge bit.

Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until V

threshold value, and all operations are disabled –

the device will not respond to any command. In the

same way, when V

voltage, below the POR threshold value, all oper-

ations are disabled and the device will not respond

has reached the POR

drops from the operating

to any command. A stable and valid V

applied before applying any logic signal.

must be

When writing data to the memory, the device in-

serts an acknowledge bit during the 9 bit time,

2/21

M24164

SIGNAL DESCRIPTION

Serial Clock (SCL)

This input signal is used to strobe all data in and

out of the device. In applications where this signal

is used by slave devices to synchronize the bus to

a slower clock, the bus master must have an open

drain output, and a pull-up resistor must be con-

ure 4 indicates how the value of the pull-up resistor

can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that

is to be looked for on three bits (b6, b5, b4) of the

7-bit Device Select Code. These inputs must be

nected from Serial Clock (SCL) to V . (Figure 4

tied to V

Code.

or V , to establish the Device Select

indicates how the value of the pull-up resistor can

be calculated). In most applications, though, this

method of synchronization is not employed, and

so the pull-up resistor is not necessary, provided

that the bus master has a push-pull (rather than

open drain) output.

Write Control (WC)

This input signal is useful for protecting the entire

contents of the memory from inadvertent write op-

erations. Write operations are disabled to the en-

tire memory array when Write Control (WC) is

driven High. When unconnected, the signal is in-

Serial Data (SDA)

This bi-directional signal is used to transfer data in

or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open

collector signals on the bus. A pull up resistor must

ternally read as V , and Write operations are al-

lowed.

When Write Control (WC) is driven High, Device

Select and Address bytes are acknowledged,

Data bytes are not acknowledged.

be connected from Serial Data (SDA) to V . (Fig-

Figure 5. Maximum R Value versus Bus Capacitance (C

) for an I C Bus

BUS

SDA

MASTER

BUS

SCL

fc = 100kHz

fc = 400kHz

BUS

100

(pF)

1000

BUS

AI01665

3/21

M24164

DEVICE OPERATION

The device supports the I C protocol. This is sum-

marized in Figure 2. Any device that sends data on

to the bus is defined to be a transmitter, and any

device that reads the data to be a receiver. The

device that controls the data transfer is known as

the bus master, and the other as the slave device.

A data transfer can only be initiated by the bus

master, which will also provide the serial clock for

synchronization. The M24164 device is always a

slave in all communication.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change only when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus master must initiate

a Start condition. Following this, the bus master

sends eight bits, on Serial Data (SDA), most signif-

icant bit first. These consist of the 7-bit Device Se-

lect Code, and the Read/Write bit (RW), as shown

in Table 2. This last bit is set to 1 for Read, and 0

for Write operations.

The Device Select Code contains the three most

significant bits of the address within the memory

(A10, A9, A8), and a 3-bit Chip Enable “Address”

(E2, E1, E0).

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminates communica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a Write command triggers the internal EE-

PROM Write cycle.

When the Device Select Code is received on Seri-

al Data (SDA), the device only responds if the Chip

Enable Address is the same as the value on the

Chip Enable (E0, E2, and the inverse of E1) in-

puts. Up to eight devices can be connected on the

same bus, giving a total memory capacity of

128 Kbits, 16 KBytes.

Acknowledge Bit (ACK)

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9 bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

(SDA) after sending eight bits of data. During the

clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Table 2. Device Select Code

Device

Type

Chip Enable Address

Most Significant Address Bits

Identifier

Device Select Code

A10

Note: 1. The most significant bit, b7, is sent first.

4/21

M24164

Figure 6. I C Bus Protocol

SCL

SDA

Input

SDA

Change

START

Condition

STOP

Condition

SCL

SDA

ACK

MSB

START

Condition

SCL

SDA

MSB

ACK

STOP

Condition

AI00792B

Table 3. Operating Modes

Mode

RW bit

Bytes

Initial Sequence

START, Device Select, RW = 1

Current Address Read

Random Address Read

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Similar to Current or Random Address Read

START, Device Select, RW = 0

Sequential Read

Byte Write

≥ 1

V_IL

Page Write

≤ 16

START, Device Select, RW = 0

Note: 1. X = V_IHor V_IL.

5/21

M24164

Figure 7. Write Mode Sequences with WC=1 (data write inhibited)

ACK

NO ACK

DATA IN

Byte Write

DEV SEL

BYTE ADDR

R/W

ACK

NO ACK

DATA IN 3

Page Write

DEV SEL

BYTE ADDR

DATA IN 1 DATA IN 2

R/W

WC (cont'd)

NO ACK

Page Write

(cont'd)

DATA IN N

AI02803C

A Stop condition at any other time slot does not

trigger the internal Write cycle.

Write Operations

Following a Start condition the bus master sends

a Device Select Code with the RW bit reset to 0.

The device acknowledges this, as shown in Figure

8, and waits for an address byte. The device re-

sponds to the address byte with an acknowledge

bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write

Control (WC) is driven High. Any Write instruction

with Write Control (WC) driven High (during a pe-

riod of time from the Start condition until the end of

the address byte) will not modify the memory con-

tents, and the accompanying data bytes are not

acknowledged, as shown in Figure 7.

During the internal Write cycle, Serial Data (SDA)

is disabled internally, and the device does not re-

spond to any requests.

Byte Write

After the Device Select code and the address byte,

the bus master sends one data byte. If the ad-

dressed location is Write-protected, by Write Con-

trol (WC) being driven High, the device replies with

NoAck, and the location is not modified. If, instead,

the addressed location is not Write-protected, the

device replies with Ack. The bus master termi-

nates the transfer by generating a Stop condition,

as shown in Figure 8.

When the bus master generates a Stop condition

Page Write

immediately after the Ack bit (in the “10 bit” time

The Page Write mode allows up to 16 bytes to be

written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

6/21

M24164

that is, the most significant memory address bits

are the same. If more bytes are sent than will fit up

to the end of the row, a condition known as ‘roll-

over’ occurs. This should be avoided, as data

starts to become overwritten in an implementation

dependent way.

Write Control (WC) is Low. If Write Control (WC) is

High, the contents of the addressed memory loca-

tion are not modified, and each data byte is fol-

lowed by a NoAck. After each byte is transferred,

the internal byte address counter (the 4 least sig-

nificant address bits only) is incremented. The

transfer is terminated by the bus master generat-

ing a Stop condition.

The bus master sends from 1 to 16 bytes of data,

each of which is acknowledged by the device if

Figure 8. Write Mode Sequences with WC=0 (data write enabled)

ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

R/W

ACK

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

DATA IN 3

R/W

WC (cont'd)

ACK

PAGE WRITE

(cont'd)

DATA IN N

AI02804

7/21

M24164

Figure 9. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

First byte of instruction

with RW = 0 already

decoded by the device

YES

Operation is

Addressing the

Memory

YES

Send Address

and Receive ACK

ReSTART

START

YES

STOP

Condition

DATA for the

WRITE Operation

DEVICE SELECT

with RW = 1

Continue the

Random READ Operation

WRITE Operation

AI01847C

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first byte

of the new instruction).

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon-

nects itself from the bus, and writes a copy of the

data from its internal latches to the memory cells.

– Step 2: if the device is busy with the internal

Write cycle, no Ack will be returned and the bus

master goes back to Step 1. If the device has

terminated the internal Write cycle, it responds

with an Ack, indicating that the device is ready

to receive the second part of the instruction (the

first byte of this instruction having been sent

during Step 1).

The maximum Write time (t ) is shown in Tables

11 and 12, but the typical time is shorter. To make

use of this, a polling sequence can be used by the

bus master.

The sequence, as shown in Figure 9, is:

– Initial condition: a Write cycle is in progress.

8/21

M24164

Figure 10. Read Mode Sequences

ACK

NO ACK

DATA OUT

CURRENT

ADDRESS

READ

DEV SEL

R/W

ACK

NO ACK

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

BYTE ADDR

DEV SEL *

R/W

ACK

NO ACK

DATA OUT N

SEQUENTIAL

CURRENT

READ

DEV SEL

DATA OUT 1

R/W

ACK

SEQUENTIAL

RANDOM

READ

DEV SEL *

BYTE ADDR

DEV SEL * DATA OUT 1

R/W

ACK

NO ACK

DATA OUT N

AI01942

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.

ter must not acknowledge the byte, and terminates

the transfer with a Stop condition.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

Random Address Read

A dummy Write is performed to load the address

into the address counter (as shown in Figure 10)

but without sending a Stop condition. Then, the

bus master sends another Start condition, and re-

peats the Device Select Code, with the RW bit set

to 1. The device acknowledges this, and outputs

the contents of the addressed byte. The bus mas-

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read operation, following a Start

condition, the bus master only sends a Device Se-

lect Code with the RW bit set to 1. The device ac-

knowledges this, and outputs the byte addressed

by the internal address counter. The counter is

then incremented. The bus master terminates the

9/21

M24164

transfer with a Stop condition, as shown in Figure

10, without acknowledging the byte.

Sequential Read

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 10.

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, for an acknowledgment during the

9 bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device termi-

nates the data transfer and switches to its Stand-

by mode.

The output data comes from consecutive address-

es, with the internal address counter automatically

10/21

M24164

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 4. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

Unit

T_STG

Storage Temperature

–65

150

°C

PDIP: 10 seconds

260

235

T_LEAD

Lead Temperature during Soldering

°C

SO: 20 seconds (max)

V_IO

V_CC

V_ESD

Input or Output range

Supply Voltage

–0.6

–0.3

6.5

–4000

4000

Electrostatic Discharge Voltage (Human Body model)

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

11/21

M24164

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 5. Operating Conditions (M24164)

Symbol

Parameter

Min.

4.5

Max.

5.5

Unit

Supply Voltage

Ambient Operating Temperature

T_A

°C

Table 6. Operating Conditions (M24164-W)

Symbol

Parameter

Min.

2.5

Max.

5.5

Unit

Supply Voltage

Ambient Operating Temperature

T_A

°C

Table 7. AC Measurement Conditions

Symbol

Parameter

Min.

Max.

Unit

Load Capacitance

Input Rise and Fall Times

Input Pulse Voltages

0.2V to 0.8V

0.3V to 0.7V

Input and Output Timing Reference Voltages

Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 11. AC Measurement I/O Waveform

0.8V

0.7V

0.3V

0.2V

AI00825

12/21

M24164

Table 8. Capacitance

1,2

Symbol

C_IN

Test Condition

Min.

Max.

Unit

Parameter

Input Capacitance (SDA)

C_IN

Input Capacitance (other pins)

Pulse width ignored

(Input Filter on SCL and SDA)

t_NS

Single glitch

100

Note: 1. T = 25 °C, f = 400 kHz

2. Sampled only, not 100% tested.

Table 9. DC Characteristics (M24164)

Test Condition

(in addition to those in Table 5)

Symbol

Parameter

Min.

Max.

Unit

Input Leakage Current

(SCL, SDA)

I_LI

V_IN= V_SSor V_CC

± 2

µA

I_LO

I_CC

Output Leakage Current

Supply Current

0 V ≤ V_OUT≤ V_CC,SDA in Hi-Z

± 2

µA

_CC=5V, f =400kHz (rise/fall time < 30ns)

I_CC1

V_IN= V_SSor V_CC, V_CC= 5 V

Stand-by Supply Current

Input Low Voltage

(E0, E1, E2, SCL, SDA)

V_IL

V_IH

– 0.3

0.3V_CC

V_CC+1

Input High Voltage

(E0, E1, E2, SCL, SDA)

0.7V_CC

V_IL

V_IH

V_OL

Input Low Voltage (WC)

Input High Voltage (WC)

Output Low Voltage

– 0.3

0.5

V_CC+1

0.4

0.7V_CC

I_OL= 3 mA, 4.5 V ≤ V_CC≤ 5.5 V

Table 10. DC Characteristics (M24164-W)

Test Condition

(in addition to those in Table 6)

Symbol

Parameter

Min.

Max.

Unit

Input Leakage Current

(SCL, SDA)

I_LI

V_IN= V_SSor V_CC

± 2

µA

I_LO

I_CC

Output Leakage Current

Supply Current

0 V ≤ V_OUT≤ V_CC,SDA in Hi-Z

± 2

µA

_CC=2.5V, f =400kHz (rise/fall time < 30ns)

I_CC1

V_IN= V_SSor V_CC, V_CC= 5 V

Stand-by Supply Current

Input Low Voltage

(E0, E1, E2, SCL, SDA)

V_IL

V_IH

– 0.3

0.3V_CC

V_CC+1

Input High Voltage

(E0, E1, E2, SCL, SDA)

0.7V_CC

V_IL

V_IH

V_OL

Input Low Voltage (WC)

Input High Voltage (WC)

Output Low Voltage

– 0.3

0.5

V_CC+1

0.4

0.7V_CC

I_OL= 2.1 mA, 2.5 V ≤ V_CC≤ 5.5 V

13/21

M24164

Table 11. AC Characteristics (M24164)

Test conditions specified in Table 7 and Table 5

Symbol

f_C

Alt.

f_SCL

Parameter

Min.

Max.

400

300

Unit

kHz

Clock Frequency

Clock Rise Time

Clock Fall Time

t_CH1CH2

t_CL1CL2

t_CHCL

t_R

t_F

t_HIGH

t_LOW

t_R

Clock Pulse Width High

Clock Pulse Width Low

SDA Rise Time

600

1300

t_CLCH

300

t_DH1DH2

t_F

SDA Fall Time

t_DL1DL2

t_DXCX

t_CLDX

t_CLQX

t_SU:DAT

t_HD:DAT

t_DH

Data In Set Up Time

100

Data In Hold Time

Data Out Hold Time

200

600

t_AA

Clock Low to Next Data Valid (Access Time)

Start Condition Set Up Time

Start Condition Hold Time

Stop Condition Set Up Time

900

t_CLQV

t_SU:STA

t_HD:STA

t_SU:STO

t_CHDX

t_DLCL

t_CHDH

Time between Stop Condition and Next Start

Condition

t_DHDL

t_W

t_BUF

t_WR

1300

Write Time

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

14/21

M24164

Table 12. AC Characteristics (M24164-W)

Test conditions specified in Table 7 and Table 6

Symbol

f_C

Alt.

f_SCL

Parameter

Min.

Max.

400

300

Unit

kHz

Clock Frequency

Clock Rise Time

Clock Fall Time

t_CH1CH2

t_CL1CL2

t_CHCL

t_R

t_F

t_HIGH

t_LOW

t_R

Clock Pulse Width High

Clock Pulse Width Low

SDA Rise Time

600

1300

t_CLCH

300

t_DH1DH2

t_F

SDA Fall Time

t_DL1DL2

t_DXCX

t_CLDX

t_CLQX

t_SU:DAT

t_HD:DAT

t_DH

Data In Set Up Time

100

Data In Hold Time

Data Out Hold Time

200

600

t_AA

Clock Low to Next Data Valid (Access Time)

Start Condition Set Up Time

Start Condition Hold Time

Stop Condition Set Up Time

900

t_CLQV

t_SU:STA

t_HD:STA

t_SU:STO

t_CHDX

t_DLCL

t_CHDH

Time between Stop Condition and Next Start

Condition

t_DHDL

t_W

t_BUF

t_WR

1300

Write Time

Note: 1. For a reSTART condition, or following a Write cycle.

2. Sampled only, not 100% tested.

3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

15/21

M24164

Figure 12. AC Waveforms

tCHCL

tCLCH

SCL

tDLCL

SDA In

tCHDX

tCLDX

tDXCX

SDA

tCHDH tDHDL

Change

START

Condition

START

Condition

SDA

Input

STOP

Condition

SCL

SDA In

tCHDH

STOP

tCHDX

START

Condition

Write Cycle

Condition

SCL

tCLQV

tCLQX

Data Valid

SDA Out

AI00795C

16/21

M24164

PACKAGE MECHANICAL

PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame

PDIP-B

Notes: 1. Drawing is not to scale.

PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame

inches

Min.

Symb.

Typ.

Min.

Max.

Typ.

Max.

5.33

0.210

0.38

2.92

0.36

1.14

0.20

9.02

7.62

6.10

–

0.015

0.115

0.014

0.045

0.008

0.355

0.300

0.240

–

3.30

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

4.95

0.56

1.78

0.36

0.130

0.018

0.060

0.010

0.365

0.310

0.250

0.100

0.300

0.195

0.022

0.070

0.014

0.400

0.325

0.280

–

10.16

8.26

7.11

–

10.92

3.81

0.430

0.150

3.30

2.92

0.130

0.115

17/21

M24164

SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width

h x 45˚

SO-a

Note: Drawing is not to scale.

SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width

inches

Min.

0.053

0.004

0.013

0.007

0.189

0.150

–

Symb.

Typ.

Min.

1.35

0.10

0.33

0.19

4.80

3.80

–

Max.

1.75

0.25

0.51

0.25

5.00

4.00

–

Typ.

Max.

0.069

0.010

0.020

0.010

0.197

0.157

–

1.27

0.050

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

0.10

0.004

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M24164

PART NUMBERING

Table 13. Ordering Information Scheme

Example:

M24164

–

W MN

Device Type

M24 = I C serial access EEPROM

Device Function

164 = 16 Kbit (2048 x 8)

Operating Voltage

blank = V = 4.5 to 5.5V

W = V = 2.5 to 5.5V

Package

BN = PDIP8 (0.25 mm frame)

MN = SO8 (150 mil width)

Temperature Range

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

For a list of available options (speed, package,

etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-

fice.

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M24164

REVISION HISTORY

Table 14. Document Revision History

Date

Rev.

Description of Revision

Jan-1999

1.0

Document written

Document reformatted.

-R voltage range taken out

23-Oct-2001 2.0

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M24164

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners

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www.st.com

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MM24164BN3T [STMICROELECTRONICS]

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