NAND512R4M0AZC5E [STMICROELECTRONICS]
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP; 256 / 512MB / 1Gb的（ X8 / X16 ， 1.8 / 3V ， 528字节页） NAND闪存+ 256 / 512Mb的（ X16 / X32 ， 1.8V ） LPSDRAM ， MCP
| 型号： | NAND512R4M0AZC5E |
| 厂家： | 
ST |
| 描述： | 256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP |
| 文件： | 总23页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND256-M
NAND512-M, NAND01G-M
256/512Mb/1Gb (x8/x16, 1.8/3V, 528 Byte Page) NAND
Flash Memories + 256/512Mb (x16/x32, 1.8V) LPSDRAM, MCP
Features
■ Multi-Chip Packages
FBGA
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash + 1 die of 256 Mb (x16) SDR
LPSDRAM
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash + 2 dice of 256 Mb (x16) SDR
LPSDRAMs
TFBGA107 10.5 x 13 x 1.2mm
TFBGA149 10 x 13.5 x 1.2mm
LFBGA137 10.5 x 13 x 1.4mm
TFBGA137 10.5 x 13 x 1.2 mm(1)
– 1 die of 256 Mb, 512 Mb (x8/ x16) NAND
Flash +1 die of 256 Mb (x16) DDR
LPSDRAM
– 1 die of 512 Mb (x16) NAND Flash + 1 die
of 256 Mb or 512 Mb (x16) DDR LPSDRAM
■ Supply voltages
(1) Preliminary specifications.
– V
– V
= 1.7V to 1.95V or 2.5V to 3.6V
DDF
DDD
■ Fast Block Erase
= V
= 1.7V to 1.9V
DDQD
– Block erase time: 2ms (typ)
■ Electronic Signature
®
■ Status Register
■ ECOPACK packages
■ Data integrity
■ Temperature range
– 100,000 Program/Erase cycles
– 10 years Data Retention
– -30 to 85°C
Flash Memory
LPSDRAM
■ NAND Interface
■ Interface: x16 or x 32 bus width
■ Deep Power Down mode
■ 1.8v LVCMOS interface
– x8 or x16 bus width
– Multiplexed Address/ Data
■ Page size
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
■ Quad internal Banks controlled by BA0 and
BA1
■ Automatic and controlled Precharge
■ Block size
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
■ Auto Refresh and Self Refresh
– 8,192 Refresh cycles/64ms
– Programmable Partial Array Self Refresh
■ Page Read/Program
– Auto Temperature Compensated Self
Refresh
– Random access: 15µs (max)
– Sequential access: 50ns (min)
– Page program time: 200µs (typ)
■ Wrap sequence: sequential/interleave
■ Burst Termination by Burst Stop command and
■ Copy Back Program mode
Precharge command
– Fast page copy without external buffering
August 2006
Rev 5
1/23
www.st.com
2
NAND256-M, NAND512-M, NAND01G-M
Table 1.
Product List
Part Number
Reference
NAND Product
LPSDRAM Product
Package
NAND256R3M0
256 Mbit (x8), 1.8V
256Mbit (x16) 1.8V
256Mbit (x16) 3V
256 Mbit SDR, (x16), 1.8V, 104MHz TFBGA107
256 Mbit DDR (x16) 1.8V, 133MHz TFBGA149
256 Mbit SDR (x16), 1.8V, 104MHz TFBGA149
256 Mbit SDR (x16), 1.8V, 104MHz TFBGA107
256 Mbit DDR (x16) 1.8V, 133MHz TFBGA149
512 Mbit DDR (x16) 1.8V, 133MHz TFBGA149
NAND256-M NAND256R4M3
NAND256W3M4
NAND512R3M0
NAND512R4M3
512 Mbit (x8), 1.8V
512Mbit (x8) 3V
NAND512-M
NAND512R4M5
512Mbit SDR (2x16) (2x256Mbit
LFBGA 137
NAND512W3M2
SDR x16) 1.8V,104Mhz
512 Mbit SDR (2x16) (2 x 256Mbit
LFBGA137
2 x 512Mbit NAND (x8) 3V
1 Gbit NAND (x8) 3V
SDR x16) 1.8V, 104MHz
NAND01G-M NAND01GW3M2
512Mbit SDR (x32) 1.8V, 133MHz
TFBGA137
2/23
NAND256-M, NAND512-M, NAND01G-M
Contents
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
NAND Flash Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
LPSDRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
3
4
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of tables
NAND256-M, NAND512-M, NAND01G-M
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Product List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Signal Names: NAND Flash & 1 x SDR LPSDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Names: NAND Flash & 2 x SDR LPSDRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Signal Names - NAND Flash & DDR LPSDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Mechanical Data. . . . . . 17
TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Mechanical Data. . . . . . 18
LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Mechanical Data. . . . . . . 19
TFBGA137 10.5x13mm - 10x13 active ball array, 0.80mm pitch . . . . . . . . . . . . . . . . . . . . 20
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4/23
NAND256-M, NAND512-M, NAND01G-M
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic Diagram: NAND Flash & 1 x SDR LPSDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Diagram: NAND Flash & 2 x SDR LPSDRAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Diagram: NAND Flash & DDR LPSDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TFBGA107 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TFBGA149 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LFBGA137 and TFBGA137 Connections (Top view through package) . . . . . . . . . . . . . . . 15
TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Bottom Outline . . . . . . . 17
TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Bottom Outline . . . . . . . 18
LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline . . . . . . . . 19
Figure 10. TFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline . . . . . . . . 20
5/23
Summary description
NAND256-M, NAND512-M, NAND01G-M
1
Summary description
The NAND256-M, NAND512-M and NAND01G-M are Multi-Chip Packages which combine
up to 512 Mbit LPSDRAM with a 256 Mbit, 512 Mbit or 1 Gbit NAND Flash memory. This
combination of LPSDRAM and NAND Flash can result in up to 1 Gbit of memory.
The NAND Flash memory and LPSDRAM components have separate power supplies and
grounds. They also have separate control, address and input/output signals, which allows
simultaneous access to both devices at any moment.
They are distinguished by two chip enable inputs: E for the NAND Flash memory and E
F
D
for the LPSDRAM. See Figure 1: Logic Diagram: NAND Flash & 1 x SDR LPSDRAM and
Table 2: Signal Names: NAND Flash & 1 x SDR LPSDRAM for an overview of the signals
attached to each component.
The NAND256-M, NAND512-M and NAND01G-M are available with a 1.8 or 3V voltage
supply. See Table 1: Product List for a complete list of the products available.
The devices are offered in the following Multi-Chip packages:
■
■
■
■
TFBGA107 (10.5 x 13 x 1.2mm)
LFBGA137 (10.5 x 13 x 1.4mm)
TFBGA149 (10 x 13.5 x 1.2mm)
TFBGA137 (10.5 x 13 x 1.2mm)
In order to meet environmental requirements, ST offers the NAND256-M, NAND512-M and
®
NAND01G-M devices in ECOPACK package. ECOPACK packages are Lead-free. The
category of second Level Interconnect is marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
The memories are supplied with all the NAND Flash memory bits erased (set to ‘1’).
This datasheet should be read in conjunction with the NAND Flash and LPSDRAM
datasheets.
NAND Flash Component
The NAND256-M, NAND512-M and NAND01G-M devices contain a 1.8V, 256 Mbit or 512
Mbit, x8 528 Byte Page or x16 264 Word Page, NAND Flash memory with the Chip Enable
Don’t Care option.
For detailed information on how to use the devices, see the NANDxxx-A and
NAND01GWxA2B-KGD datasheets.
6/23
NAND256-M, NAND512-M, NAND01G-M
Summary description
LPSDRAM Component
The NAND256-M and NAND512-M devices contain either:
■
■
one M65KA256AL: 256Mbit (x16) Single Data Rate (SDR) LPSDRAM
two M65KA256AL: 256Mbit (x16) Single Data Rate (SDR) LPSDRAMs (SDR and
0
SDR )
1
■
■
■
one M65KG256AF: 256Mbit (x16) Double Data Rate (DDR) LPSDRAM
one M65KG512AB: 512Mbit (x16) Double Data Rate (DDR) LPSDRAM
one M65KC512AB: 512Mbit (x32) Single Data Rate (SDR) LPSDRAM
Refer to Table 1: Product List, for a description of the memories contained in the NAND256-
M, NAND256-M and NAND01G-M devices.
For detailed information on how to use the SDR LPSDRAM devices, refer to the
M65KA256AL and M65KC512AB datasheets which are available from your local
STMicroelectronics distributor.
For detailed information on how to use the DDR LPSDRAM device, refer to the
M65KG256AB datasheet which is available from your local STMicroelectronics distributor.
Figure 1.
Logic Diagram: NAND Flash & 1 x SDR LPSDRAM
V
V
V
DDQD DDD DDF
13
2
A0-A12
8/16
16
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
BA0-BA1
E
F
R
DQ0-DQ15
W
F
NAND256-M
NAND512-M
NAND01G-M
AL
CL
WP
K
RB
KE
DQM0
DQM1
E
D
W
D
RAS
CAS
V
V
V
SSQD
SSF
SSD
Ai11024b
7/23
Summary description
Table 2.
NAND256-M, NAND512-M, NAND01G-M
Signal Names: NAND Flash & 1 x SDR LPSDRAM
NAND Flash
Data Inputs/Outputs for x8 devices
Data Inputs/Outputs for x16 devices
Address Latch Enable
Command Latch Enable
Chip Enable
I/O0-I/O7
I/O8-I/O15
AL
CL
EF
R
Read Enable
RB
Ready/Busy (open-drain output)
Write Enable
WF
WP
Write Protect
VDDF
Supply Voltage
V
Ground
SSF
SDR LPSDRAM
Row Address: RA0-RA11
Column Address: CA0-CA8
Auto-precharge flag: A10
A0-A12
BA0-BA1
DQ0-DQ15
K
Bank Address
Data Inputs/Outputs
Clock Input
KE
Clock Enable Input
ED
Chip Select inputs
WD
Write Enable Input
RAS
Row Address Strobe Input
Column Address Strobe Input
Upper DQ Mask Enable Output
Lower DQ Mask Enable Output
Supply Voltage
CAS
DQM0
DQM1
VDDD
VDDQD
VSSD
Input/Output Supply Voltage
Ground
V
Input/Output Ground
Not Connected Internally
SSQD
NC
8/23
NAND256-M, NAND512-M, NAND01G-M
Summary description
Figure 2.
Logic Diagram: NAND Flash & 2 x SDR LPSDRAMs
V
V
V
DDQD DDD DDF
13
2
A0-A12
I/O0-I/O7, x8/x16
I/O8-I/O15, x16
BA0-BA1
E
F
R
DQ0-DQ15 x16 SDR0
DQ16-DQ31 x16 SDR1
NAND256-M
NAND512-M
NAND01G-M
W
F
AL
CL
WP
K
RB
KE
E
E
0D
1D
DQM0-DQM3
W
D
RAS
CAS
Ai11022b
V
SS
9/23
Summary description
Table 3.
NAND256-M, NAND512-M, NAND01G-M
Signal Names: NAND Flash & 2 x SDR LPSDRAMs
NAND Flash
Data Inputs/Outputs
I/O0-I/O7
AL
Address Latch Enable
Command Latch Enable
Chip Enable
CL
EF
R
Read Enable
RB
Ready/Busy (open-drain output)
Write Enable
WF
WP
VDDF
Write Protect
Supply Voltage
V
Ground
SSF
SDR LPSDRAM
Row Address: RA0-RA11
Column Address: CA0-CA8
Auto-precharge flag: A10
A0-A12
BA0-BA1
DQ0-DQ15
DQ16-DQ31
K
Bank Address
Data Inputs/Outputs for x16 devices SDR0
Data Inputs/Outputs for x16 devices SDR1
Clock Input
KE
Clock Enable Input
E0D
Chip Select input for SDR0
Chip Select input for SDR1
Write Enable Input
E1D
WD
RAS
Row Address Strobe Input
Column Address Strobe Input
Lower DQ Mask Enable Output for SDR0
Upper DQ Mask Enable Output for SDR0
Lower DQ Mask Enable Output for SDR1
Upper DQ Mask Enable Output for SDR1
Supply Voltage
CAS
DQM0
DQM1
DQM2
DQM3
VDDD
VDDQD
VSSD
Input/Output Supply Voltage
Ground
V
Input/Output Ground
SSQD
NC
Not Connected Internally
10/23
NAND256-M, NAND512-M, NAND01G-M
Summary description
Figure 3.
Logic Diagram: NAND Flash & DDR LPSDRAM
V
V
V
DDQD DDD DDF
13
2
16
A0-A12
I/O0-I/O15
BA0-BA1
E
F
R
DQ0-DQ15
W
F
AL
CL
WP
K
NAND256-M
NAND512-M
NAND01G-M
UDQS-LDQS
RB
K
KE
E
D
W
D
RAS
CAS
DQM0
DQM1
V
V
V
SSQD
SSF
SSD
Ai11023b
11/23
Summary description
Table 4.
NAND256-M, NAND512-M, NAND01G-M
Signal Names - NAND Flash & DDR LPSDRAM
NAND Flash
Data Inputs/Outputs
I/O0-I/O15
AL
Address Latch Enable
Command Latch Enable
Chip Enable
CL
EF
R
Read Enable
RB
Ready/Busy (open-drain output)
Write Enable
WF
WP
VDDF
Write Protect
Supply Voltage
V
Ground
SSF
DDR LPSDRAM
Address Inputs
A0-A12
A10 determines the Precharge mode.
BA0-BA1
DQ0-DQ15
UDQS-LDQS
K
Bank Select Inputs
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Clock Input
K
Clock Input
KE
Clock Enable Input
ED
Chip Select inputs
WD
Write Enable Input
RAS
Row Address Strobe Input
Column Address Strobe Input
DQ Mask Enable Input (controls DQ0-DQ7)
DQ Mask Enable Input (controls DQ8-DQ15)
Supply Voltage
CAS
DQM0
DQM1
VDDD
VDDQD
VSSD
Input/Output Supply Voltage
Ground
V
Input/Output Ground
Not Connected Internally
Do Not Use
SSQD
NC
DU
12/23
NAND256-M, NAND512-M, NAND01G-M
Summary description
Figure 4.
TFBGA107 Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
B
DU
DU
DU
V
V
A3
A1
NC
DU
NC
DQ0
DQ2
DQ4
DQ6
NC
V
NC
A0
DU
DDF
SSF
DDD
CL
V
DQ1
DQ3
DQ5
DQ7
NC
C
E
A2
SSD
F
A10
V
AL
R
W
BA0
RAS
CAS
A12
A8
BA1
NC
W
D
E
F
DDQD
F
V
RB
NC
NC
E
D
SSQD
V
V
WP
NC
NC
SSD
DDD
DDQD
D
V
V
DQM0
DQM1
NC
KE
A9
G
H
J
SSD
A11
A7
V
K
NC
DDD
V
V
DQ8
DQ10
DQ12
DQ14
I/O0
I/O8
I/O2
I/O4
I/O6
SSQD
A6
I/O10
I/O12
I/O14
K
L
DQ9
DQ11
DQ13
DQ15
DDQD
A5
V
I/O1
I/O9
I/O3
I/O5
I/O7
SSQD
I/O13
I/O15
V
A4
I/O11
M
N
P
DDD
NC
V
NC
DU
DU
DU
DU
DU
V
V
V
V
SSF
SSD
DDF
DDF
SSF
DU
AI10143b
13/23
Summary description
NAND256-M, NAND512-M, NAND01G-M
Figure 5.
TFBGA149 Connections (Top view through package)
11
DU
DU
NC
1
2
3
4
5
6
7
8
9
10
DU
DU
I/O7
12
DU
DU
DU
A
B
DU
DU
DU
DU
DU
DU
DU
V
V
V
V
K
DDD
SSD
A8
K
NC
NC
DDD
A0
SSD
C
DU
NC
NC
RB
R
E
D
WD
KE
A7
A6
I/O6
I/O5
I/O4
NC
I/O15
I/O14
I/O13
I/O12
D
E
F
G
H
J
A1
A2
A3
BA0
NC
NC
NC
CAS
A12
A11
A5
BA1
A10
RAS
NC
NC
NC
V
E
F
A9
A4
SSF
DDF
NC
V
NC
NC
CL
AL
NC
NC
V
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
SSF
DDF
NC
NC
NC
NC
NC
NC
NC
DQM0
LDQS
DQM1
UDQS
NC
NC
I/O11
I/O10
I/O9
I/O8
NC
K
L
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O3
I/O2
I/O1
I/O0
NC
W
F
DQ6
DQ7
DQ8
DQ9
M
N
P
WP
NC
V
V
V
V
V
V
DU
DDQD
SSQD
SSD
DDQD
SSD
DU
DU
DU
NC
DU
DU
NC
DU
DU
DDD
DU
DU
DU
DU
DU
DU
R
T
AI11007b
1. Balls shaded in gray are only present for NAND + DDR devices delivered in the TFBGA149 package.
14/23
NAND256-M, NAND512-M, NAND01G-M
Summary description
Figure 6.
LFBGA137 and TFBGA137 Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
B
DU
DU
DU
V
V
E
W
V
V
SSD
NC
NC
R
WP
CL
AL
NC
DDF
F
F
DDD
V
V
A4
RB
DQ31
DQ29
DQM3
DQ23
DQ9
DQ30
DQ28
DQ26
DQM2
K
C
V
V
SSQD
SSD
SSF
DDQD
V
V
DDQD
A5
A7
A9
DQ25
NC
DQ27
DQ22
DQ24
DQM1
DQ12
D
E
F
DDD
A6
SSQD
V
V
A8
KE
DQ18
DQ17
DQ16
DQ21
DDQD
SSQD
V
V
A12
NC
A11
RAS
CAS
NC
DQ19
NC
SSQD
DDQD
DDQD
V
V
SSQD
DQ15
DQ20
G
H
J
V
V
V
DDD
DQ13
DQ11
DQ7
DQ1
I/O3
NC
NC
DDD
SSQD
V
E
D
V
V
BA0
A10
A3
DQ14
A0
DQ10
DQ8
DQ2
I/O5
NC
DQ6
DQ3
NC
DQM0
DQ4
DQ5
I/O7
SSD
SSQD
DDQD
DDQD
W
D
V
V
K
L
BA1
A2
SSQD
V
V
A1
DQ0
NC
DDQD
SSQD
DDQD
V
V
V
V
M
N
P
R
NC
DDD
I/O0
NC
SSD
I/O1
NC
SSQD
V
V
V
I/O2
NC
NC
I/O6
NC
NC
DDF
DDQD
SSQD
V
V
V
NC
NC
NC
I/O4
SSF
DDD
SSD
DU
DU
DU
DU
AI13146
15/23
Maximum rating
NAND256-M, NAND512-M, NAND01G-M
2
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
85
TA
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
-30
°C
°C
°C
V
TBIAS
TSTG
TBD(1) TBD(1)
-55
-0.6
-0.6
125
2.7
4.6
1.8V device
3V device
NAND Flash Input or Output
Voltage
V
(2)
VIO
LPSDRAM Input or Output
Voltage
1.8V device
-0.5
2.6
V
VDDF
1.8V device
3V device
-0.6
-0.6
-0.5
2.7
4.6
2.6
V
V
V
NAND Flash Supply Voltage
LPSDRAM Supply Voltage
VDDD, VDDQD
1.8V device
LPSDRAM Short
Circuit Output
Current
IOS
PD
50
mA
W
LPSDRAM Power
Dissipation
1.0
1. TBD stands for To Be Defined.
2. Minimum Voltage may undershoot to -2V for less than 20ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins.
16/23
NAND256-M, NAND512-M, NAND01G-M
Package Mechanical
3
Package Mechanical
Figure 7.
TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Bottom Outline
D
D1
FD
b
SE
E
E1
ddd
BALL "B1"
e
FE
SD
e
A
A2
A1
BGA-Z24
1. Drawing not to scale.
Table 6.
Symbol
TFBGA107 10.5x13mm - 10x14 active ball array, 0.80mm pitch, Mechanical Data
millimeters
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
1.20
0.047
0.25
0.010
0.80
0.45
0.031
0.018
0.413
0.283
0.40
0.50
0.016
0.409
0.020
0.417
D
10.50
7.20
10.40
10.60
D1
ddd
E
0.10
0.004
0.516
13.00
10.40
0.80
1.65
1.30
0.40
0.40
12.90
–
13.10
0.512
0.409
0.031
0.065
0.051
0.016
0.016
0.508
–
E1
e
–
–
FD
FE
SD
SE
17/23
Package Mechanical
NAND256-M, NAND512-M, NAND01G-M
Figure 8.
TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Bottom Outline
D
D1
b
SE
E
E1
ddd
e
BALL "A1"
e
FE
FD
SD
A
A2
A1
BGA-Z78
Table 7.
Symbol
TFBGA149 10x13.5mm - 12x16 active ball array, 0.80mm pitch, Mechanical Data
millimeters
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.250
0.0098
0.800
0.450
10.000
8.800
0.0315
0.0177
0.3937
0.3465
0.400
9.900
0.500
0.0157
0.3898
0.0197
0.3976
D
10.100
D1
ddd
E
0.100
0.0039
0.5354
13.500
12.000
0.800
0.600
0.750
0.400
0.400
13.400
–
13.600
0.5315
0.4724
0.0315
0.0236
0.0295
0.0157
0.0157
0.5276
–
E1
e
–
–
FD
FE
SD
SE
–
–
–
–
–
–
–
–
18/23
NAND256-M, NAND512-M, NAND01G-M
Package Mechanical
Figure 9.
LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline
D
D1
FD
SD
e
E
E1
ddd
BALL "B1"
FE
A1
e
b
A2
A
BGA-Z83
1. Subject to change without prior notice.
(1)
Table 8.
Symbol
LFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Mechanical Data
millimeters
Min
inches
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.40
0.055
0.25
0.010
1.00
0.45
0.039
0.018
0.413
0.283
0.40
0.50
0.016
0.409
0.020
0.417
D
10.50
7.20
10.40
10.60
D1
ddd
E
0.10
0.004
0.516
13.00
11.20
0.80
1.65
0.90
0.40
12.90
–
13.10
0.512
0.441
0.031
0.065
0.035
0.016
0.508
–
E1
e
–
–
FD
FE
SD
1. Subject to change without prior notice.
19/23
Package Mechanical
NAND256-M, NAND512-M, NAND01G-M
Figure 10. TFBGA137 10.5x13mm - 10x13 active ball array, 0.8mm pitch- Bottom Outline
D
D1
FD
SD
e
E
E1
ddd
BALL "B1"
FE
A1
e
b
A2
A
BGA-Z83
1. Subject to change without prior notice.
Table 9.
TFBGA137 10.5x13mm - 10x13 active ball array, 0.80mm pitch
millimeters
inches
Min
Symbol
Typ
Min
Max
Typ
Max
A
A1
A2
b
1.20
0.047
0.25
0.010
0.80
0.45
10.50
7.20
13.00
11.20
0.80
1.65
0.90
0.40
0.031
0.018
0.413
0.283
0.512
0.441
0.031
0.065
0.035
0.016
0.40
0.50
0.016
0.409
0.020
0.417
D
10.40
10.60
D1
E
12.90
–
13.10
–
0.508
–
0.516
–
E1
e
FD
FE
SD
–
–
–
–
20/23
NAND256-M, NAND512-M, NAND01G-M
Part Numbering
4
Part Numbering
Table 10. Ordering Information Scheme
Example:
NAND256
R
3
M
4
A
ZB
5
E
Device Type
NAND Flash Memory
NAND Flash Density
256 = 256Mb
512 = 512Mb
01G = 1Gb
Operating Voltage
R = VDDF = 1.7V to 1.95V
W = VDDF = 2.5V to 3.6V
NAND Bus Width
3 = x8
4 = x16
Family Identifier
M = 528 Byte Page NAND Flash + LPSDRAM
Device Options
0 = 256, x16, 104MHz, SDR, BGA107
2 = 2 x 256, 2x16, 104MHz, SDR, BGA137 or
512, x32, 133MHz, SDR, BGA137
3 = 256, x16, 133MHz, DDR BGA149
4 = 256, x16, 104MHz, SDR, BGA149
5 = 512, x16, 133MHz, DDR, BGA149
Product Version
A
B
C
Package
ZB = TFBGA
ZC = LFBGA
Temperature range
5 = -30°c to 85°C
Option
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
Devices are shipped from the factory with the Flash memory content bits, in valid blocks,
erased to ’1’. For further information on any aspect of this device, please contact your
nearest ST Sales Office.
21/23
Revision history
NAND256-M, NAND512-M, NAND01G-M
5
Revision history
Table 11. Document Revision History
Date
Version
Revision Details
06-Feb-2006
09-Feb-2006
1.0
2.0
First Issue.
Reference M65KG256AD changed to M65KG256AB.
Part numbers NAND512R4M3 and NAND512R4M5 added,
corresponding to 1 die of 512 Mb (x16) NAND Flash + 1 die of 256 Mb or
512 Mb (x16) DDR LPSDRAM.
07-Apr-2006
23-May-2006
24-Aug-2006
3
4
5
Temperature range -25 to 85°C removed for 512 Mbit LPSDRAMs.
NAND512W3M2 part number added in Table 1: Product List.
Figure 5: TFBGA149 Connections (Top view through package) updated.
LPSDRAM supply voltage changed to 1.7 to 1.9V.
1 Gbit (x8) 3V NAND Flash memory and 512Mbit SDR (x32) 1.8V,
133MHz LPSDRAM added for NAND01GW3M2.
TFBGA137 package added.
22/23
NAND256-M, NAND512-M, NAND01G-M
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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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23/23
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