PSD854512MT_技术文档

PSD813F2, PSD833F2

PSD834F2, PSD853F2, PSD854F2

Flash In-System Programmable (ISP)

Peripherals for 8-bit MCUs, 5V

PRELIMINARY DATA

FEATURES SUMMARY

■

FLASH IN-SYSTEM PROGRAMMABLE (ISP)

Figure 1. Packages

PERIPHERAL FOR 8-BIT MCUS

■

DUAL BANK FLASH MEMORIES

–

UP TO 2 Mbit OF PRIMARY FLASH

MEMORY (8 Uniform Sectors, 32K x8)

UP TO 256 Kbit SECONDARY FLASH

MEMORY (4 Uniform Sectors)

Concurrent operation: READ from one

memory while erasing and writing the

other

PQFP52 (M)

■

UP TO 256 Kbit BATTERY-BACKED SRAM

27 RECONFIGURABLE I/O PORTS

ENHANCED JTAG SERIAL PORT

PLD WITH MACROCELLS

–

Over 3000 Gates of PLD: CPLD and

DPLD

CPLD with 16 Output Macrocells (OMCs)

and 24 Input Macrocells (IMCs)

DPLD - user defined internal chip select

decoding

PLCC52 (J)

■

27 INDIVIDUALLY CONFIGURABLE I/O

PORT PINS

The can be used for the following functions:

–

MCU I/Os

PLD I/Os

Latched MCU address output

Special function I/Os.

16 of the I/O ports may be configured as

open-drain outputs.

TQFP64 (U)

■

IN-SYSTEM PROGRAMMING (ISP) WITH

JTAG

–

Built-in JTAG compliant serial port allows

full-chip In-System Programmability

Efficient manufacturing allow easy

product testing and programming

■

HIGH ENDURANCE:

–

100,000 Erase/WRITE Cycles of Flash

Memory

Use low cost FlashLINK cable with PC

■

PAGE REGISTER

–

1,000 Erase/WRITE Cycles of PLD

15 Year Data Retention

Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

■

5V±10% SINGLE SUPPLY VOLTAGE

STANDBY CURRENT AS LOW AS 50µA

PROGRAMMABLE POWER MANAGEMENT

June 2004

1/110

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PSD Register Description and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 20

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x). . . . . . . . . . . . . . . . . . . . 26

ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 30

Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 30

PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Data Byte Enable Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Port Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

For Users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Power-Up Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . . 67

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 69

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SUMMARY DESCRIPTION

The PSD8XXFX family of memory systems for mi-

crocontrollers (MCUs) brings In-System-Program-

mability (ISP) to Flash memory and programmable

logic. The result is a simple and flexible solution for

embedded designs. PSD devices combine many

of the peripheral functions found in MCU based

applications.

The innovative PSD8XXFX family solves key

problems faced by designers when managing dis-

crete Flash memory devices, such as:

–

First-time In-System Programming (ISP)

Complex address decoding

Simultaneous read and write to the device.

The JTAG Serial Interface block allows In-System

Programming (ISP), and eliminates the need for

an external Boot EPROM, or an external program-

mer. To simplify Flash memory updates, program

execution is performed from a secondary Flash

memory while the primary Flash memory is being

updated. This solution avoids the complicated

hardware and software overhead necessary to im-

plement IAP.

ST makes available a software development tool,

PSDsoft Express, that generates ANSI-C compli-

ant code for use with your target MCU. This code

allows you to manipulate the non-volatile memory

(NVM) within the PSD. Code examples are also

provided for:

Table 1 summarizes all the devices in the

PSD834F2, PSD853F2, PSD854F2.

The CPLD in the PSD devices features an opti-

mized macrocell logic architecture. The PSD mac-

rocell was created to address the unique

requirements of embedded system designs. It al-

lows direct connection between the system ad-

dress/data bus, and the internal PSD registers, to

simplify communication between the MCU and

other supporting devices.

The PSD device includes a JTAG Serial Program-

ming interface, to allow In-System Programming

(ISP) of the entire device. This feature reduces de-

velopment time, simplifies the manufacturing flow,

and dramatically lowers the cost of field upgrades.

Using ST’s special Fast-JTAG programming, a de-

sign can be rapidly programmed into the PSD in as

little as seven seconds.

–

Flash memory IAP via the UART of the host

MCU

Memory paging to execute code across

several PSD memory pages

Loading, reading, and manipulation of PSD

macrocells by the MCU.

Table 1. Product Range

Number of

Macrocells

Serial

ISP

JTAG/

ISC Port

Primary Flash

Memory

(8 Sectors)

Secondary

Flash Memory

4 Sectors)

Turbo

Mode

(1)

(2)

I/O Ports

Part Number

SRAM

Input

Output

16

PSD813F2

PSD813F3

PSD813F4

PSD813F5

PSD833F2

PSD834F2

PSD853F2

PSD854F2

1 Mbit

2 Mbit

1 Mbit

2 Mbit

256 Kbit

none

16 Kbit

none

27

24

yes

16

256 Kbit

none

16

none

16

256 Kbit

64 Kbit

256 Kbit

16

Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management

Unit (PMU), Automatic Power-down (APD)

2. SRAM may be backed up using an external battery.

6/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 2. PQFP52 Connections

PD2 1

PD1 2

PD0 3

PC7 4

PC6 5

PC5 6

PC4 7

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

V

8

32 AD8

CC

GND 9

31 V

CC

PC3 10

PC2 11

PC1 12

PC0 13

30 AD7

29 AD6

28 AD5

27 AD4

AI02858

7/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 3. PLCC52 Connections

8

PD2

PD1

PD0

PC7

PC6

PC5

PC4

AD15

AD14

AD13

AD12

AD11

AD10

AD9

46

45

44

43

42

41

40

39

38

37

36

9

10

11

12

13

14

15

16

17

18

V

AD8

CC

GND

V

CC

PC3

PC2

AD7

AD6

19

20

PC1

PC0

AD5

AD4

35

34

AI02857

8/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 4. TQFP64 Connections

PD2 1

PD1 2

PD0 3

PC7 4

PC6 5

PC5 6

48 CNTL0

47 AD15

46 AD14

45 AD13

44 AD12

43 AD11

42 AD10

41 AD9

V

7

8

9

CC

40 AD8

GND 10

GND 11

PC3 12

PC2 13

PC1 14

PC0 15

NC 16

39 V

CC

38 V

CC

37 AD7

36 AD6

35 AD5

34 AD4

33 AD3

AI09645

9/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PIN DESCRIPTION

Table 2. Pin Description (for the PLCC52 package - Note 1)

Pin Name

Type

Description

This is the lower Address/Data port. Connect your MCU address or address/data bus

according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect AD0-AD7 to this port.

If your MCU does not have a multiplexed address/data bus, or you are using an 80C251

ADIO0-7 30-37

I/O in page mode, connect A0-A7 to this port.

If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are

passed to the PLDs.

This is the upper Address/Data port. Connect your MCU address or address/data bus

according to the following rules:

If your MCU has a multiplexed address/data bus where the data is multiplexed with the

lower address bits, connect A8-A15 to this port.

If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port.

I/O If you are using an 80C251 in page mode, connect AD8-AD15 to this port.

ADIO8-15 39-46

If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this

port.

ALE or AS latches the address. The PSD drives data out only if the READ signal is active

and one of the PSD functional blocks was selected. The addresses on this port are

passed to the PLDs.

The following control signals can be connected to this port, based on your MCU:

WR – active Low Write Strobe input.

CNTL0

47

I

R_W – active High READ/active Low write input.

This port is connected to the PLDs. Therefore, these signals can be used in decode and

other logic equations.

The following control signals can be connected to this port, based on your MCU:

RD – active Low Read Strobe input.

E – E clock input.

DS – active Low Data Strobe input.

CNTL1

50

I

PSEN – connect PSEN to this port when it is being used as an active Low READ signal.

For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the

READ signal.

This port is connected to the PLDs. Therefore, these signals can be used in decode and

other logic equations.

This port can be used to input the PSEN (Program Select Enable) signal from any MCU

that uses this signal for code exclusively. If your MCU does not output a Program Select

Enable signal, this port can be used as a generic input. This port is connected to the

PLDs.

CNTL2

49

I

10/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Pin Name

Type

Description

Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low

at Power-up.

Reset

48

I

These pins make up Port A. These port pins are configurable and can have the following

functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7) outputs.

Inputs to the PLDs.

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

29

28

27

25

24

23

22

21

Latched address outputs (see Table 6).

I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in

burst mode.

As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

D0/A16-D3/A19 in M37702M2 mode.

Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,

PA4-PA7 can be configured as CMOS or Open Drain Outputs.

These pins make up Port B. These port pins are configurable and can have the following

functions:

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

7

6

5

4

3

2

52

51

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

I/O

Inputs to the PLDs.

Latched address outputs (see Table 6).

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.

However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC0) output.

PC0

20

I/O

Input to the PLDs.

2

TMS Input for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC1) output.

PC1

19

I/O

Input to the PLDs.

2

TCK Input for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

11/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Pin Name

Type

Description

PC2 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC2) output.

Input to the PLDs.

PC2

18

I/O

V

STBY

– SRAM stand-by voltage input for SRAM battery backup.

This pin can be configured as a CMOS or Open Drain output.

PC3 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC3) output.

Input to the PLDs.

PC3

17

I/O

2

TSTAT output for the JTAG Serial Interface.

Ready/Busy output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC4) output.

Input to the PLDs.

PC4

14

I/O

2

TERR output for the JTAG Serial Interface.

Battery-on Indicator (V

battery.

). Goes High when power is being drawn from the external

BATON

This pin can be configured as a CMOS or Open Drain output.

PC5 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC5) output.

Input to the PLDs.

PC5

13

I/O

2

TDI input for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC6 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC6) output.

Input to the PLDs.

PC6

12

I/O

2

TDO output for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

12/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Pin Name

Type

Description

PC7 pin of Port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC7) output.

PC7

11

I/O

Input to the PLDs.

DBE – active Low Data Byte Enable input from 68HC912 type MCUs.

This pin can be configured as a CMOS or Open Drain output.

PD0 pin of Port D. This port pin can be configured to have the following functions:

ALE/AS input latches address output from the MCU.

MCU I/O – write or read from a standard output or input port.

Input to the PLDs.

PD0

10

I/O

CPLD output (External Chip Select).

PD1 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

Input to the PLDs.

PD1

9

I/O

CPLD output (External Chip Select).

CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and

the CPLD AND Array.

PD2 pin of Port D. This port pin can be configured to have the following functions:

MCU I/O - write to or read from a standard output or input port.

Input to the PLDs.

PD2

8

I/O

CPLD output (External Chip Select).

PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O.

When High, the PSD memory blocks are disabled to conserve power.

V

15, 38

Supply Voltage

Ground pins

CC

1, 16,

26

GND

Note: 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 74., page 102 onwards, for

pin numbers on other package types.

2. These functions can be multiplexed with other functions.

13/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 5. PSD Block Diagram

AI02861E

14/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD ARCHITECTURAL OVERVIEW

PSD devices contain several major functional

blocks. Figure 5 shows the architecture of the PSD

device family. The functions of each block are de-

scribed briefly in the following sections. Many of

the blocks perform multiple functions and are user

configurable.

The DPLD is used to decode addresses and to

generate Sector Select signals for the PSD inter-

nal memory and registers. The DPLD has combi-

natorial outputs. The CPLD has 16 Output

Macrocells (OMC) and 3 combinatorial outputs.

The PSD also has 24 Input Macrocells (IMC) that

can be configured as inputs to the PLDs. The

PLDs receive their inputs from the PLD Input Bus

and are differentiated by their output destinations,

number of product terms, and macrocells.

The PLDs consume minimal power. The speed

and power consumption of the PLD is controlled

by the Turbo Bit in PMMR0 and other bits in the

PMMR2. These registers are set by the MCU at

run-time. There is a slight penalty to PLD propaga-

tion time when invoking the power management

features.

Memory

Each of the memory blocks is briefly discussed in

the following paragraphs. A more detailed discus-

sion can be found in the section entitled Memory

Blocks, page 19.

The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash

memory is the primary memory of the PSD. It is di-

vided into 8 equally-sized sectors that are individ-

ually selectable.

The optional 256 Kbit (32K x 8) secondary Flash

memory is divided into 4 equally-sized sectors.

Each sector is individually selectable.

I/O Ports

The PSD has 27 individually configurable I/O pins

distributed over the four ports (Port A, B, C, and

D). Each I/O pin can be individually configured for

different functions. Ports can be configured as

standard MCU I/O ports, PLD I/O, or latched ad-

dress outputs for MCUs using multiplexed ad-

dress/data buses.

The optional SRAM is intended for use as a

scratch-pad memory or as an extension to the

MCU SRAM. If an external battery is connected to

Voltage Stand-by (V

, PC2), data is retained in

STBY

the event of power failure.

Each sector of memory can be located in a differ-

ent address space as defined by the user. The ac-

cess times for all memory types includes the

address latching and DPLD decoding time.

The JTAG pins can be enabled on Port C for In-

System Programming (ISP).

Ports A and B can also be configured as a data

port for a non-multiplexed bus.

Page Register

The 8-bit Page Register expands the address

range of the MCU by up to 256 times. The paged

address can be used as part of the address space

to access external memory and peripherals, or in-

ternal memory and I/O. The Page Register can

also be used to change the address mapping of

sectors of the Flash memories into different mem-

ory spaces for IAP.

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that

have either multiplexed or non-multiplexed ad-

dress/data buses. The device is configured to re-

spond to the MCU’s control signals, which are also

used as inputs to the PLDs. For examples, please

see the section entitled MCU Bus Interface

Examples, page 45.

PLDs

The device contains two PLDs, the Decode PLD

(DPLD) and the Complex PLD (CPLD), as shown

in Table 3, each optimized for a different function.

The functional partitioning of the PLDs reduces

power consumption, optimizes cost/performance,

and eases design entry.

Table 3. PLD I/O

Product

Terms

Name

Inputs Outputs

Decode PLD (DPLD)

73

17

19

42

140

Complex PLD (CPLD) 73

15/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

JTAG Port

In-System Programming (ISP) can be performed

through the JTAG signals on Port C. This serial in-

terface allows complete programming of the entire

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR, TDI, TDO) can be multiplexed with

other functions on Port C. Table 4 indicates the

JTAG pin assignments.

MCU inactivity. The APD Unit has a Power-down

mode that helps reduce power consumption.

The PSD also has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to '0' and the CPLD latches its outputs and

goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the

MCU to block signals from entering the CPLD to

reduce power consumption. Please see the sec-

tion entitled POWER MANAGEMENT, page 62 for

more details.

In-System Programming (ISP)

Using the JTAG signals on Port C, the entire PSD

device can be programmed or erased without the

use of the MCU. The primary Flash memory can

also be programmed in-system by the MCU exe-

cuting the programming algorithms out of the sec-

ondary memory, or SRAM. The secondary

memory can be programmed the same way by ex-

ecuting out of the primary Flash memory. The PLD

or other PSD Configuration blocks can be pro-

grammed through the JTAG port or a device pro-

grammer. Table 5 indicates which programming

methods can program different functional blocks

of the PSD.

Table 4. JTAG SIgnals on Port C

Port C Pins

PC0

JTAG Signal

TMS

TCK

PC1

PC3

PC4

PC5

PC6

TSTAT

TERR

TDI

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the

user control of the power consumption on selected

functional blocks based on system requirements.

The PMU includes an Automatic Power-down

(APD) Unit that turns off device functions during

TDO

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block

Primary Flash Memory

JTAG Programming Device Programmer

IAP

Yes

No

Secondary Flash Memory

PLD Array (DPLD and CPLD)

PSD Configuration

No

16/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

DEVELOPMENT SYSTEM

The PSD8XXFX family is supported by PSDsoft

Express, a Windows-based software development

tool. A PSD design is quickly and easily produced

in a point and click environment. The designer

does not need to enter Hardware Description Lan-

guage (HDL) equations, unless desired, to define

PSD pin functions and memory map information.

The general design flow is shown in Figure 6. PS-

Dsoft Express is available from our web site (the

address is given on the back page of this data

sheet) or other distribution channels.

PSDsoft Express directly supports two low cost

device programmers form ST: PSDpro and

FlashLINK (JTAG). Both of these programmers

may be purchased through your local distributor/

representative, or directly from our web site using

a credit card. The PSD is also supported by third

party device programmers. See our web site for

the current list.

Figure 6. PSDsoft Express Development Tool

PSDabel

PLD DESCRIPTION

MODIFY ABEL TEMPLATE FILE

OR GENERATE NEW FILE

PSD Configuration

PSD TOOLS

CONFIGURE MCU BUS

INTERFACE AND OTHER

PSD ATTRIBUTES

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

PSD Fitter

USER'S CHOICE OF

FIRMWARE

LOGIC SYNTHESIS

AND FITTING

MICROCONTROLLER

HEX OR S-RECORD

FORMAT

COMPILER/LINKER

ADDRESS TRANSLATION

AND MEMORY MAPPING

*.OBJ FILE

PSD Simulator

PSD Programmer

*.OBJ AND *.SVF

FILES AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

(CONVENTIONAL or

JTAG-ISC)

PSDsilos III

DEVICE SIMULATION

(OPTIONAL)

PSDPro, or

FlashLINK (JTAG)

AI04918

17/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 6 shows the offset addresses to the PSD

registers relative to the CSIOP base address. The

CSIOP space is the 256 bytes of address that is al-

located by the user to the internal PSD registers.

Table 7 provides brief descriptions of the registers

in CSIOP space. The following section gives a

more detailed description.

Table 6. I/O Port Latched Address Output Assignments (Note1)

Port A

Port B

MCU

Port A (3:0)

Port A (7:4)

Address a7-a4

N/A

Port B (3:0)

Address a11-a8

Address a3-a0

Port B (7:4)

8051XA (8-bit)

N/A

80C251 (page mode)

All other 8-bit multiplexed

8-bit non-multiplexed bus

Address a15-a12

Address a7-a4

Address a3-a0

N/A

Address a7-a4

N/A

Note: 1. See the section entitled I/O PORTS, page 51, on how to enable the Latched Address Output function.

2. N/A = Not Applicable

Table 7. Register Address Offset

1

Register Name

Data In

Port A Port B Port C Port D

Description

Other

00

02

01

03

10

11

Reads Port pin as input, MCU I/O input mode

Selects mode between MCU I/O or Address Out

Control

Stores data for output to Port pins, MCU I/O

output mode

Data Out

Direction

04

06

05

07

12

14

13

15

Configures Port pin as input or output

Configures Port pins as either CMOS or Open

Drain on some pins, while selecting high slew rate

on other pins.

Drive Select

08

09

16

17

Input Macrocell

Enable Out

0A

0C

0B

0D

18

1A

Reads Input Macrocells

Reads the status of the output enable to the I/O

Port driver

1B

Output Macrocells

AB

READ – reads output of macrocells AB

WRITE – loads macrocell flip-flops

20

21

Output Macrocells

BC

READ – reads output of macrocells BC

WRITE – loads macrocell flip-flops

21

23

Mask Macrocells AB 22

Mask Macrocells BC

22

23

Blocks writing to the Output Macrocells AB

Blocks writing to the Output Macrocells BC

Primary Flash

Protection

C0

C2

Read only – Primary Flash Sector Protection

Secondary Flash

memory Protection

Read only – PSD Security and Secondary Flash

memory Sector Protection

JTAG Enable

PMMR0

PMMR2

Page

C7

B0

B4

E0

Enables JTAG Port

Power Management Register 0

Power Management Register 2

Page Register

Places PSD memory areas in Program and/or

Data space on an individual basis.

VM

E2

Note: 1. Other registers that are not part of the I/O ports.

18/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

DETAILED OPERATION

As shown in Figure 5., page 14, the PSD consists

of six major types of functional blocks:

Memory Blocks

The PSD has the following memory blocks:

■

Memory Blocks

–

Primary Flash memory

Optional Secondary Flash memory

Optional SRAM

PLD Blocks

MCU Bus Interface

I/O Ports

Power Management Unit (PMU)

JTAG Interface

The Memory Select signals for these blocks origi-

nate from the Decode PLD (DPLD) and are user-

defined in PSDsoft Express.

The functions of each block are described in the

following sections. Many of the blocks perform

multiple functions, and are user configurable.

Table 8. Memory Block Size and Organization

Primary Flash Memory

Secondary Flash Memory

SRAM

Sector

Number

Sector Size

(Bytes)

Sector Select

Signal

Sector Size

(Bytes)

Sector Select

Signal

SRAM Size

(Bytes)

SRAM Select

Signal

0

1

32K

512K

FS0

FS1

16K

CSBOOT0

CSBOOT1

CSBOOT2

CSBOOT3

256K

RS0

2

FS2

3

FS3

4

FS4

5

FS5

6

FS6

7

FS7

Total

8 Sectors

64K

4 Sectors

256K

19/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Primary Flash Memory and Secondary Flash

memory Description

Memory Operation. The primary Flash memory

and secondary Flash memory are addressed

through the MCU Bus Interface. The MCU can ac-

cess these memories in one of two ways:

The primary Flash memory is divided evenly into

eight equal sectors. The secondary Flash memory

is divided into four equal sectors. Each sector of

either memory block can be separately protected

from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec-

tor basis. Flash sector erasure may be suspended

while data is read from other sectors of the block

and then resumed after reading.

During a Program or Erase cycle in Flash memory,

the status can be output on Ready/Busy (PC3).

This pin is set up using PSDsoft Express Configu-

ration.

–

The MCU can execute a typical bus WRITE or

READ operation just as it would if accessing a

RAM or ROM device using standard bus

cycles.

The MCU can execute a specific instruction

that consists of several WRITE and READ

operations. This involves writing specific data

patterns to special addresses within the Flash

memory to invoke an embedded algorithm.

These instructions are summarized in Table

9., page 21.

Typically, the MCU can read Flash memory using

READ operations, just as it would read a ROM de-

vice. However, Flash memory can only be altered

using specific Erase and Program instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as it would write a byte to

RAM. To program a byte into Flash memory, the

MCU must execute a Program instruction, then

test the status of the Program cycle. This status

test is achieved by a READ operation or polling

Ready/Busy (PC3).

Memory Block Select Signals

The DPLD generates the Select signals for all the

internal memory blocks (see the section entitled

PLDS, page 33). Each of the eight sectors of the

primary Flash memory has a Select signal (FS0-

FS7) which can contain up to three product terms.

Each of the four sectors of the secondary Flash

memory has

a

Select signal (CSBOOT0-

CSBOOT3) which can contain up to three product

terms. Having three product terms for each Select

signal allows a given sector to be mapped in differ-

ent areas of system memory. When using a MCU

with separate Program and Data space, these

flexible Select signals allow dynamic re-mapping

of sectors from one memory space to the other.

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

Ready/Busy (PC3). This signal can be used to

output the Ready/Busy status of the PSD. The out-

put on Ready/Busy (PC3) is a 0 (Busy) when Flash

memory is being written to, or when Flash memory

is being erased. The output is a 1 (Ready) when

no WRITE or Erase cycle is in progress.

20/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 9. Instructions

FS0-FS7 or

Instruction

CSBOOT0-

Cycle 1

Cycle 2 Cycle 3

Cycle 4

Cycle 5 Cycle 6 Cycle 7

CSBOOT3

“READ”

RD @ RA

5

1

READ

Read Main

AAh@

X555h

55h@

XAAAh

90h@

X555h

Read identifier

(A6,A1,A0 = 0,0,1)

6

Flash ID

Read Sector

AAh@

X555h

55h@

XAAAh

90h@

X555h

Read identifier

(A6,A1,A0 = 0,1,0)

6,8,13

Protection

Program a

Flash Byte

AAh@

X555h

55h@

XAAAh

A0h@

X555h

PD@ PA

13

7

Flash Sector

AAh@

X555h

55h@

XAAAh

80h@

X555h

55h@

XAAAh

30h@

SA

30h @

AAh@ X555h

7,13

Erase

next SA

Flash Bulk

AAh@

X555h

55h@

XAAAh

80h@

X555h

55h@

XAAAh

10h@

X555h

13

Erase

Suspend

B0h@

XXXXh

11

12

Sector Erase

Resume

30h@

XXXXh

1

Sector Erase

F0h@

XXXXh

6

Reset

AAh@

X555h

55h@

XAAAh

20h@

X555h

Unlock Bypass

A0h@

XXXXh

PD@ PA

9

Program

Unlock Bypass

90h@

XXXXh

00h@

XXXXh

1

10

Reset

Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label

2. All values are in hexadecimal:

X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses

RA = Address of the memory location to be read

RD = Data read from location RA during the READ cycle

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).

PA is an even address for PSD in word programming mode.

PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0)

SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be

erased, or verified, must be Active (High).

3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.

4. Only address bits A11-A0 are used in instruction decoding.

5. No Unlock or instruction cycles are required when the device is in the READ Mode

6. The Reset instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Sta-

tus, or if the Error Flag Bit (DQ5/DQ13) goes High.

7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.

8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and

(A1,A0)=(1,0)

9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.

10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass

mode.

11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status

when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.

12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.

13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is

intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status

of the primary Flash memory.

21/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

INSTRUCTIONS

An instruction consists of a sequence of specific

operations. Each received byte is sequentially de-

coded by the PSD and not executed as a standard

WRITE operation. The instruction is executed

when the correct number of bytes are properly re-

ceived and the time between two consecutive

bytes is shorter than the time-out period. Some in-

structions are structured to include READ opera-

tions after the initial WRITE operations.

The instruction must be followed exactly. Any in-

valid combination of instruction bytes or time-out

between two consecutive bytes while addressing

Flash memory resets the device logic into READ

Mode (Flash memory is read like a ROM device).

for maximum security of the data contents and to

remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

WRITE cycle initiation is locked when V

is be-

CC

low V

.

LKO

READ

Under typical conditions, the MCU may read the

primary Flash memory or the secondary Flash

memory using READ operations just as it would a

ROM or RAM device. Alternately, the MCU may

use READ operations to obtain status information

about a Program or Erase cycle that is currently in

progress. Lastly, the MCU may use instructions to

read special data from these memory blocks. The

following sections describe these READ functions.

The PSD supports the instructions summarized in

Table 9., page 21:

Read Memory Contents

Flash memory:

Primary Flash memory and secondary Flash

memory are placed in the READ Mode after Pow-

er-up, chip reset, or a Reset Flash instruction (see

Table 9., page 21). The MCU can read the memo-

ry contents of the primary Flash memory or the

secondary Flash memory by using READ opera-

tions any time the READ operation is not part of an

instruction.

■

Erase memory by chip or sector

Suspend or resume sector erase

Program a Byte

Reset to READ Mode

Read primary Flash Identifier value

Read Sector Protection Status

Read Primary Flash Identifier

Bypass (on the PSD833F2, PSD834F2,

PSD853F2 and PSD854F2)

The primary Flash memory identifier is read with

an instruction composed of 4 operations: 3 specific

WRITE operations and a READ operation (see Ta-

ble 9., page 21). During the READ operation, ad-

dress bits A6, A1, and A0 must be '0,0,1,'

respectively, and the appropriate Sector Select

(FS0-FS7) must be High. The identifier for the

PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or

PSD85xF2 it is E7h.

These instructions are detailed in Table

9., page 21. For efficient decoding of the instruc-

tions, the first two bytes of an instruction are the

coded cycles and are followed by an instruction

byte or confirmation byte. The coded cycles con-

sist of writing the data AAh to address X555h dur-

ing the first cycle and data 55h to address XAAAh

during the second cycle. Address signals A15-A12

are Don’t Care during the instruction WRITE cy-

cles. However, the appropriate Sector Select

(FS0-FS7 or CSBOOT0-CSBOOT3) must be se-

lected.

The primary and secondary Flash memories have

the same instruction set (except for Read Primary

Flash Identifier). The Sector Select signals deter-

mine which Flash memory is to receive and exe-

cute the instruction. The primary Flash memory is

selected if any one of Sector Select (FS0-FS7) is

High, and the secondary Flash memory is selected

if any one of Sector Select (CSBOOT0-

CSBOOT3) is High.

Read Memory Sector Protection Status

The primary Flash memory Sector Protection Sta-

tus is read with an instruction composed of 4 oper-

ations: 3 specific WRITE operations and a READ

operation (see Table 9., page 21). During the

READ operation, address Bits A6, A1, and A0

must be '0,1,0,' respectively, while Sector Select

(FS0-FS7 or CSBOOT0-CSBOOT3) designates

the Flash memory sector whose protection has to

be verified. The READ operation produces 01h if

the Flash memory sector is protected, or 00h if the

sector is not protected.

The sector protection status for all NVM blocks

(primary Flash memory or secondary Flash mem-

ory) can also be read by the MCU accessing the

Flash Protection registers in PSD I/O space. See

the section entitled Flash Memory Sector

Protect, page 28 for register definitions.

Power-up Mode

The PSD internal logic is reset upon Power-up to

the READ Mode. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must be held Low, and

Write Strobe (WR, CNTL0) High, during Power-up

22/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Reading the Erase/Program Status Bits

The PSD provides several status bits to be used

by the MCU to confirm the completion of an Erase

or Program cycle of Flash memory. These status

bits minimize the time that the MCU spends per-

forming these tasks and are defined in Table 10.

The status bits can be read as many times as

needed.

For Flash memory, the MCU can perform a READ

operation to obtain these status bits while an

Erase or Program instruction is being executed by

the embedded algorithm. See the section entitled

PROGRAMMING FLASH MEMORY, page 25 for

details.

Table 10. Status Bit

FS0-FS7/CSBOOT0-

Functional Block

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

CSBOOT3

Erase

Time-

out

Data

Polling Flag

Toggle Error

Flag

V

Flash Memory

X

IH

Note: 1. X = Not guaranteed value, can be read either '1' or ’0.’

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.

3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.

23/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Data Polling Flag (DQ7)

When erasing or programming in Flash memory,

the Data Polling Flag Bit (DQ7) outputs the com-

plement of the bit being entered for programming/

writing on the DQ7 Bit. Once the Program instruc-

tion or the WRITE operation is completed, the true

logic value is read on the Data Polling Flag Bit

(DQ7, in a READ operation).

–

The Toggle Flag Bit (DQ6) is effective after the

fourth WRITE pulse (for a Program instruction)

or after the sixth WRITE pulse (for an Erase

instruction).

If the byte to be programmed belongs to a

protected Flash memory sector, the

instruction is ignored.

If all the Flash memory sectors selected for

erasure are protected, the Toggle Flag Bit

(DQ6) toggles to '0' for about 100µs and then

returns to the previous addressed byte.

–

Data Polling is effective after the fourth WRITE

pulse (for a Program instruction) or after the

sixth WRITE pulse (for an Erase instruction). It

must be performed at the address being

programmed or at an address within the Flash

memory sector being erased.

Error Flag (DQ5)

During a normal Program or Erase cycle, the Error

Flag Bit (DQ5) is to ’0.’ This bit is set to '1' when

there is a failure during Flash memory Byte Pro-

gram, Sector Erase, or Bulk Erase cycle.

In the case of Flash memory programming, the Er-

ror Flag Bit (DQ5) indicates the attempt to program

a Flash memory bit from the programmed state,

’0,’ to the erased state, '1,' which is not valid. The

Error Flag Bit (DQ5) may also indicate a Time-out

condition while attempting to program a byte.

In case of an error in a Flash memory Sector Erase

or Byte Program cycle, the Flash memory sector in

which the error occurred or to which the pro-

grammed byte belongs must no longer be used.

Other Flash memory sectors may still be used.

The Error Flag Bit (DQ5) is reset after a Reset

Flash instruction.

–

During an Erase cycle, the Data Polling Flag

Bit (DQ7) outputs a ’0.’ After completion of the

cycle, the Data Polling Flag Bit (DQ7) outputs

the last bit programmed (it is a '1' after

erasing).

–

If the byte to be programmed is in a protected

Flash memory sector, the instruction is

ignored.

If all the Flash memory sectors to be erased

are protected, the Data Polling Flag Bit (DQ7)

is reset to '0' for about 100µs, and then returns

to the previous addressed byte. No erasure is

performed.

Toggle Flag (DQ6)

The PSD offers another way for determining when

the Flash memory Program cycle is completed.

During the internal WRITE operation and when ei-

ther the FS0-FS7 or CSBOOT0-CSBOOT3 is true,

the Toggle Flag Bit (DQ6) toggles from '0' to '1' and

'1' to '0' on subsequent attempts to read any byte

of the memory.

When the internal cycle is complete, the toggling

stops and the data read on the Data Bus D0-D7 is

the addressed memory byte. The device is now

accessible for a new READ or WRITE operation.

The cycle is finished when two successive READs

yield the same output data.

Erase Time-out Flag (DQ3)

The Erase Time-out Flag Bit (DQ3) reflects the

time-out period allowed between two consecutive

Sector Erase instructions. The Erase Time-out

Flag Bit (DQ3) is reset to '0' after a Sector Erase

cycle for a time period of 100µs + 20% unless an

additional Sector Erase instruction is decoded. Af-

ter this time period, or when the additional Sector

Erase instruction is decoded, the Erase Time-out

Flag Bit (DQ3) is set to '1.'

24/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PROGRAMMING FLASH MEMORY

Flash memory must be erased prior to being pro-

grammed. A byte of Flash memory is erased to all

1s (FFh), and is programmed by setting selected

bits to ’0.’ The MCU may erase Flash memory all

at once or by-sector, but not byte-by-byte. Howev-

er, the MCU may program Flash memory byte-by-

byte.

The primary and secondary Flash memories re-

quire the MCU to send an instruction to program a

byte or to erase sectors (see Table 9., page 21).

Once the MCU issues a Flash memory Program or

Erase instruction, it must check for the status bits

for completion. The embedded algorithms that are

invoked inside the PSD support several means to

provide status to the MCU. Status may be checked

using any of three methods: Data Polling, Data

Toggle, or Ready/Busy (PC3).

ming algorithm has completed, to compare the

byte that was written to the Flash memory with the

byte that was intended to be written.

When using the Data Polling method during an

Erase cycle, Figure 7 still applies. However, the

Data Polling Flag Bit (DQ7) is '0' until the Erase cy-

cle is complete. A 1 on the Error Flag Bit (DQ5) in-

dicates a time-out condition on the Erase cycle; a

0 indicates no error. The MCU can read any loca-

tion within the sector being erased to get the Data

Polling Flag Bit (DQ7) and the Error Flag Bit

(DQ5).

PSDsoft Express generates ANSI C code func-

tions which implement these Data Polling algo-

rithms.

Figure 7. Data Polling Flowchart

Data Polling

Polling on the Data Polling Flag Bit (DQ7) is a

method of checking whether a Program or Erase

cycle is in progress or has completed. Figure 7

shows the Data Polling algorithm.

START

READ DQ5 & DQ7

at VALID ADDRESS

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location of the byte to be pro-

grammed in Flash memory to check status. The

Data Polling Flag Bit (DQ7) of this location be-

comes the complement of b7 of the original data

byte to be programmed. The MCU continues to

poll this location, comparing the Data Polling Flag

Bit (DQ7) and monitoring the Error Flag Bit (DQ5).

When the Data Polling Flag Bit (DQ7) matches b7

of the original data, and the Error Flag Bit (DQ5)

remains ’0,’ the embedded algorithm is complete.

If the Error Flag Bit (DQ5) is '1,' the MCU should

test the Data Polling Flag Bit (DQ7) again since

the Data Polling Flag Bit (DQ7) may have changed

simultaneously with the Error Flag Bit (DQ5, see

Figure 7).

DQ7

=

YES

DATA

NO

DQ5

= 1

YES

READ DQ7

DQ7

=

DATA

YES

NO

The Error Flag Bit (DQ5) is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the byte or if the MCU at-

tempted to program a '1' to a bit that was not

erased (not erased is logic '0').

FAIL

PASS

AI01369B

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

25/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Data Toggle

Checking the Toggle Flag Bit (DQ6) is a method of

determining whether a Program or Erase cycle is

in progress or has completed. Figure 8 shows the

Data Toggle algorithm.

The Flash memory then enters the Unlock Bypass

mode. A two-cycle Unlock Bypass Program in-

struction is all that is required to program in this

mode. The first cycle in this instruction contains

the Unlock Bypass Program code, A0h. The sec-

ond cycle contains the program address and data.

Additional data is programmed in the same man-

ner. These instructions dispense with the initial

two Unlock cycles required in the standard Pro-

gram instruction, resulting in faster total Flash

memory programming.

During the Unlock Bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset Flash

instructions are valid.

To exit the Unlock Bypass mode, the system must

issue the two-cycle Unlock Bypass Reset Flash in-

struction. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

Don’t Care for both cycles. The Flash memory

then returns to READ Mode.

When the MCU issues a Program instruction, the

embedded algorithm within the PSD begins. The

MCU then reads the location of the byte to be pro-

grammed in Flash memory to check status. The

Toggle Flag Bit (DQ6) of this location toggles each

time the MCU reads this location until the embed-

ded algorithm is complete. The MCU continues to

read this location, checking the Toggle Flag Bit

(DQ6) and monitoring the Error Flag Bit (DQ5).

When the Toggle Flag Bit (DQ6) stops toggling

(two consecutive reads yield the same value), and

the Error Flag Bit (DQ5) remains ’0,’ the embed-

ded algorithm is complete. If the Error Flag Bit

(DQ5) is '1,' the MCU should test the Toggle Flag

Bit (DQ6) again, since the Toggle Flag Bit (DQ6)

may have changed simultaneously with the Error

Flag Bit (DQ5, see Figure 8).

The Error Flag Bit (DQ5) is set if either an internal

time-out occurred while the embedded algorithm

attempted to program the byte, or if the MCU at-

tempted to program a '1' to a bit that was not

erased (not erased is logic '0').

Figure 8. Data Toggle Flowchart

START

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

byte that was written to Flash memory with the

byte that was intended to be written.

When using the Data Toggle method after an

Erase cycle, Figure 8 still applies. the Toggle Flag

Bit (DQ6) toggles until the Erase cycle is complete.

A '1' on the Error Flag Bit (DQ5) indicates a time-

out condition on the Erase cycle; a '0' indicates no

error. The MCU can read any location within the

sector being erased to get the Toggle Flag Bit

(DQ6) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code func-

tions which implement these Data Toggling algo-

rithms.

Unlock Bypass (PSD833F2x, PSD834F2x,

PSD853F2x, PSD854F2x)

The Unlock Bypass instructions allow the system

to program bytes to the Flash memories faster

than using the standard Program instruction. The

Unlock Bypass mode is entered by first initiating

two Unlock cycles. This is followed by a third

WRITE cycle containing the Unlock Bypass code,

20h (as shown in Table 9., page 21).

READ

DQ5 & DQ6

DQ6

NO

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

DQ6

=

NO

TOGGLE

YES

FAIL

PASS

AI01370B

26/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

ERASING FLASH MEMORY

Flash Bulk Erase

The Flash Bulk Erase instruction uses six WRITE

operations followed by a READ operation of the

status register, as described in Table 9., page 21.

If any byte of the Bulk Erase instruction is wrong,

the Bulk Erase instruction aborts and the device is

reset to the Read Flash memory status.

During execution of the Erase cycle, the Flash

memory accepts only Reset and Suspend Sector

Erase instructions. Erasure of one Flash memory

sector may be suspended, in order to read data

from another Flash memory sector, and then re-

sumed.

During a Bulk Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in the section entitled PRO-

GRAMMING FLASH MEMORY, page 25. The Er-

ror Flag Bit (DQ5) returns a '1' if there has been an

Erase Failure (maximum number of Erase cycles

have been executed).

It is not necessary to program the memory with

00h because the PSD automatically does this be-

fore erasing to 0FFh.

During execution of the Bulk Erase instruction, the

Flash memory does not accept any instructions.

Suspend Sector Erase

When a Sector Erase cycle is in progress, the Sus-

pend Sector Erase instruction can be used to sus-

pend the cycle by writing 0B0h to any address

when an appropriate Sector Select (FS0-FS7 or

CSBOOT0-CSBOOT3) is High. (See Table

9., page 21). This allows reading of data from an-

other Flash memory sector after the Erase cycle

has been suspended. Suspend Sector Erase is

accepted only during an Erase cycle and defaults

to READ Mode. A Suspend Sector Erase instruc-

tion executed during an Erase time-out period, in

addition to suspending the Erase cycle, terminates

the time out period.

Flash Sector Erase

The Toggle Flag Bit (DQ6) stops toggling when the

PSD internal logic is suspended. The status of this

bit must be monitored at an address within the

Flash memory sector being erased. The Toggle

Flag Bit (DQ6) stops toggling between 0.1µs and

15µs after the Suspend Sector Erase instruction

has been executed. The PSD is then automatically

set to READ Mode.

The Sector Erase instruction uses six WRITE op-

erations, as described in Table 9., page 21. Addi-

tional Flash Sector Erase codes and Flash

memory sector addresses can be written subse-

quently to erase other Flash memory sectors in

parallel, without further coded cycles, if the addi-

tional bytes are transmitted in a shorter time than

the time-out period of about 100µs. The input of a

new Sector Erase code restarts the time-out peri-

od.

If an Suspend Sector Erase instruction was exe-

cuted, the following rules apply:

–

Attempting to read from a Flash memory

sector that was being erased outputs invalid

data.

Reading from a Flash sector that was not

being erased is valid.

The Flash memory cannot be programmed,

and only responds to Resume Sector Erase

and Reset Flash instructions (READ is an

operation and is allowed).

If a Reset Flash instruction is received, data in

the Flash memory sector that was being

erased is invalid.

The status of the internal timer can be monitored

through the level of the Erase Time-out Flag Bit

(DQ3). If the Erase Time-out Flag Bit (DQ3) is ’0,’

the Sector Erase instruction has been received

and the time-out period is counting. If the Erase

Time-out Flag Bit (DQ3) is '1,' the time-out period

has expired and the PSD is busy erasing the Flash

memory sector(s). Before and during Erase time-

out, any instruction other than Suspend Sector

Erase and Resume Sector Erase instructions

abort the cycle that is currently in progress, and re-

set the device to READ Mode. It is not necessary

to program the Flash memory sector with 00h as

the PSD does this automatically before erasing

(byte = FFh).

–

Resume Sector Erase

If a Suspend Sector Erase instruction was previ-

ously executed, the erase cycle may be resumed

with this instruction. The Resume Sector Erase in-

struction consists of writing 030h to any address

while an appropriate Sector Select (FS0-FS7 or

CSBOOT0-CSBOOT3) is High. (See Table

9., page 21.)

During a Sector Erase, the memory status may be

checked by reading the Error Flag Bit (DQ5), the

Toggle Flag Bit (DQ6), and the Data Polling Flag

Bit (DQ7), as detailed in the section entitled PRO-

GRAMMING FLASH MEMORY, page 25.

27/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SPECIFIC FEATURES

Flash Memory Sector Protect

Each primary and secondary Flash memory sector

can be separately protected against Program and

Erase cycles. Sector Protection provides addition-

al data security because it disables all Program or

Erase cycles. This mode can be activated through

the JTAG Port or a Device Programmer.

Sector protection can be selected for each sector

using the PSDsoft Express Configuration pro-

gram. This automatically protects selected sectors

when the device is programmed through the JTAG

Port or a Device Programmer. Flash memory sec-

tors can be unprotected to allow updating of their

contents using the JTAG Port or a Device Pro-

grammer. The MCU can read (but cannot change)

the sector protection bits.

Any attempt to program or erase a protected Flash

memory sector is ignored by the device. The Verify

operation results in a READ of the protected data.

This allows a guarantee of the retention of the Pro-

tection status.

The sector protection status can be read by the

MCU through the Flash memory protection and

PSD/EE protection registers (in the CSIOP block).

See Tables 11 and 12.

On the PSD813F2/3/4/5, the Reset Flash instruc-

tion puts the Flash memory back into normal

READ Mode. It may take the Flash memory up to

a few milliseconds to complete the Reset cycle.

The Reset Flash instruction is ignored when it is is-

sued during a Program or Bulk Erase cycle of the

Flash memory. The Reset Flash instruction aborts

any on-going Sector Erase cycle, and returns the

Flash memory to the normal READ Mode within a

few milliseconds.

On the PSD83xF2 or PSD85xF2, the Reset Flash

instruction puts the Flash memory back into nor-

mal READ Mode. If an Error condition has oc-

curred (and the device has set the Error Flag Bit

(DQ5) to '1') the Flash memory is put back into nor-

mal READ Mode within 25µs of the Reset Flash in-

struction having been issued. The Reset Flash

instruction is ignored when it is issued during a

Program or Bulk Erase cycle of the Flash memory.

The Reset Flash instruction aborts any on-going

Sector Erase cycle, and returns the Flash memory

to the normal READ Mode within 25µs.

Reset (RESET) Signal (on the PSD83xF2 and

PSD85xF2)

A pulse on Reset (RESET) aborts any cycle that is

in progress, and resets the Flash memory to the

READ Mode. When the reset occurs during a Pro-

gram or Erase cycle, the Flash memory takes up

to 25µs to return to the READ Mode. It is recom-

mended that the Reset (RESET) pulse (except for

Power On Reset, as described on RESET TIMING

AND DEVICE STATUS AT RESET, page 67) be

at least 25µs so that the Flash memory is always

ready for the MCU to fetch the bootstrap instruc-

tions after the Reset cycle is complete.

Reset Flash

The Reset Flash instruction consists of one

WRITE cycle (see Table 9., page 21). It can also

be optionally preceded by the standard two

WRITE decoding cycles (writing AAh to 555h and

55h to AAAh). It must be executed after:

–

Reading the Flash Protection Status or Flash

ID

–

An Error condition has occurred (and the

device has set the Error Flag Bit (DQ5) to '1')

during a Flash memory Program or Erase

cycle.

Table 11. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot

Sec6_Prot

Sec5_Prot

Sec4_Prot

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Note: 1. Bit Definitions:

Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected.

Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write protected.

Table 12. Sector Protection/Security Bit Definition – PSD/EE Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_Bit not used

Note: 1. Bit Definitions:

not used

Sec3_Prot

Sec2_Prot

Sec1_Prot

Sec0_Prot

Sec_Prot 1 = Secondary Flash memory Sector is write protected.

Sec_Prot 0 = Secondary Flash memory Sector is not write protected.

Security_Bit 0 = Security Bit in device has not been set.

1 = Security Bit in device has been set.

28/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SRAM

The SRAM is enabled when SRAM Select (RS0)

from the DPLD is High. SRAM Select (RS0) can

contain up to two product terms, allowing flexible

memory mapping.

PC4 can be configured as an output that indicates

when power is being drawn from the external bat-

tery. Battery-on Indicator (VBATON, PC4) is High

with the supply voltage falls below the battery volt-

age and the battery on Voltage Stand-by (V

PC2) is supplying power to the internal SRAM.

,

STBY

The SRAM can be backed up using an external

battery. The external battery should be connected

to Voltage Stand-by (V

, PC2). If you have an

SRAM Select (RS0), Voltage Stand-by (V

,

STBY

external battery connected to the PSD, the con-

tents of the SRAM are retained in the event of a

power loss. The contents of the SRAM are re-

tained so long as the battery voltage remains at

2 V or greater. If the supply voltage falls below the

battery voltage, an internal power switch-over to

the battery occurs.

PC2) and Battery-on Indicator (VBATON, PC4)

are all configured using PSDsoft Express Configu-

ration.

29/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

SECTOR SELECT AND SRAM SELECT

Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)

and SRAM Select (RS0) are all outputs of the

DPLD. They are setup by writing equations for

them in PSDabel. The following rules apply to the

equations for these signals:

1. Primary Flash memory and secondary Flash

memory Sector Select signals must not be

larger than the physical sector size.

This is controlled through manipulation of the VM

register that resides in the CSIOP space.

The VM register is set using PSDsoft Express to

have an initial value. It can subsequently be

changed by the MCU so that memory mapping

can be changed on-the-fly.

For example, you may wish to have SRAM and pri-

mary Flash memory in the Data space at Boot-up,

and secondary Flash memory in the Program

space at Boot-up, and later swap the primary and

secondary Flash memories. This is easily done

with the VM register by using PSDsoft Express

Configuration to configure it for Boot-up and hav-

ing the MCU change it when desired. Table

13., page 31 describes the VM Register.

2. Any primary Flash memory sector must not be

mapped in the same memory space as

another Flash memory sector.

3. A secondary Flash memory sector must notbe

mapped in the same memory space as

another secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not overlap.

Figure 9. Priority Level of Memory and I/O

Components

5. A secondary Flash memory sector may

overlap a primary Flash memory sector. In

case of overlap, priority is given to the

secondary Flash memory sector.

6. SRAM, I/O, and Peripheral I/O spaces may

overlap any other memory sector. Priority is

given to the SRAM, I/O, or Peripheral I/O.

Highest Priority

Level 1

SRAM, I/O, or

Peripheral I/O

Example

FS0 is valid when the address is in the range of

8000h to BFFFh, CSBOOT0 is valid from 8000h to

9FFFh, and RS0 is valid from 8000h to 87FFh.

Any address in the range of RS0 always accesses

the SRAM. Any address in the range of CSBOOT0

greater than 87FFh (and less than 9FFFh) auto-

matically addresses secondary Flash memory

segment 0. Any address greater than 9FFFh ac-

cesses the primary Flash memory segment 0. You

can see that half of the primary Flash memory seg-

ment 0 and one-fourth of secondary Flash memory

segment 0 cannot be accessed in this example.

Also note that an equation that defined FS1 to any-

where in the range of 8000h to BFFFh would not

be valid.

Figure 9 shows the priority levels for all memory

components. Any component on a higher level can

overlap and has priority over any component on a

lower level. Components on the same level must

not overlap. Level one has the highest priority and

level 3 has the lowest.

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

Lowest Priority

AI02867D

Configuration Modes for MCUs with Separate

Program and Data Spaces

Separate Space Modes. Program space is sep-

arated from Data space. For example, Program

Select Enable (PSEN, CNTL2) is used to access

the program code from the primary Flash memory,

while Read Strobe (RD, CNTL1) is used to access

data from the secondary Flash memory, SRAM

and I/O Port blocks. This configuration requires

the VM register to be set to 0Ch (see Figure

10., page 31).

Combined Space Modes. The Program and

Data spaces are combined into one memory

space that allows the primary Flash memory, sec-

ondary Flash memory, and SRAM to be accessed

by either Program Select Enable (PSEN, CNTL2)

or Read Strobe (RD, CNTL1). For example, to

configure the primary Flash memory in Combined

space, Bits b2 and b4 of the VM register are set to

'1' (see Figure 11., page 31).

Memory Select Configuration for MCUs with

Separate Program and Data Spaces

The 8031 and compatible family of MCUs, which

includes the 80C51, 80C151, 80C251, and

80C51XA, have separate address spaces for Pro-

gram memory (selected using Program Select En-

able (PSEN, CNTL2)) and Data memory (selected

using Read Strobe (RD, CNTL1)). Any of the

memories within the PSD can reside in either

space or both spaces.

30/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 10. 8031 Memory Modules – Separate Space

Primary

Flash

Secondary

Flash

SRAM

DPLD

RS0

Memory

CSBOOT0-3

FS0-FS7

CS

OE

CS

OE

PSEN

RD

AI02869C

Figure 11. 8031 Memory Modules – Combined Space

Primary

Flash

Secondary

Flash

SRAM

DPLD

RS0

Memory

RD

CSBOOT0-3

FS0-FS7

CS

OE

CS

OE

VM REG BIT 3

VM REG BIT 4

PSEN

VM REG BIT 1

RD

VM REG BIT 2

VM REG BIT 0

AI02870C

Table 13. VM Register

Bit 7

Bit 4

Primary

FL_Data

Bit 3

Secondary

EE_Data

Bit 2

Primary

FL_Code

Bit 1

Secondary

EE_Code

Bit 0

SRAM_Code

Bit 6

Bit 5

PIO_EN

0 = RD can’t

access

Secondary Flash

memory

0 = PSEN

can’t access

Flash

0 = PSEN can’t

access

Secondary Flash

memory

0 = RD

can’t access

Flash memory

0 = PSEN

can’t access

SRAM

0 = disable

PIO mode

not

used

not

used

memory

1 = PSEN

access

Flash

1 = RD

access Flash

memory

1 = RD access

Secondary Flash

memory

1 = PSEN access

Secondary Flash

memory

1 = PSEN

access

SRAM

1= enable

PIO mode

not

used

not

used

memory

31/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PAGE REGISTER

The 8-bit Page Register increases the addressing

capability of the MCU by a factor of up to 256. The

contents of the register can also be read by the

MCU. The outputs of the Page Register (PGR0-

PGR7) are inputs to the DPLD decoder and can be

included in the Sector Select (FS0-FS7,

CSBOOT0-CSBOOT3), and SRAM Select (RS0)

equations.

If memory paging is not needed, or if not all 8 page

register bits are needed for memory paging, then

these bits may be used in the CPLD for general

logic. See Application Note AN1154.

Figure 12 shows the Page Register. The eight flip-

flops in the register are connected to the internal

data bus D0-D7. The MCU can write to or read

from the Page Register. The Page Register can be

accessed at address location CSIOP + E0h.

Figure 12. Page Register

RESET

PGR0

INTERNAL

SELECTS

AND LOGIC

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

PGR1

PGR2

D0 - D7

DPLD

AND

CPLD

PGR3

PGR4

PGR5

PGR6

PGR7

R/W

PAGE

REGISTER

PLD

AI02871B

32/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PLDS

The PLDs bring programmable logic functionality

to the PSD. After specifying the logic for the PLDs

using the PSDabel tool in PSDsoft Express, the

logic is programmed into the device and available

upon Power-up.

Additionally, five bits are available in PMMR2 to

block MCU control signals from entering the PLDs.

This reduces power consumption and can be used

only when these MCU control signals are not used

in PLD logic equations.

The PSD contains two PLDs: the Decode PLD

(DPLD), and the Complex PLD (CPLD). The PLDs

are briefly discussed in the next few paragraphs,

and in more detail in the section entitled Decode

PLD (DPLD), page 35 and the section entitled

Each of the two PLDs has unique characteristics

suited for its applications. They are described in

the following sections.

Table 14. DPLD and CPLD Inputs

Number

Complex

PLD

(CPLD), page 36.

Figure

13., page 34 shows the configuration of the PLDs.

Input Source

Input Name

of

The DPLD performs address decoding for Select

signals for internal components, such as memory,

registers, and I/O ports.

Signals

1

A15-A0

16

MCU Address Bus

The CPLD can be used for logic functions, such as

loadable counters and shift registers, state ma-

chines, and encoding and decoding logic. These

logic functions can be constructed using the 16

Output Macrocells (OMC), 24 Input Macrocells

(IMC), and the AND Array. The CPLD can also be

used to generate External Chip Select (ECS0-

ECS2) signals.

The AND Array is used to form product terms.

These product terms are specified using PSDabel.

An Input Bus consisting of 73 signals is connected

to the PLDs. The signals are shown in Table 14.

MCU Control Signals

Reset

CNTL2-CNTL0

RST

3

1

Power-down

PDN

Port A Input

Macrocells

PA7-PA0

PB7-PB0

PC7-PC0

8

Port B Input

Macrocells

Port C Input

Macrocells

The Turbo Bit in PSD

Port D Inputs

Page Register

PD2-PD0

3

8

The PLDs in the PSD can minimize power con-

sumption by switching off when inputs remain un-

changed for an extended time of about 70ns.

Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) au-

tomatically places the PLDs into standby if no in-

puts are changing. Turning the Turbo mode off

increases propagation delays while reducing pow-

er consumption. See the section entitled POWER

MANAGEMENT, page 62 on how to set the Turbo

Bit.

PGR7-PGR0

Macrocell AB

Feedback

MCELLAB.FB7-

FB0

8

Macrocell BC

Feedback

MCELLBC.FB7-

FB0

Secondary Flash

memory Program

Status Bit

Ready/Busy

1

Note: 1. The address inputs are A19-A4 in 80C51XA mode.

33/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 13. PLD Diagram

I / O P O R T S

P L D I N P U T B U S

34/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Decode PLD (DPLD)

The DPLD, shown in Figure 14, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

■

1 internal SRAM Select (RS0) signal (two

product terms)

1 internal CSIOP Select (PSD Configuration

Register) signal

1 JTAG Select signal (enables JTAG on Port

C)

2 internal Peripheral Select signals

(Peripheral I/O mode).

■

8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

■

4 Sector Select (CSBOOT0-CSBOOT3)

signals for the secondary Flash memory (three

product terms each)

Figure 14. DPLD Logic Array

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

3

(INPUTS)

(24)

3

FS0

FS1

FS2

FS3

FS4

FS5

I/O PORTS (PORT A,B,C)

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

(8)

8 PRIMARY FLASH

MEMORY SECTOR SELECTS

PGR0 -PGR7

(16)

(3)

[

]

A 15:0

*

[

]

PD 2:0 (ALE,CLKIN,CSI)

PDN (APD OUTPUT)

FS6

FS7

(1)

(3)

(1)

[

] (

CNTRL 2:0 READ/WRITE CONTROL SIGNALS)

RESET

RS0

2

1

SRAM SELECT

RD_BSY

CSIOP

I/O DECODER

SELECT

PSEL0

1

PERIPHERAL I/O MODE

SELECT

PSEL1

JTAGSEL

AI02873D

35/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Complex PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. The CPLD can

also be used to generate three External Chip Se-

lect (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can

be produced by any Output Macrocell (OMC),

these three External Chip Select (ECS0-ECS2) on

Port D do not consume any Output Macrocells

(OMC).

■

Product Term Allocator

AND Array capable of generating up to 137

product terms

■

Four I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the PSD internal data bus

and can be directly accessed by the MCU. This

enables the MCU software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macrocell architectures.

As shown in Figure 13., page 34, the CPLD has

the following blocks:

■

24 Input Macrocells (IMC)

16 Output Macrocells (OMC)

Macrocell Allocator

Figure 15. Macrocell and I/O Port

PRODUCT TERMS

FROM OTHER

MACROCELLS

MCU ADDRESS / DATA BUS

TO OTHER I/O PORTS

CPLD MACROCELLS

I/O PORTS

DATA

LOAD

CONTROL

LATCHED

ADDRESS OUT

PT PRESET

MCU DATA IN

MCU LOAD

PRODUCT TERM

ALLOCATOR

I/O PIN

DATA

D

Q

MUX

WR

UP TO 10

PRODUCT TERMS

MACROCELL

OUT TO

MCU

CPLD OUTPUT

POLARITY

SELECT

PR DI LD

D/T

SELECT

Q

PT

CPLD

OUTPUT

PDR

CLOCK

INPUT

D/T/JK FF

SELECT

COMB.

/REG

SELECT

GLOBAL

CLOCK

MACROCELL

CK

TO

I/O PORT

ALLOC.

CL

CLOCK

SELECT

Q

DIR

REG.

D

WR

PT CLEAR

(

)

PT OUTPUT ENABLE OE

MACROCELL FEEDBACK

I/O PORT INPUT

INPUT MACROCELLS

Q

D

PT INPUT LATCH GATE/CLOCK

D

G

ALE/AS

AI02874

36/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con-

nected to Ports A and B pins and are named as

McellAB0-McellAB7. The other eight macrocells

are connected to Ports B and C pins and are

named as McellBC0-McellBC7. If an McellAB out-

put is not assigned to a specific pin in PSDabel,

the Macrocell Allocator block assigns it to either

Port A or B. The same is true for a McellBC output

on Port B or C. Table 15 shows the macrocells and

port assignment.

The Output Macrocell (OMC) architecture is

shown in Figure 16., page 39. As shown in the fig-

ure, there are native product terms available from

the AND Array, and borrowed product terms avail-

able (if unused) from other Output Macrocells

(OMC). The polarity of the product term is con-

trolled by the XOR gate. The Output Macrocell

(OMC) can implement either sequential logic, us-

ing the flip-flop element, or combinatorial logic.

The multiplexer selects between the sequential or

combinatorial logic outputs. The multiplexer output

can drive a port pin and has a feedback path to the

AND Array inputs.

The flip-flop in the Output Macrocell (OMC) block

can be configured as a D, T, JK, or SR type in the

PSDabel program. The flip-flop’s clock, preset,

and clear inputs may be driven from a product

term of the AND Array. Alternatively, CLKIN (PD1)

can be used for the clock input to the flip-flop. The

flip-flop is clocked on the rising edge of CLKIN

(PD1). The preset and clear are active High inputs.

Each clear input can use up to two product terms.

Table 15. Output Macrocell Port and Data Bit Assignments

Output

Macrocell

Port

Assignment

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

Native Product Terms

McellAB0

McellAB1

McellAB2

McellAB3

McellAB4

McellAB5

McellAB6

McellAB7

McellBC0

McellBC1

McellBC2

McellBC3

McellBC4

McellBC5

McellBC6

McellBC7

Port A0, B0

Port A1, B1

Port A2, B2

Port A3, B3

Port A4, B4

Port A5, B5

Port A6, B6

Port A7, B7

Port B0, C0

Port B1, C1

Port B2, C2

Port B3, C3

Port B4, C4

Port B5, C5

Port B6, C6

Port B7, C7

3

4

6

5

6

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

37/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Product Term Allocator

The CPLD has a Product Term Allocator. The PS-

Dabel compiler uses the Product Term Allocator to

borrow and place product terms from one macro-

cell to another. The following list summarizes how

product terms are allocated:

Data can be loaded to the Output Macrocells

(OMC) on the trailing edge of Write Strobe (WR,

CNTL0) (edge loading) or during the time that

Write Strobe (WR, CNTL0) is active (level load-

ing). The method of loading is specified in PSDsoft

Express Configuration.

■

McellAB0-McellAB7 all have three native

product terms and may borrow up to six more

McellBC0-McellBC3 all have four native

product terms and may borrow up to five more

The OMC Mask Register

There is one Mask Register for each of the two

groups of eight Output Macrocells (OMC). The

Mask Registers can be used to block the loading

of data to individual Output Macrocells (OMC).

The default value for the Mask Registers is 00h,

which allows loading of the Output Macrocells

(OMC). When a given bit in a Mask Register is set

to a 1, the MCU is blocked from writing to the as-

sociated Output Macrocells (OMC). For example,

suppose McellAB0-McellAB3 are being used for a

state machine. You would not want a MCU write to

McellAB to overwrite the state machine registers.

Therefore, you would want to load the Mask Reg-

ister for McellAB (Mask Macrocell AB) with the val-

ue 0Fh.

McellBC4-McellBC7 all have four native

product terms and may borrow up to six more.

Each macrocell may only borrow product terms

from certain other macrocells. Product terms al-

ready in use by one macrocell are not available for

another macrocell.

If an equation requires more product terms than

are available to it, then “external” product terms

are required, which consume other Output Macro-

cells (OMC). If external product terms are used,

extra delay is added for the equation that required

the extra product terms.

This is called product term expansion. PSDsoft

Express performs this expansion as needed.

Loading and Reading the Output Macrocells

(OMC)

The Output Enable of the OMC

The Output Macrocells (OMC) block can be con-

nected to an I/O port pin as a PLD output. The out-

put enable of each port pin driver is controlled by

a single product term from the AND Array, ORed

with the Direction Register output. The pin is en-

abled upon Power-up if no output enable equation

is defined and if the pin is declared as a PLD out-

put in PSDsoft Express.

If the Output Macrocell (OMC) output is declared

as an internal node and not as a port pin output in

the PSDabel file, the port pin can be used for other

I/O functions. The internal node feedback can be

routed as an input to the AND Array.

The Output Macrocells (OMC) block occupies a

memory location in the MCU address space, as

defined by the CSIOP block (see the section enti-

tled I/O PORTS, page 51). The flip-flops in each of

the 16 Output Macrocells (OMC) can be loaded

from the data bus by a MCU. Loading the Output

Macrocells (OMC) with data from the MCU takes

priority over internal functions. As such, the preset,

clear, and clock inputs to the flip-flop can be over-

ridden by the MCU. The ability to load the flip-flops

and read them back is useful in such applications

as loadable counters and shift registers, mailbox-

es, and handshaking protocols.

38/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 16. CPLD Output Macrocell

A N D A R R A Y

P L D I N P U T B U S

39/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Input Macrocells (IMC)

The CPLD has 24 Input Macrocells (IMC), one for

each pin on Ports A, B, and C. The architecture of

the Input Macrocells (IMC) is shown in Figure

17., page 41. The Input Macrocells (IMC) are indi-

vidually configurable, and can be used as a latch,

register, or to pass incoming Port signals prior to

driving them onto the PLD input bus. The outputs

of the Input Macrocells (IMC) can be read by the

MCU through the internal data bus.

Input Macrocells (IMC) can use Address Strobe

(ALE/AS, PD0) to latch address bits higher than

A15. Any latched addresses are routed to the

PLDs as inputs.

Input Macrocells (IMC) are particularly useful with

handshaking communication applications where

two processors pass data back and forth through

a common mailbox. Figure 18., page 42 shows a

typical configuration where the Master MCU writes

to the Port A Data Out Register. This, in turn, can

be read by the Slave MCU via the activation of the

“Slave-Read” output enable product term.

The Slave can also write to the Port A Input Mac-

rocells (IMC) and the Master can then read the In-

put Macrocells (IMC) directly.

Note that the “Slave-Read” and “Slave-Wr” signals

are product terms that are derived from the Slave

MCU inputs Read Strobe (RD, CNTL1), Write

Strobe (WR, CNTL0), and Slave_CS.

The enable for the latch and clock for the register

are driven by a multiplexer whose inputs are a

product term from the CPLD AND Array or the

MCU Address Strobe (ALE/AS). Each product

term output is used to latch or clock four Input

Macrocells (IMC). Port inputs 3-0 can be con-

trolled by one product term and 7-4 by another.

Configurations for the Input Macrocells (IMC) are

specified by equations written in PSDabel (see Ap-

plication Note AN1171). Outputs of the Input Mac-

rocells (IMC) can be read by the MCU via the IMC

buffer.

See

the

section

entitled

I/O

PORTS, page 51.

40/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 17. Input Macrocell

A N D A R R A Y

P L D I N P U T B U S

41/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 18. Handshaking Communication Using Input Macrocells

42/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

MCU BUS INTERFACE

The “no-glue logic” MCU Bus Interface block can

be directly connected to most popular MCUs and

their control signals. Key 8-bit MCUs, with their

bus types and control signals, are shown in Table

16. The interface type is specified using the PSD-

soft Express Configuration.

Table 16. MCUs and their Control Signals

Data Bus

2

MCU

CNTL0 CNTL1 CNTL2

PC7

ADIO0 PA3-PA0 PA7-PA3

PD0

ALE

Width

1

8031

8

WR

R/W

WR

R/W

RD

PSEN

RD

E

PSEN

A0

A4

A0

(Note )

1

80C51XA

80C251

80198

ALE

AS

A3-A0

(Note )

1

(Note ) (Note )

(Note )

1

PSEN

(Note )

1

(Note ) (Note )

(Note )

1

68HC11

68HC912

Z80

(Note ) (Note )

(Note )

1

E

DBE

AS

(Note )

1

RD

DS

E

D3-D0

D7-D4

(Note ) (Note ) (Note )

1

Z8

AS

(Note ) (Note )

(Note )

1

68330

AS

(Note ) (Note )

(Note )

1

M37702M2

ALE

D3-D0

D7-D4

(Note ) (Note )

Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-

tions.

2. ALE/AS input is optional for MCUs with a non-multiplexed bus

43/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD Interface to a Multiplexed 8-Bit Bus

Figure 19 shows an example of a system using a

MCU with an 8-bit multiplexed bus and a PSD. The

ADIO port on the PSD is connected directly to the

MCU address/data bus. Address Strobe (ALE/AS,

PD0) latches the address signals internally.

Latched addresses can be brought out to Port A or

B. The PSD drives the ADIO data bus only when

one of its internal resources is accessed and Read

Strobe (RD, CNTL1) is active. Should the system

address bus exceed sixteen bits, Ports A, B, C, or

D may be used as additional address inputs.

Figure 19. An Example of a Typical 8-bit Multiplexed Bus Interface

MCU

PSD

[

]

AD 7:0

[

]

A 7:0

PORT

A

(

)

OPTIONAL

ADIO

PORT

[

]

A 15:8

[

]

A 15:8

PORT

B

OPTIONAL

(

)

WR

RD

WR CNTRL0

(

)

RD CNTRL1

(

)

BHE

BHE CNTRL2

PORT

C

RST

ALE

(

)

ALE PD0

PORT D

RESET

AI02878C

44/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD Interface to a Non-Multiplexed 8-Bit Bus

MCU Bus Interface Examples

Figure 20 shows an example of a system using a

MCU with an 8-bit non-multiplexed bus and a

PSD. The address bus is connected to the ADIO

Port, and the data bus is connected to Port A. Port

A is in tri-state mode when the PSD is not access-

ed by the MCU. Should the system address bus

exceed sixteen bits, Ports B, C, or D may be used

for additional address inputs.

Figure 21 through 25 show examples of the basic

connections between the PSD and some popular

MCUs. The PSD Control input pins are labeled as

to the MCU function for which they are configured.

The MCU bus interface is specified using the PS-

Dsoft Express Configuration.

Table 17. Eight-Bit Data Bus

Data Byte Enable Reference

BHE

X

A0

0

D7-D0

Even Byte

Odd Byte

MCUs have different data byte orientations. Table

17 shows how the PSD interprets byte/word oper-

ations in different bus WRITE configurations.

Even-byte refers to locations with address A0

equal to '0' and odd byte as locations with A0 equal

to ’1.’

X

1

Figure 20. An Example of a Typical 8-bit Non-Multiplexed Bus Interface

PSD

MCU

[

]

D 7:0

[

]

D 7:0

PORT

A

ADIO

PORT

[

]

A 15:0

[

]

A 23:16

PORT

B

(OPTIONAL)

(

)

WR

RD

WR CNTRL0

(

)

RD CNTRL1

(

)

BHE

BHE CNTRL2

RST

PORT

C

ALE

(

)

ALE PD0

PORT D

RESET

AI02879C

45/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

80C31

Figure 21 shows the bus interface for the 80C31,

which has an 8-bit multiplexed address/data bus.

The lower address byte is multiplexed with the

data bus. The MCU control signals Program Se-

lect Enable (PSEN, CNTL2), Read Strobe (RD,

CNTL1), and Write Strobe (WR, CNTL0) may be

used for accessing the internal memory and I/O

Ports blocks. Address Strobe (ALE/AS, PD0)

latches the address.

Figure 21. Interfacing the PSD with an 80C31

AD7-AD0

[

]

AD 7:0

PSD

80C31

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

29

30

31

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

31

39

38

37

36

35

34

33

32

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

28

27

25

24

23

22

21

EA/VP

X1

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

32

33

34

35

36

37

19

18

9

X2

RESET

12

13

14

15

INT0

INT1

T0

21

22

23

24

25

26

27

28

A8

A9

39

40

41

42

43

44

45

46

7

6

5

4

3

2

52

51

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

ADIO8

ADIO9

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

A10

A11

A12

A13

A14

A15

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

T1

1

2

3

4

5

6

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

17

16

RD

WR

20

19

18

17

14

13

12

11

WR

47

50

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

CNTL0(WR)

CNTL1(RD)

7

8

29

30

11

10

PSEN

ALE

PSEN

ALE/P

TXD

49

CNTL2(PSEN)

10

9

RXD

PD0-ALE

PD1

8

PD2

RESET

48

RESET

AI02880C

46/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

80C251

The Intel 80C251 MCU features a user-config-

urable bus interface with four possible bus config-

urations, as shown in Table 18., page 48.

The 80C251 has two major operating modes:

Page mode and Non-page mode. In Non-page

mode, the data is multiplexed with the lower ad-

dress byte, and Address Strobe (ALE/AS, PD0) is

active in every bus cycle. In Page mode, data (D7-

D0) is multiplexed with address (A15-A8). In a bus

cycle where there is a Page hit, Address Strobe

(ALE/AS, PD0) is not active and only addresses

(A7-A0) are changing. The PSD supports both

modes. In Page Mode, the PSD bus timing is iden-

tical to Non-Page Mode except the address hold

time and setup time with respect to Address

Strobe (ALE/AS, PD0) is not required. The PSD

access time is measured from address (A7-A0)

valid to data in valid.

The first configuration is 80C31-compatible, and

the bus interface to the PSD is identical to that

shown in Figure 21., page 46. The second and

third configurations have the same bus connection

as shown in Figure 22. There is only one Read

Strobe (PSEN) connected to CNTL1 on the PSD.

The A16 connection to PA0 allows for a larger ad-

dress input to the PSD. The fourth configuration is

shown in Figure 23., page 48. Read Strobe (RD) is

connected to CNTL1 and Program Select Enable

(PSEN) is connected to CNTL2.

Figure 22. Interfacing the PSD with the 80C251, with One READ Input

PSD

80C251SB

43

42

41

40

39

38

37

36

A0

A1

A2

A3

A4

A5

A6

A7

30

31

32

33

34

35

36

37

A0

A1

A2

A3

A4

A5

A6

A7

2

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

A16

29

28

27

25

24

23

22

21

3

4

5

6

7

8

9

PA0

PA1

PA2

PA3

PA4

PA5

1

A17

PA6

PA7

24

25

26

AD8

AD9

AD10

21

20

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

X1

X2

AD8

39

40

41

42

43

44

45

46

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

7

6

5

4

3

2

52

51

AD9

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

27

28

AD11

AD12

AD10

AD11

AD12

AD13

AD14

AD15

11

13

14

15

16

17

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

29

30

AD13

AD14

AD15

31

P2.7

ALE

RD

47

50

33

32

P3.5/T1

(

)

CNTL0 WR

ALE

10

RST

RESET

(

)

CNTL1 RD

PSEN

20

19

18

17

14

13

12

11

18

19

WR

A16

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

WR

RD/A16

35

49

CNTL2(PSEN)

EA

10

9

8

PD0-ALE

PD1

PD2

48

RESET

AI02881C

Note: 1. The A16 and A17 connections are optional.

2. In non-Page-Mode, AD7-AD0 connects to ADIO7-ADIO0.

47/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs

80C251SB

PSD

43

42

41

40

39

38

37

36

A0

A1

A2

A3

A4

A5

A6

A7

30

31

32

33

34

35

36

37

A0

A1

A2

A3

A4

A5

A6

A7

2

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

29

28

27

25

24

23

22

21

3

4

5

6

7

8

9

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

24

25

26

AD8

AD9

AD10

21

20

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

X1

X2

AD8

39

40

41

42

43

44

45

46

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

7

6

5

4

3

2

52

51

AD9

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

27

28

AD11

AD12

AD10

AD11

AD12

AD13

AD14

AD15

11

13

14

15

16

17

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

29

30

AD13

AD14

AD15

31

P2.7

P3.5/T1

33

32

ALE

RD

47

50

(

)

CNTL0 WR

ALE

10

RST

EA

RESET

(

)

CNTL1 RD

PSEN

20

19

18

17

14

13

12

11

18

19

WR

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

WR

RD/A16

PSEN

35

49

CNTL2(PSEN)

10

9

8

PD0-ALE

PD1

PD2

48

RESET

AI02882C

Table 18. 80C251 Configurations

80C251 READ/WRITE

Pins

Configuration

Connecting to PSD Pins

Page Mode

WR

RD

PSEN

CNTL0

CNTL1

CNTL2

Non-Page Mode, 80C31 compatible A7-

A0 multiplex with D7-D0

1

WR

PSEN only

CNTL0

CNTL1

Non-Page Mode

A7-A0 multiplex with D7-D0

2

3

WR

PSEN only

CNTL0

CNTL1

Page Mode

A15-A8 multiplex with D7-D0

WR

RD

PSEN

CNTL0

CNTL1

CNTL2

Page Mode

A15-A8 multiplex with D7-D0

4

48/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

80C51XA

The Philips 80C51XA MCU family supports an 8-

or 16-bit multiplexed bus that can have burst cy-

cles. Address bits (A3-A0) are not multiplexed,

while (A19-A4) are multiplexed with data bits

(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)

are multiplexed with data bits (D7-D0).

The 80C51XA can be configured to operate in

eight-bit data mode (as shown in Figure 24).

The 80C51XA improves bus throughput and per-

formance by executing burst cycles for code fetch-

es. In Burst Mode, address A19-A4 are latched

internally by the PSD, while the 80C51XA changes

the A3-A0 signals to fetch up to 16 bytes of code.

The PSD access time is then measured from ad-

dress A3-A0 valid to data in valid. The PSD bus

timing requirement in Burst Mode is identical to the

normal bus cycle, except the address setup and

hold time with respect to Address Strobe (ALE/AS,

PD0) does not apply.

Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus

80C51XA

PSD

21

20

30

31

32

33

34

35

36

37

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

2

3

4

A0

A1

A2

A3

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

A12

A13

A14

A15

A16

A17

A18

A19

XTAL1

XTAL2

ADIO0

A0/WRH

A1

29 A0

ADIO1

ADIO2

ADIO3

AD104

AD105

ADIO6

ADIO7

PA0

PA1

28 A1

27 A2

25 A3

24

23

22

A2

A3

A4D0

A5D1

A6D2

A7D3

A8D4

A9D5

A10D6

A11D7

A12D8

A13D9

A14D10

A15D11

A16D12

A17D13

A18D14

A19D15

5

PA2

43

42

41

40

39

PA3

PA4

PA5

PA6

11

13

6

RXD0

TXD0

RXD1

TXD1

7

21

PA7

38

37

A12

A13

A14

A15

A16

A17

A18

A19

39

40

41

42

43

44

45

46

ADIO8

ADIO9

9

8

16

7

36

24

25

26

27

28

29

30

31

T2EX

T2

T0

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

6

5

4

3

2

52

51

ADIO10

ADIO11

AD1012

AD1013

ADIO14

ADIO15

10

RST

INT0

INT1

RESET

14

15

47

50

(

)

CNTL0 WR

20

19

18

17

14

13

12

11

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

(

)

CNTL1 RD

PSEN

32

49

35

17

PSEN

RD

CNTL2(PSEN)

EA/WAIT

BUSW

19

18

33

RD

WR

10

8

9

PD0-ALE

PD1

WRL

ALE

PD2

48

RESET

AI02883C

49/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

68HC11

Figure 25 shows a bus interface to a 68HC11

where the PSD is configured in 8-bit multiplexed

mode with E and R/W settings. The DPLD can be

used to generate the READ and WR signals for

external devices.

Figure 25. Interfacing the PSD with a 68HC11

AD7-AD0

29

PSD

30

31

32

33

34

35

36

37

AD0

AD1

ADIO0

ADIO1

ADIO2

ADIO3

AD104

AD105

ADIO6

ADIO7

PA0

28

27

25

24

23

22

21

68HC11

PA1

PA2

PA3

PA4

PA5

PA6

PA7

AD2

AD3

AD4

AD5

AD6

AD7

31

PA3

PA4

PA5

PA6

PA7

8

7

30

29

28

27

XT

EX

17

19

18

RESET

IRQ

39

40

41

42

43

44

45

46

7

6

5

4

3

2

52

51

XIRQ

42

41

40

39

38

37

36

35

A8

A9

A10

A11

A12

A13

A14

A15

ADIO8

ADIO9

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

2

MODB

ADIO10

ADIO11

AD1012

AD1013

ADIO14

ADIO15

34

33

32

PA0

PA1

PA2

9

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

43

44

45

46

47

48

49

50

20

19

18

17

14

13

12

11

10

11

12

13

14

15

16

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PC0

PC1

PC2

PC3

PC4

47

50

_

CNTL0(R W)

CNTL1(E)

49

CNTL2

PC5

PC6

PC7

10

9

8

PD0 AS

–

PD1

PD2

20

21

22

23

24

25

52

51

PD0

PD1

PD2

PD3

PD4

PD5

VRH

VRL

48

RESET

3

MODA

5

4

6

E

AS

R/W

AS

R/W

RESET

AI02884C

50/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

I/O PORTS

There are four programmable I/O ports: Ports A, B,

C, and D. Each of the ports is eight bits except Port

D, which is 3 bits. Each port pin is individually user

configurable, thus allowing multiple functions per

port. The ports are configured using PSDsoft Ex-

press Configuration or by the MCU writing to on-

chip registers in the CSIOP space.

The Port pin’s tri-state output driver enable is con-

trolled by a two input OR gate whose inputs come

from the CPLD AND Array enable product term

and the Direction Register. If the enable product

term of any of the Array outputs are not defined

and that port pin is not defined as a CPLD output

in the PSDabel file, then the Direction Register has

sole control of the buffer that drives the port pin.

The topics discussed in this section are:

The contents of these registers can be altered by

the MCU. The Port Data Buffer (PDB) feedback

path allows the MCU to check the contents of the

registers.

Ports A, B, and C have embedded Input Macro-

cells (IMC). The Input Macrocells (IMC) can be

configured as latches, registers, or direct inputs to

the PLDs. The latches and registers are clocked

by Address Strobe (ALE/AS, PD0) or a product

term from the PLD AND Array. The outputs from

the Input Macrocells (IMC) drive the PLD input bus

and can be read by the MCU. See the section en-

titled Input Macrocell, page 41.

■

General Port architecture

Port operating modes

Port Configuration Registers (PCR)

Port Data Registers

Individual Port functionality.

General Port Architecture

The general architecture of the I/O Port block is

shown in Figure 26., page 52. Individual Port ar-

chitectures are shown in Figure 28., page 58 to

Figure 31., page 61. In general, once the purpose

for a port pin has been defined, that pin is no long-

er available for other purposes. Exceptions are

noted.

Port Operating Modes

The I/O Ports have several modes of operation.

Some modes can be defined using PSDabel,

some by the MCU writing to the Control Registers

in CSIOP space, and some by both. The modes

that can only be defined using PSDsoft Express

must be programmed into the device and cannot

be changed unless the device is reprogrammed.

The modes that can be changed by the MCU can

be done so dynamically at run-time. The PLD I/O,

Data Port, Address Input, and Peripheral I/O

modes are the only modes that must be defined

before programming the device. All other modes

can be changed by the MCU at run-time. See Ap-

plication Note AN1171 for more detail.

As shown in Figure 26., page 52, the ports contain

an output multiplexer whose select signals are

driven by the configuration bits in the Control Reg-

isters (Ports A and B only) and PSDsoft Express

Configuration. Inputs to the multiplexer include the

following:

■

Output data from the Data Out register

Latched address outputs

CPLD macrocell output

External Chip Select (ECS0-ECS2) from the

CPLD.

The Port Data Buffer (PDB) is a tri-state buffer that

allows only one source at a time to be read. The

Port Data Buffer (PDB) is connected to the Internal

Data Bus for feedback and can be read by the

MCU. The Data Out and macrocell outputs, Direc-

tion and Control Registers, and port pin input are

all connected to the Port Data Buffer (PDB).

Table 19., page 53 summarizes which modes are

available on each port. Table 22., page 56 shows

how and where the different modes are config-

ured. Each of the port operating modes are de-

scribed in the following sections.

51/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 26. General I/O Port Architecture

DATA OUT

REG.

DATA OUT

D

Q

WR

ADDRESS

ALE

ADDRESS

PORT PIN

D

G

Q

OUTPUT

MUX

MACROCELL OUTPUTS

EXT CS

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

CONTROL REG.

ENABLE OUT

D

Q

WR

DIR REG.

D

Q

(

)

ENABLE PRODUCT TERM .OE

INPUT

MACROCELL

CPLD-INPUT

AI02885

52/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

MCU I/O Mode

In the MCU I/O mode, the MCU uses the I/O Ports

block to expand its own I/O ports. By setting up the

CSIOP space, the ports on the PSD are mapped

into the MCU address space. The addresses of

the ports are listed in Table 7., page 18.

A port pin can be put into MCU I/O mode by writing

a 0 to the corresponding bit in the Control Regis-

ter. The MCU I/O direction may be changed by

writing to the corresponding bit in the Direction

Register, or by the output enable product term.

See the section entitled Peripheral I/O

Mode, page 55. When the pin is configured as an

output, the content of the Data Out Register drives

the pin. When configured as an input, the MCU

can read the port input through the Data In buffer.

See Figure 26., page 52.

corresponding bit in the Direction Register to ’0.’

The corresponding bit in the Direction Register

must not be set to '1' if the pin is defined for a PLD

input signal in PSDabel. The PLD I/O mode is

specified in PSDabel by declaring the port pins,

and then writing an equation assigning the PLD I/

O to a port.

Address Out Mode

For MCUs with a multiplexed address/data bus,

Address Out Mode can be used to drive latched

addresses on to the port pins. These port pins can,

in turn, drive external devices. Either the output

enable or the corresponding bits of both the Direc-

tion Register and Control Register must be set to

a 1 for pins to use Address Out Mode. This must

be done by the MCU at run-time. See Table 21 for

the address output pin assignments on Ports A

and B for various MCUs.

Ports C and D do not have Control Registers, and

are in MCU I/O mode by default. They can be used

for PLD I/O if equations are written for them in PS-

Dabel.

For non-multiplexed 8-bit bus mode, address sig-

nals (A7-A0) are available to Port B in Address Out

Mode.

PLD I/O Mode

The PLD I/O Mode uses a port as an input to the

CPLD’s Input Macrocells (IMC), and/or as an out-

put from the CPLD’s Output Macrocells (OMC).

The output can be tri-stated with a control signal.

This output enable control signal can be defined

by a product term from the PLD, or by resetting the

Note: Do not drive address signals with Address

Out Mode to an external memory device if it is in-

tended for the MCU to Boot from the external de-

vice. The MCU must first Boot from PSD memory

so the Direction and Control register bits can be

set.

Table 19. Port Operating Modes

Port Mode

MCU I/O

Port A

Port B

Port C

Port D

Yes

PLD I/O

McellAB Outputs

McellBC Outputs

Additional Ext. CS Outputs No

Yes

No

Yes

No

Yes

No

Yes

PLD Inputs

Yes

Yes (A7 – 0)

or (A15 – 8)

Address Out

Yes (A7 – 0)

No

Address In

Data Port

Yes

No

Yes

No

Yes

No

Yes (D7 – 0)

Peripheral I/O

JTAG ISP

Yes

No

1

Yes

Note: 1. Can be multiplexed with other I/O functions.

53/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 20. Port Operating Mode Settings

Control

Direction

Register

Setting

VM

Defined in

PSDabel

Defined in PSD

Configuration

Mode

Register

Setting

Register JTAG Enable

Setting

1 = output,

0 = input

1

MCU I/O

Declare pins only

0

N/A

2

(Note )

2

PLD I/O

Logic equations

N/A

(Note )

Data Port (Port A)

Specify bus type

N/A

Address Out

(Port A,B)

2

Declare pins only

N/A

1

N/A

1 (Note )

Address In

(Port A,B,C,D)

Logic for equation

Input Macrocells

N/A

Peripheral I/O

(Port A)

Logic equations

(PSEL0 & 1)

PIO bit = 1 N/A

N/A JTAG_Enable

JTAG

Configuration

3

JTAGSEL

JTAG ISP (Note )

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port C.

Table 21. I/O Port Latched Address Output Assignments

MCU

Port A (PA3-PA0)

Port A (PA7-PA4)

Port B (PB3-PB0)

Port B (PB7-PB4)

N/A

1

8051XA (8-Bit)

Address a7-a4

Address a11-a8

N/A

80C251

(Page Mode)

N/A

Address a11-a8

Address a3-a0

Address a15-a12

Address a7-a4

All Other

8-Bit Multiplexed

Address a3-a0

N/A

Address a7-a4

N/A

8-Bit

Non-Multiplexed Bus

Note: 1. N/A = Not Applicable.

54/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Peripheral I/O Mode

Address In Mode

For MCUs that have more than 16 address sig-

nals, the higher addresses can be connected to

Port A, B, C, and D. The address input can be

latched in the Input Macrocell (IMC) by Address

Strobe (ALE/AS, PD0). Any input that is included

in the DPLD equations for the SRAM, or primary or

secondary Flash memory is considered to be an

address input.

Peripheral I/O mode can be used to interface with

external peripherals. In this mode, all of Port A

serves as a tri-state, bi-directional data buffer for

the MCU. Peripheral I/O Mode is enabled by set-

ting Bit 7 of the VM Register to a ’1.’ Figure 27

shows how Port A acts as a bi-directional buffer for

the MCU data bus if Peripheral I/O Mode is en-

abled. An equation for PSEL0 and/or PSEL1 must

be written in PSDabel. The buffer is tri-stated

when PSEL0 or PSEL1 is not active.

Data Port Mode

Port A can be used as a data bus port for a MCU

with a non-multiplexed address/data bus. The

Data Port is connected to the data bus of the MCU.

The general I/O functions are disabled in Port A if

the port is configured as a Data Port.

Figure 27. Peripheral I/O Mode

RD

PSEL0

PSEL

PSEL1

D0-D7

VM REGISTER BIT 7

PA0-PA7

DATA BUS

WR

AI02886

55/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

JTAG In-System Programming (ISP)

Drive Select Register

Port C is JTAG compliant, and can be used for In-

System Programming (ISP). You can multiplex

JTAG operations with other functions on Port C

because In-System Programming (ISP) is not per-

formed in normal Operating mode. For more infor-

mation on the JTAG Port, see the section entitled

PROGRAMMING IN-CIRCUIT USING THE JTAG

SERIAL INTERFACE, page 69.

The Drive Select Register configures the pin driver

as Open Drain or CMOS for some port pins, and

controls the slew rate for the other port pins. An

external pull-up resistor should be used for pins

configured as Open Drain.

A pin can be configured as Open Drain if its corre-

sponding bit in the Drive Select Register is set to a

’1.’ The default pin drive is CMOS.

Port Configuration Registers (PCR)

Note that the slew rate is a measurement of the

rise and fall times of an output. A higher slew rate

means a faster output response and may create

more electrical noise. A pin operates in a high slew

rate when the corresponding bit in the Drive Reg-

ister is set to ’1.’ The default rate is slow slew.

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal READ/WRITE bus cycles at the addresses

given in Table 7., page 18. The addresses in Ta-

ble 7 are the offsets in hexadecimal from the base

of the CSIOP register.

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 22, are used for setting the

Port configurations. The default Power-up state for

each register in Table 22 is 00h.

Table 26., page 57 shows the Drive Register for

Ports A, B, C, and D. It summarizes which pins can

be configured as Open Drain outputs and which

pins the slew rate can be set for.

Table 22. Port Configuration Registers (PCR)

Register Name

Control

Port

MCU Access

WRITE/READ

A,B

Control Register

Direction

A,B,C,D

Any bit reset to '0' in the Control Register sets the

corresponding port pin to MCU I/O Mode, and a '1'

sets it to Address Out Mode. The default mode is

MCU I/O. Only Ports A and B have an associated

Control Register.

1

Drive Select

Note: 1. See Table 26., page 57 for Drive Register bit definition.

Table 23. Port Pin Direction Control, Output

Enable P.T. Not Defined

Direction Register

The Direction Register, in conjunction with the out-

put enable (except for Port D), controls the direc-

tion of data flow in the I/O Ports. Any bit set to '1'

in the Direction Register causes the correspond-

ing pin to be an output, and any bit set to '0' causes

it to be an input. The default mode for all port pins

is input.

Figure 28., page 58 and Figure 29., page 59 show

the Port Architecture diagrams for Ports A/B and

C, respectively. The direction of data flow for Ports

A, B, and C are controlled not only by the direction

register, but also by the output enable product

term from the PLD AND Array. If the output enable

product term is not active, the Direction Register

has sole control of a given pin’s direction.

Direction Register Bit

Port Pin Mode

0

1

Input

Output

Table 24. Port Pin Direction Control, Output

Enable P.T. Defined

Direction

Register Bit

Output Enable

P.T.

Port Pin Mode

0

1

0

Input

1

0

1

Output

An example of a configuration for a Port with the

three least significant bits set to output and the re-

mainder set to input is shown in Table 25. Since

Port D only contains three pins (shown in Figure

31., page 61), the Direction Register for Port D

has only the three least significant bits active.

Table 25. Port Direction Assignment Example

Bit 7 Bit6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0

0

1

56/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 26. Drive Register Pin Assignment

Drive

Register

Bit 7

Bit 6

Bit 5

Bit 4

Open

Bit 3

Slew

Bit 2

Slew

Bit 1

Slew

Bit 0

Slew

Open

Port A

Port B

Port C

Port D

Drain

Rate

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Slew

Rate

Slew

Rate

Slew

Rate

Slew

Rate

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Slew

Rate

Slew

Rate

Slew

Rate

1

NA

Note: 1. NA = Not Applicable.

Port Data Registers

Output Macrocells (OMC). The CPLD Output

Macrocells (OMC) occupy a location in the MCU’s

address space. The MCU can read the output of

the Output Macrocells (OMC). If the OMC Mask

Register bits are not set, writing to the macrocell

loads data to the macrocell flip-flops. See the sec-

tion entitled PLDS, page 33.

The Port Data Registers, shown in Table 27, are

used by the MCU to write data to or read data from

the ports. Table 27 shows the register name, the

ports having each register type, and MCU access

for each register type. The registers are described

below.

OMC Mask Register

Data In

Each OMC Mask Register bit corresponds to an

Output Macrocell (OMC) flip-flop. When the OMC

Mask Register bit is set to a 1, loading data into the

Output Macrocell (OMC) flip-flop is blocked. The

default value is 0 or unblocked.

Port pins are connected directly to the Data In buff-

er. In MCU I/O input mode, the pin input is read

through the Data In buffer.

Data Out Register

Stores output data written by the MCU in the MCU

I/O output mode. The contents of the Register are

driven out to the pins if the Direction Register or

the output enable product term is set to ’1.’ The

contents of the register can also be read back by

the MCU.

Table 27. Port Data Registers

Register Name

Port

A,B,C,D

MCU Access

Data In

READ – input on pin

Data Out

A,B,C,D

A,B,C

WRITE/READ

READ – outputs of macrocells

WRITE – loading macrocells flip-flop

Output Macrocell

Mask Macrocell

WRITE/READ – prevents loading into a given

macrocell

A,B,C

Input Macrocell

Enable Out

A,B,C

READ – outputs of the Input Macrocells

READ – the output enable control of the port driver

57/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Input Macrocells (IMC)

Ports A and B – Functionality and Structure

The Input Macrocells (IMC) can be used to latch or

store external inputs. The outputs of the Input

Macrocells (IMC) are routed to the PLD input bus,

and can be read by the MCU. See the section en-

titled PLDS, page 33.

Ports A and B have similar functionality and struc-

ture, as shown in Figure 28. The two ports can be

configured to perform one or more of the following

functions:

■

MCU I/O Mode

Enable Out

■

CPLD Output – Macrocells McellAB7-

McellAB0 can be connected to Port A or Port

B. McellBC7-McellBC0 can be connected to

Port B or Port C.

CPLD Input – Via the Input Macrocells (IMC).

Latched Address output – Provide latched

address output as per Table 21., page 54.

The Enable Out register can be read by the MCU.

It contains the output enable values for a given

port. A 1 indicates the driver is in output mode. A

0 indicates the driver is in tri-state and the pin is in

input mode.

■

Address In – Additional high address inputs

using the Input Macrocells (IMC).

Open Drain/Slew Rate – pins PA3-PA0 and

PB3-PB0 can be configured to fast slew rate,

pins PA7-PA4 and PB7-PB4 can be

configured to Open Drain Mode.

■

Data Port – Port A to D7-D0 for 8 bit non-

multiplexed bus

Multiplexed Address/Data port for certain

types of MCU bus interfaces.

Peripheral Mode – Port A only

Figure 28. Port A and Port B Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT

A OR B PIN

ADDRESS

ALE

ADDRESS

D

G

Q

[

]

[

]

A 7:0 OR A 15:8

OUTPUT

MUX

MACROCELL OUTPUTS

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

CONTROL REG.

ENABLE OUT

D

Q

WR

DIR REG.

D

Q

(

)

ENABLE PRODUCT TERM .OE

CPLD-INPUT

INPUT

MACROCELL

AI02887

58/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Port C – Functionality and Structure

Port C can be configured to perform one or more

of the following functions (see Figure 29):

■

Open Drain – Port C pins can be configured in

Open Drain Mode

Battery Backup features – PC2 can be

■

MCU I/O Mode

configured for a battery input supply, Voltage

■

CPLD Output – McellBC7-McellBC0 outputs

can be connected to Port B or Port C.

Stand-by (V ).

STBY

PC4 can be configured as a Battery-on Indicator

(V ), indicating when V is less than

■

CPLD Input – via the Input Macrocells (IMC)

Address In – Additional high address inputs

using the Input Macrocells (IMC).

BATON

CC

V

.

BAT

Port C does not support Address Out mode, and

therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in

certain MCU bus interfaces.

■

In-System Programming (ISP) – JTAG port

can be enabled for programming/erase of the

PSD device. (See the section entitled

PROGRAMMING IN-CIRCUIT USING THE

JTAG SERIAL INTERFACE, page 69 for

more information on JTAG programming.)

Figure 29. Port C Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT C PIN

1

SPECIAL FUNCTION

OUTPUT

MUX

[

]

MCELLBC 7:0

READ MUX

P

D

B

OUTPUT

SELECT

DATA IN

ENABLE OUT

DIR REG.

D

Q

WR

(

)

ENABLE PRODUCT TERM .OE

INPUT

MACROCELL

1

SPECIAL FUNCTION

CPLD-INPUT

CONFIGURATION

BIT

AI02888B

59/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Port D – Functionality and Structure

Port D has three I/O pins. See Figure 30 and Fig-

ure 31., page 61. This port does not support Ad-

dress Out mode, and therefore no Control

Register is required. Port D can be configured to

perform one or more of the following functions:

■

Slew rate – pins can be set up for fast slew

rate

Port D pins can be configured in PSDsoft Express

as input pins for other dedicated functions:

■

Address Strobe (ALE/AS, PD0)

CLKIN (PD1) as input to the macrocells flip-

flops and APD counter

PSD Chip Select Input (CSI, PD2). Driving this

signal High disables the Flash memory, SRAM

and CSIOP.

■

MCU I/O Mode

■

CPLD Output – External Chip Select (ECS0-

ECS2)

■

CPLD Input – direct input to the CPLD, no

Input Macrocells (IMC)

Figure 30. Port D Structure

DATA OUT

REG.

DATA OUT

D

Q

WR

PORT D PIN

OUTPUT

MUX

[

]

ECS 2:0

READ MUX

OUTPUT

SELECT

P

D

B

DATA IN

ENABLE PRODUCT

TERM (.OE)

DIR REG.

D

Q

WR

CPLD-INPUT

AI02889

60/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

External Chip Select

The CPLD also provides three External Chip Se-

lect (ECS0-ECS2) outputs on Port D pins that can

be used to select external devices. Each External

Chip Select (ECS0-ECS2) consists of one product

term that can be configured active High or Low.

The output enable of the pin is controlled by either

the output enable product term or the Direction

Register. (See Figure 31.)

Figure 31. Port D External Chip Select Signals

ENABLE (.OE)

DIRECTION

REGISTER

PD0 PIN

ECS0

PT0

PT1

PT2

POLARITY

BIT

ENABLE (.OE)

DIRECTION

REGISTER

PD1 PIN

ECS1

POLARITY

BIT

ENABLE (.OE)

DIRECTION

REGISTER

PD2 PIN

ECS2

POLARITY

BIT

AI02890

61/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

POWER MANAGEMENT

All PSD devices offer configurable power saving

options. These options may be used individually or

in combinations, as follows:

remain in standby mode even if the address/

data signals are changing state externally

(noise, other devices on the MCU bus, etc.).

Keep in mind that any unblocked PLD input

signals that are changing states keeps the PLD

out of Stand-by mode, but not the memories.

■

All memory blocks in a PSD (primary and

secondary Flash memory, and SRAM) are

built with power management technology. In

addition to using special silicon design

methodology, power management technology

puts the memories into standby mode when

address/data inputs are not changing (zero

DC current). As soon as a transition occurs on

an input, the affected memory “wakes up”,

changes and latches its outputs, then goes

back to standby. The designer does not have

to do anything special to achieve memory

standby mode when no inputs are changing—

it happens automatically.

■

PSD Chip Select Input (CSI, PD2) can be

used to disable the internal memories, placing

them in standby mode even if inputs are

changing. This feature does not block any

internal signals or disable the PLDs. This is a

good alternative to using the APD Unit. There

is a slight penalty in memory access time

when PSD Chip Select Input (CSI, PD2)

makes its initial transition from deselected to

selected.

The PMMRs can be written by the MCU at run-

time to manage power. All PSD supports

“blocking bits” in these registers that are set to

block designated signals from reaching both

PLDs. Current consumption of the PLDs is

directly related to the composite frequency of

the changes on their inputs (see Figure 35 and

Figure 36., page 72). Significant power

savings can be achieved by blocking signals

that are not used in DPLD or CPLD logic

equations.

PSD devices have a Turbo Bit in PMMR0. This

bit can be set to turn the Turbo mode off (the

default is with Turbo mode turned on). While

Turbo mode is off, the PLDs can achieve

standby current when no PLD inputs are

changing (zero DC current). Even when inputs

do change, significant power can be saved at

lower frequencies (AC current), compared to

when Turbo mode is on. When the Turbo mode

is on, there is a significant DC current

■

The PLD sections can also achieve Stand-by

mode when its inputs are not changing, as

described in the sections on the Power

Management Mode Registers (PMMR).

■

As with the Power Management mode, the

Automatic Power Down (APD) block allows

the PSD to reduce to stand-by current

automatically. The APD Unit can also block

MCU address/data signals from reaching the

memories and PLDs. This feature is available

on all the devices of the PSD family. The APD

Unit is described in more detail in the sections

entitled Automatic Power-down (APD) Unit

and Power-down Mode, page 63.

Built in logic monitors the Address Strobe of the

MCU for activity. If there is no activity for a

certain time period (MCU is asleep), the APD

Unit initiates Power-down mode (if enabled).

Once in Power-down mode, all address/data

signals are blocked from reaching PSD memory

and PLDs, and the memories are deselected

internally. This allows the memory and PLDs to

component and the AC component is higher.

62/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 32, puts the PSD

into Power-down mode by monitoring the activity

of Address Strobe (ALE/AS, PD0). If the APD Unit

is enabled, as soon as activity on Address Strobe

(ALE/AS, PD0) stops, a four bit counter starts

counting. If Address Strobe (ALE/AS, PD0) re-

mains inactive for fifteen clock periods of CLKIN

(PD1), Power-down (PDN) goes High, and the

PSD enters Power-down mode, as discussed

next.

Power-down Mode. By default, if you enable the

APD Unit, Power-down mode is automatically en-

abled. The device enters Power-down mode if Ad-

dress Strobe (ALE/AS, PD0) remains inactive for

fifteen periods of CLKIN (PD1).

registers. The blocked signals include MCU

control signals and the common CLKIN (PD1).

Note that blocking CLKIN (PD1) from the

PLDs does not block CLKIN (PD1) from the

APD Unit.

All PSD memories enter Standby mode and

are drawing standby current. However, the

PLD and I/O ports blocks do not go into

Standby Mode because you don’t want to

have to wait for the logic and I/O to “wake-up”

before their outputs can change. See Table 28

for Power-down mode effects on PSD ports.

–

Typical standby current is of the order of

microamperes. These standby current values

assume that there are no transitions on any

PLD input.

The following should be kept in mind when the

PSD is in Power-down mode:

–

If Address Strobe (ALE/AS, PD0) starts

pulsing again, the PSD returns to normal

Operating mode. The PSD also returns to

normal Operating mode if either PSD Chip

Select Input (CSI, PD2) is Low or the Reset

(RESET) input is High.

The MCU address/data bus is blocked from all

memory and PLDs.

Various signals can be blocked (prior to

Power-down mode) from entering the PLDs by

setting the appropriate bits in the PMMR

Table 28. Power-down Mode’s Effect on Ports

Port Function

MCU I/O

Pin Level

No Change

PLD Out

No Change

Undefined

Tri-State

–

Address Out

Data Port

Peripheral I/O

Tri-State

Figure 32. APD Unit

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

DISABLE BUS

INTERFACE

ALE

PD

CLR

APD

EEPROM SELECT

FLASH SELECT

COUNTER

RESET

EDGE

DETECT

PD

CSI

PLD

SRAM SELECT

POWER DOWN

CLKIN

(

)

PDN SELECT

DISABLE

FLASH/EEPROM/SRAM

AI02891

Table 29. PSD Timing and Stand-by Current during Power-down Mode

Typical Stand-by Current

PLD Propagation

Delay

Memory

Access Time

Access Recovery Time

to Normal Access

Mode

5V V

3V V

CC

1

2

t

Power-down

No Access

Normal t (Note )

LVDV

75µA (Note ) 25µA (Note )

PD

Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.

2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’

63/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

For Users of the HC11 (or compatible)

PLD Power Management

The HC11 turns off its E clock when it sleeps.

Therefore, if you are using an HC11 (or compati-

ble) in your design, and you wish to use the Pow-

er-down mode, you must not connect the E clock

to CLKIN (PD1). You should instead connect a

crystal oscillator to CLKIN (PD1). The crystal oscil-

lator frequency must be less than 15 times the fre-

quency of AS. The reason for this is that if the

frequency is greater than 15 times the frequency

of AS, the PSD keeps going into Power-down

mode.

The power and speed of the PLDs are controlled

by the Turbo Bit (Bit 3) in PMMR0. By setting the

bit to '1,' the Turbo mode is off and the PLDs con-

sume the specified stand-by current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time is increased by

10ns after the Turbo Bit is set to '1' (turned off)

when the inputs change at a composite frequency

of less than 15 MHz. When the Turbo Bit is reset

to '0' (turned on), the PLDs run at full power and

speed. The Turbo Bit affects the PLD’s DC power,

AC power, and propagation delay.

Other Power Saving Options

Blocking MCU control signals with the bits of

PMMR2 can further reduce PLD AC power con-

sumption.

SRAM Standby Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has Voltage Stand-by

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the SRAM Stand-by and PSD

Chip Select Input (CSI, PD2) features, they are en-

abled by setting bits in PMMR0 and PMMR2.

Figure 33. Enable Power-down Flow Chart

(V , PC2) that can be connected to an external

STBY

battery. When V

becomes lower than V

RESET

CC

STBY

then the PSD automatically connects to Voltage

Stand-by (V , PC2) as a power source to the

STBY

Enable APD

Set PMMR0 Bit 1 = 1

SRAM. The SRAM Standby Current (I

) is typ-

STBY

ically 0.5µA. The SRAM data retention voltage is

2V minimum. The Battery-on Indicator (VBATON)

can be routed to PC4. This signal indicates when

the V has dropped below V

.

OPTIONAL

CC

STBY

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

ALE/AS idle

for 15 CLKIN

clocks?

No

Yes

PSD in Power

Down Mode

AI02892

64/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 30. Power Management Mode Registers PMMR0 (Note 1)

Bit 0

Bit 1

Bit 2

Bit 3

X

0

Not used, and should be set to zero.

0 = off Automatic Power-down (APD) is disabled.

1 = on Automatic Power-down (APD) is enabled.

APD Enable

X

0

Not used, and should be set to zero.

0 = on PLD Turbo mode is on

PLD Turbo

1 = off PLD Turbo mode is off, saving power.

CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN

(PD1) Powers-up the PLD when Turbo Bit is ’0.’

0 = on

Bit 4

Bit 5

PLD Array clk

PLD MCell clk

1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.

0 = on CLKIN (PD1) input to the PLD macrocells is connected.

1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.

Bit 6

Bit 7

X

0

Not used, and should be set to zero.

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.

Table 31. Power Management Mode Registers PMMR2 (Note 1)

Bit 0

Bit 1

X

0

Not used, and should be set to zero.

0 = on Cntl0 input to the PLD AND Array is connected.

PLD Array

CNTL0

Bit 2

Bit 3

Bit 4

Bit 5

1 = off Cntl0 input to PLD AND Array is disconnected, saving power.

0 = on Cntl1 input to the PLD AND Array is connected.

PLD Array

CNTL1

1 = off Cntl1 input to PLD AND Array is disconnected, saving power.

0 = on Cntl2 input to the PLD AND Array is connected.

PLD Array

CNTL2

1 = off Cntl2 input to PLD AND Array is disconnected, saving power.

0 = on ALE input to the PLD AND Array is connected.

PLD Array

ALE

1 = off ALE input to PLD AND Array is disconnected, saving power.

0 = on DBE input to the PLD AND Array is connected.

PLD Array

DBE

Bit 6

Bit 7

1 = off DBE input to PLD AND Array is disconnected, saving power.

X

0

Not used, and should be set to zero.

Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.

65/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PSD Chip Select Input (CSI, PD2)

Input Clock

PD2 of Port D can be configured in PSDsoft Ex-

press as PSD Chip Select Input (CSI). When Low,

the signal selects and enables the internal Flash

memory, EEPROM, SRAM, and I/O blocks for

READ or WRITE operations involving the PSD. A

High on PSD Chip Select Input (CSI, PD2) dis-

ables the Flash memory, EEPROM, and SRAM,

and reduces the PSD power consumption. How-

ever, the PLD and I/O signals remain operational

when PSD Chip Select Input (CSI, PD2) is High.

The PSD provides the option to turn off CLKIN

(PD1) to the PLD to save AC power consumption.

CLKIN (PD1) is an input to the PLD AND Array and

the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting Bits 4 or 5

to a 1 in PMMR0.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

Input Control Signals

The PSD provides the option to turn off the input

control signals (CNTL0, CNTL1, CNTL2, Address

Strobe (ALE/AS, PD0) and DBE) to the PLD to

save AC power consumption. These control sig-

nals are inputs to the PLD AND Array. During

Power-down mode, or, if any of them are not being

used as part of the PLD logic equation, these con-

trol signals should be disabled to save AC power.

They are disconnected from the PLD AND Array

by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

the timing parameter t

in Table 61., page 94

SLQV

or Table 62., page 95.

Table 32. APD Counter Operation

APD Enable Bit ALE PD Polarity

ALE Level

APD Counter

Not Counting

0

1

X

1

0

X

Pulsing

Not Counting

1

0

Counting (Generates PDN after 15 Clocks)

66/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

RESET TIMING AND DEVICE STATUS AT RESET

Power-Up Reset

Upon Power-up, the PSD requires a Reset (RE-

The same t

period is needed before the device

OPR

SET) pulse of duration t

after V

is

is operational after warm reset. Figure 34 shows

the timing of the Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 33., page 68 shows the I/O pin, register and

PLD status during Power On Reset, warm reset

and Power-down mode. PLD outputs are always

valid during warm reset, and they are valid in Pow-

er On Reset once the internal PSD Configuration

bits are loaded. This loading of PSD is completed

NLNH-PO

CC

steady. During this period, the device loads inter-

nal configurations, clears some of the registers

and sets the Flash memory into Operating mode.

After the rising edge of Reset (RESET), the PSD

remains in the Reset mode for an additional peri-

od, t

, before the first memory access is al-

OPR

lowed.

The Flash memory is reset to the READ Mode

upon Power-up. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must all be Low, Write

Strobe (WR, CNTL0) High, during Power On Re-

set for maximum security of the data contents and

to remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

Flash memory WRITE cycle initiation is prevented

typically long before the V

ramps up to operat-

CC

ing level. Once the PLD is active, the state of the

outputs are determined by the PSDabel equa-

tions.

Reset of Flash Memory Erase and Program

Cycles (on the PSD834Fx)

A Reset (RESET) also resets the internal Flash

memory state machine. During a Flash memory

Program or Erase cycle, Reset (RESET) termi-

nates the cycle and returns the Flash memory to

automatically when V is below V

.

CC

LKO

Warm Reset

Once the device is up and running, the device can

be reset with a pulse of a much shorter duration,

the Read Mode within a period of t

.

NLNH-A

t

.

NLNH

Figure 34. Reset (RESET) Timing

V_CC(min)

V

CC

t

NLNH

t

OPR

t

NLNH-PO

NLNH-A

OPR

Power-On Reset

Warm Reset

RESET

AI02866b

67/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode

Port Configuration

MCU I/O

Power-On Reset

Input mode

Warm Reset

Input mode

Power-down Mode

Unchanged

Valid after internal PSD

configuration bits are

loaded

Depends on inputs to PLD

(addresses are blocked in

PD mode)

PLD Output

Valid

Address Out

Data Port

Tri-stated

Not defined

Tri-stated

Peripheral I/O

Register

Power-On Reset

Warm Reset

Power-down Mode

PMMR0 and PMMR2

Cleared to '0'

Unchanged

Cleared to '0' by internal

Power-On Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

Macrocells flip-flop status

Initialized, based on the

selection in PSDsoft

Configuration menu

Initialized, based on the

selection in PSDsoft

Configuration menu

1

Unchanged

VM Register

All other registers

Cleared to '0'

Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.

68/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE

The JTAG Serial Interface block can be enabled

on Port C (see Table 34., page 70). All memory

blocks (primary and secondary Flash memory),

PLD logic, and PSD Configuration Register bits

may be programmed through the JTAG Serial In-

terface block. A blank device can be mounted on

a printed circuit board and programmed using

JTAG.

The standard JTAG signals (IEEE 1149.1) are

TMS, TCK, TDI, and TDO. Two additional signals,

TSTAT and TERR, are optional JTAG extensions

used to speed up Program and Erase cycles.

By default, on a blank PSD (as shipped from the

factory or after erasure), four pins on Port C are

enabled for the basic JTAG signals TMS, TCK,

TDI, and TDO.

See Application Note AN1153 for more details on

JTAG In-System Programming (ISP).

This dedicates the pins for JTAG at all

times (compliant with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a bit at

run-time by writing to the PSD

register, JTAG Enable. Thisregister is

located at address CSIOP + offset C7h.

Setting the JTAG_ENABLE bit in this

register will enable the pins for JTAG

use. This bit is cleared by a PSD reset

or the microcontroller. See Table

35., page 71 for bit definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT) inside

the PSD can be used to enable the JTAG

pins. This PT has the reserved name

JTAGSEL. Once defined as a node in

PSDabel, the designer can write an

equation for JTAGSEL. This method is

used when the Port C JTAG pins are

multiplexed with other I/O signals. It

is recommended to logically tie the

node JTAGSEL to the JEN\ signal on the

Flashlink cable when multiplexing JTAG

signals. See Application Note 1153 for

details. */

Standard JTAG Signals

The standard JTAG signals (TMS, TCK, TDI, and

TDO) can be enabled by any of three different con-

ditions that are logically ORed. When enabled,

TDI, TDO, TCK, and TMS are inputs, waiting for a

JTAG serial command from an external JTAG con-

troller device (such as FlashLINK or Automated

Test Equipment). When the enabling command is

received, TDO becomes an output and the JTAG

channel is fully functional inside the PSD. The

same command that enables the JTAG channel

may optionally enable the two additional JTAG sig-

nals, TSTAT and TERR.

The following symbolic logic equation specifies the

conditions enabling the four basic JTAG signals

(TMS, TCK, TDI, and TDO) on their respective

Port C pins. For purposes of discussion, the logic

label JTAG_ON is used. When JTAG_ON is true,

the four pins are enabled for JTAG. When

JTAG_ON is false, the four pins can be used for

general PSD I/O.

The state of the PSD Reset (RESET) signal does

not interrupt (or prevent) JTAG operations if the

JTAG pins are dedicated by an NVM configuration

bit (via PSDsoft Express). However, Reset (RE-

SET) will prevent or interrupt JTAG operations if

the JTAG enable register is used to enable the

JTAG pins.

The PSD supports JTAG In-System-Configuration

(ISC) commands, but not Boundary Scan. The PS-

Dsoft Express software tool and FlashLINK JTAG

programming cable implement the JTAG In-Sys-

tem-Configuration (ISC) commands. A definition

of these JTAG In-System-Configuration (ISC)

commands and sequences is defined in a supple-

mental document available from ST. This docu-

ment is needed only as a reference for designers

who use a FlashLINK to program their PSD.

JTAG_ON = PSDsoft_enabled +

/* An NVM configuration bit inside the

PSD is set by the designer in the

PSDsoft Express Configuration utility.

69/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

JTAG Extensions

Security and Flash memory Protection

TSTAT and TERR are two JTAG extension signals

enabled by an “ISC_ENABLE” command received

over the four standard JTAG signals (TMS, TCK,

TDI, and TDO). They are used to speed Program

and Erase cycles by indicating status on PSD sig-

nals instead of having to scan the status out seri-

ally using the standard JTAG channel. See

Application Note AN1153.

When the security bit is set, the device cannot be

read on a Device Programmer or through the

JTAG Port. When using the JTAG Port, only a Full

Chip Erase command is allowed.

All other Program, Erase and Verify commands

are blocked. Full Chip Erase returns the part to a

non-secured blank state. The Security Bit can be

set in PSDsoft Express Configuration.

TERR indicates if an error has occurred when

erasing a sector or programming a byte in Flash

memory. This signal goes Low (active) when an

Error condition occurs, and stays Low until an

“ISC_CLEAR” command is executed or a chip Re-

set (RESET) pulse is received after an

“ISC_DISABLE” command.

All primary and secondary Flash memory sectors

can individually be sector protected against era-

sures. The sector protect bits can be set in PSD-

soft Express Configuration.

Table 34. JTAG Port Signals

Port C Pin

PC0

JTAG Signals

TMS

Description

Mode Select

TSTAT behaves the same as Ready/Busy de-

scribed in the section entitled Ready/Busy

(PC3), page 20. TSTAT is High when the PSD de-

vice is in READ Mode (primary and secondary

Flash memory contents can be read). TSTAT is

Low when Flash memory Program or Erase cycles

are in progress, and also when data is being writ-

ten to the secondary Flash memory.

TSTAT and TERR can be configured as open-

drain type signals during an “ISC_ENABLE” com-

mand. This facilitates a wired-OR connection of

TSTAT signals from multiple PSD devices and a

wired-OR connection of TERR signals from those

same devices. This is useful when several PSD

devices are “chained” together in a JTAG environ-

ment.

PC1

PC3

PC4

PC5

PC6

TCK

Clock

TSTAT

TERR

TDI

Status

Error Flag

Serial Data In

Serial Data Out

TDO

70/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to ’1.’ The PSD

Configuration Register bits are set to ’0.’ The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

Table 35. JTAG Enable Register

0 = off JTAG port is disabled.

Bit 0

JTAG_Enable

1 = on JTAG port is enabled.

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

X

0

Not used, and should be set to zero.

Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-

uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is

used to enable the JTAG signals.

71/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

AC/DC PARAMETERS

These tables describe the AD and DC parameters

of the PSD:

■ DC Electrical Specification

■ AC Timing Specification

–

Power-down and Reset Timing

The following are issues concerning the parame-

ters presented:

–

In the DC specification the supply current is

given for different modes of operation. Before

calculating the total power consumption,

determine the percentage of time that the PSD

is in each mode. Also, the supply power is

considerably different if the Turbo Bit is ’0.’

The AC power component gives the PLD,

Flash memory, and SRAM mA/MHz

specification. Figures 35 and 36 show the PLD

mA/MHz as a function of the number of

Product Terms (PT) used.

■

PLD Timing

–

Combinatorial Timing

Synchronous Clock Mode

Asynchronous Clock Mode

Input Macrocell Timing

–

■

MCU Timing

–

READ Timing

WRITE Timing

Peripheral Mode Timing

In the PLD timing parameters, add the

required delay when Turbo Bit is ’0.’

Figure 35. PLD I /Frequency Consumption (5V range)

CC

110

100

90

V

= 5V

CC

80

70

60

50

40

30

20

10

0

PT 100%

PT 25%

0

5

10

15

20

25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

AI02894

Figure 36. PLD I /Frequency Consumption (3V range)

CC

60

V

= 3V

CC

50

40

30

20

10

0

PT 100%

PT 25%

0

5

10

15

20

25

HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)

AI03100

72/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 36. Example of PSD Typical Power Calculation at V = 5.0V (Turbo Mode On)

CC

Conditions

Highest Composite PLD input frequency

(Freq PLD)

MCU ALE frequency (Freq ALE)

% Flash memory Access

% SRAM access

= 8 MHz

= 4 MHz

= 80%

= 15%

% I/O access

= 5% (no additional power above base)

Operational Modes

% Normal

= 10%

= 90%

% Power-down Mode

Number of product terms used

(from fitter report)

= 45 PT

% of total product terms

Turbo Mode

= 45/182 = 24.7%

= ON

Calculation (using typical values)

I

total

= Ipwrdown x %pwrdown + %normal x (I (ac) + I

(dc))

CC

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE

+ % PLD x 2mA/MHz x Freq PLD

+ #PT x 400µA/PT)

= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz

+ 2mA/MHz x 8 MHz

+ 45 x 0.4mA/PT)

= 45µA + 0.1 x (8 + 0.9 + 16 + 18mA)

= 45µA + 0.1 x 42.9

= 45µA + 4.29mA

= 4.34mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based

on I = 0mA.

OUT

73/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 37. Example of PSD Typical Power Calculation at V = 5.0V (Turbo Mode Off)

CC

Conditions

Highest Composite PLD input frequency

(Freq PLD)

MCU ALE frequency (Freq ALE)

% Flash memory Access

% SRAM access

= 8 MHz

= 4 MHz

= 80%

= 15%

% I/O access

= 5% (no additional power above base)

Operational Modes

% Normal

= 10%

= 90%

% Power-down Mode

Number of product terms used

(from fitter report)

= 45 PT

% of total product terms

Turbo Mode

= 45/182 = 24.7%

= Off

Calculation (using typical values)

I

total

= Ipwrdown x %pwrdown + %normal x (I (ac) + I

(dc))

CC

= Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE

+ %SRAM x 1.5mA/MHz x Freq ALE

+ % PLD x (from graph using Freq PLD))

= 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz

+ 0.15 x 1.5mA/MHz x 4 MHz

+ 24mA)

= 45µA + 0.1 x (8 + 0.9 + 24)

= 45µA + 0.1 x 32.9

= 45µA + 3.29mA

= 3.34mA

This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based

on I = 0mA.

OUT

74/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings” table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 38. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

125

235

7.0

Unit

°C

V

T

Storage Temperature

Lead Temperature during Soldering (20 seconds max.)

–65

STG

1

T

LEAD

V

IO

Input and Output Voltage (Q = V

Supply Voltage

or Hi-Z)

OH

–0.6

V

CC

7.0

V

Device Programmer Supply Voltage

Electrostatic Discharge Voltage (Human Body model)

–0.6

14.0

2000

V

PP

2

V

ESD

–2000

V

Note: 1. IPC/JEDEC J-STD-020A

2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

75/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Designers should check that the operating

conditions in their circuit match the measurement

conditions when relying on the quoted parame-

ters.

Table 39. Operating Conditions (5V devices)

Symbol

Parameter

Min.

4.5

–40

0

Max.

5.5

85

Unit

V

CC

Supply Voltage

Ambient Operating Temperature (industrial)

Ambient Operating Temperature (commercial)

°C

T_A

70

Table 40. Operating Conditions (3V devices)

Symbol

Parameter

Min.

3.0

–40

0

Max.

3.6

85

Unit

V

CC

Supply Voltage

Ambient Operating Temperature (industrial)

Ambient Operating Temperature (commercial)

°C

T_A

70

Table 41. AC Signal Letters for PLD Timing

Table 42. AC Signal Behavior Symbols for PLD

Timing

A

C

D

E

G

I

Address Input

t

Time

CEout Output

L

Logic Level Low or ALE

Logic Level High

Valid

Input Data

H

V

X

Z

E Input

Internal WDOG_ON signal

Interrupt Input

No Longer a Valid Logic Level

Float

L

ALE Input

PW

Pulse Width

N

P

Q

R

S

T

RESET Input or Output

Port Signal Output

Output Data

Note: Example: t

= Time from Address Valid to ALE Invalid.

AVLX

WR, UDS, LDS, DS, IORD, PSEN Inputs

Chip Select Input

R/W Input

W

B

Internal PDN Signal

V

STBY

Output

M

Output Macrocell

Note: Example: t

= Time from Address Valid to ALE Invalid.

AVLX

Table 43. AC Measurement Conditions

Symbol

Parameter

Min.

Max.

Unit

C

Load Capacitance

30

pF

L

Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.

76/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 44. Capacitance

Symbol

2

Parameter

Test Condition

Max.

Unit

pF

Typ.

C

V

= 0V

Input Capacitance (for input pins)

4

6

IN

Output Capacitance (for input/

output pins)

pF

C

V

OUT

8

12

25

OUT

C

Capacitance (for CNTL2/V

)

PP

V = 0V

PP

pF

18

VPP

Note: 1. Sampled only, not 100% tested.

2. Typical values are for T = 25°C and nominal supply voltages.

A

Figure 37. AC Measurement I/O Waveform

Figure 38. AC Measurement Load Circuit

2.01 V

3.0V

195 Ω

Test Point

1.5V

Device

Under Test

0V

C_L= 30 pF

(Including Scope and

AI03103b

Jig Capacitance)

AI03104b

Figure 39. Switching Waveforms – Key

INPUTS

OUTPUTS

WAVEFORMS

STEADY INPUT

STEADY OUTPUT

MAY CHANGE FROM

HI TO LO

WILL BE CHANGING

FROM HI TO LO

MAY CHANGE FROM

LO TO HI

WILL BE CHANGING

LO TO HI

DON'T CARE

CHANGING, STATE

UNKNOWN

OUTPUTS ONLY

CENTER LINE IS

TRI-STATE

AI03102

77/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 45. DC Characteristics (5V devices)

Test Condition

Symbol

Parameter

(in addition to those in

Table 39., page 76)

Min.

Typ.

Max.

+0.5

Unit

V

4.5 V < V < 5.5 V

V

Input High Voltage

2

V

IH

CC

V

4.5 V < V < 5.5 V

Input Low Voltage

–0.5

0.8

+0.5

IL

CC

1

0.8V

Reset High Level Input Voltage

IH1

CC

(Note )

1

0.2V –0.1

Reset Low Level Input Voltage

Reset Pin Hysteresis

–0.5

0.3

V

IL1

CC

(Note )

HYS

V

(min) for Flash Erase and

CC

V

2.5

4.2

V

LKO

OL

Program

I

= 20µA, V = 4.5 V

0.01

0.25

4.49

3.9

0.1

V

OL

CC

Output Low Voltage

I

= 8mA, V = 4.5 V

0.45

OL

CC

I

= –20µA, V = 4.5 V

4.4

2.4

V

OH

CC

Output High Voltage Except

V

OH

V

STBY

On

I

= –2mA, V = 4.5 V

V

OH

CC

V

I

Output High Voltage V

On

I

= 1µA

V

– 0.8

STBY

V

OH1

STBY

OH1

V

SRAM Stand-by Voltage

SRAM Stand-by Current

2.0

V

STBY

CC

V

= 0 V

0.5

1

µA

V

STBY

IDLE

CC

I

Idle Current (V

input)

V

> V

CC STBY

–0.1

2

0.1

STBY

V

I

Only on V

STBY

SRAM Data Retention Voltage

DF

Stand-by Supply Current

for Power-down Mode

2,3

50

200

µA

SB

CSI >V –0.3 V (Notes

)

CC

I

V

< V < V

SS IN CC

Input Leakage Current

Output Leakage Current

–1

±0.1

±5

1

µA

LI

0.45 < V

< V

CC

–10

10

LO

OUT

PLD_TURBO = Off,

0

µA/PT

mA

5

f = 0 MHz (Note )

PLD Only

PLD_TURBO = On,

f = 0 MHz

400

15

700

30

Operating

Supply

Current

I

(DC)

5

CC

During Flash memory

WRITE/Erase Only

(Note )

Flash memory

Read only, f = 0 MHz

f = 0 MHz

0

mA

SRAM

4

PLD AC Adder

note

mA/

MHz

I

(AC)

5

CC

Flash memory AC Adder

SRAM AC Adder

2.5

1.5

3.5

3.0

(Note )

mA/

MHz

Note: 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V

is valid at or above 0.8V

.

CC

IL1

CC

IH1

2. CSI deselected or internal Power-down mode is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 35., page 72 for the PLD current calculation.

5. I

= 0mA

OUT

78/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 46. DC Characteristics (3V devices)

Symbol

Parameter

Conditions

Min.

0.7V

Typ.

Max.

+0.5

CC

Unit

V

3.0 V < V < 3.6 V

V

High Level Input Voltage

Low Level Input Voltage

Reset High Level Input Voltage

IH

CC

V

3.0 V < V < 3.6 V

–0.5

0.8V

0.8

+0.5

V

IL

CC

1

V

IH1

CC

(Note )

1

0.2V –0.1

Reset Low Level Input Voltage

Reset Pin Hysteresis

–0.5

0.3

V

IL1

CC

(Note )

HYS

V

(min) for Flash Erase and

CC

V

1.5

2.2

V

LKO

OL

Program

I

= 20µA, V = 3.0 V

0.01

0.15

2.99

2.8

0.1

V

OL

CC

Output Low Voltage

I

= 4mA, V = 3.0 V

0.45

OL

CC

I

= –20µA, V = 3.0 V

2.9

2.7

V

OH

CC

Output High Voltage Except

V

OH

V

STBY

On

I

= –1mA, V = 3.0 V

V

OH

CC

V

I

Output High Voltage V

On

I

= 1µA

V

– 0.8

STBY

V

OH1

STBY

OH1

V

SRAM Stand-by Voltage

SRAM Stand-by Current

2.0

V

STBY

CC

V

= 0 V

0.5

1

µA

V

STBY

IDLE

CC

I

Idle Current (V

input)

V

> V

CC STBY

–0.1

2

0.1

STBY

V

I

Only on V

STBY

SRAM Data Retention Voltage

DF

Stand-by Supply Current

for Power-down Mode

2,3

25

100

µA

CSI >V –0.3 V (Notes

)

SB

CC

I

V

< V < V

SS IN CC

Input Leakage Current

Output Leakage Current

–1

±0.1

±5

1

µA

LI

0.45 < V < V

CC

–10

10

LO

IN

PLD_TURBO = Off,

0

µA/PT

mA

3

f = 0 MHz (Note )

PLD Only

PLD_TURBO = On,

f = 0 MHz

200

10

400

25

Operating

Supply

Current

I

(DC)

5

CC

During Flash memory

WRITE/Erase Only

(Note )

Flash memory

Read only, f = 0 MHz

f = 0 MHz

0

mA

SRAM

4

PLD AC Adder

note

1.5

mA/

MHz

I

(AC)

5

CC

Flash memory AC Adder

SRAM AC Adder

2.0

1.5

(Note )

mA/

MHz

0.8

Note: 1. Reset (RESET) has hysteresis. V is valid at or below 0.2V –0.1. V

is valid at or above 0.8V

.

CC

IL1

CC

IH1

2. CSI deselected or internal PD is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 36., page 72 for the PLD current calculation.

5. I

= 0mA

OUT

79/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 40. Input to Output Disable / Enable

INPUT

tER

tEA

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

Table 47. CPLD Combinatorial Timing (5V devices)

-70

-90

-15

Fast

PT

Aloc

Slew

Turbo

Off

Symbol

Parameter

Conditions

Unit

1

rate

Min Max Min Max Min Max

CPLD Input Pin/

Feedback to CPLD

Combinatorial Output

t

20

25

32

+ 2

+ 10

– 2

ns

PD

CPLD Input to CPLD

Output Enable

t

21

26

32

33

+ 10

– 2

ns

EA

CPLD Input to CPLD

Output Disable

ER

CPLD Register Clear

or Preset Delay

ARP

ARPW

ARD

CPLD Register Clear

or Preset Pulse Width

10

20

29

Any

macrocell

CPLD Array Delay

11

16

22

+ 2

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 48. CPLD Combinatorial Timing (3V devices)

-12

-15

-20

Slew

PT Turbo

Symbol

Parameter

Conditions

Unit

1

Aloc

Off

rate

Min Max Min Max Min Max

CPLD Input Pin/

t

Feedback to CPLD

Combinatorial Output

40

45

50

+ 4

+ 20

– 6

ns

PD

CPLD Input to CPLD

Output Enable

t

43

45

50

+ 20

– 6

ns

EA

ER

CPLD Input to CPLD

Output Disable

CPLD Register Clear

or

Preset Delay

t

40

43

48

+ 20

– 6

ns

ARP

CPLD Register Clear

or

Preset Pulse Width

t

25

30

35

ns

ARPW

ARD

Any

macrocell

CPLD Array Delay

25

29

33

+ 4

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

80/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 41. Synchronous Clock Mode Timing – PLD

t

CL

CH

CLKIN

INPUT

t

S

t

H

t

CO

REGISTERED

OUTPUT

AI02860

Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)

-70

-90

-15

Fast

PT

Aloc

Slew

Turbo

Off

Symbol

Parameter

Conditions

Unit

1

rate

Min Max Min Max Min Max

Maximum

Frequency

External

1/(t +t

)

40.0

30.30

25.00

MHz

S

CO

Feedback

Maximum

Frequency

Internal

f

MAX

1/(t +t –10)

66.6

83.3

43.48

50.00

31.25

35.71

MHz

S

CO

Feedback

(f

CNT

)

Maximum

Frequency

Pipelined Data

1/(t +t

)

MHz

ns

CH CL

Input Setup

Time

t

12

15

20

+ 2

+ 10

S

t

Input Hold Time

Clock High Time

Clock Low Time

0

6

0

ns

H

Clock Input

10

15

CH

CL

Clock to Output

Delay

t

Clock Input

13

11

18

16

22

– 2

ns

CO

CPLD Array

Delay

Any macrocell

+ 2

ARD

Minimum Clock

t +t

CH CL

12

20

30

MIN

2

Period

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

2. CLKIN (PD1) t = t + t

.

CL

CLCL

CH

81/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)

-12

-15

-20

Slew

PT

Aloc

Turbo

Off

Symbol

Parameter

Conditions

Unit

1

rate

Min Max Min Max Min Max

Maximum

Frequency

1/(t +t

)

22.2

28.5

40.0

18.8

23.2

33.3

15.8

18.8

31.2

MHz

S

CO

External Feedback

Maximum

Frequency

Internal Feedback

f

1/(t +t –10)

S CO

MHz

MAX

(f

CNT

)

Maximum

Frequency

Pipelined Data

1/(t +t

)

CH CL

t

Input Setup Time

Input Hold Time

Clock High Time

Clock Low Time

20

0

25

0

30

0

+ 4

+ 20

ns

S

H

Clock Input

15

10

15

16

CH

CL

Clock to Output

Delay

t

Clock Input

25

28

29

33

– 6

ns

CO

CPLD Array Delay

Any macrocell

+ 4

ARD

MIN

Minimum Clock

t +t

CH CL

25

29

32

2

Period

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

2. CLKIN (PD1) t = t + t

.

CL

CLCL

CH

82/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 42. Asynchronous Reset / Preset

tARPW

RESET/PRESET

INPUT

tARP

REGISTER

OUTPUT

AI02864

Figure 43. Asynchronous Clock Mode Timing (product term clock)

tCHA

tCLA

CLOCK

INPUT

tSA

tHA

tCOA

REGISTERED

OUTPUT

AI02859

83/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)

-70

-90

-15

PT Turbo Slew

Symbol

Parameter

Conditions

Unit

Aloc

Off

Rate

Min Max Min Max Min Max

Maximum

Frequency

External

1/(t +t

)

38.4

62.5

71.4

26.32

35.71

41.67

21.27

27.78

35.71

MHz

SA COA

Feedback

Maximum

Frequency

Internal

f

1/(t +t

–10)

MHz

MAXA

SA COA

Feedback

(f

CNTA

)

Maximum

Frequency

Pipelined

Data

1/(t

+t

)

CHA CLA

Input Setup

Time

t

7

8

9

8

12

14

15

+ 2

+ 10

ns

SA

Input Hold

Time

12

HA

Clock Input

High Time

+ 10

CHA

CLA

COA

ARDA

MINA

Clock Input

Low Time

Clock to

Output Delay

21

11

30

16

37

22

– 2

CPLD Array

Delay

Any macrocell

+ 2

Minimum

Clock Period

1/f

CNTA

16

28

39

84/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)

-12

-15

-20

PT Turbo Slew

Symbol

Parameter

Conditions

Unit

Aloc

Off

Rate

Min Max Min Max Min Max

Maximum

Frequency

External

1/(t +t

)

21.7

19.2

16.9

MHz

SA COA

Feedback

Maximum

Frequency

Internal

f

MAXA

1/(t +t

–10)

27.8

33.3

23.8

27

20.4

24.4

MHz

SA COA

Feedback

(f

CNTA

)

Maximum

Frequency

Pipelined Data

1/(t

+t

)

MHz

ns

CHA CLA

Input Setup

Time

t

10

12

13

+ 4

+ 20

SA

t

Input Hold Time

Clock High Time

Clock Low Time

12

17

13

15

22

15

17

25

16

ns

HA

+ 20

CHA

CLA

Clock to Output

Delay

t

36

25

40

29

46

33

+ 20

– 6

ns

COA

ARD

MINA

CPLD Array

Delay

Any macrocell

+ 4

Minimum Clock

Period

1/f

36

42

49

CNTA

85/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 44. Input Macrocell Timing (product term clock)

t

INL

INH

PT CLOCK

INPUT

t

IH

IS

OUTPUT

t

INO

AI03101

Table 53. Input Macrocell Timing (5V devices)

-70

-90

-15

PT

Aloc

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

1

t

Input Setup Time

Input Hold Time

0

15

9

0

ns

IS

(Note )

1

t

20

12

26

18

+ 10

IH

(Note )

1

NIB Input High Time

NIB Input Low Time

INH

INL

(Note )

1

9

(Note )

NIB Input to Combinatorial

Delay

1

t

34

46

59

+ 2

+ 10

ns

INO

(Note )

Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t

and t

.

LXAX

AVLX

Table 54. Input Macrocell Timing (3V devices)

-12

-15

-20

PT

Aloc

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

1

t

Input Setup Time

Input Hold Time

0

ns

IS

(Note )

1

t

25

12

25

13

30

15

+ 20

IH

(Note )

1

NIB Input High Time

NIB Input Low Time

INH

INL

(Note )

1

(Note )

NIB Input to Combinatorial

Delay

1

t

46

62

70

+ 4

+ 20

ns

INO

(Note )

Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t

and t

.

LXAX

AVLX

86/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 45. READ Timing

1

t

LXAX

AVLX

ALE/AS

t

LVLX

A/D

MULTIPLEXED

BUS

ADDRESS

VALID

DATA

VALID

t

AVQV

ADDRESS

NON-MULTIPLEXED

BUS

ADDRESS

VALID

DATA

NON-MULTIPLEXED

BUS

DATA

VALID

t

SLQV

CSI

t

RLQV

t

RHQX

RLRH

RD

(PSEN, DS)

tRHQZ

t

EHEL

E

t

THEH

t

ELTL

R/W

t

AVPV

ADDRESS OUT

AI02895

Note: 1. t

and t

are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.

LXAX

AVLX

87/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 55. READ Timing (5V devices)

-70

-90

-15

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

t

ALE or AS Pulse Width

Address Setup Time

15

4

20

6

28

10

11

ns

LVLX

AVLX

LXAX

AVQV

SLQV

3

t

(Note )

3

Address Hold Time

7

8

(Note )

3

Address Valid to Data Valid

CS Valid to Data Valid

RD to Data Valid 8-Bit Bus

70

75

24

90

100

32

150 + 10

(Note )

150

40

5

(Note )

t

RLQV

RD or PSEN to Data Valid

8-Bit Bus, 8031, 80251

2

31

38

45

30

ns

(Note )

1

t

RD Data Hold Time

RD Pulse Width

0

ns

RHQX

RLRH

(Note )

1

27

32

38

(Note )

1

t

RD to Data High-Z

20

25

ns

RHQZ

EHEL

THEH

ELTL

(Note )

E Pulse Width

27

6

32

10

0

38

18

0

R/W Setup Time to Enable

R/W Hold Time After Enable

0

Address Input Valid to

Address Output Delay

4

t

20

25

30

ns

AVPV

(Note )

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD and PSEN have the same timing.

3. Any input used to select an internal PSD function.

4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS, LDS, and UDS signals.

88/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 56. READ Timing (3V devices)

-12

-15

-20

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

t

ALE or AS Pulse Width

Address Setup Time

26

9

26

10

12

30

12

14

ns

LVLX

AVLX

LXAX

AVQV

SLQV

3

t

(Note )

3

Address Hold Time

9

(Note )

3

Address Valid to Data Valid

CS Valid to Data Valid

RD to Data Valid 8-Bit Bus

120

35

150

35

200 + 20

(Note )

200

40

5

(Note )

t

RLQV

RD or PSEN to Data Valid 8-Bit Bus,

8031, 80251

2

45

50

55

ns

(Note )

1

t

RD Data Hold Time

RD Pulse Width

0

ns

RHQX

RLRH

RHQZ

EHEL

THEH

ELTL

(Note )

38

40

45

1

RD to Data High-Z

38

40

45

(Note )

E Pulse Width

40

15

0

45

18

0

52

20

0

R/W Setup Time to Enable

R/W Hold Time After Enable

Address Input Valid to

Address Output Delay

4

t

33

35

40

ns

AVPV

(Note )

Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

2. RD and PSEN have the same timing for 8031.

3. Any input used to select an internal PSD function.

4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

5. RD timing has the same timing as DS, LDS, and UDS signals.

89/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 46. WRITE Timing

t

LXAX

AVLX

ALE/AS

t

LVLX

A/D

MULTIPLEXED

BUS

ADDRESS

VALID

DATA

VALID

t

AVWL

ADDRESS

NON-MULTIPLEXED

BUS

ADDRESS

VALID

DATA

NON-MULTIPLEXED

BUS

DATA

VALID

t

SLWL

CSI

t

DVWH

WHDX

t

WR

WLWH

t

WHAX

(DS)

t

EHEL

E

t

THEH

ELTL

R/ W

t

WLMV

t

AVPV

WHPV

STANDARD

MCU I/O OUT

ADDRESS OUT

AI02896

90/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 57. WRITE Timing (5V devices)

-70

-90

-15

Symbol

Parameter

ALE or AS Pulse Width

Conditions

Unit

Min Max Min Max Min Max

t

15

4

20

6

28

10

11

ns

LVLX

AVLX

LXAX

1

t

Address Setup Time

Address Hold Time

(Note )

1

7

8

(Note )

Address Valid to Leading

Edge of WR

1,3

t

8

15

20

ns

AVWL

(Notes

)

3

t

CS Valid to Leading Edge of WR

WR Data Setup Time

12

25

4

15

35

5

20

45

5

ns

SLWL

(Note )

3

DVWH

WHDX

WLWH

WHAX1

(Note )

3

WR Data Hold Time

(Note )

3

WR Pulse Width

31

6

35

8

45

10

(Note )

3

Trailing Edge of WR to Address Invalid

(Note )

Trailing Edge of WR to DPLD Address

Invalid

3,6

t

0

ns

WHAX2

WHPV

(Note

)

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

3

27

42

30

55

38

65

(Note )

Data Valid to Port Output Valid

Using Macrocell Register

Preset/Clear

3,5

t

ns

DVMV

(Notes

)

Address Input Valid to Address

Output Delay

2

t

20

48

25

55

30

65

ns

AVPV

(Note )

WR Valid to Port Output Valid Using

Macrocell Register Preset/Clear

3,4

WLMV

(Notes

)

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

91/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 58. WRITE Timing (3V devices)

-12

-15

-20

Symbol

Parameter

ALE or AS Pulse Width

Conditions

Unit

Min Max Min Max Min Max

t

26

9

26

10

12

30

12

14

LVLX

AVLX

LXAX

1

t

Address Setup Time

Address Hold Time

ns

(Note )

1

9

(Note )

Address Valid to Leading

Edge of WR

1,3

t

17

20

25

ns

AVWL

(Notes

)

3

t

CS Valid to Leading Edge of WR

WR Data Setup Time

17

45

7

20

45

8

25

50

10

53

17

ns

SLWL

(Note )

3

DVWH

WHDX

WLWH

WHAX1

(Note )

3

WR Data Hold Time

(Note )

3

WR Pulse Width

46

10

48

12

(Note )

3

Trailing Edge of WR to Address Invalid

(Note )

Trailing Edge of WR to DPLD Address

Invalid

3,6

t

0

ns

WHAX2

WHPV

DVMV

AVPV

(Note

)

Trailing Edge of WR to Port Output

Valid Using I/O Port Data Register

3

33

70

33

70

35

70

35

70

40

80

40

80

(Note )

Data Valid to Port Output Valid

Using Macrocell Register Preset/Clear

3,5

(Notes

)

Address Input Valid to Address

Output Delay

2

(Note )

WR Valid to Port Output Valid Using

Macrocell Register Preset/Clear

3,4

WLMV

(Notes

)

Note: 1. Any input used to select an internal PSD function.

2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.

4. Assuming data is stable before active WRITE signal.

5. Assuming WRITE is active before data becomes valid.

6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Table 59. Program, WRITE and Erase Times (5V devices)

Symbol

Parameter

Min.

Typ.

8.5

3

Max.

30

Unit

Flash Program

s

1

s

Flash Bulk Erase (pre-programmed)

Flash Bulk Erase (not pre-programmed)

Sector Erase (pre-programmed)

Sector Erase (not pre-programmed)

Byte Program

5

s

t

1

30

WHQV3

WHQV2

WHQV1

2.2

14

s

1200

µs

Program / Erase Cycles (per Sector)

Sector Erase Time-Out

100,000

cycles

µs

t

100

WHWLO

Q7VQV

2

30

ns

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

Note: 1. Programmed to all zero before erase.

2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

92/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 60. Program, WRITE and Erase Times (3V devices)

Symbol

Parameter

Min.

Typ.

8.5

3

Max.

30

Unit

Flash Program

s

1

s

Flash Bulk Erase (pre-programmed)

Flash Bulk Erase (not pre-programmed)

Sector Erase (pre-programmed)

Sector Erase (not pre-programmed)

Byte Program

5

s

t

1

30

WHQV3

WHQV2

WHQV1

2.2

14

s

1200

µs

Program / Erase Cycles (per Sector)

Sector Erase Time-Out

100,000

cycles

µs

t

100

WHWLO

Q7VQV

2

30

ns

DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)

Note: 1. Programmed to all zero before erase.

2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

93/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 47. Peripheral I/O READ Timing

ALE/AS

ADDRESS

DATA VALID

A/D BUS

t

(PA)

AVQV

t

SLQV

CSI

RD

t

(PA)

RLQV

t

(PA)

QXRH

RHQZ

RLRH

t

(PA)

DVQV

DATA ON PORT A

AI02897

Table 61. Port A Peripheral Data Mode READ Timing (5V devices)

-70

-90

-15

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

Address Valid to Data

Valid

3

t

37

39

45

+ 10

ns

AVQV–PA

SLQV–PA

(Note )

CSI Valid to Data Valid

RD to Data Valid

27

21

32

22

35

32

38

30

45

40

45

38

ns

1,4

(Notes

)

t

RLQV–PA

RD to Data Valid 8031 Mode

Data In to Data Out Valid

RD Data Hold Time

RD Pulse Width

t

DVQV–PA

QXRH–PA

RLRH–PA

0

1

27

32

38

(Note )

1

t

RD to Data High-Z

23

25

30

ns

RHQZ–PA

(Note )

94/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 62. Port A Peripheral Data Mode READ Timing (3V devices)

-12

-15

-20

Turbo

Off

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

3

t

Address Valid to Data Valid

50

+ 20

ns

AVQV–PA

SLQV–PA

(Note )

CSI Valid to Data Valid

RD to Data Valid

37

45

38

45

40

45

40

50

45

50

45

ns

1,4

(Notes

)

t

RLQV–PA

RD to Data Valid 8031 Mode

Data In to Data Out Valid

RD Data Hold Time

RD Pulse Width

t

DVQV–PA

QXRH–PA

RLRH–PA

0

1

36

46

(Note )

1

t

RD to Data High-Z

36

40

45

ns

RHQZ–PA

(Note )

Figure 48. Peripheral I/O WRITE Timing

ALE/AS

ADDRESS

DATA OUT

A/D BUS

tWHQZ (PA)

tWLQV (PA)

WR

tDVQV (PA)

PORT A

DATA OUT

AI02898

Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)

-70

-90

-15

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

2

t

WR to Data Propagation Delay

Data to Port A Data Propagation Delay

WR Invalid to Port A Tri-state

25

22

20

35

30

25

40

38

33

ns

WLQV–PA

DVQV–PA

WHQZ–PA

(Note )

5

(Note )

2

(Note )

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

95/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)

-12

-15

-20

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

2

t

WR to Data Propagation Delay

Data to Port A Data Propagation Delay

WR Invalid to Port A Tri-state

42

38

33

45

40

33

55

45

35

ns

WLQV–PA

DVQV–PA

WHQZ–PA

(Note )

5

(Note )

2

(Note )

Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).

2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.

3. Any input used to select Port A Data Peripheral mode.

4. Data is already stable on Port A.

5. Data stable on ADIO pins to data on Port A.

Figure 49. Reset (RESET) Timing

V_CC(min)

V

CC

t

NLNH

t

OPR

t

NLNH-PO

Power-On Reset

NLNH-A

OPR

Warm Reset

RESET

AI02866b

Table 65. Reset (RESET) Timing (5V devices)

Symbol

Parameter

Conditions

Min

150

1

Max

Unit

1

t

ns

ms

µs

ns

NLNH

RESET Active Low Time

Power On Reset Active Low Time

NLNH–PO

NLNH–A

OPR

2

25

Warm Reset (on the PSD834Fx)

RESET High to Operational Device

120

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 66. Reset (RESET) Timing (3V devices)

Symbol

Parameter

Conditions

Min

300

1

Max

Unit

ns

1

t

NLNH

RESET Active Low Time

Power On Reset Active Low Time

ms

µs

NLNH–PO

NLNH–A

OPR

2

25

Warm Reset (on the PSD834Fx)

RESET High to Operational Device

300

ns

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

96/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 67. V

Symbol

Timing (5V devices)

STBYON

Parameter

Detection to V Output High

STBYON

Conditions

Min

Typ

Max

Unit

1

t

V

STBY

20

µs

BVBH

(Note )

V

Low

Off Detection to V

Output

STBYON

STBY

1

t

20

µs

BXBL

(Note )

Note: 1. V

timing is measured at V ramp rate of 2 ms.

CC

STBYON

Table 68. V

Symbol

Timing (3V devices)

Parameter

STBYON

Conditions

Min

Typ

Max

Unit

1

t

V

STBY

Detection to V

Output High

STBYON

20

µs

BVBH

(Note )

V

Low

Off Detection to V

Output

STBYON

STBY

1

t

20

µs

BXBL

(Note )

Note: 1. V

timing is measured at V ramp rate of 2 ms.

CC

STBYON

97/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 50. ISC Timing

t_ISCCH

TCK

t_ISCCL

t_ISCPSU

t_ISCPH

TDI/TMS

t _ISCPZV

t_ISCPCO

ISC OUTPUTS/TDO

t_ISCPVZ

ISC OUTPUTS/TDO

AI02865

Table 69. ISC Timing (5V devices)

-70

-90

-15

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

Clock (TCK, PC1) Frequency (except for

PLD)

1

t

20

18

14 MHz

ISCCF

ISCCH

ISCCL

(Note )

Clock (TCK, PC1) High Time (except for

PLD)

1

t

23

26

31

ns

(Note )

Clock (TCK, PC1) Low Time (except for

PLD)

1

(Note )

2

t

Clock (TCK, PC1) Frequency (PLD only)

Clock (TCK, PC1) High Time (PLD only)

2

MHz

ns

ISCCFP

ISCCHP

(Note )

2

240

(Note )

2

t

Clock (TCK, PC1) Low Time (PLD only)

ISC Port Set Up Time

240

7

240

8

240

10

5

ns

ISCCLP

ISCPSU

ISCPH

(Note )

ISC Port Hold Up Time

5

ISC Port Clock to Output

21

23

25

ISCPCO

ISCPZV

ISC Port High-Impedance to Valid Output

ISC Port Valid Output to

High-Impedance

t

21

23

25

ns

ISCPVZ

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

98/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 70. ISC Timing (3V devices)

-12

-15

-20

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

Clock (TCK, PC1) Frequency (except for

PLD)

1

t

12

10

9

2

MHz

ns

ISCCF

ISCCH

ISCCL

(Note )

Clock (TCK, PC1) High Time (except for

PLD)

1

t

40

45

51

(Note )

Clock (TCK, PC1) Low Time (except for

PLD)

1

ns

(Note )

2

t

Clock (TCK, PC1) Frequency (PLD only)

Clock (TCK, PC1) High Time (PLD only)

2

MHz

ns

ISCCFP

ISCCHP

(Note )

2

240

(Note )

2

t

Clock (TCK, PC1) Low Time (PLD only)

ISC Port Set Up Time

240

12

5

240

13

5

240

15

5

ns

ISCCLP

ISCPSU

ISCPH

(Note )

ISC Port Hold Up Time

ISC Port Clock to Output

30

36

40

ISCPCO

ISCPZV

ISC Port High-Impedance to Valid Output

ISC Port Valid Output to

High-Impedance

t

30

36

40

ns

ISCPVZ

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

Table 71. Power-down Timing (5V devices)

-70

-90

-15

Symbol

Parameter

Conditions

Unit

Min Max Min Max Min Max

t

ALE Access Time from Power-down

80

90

150

ns

LVDV

Maximum Delay from

APD Enable to Internal PDN Valid

Signal

Using CLKIN

(PD1)

1

t

µs

15 * t

CLWH

CLCL

Note: 1. t

is the period of CLKIN (PD1).

CLCL

Table 72. Power-down Timing (3V devices)

-12

Min Max Min Max Min Max

145 150 200

-15

-20

Symbol

Parameter

Conditions

Unit

t

ALE Access Time from Power-down

ns

µs

LVDV

Maximum Delay from APD Enable to

Internal PDN Valid Signal

Using CLKIN

(PD1)

1

t

15 * t

CLWH

CLCL

Note: 1. t

is the period of CLKIN (PD1).

CLCL

99/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PACKAGE MECHANICAL

Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing

D

D1

D2

A2

e

b

Ne

E2 E1 E

N

1

Nd

A

CP

L1

c

A1

α

L

QFP-A

Note: Drawing is not to scale.

100/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions

mm

inches

Symb.

Typ.

Min.

Max.

2.35

0.25

2.10

0.38

0.23

13.25

10.05

–

Typ.

Min.

Max.

0.093

0.010

0.083

0.015

0.009

0.522

0.396

–

A

A1

A2

b

2.00

1.80

0.22

0.11

13.15

9.95

–

0.079

0.077

0.009

0.004

0.518

0.392

–

c

D

13.20

10.00

7.80

0.520

0.394

0.307

0.520

0.394

0.307

0.026

0.035

0.063

D1

D2

E

13.20

10.00

7.80

13.15

9.95

–

13.25

10.05

–

0.518

0.392

–

0.522

0.396

–

E1

E2

e

0.65

–

L

0.88

0.73

–

1.03

–

0.029

0.041

7°

L1

α

1.60

0°

7°

0°

52

13

N

52

Nd

Ne

CP

13

0.10

0.004

101/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing

D

A1

D1

A2

M1

M

1 N

b1

e

E1 E

D2/E2 D3/E3

b

L1

L

C

A

CP

PLCC-B

Note: Drawing is not to scale.

Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions

mm

Min.

4.19

2.54

–

inches

Min.

0.165

0.100

–

Symbol

Typ.

Max.

4.57

2.79

0.91

0.53

0.81

0.261

20.19

19.15

18.54

20.19

19.15

18.54

–

Typ.

Max.

0.180

0.110

0.036

0.021

0.032

A

A1

A2

B

0.33

0.66

0.246

19.94

19.05

17.53

19.94

19.05

17.53

–

0.013

0.026

0.0097

0.785

0.750

0.690

0.785

0.750

0.690

–

B1

C

0.0103

0.795

0.754

0.730

0.795

0.754

0.730

–

D

D1

D2

E

E1

E2

e

1.27

0.89

0.050

0.035

R

–

N

52

Nd

Ne

13

102/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline

D

D1

D2

A2

e

b

Ne

E2 E1 E

N

1

Nd

A

CP

L1

c

A1

α

L

QFP-A

Note: Drawing is not to scale.

103/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data

mm

inches

Min.

Symb.

Typ.

Min.

1.42

0.07

1.36

0.0°

0.33

Max.

1.54

Typ.

Max.

0.061

0.005

0.057

7.0°

A

A1

A2

α

0.056

0.003

0.054

0.0°

0.10

1.40

3.5°

0.35

0.14

0.004

0.055

3.5°

1.44

7.0°

b

0.38

0.014

0.013

0.015

0.006

0.634

0.552

0.474

0.634

0.552

0.474

0.033

0.030

0.042

c

0.17

D

16.00

14.00

12.00

16.00

14.00

12.00

0.80

15.90

13.98

11.95

15.90

13.98

11.95

0.75

16.10

14.03

12.05

16.10

14.03

12.05

0.85

0.630

0.551

0.472

0.630

0.551

0.472

0.031

0.024

0.039

0.004

0.626

0.550

0.470

0.626

0.550

0.470

0.030

0.018

0.037

D1

D2

E

E1

E2

e

L

0.60

0.45

0.75

L1

CP

N

1.00

0.94

1.06

0.10

64

16

64

16

Nd

Ne

104/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

PART NUMBERING

Table 76. Ordering Information Scheme

Example:

PSD8

1

3

F

2

V

–

15

J

1

T

Device Type

PSD8 = 8-bit PSD with Register Logic

PSD9 = 8-bit PSD with Combinatorial Logic

SRAM Capacity

1 = 16 Kbit

3 = 64 Kbit

5 = 256 Kbit

Flash Memory Capacity

3 = 1 Mbit (128K x 8)

4 = 2 Mbit (256K x 8)

2nd Flash Memory

2 = 256 Kbit Flash memory + SRAM

3 = SRAM but no Flash memory

4 = 256 Kbit Flash memory but no SRAM

5 = no Flash memory + no SRAM

Operating Voltage

blank = V = 4.5 to 5.5V

CC

V = V = 3.0 to 3.6V

CC

Speed

70 = 70ns

90 = 90ns

12 = 120ns

15 = 150ns

20 = 200ns

Package

J = PLCC52

M = PQFP52

U = TQFP64

Temperature Range

blank = 0 to 70°C (commercial)

I = –40 to 85°C (industrial)

Option

T = Tape & Reel Packing

For a list of available options (e.g., speed, package) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

105/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

APPENDIX A. PQFP52 PIN ASSIGNMENTS

Table 77. PQFP52 Connections (Figure 2)

Pin Number

Pin Assignments

Pin Number

Pin Assignments

1

PD2

PD1

PD0

PC7

PC6

PC5

PC4

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

AD4

AD5

AD6

AD7

2

3

4

5

V

CC

6

AD8

AD9

7

V

CC

8

AD10

AD11

AD12

AD13

AD14

AD15

CNTL0

RESET

CNTL2

CNTL1

PB7

9

GND

PC3

PC2

PC1

PC0

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

AD2

AD3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

PB6

GND

PB5

PB4

PB3

PB2

PB1

PB0

106/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

APPENDIX B. PLCC52 PIN ASSIGNMENTS

Table 78. PLCC52 Connections (Figure 3)

Pin Number

Pin Assignments

Pin Number

Pin Assignments

1

GND

PB5

PB4

PB3

PB2

PB1

PB0

PD2

PD1

PD0

PC7

PC6

PC5

PC4

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

PA2

PA1

PA0

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

V

CC

AD8

AD9

V

CC

AD10

AD11

AD12

AD13

AD14

AD15

CNTL0

RESET

CNTL2

CNTL1

PB7

GND

PC3

PC2 (V

)

STBY

PC1

PC0

PA7

PA6

PA5

PA4

PA3

GND

PB6

107/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

APPENDIX C. TQFP64 PIN ASSIGNMENTS

Table 79. TQFP64 Connections (Figure 4)

Pin Number

Pin Assignments

Pin Number

33

Pin Assignments

1

PD2

PD1

PD0

PC7

PC6

PC5

AD3

AD4

AD5

AD6

AD7

2

34

3

35

4

36

5

37

6

V

CC

38

V

CC

7

V

CC

39

V

8

40

AD8

AD9

CC

V

CC

41

9

42

AD10

AD11

AD12

AD13

AD14

AD15

CNTL0

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

GND

PC3

PC2

PC1

PC0

NC

43

44

45

46

47

48

NC

49

NC

50

RESET

CNTL2

CNTL1

PB7

PA7

PA6

PA5

PA4

PA3

GND

PA2

PA1

PA0

AD0

AD1

N/D

AD2

51

52

53

54

PB6

55

GND

PB5

56

57

58

PB4

59

PB3

60

PB2

61

PB1

62

PB0

63

NC

64

NC

108/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

REVISION HISTORY

Table 80. Document Revision History

Date

Rev.

Description of Revision

15-Oct-99

27-Oct-00

30-Nov-00

23-Oct-01

07-Apr-03

12-Jun-03

02-Oct-03

17-Nov-03

1.0 Initial release as a WSI document

1.1 Port A Peripheral Data Mode Read Timing, changed to 50

1.2 PSD85xF2 added

2.0 Document rewritten using the ST template

3.0 v2.2 Template applied; voltage correction (Table 76)

3.1 Fix errors in PQFQ52 Connections (Table 77)

3.2 Correct Instructions (Table 9); update disclaimer, Title for EDOCS application

3.3 Correct package references (Figure 1)

Reformatted (adjust RPN list); added Table 8; added ‘U’ package (64-pin) (Figure 1, 4, 53;

Table 75, 76, 79); 5V split from original

04-Jun-04

4.0

109/110

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequ

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are s

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products a

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectron

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -

Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -

Spain - Sweden - Switzerland - United Kingdom - United States

www.st.com

110/110


型号：	PSD854512MT
厂家：	ST
描述：	Flash In-System Programmable ISP Peripherals For 8-bit MCUs Flash在系统可编程ISP外设对于8位MCU
文件：	总110页 (文件大小：1732K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PSD854512MT [STMICROELECTRONICS]

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