RHRXH162373K1 [STMICROELECTRONICS]

Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs; 抗辐射低电压CMOS 16位D型锁存器（三态）与3.6 V容限输入和输出


型号：	RHRXH162373K1
厂家：	ST
描述：	Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs 抗辐射低电压CMOS 16位D型锁存器（三态）与3.6 V容限输入和输出总线驱动器总线收发器锁存器逻辑集成电路 CD
文件：	总18页 (文件大小：506K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

54VCXH162373

Rad hard low voltage CMOS 16-bit D-type latch (3-state)

with 3.6 V tolerant inputs and outputs

Features

■ 1.65 to 3.6 V inputs and outputs

■ High speed:

– t = 3.3 ns (Max.) at V = 3.0 to 3.6 V

– t = 4.5 ns (Max.) at V = 2.3 to 2.7 V

■ Symmetrical impedance outputs:

– |I | = I = 12 mA (Min.) at V = 3.0 V

Flat-48

– |I | = I = 8 mA (Min.) at V = 2.3 V

■ Power down protection on inputs and outputs

■ 26 Ω serie resistors in outputs

The upper metallic lid is not electrically connected to any

pins, nor to the IC die inside the package.

■ Operating voltage range:

– V (Opr) = 1.65 V to 3.6 V

Description

■ Pin and function compatible with 54 series

HR162373

The 54VCXH162373 is a low voltage CMOS 16

bit d-type latch with 3 state outputs non inverting

fabricated with sub-micron silicon gate and five-

layer metal wiring C²MOS technology. It is ideal

for low power and very high speed 1.65 to 3.6 V

applications; it can be interfaced to 3.6 V signal

environment for both inputs and outputs. These

16 bit D-type latches are bite controlled by two

latch enable inputs (nLE) and two output enable

inputs (OE). While the nLE input is held at a high

level, the nQ outputs will follow the data input

precisely. When the nLE is taken low, the nQ

outputs will be in a normal logic state (high or low

logic level) and while high level the outputs will be

in a high impedance state. Bus hold on data

inputs is provided in order to eliminate the need

for external pull-up or pull-down resistor. The

device circuits is including 26 Ω series resistance

in the outputs. These resistors permit to reduce

line noise in high speed applications. All inputs

and outputs are equipped with protection circuits

against static discharge, giving them 2 kV ESD

immunity and transient excess voltage.

■ Bus hold provided on both sides

■ Cold spare function

■ Latch-up performance exceeds

300 mA (JESD 17)

■ ESD performance:

– HBM > 2000 V

(MIL STD 883 method 3015); MM > 200 V

■ 300 krad Mil1019.6 condition A, (RHA QML

qualification extension undergone)

■ No SEL, no SEUand no SET under 110

Mev/cm2/mg LET heavy ions irradiation

■ QML qualified product

■ Device fully compliant with

DSCC SMD 5962-05211

■ 100 mV typical input hysteresis

August 2011

Doc ID 10653 Rev 7

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www.st.com

Contents

54VCXH162373

Contents

Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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54VCXH162373

Logic symbols and I/O equivalent circuit

Figure 1.

IEC logic symbols

Figure 2.

Input and output equivalent circuit

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Logic symbols and I/O equivalent circuit

54VCXH162373

Figure 3.

Logic diagram

Note:

This logic diagram has not to be used to estimate propagation delays

4/18

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54VCXH162373

Pin settings

2.1

Pin connection

Figure 4.

Pin connection (top through view)

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Pin settings

54VCXH162373

2.2

Pin description

Table 1.

Pin description

Pin n°

Symbol

Name and function

3 state output enable input (active LOW)

1OE

2, 3, 5, 6, 8, 9, 11, 12

13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 3-state outputs

1Q0 to 1Q7 3-state outputs

2OE

2LE

3 state output enable input (active LOW)

Latch enable input

36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 Data inputs

47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 Data inputs

1LE

GND

V_CC

Latch enable input

Ground (0 V)

4, 10, 15, 21, 28, 34, 39, 45

7, 18, 31, 42

Positive supply voltage

2.3

Truth table

Table 2.

Truth table

Inputs

Output

No change ⁽¹⁾

1. Q outputs are latched at the time when the LE input is taken low logic level.

Note:

X = Do not care; Z = High impedance

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54VCXH162373

Maximum rating

Stressing the device above the rating listed in the “absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 3.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

V_CC

V_I

Supply voltage

-0.5 to +4.6

-0.5 to V_CC+ 0.5

- 50

DC input voltage

V_O

I_IK

DC output voltage (OFF state)

DC output voltage (High or low state) ⁽¹⁾

DC input diode current

DC output diode current ⁽²⁾

DC output current

I_OK

I_O

_CCor

- 50

± 50

DC V_CCor ground current per supply pin

± 100

I_GND

P_D

Power dissipation

400

-65 to +150

260

°C

T_stg

T_L

Storage temperature

Lead temperature (10 sec)

°C

1. I_Oabsolute maximum rating must be observed

2. V_O< GND, V_O> V_CC

3.1

Recommended operating conditions

Table 4.

Symbol

Recommended operating conditions

Parameter

Value

Unit

V_CC

V_I

Supply voltage

1.8 to 3.6

-0.3 to 3.6

0 to 3.6

0 to V_CC

± 12

Input voltage

V_O

Output voltage (OFF state)

Output voltage (high or low state)

_OH, I_OLHigh or low level output current (V_CC= 3.0 to 3.6 V)

°C

ns/V

I_OH, I_OLHigh or low level output current (V_CC= 2.3 to 2.7 V)

± 8

T_op

Operating temperature

Input rise and fall time ⁽¹⁾

-55 to 125

0 to 10

dt/dv

1. V_INfrom 0.8 V to 2 V at V_CC= 3.0 V

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Electrical characteristics

54VCXH162373

Electrical characteristics

2.7 V < V < 3.6 V unless otherwise specified

Table 5.

DC specifications

Test condition

Value

-55 to 125°C

Symbol

Parameter

Unit

V_CC

(V)

Min.

Max.

V_IH

V_IL

High level input voltage

Low level input voltage

2.0

2.7 to 3.6

0.8

2.7 to 3.6

2.7

I_O=-100 μA

V_CC-0.2

2.2

I_O=-6 mA

I_O=-8 mA

High level output

voltage

V_OH

2.4

3.0

I_O=-12 mA

I_O=100 μA

I_O=6 mA

2.2

2.7 to 3.6

2.7

0.2

0.4

Low level output

voltage

V_OL

I_O=8 mA

0.55

0.8

3.0

2.7 to 3.6

3.0

I_O=12 mA

V_I= 0 to 3.6 V

V_I= 0.8 V

V_I= 2 V

I_I

Input leakage current

± 5

μA

I_I(HOLD)Input hold current

-75

3.6

V_I= 0 to 3.6 V

± 500

Power Off leakage

current

I_off

V_Ior V_O= 0 to 3.6 V

μA

High impedance output

leakage current

V_I= V_IHor V_IL

V_O= 0 to 3.6 V

I_OZ

2.7 to 3.6

± 10

V_I= V_CCor GND

V_Ior V_O= V_CCto 3.6 V

V_IH= V_CC- 0.6 V

Quiescent supply

current

I_CC

2.7 to 3.6

μA

± 20

750

ΔI_CC

I_CCincr. per Input

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54VCXH162373

2.3 V < V < 2.7 V unless otherwise specified

Electrical characteristics

Table 6.

Symbol

DC specifications

Parameter

Test condition

Value

-55 to 125 °C

Unit

V_CC

(V)

Min.

Max.

V_IH

V_IL

High level input voltage

Low level input voltage

1.6

2.3 to 2.7

0.7

I_O= -100 μA

V_CC-0.2

2.0

I_O= -4 mA

I_O= -6 mA

I_O= -8 mA

I_O= 100 μA

I_O= 6 mA

V_OH

High level output voltage

2.3

1.8

1.7

2.3 to 2.7

2.3

0.2

0.4

0.6

± 5

V_OL

Low level output voltage

Input leakage current

I_O= 8 mA

I_I

2.3 to 2.7

2.3

V_I= V_CCor GND

V_I= 0.7 V

μA

I_I(HOLD)Input hold current

V_I= 1.7 V

-45

Power Off leakage

current

I_off

V_Ior V_O= 0 to 3.6 V

μA

High impedance output

leakage current

V_I= V_IHor V_IL

V_O= 0 to 3.6 V

I_OZ

2.3 to 2.7

± 10

V_I= V_CCor GND

Quiescent supply

current

I_CC

2.3 to 2.7

μA

V_Ior V_O=

V_CCto 3.6 V

± 20

T = 25 °C, Input t = t = 2.0 ns, C = 30 pF, R = 500 Ω

Table 7.

Dynamic switching characteristics

Test condition

Value

Symbol

Parameter

T_A= 25 °C

Unit

V_CC

(V)

Min. Typ. Max.

2.5

3.3

2.5

3.3

2.5

3.3

0.25

0.35

-0.25

-0.35

2.05

2.65

Dynamic valley low voltage

quiet output ^{(1) (2)}

_IL= 0 V

V_OLV

V_OHV

V_IH= V_CC

Dynamic valley high voltage

quiet output ^{(2) (3)}

V_IL= 0 V

V_IH= V_CC

Dynamic valley high voltage

quiet output ^{(2) (3)}

V_IL= 0 V

V_IH= V_CC

1. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to

HIGH. The remaining output is measured in the LOW state.

2. Parameters guaranteed by design.

3. Number of outputs defined as “n”. Measured with “n-1” outputs switching from HIGH to LOW or LOW to

HIGH. The remaining output is measured in the HIGH state.

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Electrical characteristics

54VCXH162373

C = 30 pF, R = 500 Ω, Input t = t = 2.0 ns

Table 8.

AC electrical characteristics

Test condition

Value

-55 to 125 °C

Symbol

Parameter

Unit

V_CC

(V)

Min.

Max.

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

2.3 to 2.7

3.0 to 3.6

1.0

0.8

1.0

0.8

1.0

0.8

1.0

0.8

1.0

1.5

5.2

4.0

5.7

4.2

6.2

4.7

5.1

4.8

Propagation delay

time Dn to Qn

_PLHt_PHL

Propagation delay

time LE to Qn

t_{PLH PHL}

t_{PZL PZH}

Output enable time

Output disable time

t_{PLZ PHZ}

Setup tIme, HIGH or

LOW level Dn to LE

t_s

Hold time HIGH or

LOW level Dn to LE

t_h

t_w

LE pulse width, HIGH

0.5

Output to output skew

time ^{(1) (2)}

_OSLHt_OSHL

1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

outputs of the same device switching in the same direction, either HIGH or LOW (t_OSLH= | t_PLHm- t_PLHn|,

t_OSHL= | t_PHLm- t_PHLn|)

2. Parameter guaranteed by design

Table 9.

Symbol

Capacitive characteristics

Test condition

V_CC

Value

Parameter

T_A= 25 °C

Unit

(V)

Min. Typ. Max.

C_IN

Input capacitance

Output capacitance

2.5 or 3.3 V_IN= 0 or V_CC

C_OUT

Power dissipation

capacitance ⁽¹⁾

_IN= 10MHz

C_PD

2.5 or 3.3

V_IN= 0 or V_CC

1. C_PDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the

operating current consumption without load. (Refer to Test Circuit). Average operating current can be

obtained by the following equation. I_CC(opr)= C_PDx V_CCx f_IN+ I_CC/16 (per circuit)

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54VCXH162373

Test circuit

Figure 5.

Test circuit

Table 10. Test circuit

Test

Switch

_PLH, t_PHL

Open

6 V

t_PZL, t_PLZ(V_CC= 3.0 to 3.6 V)

t_PZL, t_PLZ(V_CC= 2.3 to 2.7 V)

t_PZH, t_PHZ

2 V_CC

GND

C = 30 pF or equivalent (includes jig and probe capacitance)

R = R = 500 Ω or equivalent

R = Z

of pulse generator (typically 50 Ω)

OUT

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Waveforms

54VCXH162373

Waveforms

Table 11. Waveform symbol value

Symbol

V_CC

3.0 to 3.6 V

2.3 to 2.7 V

V_IH

V_M

V_X

V_Y

2.7 V

1.5 V

V_CC

V_CC/2

V_OL+0.3 V

V_OH-0.3 V

V_OL+0.15 V

V_OH-0.15 V

Figure 6.

Waveform - LE TO Qn propagation delays, LE minimum pulse width, Dn to

LE setup and hold times (f = 1 MHz; 50% duty cycle)

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54VCXH162373

Figure 7.

Waveforms

Waveform - output enable and disable time (f = 1 MHz; 50% duty cycle)

Figure 8.

Waveform - propagation delay time (f = 1 MHz; 50% duty cycle)

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Package mechanical data

54VCXH162373

Package mechanical data

54VCXH162373 products are supplied into ceramic body / metal lid hermetic Flat 48-pin

space package

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Table 12.

Dim.

Flat-48 (MIL-STD-1835) mechanical data

inch

Typ.

Min.

Typ.

Max.

Min.

Max.

2.18

0.20

0.12

15.57

9.52

6.22

1.52

2.47

0.254

0.15

15.75

9.65

6.35

1.65

0.635

0.20

8.38

0.79

0.43

2.72

0.30

0.18

15.92

9.78

6.48

1.78

0.086

0.008

0.005

0.613

0.375

0.245

0.060

0.097

0.010

0.006

0.620

0.380

0.250

0.065

0.025

0.008

0.330

0.031

0.017

0.107

0.012

0.007

0.627

0.385

0.255

0.070

6.85

0.66

0.25

9.40

0.92

0.61

0.270

0.026

0.010

0.370

0.036

0.024

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Figure 9.

Package mechanical data

Package dimension

7330585B

Note:

The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the

package. Connecting unused pins or metal lid to ground or to the power supply will not affect

the electrical characteristics.

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Order codes

54VCXH162373

Order codes

Table 13. Ordering information

Flight models

QML-V

Min op.

voltage

Lead

finish

Radiation

level

Package

Engineering model

Packing

48-pin flat 1.8 V Gold plated 300 krad RHFXH162373K03V RHRXH162373K1 Conductive strip pack

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Revision history

Table 14. Document revision history

Date

Revision

Changes

09-Jul-2004

17-May-2005

19-Jun-2006

30-Jul-2007

17-Sep-2008

23-Sep-2009

First release

SMD qualified

300 krad bullet updated, new template, mechanical data updated

Typo in Table 12 on page 14.

Updated cover page

Updated Table 13 on page 16

Added Note: on page 15 and in the "Pin connections" diagram on the

coverpage

02-Aug-2011

Doc ID 10653 Rev 7

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54VCXH162373

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18/18

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RHRXH162373K1 [STMICROELECTRONICS]

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