ST1L05APU33R [STMICROELECTRONICS]
Very low quiescent current BiCMOS voltage regulator;
| 型号： | ST1L05APU33R |
| 厂家： | 
ST |
| 描述： | Very low quiescent current BiCMOS voltage regulator 信息通信管理 光电二极管 输出元件 调节器 |
| 文件： | 总30页 (文件大小：1105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST1L05
Very low quiescent current BiCMOS voltage regulator
Datasheet
-
production data
Description
The ST1L05 is a low drop linear voltage regulator,
which supplies up to 1.3 A output current.
The output voltage is fixed at 1.8 V, 2.5 V, 3.3 V
and it is adjustable. It is available in three different
versions with different pinouts.
DFN6 (3x3 mm)
DFN8 (4x4 mm)
Thanks to BiCMOS technology, the quiescent
current is controlled and maintained below
650 µA over the entire allowed junction
temperature range. The ST1L05 is stable with low
ESR output ceramic capacitors.
Features
• Fixed output voltage: 1.8 V, 2.5 V, 3.3 V and
ADJ
Internal protection circuitry includes thermal
protection with hysteresis and overcurrent
limiting.
• Output voltage tolerance: ± 2% at 25 °C
• Output current capability: 1.3 A
• Very low quiescent current: max. 650 µA
• Typ. dropout 0.3 V (@ IO = 1.3 A)
• Enable function for B, C and D versions
• Power Good function for B and D versions
• Stable with low ESR ceramic capacitors
• Thermal shutdown protection with hysteresis
• Overcurrent protection
The ST1L05 is suitable for data storage
applications such as HDDs, where it can supply
3.3 V required by read channel and memory
chips.
The regulator is available in the small and thin
DFN6 (3x3 mm) and DFN8 (4x4 mm) packages.
• Operating junction temperature range: from 0
to 125 °C
Table 1. Device summary
Package
Order codes
Output voltage
ST1L05PU25R
ST1L05APU33R
ST1L05BPUR
DFN6 (3x3 mm)
DFN6 (3x3 mm)
DFN6 (3x3 mm)
DFN6 (3x3 mm)
DFN8 (4x4 mm)
2.5 V
3.3 V
ADJ
ST1L05CPU33R
ST1L05DPUR
3.3 V
ADJ
May 2014
DocID14492 Rev 3
1/30
This is information on a product in full production.
www.st.com
Contents
ST1L05
Contents
1
2
3
4
5
6
Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
6.3
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Enable function (ST1L05B, ST1L05C and ST1L05D only) . . . . . . . . . . . 20
Power Good function (ST1L05B and ST1L05D only) . . . . . . . . . . . . . . . . 20
7
8
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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ST1L05
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ESD data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ST1L05PU25R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ST1L05APU33R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ST1L05CPU33R electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ST1L05BPUR and ST1L05DPUR electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12
DFN6 (3x3 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DFN8 (4x4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DFN6 (3x3 mm) tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DFN8 (4x4 mm) reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of figures
ST1L05
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
ST1L05 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ST1L05A schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ST1L05B and ST1L05D schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ST1L05C schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output voltage vs temperature VO = 1.22 V, IO = 10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage vs temperature VO = 1.22 V, IO = 1.3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage vs temperature VO = 2.5 V, IO = 10 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage vs temperature VO = 2.5 V, IO = 1.3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Line regulation vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Load regulation vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Dropout voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. ESR required for stability with ceramic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Quiescent current vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Quiescent current vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16. Enable voltage vs temperature VI = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. Enable voltage vs temperature VI = 5.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Supply voltage rejection vs temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Supply voltage rejection vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Load transient. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21. Short-circuit removal transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Line transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Enable transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. ST1L05 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. ST1L05A application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. ST1L05B and ST1L05D application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. ST1L05C application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28. DFN6 (3x3 mm) drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. DFN6 (3x3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. DFN8 (4x4 mm) drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. DFN8 (4x4 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. DFN6 (3x3 mm) tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. DFN6 (3x3 mm) reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 34. DFN8 (4x4 mm) carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 35. DFN8 (4x4 mm) reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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ST1L05
Schematic diagram
1
Schematic diagram
Figure 1. ST1L05 schematic diagram
VI
VI
BandGap
reference
Current
limit
OpAmp
VO
Thermal
protection
VO_SENSE
R1
R2
GND
Figure 2. ST1L05A schematic diagram
VI
VI
BandGap
reference
Current
limit
OpAmp
VO
Thermal
protection
R1
R2
GND
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30
Schematic diagram
ST1L05
Figure 3. ST1L05B and ST1L05D schematic diagram
VI
PG
Power-good
signal
VI
BandGap
reference
Current
limit
OpAmp
VO
Thermal
protection
VI
ADJ
RP
EN
Internal
enable
GND
Figure 4. ST1L05C schematic diagram
VI
VI
BandGap
reference
Current
limit
OpAmp
VO
Thermal
protection
VI
ADJ
RP
EN
Internal
enable
GND
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DocID14492 Rev 3
ST1L05
Pin configuration
2
Pin configuration
Figure 5. Pin connections (top view)
ST1L05
ST1L05B
ST1L05A
ST1L05D
ST1L05C
Table 2. Pin description
Pin
ST1L05 ST1L05A ST1L05B ST1L05C ST1L05D
Symbol
Function
Supply voltage input pin. Bypass with a
4.7 µF capacitor to GND
VI
6
4
3
2
6
4
6
4
8
6
Output voltage pin. Bypass with a 4.7 µF
capacitor to GND
VO
GND
ADJ
2
-
6
2
2
-
2
7
Ground pin
-
5
Adjust pin
VO_SENSE
PG
5
-
-
5
-
-
VO sense
-
-
-
3
3
Power Good pin
EN
-
1
1
3
1
Enable pin. Internal pull-up to VI
Not connected
N.C.
1-3
1-4-5
-
4-5
GND
Exposed
Exposed pad has to be connected to GND
DocID14492 Rev 3
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30
Maximum ratings
ST1L05
3
Maximum ratings
Table 3. Absolute maximum ratings
Parameter
Symbol
Value
Unit
VI
DC supply voltage
-0.3 to 7
-0.3 to 7
V
V
VO
PG
EN
DC output voltage
Power Good
Enable pin
-0.3 to 7
V
-0.3 to 7
V
ADJ/VOUT_SENSE Adjust pin or VO sense
4
V
PD
IO
Power dissipation
Internally limited
Internally limited
0 to 150
W
A
Output current
TOP
TSTG
TLEAD
Operating junction temperature range
Storage temperature range(1)
Lead temperature (soldering) 10 seconds
°C
°C
°C
-65 to 150
260
1. Storage temperature > 125 °C is acceptable only if the regulator is soldered to a PCBA.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4. Thermal data
Symbol
Parameter
DFN6
DFN8
Unit
RthJC
RthJA
Thermal resistance junction-case
Thermal resistance junction-ambient
10
55
4
°C/W
°C/W
40
Table 5. ESD data
Parameter
Human body model
Machine model
Symbol
Value
Unit
HBM
MM
2
kV
V
150
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DocID14492 Rev 3
ST1L05
Electrical characteristics
4
Electrical characteristics
Refer to the typical application schematic, VI = 3.3 V to 4.5 V, IO = 5 mA to 1.3 A,
CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is
TJ = 25 °C unless otherwise specified.
Table 6. ST1L05PU25R electrical characteristics
Symbol
Parameter
Output voltage
Test conditions
Min.
Typ.
Max.
Unit
VO
VO
VI = 3.3 V to 5.25 V, T = 25 °C
VI = 3.3 V to 5.25 V
2.45
2.5
2.5
2.55
2.5625
15
V
V
Output voltage
Line regulation
Load regulation
Output current limit
2.4375
ΔVO
ΔVO
IS
VI = 4.75 V to 5.25 V
VI = 4.75 V, IO = 10 mA to 1.3 A
VI = 5.5 V
mV
mV
A
15
30
1.3
Minimum output current for
regulation
IOMIN
0
mA
IO = 0.8 A
0.2
0.25
0.3
0.4
0.45
0.5
V
V
V
Vd
Dropout voltage
IO = 1 A
IO = 1.3 A
VI = 5 V, IO = 2 mA to 1.3 A,
T = 25 °C
350
500
650
IQ
Quiescent current
µA
VI = 5.5 V, IO = 2 mA to 1.3 A
350
68
SVR
eN
Supply voltage rejection(1)
RMS output noise(1)
VI = 5 ± ±0.5 V, IO = 5 mA, f = 120 Hz
50
dB
B = 10 Hz to 10 kHz, VI = 5 V,
IO = 5 mA
0.003
%VO
VI = 5 V, any 200 mA step from
100 mA to 1.3 A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising)(1)(2)
ΔVO/ΔIO Load transient (falling)(1)(2)
ΔVO/ΔVI Start-up transient(1)(2)
5
%VO
V
VI = 5 V, IO = 1.3 A to 10 mA,
2.75
2.75
2.75
tF ≥±1 µs
VI = 0 V to 5 V, IO = 10 mA to 1.3 A,
tR ≥±1 µs
V
Short-circuit removal
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
V
response(1)(2)
TSH
Thermal shutdown trip point(1) VI = 5 V
165
°C
1. Guaranteed by design. Not tested in production.
2. C = 10 µF, C = 10 µF, all X7R ceramic capacitors.
I
O
DocID14492 Rev 3
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30
Electrical characteristics
ST1L05
Refer to the typical application schematic, VI = 4.5 V to 5.5 V, IO = 5 mA to 1.3 A,
CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is
TJ = 25 °C unless otherwise specified.
Table 7. ST1L05APU33R electrical characteristics
Symbol
Parameter
Output voltage
Test conditions
Min.
Typ.
Max. Unit
VO
VO
VI = 4.75 V to 5.25 V, T = 25 °C
VI = 4.75 V to 5.25 V
3.234
3.3
3.3
3.366
3.3825
15
V
V
Output voltage
Line regulation
Load regulation
Output current limit
3.2175
ΔVO
ΔVO
IS
VI = 4.75 V to 5.25 V
mV
mV
A
VI = 4.75 V, IO = 10 mA to 1.3 A
VI = 5.5 V
15
30
1.3
Minimum output current for
regulation
IOMIN
0
mA
IO = 0.8 A
IO = 1 A
0.2
0.25
0.3
0.4
0.45
0.5
V
V
V
Vd
Dropout voltage
I
O = 1.3 A
VI = 5 V, IO = 2 mA to 1.3 A,
T = 25 °C
350
500
650
IQ
Quiescent current
µA
VI = 5.5 V, IO = 2 mA to 1.3 A
350
65
SVR
eN
Supply voltage rejection(1)
RMS output noise(1)
VI = 5 ± ±0.5 V, IO = 5 mA, f = 120 Hz
50
dB
B = 10 Hz to 10 kHz, VI = 5 V,
IO = 5 mA
0.003
%VO
VI = 5 V, any 200 mA step from
100 mA to 1.3 A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising)(1)(2)
ΔVO/ΔIO Load transient (falling)(1)(2)
ΔVO/ΔVI Start-up transient(1)(2)
5
%VO
V
VI = 5 V, IO = 1.3 A to 10 mA,
3.6
3.5
3.5
tF ≥±1 µs
VI = 0 V to 5 V, IO = 10 mA to 1.3 A,
V
tR ≥±1 µs
Short-circuit removal
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
V
response (1)(2)
TSH
Thermal shutdown trip point(1) VI = 5 V
165
°C
1. Guaranteed by design. Not tested in production.
2. C = 10µF, C = 10µF, all X7R ceramic capacitors.
I
O
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DocID14492 Rev 3
ST1L05
Electrical characteristics
Refer to the typical application schematic, VI = 4.5 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A,
CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is
TJ = 25 °C unless otherwise specified.
Table 8. ST1L05CPU33R electrical characteristics
Symbol
Parameter
Output voltage
Test conditions
Min.
Typ.
Max. Unit
VO
VO
VI = 4.75 V to 5.25 V, T = 25 °C
VI = 4.75 V to 5.25 V
3.234
3.3
3.3
3.366
3.3825
15
V
V
Output voltage
Line regulation
Load regulation
Output current limit
3.2175
ΔVO
ΔVO
IS
VI = 4.75 V to 5.25 V
mV
mV
A
VI = 4.75 V, IO = 10 mA to 1.3 A
VI = 5.5 V
15
30
1.3
Minimum output current for
regulation
IOMIN
0
mA
IO = 0.8 A
IO = 1 A
0.2
0.25
0.3
0.4
0.45
0.5
V
V
V
Vd
Dropout voltage
I
O = 1.3 A
VI = 5 V, IO = 2 mA to 1.3 A,
T = 25 °C
350
350
500
650
IQ
Quiescent current
µA
V
VI = 5.5 V, IO = 2 mA to 1.3 A
VI = 4.5 V to 5.25, IO = 50 mA
VI = 4.5 V to 5.25, IO = 50 mA
VEN = VI = 5 V
VEN_H Enable threshold high
VEN_L Enable threshold low
2
0.8
2
IEN
Enable pin current
µA
dB
VI = 5 ± ±0.5 V, IO = 5 mA,
f = 120 Hz
SVR
Supply voltage rejection(1)
50
65
B = 10 Hz to 10 kHz, VI = 5 V,
eN
RMS output noise(1)
0.003
%VO
%VO
V
I
O = 5 mA
VI = 5 V, any 200 mA step from
100 mA to 1.3 A, tR ≥±1 µs
ΔVO/ΔIO Load transient (rising) (1)(2)
ΔVO/ΔIO Load transient (falling)(1)(2)
ΔVO/ΔVI Start-up transient (1)(2)
5
VI = 5 V, IO = 1.3 A to 10 mA,
3.6
3.5
3.5
tF ≥±1 µs
VI = 0 V to 5 V, IO = 10 mA to 1.3 A,
tR ≥±1 µs
V
Short-circuit removal
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
VI = 5 V
V
response (1)(2)
TSH
Thermal shutdown trip point(1)
165
°C
1. Guaranteed by design. Not tested in production.
2. C =10 µF, C =10 µF, all X7R ceramic capacitors.
I
O
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30
Electrical characteristics
ST1L05
Refer to the typical application schematic, VI = 3 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A,
CI = CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Intended typical value is
TJ = 25 °C unless otherwise specified.
Table 9. ST1L05BPUR and ST1L05DPUR electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VI = 3 V to 5.25 V,
VO
Output voltage
1.195
1.18
1.22
1.22
1.245
V
T = 25 °C
VO
Output voltage
Line regulation
VI = 3 V to 5.25 V
VI = 4.75 V to 5.25 V
1.256
15
V
ΔVO
mV
VI = 4.75 V, IO = 10 mA to
1.3 A
ΔVO
Load regulation
15
1
30
mV
IADJ
IS
Adjust pin current
Output current limit
VI = 3 V to 5.25 V
VI = 5.5 V
nA
A
1.3
Minimum output current for
regulation
IOMIN
1
mA
IO = 0.8 A, VO = 3.3 V
0.2
0.25
0.3
V
V
V
Vd
Dropout voltage (1)
IO = 1 A, VO = 3.3 V
IO = 1.3 A, VO = 3.3 V
VI = 5 V, IO = 2 mA to 1.3 A,
T = 25 °C
300
350
500
IQ
Quiescent current
µA
VI = 5.5 V, IO = 2 mA to 1.3 A
Device OFF(2)
650
1
VEN_H Enable threshold high
VEN_L Enable threshold low
VI = 3 V to 5.25, IO = 50 mA
VI = 3 V to 5.25, IO= 50 mA
VEN = VI = 5 V
2
V
µA
V
0.8
2
IEN
Enable pin current
Rising edge
0.92 VO
0.8 VO
Power Good output threshold
Falling edge
PG
Power Good output voltage
low(3)
ISINK = 6 mA open drain output
0.4
V
VI = 5 ± ±0.5 V, IO = 5 mA,
SVR
eN
Supply voltage rejection(3)
RMS output noise(3)
50
72
dB
f = 120 Hz
B = 10 Hz to 10 kHz, VI = 5 V,
IO = 5 mA
0.003
%VO
VI = 5 V, any 200 mA step
ΔVO/ΔIO Load transient (rising)(3)(4)
ΔVO/ΔIO Load transient (falling)(3)(4)
ΔVO/ΔVI Start-up transient(3)(4)
5
%VO
V
from 100 mA to 1.3 A, tR ≥±1 µs
VI = 5 V, IO = 1.3 A to 10 mA,
tF ≥ 1 µs
1.38
1.38
VI = 0 V to 5 V,
V
IO = 10 mA to 1 A, tR ≥±1 µs
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ST1L05
Symbol
Electrical characteristics
Table 9. ST1L05BPUR and ST1L05DPUR electrical characteristics (continued)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Short-circuit removal
response(3)(4)
ΔVO/ΔIO
VI = 5 V, IO = short to 10 mA
1.38
V
TSH
Thermal shutdown trip point (3) VI = 5 V
165
°C
1. See minimum start-up voltage, V = 2.9 V.
I
2. PG pin floating.
3. Guaranteed by design. Not tested in production.
4. C = 10 µF, C = 10 µF, all X7R ceramic capacitors.
I
O
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13/30
30
Typical characteristics
ST1L05
5
Typical characteristics
Figure 6. Output voltage vs temperature
VO = 1.22 V, IO = 10 mA
Figure 7. Output voltage vs temperature
VO = 1.22 V, IO = 1.3 A
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
VEN = VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
-5 20 45 70
VEN = VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
-30
95
120
145
-30
-5
20
45
70
95
120
145
T [°C]
T [°C]
Figure 8. Output voltage vs temperature
VO = 2.5 V, IO = 10 mA
Figure 9. Output voltage vs temperature
VO = 2.5 V, IO = 1.3 A
2.70
2.70
VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
-30
-5
20
45
T [°C]
70
95
120
145
-30
-5
20
45
T [°C]
70
95
120
145
Figure 10. Line regulation vs temperature
Figure 11. Load regulation vs temperature
50
20
VEN = VI = from 4.75 to 5.25 V, IO = 0.005 A, CIN = CO = 4.7 µF
VEN = VI = 4.75 V, IO = from 0.01 to 1.3 A, CI = CO = 4.7 µF
15
40
10
5
30
20
10
0
0
-5
-10
-15
-20
-30
-5
20
45
T [°C]
70
95
120
-30
-5
20
45
T [°C]
70
95
120
145
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ST1L05
Typical characteristics
Figure 12. Dropout voltage vs temperature
Figure 13. ESR required for stability with
ceramic capacitors
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
CI = CO = 4.7 µF, VO @ 3.3 V
IO = 800 mA
IO = 1 A
CI = 4.7 µF, VEN = VI = from 3 V to 5.5 V, IO = from 5 mA to 1.3 A
0.35
0.3
IO = 1.3 A
0.25
0.2
0.15
0.1
Stable zone
0.05
0
0
2
4
6
8
10
12
14
16
18
20
22
-30
-5
20
45
70
95
120
145
CO [µF] (nominal value)
T [°C]
Figure 14. Quiescent current vs temperature
Figure 15. Quiescent current vs output current
400
700
VEN = VI = 5.5 V, CI = CO = 4.7 µF
VEN = VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
350
600
300
250
200
150
100
50
500
400
300
200
100
0
0
-30
-5
20
45
70
T [°C]
95
120
145
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
IO [A]
Figure 16. Enable voltage vs temperature
VI = 3 V
Figure 17. Enable voltage vs temperature
VI = 5.25 V
2.5
2.5
ON
VI = 5.25 V, IO = 50 mA, CI = CO = 4.7 µF
VI = 3 V, IO = 50 mA, CI = CO = 4.7 µF
ON
OFF
2
1.5
1
2
1.5
1
OFF
0.5
0
0.5
0
-30
-5
20
45
70
95
120
145
-30
-5
20
45
70
95
120
145
T [°C]
T [°C]
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30
Typical characteristics
ST1L05
Figure 18. Supply voltage rejection vs
temperature
Figure 19. Supply voltage rejection vs
frequency
80
75
70
65
80
70
60
50
40
30
20
60
VEN = VI = from 3 to 5.5 V, IO = 5 mA, VO = 1.22 V,
55
CI = CO = 4.7 µF, F = 120 Hz
VEN = VI = 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF
50
-30
-5
20
45
70
95
120
145
10
100
1000
10000
100000
1000000
Frequency [Hz]
T[°C]
Figure 20. Load transient
Figure 21. Short-circuit removal transient
IO=10 mA to 1.3 A, CI=CO=10 µF, VEN=VI=5 V, VO@3.3 V
IO=10 mA to short, CI=CO=10 µF, VEN=VI=5.5 V
Figure 22. Line transient
Figure 23. Enable transient
VEN
VI
VO
VO
CO=CI=4.7 µF, VEN=0 to 2 V, VI=5.5 V, IO=5 mA
CI=CO=4.7 µF, VI=3 to 5.5V, IO=5 mA
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ST1L05
Application information
6
Application information
The ST1L05 is a low-dropout linear regulator. It provides up to 1.3 A with a low 300 mV
dropout. The input voltage range is from 3 V to 5.5 V. The device is available in fixed and
adjustable output versions.
The regulator is equipped with internal protection circuitry, such as short-circuit current
limiting and thermal protection.
The regulator is designed to be stable with ceramic capacitors on the input and the output.
The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with
4.7 µF typical. The input capacitor has to be connected within 1 cm from VI terminal. The
output capacitor has also to be connected 1 cm far from output pin. There isn’t any upper
limit to the value of the input capacitor.
Figure 24, Figure 25, Figure 26 and Figure 27 illustrate the typical application schematics:
Figure 24. ST1L05 application schematic
VO
VI
VO
VI
ST1L05
VO_SENSE
CO
CI
GND
GND
GIPG3005141059LM
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30
Application information
ST1L05
Figure 25. ST1L05A application schematic
VO
VI
VO
VI
ST1L05A
CO
CI
GND
GND
GIPG3004141216LM
Figure 26. ST1L05B and ST1L05D application schematic
PG
VO
VO
VI
VI
ST1L05B
ST1L05D
OFF ON
EN
CO
R1
R2
CI
ADJ
GND
GND
GIPG3004141246LM
18/30
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ST1L05
Application information
Figure 27. ST1L05C application schematic
VO
VI
VO
VI
ST1L05C
VO_SENSE
OFF ON EN
CI
CO
GND
GND
Regarding to the adjustable version, the output voltage can be adjusted from 1.22 V up to
the input voltage, minus the voltage drop across PMOS (dropout voltage), by connecting a
resistor divider between ADJ pin and the output, thus allowing remote voltage sensing. The
resistor divider should be selected according to the following equation:
Equation 1
VO = VADJ (1 + R1 / R2) with VADJ = 1.22 V (typ.)
Resistors should be used with values in the range from 10 kΩ to 100 kΩ. Lower values can
also be suitable, but they increase current consumption.
6.1
Power dissipation
An internal thermal feedback loop disables the output voltage if the die temperature rises to
approximately 165 °C. This feature protects the device from excessive temperature and
allows the user to push the limits of the power handling capability of a given circuit board
without risk of damaging the device.
A good PC board layout should be used to maximize the power dissipation. Thermal path
goes from the die to the copper lead frame through the package leads and exposed pad to
the PC board copper. The PC board copper works as a heatsink. Footprint copper pads
should be as wider as possible to spread and dissipate the heat to the surrounding ambient.
Feed-through vias to inner or backside copper layers are also useful to improve the overall
thermal performance of the device.
Power dissipation of the device depends on the input voltage, output voltage and output
current, and is given by:
Equation 2
PD = (VI -VO) IO
DocID14492 Rev 3
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30
Application information
ST1L05
The junction temperature of the device is:
J_MAX = TA + RthJA x PD
where:
J_MAX is the maximum junction of the die, 125 °C
TA is the ambient temperature
thJA is the thermal resistance junction-to-ambient
T
T
R
6.2
6.3
Enable function (ST1L05B, ST1L05C and ST1L05D only)
The ST1L05 features the enable function. When EN voltage is higher than 2 V the device is
ON, and if it is lower than 0.8 V the device is OFF. In shutdown mode, consumption is lower
than 1 µA. EN pin has an internal pull-up, so it can be left floating if it is not used.
Power Good function (ST1L05B and ST1L05D only)
Most applications require a flag showing that the output voltage is in the correct range.
Power Good threshold depends on the adjust voltage. When the adjust is higher than
0.92*VADJ, Power Good (PG) pin goes to high impedance. If the adjust is below 0.92*VADJ
PG pin goes to low impedance. If the device works correctly, Power Good pin is at high
impedance.
If the output voltage is fixed using an external or internal resistor divider, Power Good
threshold is 0.92*VO.
To use Power Good function, an external pull-up resistor is required, and it has to be
connected between PG pin and VI or VO. PG pin typical current capability is up to 6 mA. A
pull-up resistor in the range of 100 kΩ to 1 MΩ is recommended. If Power Good function is
not used, PG pin has to remain floating.
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ST1L05
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 28. DFN6 (3x3 mm) drawings
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30
Package mechanical data
ST1L05
Table 10. DFN6 (3x3 mm) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
A1
A3
b
0.80
0
1
0.02
0.20
0.05
0.23
2.90
2.23
2.90
1.50
0.45
3.10
2.50
3.10
1.75
D
3
3
D2
E
E2
0.95
0.40
L
0.30
0.50
Figure 29. DFN6 (3x3 mm) recommended footprint
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ST1L05
Package mechanical data
Figure 30. DFN8 (4x4 mm) drawings
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30
Package mechanical data
ST1L05
Table 11.DFN8 (4x4 mm) mechanical data
mm
Dim.
Min.
0.80
0
Typ.
0.90
0.02
0,20
0.30
4
Max.
1
A
A1
A3
b
0.05
0.23
3.90
2.82
3.90
2.05
0.38
4.10
3.23
4.10
2.30
D
D2
E
3
4
E2
e
2.20
0.80
0.50
L
0.40
0.60
Figure 31. DFN8 (4x4 mm) recommended footprint
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Packaging mechanical data
8
Packaging mechanical data
Figure 32. DFN6 (3x3 mm) tape
ꢀꢁꢀꢂꢃꢀꢁB1
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30
Packaging mechanical data
ST1L05
Figure 33. DFN6 (3x3 mm) reel
ꢀꢁꢀꢂꢃꢀꢁB1
Table 12. DFN6 (3x3 mm) tape and reel mechanical data
mm
Dim.
Min.
Typ.
Max.
A0
B0
K0
3.20
3.20
1
3.30
3.30
1.10
3.40
3.40
1.20
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ST1L05
Packaging mechanical data
Figure 34. DFN8 (4x4 mm) carrier tape
7279936
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30
Packaging mechanical data
ST1L05
Figure 35. DFN8 (4x4 mm) reel
Table 13. DFN8 (4x4 mm) reel mechanical data
mm
Dim.
Min.
Typ.
Max.
A
C
D
N
T
330
12.8
20.2
60
13.0
13.2
22.4
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Revision history
9
Revision history
Table 14. Document revision history
Changes
Date
Revision
29-Feb-2008
07-Jul-2009
1
2
First release.
Added: package DFN8 (4 x 4 mm).
Part numbers: ST1L05A, ST1L05B, ST1L05C, ST1L05D have been
included in the ST1L05 for product rationalization.
Changed title of Figure 6, Figure 7, Figure 8, Figure 9, Figure 16 and
Figure 17.
05-May-2014
3
Updated package mechanical data.
Added Section 8.
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ST1L05
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