ST1S10PHR_技术文档

ST1S10

3 A, 900 kHz, monolithic synchronous

step-down regulator

Features

■ Step-down current mode PWM regulator

■ Output voltage adjustable from 0.8 V

■ Input voltage from 2.5 V up to 18 V

■ 2% DC output voltage tolerance

■ Synchronous rectification

■ Inhibit function

DFN8 (4x4mm)

PowerSO-8

■ Synchronizable switching frequency from 400

kHz up to 1.2 MHz

■ Internal soft start

■ Dynamic short circuit protection

■ Typical efficiency: 90%

■ 3 A output current capability

Description

The ST1S10 is a high efficiency step-down PWM

current mode switching regulator capable of

providing up to 3 A of output current. The device

operates with an input supply range from 2.5 V to

18 V and provides an adjustable output voltage

■ Stand-by supply current: max 6 µA over

temperature range

■ Operative junction temp: from -25°C to 125°C

from 0.8 V (V ) to 0.85*V

[V

=

FB

IN_SW OUT

Applications

V

*(1+R1/R2)]. It operates either at a 900 kHz

FB

fixed frequency or can be synchronized to an

external clock (from 400 kHz to 1.2 MHz). The

high switching frequency allows the use of tiny

SMD external components, while the integrated

synchronous rectifier eliminates the need for a

Schottky diode. The ST1S10 provides excellent

transient response, and is fully protected against

thermal overheating, switching over-current and

output short circuit.

■ Consumer

– STB, DVD, DVD recorders, TV, VCR, car

audio, LCD monitors

■ Networking

– XDSL, modems, DC-DC modules

■ Computer

– Optical storage, HD drivers, printers,

audio/graphic cards

The ST1S10 is the ideal choice for point-of-load

regulators or LDO pre-regulation.

■ Industrial and security

– Battery chargers, DC-DC converters, PLD,

PLA, FPGA, LED drivers

Table 1.

Device summary

Part number

Package

DFN8 (4x4 mm)

PowerSO-8

ST1S10

ST1S10PUR

ST1S10PHR

October 2007

Rev. 3

1/26

www.st.com

26

Contents

ST1S10

Contents

1

2

3

4

5

Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1

5.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.2.1

Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.3

5.4

5.5

5.6

5.7

5.8

Output capacitor (V_OUT> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output capacitor (0.8 V < V_OUT< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Inductor (V_OUT> 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Inductor (0.8 V < V_OUT< 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.8.1

5.8.2

5.8.3

5.8.4

5.8.5

Sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

OCP (over-current protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SCP (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 12

6

Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1

Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8

9

10

2/26

ST1S10

Application circuit

1

Application circuit

Figure 1. Typical application circuit

L1

3.3µH

12V

5V – 3A

VIN_SW

SW

FB

C1

EN

R1

4.7µF

ST1S10

VIN_A

C2

22µF

C3

R2

0.1µF

SYNC

AGND

PGND

3/26

Pin configuration

ST1S10

2

Pin configuration

Figure 2.

Pin connections (top view for PowerSO-8, bottom view for DFN8)

DFN8 (4x4)

PowerSO-8

Table 2.

Pin n°

Pin description

Symbol

Name and function

1

2

V_{IN_A}

Analog input supply voltage to be tied to V_INsupply source

Inhibit pin active low. Connect to V_{IN_A}if not used

INH (EN)

Feedback voltage for connection to external voltage divider to set the V_OUT

from 0.8V up to 0.85*V_{IN_SW}. (see output voltage selection paragraph 5.5)

3

4

V_FB

AGND

Analog ground

Synchronization and frequency select. Connect SYNC to GND for 900 kHz

operation, or to an external clock from 400 kHz to 1.2 MHz. (see Sync

operation paragraph 5.8.1)

5

SYNC

6

7

V_{IN_SW}

SW

Power input supply voltage to be tied to V_INpower supply source

Switching node to be connected to the inductor

Power ground

8

PGND

epad

Exposed pad to be connected to ground

4/26

ST1S10

3

Maximum ratings

Table 3.

Absolute maximum ratings

Symbol

V_{IN_SW}

Parameter

Value

Unit

Positive power supply voltage

Positive supply voltage

Inhibit voltage

-0.3 to 20

-0.3 to V_{IN_A}

-0.3 to 20

-0.3 to 2.5

-1 to +1

V

V_{IN_A}

V_INH

V_SW

V_FB

V

Output switch voltage

Feedback voltage

V

I_FB

FB current

mA

V

Sync

T_STG

T_OP

Synchronization

-0.3 to 6

Storage temperature range

Operating junction temperature range

-40 to 150

-25 to 125

°C

Note:

Absolute maximum ratings are the values beyond which damage to the device may occur.

Functional operation under these conditions is not implied.

Table 4.

Symbol

Thermal data

Parameter

PowerSO-8

DFN8

Unit

R_thJA

R_thJC

Thermal resistance junction-ambient

Thermal resistance junction-case

40

12

40

4

°C/W

5/26

Electrical characteristics

ST1S10

4

Electrical characteristics

Table 5.

Electrical characteristics

= V = V = V

V

= 12 V, V

= GND, V

= 5 V, I

= 10 mA, C = 4.7 µF

IN

IN_SW

IN_A

INH

SYNC

OUT

OUT IN

+0.1 µF, C

= 22 µF, L1 = 3.3 µH, T = -25 to 125°C (Unless otherwise specified, refer to

OUT

J

the typical application circuit. Typical values assume T = 25°C)

J

Symbol

Parameter

Test conditions

T_J= 25°C

T_J= -25°C to 125°C

Min.

Typ. Max.

Unit

784

776

800 816

800 824

600

mV

nA

V_FB

I_FB

I_Q

Feedback voltage

V_FBpin bias current

Quiescent current

V_INH> 1.2 V, not switching

1.5

2

2.5

6

mA

µA

V_INH< 0.4 V

V_IN= 2.5 V to 18 V

I_OUT

Output current ⁽¹⁾

3.0

1.2

A

V_OUT= 0.8 V to 13.6 V ⁽²⁾

Device ON

V

V_INH

I_INH

Inhibit threshold

Inhibit pin current

Device OFF

0.4

2

µA

%V_OUT

ΔV_IN

/

%V_OUT/ΔV_INReference line regulation

2.5 V < V_IN< 18 V

10 mA < I_OUT< 3 A

0.4

%V_OUT

ΔI_OUT

/

%V_OUT

/

Reference load regulation

0.5

0.9

ΔI_OUT

V_FB= 0.7 V, Sync = GND

T_J= 25°C

PWM fs

PWM switching frequency

0.7

85

1.1

MHz

D_MAX

Maximum duty cycle ⁽²⁾

90

0.10

0.12

5.0

85

%

Ω

R_DSon-N

NMOS switch on resistance

PMOS switch on resistance

Switch current limitation

I_SW= 750 mA

R_DSon-P

Ω

I_SWL

A

I

_OUT= 100 mA to 300 mA

_OUT= 300 mA to 3 A

%

°C

ν

Efficiency

90

T_SHDN

T_HYS

Thermal shut down

150

15

Thermal shut down hysteresis

100 mA < I_OUT< 1 A,

t_R= t_F≥ 500 ns

V_OUT/ΔI_OUTOutput transient response

5

%V_O

MHz

V_OUT/ΔI_OUTShort circuit removal response

@I_O=short (overshot)

10 mA < I_OUT< short

10

V_IN= 2.5 V to 18 V,

V_SYNC= 0 to 5 V

F_SYNC

SYNC frequency capture range

0.4

1.2

0.4

SYNC_WDSYNC pulse width

V_IN= 2.5 V to 18 V

250

ns

V

V_{IL_SYNC}SYNC input threshold low

V_{IH_SYNC}SYNC input threshold high

1.6

V

6/26

ST1S10

Table 5.

Electrical characteristics

Electrical characteristics (continued)

= V = V = V = 12 V, V

V

= GND, V

= 5 V, I

= 10 mA, C = 4.7 µF

IN

IN_SW

IN_A

INH

SYNC

OUT

OUT IN

+0.1 µF, C

= 22 µF, L1 = 3.3 µH, T = -25 to 125°C (Unless otherwise specified, refer to

OUT

J

the typical application circuit. Typical values assume T = 25°C)

J

Symbol

Parameter

Test conditions

Min.

Typ. Max.

Unit

V_IN= 2.5 V to 18 V,

V_SYNC= 0 or 5 V

I_{IL, IH}

I

SYNC input current

-10

+10

µA

V

_INrising

2.3

V

UVLO

Under voltage lock-out threshold

Hysteresis

200

mV

1. Guaranteed by design, but not tested in production.

2. See output voltage selection paragraph 5.5 for maximum duty cycle conditions.

7/26

Application information

ST1S10

5

Application information

5.1

Description

The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit

function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V, and the output

voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous

rectification removes the need for an external Schottky diode and allows higher efficiency

even at very low output voltages.

A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount

components, as well as a resistor divider to set the output voltage value. In typical

application conditions, only an inductor and 3 capacitors are required for proper operation.

The device can operate in PWM mode with a fixed frequency or synchronized to an external

frequency through the SYNC pin. The current mode PWM architecture and stable operation

with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external

compensation is needed.

To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light

load conditions and automatically switches to PWM mode when the output current

increases.

The ST1S10 is equipped with thermal shut down protection activated at 150°C (typ.).

Cycle-by-cycle short circuit protection provides protection against shorted outputs for the

application and the regulator. An internal soft start for start-up current limiting and power ON

delay of 275 µs (typ.) helps to reduce inrush current during start-up.

5.2

External components selection

5.2.1

Input capacitor

The ST1S10 features two V pins: V

switching peak current is drawn, and V

drivers.

for the power supply input voltage where the

to supply the ST1S10 internal circuitry and

IN

IN_SW

IN_A

The V

input capacitor reduces the current peaks drawn from the input power supply

IN_SW

and reduces switching noise in the IC. A high power supply source impedance requires

larger input capacitance.

For the V

input capacitor the RMS current rating is a critical parameter that must be

IN_SW

higher than the RMS input current. The maximum RMS input current can be calculated

using the following equation:

2

D²

η

⋅

η

2 D

⋅

+

=

I_RMSI_O

D -

where η is the expected system efficiency, D is the duty cycle and I is the output DC

O

current. The duty cycle can be derived using the equation:

D = (V

+ V ) / (V -V

)

OUT

F

IN SW

where V is the voltage drop across the internal NMOS, and V

represents the voltage

SW

F

drop across the internal PDMOS. The minimum duty cycle (at V

) and the maximum

IN_max

8/26

ST1S10

Application information

) should be considered in order to determine the max I flowing

duty cycle (at V

IN_min

RMS

through the input capacitor.

A minimum value of 4.7 µF for the V

and a 0.1 µF ceramic capacitor for the V

are

IN_A

IN_SW

suitable in most application conditions. A 10 µF or higher ceramic capacitor for the V

IN_SW

and a 1 µF or higher for the V

are recommended in cases of higher power supply source

IN_A

impedance or where long wires are needed between the power supply source and the V

pins. The above higher input capacitor values are also recommended in cases where an

IN

output capacitive load is present (47 µF < C

< 100 µF), which could impact the

LOAD

switching peak current drawn from the input capacitor during the start-up transient.

In cases of very high output capacitive loads (C > 100 µF), all input/output capacitor

LOAD

values shall be modified as described in the OCP and SCP operation section 5.8.5 of this

document.

The input ceramic capacitors should have a voltage rating in the range of 1.5 times the

maximum input voltage and be located as close as possible to V pins.

IN

5.3

Output capacitor (V_OUT> 2.5 V)

The most important parameters for the output capacitor are the capacitance, the ESR and

the voltage rating. The capacitance and the ESR affect the control loop stability, the output

ripple voltage and transient response of the regulator.

The ripple due to the capacitance can be calculated with the following formula:

V

= (0.125 x ΔI ) / (F x C

)

OUT

RIPPLE(C)

SW

S

where F is the PWM switching frequency and ΔI

is the inductor peak-to-peak switching

S

SW

current, which can be calculated as:

ΔI

= [(V - V

) / (F x L)] x D

SW

IN

OUT S

where D is the duty cycle.

The ripple due to the ESR is given by:

V

(ESR) = ΔI

x ESR

SW

RIPPLE

The equations above can be used to define the capacitor selection range, but final values

should be verified by testing an evaluation circuit.

Lower ESR ceramic capacitors are usually recommended to reduce the output ripple

voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower

output ripple voltage.

Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors

usually have very low ESL, making ripple voltages due to the ESL negligible. In order to

reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection

paths should be kept as short as possible.

The ST1S10 has been designed to perform best with ceramic capacitors. Under typical

application conditions a minimum ceramic capacitor value of 22 µF is recommended on the

output, but higher values are suitable considering that the control loop has been designed to

work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF

output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a

47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and

SCP operation section 5.8.5. of this document.

9/26

Application information

ST1S10

The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum

output voltage is recommended.

5.4

5.5

Output capacitor (0.8 V < V_OUT< 2.5 V)

For applications with lower output voltage levels (V < 2.5 V) the output capacitance and

out

inductor values should be selected in a way that improves the DC-DC control loop behavior.

In this output condition two cases must be considered: V > 8 V and V < 8 V.

IN

For V < 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as

IN

shown in Figure 4.

For V > 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to

IN

the 2 x 22 µF output capacitors as shown in Figure 5.

Output voltage selection

The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by

connecting a resistor divider (see R1 and R2 in the typical application circuit) between the

output and the V pin. A resistor divider with R2 in the range of 20 kΩ is a suitable

FB

compromise in terms of current consumption. Once the R2 value is selected, R1 can be

calculated using the following equation:

R1 = R2 x (V

- V ) / V

FB FB

OUT

where V = 0.8 V (typ.).

FB

Lower values are suitable as well, but will increase current consumption. Be aware that duty

cycle must be kept below 85% at all application conditions, so that:

D = (V

+ V ) / (V -V ) < 0.85

F IN SW

OUT

where V is the voltage drop across the internal NMOS, and V

represents the voltage

F

SW

drop across the internal PDMOS.

Note that once the output current is fixed, higher V

levels increase the power dissipation

OUT

of the device leading to an increase in the operating junction temperature. It is

recommended to select a V level which maintains the junction temperature below the

OUT

thermal shut-down protection threshold (150°C typ.) at the rated output current. The

following equation can be used to calculate the junction temperature (T ):

J

T = {[V

x I

x R

x (1-η)] / η} +T

thJA AMB

J

OUT

where R

is the junction-to-ambient thermal resistance, η is the efficiency at the rated

thJA

I

current and T

is the ambient temperature.

OUT

AMB

To ensure safe operating conditions the application should be designed to keep T < 140°C.

J

5.6

Inductor (V_OUT> 2.5 V)

The inductor value fixes the ripple current flowing through output capacitor and switching

peak current. The ripple current should be kept in the range of 20-40% of I

(for

OUT_MAX

example it is 0.6 - 1.2 A at I

the following formula:

= 3 A). The approximate inductor value can be obtained with

OUT

L = [(V - V

) / ΔI ] x T

SW ON

IN

OUT

10/26

ST1S10

Application information

where T is the ON time of the internal switch, given by:

ON

T

= D/F

S

ON

The inductor should be selected with saturation current (I ) equal to or higher than the

SAT

inductor peak current, which can be calculated with the following equation:

I

= I + (ΔI /2), I

≥ I

SAT PK

PK

O

SW

The inductor peak current must be designed so that it does not exceed the switching current

limit.

5.7

Inductor (0.8 V < V_OUT< 2.5 V)

For applications with lower output voltage levels (V < 2.5 V) the description in the previous

out

section is still valid but it is recommended to keep the inductor values in a range from 1µH to

2.2 µH in order to improve the DC-DC control loop behavior, and increase the output

capacitance depending on the V level as shown in the Figure 4 and Figure 5. In most

IN

application conditions a 2.2 µH inductor is the best compromise between DC-DC control

loop behavior and output voltage ripple.

5.8

Function operation

5.8.1

Sync operation

The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency

with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is

connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2

MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,

this pin must be connected to ground with a path as short as possible to avoid any possible

noise injected in the SYNC internal circuitry.

5.8.2

5.8.3

Inhibit function

The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically

reducing the current consumption down to less than 6 µA. When the inhibit feature is not

used, this pin must be tied to V to keep the regulator output ON at all times. To ensure

proper operation, the signal source used to drive the inhibit pin must be able to swing above

and below the specified thresholds listed in the electrical characteristics section under V

Any slew rate can be used to drive the inhibit pin.

IN

.

INH

OCP (over-current protection)

The ST1S10 DC-DC converter is equipped with a switch over-current protection. In order to

provide protection for the application and the internal power switches and bonding wires, the

device goes into a shutdown state if the switch current limit is reached and is kept in this

condition for the T

period (T

= 135 µs typ.) and turns on again for the T period

OFF

OFF(OCP) ON

(T

= 22 µs typ.) under typical application conditions. This operation is repeated cycle

ON(OCP)

by cycle. Normal operation is resumed when no over-current is detected.

11/26

Application information

ST1S10

5.8.4

SCP (short circuit protection)

In order to protect the entire application and reduce the total power dissipation during an

overload or an output short circuit condition, the device is equipped with dynamic short

circuit protection which works by internally monitoring the V (feedback voltage).

FB

In the event of an overload or output short circuit, if the V

voltage is reduced causing the

OUT

feedback voltage (V ) to drop below 0.3 V (typ.), the device goes into shutdown for the

FB

T

time (T

= 288 µs typ.) and turns on again for the T period (T

= 130

OFF

OFF(SCP)

ON

ON(SCP)

µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when

no overload is detected (V > 0.3 V typ.) for the full T period.

FB

ON

This dynamic operation can greatly reduce the power dissipation in overload conditions,

while still ensuring excellent power-on startup in most conditions.

5.8.5

SCP and OCP operation with high capacitive load

Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from

short circuit and overload.

However, a highly capacitive load on the output may cause difficulties during start-up. This

can be resolved by using the modified application circuit shown in Figure 3, in which a

minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for

C

> 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage

LOAD

divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.

Note that C4 may impact the control loop response and should be added only when a

capacitive load higher than 100 µF is continuously present. If the high capacitive load is

variable or not present at all times, in addition to C4 an increase in the output ceramic

capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also

in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for

C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.

Figure 3.

Application schematic for heavy capacitive load

L1

3.3µH

C4 (*)

12V

5V – 3A

4.7nF

VIN_SW

SW

FB

C1

EN

R1

R2

10µF

ST1S10

LOAD

VIN_A

C2(*)

22µF

C_LOAD

C3

4.7µF

Output Load

SYNC

AGND PGND

(*) see OCP and SCP descriptions for C2 and C4 selection

12/26

ST1S10

Application information

Figure 4.

Application schematic for low output voltage (V

< 2.5 V) and 2.5 V < V < 8 V

OUT IN

L1

2.2µH

VIN<8V

0.8V<VOUT<2.5V

VIN_SW

SW

C1

EN

R1

10µF

ST1S10

VIN_A

C2

2x22µF

FB

C3

0.1µF

R2

SYNC

AGND PGND

Figure 5.

Application schematic for low output voltage (V

< 2.5 V) and 8 V < V < 16 V

OUT IN

L1

2.2µH

8V<VIN<16V

0.8V<VOUT<2.5V

+

VIN_SW

SW

C1

EN

R1

R2

10µF

ST1S10

VIN_A

C5

C2

100µF

2x22µF

FB

Electrolytic

ESR<0.1Ohm

C3

4.7µF

SYNC

AGND PGND

13/26

Layout considerations

ST1S10

6

Layout considerations

Layout is an important step in design for all switching power supplies.

High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB

layout. Care must be taken in board layout to get device performance, otherwise the

regulator could show poor line and load regulation, stability issues as well as EMI problems.

It is critical to provide a low inductance, impedance ground path. Therefore, use wide and

short traces for the main current paths.

The input capacitor must be placed as close as possible to the IC pins as well as the

inductor and output capacitor. Use a common ground node for power ground and a different

one for control ground (AGND) to minimize the effects of ground noise. Connect these

ground nodes together underneath the device and make sure that small signal components

returning to the AGND pin and do not share the high current path of C and C

.

IN

OUT

The feedback voltage sense line (V ) should be connected right to the output capacitor and

FB

routed away from noisy components and traces (e.g., SW line). Its trace should be

minimized and shielded by a guard-ring connected to the ground.

Figure 6.

PCB layout suggestion

CN1=Input power supply

CN2=Enable/Disable

V_FBguard-ring

CN3=Input sync.

CN4=V_OUT

Input capacitor C1 must be placed

as close as possible to the IC

pins as well as the inductor L1

and output capacitor C2

Vias from thermal pad

to bottom layer

47mm

14/26

ST1S10

Layout considerations

Figure 7.

PCB layout suggestion

Common ground node

for power ground

Power Ground

I_IN

6.1

Thermal considerations

The leadframe die pad, of ST1S10, is exposed at the bottom of the package and must be

soldered directly to a properly designed thermal pad on the PCB, the addition of thermal

vias from the thermal pad to an internal ground plane will help increase power dissipation.

15/26

Diagram

7

ST1S10

Diagram

Figure 8.

Block diagram

16/26

ST1S10

Typical performance characteristics

8

Typical performance characteristics

Unless otherwise specified, refer to the typical application circuit under the following

conditions: T = 25°C, V = V

= V

= 12 V, V

= GND, V = 5 V,

J

IN

IN-SW

IN-A

OUT

INH

SYNC

OUT

I

= 10 mA, C = 4.7 µF + 0.1 µF, C

= 22 µF, L1 = 3.3 µH

OUT

IN

Figure 9.

Voltage feedback vs. temperature

Figure 10. Oscillator frequency vs.

temperature

830

820

810

800

790

780

770

1.2

1.1

1

0.9

0.8

V_IN=V_INH=12V, V_OUT=0.8V, I_OUT=10mA

0.7

V_IN-A=V_IN-SW=V_INH=12V, V_FB=0V

0.6

-50

760

-50

-25

0

25

50

75

100

125

-25

0

25

50

75

100

125

TEMPERATURE [°C]

Figure 11. Max duty cycle vs. temperature

Figure 12. Inhibit threshold vs. temperature

1.4

1.2

1

92

90

88

86

0.8

0.6

84

0.4

V_IN-A=V_IN-SW=V_INH=12V, V_FB=0V

V_IN-A=V_IN-SW=2.5V, V_OUT=0.8V, I_OUT=10mA

82

80

0.2

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100 125

TEMPERATURE [°C]

Figure 13. Reference line regulation vs.

temperature

Figure 14. Reference load regulation vs.

temperature

0.2

0.1

0

1.3

V_IN-A=V_IN-SW=V_INH=12V, I_OUTfrom 10mA to 3A

1

0.7

0.4

0.1

-0.2

-0.5

-0.1

V_IN-A=V_IN-SW=V_INHfrom 2.5 to 20V, V_OUT=0.8V, I_OUT=10mA

-0.2

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE [°C]

17/26

Typical performance characteristics

ST1S10

Figure 15. ON mode quiescent current vs.

temperature

Figure 16. Shutdown mode quiescent current

vs. temperature

7

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

6

V_IN-A=V_IN-SW=12V, V_INH=GND, V_OUT=0.8V

5

4

3

2

1

0

V_IN-A=V_IN-SW=12V, V_INH=1.2V, V_OUT=0.8V

0.2

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

3

TEMPERATURE [°C]

Figure 17. PMOS ON resistance vs.

temperature

Figure 18. NMOS ON resistance vs.

temperature

320

270

220

170

120

110

100

90

80

70

60

V_IN=12V, I_SW=750mA

50

-50

20

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

125

TEMPERATURE [°C]

Figure 19. Efficiency vs. temperature

Figure 20. Efficiency vs. output current

100

90

100

90

80

70

60

V_IN-A=V_IN-SW=V_INH=12V, V_OUT=5V, I_OUT=3A

V_IN-A=V_IN-SW=V_INH=12V, V_OUT=5V, T_J=25°C

50

-50

50

-25

0

25

50

75

100

125

0

0.5

1

1.5

2

2.5

TEMPERATURE [°C]

OUTPUT CURRENT [A]

18/26

ST1S10

Typical performance characteristics

Figure 21. Efficiency vs. output current

Figure 22. Efficiency vs. output current

100

90

100

90

80

70

60

V_IN-A=V_IN-SW=V_INH=5V, V_OUT=3.3V, T_J=25°C

V_IN-A=V_IN-SW=V_INH=16V, V_OUT=12V, T_J=25°C

50

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

2.5

3

OUTPUT CURRENT [A]

19/26

Package mechanical data

ST1S10

9

Package mechanical data

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

20/26

ST1S10

Package mechanical data

PowerSO-8 mechanical data

mm.

inch.

Dim.

Min.

Typ.

Max.

Min.

Typ.

Max.

A

A1

A2

b

1.70

0.067

0.00

1.25

0.31

0.17

4.80

2.24

5.80

3.80

1.55

0.15

0.00

0.006

0.142

0.020

0.010

0.197

0.126

0.244

0.157

0.099

0.049

0.012

0.007

0.189

0.088

0.228

0.150

0.061

0.51

0.25

5.00

3.20

6.20

4.00

2.51

c

D

4.90

3.10

6.00

3.90

2.41

1.27

0193

0.122

0.236

0.154

0.095

0.050

D1

E

E1

E2

e

h

0.25

0.40

0°

0.50

1.27

8°

0.010

0.016

0°

0.020

0.050

8°

L

k

ccc

0.10

0.004

7195016C

21/26

Package mechanical data

ST1S10

DFN8 (4x4) mechanical data

mm.

inch.

Typ.

Dim.

Min.

Typ.

0.90

0.02

0.20

0.30

4.00

3.00

4.00

2.20

0.80

0.50

Max.

1.00

0.05

Min.

0.031

0

Max.

A

A1

A3

b

0.80

0.035

0.039

0

0.001

0.008

0.012

0.157

0.118

0.157

0.087

0.031

0.020

0.002

0.23

3.90

2.82

3.90

2.05

0.38

4.10

3.23

4.10

2.30

0.009

0.154

0.111

0.154

0.081

0.015

0.161

0.127

0.161

0.091

D

D2

E

E2

e

L

0.40

0.60

0.016

0.024

7869653B

22/26

ST1S10

Package mechanical data

Tape & reel SO-8 mechanical data

mm.

inch.

Typ.

Dim.

Min.

Typ.

Max.

330

Min.

Max.

12.992

0.519

A

C

12.8

20.2

60

13.2

0.504

0.795

2.362

D

N

T

22.4

8.5

5.9

2.3

4.1

8.1

0.882

0.335

0.232

0.090

0.161

0.319

Ao

Bo

Ko

Po

P

8.1

5.5

2.1

3.9

7.9

0.319

0.216

0.082

0.153

0.311

23/26

Package mechanical data

ST1S10

Tape & reel QFNxx/DFNxx (4x4) mechanical data

mm.

Typ.

inch.

Typ.

Dim.

Min.

Max.

330

Min.

Max.

A

C

12.992

0.519

12.8

20.2

99

13.2

0.504

0.795

3.898

D

N

101

3.976

T

14.4

0.567

Ao

Bo

Ko

Po

P

4.35

1.1

4

0.171

0.043

0.157

0.315

8

24/26

ST1S10

10

Revision history

Table 6.

Document revision history

Revision

Date

Changes

28-Aug-2007

24-Sep-2007

25-Oct-2007

1

2

3

Initial release.

Add R_thJCon Table 4.

Added new paragraph 6: Layout considerations.

25/26

ST1S10

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26/26


型号：	ST1S10PHR
厂家：	ST
描述：	3 A, 900 kHz, monolithic synchronous step-down regulator 3 A， 900千赫，单片同步降压型稳压器稳压器
文件：	总26页 (文件大小：788K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST1S10PHR [STMICROELECTRONICS]

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