ST2S06D33 [STMICROELECTRONICS]
Dual synchronous rectification with reset or inhibit, 0.5 A, 1.5 MHz adjustable step-down switching regulator; 双通道同步整流带复位或抑制， 0.5 A ， 1.5 MHz的可调降压型开关稳压器
| 型号： | ST2S06D33 |
| 厂家： | 
ST |
| 描述： | Dual synchronous rectification with reset or inhibit, 0.5 A, 1.5 MHz adjustable step-down switching regulator |
| 文件： | 总21页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST2S06A33
ST2S06B - ST2S06D33
Dual synchronous rectification with reset or inhibit, 0.5 A, 1.5 MHz
adjustable step-down switching regulator
Features
■ Step-down current mode PWM (1.5 MHz)
DC-DC converter
■ Fixed or adjustable output voltage from 0.8 V
■ 2% DC output voltage tolerance
■ Synchronous rectification
■ Reset function for A and D versions
QFN12L (4x4 mm)
■ Inhibit function for B version
■ Internal soft start for start-up current limitation
and power ON delay of 50-100 µs
the power dissipation may cause a high heating of
the application environment. It provides up to 0.5
A over an input voltage range of 2.5 V to 5.5 V.
■ Typical efficiency: > 90%
■ 0.5 A output current capability
■ Non-switching quiescent current: max 1 mA
A high switching frequency of 1.5 MHz allows the
use of tiny surface-mount components as well as
a resistor divider to set the output voltage value.
Only an inductor and two capacitors are required.
A low output ripple is guaranteed by the current
mode PWM topology and the utilization of low
ESR SMD ceramic capacitors. The device is
thermally protected and current limited to prevent
damage due to accidental short circuit. The
ST2S06 series is available in the QFN12L (4x4
mm) package.
over temperature range
■ R
150 mΩ (typ.)
DS(ON)
■ Uses tiny capacitors and inductors
■ Available in QFN12L (4x4 mm)
Description
The ST2S06 is a dual step-down DC-DC
converter optimized for powering low-voltage
digital cores in ODD applications and, generally,
to replace the high current linear solution when
Table 1.
Device summary
Order code
Package
Packaging
ST2S06APQR(1)
ST2S06A33PQR
ST2S06D33PQR
ST2S06BPQR
QFN12L (4x4 mm)
QFN12L (4x4 mm)
QFN12L (4x4 mm)
QFN12L (4x4 mm)
Tape and reel
Tape and reel
Tape and reel
Tape and reel
1. Available on request.
March 2008
Rev 3
1/21
www.st.com
21
Contents
ST2S06A33 - ST2S06B - ST2S06D33
Contents
1
2
3
4
5
6
7
8
9
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
ST2S06A33 - ST2S06B - ST2S06D33
Diagram
1
Diagram
Figure 1. Schematic diagram
RESET_OUT *
VI_SW
VI_A
Delay
Ref
SW
HV
Trimming
FB1
VI_SW
SW2
FB2
CONTROL
LOGIC
Ref
Soft Start
GND
INH**
GND
* ST2S06A/D
** ST2S06B
3/21
Pin configuration
ST2S06A33 - ST2S06B - ST2S06D33
2
Pin configuration
Figure 2.
Pin connections (top view)
Table 2.
Pin n°
Pin description
ST2S06A/D
ST2S06B
Name and function
1
2
HV
FB2
HV
FB2
Programing pin. It must be floating or connected to GND.
Feedback voltage
3
GND2
SW2
GND2
SW2
Power ground
4
Switching pin
5
VIN_SW
SW1
VIN_SW
SW1
Power input voltage pin
Switching pin
6
7
GND1
FB1/OUT1
Reset_out
NC
GND1
FB1
Power ground
8
Feedback voltage / output voltage
Reset out pin
9
NC
10
11
12
INH
Inhibit pin
VIN_A
GND_A
VIN_A
GND_A
Supply for analog circuit
System ground
4/21
ST2S06A33 - ST2S06B - ST2S06D33
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
VIN_SW
Parameter
Value
Unit
Positive power supply voltage
Positive power supply voltage
Inhibit voltage
-0.3 to 7
-0.3 to 7
-0.3 to 7
-0.3 to 7
V
V
V
V
VIN_A
VINH
SWITCH voltage Max. voltage of output pin
VFB1,2/VO1
VO1
Feedback voltage/output voltage
Output voltage (for VO > 1.6 V)
-0.3 to 2.5
-0.3 to 5
V
V
Current into VFB
pin
Common mode input voltage
+1 to -1
mA
TJ
Max junction temperature
150
-65 to +150
300
°C
°C
°C
TSTG
TLEAD
Storage temperature range
Lead temperature (soldering) 10 sec.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Thermal data
Symbol
Parameter
Thermal resistance junction-case
Value
Unit
RthJC
RthJA
10
60
°C/W
°C/W
Thermal resistance junction-ambient
Table 5.
ESD performance
Parameter
Symbol
Test conditions
HBM-DH11C
Value
Unit
kV
ESD
ESD protection voltage
4
5/21
Electrical characteristics
ST2S06A33 - ST2S06B - ST2S06D33
4
Electrical characteristics
Table 6.
Electrical characteristics for ST2S06A (V
= V
= 5 V, V
= 1.2 V, C = 4.7 µF,
IN_SW
IN_A
O1,2 1
C = C = 22 µF, L1 = L2 = 3.3 µH, T = -30 to 125 °C unless otherwise specified. Typical
2
3
J
values are referred to 25 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
FB1,2
IFB1,2
IQ
Feedback voltage
784
800
816
600
1.2
mV
nA
mA
A
VFB pin bias current
Quiescent current
Output current
VFB = 1 V
VFB = 1 V
IO1,2
IMIN
VIN = 2.5 to 5.5 V (1)
0.8
Minimum output current
1
mA
%VO1,2
ΔVIN
/
%VO/
VIN
Reference line regulation
2.5 V < VIN < 5.5 V
0.032
ΔVO1,2
Reference load regulation
PWM switching frequency
Maximum duty cycle
10 mA < IO < 0.5 A
5.5
1.5
94
15
mV
MHz
%
PWM fS
DMAX
ISWL
VFB = 0.7 V, TA = 25°C
VFB = 0.7 V, TA = 25°C
1.2
85
1
1.8
Switching current limitation
NMOS leakage current
PMOS leakage current
1.2
0.1
0.1
0.15
0.2
75
A
ILKN
VFB = 0.9 V, TA = 25°C
VFB = 0.9 V, TA = 25°C
µA
µA
Ω
ILKP
RDSon-N NMOS switch on resistance ISW = 250 mA
RDSon-P PMOS switch on resistance ISW = 250 mA
0.3
0.4
Ω
I
O = 20 mA to 100 mA
%
η
Efficiency
IO = 100 mA to 0.5 A
90
%
TSHDN
THYS
Thermal shut down (2)
130
-5
150
°C
Thermal shut down
hysteresis (2)
15
°C
100 mA < IO < 500 mA,
tR = tF => 100 ns, TA = 25°C
ΔVO1,2/ΔIO Load transient response (2)
+5
%VO
Reset section
tDEL
Delay time
TA = 25°C
80
4.5
85
4.6
4.2
ms
V
VIN_A Rising
VIN_A Falling
4.75
4.28
Reset in threshold
measured on input pin
VRES
4.12
1. VO = 90% of nominal value.
2. Guaranteed by design, but not tested in production.
6/21
ST2S06A33 - ST2S06B - ST2S06D33
Electrical characteristics
= 5 V, V = 3.3 V, V = 1.2 V,
Table 7.
Electrical characteristics for ST2S06A33 (V
= V
IN_SW IN_A
01
O2
C = 4.7 µF, C = C = 22 µF, L1 = L2 = 3.3 µH, T = -30 to 125 °C unless otherwise
1
2
3
J
specified. Typical values are referred to 25 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
OUT1
FB2
IO1
Output feedback pin
Feedback voltage
IO1 pin bias current
VFB pin bias current
Quiescent current
Output current
3.23
784
3.3
800
15
3.37
816
20
V
mV
µA
nA
mA
A
VO = 3.5 V
VFB = 1 V
VFB = 1 V
IFB2
IQ
IO1,2
IMIN
600
1.2
VIN = 4 to 5.5 V (1)
0.8
Minimum output current
1
mA
%VO1,2/ΔVI
%VO/
VIN
Reference line regulation
Reference load regulation
4V < VIN < 5.5 V
0.032
5.5
N
ΔVO1,2
10mA < IO < 0.5 A
VFB = 0.7 V, TA = 25°C
VFB = 0.7 V, TA = 25°C
15
mV
PWM switching
frequency(1)
PWM fS
1.2
1.5
1.8
MHz
DMAX
ISWL
ILKN
Maximum duty cycle
85
1
94
1.2
0.1
0.1
0.15
0.2
75
%
A
Switching current limitation
NMOS leakage current
PMOS leakage current
VFB = 0.9 V, TA = 25°C
VFB = 0.9 V, TA = 25°C
µA
µA
Ω
ILKP
RDSon-N NMOS switch on resistance ISW = 250 mA
DSon-P PMOS switch on resistance ISW = 250 mA
0.3
0.4
R
Ω
I
O = 20 mA to 100 mA
%
%
°C
η
Efficiency
IO = 100 mA to 0.5 A
90
TSHDN
THYS
Thermal shut down (2)
130
-5
150
Thermal shut down
hysteresis (2)
15
°C
100 mA < IO < 500 mA
tR = tF => 100 ns, TA = 25°C
ΔVO1,2/ΔIO Load transient response (2)
+5
%VO
Reset section
tDEL
Delay time
TA = 25°C
80
4.5
85
4.6
4.2
ms
V
VIN_A Rising
VIN_A Falling
4.75
4.28
Reset in threshold
measured on input pin
VRES
4.12
1. VO= 90% of nominal value.
2. Guaranteed by design, but not tested in production.
7/21
Electrical characteristics
ST2S06A33 - ST2S06B - ST2S06D33
Table 8.
Electrical characteristics for ST2S06D33 (V
= V
= 5 V, V = 3.3 V, V = 1.2 V,
IN_A 01 O2
IN_SW
C = 4.7 µF, C = C = 22 µF, L1 = L2 = 3.3 µH, T = -30 to 125 °C unless otherwise
1
2
3
J
specified. Typical values are referred to 25 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
OUT1
FB2
IO1
Output feedback pin
Feedback voltage
IO1 pin bias current
VFB pin bias current
Quiescent current
Output current
3.23
784
3.3
800
15
3.37
816
20
V
mV
µA
nA
mA
A
VO = 3.5 V
VFB = 1 V
VFB = 1 V
IFB2
IQ
IO1,2
IMIN
600
1.2
VIN = 4 to 5.5 V (1)
0.8
Minimum output current
1
mA
%VO1,2/ΔVI
%VO/
VIN
Reference line regulation
Reference load regulation
4V < VIN < 5.5 V
0.032
5.5
N
ΔVO1,2
10mA < IO < 0.5 A
VFB = 0.7 V, TA = 25°C
VFB = 0.7 V, TA = 25°C
15
mV
PWM switching
frequency(1)
PWM fS
1.2
1.5
1.8
MHz
DMAX
ISWL
ILKN
Maximum duty cycle
85
1
94
1.2
0.1
0.1
0.15
0.2
75
%
A
Switching current limitation
NMOS leakage current
PMOS leakage current
VFB = 0.9 V, TA = 25°C
VFB = 0.9 V, TA = 25°C
µA
µA
Ω
ILKP
RDSon-N NMOS switch on resistance ISW = 250 mA
RDSon-P PMOS switch on resistance ISW = 250 mA
0.3
0.4
Ω
I
O = 20 mA to 100 mA
%
%
°C
η
Efficiency
IO = 100 mA to 0.5 A
90
TSHDN
THYS
Thermal shut down (2)
130
-5
150
Thermal shut down
hysteresis (2)
15
°C
100 mA < IO < 500 mA
tR = tF => 100 ns, TA = 25°C
ΔVO1,2/ΔIO Load transient response (2)
+5
%VO
Reset section
tDEL
Delay time
TA = 25°C
52
65
78
ms
V
VIN_A Rising
VIN_A Falling
4.55
3.775
Reset in threshold
measured on input pin
VRES
3.625
3.7
1. VO= 90% of nominal value.
2. Guaranteed by design, but not tested in production.
8/21
ST2S06A33 - ST2S06B - ST2S06D33
Electrical characteristics
= 5 V, V =1.2 V, C = 4.7 µF,
Table 9.
Electrical characteristics for ST2S06B (V
= V
IN_SW IN_A
O1,2
1
C = C = 22 µF, L1 = L2 = 3.3 µH, T = -30 to 125 °C unless otherwise specified. Typical
2
3
J
values are referred to 25 °C
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
FB1,2
IFB1,2
Feedback voltage
784
800
816
600
1
mV
nA
mA
µA
A
VFB pin bias current
VFB = 1 V
VINH > 1.2 V, VFB = 1 V
IQ
Quiescent current
VINH < 0.4 V
1
IO1,2
IMIN
Output current
VIN = 2.5 to 5.5 V (1)
0.8
Minimum output current
1
mA
2.5V < VIN < 5 V
2.5V < VIN < 5.5 V
Device OFF
1.2
1.3
VINH
Inhibit threshold
V
0.4
2
IINH1,2
Inhibit pin current
µA
%VO1,2
ΔVIN
/
%VO/
VIN
Reference line regulation
Reference load regulation
2.5V < VIN < 5.5 V
0.032
5.5
ΔVO1,2
10 mA < IO < 0.5 A
VFB = 0.7 V, TA = 25°C
VFB = 0.7 V, TA = 25°C
15
mV
PWM switching
frequency(1)
PWM fS
1.2
1.5
1.8
MHz
DMAX
ISWL
ILKN
Maximum duty cycle
85
1
94
1.2
0.1
0.1
0.15
0.2
75
%
A
Switching current limitation
NMOS leakage current
PMOS leakage current
VFB = 0.9 V, TA = 25°C
VFB = 0.9 V, TA = 25°C
µA
µA
Ω
ILKP
RDSon-N NMOS switch on resistance ISW = 250 mA
DSon-P PMOS switch on resistance ISW = 250 mA
0.3
0.4
R
Ω
I
O = 20 mA to 100 mA
%
%
°C
η
Efficiency
IO = 100 mA to 0.5 A
90
TSHDN
THYS
Thermal shut down (2)
130
-5
150
Thermal shut down
hysteresis (1)
15
°C
100 mA < IO < 500 mA,
tR = tF1 => 100 ns, TA = 25°C
ΔVO1,2/ΔIO Load transient response (1)
+5
%VO
1. VO= 90% of nominal value.
2. Guaranteed by design, but not tested in production.
9/21
Typical performance characteristics
ST2S06A33 - ST2S06B - ST2S06D33
5
Typical performance characteristics
Figure 3.
Feedback voltage 1 vs. temperature Figure 4.
(ST2S06B)
Feedback voltage 2 vs. temperature
(ST2S06B)
0.82
0.81
0.8
0.82
VI=5V, VFB1 connected to VO1
IO1=IO2=NO LOAD
VI=5V, VFB2 connected to VO2
IO1=IO2 =NO LOAD
0.81
0.8
0.79
0.79
0.78
0.78
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE [°C]
TEMPERATURE [°C]
Figure 5.
Efficiency vs. output current 1
Figure 6.
Efficiency vs. output current 2
100
95
90
85
80
75
70
65
60
0
100
95
90
85
80
75
70
65
60
55
50
45
40
VI=5V, VO2=1.2V, IO1 NO LOAD
VI=5V, VO1=3.3V, IO2 NO LOAD
0.1
0.2
0.3
0.4
0.5
0.6
0
0.1
0.2
0.3
0.4
0.5
0.6
Output Current 1 [A]
Output Current 2 [A]
Figure 7.
Switching frequency vs.
temperature (ST2S06A)
Figure 8.
Duty cycle vs. temperature
(ST2S06A)
1.9
100
99
98
97
96
95
94
93
92
91
90
VI=5V, VFB1=3.2V, VFB2=0.7V
VI=5V, VFB1=3.2V, VFB2=0.7V
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
10/21
ST2S06A33 - ST2S06B - ST2S06D33
Typical performance characteristics
Figure 9.
Switching frequency vs.
temperature (ST2S06B)
Figure 10. Inhibit threshold vs. temperature
(ST2S06B)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
-50
1.4
VI=5V, IO1= IO2=100mA
1.2
ON
1
0.8
OFF
0.6
0.4
0.2
0
-50
-25
0
25
50
T [C°]
75
100
125
-25
0
25
50
75
100
125
Temperature [°C]
Figure 11. Switching current limitation vs.
input voltage (ST2S06A)
Figure 12. PMOS switch on resistance vs.
temperature
2
240
VCC=5V, ISW=250mA
VI from 2.5V to 5.5V, Output2 Maximum load Current
220
200
180
160
140
120
100
1.8
1.6
1.4
1.2
1
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
T [°C]
75
100
125
VI [V]
Figure 13. NMOS switch on resistance vs.
temperature
Figure 14. Delay time vs. temperature
(ST2S06A)
170
150
130
VI
110
VCC=5V, ISW=250mA
90
70
50
VRES
-50
-25
0
25
50
T [°C]
75
100
125
VI Rising from 0V to 5V, Delay from VRES threshold and
reset pin below 0V.
11/21
Typical performance characteristics
ST2S06A33 - ST2S06B - ST2S06D33
Figure 15. Delay time vs. temperature
(ST2S06A)
Figure 16. Reset in threshold vs. temperature
(ST2S06A)
100
95
90
85
80
75
70
65
5
4.9
4.8
Rising
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
60
55
50
Falling
VI Rising from 0V to 5V
-50
-25
0
25
50
T [C°]
75
100
125
-50
-25
0
25
50
T [C°]
75
100 125
Figure 17. Reset in threshold vs. temperature Figure 18. Delay time vs. temperature
(ST2S06D) (ST2S06D)
75
70
65
60
55
50
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
Rising
VIN Rising from 0V to 5V
Falling
-50
-25
0
25
50
T [°C]
75
100
125
-50
-25
0
25
50
T [°C]
75
100
125
Figure 19. Load transient response (ST2S06A) Figure 20. Start-up transient (ST2S06A)
VI
VO1
VO1
IO1
VI= from 0V to 5V, IO1=500mA, Output Voltage=3.3V
VI= 5V, IO1 from 100mA to 500mA
12/21
ST2S06A33 - ST2S06B - ST2S06D33
Typical performance characteristics
Figure 21. Start-up transient (ST2S06B)
Figure 22. Inhibit transient (ST2S06B)
VINH
IO1
VI
VO1
VO1
VO2
VINH= from 0V to 2V, VI=5V, IO1=IO2=1A
VI= from 0V to 5V, IO1 =1A, Output Voltage=1.2V
13/21
Typical application
ST2S06A33 - ST2S06B - ST2S06D33
6
Typical application
Figure 23. Application circuit for ST2S06A/D
VIN
L2
3.3µH
SW2
VFB2
VIN_A
R3
VO2
VIN_SW
L1
3.3µH
ST2S06A/D
SW1
NC
R1
VO1
VFB1
Reset_Out
GND1 GND2 HV GND_A
C1
4.7µF
C2
22µF
R2
C3
R4
22µF
Figure 24. Application circuit for ST2S06B
VIN
L2
3.3µH
SW2
VIN_A
R3
VO2
VFB2
VIN_SW
L1
3.3µH
ST2S06B
SW1
INH
R1
VO1
VFB1
NC
GND1 GND2 HV
GND_A
C1
4.7µF
C2
22µF
R2
C3
R4
22µF
14/21
ST2S06A33 - ST2S06B - ST2S06D33
Application information
7
Application information
The ST2S06 represents a series of dual adjustable current mode PWM step-down DC-DC
converters with an internal 0.5 A power switch, packaged in a QFN12L (4x4 mm).
It is a complete 0.5 A switching regulator with internal compensation that eliminates the
need for additional components.
The constant frequency, current mode, PWM architecture and stable operation with ceramic
capacitors results in low, predictable output ripple.
To clamp the error amplifier reference voltage a Soft Start control block generating a voltage
ramp has been implemented. Other circuits fitted to the device protection are the Thermal
Shut-down block, which turns off the regulator when the junction temperature exceeds 150
°C (typ.), and the cycle-by-cycle current limiting that provides protection against shorted
outputs.
Because the ST2S06 is an adjustable regulator, the output voltage is determined by an
external resistor divider. The desired value is given by the following equation:
V = V [1+R1/R2]
O
FB
Operation of the device requires few components: 2 inductors, 3 capacitors and a resistor
divider. The chosen inductor must be capable of not saturating at the peak current level. Its
value should be selected keeping in mind that a large inductor value increases the efficiency
at low output current and reduces output voltage ripple, while a smaller inductor can be
chosen when it is important to reduce package size and total application cost. Finally, the
ST2S06 has been designed to work properly with X5R or X7R SMD ceramic capacitors both
at the input and at the output. These types of capacitors, due to their very low series
resistance (ESR), minimize the output voltage ripple. Other low ESR capacitors can be used
according to the need of the application without compromising the correct functionality of the
device. Due to the high switching frequency and peak current, it is important to optimize the
application environment by reducing the length of the PCB traces and placing all the
external components near the device.
Figure 25. Reset function
VTH
VIN
VTL
tDEL
Reset
15/21
Package mechanical data
ST2S06A33 - ST2S06B - ST2S06D33
8
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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ST2S06A33 - ST2S06B - ST2S06D33
Package mechanical data
QFN12L (4x4) mechanical data
mm.
Typ.
0.90
inch.
Dim.
Min.
Max.
1.00
0.05
Min.
Typ.
0.035
0.001
0.008
0.012
0.157
0.085
0.157
0.085
0.031
0.022
Max.
0.039
0.002
A
A1
A3
b
0.80
0.031
0.02
0.20
0.30
4.00
2.15
4.00
2.15
0.80
0.55
0.25
3.90
2.00
3.90
2.00
0.35
4.10
2.25
4.10
2.25
0.010
0.154
0.079
0.154
0.079
0.014
0.161
0.089
0.161
0.089
D
D2
E
E2
e
L
0.45
0.65
0.018
0.026
7936361B
17/21
Package mechanical data
ST2S06A33 - ST2S06B - ST2S06D33
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
330
Min.
Max.
12.992
0.519
A
C
D
12.8
20.2
99
13.2
0.504
0.795
3.898
N
101
3.976
T
14.4
0.567
Ao
Bo
Ko
Po
P
4.35
4.35
1.1
4
0.171
0.171
0.043
0.157
0.315
8
18/21
ST2S06A33 - ST2S06B - ST2S06D33
Package mechanical data
Figure 26. QFN12L (4x4 mm) footprint recommended data
19/21
Revision history
ST2S06A33 - ST2S06B - ST2S06D33
9
Revision history
Table 10. Document revision history
Date
Revision
Changes
3-Sep-2007
21-Jan-2008
18-Mar-2008
1
2
3
Initial release.
Added root part number ST2S06D33.
Modified: Table 2 on page 4.
20/21
ST2S06A33 - ST2S06B - ST2S06D33
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21/21
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