ST72521R9T3/XXX [STMICROELECTRONICS]
8-BIT, MROM, MICROCONTROLLER, PQFP64, 14 X 14 MM, TQFP-64;
| 型号： | ST72521R9T3/XXX |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP64, 14 X 14 MM, TQFP-64 时钟 微控制器 外围集成电路 |
| 文件： | 总11页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72521M/R/AR
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
2
FIVE TIMERS, SPI, SCI, I C, CAN INTERFACE
DATA BRIEFING
■ Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
■ Cloc anced reset system
– Enhanced low voltage supervisor (LVD) for
TQFP64
14 x 14
main supply and auxiliary voltage detector
(AVD) with interrupt capability
TQFP64
10 x 10
– Clock sources: crystal/ceramic resonator os-
cillators, internal or external RC oscillator,
clock security system and bypass for external
clock
TQFP80
14 x 14
– PLL for 2x frequency multiplication
– Four power saving modes: Halt, Active-Halt,
Wait and Slow
■ Interrupt Management
■ 4 Communications Interfaces
– SPI synchronous serial interface
– Nested interrupt controller
– SCI asynchronous serial interface (LIN com-
– 14 interrupt vectors plus TRAP and RESET
– TLI dedicated top level interrupt pin
– 15 external interrupt lines (on 4 vectors)
■ Up to 64 I/O Ports
patible)
2
– I C multimaster interface
– CAN interface (2.0B Passive)
■ Analog peripheral
– 48 multifunctional bidirectional I/O lines
– 34 alternate function lines
– 16 high sink outputs
– 10-bit ADC with 16 input pins
■ Instruction Set
■ 5 Timers
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
– True Bit Manipulation
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
and time base interrupt, external clock with
event detector
■ Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range (ROM)
Temp. Range (Flash)
Package
ST72(F)521(M/R/AR)9
60K
ST72521(M/R/AR)7
48K
ST72(F)521(R/AR)6
32K
2048 (256)
1536 (256)
1024 (256)
3.8V to 5.5V
0°C to 70°C / -10°C to +85 °C / -40°C to +85 °C / -40°C to +105°C / -40°C to +125°C
-40°C to +85 °C / -40°C to +125°C
N/A
-40°C to +125 °C
TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR)
TQFP64 14x14 (R), TQFP64 10x10 (AR)
Rev. 1.5
1/11
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1
ST72521M/R/AR
Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or stand-by state.
1 INTRODUCTION
The ST72521(A)R and ST72521M devices are
members of the ST7 microcontroller family de-
signed for mid-range applications with a CAN bus
interface (Controller Area Network).
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
All devices are based on a common industry-
standard 8-bitcore, featuring an enhanced instruc-
tion set and are available with FLASH or ROM pro-
gram memory.
Figure 1. Device Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(32K - 60K Bytes)
RESET
CONTROL
V
PP
RAM
TLI
(1024-2048 Bytes)
V
SS
DD
LVD
AVD
OSC
V
EVD
WATCHDOG
OSC1
OSC2
I2C
PA7:0
(8-bits)
MCC/RTC/BEEP
PORT A
PORT B
PORT F
TIMER A
BEEP
PF7:0
(8-bits)
PB7:0
(8-bits)
PWM ART
PORT C
PORT E
CAN
PC7:0
TIMER B
(8-bits)
PE7:0
(8-bits)
SPI
SCI
PG7:0
(8-bits)
1
PORT D
10-BIT ADC
PORT G
PD7:0
(8-bits)
PH7:0
(8-bits)
1
PORT H
V
AREF
V
SSA
1
On some devices only, see Device Summary on page 1
2/11
ST72521M/R/AR
2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
(HS) PE4
(HS) PE5
V
V
SS_1
DD_1
2
(HS) PE6
3
PA3 (HS)
(HS) PE7
4
PA2
ei0
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
PG0
5
PA1
6
PA0
ei2
7
PC7 / SS / AIN15
PC6 / SCK /ICCCLK
8
9
PH3
PH2
PH1
PG1
10
11
12
13
14
15
16
17
18
19
20
PG2
PH0
PG3
PC5 / MOSI / AIN14
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
PC4 / MISO / ICCDATA
ei3
PC3 (HS) /ICAP1_B
PC2(HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B /AIN12
VSS_0
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
ei1
VDD_0
(HS) 20mA high sink capability
eix associated external interrupt vector
3/11
ST72521M/R/AR
PIN DESCRIPTION (Cont’d)
Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
V
(HS) PE4
(HS) PE5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
SS_1
DD_1
2
PA3 (HS)
(HS) PE6
3
PA2
(HS) PE7
4
ei0
PA1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 /PB3
ARTCLK /(HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
5
PA0
6
ei2
ei3
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
7
8
9
10
11
12
13
14
15
16
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
ei1
V
SS_0
V
DD_0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(HS) 20mA high sink capability
eix associated external interrupt vector
4/11
ST72521M/R/AR
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V
DD
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
T = TTL 0.8V / 2V with Schmitt trigger
T
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
1
2
1
2
3
4
5
6
7
8
-
PE4 (HS)
I/O C
I/O C
I/O C
I/O C
I/O C
HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E4
Port E5
Port E6
Port E7
T
T
T
T
T
T
T
T
T
T
T
T
PE5 (HS)
PE6 (HS)
PE7 (HS)
PB0/PWM3
PB1/PWM2
PB2/PWM1
PB3/PWM0
PG0
HS
HS
HS
X
3
X
4
X
5
ei2
ei2
ei2
Port B0 PWM Output 3
Port B1 PWM Output 2
Port B2 PWM Output 1
Port B3 PWM Output 0
Port G0
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C
C
C
7
8
ei2
9
T
T
T
T
X
X
X
X
10
11
12
13
-
PG1
Port G1
-
PG2
Port G2
-
PG3
Port G3
9
PB4 (HS)/ARTCLK
C
C
C
C
C
C
C
C
HS
ei3
Port B4 PWM-ART External Clock
Port B5 PWM-ART Input Capture 1
Port B6 PWM-ART Input Capture 2
Port B7
T
T
T
T
T
T
T
T
T
T
14 10 PB5/ARTIC1
15 11 PB6/ARTIC2
16 12 PB7
ei3
ei3
ei3
17 13 PD0 /AIN0
18 14 PD1/AIN1
19 15 PD2/AIN2
20 16 PD3/AIN3
X
X
X
X
X
Port D0 ADC Analog Input 0
Port D1 ADC Analog Input 1
Port D2 ADC Analog Input 2
Port D3 ADC Analog Input 3
Port G6
X
X
X
X
X
X
X
X
X
21
22
-
-
PG6
PG7
T
T
Port G7
23 17 PD4/AIN4
24 18 PD5/AIN5
25 19 PD6/AIN6
26 20 PD7/AIN7
C
C
C
C
X
X
X
X
Port D4 ADC Analog Input 4
Port D5 ADC Analog Input 5
Port D6 ADC Analog Input 6
Port D7 ADC Analog Input 7
T
T
T
T
5/11
ST72521M/R/AR
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
27 21
28 22
29 23
30 24
V
V
V
V
I
Analog Reference Voltage for ADC
Analog Ground Voltage
Digital Main Supply Voltage
Digital Ground Voltage
Port G4
AREF
SSA
S
S
DD_3
SS_3
S
31
32
-
-
PG4
PG5
I/O
I/O
T
T
X
X
X
X
X
X
X
X
T
T
Port G5
Main clock
ADC Analog
33 25 PF0/MCO/AIN8
I/O
C
X
ei1
ei1
X
X
Port F0
T
out (f /2) Input 8
OSC
34 26 PF1 (HS)/BEEP
35 27 PF2 (HS)
I/O
I/O
C
C
HS
HS
X
X
X
X
X
X
Port F1 Beep signal output
Port F2
T
ei1
T
Timer A Out-
Port F3 put Compare
2
ADC Analog
Input 9
36 28 PF3/OCMP2_A/AIN9
37 29 PF4/OCMP1_A/AIN10
I/O
I/O
C
C
X
X
X
X
X
X
X
X
T
Timer A Out-
Port F4 put Compare
1
ADC Analog
Input 10
T
Timer A Input ADC Analog
Capture 2 Input 11
38 30 PF5/ICAP2_A/AIN11
39 31 PF6 (HS)/ICAP1_A
40 32 PF7 (HS)/EXTCLK_A
I/O
I/O
I/O
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
Port F5
T
T
T
HS
HS
Port F6 Timer A Input Capture 1
Timer A External Clock
Port F7
Source
41 33
42 34
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
Timer B Out-
DD_0
SS_0
ADC Analog
43 35 PC0/OCMP2_B/AIN12
44 36 PC1/OCMP1_B/AIN13
I/O
I/O
C
C
X
X
X
X
X
X
X
X
Port C0 put Compare
2
T
Input 12
Timer B Out-
Port C1 put Compare
1
ADC Analog
Input 13
T
45 37 PC2 (HS)/ICAP2_B
46 38 PC3 (HS)/ICAP1_B
I/O
I/O
C
C
HS
HS
X
X
X
X
X
X
X
X
Port C2 Timer B Input Capture 2
Port C3 Timer B Input Capture 1
SPI Master In
T
T
ICC Data In-
47 39 PC4/MISO/ICCDATA
48 40 PC5/MOSI/AIN14
I/O
I/O
C
X
X
X
X
X
X
X
X
Port C4 / Slave Out
Data
T
T
put
SPI Master
Port C5 Out / Slave In
Data
ADC Analog
Input 14
C
49
50
51
52
-
-
-
-
PH0
PH1
PH2
PH3
I/O
I/O
I/O
I/O
T
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port H0
Port H1
Port H2
Port H3
T
T
T
T
SPI Serial
Port C6
ICC Clock
Output
53 41 PC6/SCK/ICCCLK
I/O
C
X
X
X
X
T
Clock
6/11
ST72521M/R/AR
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate function
reset)
SPI Slave
Port C7 Select (active
low)
ADC Analog
Input 15
54 42 PC7/SS/AIN15
I/O
C
X
X
X
X
T
55 43 PA0
56 44 PA1
57 45 PA2
58 46 PA3 (HS)
I/O
I/O
I/O
I/O
S
C
C
C
C
X
X
X
X
ei0
ei0
ei0
X
X
X
X
X
X
X
X
Port A0
Port A1
Port A2
Port A3
T
T
T
T
HS
ei0
59 47
60 48
V
V
Digital Main Supply Voltage
Digital Ground Voltage
Port A4
DD_1
SS_1
S
61 49 PA4 (HS)
I/O
I/O
I/O
I/O
C
C
C
C
HS
HS
HS
HS
X
X
X
X
X
X
X
X
T
T
X
X
T
T
T
T
62 50 PA5 (HS)
Port A5
2
1)
63 51 PA6 (HS)/SDAI
64 52 PA7 (HS)/SCLI
Port A6
Port A7
I C Data
2
1)
I C Clock
Must be tied low. In flash programming
mode, this pin acts as the programming
65 53
V
/ ICCSEL
I
PP
voltage input V . High voltage must
PP
not be applied to ROM devices
Top priority non maskable interrupt.
External voltage detector
Top level interrupt input pin
Port H4
66 54 RESET
67 55 EVD
68 56 TLI
I/O
C
C
T
I
X
X
X
X
X
X
T
T
T
T
T
69
70
71
72
-
-
-
-
PH4
PH5
PH6
PH7
I/O
I/O
I/O
I/O
S
T
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
Port H5
Port H6
Port H7
73 57
V
Digital Ground Voltage
SS_2
Resonator oscillator inverter output or
capacitor input for RC oscillator
3)
3)
74 58 OSC2
I/O
External clock input or Resonator oscil-
lator inverter input or resistor input for
RC oscillator
75 59 OSC1
I
76 60
V
S
Digital Main Supply Voltage
DD_2
77 61 PE0/TDO
78 62 PE1/RDI
I/O
I/O
I/O
I/O
C
C
C
C
X
X
X
X
X
X
X
X
X
X
Port E0 SCI Transmit Data Out
Port E1 SCI Receive Data In
Port E2 CAN Transmit Data Output
Port E3 CAN Receive Data Input
T
T
T
T
79 63 PE2/CANTX
80 64 PE3/CANRX
X
X
X
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD
7/11
ST72521M/R/AR
are not implemented).
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, an RC oscillator, or an external source to
the on-chip oscillator;
4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up con-
figuration after reset. The configuration of these pads must be kept at reset state to avoid added current
consumption.
8/11
ST72521M/R/AR
3 PACKAGE CHARACTERISTICS
3.1 PACKAGE MECHANICAL DATA
Figure 4. 80-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.22 0.32 0.38 0.009 0.013 0.015
0.09
0.20 0.004
0.008
D
16.00
14.00
16.00
14.00
0.65
0.630
0.551
0.630
0.551
0.026
3.5°
e
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
80
c
L1
L1
L
h
N
Figure 5. 64-Pin Thin Quad Flat Package
A
mm
inches
D
Dim.
A2
Min Typ Max Min Typ Max
D1
A
1.60
0.063
0.006
A1
b
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004
0.008
D
16.00
14.00
16.00
14.00
0.80
0.630
0.551
0.630
0.551
0.031
3.5°
e
D1
E
E
E1
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
L
L1
L1
c
N
h
9/11
ST72521M/R/AR
PACKAGE MECHANICAL DATA (Cont’d)
Figure 6. 64-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
c
0.17 0.22 0.27 0.007 0.009 0.011
b
e
0.09
0.20 0.004
0.008
D
12.00
10.00
12.00
10.00
0.50
0.472
0.394
0.472
0.394
0.020
3.5°
E1
D1
E
E
E1
e
θ
0°
3.5°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
64
h
L1
L
N
Figure 7. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
mm
Min Typ Max Min Typ Max
5.08 0.200
inches
Dim.
E
A
A2
A
L
A1 0.51
A2 3.05 3.81 4.57 0.120 0.150 0.180
0.38 0.46 0.56 0.015 0.018 0.022
b2 0.89 1.02 1.14 0.035 0.040 0.045
0.020
A1
c
E1
eA
b
b2
b
e
eB
E
D
c
D
E
0.23 0.25 0.38 0.009 0.010 0.015
36.58 36.83 37.08 1.440 1.450 1.460
0.015
15.24
16.00 0.600
0.630
GAGE PLANE
E1 12.70 13.72 14.48 0.500 0.540 0.570
e
1.78
0.070
0.600
eA
eB
eC
L
15.24
eC
18.54
0.730
0.060
eB
1.52 0.000
2.54 3.30 3.56 0.100 0.130 0.140
Number of Pins
N
42
10/11
ST72521M/R/AR
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
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