ST7263BK2M1/XXX [STMICROELECTRONICS]
Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C; 低速USB 8位MCU系列具有高达32 KB的闪存/ ROM ， DFU功能， 8位ADC ， WDG ，定时器， SCI和I²C
| 型号： | ST7263BK2M1/XXX |
| 厂家： | 
ST |
| 描述： | Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C |
| 文件： | 总186页 (文件大小：2340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7263BHx ST7263BDx
ST7263BKx ST7263BEx
Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM,
DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
Features
■ Memories
– 4, 8, 16 or 32 Kbytes Program memory:
high density Flash (HDFlash), or ROM with
Readout and Write Protection
LQFP48 (7x7)
SDIP32
– In-application Programming (IAP) and in-
circuit programming (ICP)
– 384, 512 or 1024 bytes RAM memory (128-
byte stack)
24
■ Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
1
QFN40 (6x6)
SO34(Shrink)
SO24
■ 2 communication Interfaces
– RAM retention mode
– Optional low voltage detector (LVD)
– Asynchronous serial communications inter-
face
– I²C multimaster interface up to 400 kHz
■ Universal serial bus (USB) interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID
specifications (version 1.0)
■ Instruction set
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
– Integrated 3.3 V voltage regulator and
transceivers
– Supports USB DFU class specification
– Suspend and Resume operations
■ Development tools
– 3 endpoints with programmable In/Out
configuration
– Versatile development tools (under
Windows) including assembler, linker, C-
compiler, archiver, source level debugger,
software library, hardware emulator,
programming boards and gang
programmers, HID and DFU software
layers
■ Up to 27 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os
(25 mA at 1.5 V)
– Up to 8 lines individually programmable as
interrupt inputs
Table 1.
Device summary
Part number
■ 1 analog peripheral
Reference
– 8-bit A/D converter with 8 or 12 channels
ST7263BHx
ST7263BDx
ST7263BH2, ST7263BH6
ST7263BD6
■ 2 timers
– Programmable watchdog
– 16-bit timer with 2 input Captures, 2 output
Compares, PWM output and clock input
ST7263BK1, ST7263BK2,
ST7263BK4, ST7263BK6
ST7263BKx
ST7263BEx
ST7263BE1, ST7263BE2,
ST7263BE4, ST7263BE6
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1
Contents
ST7263Bxx
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
2.3
2.4
2.5
RESET signal (bidirectional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OSCIN/OSCOUT: input/output oscillator pin . . . . . . . . . . . . . . . . . . . . . . 13
VDD/VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VDDA/VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4
4.5
4.6
4.7
4.8
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
6
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1.1
6.1.2
6.1.3
Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2
Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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6.2.1
6.2.2
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1
8.2
8.3
8.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
9.2
9.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10
11
Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.4 Software Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1.5 Hardware Watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.1.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.2.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.3 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.3.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.3.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.4 USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.4.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.5.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.6 8-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.6.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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12
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.1.2 Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
13.3.1 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 141
13.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.6.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
13.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
13.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 147
13.7.2 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
13.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 148
13.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.10 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158
13.10.1 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
13.10.2 SCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
13.10.3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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13.11 8-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
14
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
14.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
14.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14.3 Soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
15
Device configuration and ordering information . . . . . . . . . . . . . . . . . 172
15.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.2 Device ordering information and transfer of customer code . . . . . . . . . . 173
15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.3.1 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.3.4 Order codes for ST7263Bx development tools . . . . . . . . . . . . . . . . . . 175
15.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
16
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.2 Unexpected RESET fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.3 USB behavior with LVD disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.4 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.5 Halt mode power consumption with ADC on . . . . . . . . . . . . . . . . . . . . . 182
16.6 SCI wrong BREAK duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6/186
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device pin description (QFN40, LQFP48, SO34 and SDIP32). . . . . . . . . . . . . . . . . . . . . . 17
Device pin description (SO24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hardware register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Recommended Values for 24 MHz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A0, A3, A4, A5, A6, A7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PA1, PA2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port B description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port C description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Port D description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O ports register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Watchdog timing (fCPU = 8 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
OC/R register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Clock Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Prescaling factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TR dividing factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
RR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TP bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STAT_TX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
STAT_RX bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Slave receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Slave Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Master Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
I²C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Doc ID 7516 Rev 8
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List of tables
ST7263Bxx
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 57.
Table 56.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Instructions supporting Direct, Indexed, Indirect and Indirect Indexed addressing modes133
Instructions supporting relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Operating conditions with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Dual voltage Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
USB DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
USB low-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SCI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SCL frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
ADC accuracy with VDD=5 V, fCPU= 8 MHz, fADC=4 MHz, RAIN< 10 κΩ. . . . . . . . . . . . .163
32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data . . . . 166
34-pin plastic small outline package, 300-mil width, package mechanical data . . . . . . . . 167
24-pin plastic small outline package, 300-mil width package mechanical data . . . . . . . . 168
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 170
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Development tool order codes for the ST7263Bx family . . . . . . . . . . . . . . . . . . . . . . . . . 175
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
48-pin LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
40-lead QFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
34-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
32-pin SDIP package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
24-pin SO package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Low voltage detector functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Low Voltage Reset signal output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Temporization timing diagram after an internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16. External clock source connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. Crystal/ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. Clock block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. PA1, PA2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 24. Port B and D[3:0] configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 25. Port C configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 28. 16-bit read sequence (from either the Counter register or the Alternate Counter register) 61
Figure 29. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 30. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 31. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 32. Input Capture block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 33. Input Capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 34. Output Compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 35. Output Compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 36. Output Compare timing diagram, ftimeR = fCPU/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 37. One Pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 38. One Pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 39. Pulse Width modulation mode timing with 2 output Compare functions. . . . . . . . . . . . . . . 70
Figure 40. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 41. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 42. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 43. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 44. USB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 45. DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 46. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 47. I²C interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 48. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Doc ID 7516 Rev 8
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List of figures
ST7263Bxx
Figure 49. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 50. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 51. ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 52. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 53. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 54. fCPU maximum operating frequency versus V supply voltage. . . . . . . . . . . . . . . . . . . 141
DD
Figure 55. Typ. IDD in Run at fCPU = 4 and 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 56. Typ. IDD in Wait at fCPU= 4 and 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 57. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 58. Typical application with a crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 59. Two typical applications with VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 60. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 61. Typ. IPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 62. Typ. RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 63. VOL standard VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 64. VOL high sink VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 65. VOL very high sink VDD=5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 66. VOL standard vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 67. VOL high sink vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 68. VOL very high sink vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 69. |VDD-VOH| @ VDD=5 V (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 70. |VDD-VOH| @ VDD=5 V (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 71. |VDD-VOH| @ IIO=2 mA (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 72. |VDD-VOH| @ IIO=10 mA (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 73. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 74. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 75. USB data signal rise and fall time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 76. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 77. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 78. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 166
Figure 80. 34-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 167
Figure 81. 24-pin plastic small outline package, 300-mil width package outline . . . . . . . . . . . . . . . . 168
Figure 82. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 83. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 170
Figure 84. Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 85. Identifying silicon revision from device marking and box label . . . . . . . . . . . . . . . . . . . . . 183
10/186
Doc ID 7516 Rev 8
ST7263Bxx
Introduction
1
Introduction
The ST7263B microcontrollers form a sub-family of the ST7 MCUs dedicated to USB
applications. The devices are based on an industry-standard 8-bit core and feature an
enhanced instruction set. They operate at a 24 MHz or 12 MHz oscillator frequency. Under
software control, the ST7263B MCUs may be placed in either Wait or Halt modes, thus
reducing power consumption. The enhanced instruction set and addressing modes afford
real programming potential. In addition to standard 8-bit data management, the ST7263B
MCUs feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes. The devices include an ST7 core, up to 32 Kbytes of program memory, up to
1024 bytes of RAM, 27 I/O lines and the following on-chip peripherals:
●
USB low speed interface with 3 endpoints with programmable in/out configuration using
the DMA architecture with embedded 3.3 V voltage regulator and transceivers (no
external components are needed).
●
●
●
●
8-bit analog-to-digital converter (ADC) with 12 multiplexed analog inputs
Industry standard asynchronous SCI serial interface
Watchdog
16-bit Timer featuring an External clock input, 2 input Captures, 2 output Compares
with Pulse Generator capabilities
●
●
Fast I²C multimaster interface
Low voltage reset (LVD) ensuring proper power-on or power-off of the device
The ST72F63B devices are Flash versions. They support programming in IAP mode (In-
application programming) via the on-chip USB interface.
Table 2.
Features
Device overview
ST7263BHx
ST7263BDx
ST7263BKx
ST7263BEx
Program
memory -
Kbytes (Flash /
ROM)
32
16
8
32
32
16
8
4
32
16
8
4
1024
(128
384
(128
RAM (stack) -
bytes
1024 512 384
(128) (128) (128)
512
(128)
384
(128)
1024 512 384 384
(128) (128) (128) (128)
1024 (128)
Standard
Peripherals
Watchdog timer, 16-bit timer, USB
SCI,
Other
Peripherals
SCI, I²C, ADC
ADC
SCI, I²C
14 (6)
AD
I/Os (high
current)
27 (10)
19 (10)
Operating
Supply
4.0 V to 5.5 V
CPU frequency
8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
0 °C to +70 °C
Operating
temp.
QFN40
(6x6)
SDIP32/
SO34
QFN40 SDIP32/
(6x6) SO34
Packages
LQFP48 (7x7)
SO24
Doc ID 7516 Rev 8
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Introduction
ST7263Bxx
Figure 1.
General block diagram
INTERNAL
CLOCK
OSC/3
OSCIN
OSCILLATOR
OSCOUT
I²C
OSC/4 or OSC/2
for USB2)
PA[7:0]
(8 bits)
VDD
VSS
PORT A
POWER
SUPPLY
WATCHDOG
CONTROL
16-BIT TIMER
PORT B
ADC(1)
PB[7:0]
(8 bits)
RESET
8-BIT CORE
ALU
PD[7:0]
(8 bits)
PORT D
LVD
PORT C
USB DMA
PC[2:0]
(3 bits)
SCI
VPP/TEST
PROGRAM
MEMORY
(UART)
VDDA
VSSA
(32K Bytes)
USBDP
USBDM
USBVCC
USB SIE
RAM
(1024 Bytes)
1. ADC channels:
12 on 48-pin devices (Port B and Port D[3:0])
8 on 34 and 32-pin devices (Port B)
None on 24-pin devices
2. 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.
3. The drive from USBVCC is sufficient to only drive an external pull-up in addition to the internal transceiver.
12/186
Doc ID 7516 Rev 8
ST7263Bxx
Pin description
2
Pin description
2.1
RESET signal (bidirectional)
It is active low and forces the initialization of the MCU. This event is the top priority non
maskable interrupt. This pin is switched low when the Watchdog is triggered or the V is
DD
low. It can be used to reset external peripherals.
Note:
Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to V
DD
and V ) will significantly improve product electromagnetic susceptibility performance.
SS
2.2
OSCIN/OSCOUT: input/output oscillator pin
These pins connect a parallel-resonant crystal, or an external source, to the on-chip
oscillator.
2.3
VDD/VSS
Main power supply and ground voltages
Note:
To enhance the reliability of operation, it is recommended that V
and V be connected
DDA DD
together on the application board. This also applies to V
and V
.
SS
SSA
2.4
VDDA/VSSA
Power supply and ground voltages for analog peripherals.
Note:
To enhance the reliability of operation, it is recommended that V
and V be connected
DD
DDA
together on the application board. This also applies to V
and V
.
SSA
SS
2.5
Alternate functions
Several pins of the I/O ports assume software programmable alternate functions as shown
in the pin description.
Note:
1
2
The USBOE alternate function is mapped on Port C2 in 32/34/48 pin devices. In SO24
devices it is mapped on Port B1.
The timer OCMP1 alternate function is mapped on Port A6 in 32/34/48 pin devices. In SO24
devices it is not available.
Doc ID 7516 Rev 8
13/186
Pin description
Figure 2.
ST7263Bxx
48-pin LQFP pinout
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
VSSA
USBDP
USBDM
USBVCC
VDDA
PA3/EXTCLK
2
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
PB5(10mA)/AIN5/IT6
VPP/TEST
3
4
5
6
VDD
7
OSCOUT
OSCIN
VSS
8
9
10
11
12
USBOE/PC2
NC
NC
13 14 15 16 17 18 19 20 21 22 23
24
14/186
Doc ID 7516 Rev 8
ST7263Bxx
Pin description
Figure 3.
40-lead QFN package pinout
40 39 38 37 36 35 34 33 32 31
30
29
28
27
26
25
24
23
22
21
PA0/MCO
VSSA
1
2
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
PB1(10mA)/AIN1
PB2(10mA)/AIN2
PB3(10mA)/AIN3
PB4(10mA)/AIN4/IT5
USBDP
USBDM
USBVCC
VDDA
3
4
5
6
VDD
7
OSCOUT
OSCIN
VSS
8
9
10
11 12 13 14 15 16 17 18 19 20
1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should
not be connected.
Doc ID 7516 Rev 8
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Pin description
Figure 4.
ST7263Bxx
34-pin SO package pinout
34 VDDA
33
VDD
OSCOUT
OSCIN
1
USBVCC
2
32 USBDM
3
31 USBDP
4
VSS
PC2/USBOE
PC1/TDO
PC0/RDI
30
5
VSSA
29 PA0/MCO
6
28
7
PA1(25mA)/SDA/ICCDATA
27
26
25
24
23
22
21
20
19
18
8
NC
NC
NC
RESET
9
NC
AIN7/IT8/PB7(10mA)
AIN6/PB6/IT7(10mA)
10
11
12
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
V
PP/TEST
AIN5/IT6/PB5(10mA)
AIN4/IT5/PB4(10mA)
AIN3/PB3(10mA)
AIN2/PB2(10mA)
AIN1/PB1(10mA)
13
14
15
16
17
Figure 5.
32-pin SDIP package pinout
1
2
VDDA
USBVCC
USBDM
USBDP
VSSA
PA0/MCO
PA1(25mA)/SDA/ICCDATA
NC
VDD
OSCOUT
OSCIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
4
VSS
5
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
6
7
8
9
AIN7/IT8/PB7(10mA)
AIN6/IT7/PB6(10mA)
VPP/TEST
AIN5/IT6/PB5(10mA)
AIN4/IT5/PB4(10mA)
AIN3/PB3(10mA)
AIN2/PB2(10mA)
AIN1/PB1/(10mA)
NC
10
11
12
13
14
15
16
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0(10mA)/AIN0
Figure 6.
24-pin SO package pinout
24
23
1
USBVcc
USBDM
USBDP
VSSA
VDD
2
OSCOUT
22
21
20
19
18
17
16
15
14
13
3
OSCIN
VSS
TDO/PC1
4
5
PA0/MCO
6
PA1(25mA)/SDA/ICCDATA
PA2(25mA)/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA7/OCMP2/IT4
PB0(10mA)
RDI/PC0
RESET/
IT7/PB6(10mA)
7
8
9
VPP/TEST
PB3(10mA)
PB2(10mA)
10
11
12
USBOE/PB1(10mA)
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Doc ID 7516 Rev 8
ST7263Bxx
Pin description
Legend / Abbreviations for Table 3 and Table 4:
Type: I = input, O = output, S = supply
In/Output level:C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level: 10 mA = 10mA high sink (Fn N-buffer only)
25 mA = 25 mA very high sink (on N-buffer only)
Port and control configuration:
●
Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open drain, PP = push-pull, T = True open drain
●
The RESET configuration of each pin is shown in bold. This configuration is kept as long as
the device is under reset state.
Table 3.
Pin n°
Device pin description (QFN40, LQFP48, SO34 and SDIP32)
Level
Port /control
Main
function
(after
Input
Output
Pin name
Alternate function
reset)
1
2
3
4
5
1
2
3
4
5
7
8
6
7
8
9
VDD
S
O
I
Power supply voltage (4- 5.5 V)
Oscillator output
OSCOUT
OSCIN
VSS
9
Oscillator input
10
S
Digital ground
11 10 PC2/USBOE
12 13 PC1/TDO
I/O
CT
CT
X
X
X
X
Port C2
Port C1
USB output Enable
SCI Transmit Data
output
6
7
6
7
I/O
SCI Receive Data
input
13 14 PC0/RDI
I/O CT
X
X
X
Port C0
Reset
8
-
8
9
-
14 15 RESET
15 16 NC
I/O
X
--
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
-
16 17 NC
--
-
-
-
-
-
-
-
18 NC
19 NC
20 NC
21 NC
22 NC
--
-
-
--
-
-
--
-
-
--
-
-
--
9
10 17 23 PB7/AIN7/IT8
I/O CT 10mA
I/O CT 10mA
S
X
X
X
X
X
X
X
X
Port B7
Port B6
ADC analog input 7
ADC analog input 6
10 11 18 24 PB6/AIN6/IT7
11 12 19 25 VPP/TEST
12 13 20 26 PB5/AIN5/IT6
13 14 21 27 PB4/AIN4/IT5
14 15 22 28 PB3/AIN3
Programming supply
I/O CT 10mA
I/O CT 10mA
I/O CT 10mA
X
X
X
X
X
X
X
X
X
X
X
Port B5
Port B4
Port B3
ADC analog input 5
ADC analog input 4
ADC analog input 3
Doc ID 7516 Rev 8
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Pin description
ST7263Bxx
Table 3.
Pin n°
Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued)
Level
Port /control
Input Output
Main
function
(after
Pin name
Alternate function
reset)
15 16 23 29 PB2/AIN2
16 17 24 30 PB1/AIN1
17 18 25 31 PB0/AIN0
I/O CT 10mA
I/O CT 10mA
I/O CT 10mA
X
X
X
X
X
X
X
X
X
Port B2
Port B1
Port B0
ADC analog input 2
ADC analog input 1
ADC analog input 0
Timer output
Compare 2
18 19 26 32 PA7/OCMP2/IT4
19 20 27 33 PA6/OCMP1/IT3
20 21 28 34 PA5/ICAP2/IT2
21 22 29 35 PA4/ICAP1/IT1
22 23 30 36 PA3/EXTCLK
23 24 31 38 PA2/SCL/ICCCLK
I/O
I/O
I/O
I/O
I/O
CT
CT
CT
CT
CT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port A7
Port A6
Port A5
Port A4
Port A3
Port A2
Timer output
Compare 1
Timer input
Capture 2
Timer input
Capture 1
Timer External
clock
I²C serial clock,
ICC clock
I/O CT 25mA
X
T
-
-
-
-
32 39 PD0(1)/AIN8
33 40 PD1(1)/AIN9
I/O CT
I/O CT
X
X
X
X
X
X
Port D0
Port D1
ADC analog input 8
ADC analog input 9
ADC analog input
10
-
-
-
-
34 41 PD2(1)/AIN10
35 42 PD3(1)/AIN11
I/O CT
I/O CT
X
X
X
X
X
X
Port D2
Port D3
ADC analog input
11
-
-
-
-
-
-
-
36 43 PD4(1)
37 44 PD5(1)
38 45 PD6(1)
39 46 PD7(1)
I/O CT
I/O CT
I/O CT
I/O CT
--
X
X
X
X
X
X
X
X
Port D4
Port D5
Port D6
Port D7
-
-
25
-
-
-
-
-
-
NC
NC
NC
Not connected
Not connected
Not connected
24 26
25 27
--
--
I²C serial data, ICC
data
26 28 40 47 PA1/SDA/ICCDATA
I/O CT 25mA
X
T
Port A1
Port A0
27 29
28 30
29 31
30 32
1
2
3
4
48 PA0/MCO
I/O
S
CT
X
X
Main clock output
1
2
3
VSSA
Analog ground
USBDP
USBDM
I/O
I/O
USB bidirectional data (data +)
USB bidirectional data (data -)
18/186
Doc ID 7516 Rev 8
ST7263Bxx
Pin description
Alternate function
Table 3.
Pin n°
Device pin description (QFN40, LQFP48, SO34 and SDIP32) (continued)
Level
Port /control
Input Output
Main
function
(after
Pin name
reset)
31 33
32 34
5
6
4
5
USBVCC(2)
VDDA
O
S
USB power supply 2)
Analog supply voltage
1. Port D functions are not available on the 8 Kbyte version of the QFN40 package (ST7263BK2) and should not be
connected.
2. The drive from USBVcc is sufficient to only drive an external pull-up in addition to the internal transceiver.
Table 4.
Pin n°
Device pin description (SO24)
Level
Port /control
Main
function
(after
Input
Output
Pin name
Alternate function
reset)
1
2
3
4
VDD
S
Power supply voltage (4- 5.5 V)
Oscillator output
OSCOUT
OSCIN
VSS
O
I
Oscillator input
S
Digital ground
SCI Transmit Data
5
PC1/TDO
I/O
CT
X
X
X
Port C1
output
6
7
PC0/RDI
RESET
PB6/IT7
VPP/TEST
PB3
I/O CT
I/O
X
X
X
Port C0
Reset
SCI Receive Data input
X
8
I/O CT 10mA
S
X
X
X
Port B6
9
Programming supply
Port B3
10
11
12
13
I/O CT 10mA
I/O CT 10mA
I/O CT 10mA
I/O CT 10mA
X
X
X
X
X
X
X
X
X
X
X
X
PB2
Port B2
PB1/USBOE
PB0
Port B1
Port B0
USB output Enable
Timer output Compare
2
14
PA7/OCMP2/IT4
I/O
CT
X
X
X
Port A7
15
16
17
PA5/ICAP2/IT2
PA4/ICAP1/IT1
PA3/EXTCLK
I/O
I/O
I/O
CT
CT
CT
X
X
X
X
X
X
X
X
Port A5
Port A4
Port A3
Timer input Capture 2
Timer input Capture 1
Timer External clock
PA2/SCL/
ICCCLK
I²C serial clock,
ICC clock
18
19
I/O CT 25mA
I/O CT 25mA
X
X
T
T
Port A2
Port A1
I²C serial data, ICC
Data
PA1/SDA/ICCDATA
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Pin description
ST7263Bxx
Table 4.
Pin n°
Device pin description (SO24) (continued)
Level
Port /control
Main
function
(after
Input
Output
Pin name
Alternate function
reset)
20
21
22
23
24
PA0/MCO
I/O
S
CT
X
X
Port A0
Main Clock output
VSSA
Analog ground
USBDP
USBDM
USBVCC
I/O
I/O
O
USB bidirectional data (data +)
USB bidirectional data (data -)
USB power supply
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Register and memory map
3
Register and memory map
As shown in Figure 7, the MCU is capable of addressing 32 Kbytes of memories and I/O
registers.
The available memory locations consist of up to 1024 bytes of RAM including 64 bytes of
register locations, and up to 32K bytes of user program memory in which the upper 32 bytes
are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.
The highest address bytes contain the user reset and interrupt vectors.
Caution:
Memory locations noted “Reserved” must never be accessed. Accessing a reserved area
can have unpredictable effects on the device.
Figure 7.
Memory map
0040h
0000h
Short Addressing
RAM (192 bytes)
HW registers
(See Table 5)
00FFh
0100h
003Fh
0040h
Stack
(128 Bytes)
RAM
(384 / 512 / 1024 Bytes)
017Fh
0180h
01BF / 023F / 043Fh
01C0 / 0240 / 0440h
16-bit Addressing
RAM
Reserved
01BF / 023F / 043Fh
8000h
7FFFh
8000h
Program memory
32 KBytes
(4 / 8 / 16 / 32 KBytes)
FFDFh
FFE0h
C000h
E000h
16 KBytes
Interrupt & Reset Vectors
(See Table 4)
8 KBytes
4 KBytes
FFFFh
F000h
FFDFh
Table 5.
Interrupt vector map
Vector address
FFE0h-FFEDh
FFEEh-FFEFh
FFF0h-FFF1h
FFF2h-FFF3h
FFF4h-FFF5h
FFF6h-FFF7h
FFF8h-FFF9h
FFFAh-FFFBh
FFFCh-FFFDh
FFFEh-FFFFh
Description
Reserved area
Masked
Remarks
Exit from Halt
USB interrupt vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
None
None
Internal interrupt
Internal interrupt
Internal interrupt
Internal interrupt
External interrupt
External interrupts
Internal interrupt
CPU interrupt
No
No
SCI interrupt vector
I²C interrupt vector
No
TIMER interrupt vector
No
IT1 to IT8 interrupt vector
USB End Suspend mode interrupt vector
Flash start programming interrupt vector
TRAP (software) interrupt vector
RESET vector
Yes
Yes
Yes
No
Yes
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Register and memory map
ST7263Bxx
Remarks
Table 6.
Address
Hardware register memory map
Reset
status
Block
Register label
Register name
0000h
0001h
PADR
Port A Data register
00h
R/W
Port A
PADDR
Port A Data Direction register
00h
R/W
0002h
0003h
PBDR
Port B Data register
00h
00h
R/W
R/W
Port B
Port C
Port D
PBDDR
Port B Data Direction register
0004h
0005h
PCDR
Port C Data register
1111 x000b R/W
1111 x000b R/W
PCDDR
Port C Data Direction register
0006h
0007h
PDDR
Port D Data register
00h
00h
R/W
R/W
PDDDR
Port D Data Direction register
0008h
0009h
ITC
ITIFRE
MISCR
Interrupt register
00h
00h
R/W
R/W
MISC
Miscellaneous register
000Ah
000Bh
ADCDR
ADC Data register
00h
00h
Read only
R/W
ADC
ADCCSR
ADC control Status register
000Ch
WDG
WDGCR
Watchdog Control register
Reserved (4 bytes)
7Fh
R/W
000Dhto
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
TCR2
Timer Control register 2
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
TCR1
Timer Control register 1
R/W
TCSR
Timer Control/Status register
R/W
TIC1HR
TIC1LR
TOC1HR
TOC1LR
TCHR
Timer input Capture High register 1
Timer input Capture Low register 1
Timer output Compare High register 1
Timer output Compare Low register 1
Timer Counter High register
Read only
Read only
R/W
R/W
TIM
Read only
R/W
TCLR
Timer Counter Low register
TACHR
TACLR
TIC2HR
TIC2LR
TOC2HR
TOC2LR
Timer Alternate Counter High register
Timer Alternate Counter Low register
Timer input Capture High register 2
Timer input Capture Low register 2
Timer output Compare High register 2
Timer output Compare Low register 2
Read only
R/W
Read only
Read only
R/W
R/W
0020h
0021h
0022h
0023h
0024h
SCISR
SCI Status register
SCI Data register
C0h
xxh
00h
Read only
R/W
SCIDR
SCI
SCIBRR
SCICR1
SCICR2
SCI Baud Rate register
SCI Control register 1
SCI Control register 2
R/W
x000 0000b R/W
00h R/W
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Register and memory map
Table 6.
Address
Hardware register memory map (continued)
Reset
Block
Register label
Register name
Remarks
status
0025h
0026h
0027h
0028h
0029h
002Ah
USBPIDR
USB PID register
x0h
Read only
R/W
USBDMAR
USBIDR
USB DMA address register
USB Interrupt/DMA register
USB Interrupt Status register
USB Interrupt Mask register
USB Control register
xxh
x0h
00h
00h
06h
00h
R/W
USBISTR
R/W
USBIMR
R/W
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
R/W
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
USB
USB Device Address register
USB Endpoint 0 register A
USB Endpoint 0 register B
USB Endpoint 1 register A
USB Endpoint 1 register B
USB Endpoint 2 register A
USB Endpoint 2 register B
R/W
0000 xxxxb R/W
80h R/W
0000 xxxxb R/W
0000 xxxxb R/W
0000 xxxxb R/W
0000 xxxxb R/W
0032h to
0036h
Reserved (5 bytes)
0032h
0036h
Reserved (5 Bytes)
0037h
0038h
Flash
Reserved (1 byte)
I2CDR
FCSR
Flash Control /Status register
00h
R/W
R/W
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
I²C Data register
00h
-
Reserved
I2COAR
I2CCCR
I2CSR2
I2CSR1
I2CCR
I²C (7 Bits) Slave Address register
I²C Clock Control register
I²C 2nd Status register
I²C 1st Status register
I²C Control register
00h
00h
00h
00h
00h
R/W
I²C
R/W
Read only
Read only
R/W
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Flash program memory
ST7263Bxx
4
Flash program memory
4.1
Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external V supply.
PP
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
Main features
●
3 Flash programming modes:
–
–
–
Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
IAP (in-application programming). In this mode, all sectors except Sector 0, can be
programmed or erased without removing the device from the application board
and while the application is running.
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
●
Readout protection
Register access security system (RASS) to prevent accidental programming or erasing
4.3
Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Table 7). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 8). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 7.
Sectors available in Flash devices
Flash size (Kbytes)
Available sectors
4
8
Sector 0
Sectors 0,1
Sectors 0,1, 2
> 8
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Flash program memory
4.3.1
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Readout protection selection depends on the device type:
●
In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
In ROM devices it is enabled by mask option specified in the Option List.
●
Figure 8.
Memory map and sector address
4K
8K
10K
16K
24K
32K
48K
60K
FLASH
MEMORY SIZE
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
SECTOR 2
52 Kbytes
2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
4.4
ICC interface
ICC (In-circuit communication) needs a minimum of four and up to six pins to be connected
to the programming tool (see Figure 9). These pins are:
●
●
●
●
●
●
●
RESET: device reset
: device power supply ground
V
SS
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/V : programming voltage
PP
OSC1(or OSCIN): main clock input for external source (optional)
V
: application board power supply (see Figure 9, Note 3)
DD
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Flash program memory
Figure 9.
ST7263Bxx
Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
APPLICATION BOARD
ICC CONNECTOR
(See Note 3)
OPTIONAL
HE10 CONNECTOR TYPE
9
7
5
6
3
1
2
(See Note 4)
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
See Note 1
APPLICATION
I/O
ST7
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in
progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by
the application, isolation such as a serial resistor has to implemented in case another device forces the
signal. Refer to the Programming Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts
between the programming tool and the application reset circuit if it drives more than 5mA at high level
(push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET
circuit in this case. When using a classical RC network with R > 1K or a reset management IC with open
drain output and pull-up resistor > 1K, no additional components are needed. In all cases the user must
ensure that no external reset is generated by the application during the ICC session.
3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be
connected when using most ST Programming Tools (it is used to monitor the application power supply).
Please refer to the Programming Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-
oscillator capability need to have OSC2 grounded in this case.
4.5
ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 9). For more details on the pin locations, refer
to the device pinout description.
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Flash program memory
4.6
IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored, etc.). For example, it is
possible to download code from the SCI or other type of serial interface and program it in the
Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is
write/erase protected to allow recovery in case errors occur during the programming
operation.
4.7
4.8
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
Register description
Flash Control/status register (FCSR)
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
Reset value: 0000 0000 (00h)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Read/write
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Central processing unit
ST7263Bxx
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2
Main features
●
●
●
●
●
●
●
●
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
5.3
CPU registers
The six CPU registers shown in Figure are not present in the memory mapping and are
accessed by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The Cross-Assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
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Central processing unit
Condition Code register (CC)
Reset value: 111x1xxx
7
1
6
1
5
1
4
3
I
2
1
Z
0
H
N
C
Read/write
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Bit 3 I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
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Central processing unit
ST7263Bxx
Bit 2 N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a
logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and
JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
Stack Pointer (SP)
Reset value: 017Fh
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
0
6
5
4
3
2
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 10).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
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Central processing unit
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 10.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 10. Stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 017Fh
Stack Higher Address = 017Fh
0100h
Stack Lower Address =
Figure 11. CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H
X
I
N
X
Z
X
C
X
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE =
8
1
1
15
7
0
RESET VALUE = STACK HIGHER ADDRESS
X = undefined value
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Reset and clock management
ST7263Bxx
6
Reset and clock management
6.1
Reset
The Reset procedure is used to provide an orderly software start-up or to exit low power
modes.
Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an
external reset at the RESET pin.
A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to
be loaded into the PC and with program execution starting from this point.
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator
becomes active.
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
6.1.1
Low voltage detector (LVD)
Low voltage reset circuitry generates a reset when V is:
DD
●
Below V when V is rising
IT+ DD
●
Below V when V is falling
IT-
DD
During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.
It is recommended to make sure that the V supply voltage rises monotonously when the
DD
device is exiting from Reset, to ensure the application functions properly.
6.1.2
6.1.3
Watchdog reset
When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset
other devices in the same way as the low voltage reset (Figure 12).
External reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 15, the RESET signal must stay low for a minimum of one and a half
CPU clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
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Reset and clock management
Figure 12. Low voltage detector functional diagram
RESET
LOW VOLTAGE
VDD
DETECTOR
INTERNAL
RESET
FROM
WATCHDOG
RESET
Figure 13. Low Voltage Reset signal output
V
IT+
V
IT-
V
DD
RESET
1. Hysteresis (VIT+-VIT-) = Vhys
Figure 14. Temporization timing diagram after an internal Reset
V
IT+
V
DD
Temporization (4096 CPU clock cycles)
$FFFE
Addresses
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Reset and clock management
Figure 15. Reset timing diagram
ST7263Bxx
t
DDR
V
DD
OSCIN
t
OXOV
f
CPU
FFFF
FFFE
PC
RESET
4096 CPU
CLOCK
CYCLES
DELAY
WATCHDOG RESET
1. Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys
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Reset and clock management
6.2
Clock system
6.2.1
General description
The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive
the internal oscillator. The internal clock (f ) is derived from the external oscillator
CPU
frequency (f
), which is divided by 3 (and by 2 or 4 for USB, depending on the external
OSC
clock used). The internal clock is further divided by 2 by setting the SMS bit in the
miscellaneous register.
Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be
used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for
the USB (refer to Figure 18).
The internal clock signal (f
) is also routed to the on-chip peripherals. The CPU clock
CPU
signal consists of a square wave with a duty cycle of 50%.
The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or
ceramic resonator in the frequency range specified for f . The circuit shown in Figure 17 is
osc
recommended when using a crystal, and Table 8 lists the recommended capacitance. The
crystal and associated components should be mounted as close as possible to the input
pins in order to minimize output distortion and start-up stabilization time.
Table 8.
Recommended Values for 24 MHz crystal resonator
Recommended capacitance and resistance
(1)
RSMAX
20 Ω
56pF
25 Ω
47pF
70 Ω
22pF
COSCIN
COSCOUT
56pF
47pF
22pF
R
1-10 MΩ
1-10 MΩ
1-10 MΩ
P
1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
6.2.2
External clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected,
as shown on Figure 16. The t specifications do not apply when using an external clock
OXOV
input. The equivalent specification of the external clock source should be used instead of
(see Table 62: Control timing characteristics).
t
OXOV
Figure 16. External clock source connections
OSCOUT
NC
OSCIN
EXTERNAL
CLOCK
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Reset and clock management
Figure 17. Crystal/ceramic resonator
ST7263Bxx
OSCIN
OSCOUT
RP
COSCIN
COSCOUT
Figure 18. Clock block diagram
8, 4 or 2 MHz
CPU and
peripherals)
0
1
%2
%3
SMS
1
6 MHz (USB)
%2
24 or
12 MHz
Crystal
0
%2
OSC24/12
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Interrupts
7
Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in Table 9 and a non-maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 19.
The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed when they are enabled (see external
interrupts subsection).
When an interrupt has to be serviced:
●
●
●
●
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 9 for vector
addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case several interrupts are simultaneously pending, a hardware priority defines which
one will be serviced first (see Table 9).
Non-maskable software interrupts
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It will be serviced according to the flowchart on Figure 19.
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to
the “Exit from HALT“ column in Table 9).
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising
edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)
can generate an interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE
register and if the I bit of the CC is reset.
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Interrupts
ST7263Bxx
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
The I bit of the CC register is cleared.
●
The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by one of the two following operations:
●
Writing “0” to the corresponding bit in the status register.
●
Accessing the status register while the flag is set followed by a read or write of an
associated register.
Note:
1
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be
enabled) will therefore be lost if the clear sequence is executed.
2
3
All interrupts allow the processor to leave the Wait low power mode.
Exit from Halt mode may only be triggered by an external interrupt on one of the ITi ports
(PA4-PA7 and PB4-PB7), an end suspend mode interrupt coming from USB peripheral, or a
reset.
Figure 19. Interrupt processing flowchart
FROM RESET
N
BIT I SET
N
Y
INTERRUPT
Y
FETCH NEXT INSTRUCTION
N
IRET
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
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Table 9.
Interrupts
Interrupt mapping
Exit
from
Halt
Register Priority
Vector
address
N° Source block
Description
label
order
RESET
TRAP
FLASH
USB
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
N/A
Software interrupt
Highest
Priority
Flash Start Programming interrupt
End Suspend mode
yes
ISTR
ITRFRE
TIMSR
I²CSR1
I²CSR2
SCISR
ISTR
yes
1
2
ITi
External interrupts
TIMER
Timer Peripheral interrupts
Lowest
Priority
3
I²C
I²C Peripheral interrupts
FFF2h-FFF3h
no
4
5
SCI
SCI Peripheral interrupts
USB Peripheral interrupts
FFF0h-FFF1h
FFEEh-FFEFh
USB
7.1
Interrupt register (ITRFRE)
Address: 0008h
Reset value: 0000 0000 (00h)
7
0
IT8E
IT7E
IT6E
IT5E
IT4E
IT3E
IT2E
IT1E
Read/write
[7:0] TiE (i=1 to 8). Interrupt Enable Control Bits.
If an ITiE bit is set, the corresponding interrupt is generated when
●
A rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6
Or a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8
●
No interrupt is generated elsewhere.
Note: Analog input must be disabled for interrupts coming from port B.
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Power saving modes
ST7263Bxx
8
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, two
main power saving modes are implemented in the ST7.
After a Reset, the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided by 3 (f
).
CPU
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
8.2
Halt mode
The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by
executing the Halt instruction. The internal oscillator is then turned off, causing all internal
processing to be stopped, including the operation of the on-chip peripherals.
When entering Halt mode, the I bit in the Condition Code register is cleared. Thus, all
external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs,
the CPU clock becomes active.
The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end
suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then
turned on and a stabilization time is provided before releasing CPU operation. The
stabilization time is 4096 CPU clock cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes
it up or by fetching the reset vector if a reset wakes it up.
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Power saving modes
Figure 20. Halt mode flowchart
HALT INSTRUCTION
OSCILLATOR
OFF
PERIPH. CLOCK
CPU CLOCK
I-BIT
OFF
OFF
CLEARED
N
RESET
N
EXTERNAL
Y
INTERRUPT*
Y
OSCILLATOR
ON
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
SET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt
routine and cleared when the CC register is popped.
8.3
8.4
Slow mode
In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the
Miscellaneous register. The CPU and peripherals are clocked at this lower frequency. Slow
mode is used to reduce power consumption, and enables the user to adapt the clock
frequency to the available supply voltage.
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the “WFI” ST7 software instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
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Power saving modes
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The MCU will remain in Wait mode until a Reset or an interrupt occurs, causing it to wake
up. Refer to Figure 21.
Related documentation
AN 980: ST7 Keypad Decoding Techniques, Implementing Wakeup on Keystroke
AN1014: How to Minimize the ST7 Power Consumption
AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode
Figure 21. Wait mode flowchart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
OFF
CLEARED
N
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
ON
ON
ON
PERIPH. CLOCK
CPU CLOCK
I-BIT
SET
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt
routine and cleared when the CC register is popped.
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I/O ports
9
I/O ports
9.1
Introduction
The I/O ports offer different functional modes:
●
●
●
●
Transfer of data through digital inputs and outputs and for specific pins
Analog signal input (ADC)
Alternate signal input/output for the on-chip peripherals
External interrupt generation
An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital
input (with or without interrupt generation) or a digital output.
9.2
Functional description
Each port is associated to 2 main registers:
●
Data register (DR)
●
Data Direction register (DDR)
Each I/O pin may be programmed using the corresponding register bits in DDR register: bit
X corresponding to pin X of the port. The same correspondence is used for the DR register.
Table 10. I/O pin functions
DDR
Mode
0
1
Input
Output
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
All the inputs are triggered by a Schmitt trigger.
Note:
1
2
When switching from input mode to output mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured as an input with interrupt, an event on this I/O can generate an
external interrupt request to the CPU. The interrupt sensitivity is given independently
according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an interrupt request.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see interrupts
section). If more than one input pin is selected simultaneously as an interrupt source, this is
logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are
masked.
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I/O ports
ST7263Bxx
Output mode
The pin is configured in output mode by setting the corresponding DDR register bit (see
Table 7).
In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin
through the latch. Therefore, the previously saved value is restored when the DR register is
read.
Note:
The interrupt function is disabled in this mode.
Digital alternate function
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over standard I/O programming. When the
signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output
mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input
mode. In this case, the pin’s state is also digitally readable by addressing the DR register.
Note:
1
Input pull-up configuration can cause an unexpected value at the input of the alternate
peripheral input.
2
When the on-chip peripheral uses a pin as input and output, this pin must be configured as
an input (DDR = 0).
Caution:
The alternate function must not be activated as long as the pin is configured as an input with
interrupt in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input the I/O must be configured as a floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
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I/O ports
9.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR register
and specific feature of the I/O port such as ADC input or true open drain.
9.3.1
Port A
Table 11. Port A0, A3, A4, A5, A6, A7 description
I/Os
Alternate function
Signal Condition
PORT A
Input(1)
Output
push-pull
PA0
PA3
with pull-up
MCO (Main Clock output) MCO = 1 (MISCR)
CC1 =1
Timer EXTCLK
with pull-up
with pull-up
push-pull
CC0 = 1 (Timer CR2)
Timer ICAP1
PA4
Push-pull
Push-pull
Push-pull
Push-pull
IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
Timer ICAP2
PA5
with pull-up
with pull-up
with pull-up
IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
Timer OCMP1
IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
Timer OCMP2 OC2E = 1
IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
OC1E = 1
PA6(2)
PA7
1. Reset state.
2. Not available on SO24
Figure 22. PA0, PA3, PA4, PA5, PA6, PA7 and PD[7:4] configuration
ALTERNATE ENABLE
1
0
V
DD
ALTERNATE
OUTPUT
P-BUFFER
VDD
DR
PULL-UP
LATCH
ALTERNATE ENABLE
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DIODES
1
0
DR SEL
ALTERNATE ENABLE
V
SS
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
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I/O ports
ST7263Bxx
(1)
Table 12. PA1, PA2 description
I / O
Alternate function
Signal Condition
Port A
Input1
Output
PA1
without pull-up
without pull-up
Very high current open drain
Very high current open drain
SDA (I²C data)
SCL (I²C clock)
I²C enable
I²C enable
PA2
1. Reset state.
Figure 23. PA1, PA2 configuration
LATCH
DDR
LATCH
PAD
DDR SEL
N-BUFFER
DR SEL
1
0
ALTERNATE ENABLE
V
SS
CMOS SCHMITT TRIGGER
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I/O ports
9.3.2
Port B
Table 13. Port B description
I/O
Alternate function
Port B
Input(1)
without pull-up
Output
push-pull
Signal
Condition
CH[3:0] = 000
(ADCCSR)
PB0
PB1
Analog input (ADC)
CH[3:0] = 001
(ADCCSR)
Analog input (ADC)
without pull-up
push-pull
USBOE (USB output
enable)(2)
USBOE =1 (MISCR)
CH[3:0]= 010
(ADCCSR)
PB2
PB3
without pull-up
without pull-up
push-pull
push-pull
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
CH[3:0]= 011
(ADCCSR)
CH[3:0]= 100
(ADCCSR)
PB4
PB5
PB6
PB7
without pull-up
without pull-up
without pull-up
without pull-up
push-pull
push-pull
push-pull
push-pull
IT5 Schmitt triggered
input
IT5E = 1 (ITIFRE)
CH[3:0]= 101
(ADCCSR)
Analog input (ADC)
IT6 Schmitt triggered
input
IT6E = 1 (ITIFRE)
CH[3:0]= 110
(ADCCSR)
Analog input (ADC)
IT7 Schmitt triggered
input
IT7E = 1 (ITIFRE)
CH[3:0]= 111
(ADCCSR)
Analog input (ADC)
IT8 Schmitt triggered
input
IT8E = 1 (ITIFRE)
1. Reset State
2. On SO24 only
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I/O ports
ST7263Bxx
Figure 24. Port B and D[3:0] configuration
ALTERNATE ENABLE
VDD
ALTERNATE
OUTPUT
1
0
V
DD
P-BUFFER
DR
LATCH
ALTERNATE ENABLE
DDR
PAD
LATCH
ANALOG ENABLE
(ADC)
DDR SEL
ANALOG
SWITCH
DIODES
N-BUFFER
1
DR SEL
ALTERNATE ENABLE
DIGITAL ENABLE
VSS
0
ALTERNATE INPUT
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I/O ports
9.3.3
Port C
Table 14. Port C description
I / O
Alternate function
Port C
Input(1)
Output
Signal
Condition
PC0
PC1
with pull-up
with pull-up
push-pull
push-pull
RDI (SCI input)
TDO (SCI output)
SCI enable
USBOE =1
(MISCR)
USBOE (USB output
enable)
PC2(2)
with pull-up
push-pull
1. Reset state
2. Not available on SO24
Figure 25. Port C configuration
ALTERNATE ENABLE
VDD
ALTERNATE
OUTPUT
0
P-BUFFER
V
DD
DR
PULL-UP
LATCH
ALTERNATE ENABLE
DDR
PAD
LATCH
DDR SEL
N-BUFFER
DIODES
1
0
DR SEL
ALTERNATE ENABLE
VSS
ALTERNATE INPUT
CMOS SCHMITT TRIGGER
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I/O ports
ST7263Bxx
9.3.4
Port D
Table 15. Port D description
I / O
Alternate function
Port D
Input(1)
Output
Signal
Condition
CH[3:0] = 1000
(ADCCSR)
PD0
PD1
PD2
PD3
without pull-up push-pull
without pull-up push-pull
without pull-up push-pull
without pull-up push-pull
Analog input (ADC)
CH[3:0] = 1001
(ADCCSR)
Analog input (ADC)
Analog input (ADC)
Analog input (ADC)
CH[3:0] = 1010
(ADCCSR)
CH[3:0] = 1011
(ADCCSR)
PD4
with pull-up
with pull-up
with pull-up
with pull-up
push-pull
push-pull
push-pull
push-pull
PD5
PD6
PD7
1. Reset state
9.3.5
Register description
DATA registers (PxDR)
Address
Port A Data register (PADR): 0000h
Port B Data register (PBDR): 0002h
Port C Data register (PCDR): 0004h
Port D Data register (PDDR): 0006h
Reset value
Port A: 0000 0000 (00h)
Port B: 0000 0000 (00h)
Port C: 1111 x000 (FXh)
Port D: 0000 0000 (00h)
Note:
Note:
For Port C, unused bits (7-3) are not accessible.
The DR register has a specific behavior according to the selected input/output configuration.
Writing the DR register is always taken into account even if the pin is configured as an input.
Reading the DR register returns either the DR register latch content (pin configured as
output) or the digital value applied to the I/O pin (pin configured as input).
When using open-drain I/Os in output configuration, the value read in DR is the digital value
applied to the I/Opin.
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I/O ports
.
7
0
D7
D6
D5
D4
Read/write
D3
D2
D1
D0
[7:0] D[7:0] Data register 8 bits.
Data Direction register (PxDDR)
Address
Port A Data Direction register (PADDR): 0001h
Port B Data Direction register (PBDDR): 0003h
Port C Data Direction register (PCDDR): 0005h
Port D Data Direction register (PDDDR): 0007h
Reset value
Port A: 0000 0000 (00h)
Port B: 0000 0000 (00h)
Port C: 1111 x000 (FXh)
Port D: 0000 0000 (00h)
Note:
For Port C, unused bits (7-3) are not accessible
.
7
0
DD7
DD6
DD5
DD4
Read/write
DD3
DD2
DD1
DD0
[7:0]D D[7:0] Data Direction register 8 bits.
The DDR register gives the input/output direction configuration of the pins. Each bit
is set and cleared by software.
0: input mode
1: output mode
Table 16. I/O ports register map
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
00
01
02
03
04
05
06
07
PADR
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
PADDR
PBDR
PBDDR
PCDR
PCDDR
PDDR
PDDDR
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9.3.6
Related documentation
2
AN1045: S/W implementation of I C bus master
AN1048: Software LCD driver
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Miscellaneous register
10
Miscellaneous register
Miscellaneous register (MISCR)
Address: 0009h
Reset value: 0000 0000 (00h)
7
0
-
-
-
-
-
SMS
USBOE
MCO
Read/write
[7:3] Reserved
2
SMS Slow mode Select.
This bit is set by software and only cleared by hardware after a reset. If this
bit is set, it enables the use of an internal divide-by-2 clock divider (refer to
Figure 18 on page 36). The SMS bit has no effect on the USB frequency.
0: Divide-by-2 disabled and CPU clock frequency is standard
1: Divide-by-2 enabled and CPU clock frequency is halved.
1
0
USBOE USB enable.
If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable
signal (at “1” when the ST7 USB is transmitting data).
Unused bits 7-4 are set.
MCO Main Clock Out selection
This bit enables the MCO alternate function on the PA0 I/O port. It is set and
cleared by software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O port)
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On-chip peripherals
ST7263Bxx
11
On-chip peripherals
11.1
Watchdog timer (WDG)
11.1.1
Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
11.1.2
11.1.3
Main features
●
●
●
●
●
Programmable free-running counter (64 increments of 49,152 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit reaches zero
Optional reset on HALT instruction (configurable by option byte)
Hardware Watchdog selectable by option byte.
Functional description
The counter value stored in the CR register (bits T6:T0), is decremented every 49,152
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle by driving low the reset
pin for t
(see Table 72).
W(RSTL)out
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This down counter is free-running: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 17):
●
●
●
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T5:T0 bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
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On-chip peripherals
Figure 26. Watchdog block diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
WDGA T6
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
fCPU
÷49152
a
Table 17. Watchdog timing (f
= 8 MHz)
CPU
CR register initial value
WDG timeout period (ms)
Max
Min
FFh
C0h
393.216
6.144
Note:
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
11.1.4
Software Watchdog option
If Software Watchdog is selected by option byte, the watchdog is disabled following a reset.
Once activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
11.1.5
11.1.6
Hardware Watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Low power modes
WAIT instruction
No effect on Watchdog.
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HALT instruction
If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes
an immediate reset generation if the Watchdog is activated (WDGA bit is set).
Using Halt mode with the WDG (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the
WDG stops counting and is no longer able to generate a reset until the microcontroller
receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a
reset is generated, the WDG is disabled (reset state).
Recommendations:
●
●
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
11.1.7
Interrupts
None.
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11.1.8
Register description
Control register (CR)
Reset value: 0111 1111 (7Fh)
7
0
WDGA
T6
T5
T4
T3
T2
T1
T0
Read/write
7 WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA
= 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
[6:0] T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset is produced when it rolls over
from 40h to 3Fh (T6 becomes cleared).
Table 18. Watchdog timer register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0Ch
Reset
value
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11.2
16-bit timer
11.2.1
Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after a MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
11.2.2
Main features
●
●
●
Programmable prescaler: f
divided by 2, 4 or 8
CPU
Overflow status flag and maskable interrupt
External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
●
1 or 2 output Compare functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated programmable signals
2 dedicated status flags
1 dedicated maskable interrupt
●
1 or 2 input Capture functions each with:
–
–
–
–
2 dedicated 16-bit registers
2 dedicated active edge selection signals
2 dedicated status flags
1 dedicated maskable interrupt
●
●
●
●
Pulse width modulation mode (PWM)
One Pulse mode
Reduced Power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 27.
Note:
Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the
device pin out description.
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
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11.2.3
Functional description
Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
●
●
Counter register (CR)
Counter High register (CHR) is the most significant byte (MSB).
Counter Low register (CLR) is the least significant byte (LSB).
Alternate Counter register (ACR)
Alternate Counter High register (ACHR) is the most significant byte (MSB).
Alternate Counter Low register (ACLR) is the least significant byte (LSB).
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 24. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
/2, f
/4, f
/8 or an external frequency.
CPU
CPU
CPU
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On-chip peripherals
Figure 27. Timer block diagram
ST7263Bxx
ST7 INTERNAL BUS
f
CPU
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control register 1) CR1
(Control register 2) CR2
(See note)
TIMER INTERRUPT
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device
Interrupt Vector Table).
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Figure 28. 16-bit read sequence (from either the Counter register or the Alternate
Counter register)
Beginning of the sequence
Read
MS Byte
LS Byte
is buffered
At t0
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +Δt
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
The TOF bit of the SR register is set.
A timer interrupt is generated if:
●
–
–
TOIE bit of the CR1 register is set and
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note:
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
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A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 29. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 30. Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 31. Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
1. The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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On-chip peripherals
Input Capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see Figure 32).
Table 19. IC/R register
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the input capture function select the following in the CR2 register:
1. Select the timer clock (CC[1:0]) (see Table 24).
2. Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
3. Select the following in the CR1 register:
a) Set the ICIE bit to generate an interrupt after an input capture coming from either
the ICAP1 pin or the ICAP2 pin
b) Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without
interrupt if this configuration is available).
When an input capture occurs:
●
ICFi bit is set.
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 33).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
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Note:
1
2
3
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
The two input capture functions can be used together even if the timer also uses the two
output compare functions.
4
5
In One Pulse mode and PWM mode only input Capture 2 can be used.
The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6
The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 32. Input Capture block diagram
ICAP1
pin
(Control register 1) CR1
IEDG1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
ICAP2
pin
(Status register) SR
ICF1
ICF2
0
0
0
IC2R register
IC1R register
(Control register 2) CR2
CC0 IEDG2
16-BIT
16-BIT FREE RUNNING
COUNTER
CC1
Figure 33. Input Capture timing diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
1. The rising edge is the active edge.
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On-chip peripherals
Output Compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the output Compare register and the free running counter,
the output compare function:
●
●
●
Assigns pins with a programmable value if the OCiE bit is set
Sets a flag in the status register
Generates an interrupt if enabled
Two 16-bit registers output Compare register 1 (OC1R) and output Compare register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
Table 20. OC/R register
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/
Procedure
).
CC[1:0]
To use the output compare function, select the following in the CR2 register:
1. Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
2. Select the timer clock (CC[1:0]) (see Table 24).
3. Select the following in the CR1 register:
a) Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
b) Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCiR register and CR register:
●
●
●
OCFi bit is set.
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Δt * fCPU
Δ OCiR =
PRESC
Where:
Δt = Output compare period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
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PRESC= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24)
If the timer clock is an external clock, the formula is:
Δ OCiR = Δt * fEXT
Where:
Δt = Output compare period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
●
Write to the OCiHR register (further compares are inhibited).
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
●
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
Note:
1
2
3
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 35 on page 67 for an example with f
/2 and
CPU
Figure 36 on page 67 for an example with f
PWM mode.
/4). This behavior is the same in OPM or
CPU
4
5
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced Compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both One Pulse mode and PWM mode.
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Figure 34. Output Compare block diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control register 2) CR2
16-bit
(Control register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R register
OCF1
OCF2
0
0
0
OC2R register
(Status register) SR
Figure 35. Output Compare timing diagram, f
= f /2
cpu
timer
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
Figure 36. Output Compare timing diagram, f
= f
/4
CPU
timeR
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi = 1)
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One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The One Pulse mode uses the input Capture1 function and the output Compare1 function.
Procedure
To use One Pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
2. Select the following in the CR1 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the output Compare 1
function.
–
–
Set the OPM bit.
Select the timer clock CC[1:0] (see Table 24).
Figure 37. One Pulse mode cycle
ICR1 = Counter
OCMP1 = OLVL2
When
event occurs
on ICAP1
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
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The OC1R register value required for a specific timing application can be calculated using
the following formula:
t * fCPU
- 5
OCiR Value =
PRESC
Where:
t = Pulse period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
PRESC= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 24)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t = Pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (See Figure 38).
Note:
1
2
The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate
an output Compare interrupt.
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
4
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the One Pulse mode.
Figure 38. One Pulse mode timing example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
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Figure 39. Pulse Width modulation mode timing with 2 output Compare functions
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
On timers with only one output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete output Compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column.
3. Select the following in the CR1 register:
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
4. Select the following in the CR2 register:
–
–
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
Set the PWM bit.
Select the timer clock (CC[1:0]) (see Table 24).
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Figure 40. Pulse width modulation cycle
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
OCMP1 = OLVL2
When
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
t * fCPU
- 5
OCiR Value =
PRESC
Where:
t = Signal or pulse period (in seconds)
f
= CPU clock frequency (in hertz)
CPU
PRESC= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 24)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
t = Signal or pulse period (in seconds)
f
= External timer clock frequency (in hertz)
EXT
The output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 39)
Note:
1
2
3
4
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5
When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
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11.2.4
Low power modes
a
Table 21. Low power modes
Mode
Description
WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from Wait mode.
16-bit Timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with “exit from Halt mode”
capability or from the counter reset value when the MCU is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with “exit from Halt
mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
11.2.5
Interrupts
The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts
chapter). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
Table 22. Interrupts
Interrupt Event
Enable Control
bit
Exit from
Wait
Exit from
Halt
Event flag
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
OCF1
OCF2
TOF
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Yes
No
OCIE
TOIE
11.2.6
Summary of timer modes
Table 23. Summary of timer modes
Timer Resources
Modes
Input
Output
Compare 1
Output
Compare 2
Input Capture 2
Capture 1
Input Capture (1 and/or 2)
Yes
Yes
Yes
No
Yes
Output Compare (1 and/or 2)
One Pulse mode
No
PWM mode
Not recommended(1)
Not recommended(3)
Partially(2)
No
1. See note 4 in Section : One Pulse mode.
2. See note 5 in Section : One Pulse mode.
3. See note 4 in Section : Pulse width modulation mode.
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11.2.7
Register description
Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Reset value: 0000 0000 (00h)
7
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Read/write
7
ICIE input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register
is set.
6
OCIE output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR
register is set.
5
4
TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
FOLV2 Forced output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison.
3
FOLV1 Forced output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison.
2
1
OLVL2 output Level 2.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs
with the OC2R register and OCxE is set in the CR2 register. This value is copied
to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.
IEDG1 input Edge 1.
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0
OLVL1 output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.
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Control register 2 (CR2)
Reset value: 0000 0000 (00h)
7
0
OC1E
OC2E
OPM
PWM
CC1
Read/write
CC0
IEDG2
EXEDG
7
6
OC1E output Compare 1 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1
in output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).
Whatever the value of the OC1E bit, the output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
OC2E output Compare 2 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2
in output Compare mode). Whatever the value of the OC2E bit, the output
Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
5
4
OPM One Pulse mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on
the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal;
the length of the pulse depends on the value of OC1R register; the period
depends on the value of OC2R register.
[3:2] CC[1:0] Clock Control.
The timer clock mode depends on these bits (see Table 24).
If the external clock pin is not available, programming the external clock
configuration stops the counter.
1
0
IEDG2 input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
EXEDG External Clock Edge.
This bit determines which type of level transition on the external clock pin
EXTCLK will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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CC0
Table 24. Clock Control bits
Timer clock
CC1
f
f
f
CPU / 4
CPU / 2
CPU / 8
0
1
0
1
0
1
External Clock (where available)
Control/status register (CSR)
Reset value: xxxx x0xx (xxh)
7
6
5
4
3
0
ICF1
OCF1
TOF
ICF2
OCF2
TIMD
0
0
Read only
Read/write
7 ICF1 input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
6 OCF1 output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
5 TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1:The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
4 ICF2 input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the
SR register, then read or write the low byte of the IC2R (IC2LR) register.
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3 OCF2 output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC2R (OC2LR) register.
2 TIMD Timer disable.
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce
power consumption. Access to the timer registers is still available, allowing the
timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
[1:0] Reserved, must be kept cleared.
Input Capture 1 High register (IC1HR)
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read only
Input Capture 1 Low register (IC1LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read only
Output Compare 1 High register (OC1HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/write
Output Compare 1 Low register (OC1LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
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7
0
MSB
LSB
Read/write
Output Compare 2 High register (OC2HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/write
Output Compare 2 Low register (OC2LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read/write
Counter High register (CHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7
0
MSB
LSB
Read only
Counter Low register (CLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
7
0
MSB
LSB
Read only
Alternate Counter High register (ACHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
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7
0
MSB
LSB
Read only
Alternate Counter Low register (ACLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
7
0
MSB
LSB
Read only
Input Capture 2 High register (IC2HR)
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input Capture 2 event).
7
0
MSB
LSB
Read only
Input Capture 2 Low register (IC2LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input Capture 2 event).
7
0
MSB
LSB
Read only
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Table 25. 16-bit timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
CR2
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Reset value
CR1
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Reset value
CSR
ICF1
0
OCF1
0
TOF
0
ICF2
0
OCF2
0
TIMD
0
0
0
0
0
Reset value
IC1HR
MSB
MSB
LSB
LSB
Reset value
IC1LR
Reset value
OC1HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
OC1LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
CHR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
1
LSB
1
Reset value
CLR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
0
LSB
0
Reset value
ACHR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
1
LSB
1
Reset value
ACLR
MSB
1
-
1
-
1
-
1
-
1
-
1
-
0
LSB
0
Reset value
IC2HR
MSB
MSB
LSB
LSB
Reset value
IC2LR
Reset value
OC2HR
MSB
1
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
OC2LR
MSB
0
-
0
-
0
-
0
-
0
-
0
-
0
LSB
0
Reset value
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11.3
Serial communications interface (SCI)
11.3.1
Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
11.3.2
Main features
●
●
●
●
●
●
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Independently programmable transmit and receive baud rates up to 250K baud.
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and End of Transmission flags
Two receiver Wakeup modes:
– Address bit (MSB)
– Idle line
●
●
●
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and Receiver
Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
●
Six interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
– Parity error
●
●
Parity control:
– Transmits parity bit
– Checks parity of received data byte
Reduced power consumption mode
11.3.3
General description
The interface is externally connected to another device by two pins (see Figure 42):
●
TDO: Transmit Data output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●
RDI: Receive Data input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
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Through these pins, serial data is transmitted and received as frames comprising:
●
●
●
●
An Idle Line prior to transmission or reception
A start bit
A data word (8 or 9 bits) least significant bit first
A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
A conventional type for commonly-used baud rates.
●
Figure 41. SCI block diagram
Write
Read
(DATA REGISTER) DR
Received Data register (RDR)
Received Shift register
Transmit Data register (TDR)
TDO
Transmit Shift register
RDI
CR1
R8 T8 SCID
M WAKE PCE PS PIE
WAKE
UP
UNIT
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
CR2
SR
TIE TCIE RIE ILIE TE RE RWU SBK
TDRE TC RDRF IDLE OR NF FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
fCPU
/PR
/16
BRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
BAUD RATE GENERATOR
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11.3.4
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 41 It contains 6
dedicated registers:
●
●
●
Two control registers (SCICR1 & SCICR2)
A status register (SCISR)
A baud rate register (SCIBRR)
Refer to the register descriptions in Section 11.3.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 41).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 42. Word length programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Bit
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Next Data Frame
Data Frame
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
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Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character Transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 41).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3. Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame
as first transmission.
4. Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
●
●
●
The TDR register is empty.
The data transfer is beginning.
The next data can be written in the SCIDR register without overwriting the previous
data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CC register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC
bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CC
register.
Clearing the TC bit is performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note:
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 42).
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As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in
the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 41).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3. Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
●
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●
●
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When a idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CC register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
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When a overrun error occurs:
●
●
●
●
The OR bit is set.
The RDR content will not be lost.
The shift register will be overwritten.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CC register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●
●
●
The NF flag is set at the rising edge of the RDRF bit.
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid
frame is received.
Note:
If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Section .
Framing error
A framing error is detected when:
–
The stop bit is not recognized on reception at the expected time, following either a
de-synchronization or excessive noise.
–
A break is received.
When the framing error is detected:
–
–
–
the FE bit is set by hardware
Data is transferred from the Shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
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Baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
fCPU
fCPU
Rx =
Tx =
(16*PR)*RR
(16*PR)*TR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f
is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and
CPU
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Receiver muting and Wakeup feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●
By Idle Line detection if the WAKE bit is reset,
By Address Mark detection if the WAKE bit is set.
●
Receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes-up by Address Mark detection when it received a “1” as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution:
In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before
the write operation, the RWU bit will be set again by this write operation. Consequently the
address byte is lost and the SCI is not woken up from Mute mode.
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Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 26.
(1)
Table 26. Frame formats
M bit
PCE bit
SCI frame
0
0
1
1
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
1. SB = Start Bit, STB = Stop Bit, PB = Parity Bit
Note:
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd
parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register
and an interrupt is generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit
is be set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32 µs & 36 µs
respectively (the first sample starting ideally at 0 µs). But if the falling edge of the internal
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clock occurs just before the pin value changes, the samples would then be out of sync by
~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample + 4
µs for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
D
: Deviation due to transmitter error (Local oscillator error of the transmitter or the
TRA
transmitter is transmitting at a different baud rate).
●
●
D
D
: Error due to the baud rate quantisation of the receiver.
QUANT
: Deviation of the local oscillator of the receiver: This deviation can occur during
REC
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
D
: Deviation due to the transmission line (generally due to the transceivers)
TCL
All the deviations of the system should be added and compared to the SCI clock tolerance:
+ D + D + D < 3.75%
D
TRA
QUANT
REC
TCL
Noise error causes
See also description of Noise error in Section .
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as '1' and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a “1”.
2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a “1”.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
●
During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.
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Figure 43. Bit sampling in reception mode
RDI LINE
sampled values
10 11 12 13 14 15 16
Sample
clock
1
2
3
4
5
6
7
8
9
6/16
7/16
7/16
One bit time
11.3.5
Low power modes
Table 27. Low power modes
Mode
Description
No effect on SCI.
WAIT
HALT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is
exited.
11.3.6
Interrupts
Table 28. Interrupts
Interrupt event
Enable
Control
bit
Exit
from
Wait
Exit
from
Halt
Event flag
Transmit Data register Empty
Transmission Complete
Received Data Ready to be Read
Overrun Error Detected
Idle Line Detected
TDRE
TC
TIE
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
TCIE
RDRF
OR
RIE
IDLE
PE
ILIE
PIE
Parity Error
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
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11.3.7
Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
7
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PE
Read only
7 TDRE Transmit data register empty.
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIE bit=1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR
register followed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift register unless the TDRE bit is
cleared.
6 TC Transmission complete.
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by
a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
5 RDRF Received data ready flag.
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
4 IDLE Idle line detect.
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a
new idle line occurs).
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3 OR Overrun error.
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RDRF=1. An interrupt
is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will not be lost but the shift register
will be overwritten.
2 NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
1 FE Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being
transferred causes both frame error and overrun error, it will be transferred
and only the OR bit will be set.
0 PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register.
0: No parity error
1: Parity error
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Control register 1 (SCICR1)
Reset value: x000 0000 (x0h)
7
0
R8
T8
SCID
M
WAKE
Read/write
PCE
PS
PIE
7 R8 Receive data bit 8.
This bit is used to store the 9th bit of the received word when M=1.
6 T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
5 SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
4 M Word length.
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission
and reception).
3 WAKE Wakeup method.
This bit determines the SCI wakeup method, it is set or cleared by software.
0: Idle Line
1: Address Mark
2 PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
1 PS Parity selection.
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be selected
after the current byte.
0: Even parity
1: Odd parity
0 PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled.
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Control register 2 (SCICR2)
Reset value: 0000 0000 (00h)
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read/write
7 TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register
6 TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in the SCISR register
5 RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR
register
4 ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register.
3 TE Transmitter enable.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”)
sends a preamble (idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission
starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and
RE bits are both cleared (or if TE is never set).
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2 RE Receiver enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
1 RWU Receiver wakeup.
This bit determines if the SCI is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wakeup sequence is
recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the RWU bit), the SCI must
receive some data first, otherwise it cannot function in Mute mode with
wakeup by idle line detection.
0 SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a
BREAK word at the end of the current word.
Data register (SCIDR)
Reset value: Undefined
This register contains the received or transmitted data character, depending on whether it is
read from or written to.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Read/write
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 41).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 41).
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Baud Rate register (SCIBRR)
Reset value: 0000 0000 (00h)
7
0
SCP1
SCP0
SCT2
SCT1
Read/write
SCT0
SCR2
SCR1
SCR0
[7:6] SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges (see
Table 29).
[5:3] SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division
applied to the bus clock to yield the transmit rate clock (see Table 30).
[2:0] SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied
to the bus clock to yield the receive rate clock (see Table 31).
Table 29. Prescaling factors
PR prescaling factor
SCP1
SCP0
1
3
0
0
1
1
0
1
0
1
4
13
.
Table 30. TR dividing factors
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
8
16
32
64
128
Table 31. RR dividing factor
RR dividing factor
SCR2
SCR1
SCR0
1
2
4
0
0
0
0
0
1
0
1
0
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Table 31. RR dividing factor
ST7263Bxx
SCR0
RR dividing factor
SCR2
SCR1
8
16
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
32
64
128
Table 32. SCI register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
SCISR
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
20
21
22
23
24
Reset value
SCIDR
DR7
x
DR6
x
DR5
x
DR4
x
DR3
x
DR2
x
DR1
x
DR0
x
Reset value
SCIBRR
SCP1
0
SCP0
0
SCT2
x
SCT1
x
SCT0
x
SCR2 SCR1 SCR0
Reset value
x
x
x
SCICR1
R8
x
T8
x
SCID
0
M
x
WAKE
x
PCE
0
PS
0
PIE
0
Reset value
SCICR2
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
Reset value
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11.4
USB interface (USB)
11.4.1
Introduction
The USB Interface implements a low-speed function interface between the USB and the
ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3
voltage regulator, SIE and DMA. No external components are needed apart from the
external pull-up on USBDM for low speed recognition by the USB host. The use of DMA
architecture allows the endpoint definition to be completely flexible. Endpoints can be
configured by software as in or out.
11.4.2
Main features
●
●
●
USB Specification Version 1.1 Compliant
Supports Low-Speed USB Protocol
Two or Three Endpoints (including default one) depending on the device (see device
feature list and register map)
●
●
●
●
●
CRC generation/checking, NRZI encoding/decoding and bit-stuffing
USB Suspend/Resume operations
DMA Data transfers
On-Chip 3.3 V Regulator
On-Chip USB Transceiver
11.4.3
Functional description
The block diagram in Figure 44, gives an overview of the USB interface hardware.
For general information on the USB, refer to the “Universal Serial Bus Specifications”
document available at http//:www.usb.org.
Serial interface engine
The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver.
The SIE processes tokens, handles data transmission/reception, and handshaking as
required by the USB standard. It also performs frame formatting, including CRC generation
and checking.
Endpoints
The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how
many bytes need to be transmitted.
DMA
When a token for a valid Endpoint is recognized by the USB interface, the related data
transfer takes place, using DMA. At the end of the transaction, an interrupt is generated.
Interrupts
By reading the Interrupt Status register, application software can know which USB event has
occurred.
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Figure 44. USB block diagram
ST7263Bxx
6 MHz
ENDPOINT
CPU
REGISTERS
USBDM
USBDP
Address,
data buses
Transceiver
SIE
DMA
and interrupts
3.3 V
Voltage
Regulator
INTERRUPT
REGISTERS
USBVCC
USBGND
MEMORY
11.4.4
Register description
DMA Address register (DMAR)
Reset value: undefined
7
0
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
Read.write
[7:0] DA[15:8] DMA address bits 15-8.
Software must write the start address of the DMA memory area whose most significant bits
are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the
description of the IDR register and Figure 45.
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Interrupt/DMA register (IDR)
Reset value: xxxx 0000 (x0h)
7
0
DA7
DA6
EP1
EP0
CNT3
Read.write
CNT2
CNT1
CNT0
[7:6] DA[7:6] DMA address bits 7-6.
Software must reset these bits. See the description of the DMAR register and
Figure 45.
[5:4] EP[1:0] Endpoint number (read-only). These bits identify the endpoint which
required attention.
00: Endpoint 0
01: Endpoint 1
10: Endpoint 2
When a CTR interrupt occurs (see register ISTR) the software should read the EP
bits to identify the endpoint which has sent or received a packet.
[3:0] CNT[3:0] Byte count (read only).
This field shows how many data bytes have been received during the last data
reception.
Note: Not valid for data transmission.
Figure 45. DMA buffers
101111
Endpoint 2 TX
Endpoint 2 RX
101000
100111
100000
011111
Endpoint 1 TX
Endpoint 1 RX
011000
010111
010000
001111
Endpoint 0 TX
Endpoint 0 RX
001000
000111
DA15-6,000000
000000
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PID register (PIDR)
Reset value: xx00 0000 (x0h)
7
0
0
RX_
SEZ
TP3
TP2
0
0
0
RXD
Read only
[7:6] TP[3:2] Token PID bits 3 & 2.
USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token
PID bits 3 & 2.
: PID bits 1 & 0 have a fixed value of 01.
Note: When a CTR interrupt occurs (see register ISTR) the software should read
the TP3 and TP2 bits to retrieve the PID name of the token received.
The USB standard defines TP bits (see Table 33).
[5:3] Reserved. Forced by hardware to 0.
2 RX_SEZ Received single-ended zero
This bit indicates the status of the RX_SEZ transceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
1 RXD Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver output (differential receiver
output).
If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the
application. By interpreting the status, software can distinguish a valid End
Suspend event from a spurious wakeup due to noise on the external USB line. A
valid End Suspend is followed by a Resume or Reset sequence. A Resume is
indicated by RXD=1, a Reset is indicated by RX_SEZ=1.
0 Reserved. Forced by hardware to 0.
Table 33. TP bit definition
TP3
TP2
PID Name
0
1
1
0
0
1
OUT
IN
SETUP
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Interrupt Status register (ISTR)
Reset value: 0000 0000 (00h)
7
0
SUSP
DOVR
CTR
ERR
IOVR
Read.write
ESUSP
RESET
SOF
When an interrupt occurs these bits are set by hardware. Software must read them to
determine the interrupt type and clear them after servicing.
Note:
These bits cannot be set by software.
7 SUSP Suspend mode request.
This bit is set by hardware when a constant idle state is present on the bus line for
more than 3 ms, indicating a suspend mode request from the USB bus. The
suspend request check is active immediately after each USB reset event and its
disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register)
until the end of resume sequence.
6 DOVR DMA over/underrun.
This bit is set by hardware if the ST7 processor can’t answer a DMA request in
time.
0: No over/underrun detected
1: Over/underrun detected
5 CTR Correct Transfer. This bit is set by hardware when a correct transfer operation
is performed. The type of transfer can be determined by looking at bits TP3-TP2 in
register PIDR. The Endpoint on which the transfer was made is identified by bits
EP1-EP0 in register IDR.
0: No Correct Transfer detected
1: Correct Transfer detected
Note: A transfer where the device sent a NAK or STALL handshake is considered
not correct (the host only sends ACK handshakes). A transfer is considered
correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1
PID is sent as expected, if there were no data overruns, bit stuffing or
framing errors.
4 ERR Error.
This bit is set by hardware whenever one of the errors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
3 IOVR Interrupt overrun.
This bit is set when hardware tries to set ERR, or SOF before they have been
cleared by software.
0: No overrun detected
1: Overrun detected
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2 ESUSP End suspend mode.
This bit is set by hardware when, during suspend mode, activity is detected that
wakes the USB interface up from suspend mode.
This interrupt is serviced by a specific vector, in order to wake up the ST7 from Halt
mode.
0: No End Suspend detected
1: End Suspend detected
1 RESET USB reset.
This bit is set by hardware when the USB reset sequence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB
registers are reset by a USB reset.
0 SOF Start of frame.
This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is
seen on the USB bus. It is also issued at the end of a resume sequence.
0: No SOF signal detected
1: SOF signal detected
Note:
To avoid spurious clearing of some bits, it is recommended to clear them using a load
instruction where all bits which must not be altered are set, and all bits to be cleared are
reset. Avoid read-modify-write instructions like AND, XOR.
Interrupt Mask register (IMR)
These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is
cleared, an interrupt request is generated. For an explanation of each bit, please refer to the
corresponding bit description in ISTR.
Reset value: 0000 0000 (00h)
7
0
SUSPM
DOVRM
CTRM
ERRM
IOVRM
ESUSPM
RESETM
SOFM
Read.write
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Control register (CTLR)
Reset value: 0000 0110 (06h)
7
0
0
0
0
0
RESUME
Read/write
PDWN
FSUSP
FRES
[7:4] Reserved. Forced by hardware to 0.
3 RESUME Resume.
This bit is set by software to wakeup the Host when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate delay.
2 PDWN Power down.
This bit is set by software to turn off the 3.3 V on-chip voltage regulator that
supplies the external pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, software should allow at least 3 µs for
stabilization of the power supply before using the USB interface.
1 FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode. The ST7 should also be halted
allowing at least 600 ns before issuing the HALT instruction.
0: Suspend mode inactive
1: Suspend mode active
When the hardware detects USB activity, it resets this bit (it can also be reset by
software).
0 FRES Force reset.
This bit is set by software to force a reset of the USB interface, just as if a RESET
sequence came from the USB.
0: Reset not forced
1: USB interface reset forced.
The USB is held in RESET state until software clears this bit, at which point a “USB-
RESET” interrupt will be generated if enabled.
Device Address register (DADDR)
Reset value: 0000 0000 (00h)
7
0
0
ADD6
ADD5
ADD4
ADD3
Read.write
ADD2
ADD1
ADD0
7 Reserved. Forced by hardware to 0.
[6:0] ADD[6:0] Device address, 7 bits.
Software must write into this register the address sent by the host during
enumeration.
Note: This register is also reset when a USB reset is received from the USB bus or
forced through bit FRES in the CTLR register.
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Endpoint n register A (EPnRA)
These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission.
They are also reset by the USB bus reset.
Note:
Endpoint 2 and the EP2RA register are not available on some devices (see device feature
list and register map).
Reset value: 0000 xxxx (0xh)
7
0
ST_
OUT
DTOG
_TX
STAT
_TX1
STAT
_TX0
TBC3
TBC2
TBC1
TBC0
Read.write
7 ST_OUT Status out.
This bit is set by software to indicate that a status out packet is expected: in this
case, all nonzero OUT data transfers on the endpoint are STALLed instead of being
ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes,
as needed.
6 DTOG_TX Data Toggle, for transmission transfers.
It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next
transmitted data packet. This bit is set by hardware at the reception of a SETUP
PID. DTOG_TX toggles only when the transmitter has received the ACK signal from
the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated
by hardware, at the receipt of a relevant PID. They can be also written by software.
[5:4] STAT_TX[1:0] Status bits, for transmission transfers.
These bits contain the information about the endpoint status, which are listed in
Table 34.
These bits are written by software. Hardware sets the STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) related to a IN or SETUP transaction
addressed to this endpoint; this allows the software to prepare the next set of data
to be transmitted.
[3:0] TBC[3:0] Transmit byte count for Endpoint n.
Before transmission, after filling the transmit buffer, software must write in the TBC
field the transmit packet size expressed in bytes (in the range 0-8).
Caution: Any value outside the range 0-8 willinduce undesired effects (such as
continuous data transmission).
Table 34. STAT_TX bit definition
STAT_TX1
STAT_TX0
Meaning
DISABLED: transmission transfers cannot be
executed.
0
0
STALL: the endpoint is stalled and all transmission
requests result in a STALL handshake.
0
1
NAK: the endpoint is naked and all transmission
requests result in a NAK handshake.
1
1
0
1
VALID: this endpoint is enabled for transmission.
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Endpoint n register B (EPnRB)
These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1
and 2. They are also reset by the USB bus reset.
Note:
Endpoint 2 and the EP2RB register are not available on some devices (see device feature
list and register map).
Reset value: 0000 xxxx (0xh)
7
0
DTOG
_RX
STAT
_RX1
STAT
_RX0
CTRL
EA3
EA2
EA1
EA0
Read.write
7 CTRL Control.
This bit should be 0.
Note: If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a
control Endpoint, but it is possible to have more than one control Endpoint).
6 DTOG_RX Data toggle, for reception transfers.
It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next
data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a
control transfer (SETUP transactions start always with DATA0 PID). The receiver
toggles DTOG_RX only if it receives a correct data packet and the packet’s data
PID matches the receiver sequence bit.
[5:4] STAT_RX [1:0] Status bits, for reception transfers.
These bits contain the information about the endpoint status, which are listed in
Table 35.
These bits are written by software. Hardware sets the STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction
addressed to this endpoint, so the software has the time to elaborate the received
data before acknowledging a new transaction.
[3:0] EA[3:0] Endpoint address.
Software must write in this field the 4-bit address used to identify the transactions
directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains
“0010”.
Table 35. STAT_RX bit definition
STAT_RX1
STAT_RX0
Meaning
DISABLED: reception transfers cannot be
executed.
0
0
STALL: the endpoint is stalled and all reception
requests result in a STALL handshake.
0
1
NAK: the endpoint is naked and all reception
requests result in a NAK handshake.
1
1
0
1
VALID: this endpoint is enabled for reception.
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Endpoint 0 register B (EP0RB)
This register is used for controlling data reception on Endpoint 0. It is also reset by the USB
bus reset.
Reset value: 1000 0000 (80h)
7
1
0
0
DTOG
RX
STAT
RX1
STAT
RX0
0
0
0
Read.write
7 Forced by hardware to 1.
[6:4] Refer to the EPnRB register for a description of these bits.
[3:0] Forced by hardware to 0.
11.4.5
Programming considerations
The interaction between the USB interface and the application program is described below.
Apart from system reset, action is always initiated by the USB interface, driven by one of the
USB events associated with the Interrupt Status register (ISTR) bits.
Initializing the registers
At system reset, the software must initialize all registers to enable the USB interface to
properly generate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of
DMA buffers). Refer the paragraph titled initializing the DMA Buffers.
2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and
endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint
Initialization.
3. When addresses are received through this channel, update the content of the DADDR.
4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB
register.
Initializing DMA buffers
The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They
can be placed anywhere in the memory space to enable the reception of messages. The 10
most significant bits of the start of this memory area are specified by bits DA15-DA6 in
registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 45.
Each buffer is filled starting from the bottom (last 3 address bits=000) up.
Endpoint Initialization
To be ready to receive, set STAT_RX to VALID (11b) in EP0RB to enable reception.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field
3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.
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Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB
Note:
(respectively) must not be modified by software, as the hardware can change their value on
the fly.
When the operation is completed, they can be accessed again to enable a new operation.
Interrupt handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF events for a 1 ms synchronization event
to the USB bus. This interrupt is generated at the end of a resume sequence and can also
be used to detect this event.
USB Reset (RESET)
When this event occurs, the DADDR register is reset, and communication is disabled in all
endpoint registers (the USB interface will not respond to any packet). Software is
responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the
STAT_RX bits in the EP0RB register to VALID.
Suspend (SUSP)
The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend
request. The software should set the USB interface to suspend mode and execute an ST7
HALT instruction to meet the USB-specified power constraints.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7
automatically terminates Halt mode.
Correct Transfer (CTR)
1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to
NAK. Every valid endpoint is NAKed until software clears the CTR bit in the ISTR
register, independently of the endpoint number addressed by the transfer which
generated the CTR interrupt. If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set to NAK.
2. Read the PIDR to obtain the token and the IDR to get the endpoint number related to
the last transfer. When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register
and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR
register is cleared.
3. Clear the CTR bit in the ISTR register.
Table 36. USB register map and reset values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
PIDR
TP3
x
TP2
x
0
0
RX_SEZ
0
RXD
0
0
0
0
0
0
0
25
26
Reset
value
DMAR
DA15
x
DA14
x
DA13
x
DA12
x
DA11
x
DA10
x
DA9
x
DA8
x
Reset
value
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Table 36. USB register map and reset values (continued)
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
IDR
DA7
x
DA6
x
EP1
x
EP0
x
CNT3
0
CNT2
0
CNT1
0
CNT0
0
27
28
29
2A
2B
2C
2D
2E
2F
30
31
Reset
value
ISTR
SUSP
0
DOVR
0
CTR
0
ERR
0
IOVR
0
ESUSP RESET
SOF
0
Reset
value
0
0
IMR
ESUSP
M
SUSPM
0
DOVRM
0
CTRM
0
ERRM
0
IOVRM
0
RESETM SOFM
Reset
value
0
0
0
CTLR
RESUM
E
0
0
0
0
0
0
0
0
PDWN
1
FSUSP
1
FRES
0
Reset
value
0
DADDR
0
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
Reset
value
EP0RA
ST_OUT
0
STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
DTOG_TX
0
Reset
value
0
0
EP0RB
STAT_RX STAT_RX
1
1
DTOG_RX
0
0
0
0
0
0
0
0
0
1
0
Reset
value
0
0
EP1RA
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset
value
0
0
0
0
EP1RB
STAT_RX STAT_RX
CTRL
0
DTOG_RX
0
EA3
x
EA2
x
EA1
x
EA0
x
1
0
Reset
value
0
0
EP2RA
ST_OUT DTOG_TX STAT_TX1 STAT_TX0
TBC3
x
TBC2
x
TBC1
x
TBC0
x
Reset
value
0
0
0
0
EP2RB
STAT_RX STAT_RX
CTRL
0
DTOG_RX
0
EA3
x
EA2
x
EA1
x
EA0
x
1
0
Reset
value
0
0
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11.5
I²C bus interface
11.5.1
Introduction
The I²C bus interface serves as an interface between the microcontroller and the serial I²C
bus. It provides both multimaster and slave functions, and controls all I²C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I²C mode (400 kHz).
11.5.2
Main features
●
●
●
●
●
●
Parallel-bus/I²C protocol converter
Multimaster capability
7-bit addressing
Transmitter/receiver flag
End-of-byte transmission flag
Transfer problem detection
I²C master features
●
●
●
●
●
●
●
Clock generation
I²C bus busy flag
Arbitration Lost Flag
End of byte transmission flag
Transmitter/Receiver Flag
Start bit detection flag
Start and Stop generation
I²C slave features
●
●
●
●
●
●
●
Stop bit detection
I²C bus busy flag
Detection of misplaced start or stop condition
Programmable I²C Address detection
Transfer problem detection
End-of-byte transmission flag
Transmitter/Receiver flag
11.5.3
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
enabled or disabled by software. The interface is connected to the I²C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I²C bus and a
Fast I²C bus. This selection is made by software.
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Mode selection
The interface can operate in the four following modes:
●
Slave transmitter/receiver
Master transmitter/receiver
●
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the
start condition is the address byte; it is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 46.
Figure 46. I²C bus protocol
SDA
ACK
9
MSB
1
SCL
2
8
START
STOP
CONDITION
CONDITION
VR02119B
Acknowledge may be enabled and disabled by software.
The I²C interface address and/or general call address can be selected by software.
The speed of the I²C interface may be selected between Standard (up to 100 kHz) and Fast
I²C (up to 400 kHz).
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data register.
The SCL frequency (F
the I²C bus mode.
) is controlled by a programmable clock divider which depends on
SCL
When the I²C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
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When the I²C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 47. I²C interface block diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
11.5.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 11.5.7. for the bit definitions.
By default the I²C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
●
Address not matched: the interface ignores it and waits for another Start condition.
Address matched
●
The interface generates in sequence:
–
–
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 48 Transfer sequencing EV1).
Next, software must read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
Slave receiver
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Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the
interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after the SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 48 Transfer sequencing EV3).
When the acknowledge pulse is received, the EVF and BTF bits are set by hardware with an
interrupt if the ITE bit is set.
Closing Slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets EVF and STOPF bits with an interrupt if the ITE bit
is set.
Then the interface waits for a read of the SR2 register (see Figure 48 Transfer sequencing
EV4).
Error cases
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop, then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start, then the interface discards the data and waits for the next slave address
on the bus.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note:
In case of errors, SCL line is not held low; however, the SDA line can remain low if the last
bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags
that are set at the same time. It is then necessary to release both lines by software.
How to Release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
Master mode
To switch from default Slave mode to Master mode, a Start condition generation is needed.
Start condition
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Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address byte, holding the SCL line low (see Figure 48 Transfer sequencing
EV5).
Slave address transmission
Then the slave address byte is sent to the SDA line via the internal shift register.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set), the
EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 48 Transfer sequencing
EV6).
Next the master must enter Receiver or Transmitter mode.
Master receiver
Following the address transmission and after the SR1 and CR registers have been
accessed, the master receives bytes from the SDA line into the DR register via the internal
shift register. After each byte the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 48 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets, EVF and BTF bits with an interrupt
if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first or second pulse of
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each 9-bit transaction:
Single Master mode
If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the
BERR flag will not be set and transfer will continue however the BUSY flag will be reset.
To work around this, slave devices should issue a NACK when they receive a
misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle
of communication gives the possibility to reinitiate transmission.
Multimaster mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
2
generates an unauthorized Start or Stop while the I C master is on the first or second
pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit
2
during I C master mode transmission. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag being set.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
●
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note:
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
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Figure 48. Transfer sequencing
Table 37. Slave receiver
Addres
S
A
Data1
A
Data2
Data2
A
DataN
A
P
s
.....
EV
1
EV
2
EV
2
EV
2
EV
4
Table 38. Slave Transmitter
Addres
N
S
A
Data1
A
A
DataN
P
s
A
.....
EV EV
EV
3
EV
3
EV3
EV
4
1
3
-1
Table 39. Master receiver
Addres
N
A
S
A
Data1
A
Data2
A
DataN
P
s
.....
EV
5
EV
6
EV
7
EV
7
EV
7
Table 40. Master Transmitter
Addres
S
A
Data1
A
Data2
A
DataN
A
P
s
.....
EV
5
EV EV
EV
8
EV
8
EV
8
6
8
1. Legend:
S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge
EVx=Event (with interrupt if ITE=1)EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.
EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared
by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).
Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.
EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.
EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register
(for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR
register.
EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR
register.
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11.5.5
Low power modes
Table 41. Low power modes
Mode
Description
No effect on I²C interface.
WAIT
I²C interrupts cause the device to exit from Wait mode.
I²C registers are frozen.
In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The
I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
HALT
11.5.6
Interrupts
Figure 49. Event flags and interrupt generation
BTF
ADSL
ITE
SB
AF
INTERRUPT
EVF
STOPF
ARLO
BERR
(1)
1. EVF can also be set by EV6 or an error from the SR2 register.
Table 42. Interrupts
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Event
flag
Interrupt event
End of Byte Transfer Event
BTF
ADSL
SB
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
AF
ITE
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
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11.5.7
Register description
I²C Control register (CR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read/write
[7:6] Reserved. Forced to 0 by hardware.
5 PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Note: When PE=0, all the bits of the CR register and the SR register except the
Stop bit are reset. All outputs are released while PE=0.
When PE=1, the corresponding I/O pins are selected by hardware as
alternate functions.
To enable the I²C interface, write the CR register TWICE with PE=1 as the
first write only activates the interface (only PE is set).
4 ENGC Enable General Call.
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE=0). The 00h General Call address is acknowledged (01h
ignored).
0: General Call disabled
1: General Call enabled
Note: In accordance with the I2C standard, when GCAL addressing is enabled, an
I2C slave can only receive data. It will not transmit data to the master.
3 START Generation of a Start condition. This bit is set and cleared by software. It is
also cleared by hardware when the interface is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if ITE=1).
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
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2 ACK Acknowledge enable.
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
1 STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also cleared by hardware in master
mode. Note: This bit is not cleared when the interface is disabled (PE=0).
In Master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition
is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this
mode the STOP bit has to be cleared by software.
0 ITE Interrupt enable.
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 49 for the relationship between the events and the interrupt.
SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See Figure 48)
is detected.
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I²C Status register 1 (SR1)
Reset value: 0000 0000 (00h)
7
0
EVF
0
TRA
BUSY
Read only
BTF
ADSL
M/SL
SB
7
EVF Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in Figure 48. It is also
cleared by hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
●
●
●
●
●
●
●
●
BTF=1 (Byte received or transmitted)
ADSL=1 (Address matched in Slave mode while ACK=1)
SB=1 (Start condition generated in Master mode)
AF=1 (No acknowledge received after byte transmission)
STOPF=1 (Stop condition detected in Slave mode)
ARLO=1 (Arbitration lost in Master mode)
BERR=1 (Bus error, misplaced Start or Stop condition detected)
Address byte successfully transmitted in Master mode.
6 Reserved. Forced to 0 by hardware.
5 TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface
is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
4 BUSY Bus busy.
This bit is set by hardware on detection of a Start condition and cleared by
hardware on detection of a Stop condition. It indicates a communication in progress
on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE=0). This
can have consequences when operating in Multimaster mode; i.e. a second
active I2C master commencing a transfer with an unset BUSY bit can cause
a conflict resulting in lost data. A software workaround consists of checking
that the I2C is not busy before enabling the I2C Multimaster cell.
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3 BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted
with interrupt generation if ITE=1. It is cleared by software reading SR1 register
followed by a read or write of DR register. It is also cleared by hardware when the
interface is disabled (PE=0).
Following a byte transmission, this bit is set after reception of the acknowledge
clock pulse. In case an address byte is sent, this bit is set only after the EV6 event
(See Figure 48). BTF is cleared by reading SR1 register followed by writing the next
byte in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge
clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading
the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
2 ADSL Address matched (Slave mode). This bit is set by hardware as soon as the
received slave address matched with the OAR register content or a general call is
recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1
register or by hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
1 M/SL Master/Slave.
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled
(PE=0).
0: Slave mode
1: Master mode
0 SB Start bit (Master mode).
This bit is set by hardware as soon as the Start condition is generated (following a
write START=1). An interrupt is generated if ITE=1. It is cleared by software reading
SR1 register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
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On-chip peripherals
I²C Status register 2 (SR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
Read only
ARLO
BERR
GCAL
[7:5] Reserved. Forced to 0 by hardware.
4 AF Acknowledge failure.
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE=1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE=0).
0: No acknowledge failure
1: Acknowledge failure
Note: While AF=1, the SCL line may be held low due to SB or BTF flags that are
set at the same time. It is then necessary to release both lines by software.
3 STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
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2 ARLO Arbitration lost.
This bit is set by hardware when the interface loses the arbitration of the bus to
another master. An interrupt is generated if ITE=1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
Receive mode it does not perform arbitration during the reception of the
Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register
may occur when a second master simultaneously requests the same data
from the same slave and the I2C master does not acknowledge the data.
The ARLO bit is then left at 0 instead of being set.
1 BERR Bus error.
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be
generated by the Master to re-synchronize communication, get the
transmission acknowledged and the bus released for further communication
0 GCAL General Call (Slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when
the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
I²C Clock Control register (CCR)
Reset value: 0000 0000 (00h)
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Read/write
7 FM/SM Fast/Standard I²C mode.
This bit is set and cleared by software. It is not cleared when the interface is
disabled (PE=0).
0: Standard I²C mode
1: Fast I²C mode
[6:0] CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (FSCL) depending on the I²C mode. They are
not cleared when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for the table of value.
Note: The programmed FSCL assumes no load on SCL and SDA lines.
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I²C Data register (DR)
These bits contain the byte to be received or transmitted on the bus.
●
●
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address. The following data bytes are then received one by
one after reading the DR register.
Reset value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
I²C Own Address register (OAR)
Reset value: 0000 0000 (00h)
7
0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read/write
[7:1] ADD[7:1] Interface address.
These bits define the I²C bus address of the interface. They are not cleared when
the interface is disabled (PE=0).
0 ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared
when the interface is disabled (PE=0).
Note: Address 01h is always ignored.
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Table 43. I²C register map
Address
(Hex.)
Register
name
7
6
5
4
3
2
1
0
39
3B
3C
3D
3E
3F
DR
OAR
CCR
SR2
SR1
CR
DR7 .. DR0
ADD7 .. ADD0
FM/SM
EVF
CC6 .. CC0
STOPF ARLO
AF
BERR
M/SL
GCAL
SB
TRA
PE
BUSY
BTF
ADSL
ACK
ENGC START
STOP
ITE
Note:
Refer to Section 16: Known limitations for information regarding a limitation on the alternate
function on pin PA2 (SCL).
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On-chip peripherals
11.6
8-bit A/D converter (ADC)
11.6.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit Data register. The A/D converter is controlled
through a Control/Status register.
11.6.2
Main features
●
●
●
●
●
●
8-bit conversion
Up to 12 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 50.
11.6.3
Functional description
Analog power supply
V
and V
are the high and low level reference voltage pins. In some devices (refer to
SSA
DDA
device pin out description) they are internally connected to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
See electrical characteristics section for more details.
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On-chip peripherals
Figure 50. ADC block diagram
ST7263Bxx
fCPU
fADC
DIV 4
COCO
0
ADON
4
0
CH3 CH2 CH1 CH0
ADCCSR
AIN0
AIN1
HOLD CONTROL
RADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
CADC
ADCDR
D7 D6 D5 D4 D3 D2 D1 D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V ) is greater than or equal to V
(high-level voltage reference) then
AIN
DDA
the conversion result in the DR register is FFh (full scale) without overflow indication.
If input voltage (V ) is lower than or equal to V
(low-level voltage reference) then the
AIN
SSA
conversion result in the DR register is 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDR
register. The accuracy of the conversion is described in the parametric section.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
A/D conversion phases
The A/D conversion is based on two conversion phases as shown in Figure 51:
●
Sample capacitor loading [duration: t
]
LOAD
During this phase, the V
input voltage to be measured is loaded into the C
AIN
ADC
sample capacitor.
●
A/D conversion [duration: t
]
CONV
During this phase, the A/D conversion is computed (8 successive approximations
cycles) and the C sample capacitor is disconnected from the analog input pin to get
ADC
the optimum analog to digital conversion accuracy.
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous
measurement load. The advantage of this behavior is that it minimizes the current
consumption on the analog pin in case of single input channel measurement.
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On-chip peripherals
Software procedure
Refer to the control/status register (CSR) and data register (DR) in Section 11.6.6 for the bit
definitions and to Figure 51 for the timings.
ADC configuration
The total duration of the A/D conversion is 12 ADC clock periods (1/f
=4/f
).
CPU
ADC
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
«I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the CSR register:
●
Select the CH[3:0] bits to assign the analog channel to be converted.
ADC conversion
In the CSR register:
●
Set the ADON bit to enable the A/D converter and to start the first conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
●
●
The COCO bit is set by hardware.
No interrupt is generated.
The result is in the DR register and remains valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO
bit and starts a new conversion.
Figure 51. ADC conversion timings
ADON
ADCCSR WRITE
tCONV
OPERATION
HOLD
CONTROL
tLOAD
COCO BIT SET
11.6.4
Low power modes
Table 44. Low power modes
Mode
Description
WAIT
HALT
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
before accurate conversions can be performed.
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
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On-chip peripherals
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11.6.5
11.6.6
Interrupts
None
Register description
Control/Status register (CSR)
Reset value: 0000 0000 (00h)
7
0
COCO
0
ADON
0
CH3
CH2
CH1
CH0
Read/write
7 COCO Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR
register or writing to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
6 Reserved. must always be cleared.
5 ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
4 Reserved. must always be cleared.
[3:0] CH[3:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert
(see Table 45).
Table 45. Channel selection
Channel pin(1)
CH3(2)
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1. The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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On-chip peripherals
2. For SDIP/SO34 devices, the CH3 bit is always at ‘0’. If, however, set to ‘1’ on error, channel (11:8)
becomes enabled which may result in a higher and unnecessary level of consumption.
Data register (DR)
This register contains the converted analog value in the range 00h to FFh.
Reset value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Read only
Note:
Reading this register reset the COCO flag.
Table 46. ADC register map
Address
(Hex.)
Register
name
7
6
5
4
3
2
1
0
0Ah
0Bh
DR
AD7 .. AD0
CH3
CSR
COCO
0
ADON
0
CH2
CH1
CH0
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Instruction set
ST7263Bxx
12
Instruction set
12.1
ST7 addressing modes
The ST7 Core features 17 different addressing modes which can be classified in 7 main
groups:
Table 47. Addressing modes
Addressing mode
Example
Inherent
Immediate
Direct
nop
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two sub-modes
called long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 48. ST7 addressing mode overview
Destination/
source
Pointer
address
Pointer size
(Hex.)
Length
(bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
ld A,$1000
Direct
Direct
00..FF
Long
0000..FFFF
+ 0 (with X
register)
+ 1 (with Y
register)
No Offset
Direct
Indexed
Indexed
ld A,(X)
00..FF
Short
Long
Short
Direct
Direct
ld A,($10,X)
00..1FE
0000..FFFF
00..FF
+ 1
+ 2
+ 2
Indexed ld A,($1000,X)
ld A,[$10]
Indirect
00..FF
byte
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Instruction set
Table 48. ST7 addressing mode overview (continued)
Destination/
Pointer
address
Pointer size
(Hex.)
Length
(bytes)
Mode
Syntax
source
Long
Short
Long
Indirect
Indirect
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
00..FF
00..FF
word
byte
+ 2
+ 2
+ 2
Indexed
ld A,([$10],X)
00..1FE
Indexed ld A,([$10.w],X) 0000..FFFF
word
PC-
jrne loop
Relative
Relative
Direct
+ 1
+ 2
128/PC+127(1)
PC-
jrne [$10]
Indirect
00..FF
00..FF
00..FF
byte
byte
byte
128/PC+127(1)
Bit
Bit
Bit
Direct
Indirect
Direct
bset $10,#7
bset [$10],#7
00..FF
00..FF
00..FF
+ 1
+ 2
+ 2
Relative btjt $10,#7,skip
btjt
Relative
Bit
Indirect
00..FF
+ 3
[$10],#7,skip
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
12.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 49. Inherent instructions
Inherent instruction
Function
NOP
TRAP
WFI
No operation
S/W interrupt
Wait For Interrupt (Low Power mode)
Halt Oscillator (Lowest Power mode)
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
HALT
RET
IRET
SIM
RIM
Reset Interrupt Mask
Set Carry Flag
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
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Instruction set
Table 49. Inherent instructions (continued)
ST7263Bxx
Inherent instruction
Function
CPL, NEG
MUL
1 or 2 Complement
Byte Multiplication
SLL, SRL, SRA, RLC, RRC
SWAP
Shift and Rotate Operations
Swap Nibbles
12.1.2
Immediate instructions
Immediate instructions have two bytes, the first byte contains the opcode, the second byte
contains the operand value.
Table 50. Immediate instructions
Immediate instruction
Function
LD
CP
Load
Compare
BCP
Bit Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
12.1.3
Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two sub-modes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
12.1.4
Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
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Instruction set
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
12.1.5
Indirect (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-
modes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
12.1.6
Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 51. Instructions supporting Direct, Indexed, Indirect and Indirect Indexed
addressing modes
Long and Short instructions
Function
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Addition/subtraction operations
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Instruction set
ST7263Bxx
Table 51. Instructions supporting Direct, Indexed, Indirect and Indirect Indexed
addressing modes (continued)
Long and Short instructions
Function
Bit Compare
Function
BCP
Short Instructions only
CLR
INC, DEC
Clear
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
Bit Test and Jump Operations
Shift and Rotate Operations
Swap Nibbles
CALL, JP
Call or Jump subroutine
12.1.7
Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 52. Instructions supporting relative addressing mode
Available relative direct/Indirect instructions
Function
JRxx
Conditional Jump
Call Relative
CALLR
The relative addressing mode consists of two sub-modes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
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Instruction set
12.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 53. Instruction groups
Load and Transfer
Stack operation
LD
CLR
PUSH POP
RSP
Increment/Decrement
Compare and Tests
INC
CP
DEC
TNZ
OR
BCP
Logical operations
AND
XOR CPL NEG
Bit Operation
BSET BRES
BTJT BTJF
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
ADC
SLL
ADD
SRL
JRT
SUB SBC MUL
SRA
JRF
RLC RRC SWAP SLA
JP CALL CALLR NOP RET
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
Interruption management
Condition Code Flag modification
WFI
RIM
HALT IRET
SCF RCF
Using a pre-byte
The instructions are described with one to four bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2End of previous instruction
PC-1Prebyte
PCOpcode
PC+1Additional word (0 to 2) according to the number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92Replace an instruction using direct, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91Replace an instruction using X indirect indexed addressing mode by a Y one.
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Instruction set
ST7263Bxx
Table 54. Instructions
Mnemo
Description
Function/example
Dst
Src
H
I
N
Z
C
ADC
ADD
AND
BCP
Add with Carry
Addition
A = A + M + C
A = A + M
A
A
M
M
M
M
H
H
N
N
N
N
Z
Z
Z
Z
C
C
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
H = 0 ?
JRNH
JRM
Jump if H = 0
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
JRUGE
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Jump if C = 0
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Instruction set
Table 54. Instructions (continued)
Mnemo
Description
Function/example
Dst
Src
H
I
N
Z
C
JRUGT
JRULE
LD
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Load
Unsigned >
Unsigned <=
dst <= src
X,A = X * A
neg $10
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
N
N
N
N
Z
Z
Z
Z
MUL
NEG
NOP
OR
Multiply
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
M
POP
reg
CC
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
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Electrical characteristics
ST7263Bxx
13
Electrical characteristics
13.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
13.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T =25 °C and T =T max (given by the
A
A
A
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
13.1.2
13.1.3
13.1.4
Typical values
Unless otherwise specified, typical data are based on T =25 °C, V =5 V. They are given
only as design guidelines and are not tested.
A
DD
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 52.
Figure 52. Pin loading conditions
ST7 PIN
C
L
13.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 53.
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Electrical characteristics
Figure 53. Pin input voltage
ST7 PIN
V
IN
13.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Note:
Directly connecting the RESET and I/O pins to V or V could damage the device if an
DD SS
unintentional internal reset is generated or an unexpected change of the I/O configuration
occurs (for example, due to a corrupted program counter). To guarantee safe operation, this
connection has to be done through a pull-up or pull-down resistor (typical: 4.7 kΩ for
RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V
DD
SS
according to their reset configuration.
Table 55. Voltage characteristics
Symbol
Ratings
Maximum value
Unit
VDD - VSS
Supply voltage
6.0
Input voltage on true open drain pins
Input voltage on any other pin
VSS-0.3 to 6.0
VSS-0.3 to VDD+0.3
V
(1)(2)
VIN
Electrostatic discharge voltage (Human Body
model)
VESD(HBM)
Section 13.7.3
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7 kΩ for RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the same
way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
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Electrical characteristics
Table 56. Current characteristics
ST7263Bxx
Symbol
Ratings
Maximum value
Unit
IVDD
IVSS
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
80
80
Output current sunk by any standard I/O and
control pin
25
50
IIO
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control
pin
- 25
mA
Injected current on VPP pin
5
5
5
5
Injected current on RESET pin
(2)(3)
IINJ(PIN)
Injected current on OSCIN and OSCOUT pins
Injected current on any other pin(4)(5)
Total injected current (sum of all I/O and
control pins)(4)
(2)
ΣIINJ(PIN)
20
Negative injected current to PB0 (10 mA)/AIN0
pin
(2)(3)
IINJ(PIN)
- 80
µA
1. All power (VDD) and ground (VSS) lines must be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open drain I/O port pins do not accept positive injection.
Table 57. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
See Section 14.2:
Thermal
characteristics for
TJmax
TJ
Maximum junction temperature
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Electrical characteristics
13.3
Operating conditions
Table 58. General operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
VDDA
VSSA
Operating Supply Voltage
Analog reference voltage
Analog reference voltage
fCPU = 8 MHz
4
VDD
VSS
-
5
-
5.5
VDD
VSS
8
V
-
f
OSC = 24 MHz
-
fCPU
TA
Operating frequency
MHz
°C
fOSC = 12 MHz
-
-
4
Ambient temperature range
0
-
70
Figure 54. f
maximum operating frequency versus V supply voltage
DD
CPU
fCPU [MHz]
8
FUNCTIONALITY
GUARANTEED
FROM 4 TO 5.5 V
4
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
2
0
SUPPLY VOLTAGE [V]
5.5
2.5
3.0
3.5
4
4.5
5
13.3.1
Operating conditions with low voltage detector (LVD)
Subject to general operating conditions for V , f
, and T . Refer to Figure 12 on
A
DD CPU
page 33.
Table 59. Operating conditions with LVD
Symbol
Parameter
Conditions
Min Typ Max Unit
Low voltage reset threshold
(VDD rising)
VDD max. variation
50 V/ms
VIT+
3.4
3.2
3.7
3.5
4.0
3.8
V
V
Low voltage reset threshold
(VDD falling)
VDD max. variation
50V/ms
VIT-
Vhyst
Hysteresis (VIT+ - VIT-)(1)
100 175 220
0.5 50
mV
VtPOR VDD rise time rate(2)
-
V/ms
1. Guaranteed by characterization - not tested in production.
2. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested
in production.
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Electrical characteristics
ST7263Bxx
13.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
Table 60. Supply current characteristics
Symbol Parameter
ΔIDD(ΔTa) Supply current variation vs. temperature Constant VDD and fCPU
Conditions
Typ
Max
Unit
-
10(1)
%
f
CPU = 4 MHz
fCPU = 8 MHz
CPU = 4 MHz
fCPU = 8 MHz
7.5 9(2)(1)
10.5 13(2)
CPU Run mode
I/Os in input mode
mA
f
6
8(1)
11(2)
40(1)
120
-
CPU Wait mode
mA
μA
μA
IDD
8.5
25
CPU Halt mode(3)
USB Suspend mode(4)
LVD disabled
LVD disabled
LVD enabled
100
230
1. Not tested in production, guaranteed by characterization.
2. Oscillator and watchdog running. All others peripherals disabled.
3. USB Transceiver and ADC are powered down.
4. CPU in Halt mode. Current consumption of external pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to
VSSA) not included.
Figure 55. Typ. I in Run at f
= 4 and 8 MHz
DD
CPU
Idd Run (mA) at fcpu=4 and 8MHz
12
10
8
6
4
8MHz
4MHz
2
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai15593
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Electrical characteristics
Figure 56. Typ. I in Wait at f
= 4 and 8 MHz
DD
CPU
Idd WFI (mA) at fcpu=4 and 8MHz
10
8
6
4
8MHz
4MHz
2
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai15594
13.5
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
A
DD CPU
Table 61. General timings
Symbol Parameter
Conditions
fCPU=8 MHz
Min
Typ(1)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST) Instruction cycle time
250
10
375
Interrupt reaction time(2)
tv(IT)
-
-
tCPU
μs
fCPU=8 MHz
tv(IT) = Δtc(INST) + 10 tCPU
1.25
2.75
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
Table 62. Control timing characteristics
Value
Typ.
Symbol
Parameter
Conditions
Unit
Min
Max
fOSC
fCPU
tRL
Oscillator frequency
-
-
-
-
-
24
8
-
MHz
MHz
ns
Operating frequency
-
External reset input pulse width
Internal power reset duration
2520
4096
tPORL
-
tCPU
Watchdog or low voltage reset
output pulse width
tWDGL
200
300
-
ns
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Electrical characteristics
ST7263Bxx
Table 62. Control timing characteristics
49152
6.144
20(1)
-
-
-
3145728
393.216
40(1)
tCPU
ms
tWDG
Watchdog timeout
fCPU = 8MHz
tOXOV
tDDR
Crystal oscillator startup time
Power up rise time
30
-
ms
from VDD = 0 to 4 V
100(1)
ms
1. Not tested in production, guaranteed by characterization.
Table 63. External clock source
Symbol
Parameter
Conditions
Min
Typ
Max
VDD
Unit
VOSCINH OSCIN input pin high level voltage
VOSCINL OSCIN input pin low level voltage
0.7xVDD
VSS
-
-
V
0.3xVDD
-
tw(OSCINH)
tw(OSCINL)
OSCIN high or low time(1)
15
-
see Figure 57
ns
tr(OSCIN)
tf(OSCIN)
OSCIN rise or fall time(1)
-
-
-
-
15
1
IL
OSCx input leakage current
VSS≤VIN≤VDD
μA
1. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 57. Typical application with an external clock source
90%
VOSCINH
10%
VOSCINL
tf(OSCIN)
tw(OSCINH)
tr(OSCIN)
tw(OSCINL)
OSCOUT
Not connected internally
fOSC
EXTERNAL
CLOCK SOURCE
IL
OSCIN
ST72XXX
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Electrical characteristics
Figure 58. Typical application with a crystal resonator
i
2
fOSC
CL1
OSCIN
RESONATOR
R
F
CL2
OSCOUT
ST72XXX
13.6
Memory characteristics
Subject to general operating conditions for f
, and T unless otherwise specified.
A
CPU
Table 64. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode(1)
Halt mode (or RESET)
2.0
-
-
V
1. Guaranteed by design. Not tested in production.
13.6.1
Flash memory
Operating Conditions: f
= 8 MHz.
CPU
(1)
Table 65. Dual voltage Flash memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Read mode
-
-
8
fCPU
Operating frequency
MHz
Write / Erase
mode, TA=25 °C
-
-
8
VPP
IPP
Programming voltage
VPP current
4.0 V ≤VDD ≤ 5.5 V 11.4
-
30
10
-
12.6
V
Write / Erase
-
-
-
-
-
-
mA
tVPP
tRET
NRW
Internal VPP stabilization time
Data retention
µs
TA ≤ 5 5°C
40
100
years
cycles
Write/erase cycles
TA=25 °C
-
1. Refer to the Flash programming reference manual for the typical HDFlash programming and erase timing
values.
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Electrical characteristics
ST7263Bxx
Figure 59. Two typical applications with V pin
PP
VPP
VPP
PROGRAMMING
TOOL
10kΩ
ST72XXX
ST72XXX
1. When the ICP mode is not required by the application, VPP pin must be tied to VSS
.
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Electrical characteristics
13.7
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
13.7.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 66. EMC characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD=5 V, TA=+25 °C, fOSC=8 MHz,
SDIP32
conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
4B
Fast transient voltage burst limits to be
VDD=5 V, TA=+25 °C, fOSC=8 MHz,
VFFTB applied through 100 pF on VDD and VDD SDIP32
4A
pins to induce a functional disturbance
conforms to IEC 1000-4-4
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Electrical characteristics
ST7263Bxx
13.7.2
Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 67. EMI characteristics
Max vs.
[fOSC/fCPU
Monitored
frequency
band
]
Symbol
Parameter
Conditions
Unit
16/8 MHz
0.1 MHz to
30 MHz
36
39
30 MHz to
130 MHz
VDD=5 V, TA=+25 °C, SDIP32
package conforming to
SAE J 1752/3(2)
dBµV
SEMI
Peak level(1)
130 MHz to
1 GHz
26
SAE EMI Level
3.5
-
1. Data based on characterization results, not tested in production.
2. Refer to application note AN1709 for data on other package types.
13.7.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard.
Table 68. Absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value(1)
Electrostatic discharge voltage
(human body model)
VESD(HBM)
TA=+25 °C
2000
V
1. Data based on characterization results, not tested in production.
Static latchup (LU)
3 complementary static tests are required on 10 parts to assess the latchup performance. A
supply overvoltage (applied to each power supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application
note AN1181.
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Electrical characteristics
Table 69. Electrical sensitivities
Symbol
Parameter
Static latchup class
Conditions
Class(1)
LU
TA=+25 °C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
13.8
I/O port pin characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 70. General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
-
-
0.3xVDD
V
0.7xVDD
-
-
6.0
VDD
-
True open drain I/O pins
Other I/O pins
-
VIN
Input voltage
VSS
V
-
400
-
Vhys
IL
Schmitt trigger voltage hysteresis
Input leakage current
-
-
mV
VSS≤VIN≤VDD
1
µA
Static current consumption induced
by each floating input pin(1)
IS
Floating input mode
-
400
-
RPU
CIO
Weak pull-up equivalent resistor(2) VIN=VSS
VDD=5 V
50
-
90
5
120
kΩ
I/O pin capacitance
-
-
-
-
pF
tf(IO)out Output high to low level fall time
tr(IO)out Output low to high level rise time
tw(IT)in External interrupt pulse time(3)
-
25
25
-
CL=50pF
Between 10% and 90%
ns
-
1
tCPU
1. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 60). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and
temperature values.
2. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in
Figure 61).
3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 60. Two typical applications with unused I/O pin
VDD
ST72XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST72XXX
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Electrical characteristics
Figure 61. Typ. I vs. V
ST7263Bxx
PU
DD
Pull-up current (µA)
90
80
70
60
50
40
30
20
10
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai15595
Figure 62. Typ. R vs. V
PU
DD
Rpu (KOhm)
140
120
100
80
60
40
20
0
4
4.2
4.4
4.6
4.8
Vdd (V)
5
5.2
5.4
ai15596
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Electrical characteristics
Table 71. Output driving current
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level voltage for a standard I/O pin
when up to 8 pins are sunk at the same time,
Port A0, Port A(3:7), Port C(0:2), Port D(0:7)
IIO=+1.6 mA
-
0.4
Output low level voltage for a high sink I/O pin
when up to 4 pins are sunk at the same time,
Port B(0:7)
(1)
VOL
IIO=+10 mA
IIO=+25 mA
-
1.3
1.5
V
Output low level voltage for a very high sink I/O
pin when up to 2 pins are sunk at the same
time, Port A1, Port A2
-
IIO=-10 mA
IIO=-1.6 mA
VDD-1.3(3)
VDD-0.8
-
-
Output high level voltage for an I/O pin
when up to 8 pins are sourced at same time
(2)
VOH
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH
.
3. The minimum VOH value (with IIO=-10mA) depends on the chosen device type. For Flash devices, min = VDD - 1.3 V and
for ROM devices, min = VDD - 1.7 V
Figure 63. V standard V =5 V
OL
DD
Vol_2mA (mV) at Vdd=5V
250
200
150
100
50
0
1
1.5
2
2.5
3
3.5
4
Iio (mA)
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Electrical characteristics
Figure 64. V high sink V =5 V
ST7263Bxx
OL
DD
Vol_10mA (V) at Vdd=5V
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
5
7
9
11
13
15
17
19
Iio (mA)
ai15598
Figure 65. V very high sink V =5 V
OL
DD
Vol_25mA (V) at Vdd=5V
0.95
0.85
0.75
0.65
0.55
0.45
0.35
15
20
25
30
35
Iio (mA)
ai15599
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Electrical characteristics
Figure 66. V standard vs. V
OL
DD
Vol_2mA (mV) at Iio=2mA
130
125
120
115
110
105
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai17200
Figure 67. V high sink vs. V
OL
DD
Vol_10mA (V) at Iio=10mA
0.6
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
0.5
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai17201
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Electrical characteristics
Figure 68. V very high sink vs. V
ST7263Bxx
OL
DD
Vol_25mA (V) at Iio=25mA
0.8
0.75
0.7
0.65
0.6
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai17202
Figure 69. |V -V | @ V =5 V (low current)
DD OH
DD
|Vdd - Voh| (V) at Vdd=5V
0.3
0.25
0.2
0.15
0.1
0.05
0
1
1.5
2
2.5
3
3.5
4
-Iio (mA)
ai17203
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Electrical characteristics
Figure 70. |V -V | @ V =5 V (high current)
DD OH
DD
|Vdd - Voh| (V) at Vdd=5V
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2
7
12
17
-Iio (mA)
ai17704
Figure 71. |V -V | @ I =2 mA (low current)
DD OH
IO
|Vdd - Voh| (V) at Iio=-2mA
0.165
0.16
0.155
0.15
0.145
0.14
0.135
0.13
0.125
0.12
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai17705
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Electrical characteristics
ST7263Bxx
Figure 72. |V -V | @ I =10 mA (high current)
DD OH
IO
|Vdd - Voh| (V) at Iio=-10mA
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4
4.2
4.4
4.6
4.8
5
5.2
5.4
Vdd (V)
ai17706
13.9
Control pin characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 72. Asynchronous RESET pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
Input high level voltage
0.7xVDD
-
VDD
V
0.3xVD
VIL
Input low voltage
VSS
-
-
V
D
Schmitt trigger voltage
hysteresis(1)
Vhys
400
-
mV
IIO=5 mA
IIO=7.5 mA
-
-
-
-
0.8
1.3
VOL
Output low level voltage(2)
VDD=5 V
V
Weak pull-up equivalent resistor
RON
VIN=VSS VDD=5 V
50
80
100
kΩ
(3)
External pin or
internal reset sources
6
30
1/fSFOSC
µs
tw(RSTL)out Generated reset pulse duration
th(RSTL)in External reset pulse hold time(4)
-
-
-
5
-
µs
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS
.
3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not
tested in production.
4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET
pin with a duration below th(RSTL)in can be ignored.
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Electrical characteristics
Figure 73 and Figure 74 show the reset circuit which protects the device against parasitic
resets:
●
●
●
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the V max. level specified in Section Table 72.:
IL
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than
the absolute maximum value specified for I
in Section Table 56.: Current
INJ(RESET)
characteristics.
When the LVD is enabled:
●
It is recommended not to connect a pull-up resistor or capacitor. A 10 nF pull-down
capacitor is required to filter noise on the reset line.
●
In case a capacitive power supply is used, it is recommended to connect a 1 MΩ pull-
down resistor to the RESET pin to discharge any residual voltage induced by the
capacitive effect of the power supply (this will add 5 µA to the power consumption of the
MCU).
●
Tips when using the LVD:
a) Check that all recommendations related to ICCCLK and reset circuit have been
applied (see notes above).
b) Check that the power supply is properly decoupled (100 nF + 10 µF close to the
MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to
put a 100 nF + 1 MΩ pull-down on the RESET pin.
c) The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps a) and b) above are sufficient
for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a
5 µF to 20 µF capacitor.
Figure 73. RESET pin protection when LVD is enabled
V
ST72XXX
DD
Optional
Required
RON
INTERNAL
RESET
EXTERNAL
RESET
Filter
0.01μF
1MΩ
WATCHDOG
LVD RESET
PULSE
GENERATOR
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Electrical characteristics
Figure 74. RESET pin protection when LVD is disabled
ST7263Bxx
V
ST72XXX
DD
RON
INTERNAL
RESET
USER
EXTERNAL
RESET
Filter
CIRCUIT
0.01μF
PULSE
GENERATOR
WATCHDOG
Required
13.10
Communication interface characteristics
13.10.1 USB interface
Operating conditions T = 0 to +70 °C, V = 4.0 to 5.25 V unless otherwise specified.
A
DD
Table 73. USB DC characteristics
Symbol
Parameter
Conditions
Min.
Max.
Unit
VDI
VCM
VSE
Differential input sensitivity
I(D+, D-)
0.2
0.8
0.8
-
-
Differential common mode range Includes VDI range
Single ended receiver threshold
2.5
2.0
0.3
3.6
3.60
V(1)
VOL
Static output low
RL(2)of 1.5 KΩ to 3.6 V
RL(2) of 15 KΩ to VSS
VDD=5 V
VOH
USBV
Static output high
2.8
3.00
USBVCC: voltage level(3)
1. All the voltages are measured from the local ground potential.
2. RL is the load connected on the USB drivers.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the USBVCC pin.
Figure 75. USB data signal rise and fall time
Differential
Data Lines
Crossover
points
VCRS
V
SS
tr
tf
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Electrical characteristics
Table 74. USB low-speed electrical characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Driver characteristics:
-
75
-
-
CL=50 pF(1)
-
ns
ns
ns
ns
%
V
tr
tf
Rise time
Fall Time
CL=600 pF(1)
CL=50 pF(1)
CL=600 pF(1)
tr/tf
300
-
75
-
300
120
2.0
trfm
Rise/ fall time matching
80
1.3
VCRS
Output signal crossover voltage
1. For more detailed information, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
13.10.2 SCI interface
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD CPU
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (RDI and TDO).
Table 75. SCI characteristics
Conditions
Accuracy
Baud
Rate
Symbol
Parameter
Standard
Unit
fCPU
vs.
Prescaler
standard
Conventional mode
TR (or RR)=128, PR=13
TR (or RR)= 32, PR=13
TR (or RR)= 16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 16, PR= 3
TR (or RR)= 2, PR=13
TR (or RR)= 1, PR=13
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69 Hz
~9615.38
~10416.67
~19230.77
~38461.54
fTx
fRx
Communication
frequency
8 MHz ~0.16%
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Electrical characteristics
ST7263Bxx
2
13.10.3 I C interface
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDAI and SCLI).
2
2
The ST7 I C interface meets the requirements of the standard I C communication protocol
described in the following table.
Subject to general operating conditions for V , f
, and T unless otherwise specified.
DD OSC
A
2
Table 76. I C characteristics
Standard mode
Fast mode I2C(1)(2)
I2C(1)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
-
-
-
-
1.3
0.6
-
µs
-
250
0(3)
100
0(4)
-
th(SDA) SDA data hold time
900(3)
tr(SDA)
ns
SDA and SCL rise time
tr(SCL)
-
-
1000 20+0.1Cb
300
300
tf(SDA)
SDA and SCL fall time
tf(SCL)
300
20+0.1Cb
th(STA) START condition hold time
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
µs
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
µs
µs
pF
tw(STO:S
STOP to START condition time (bus free)
4.7
-
1.3
-
-
TA)
Cb
Capacitive load for each bus line
-
400
400
1. Data based on standard I2C protocol requirement, not tested in production.
2. At 4 MHz fCPU, max.I2C speed (400 kHz) is not achievable. In this case, max. I2C speed will be
approximately 260 KHz.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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Figure 76. Typical application with I C bus and timing diagram
Electrical characteristics
2
VDD
VDD
4.7kΩ
4.7kΩ
100Ω
100Ω
SDAI
SCLI
I2C BUS
ST72XXX
REPEATED START
START
tsu(STA)
tw(STO:STA)
START
SDA
tr(SDA)
tf(SDA)
STOP
tsu(SDA)
th(SDA)
SCK
th(STA) tw(SCKH) tw(SCKL)
tr(SCK)
tsu(STO)
tf(SCK)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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Electrical characteristics
ST7263Bxx
2
Table 77 gives the values to be written in the I2CCCR register to obtain the required I C
SCL line frequency.
(1)(2)(3)(4)
Table 77. SCL frequency
I2CCCR Value
fCPU=4 MHz
fCPU=8 MHz
fSCL
(kHz)
VDD = 4.1 V
VDD = 5 V
VDD = 4.1 V
VDD = 5 V
RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ RP=3.3 kΩ RP=4.7 kΩ
400
300
200
100
50
NA
NA
NA
NA
83h
85h
8Ah
24h
4Ch
FFh
83
83h
85h
8Ah
24h
4Ch
FFh
83h
85h
8Ah
23h
4Ch
FFh
NA
NA
NA
NA
85h
89h
23h
4Ch
FFh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
83h
10h
24h
5Fh
20
1. Legend: RP = External pull-up resistance; fSCL = I2C speed; NA = not achievable.
2. The above variations depend on the accuracy of the external components used.
3. For speeds around 200 kHz, achieved speed can have ±5% tolerance.
4. For other speed ranges, achieved speed can have ±2% tolerance.
13.11
8-bit ADC
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Table 78. 8-bit ADC characteristics
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
fADC
VAIN
ADC clock frequency
-
VSSA
-
-
-
-
4
MHz
V
Conversion range voltage(2)
VDDA
10(3)
RAIN External input resistor
κΩ
Internal sample and hold
capacitor
CADC
-
6
-
pF
Stabilization time after ADC
enable
tSTAB
0(4)
6
µs
fCPU=8 MHz,
fADC=2 MHz
Conversion time (Sample+Hold)
tADC
- Sample capacitor loading time
- Hold conversion time
4
8
1/fADC
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than
10kΩ). Data based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable
is then always valid.
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Electrical characteristics
Figure 77. Typical application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
V
AIN
ADC
V
0.6V
T
C
~2pF
I
L
1μA
IO
V
DD
V
V
DDA
0.1μF
SSA
ST72XXX
Table 79. ADC accuracy with V =5 V, f
= 8 MHz, f
=4 MHz, R < 10 κΩ
DD
CPU
ADC
AIN
Symbol
Parameter
Typ
Max(1)(2)
|ET|
Total unadjusted error(3)
1.5
2
|EO|
|EG|
|ED|
|EL|
Offset error(3)
0.5
0.5
1
1
Gain Error(3)
1.5
1.5
1.5
Differential linearity error(3)
Integral linearity error(3)
1
1. Data based on characterization results over the whole temperature range, not tested in production.
2. Data based on characterization results, to guarantee 99.73% within max value from 0 to 70 °C ( 3s
distribution limits).
3. ADC Accuracy vs. Negative Injection Current:
For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is
a loss of 1 LSB for each 10KΩ increase of the external analog source impedance. This effect on the ADC
accuracy has been observed under worst-case conditions for injection:
- negative injection
- injection to an input with analog capability, adjacent to the enabled Analog input
- at 5V VDD supply, and worst case temperature.
Doc ID 7516 Rev 8
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Electrical characteristics
Figure 78. ADC accuracy characteristics
ST7263Bxx
E
Digital Result ADCDR
G
255
254
253
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
7
V (LSB )
IDEAL
0
in
1
2
3
4
5
6
253 254 255 256
V
V
DDA
SSA
1. (1) Example of an actual transfer curve; (2) The ideal transfer curve; (3) End point correlation line.
2. ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual transition and the first ideal one.
EG=Gain Error: deviation between the last ideal transition and the last actual one.
ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation
line.
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Package characteristics
14
Package characteristics
In order to meet environmental requirements, ST offers this device in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
®
®
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 7516 Rev 8
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Package characteristics
ST7263Bxx
14.1
Package mechanical data
Figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline
E
eC
A2
A
L
A1
E1
C
eA
eB
b
b1
e
D
Table 80. 32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data
mm
inches(1)
Dim.
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
3.560
0.510
3.050
0.360
0.760
0.200
27.430
9.910
7.620
3.760
5.080
0.1400
0.0200
0.1200
0.0140
0.0300
0.0080
1.0800
0.3900
0.3000
0.1480
0.2000
3.560
0.460
1.020
0.250
4.570
0.580
1.400
0.360
28.450
11.050
9.400
0.1400
0.0180
0.0400
0.0100
1.1000
0.4100
0.3500
0.0700
0.4000
0.1800
0.0230
0.0550
0.0140
1.1200
0.4350
0.3700
b1
C
D
E
10.410
8.890
E1
e
1.780
eA
eB
eC
L
10.160
12.700
1.400
3.810
0.5000
0.0550
0.15000
2.540
3.050
0.1000
0.1200
Number of pins
32
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 80. 34-pin plastic small outline package, 300-mil width, package outline
h x 45×
L
A
C
A1
α
e
B
D
E
H
Table 81. 34-pin plastic small outline package, 300-mil width, package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
B
C
D
E
e
2.464
0.127
0.356
0.231
17.729
7.417
2.642
0.292
0.483
0.318
18.059
7.595
0.0970
0.0050
0.0140
0.0090
0.6980
0.2920
0.1040
0.0120
0.0190
0.0130
0.7110
0.2990
1.016
0.0400
H
h
10.160
0.635
0°
10.414
0.737
8°
0.4000
0.0250
0°
0.4100
0.0290
8°
α
L
0.610
1.016
0.0240
0.0400
Number of pins
34
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
ST7263Bxx
Figure 81. 24-pin plastic small outline package, 300-mil width package outline
D
12
1
h x 45°
C
E
H
A
13
B
24
ddd
A1
e
A1
α
L
9U_ME
Table 82. 24-pin plastic small outline package, 300-mil width package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
B
2.350
0.100
0.330
0.230
15.200
7.400
2.650
0.300
0.510
0.320
15.600
7.600
0.0930
0.0040
0.0130
0.0090
0.5990
0.2910
0.1040
0.0120
0.0200
0.0130
0.6140
0.2990
C
D
E
e
1.270
0.100
0.0500
0.0040
H
10.000
0.250
0°
10.650
0.750
8°
0.3940
0.0100
0°
0.4190
0.0300
8°
h
α
L
0.400
1.270
0.0160
0.0500
ddd
Number of pins
24
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 82. 48-pin low profile quad flat package outline
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
α
Pin 1
identification
1
12
c
5B_ME
Table 83. 48-pin low profile quad flat package mechanical data
mm
inches(1)
Dim.
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
9.200
7.200
0.0630
0.0060
0.0570
0.0110
0.0080
0.3622
0.2835
0.050
1.350
0.170
0.090
8.800
6.800
0.0020
0.0530
0.0070
0.0040
0.3465
0.2677
1.400
0.220
0.0551
0.0087
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
9.200
7.200
0.3465
0.2677
0.3622
0.2835
E1
E3
e
L
0.450
0°
0.750
7°
0.0177
0°
0.0295
7°
L1
θ
ccc
0.080
0.0031
Number of pins
48
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
ST7263Bxx
Figure 83. 40-lead very thin fine pitch quad flat no-lead package outline
A
SEATING
A3
PLANE
A1
D
D2
E2
E
PIN #1 ID TYPE C
RADIUS
2
1
L
e
b
Table 84. 40-lead very thin fine pitch quad flat no-lead package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
A3
b
0.800
0.900
0.020
0.650
0.200
0.250
6.000
2.90
1.000
0.050
1.000
0.0315
0.0354
0.0008
0.0260
0.0080
0.0100
0.2360
0.1140
0.2360
0.1140
0.0200
0.0160
0.0394
0.0020
0.0390
0.180
5.850
2.750
5.850
2.750
0.300
6.150
3.050
6.150
3.050
0.0070
0.2300
0.1080
0.2300
0.1080
0.0120
0.2420
0.1200
0.2420
0.1200
D
D2
E
6.000
2.900
0.500
0.400
E2
e
L
0.300
0.500
0.0120
0.0200
Number of pins
40
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
14.2
Thermal characteristics
Table 85. Thermal characteristics
Symbol
Ratings
Value
Unit
Package thermal resistance (junction to
ambient)
SDIP32
SO34
SO24
LQFP48
QFN40
60
75
70
80
34
RthJA
°C/W
PD
Power dissipation(1)
500
150
mW
°C
TJmax
Maximum junction temperature(2)
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation
of an application can be defined by the user with the formula: PD=PINT + PPORT where PINT is the chip
internal power (IDD x VDD) and PPORT the port power dissipation depending on the ports used in the
application.
2. The maximum chip-junction temperature is based on technology characteristics.
14.3
Soldering and glueability information
Recommended glue for SMD plastic packages dedicated to molding compound with
silicone:
●
Heraeus: PD945, PD955
Loctite: 3615, 3298
●
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Device configuration and ordering information
ST7263Bxx
15
Device configuration and ordering information
Each device is available for production in user programmable versions (High Density
FLASH).
ST72F63B FLASH devices are shipped to customers with a default content (FFh).
This implies that FLASH devices have to be configured by the customer using the Option
Byte while the ROM devices are factory-configured.
15.1
Option byte
The Option Byte allows the hardware configuration of the microcontroller to be selected.
The Option Byte has no address in the memory map and can be accessed only in
programming mode using a standard ST7 programming tool. The default contents of the
FLASH is fixed to F7h. This means that all the options have “1” as their default value, except
LVD.
In ROM devices, the Option Byte is fixed in hardware by the ROM code.
Option Byte
7
0
--
--
WDG SW WD HALT
LVD
--
OSC 24/12
FMP_R
OPT 7:6 Reserved
OPT 5 WDGSW Hardware or Software Watchdog
This option bit selects the watchdog type.
0: Hardware enabled
1: Software enabled
OPT 4 WDHALT Watchdog and Halt mode
This option bit determines if a reset is generated when entering Halt mode while the
Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT 3 LVD Low voltage detector selection
This option bit selects the LVD.
0: LVD enabled
1: LVD disabled
Note: Important: on ST7263BK1M1, ST7263BK2M1, ST7263BK2B1, and
ST7263BK2B1 ROM devices, this option bit is forced by ST to 0 (LVD
always enabled).
172/186
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ST7263Bxx
Device configuration and ordering information
OPT 2 Reserved.
OPT 1 OSC24/12 Oscillator Selection
This option bit selects the clock divider used to drive the USB interface at 6MHz.
0: 24 MHz oscillator
1: 12 Mhz oscillator
OPT 0 FMP_R Flash memory readout protection
This option indicates if the user flash memory is protected against readout.
Readout protection, when selected, provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option
bytes when the FMP_R option is selected, causes the whole user memory to be
erased first and the device can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and Section 4.3.1: Readout protection for more
details.
0: Readout protection enabled
1: Readout protection disabled
15.2
Device ordering information and transfer of customer code
Customer code is made up of the ROM contents and the list of the selected options (if any).
The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal
file in .S19 format generated by the development tool. All unused bytes must be set to FFh.
The selected options are communicated to STMicroelectronics using the correctly
completed option list appended (see Section 15.2).
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
The STMicroelectronics Sales Organization will be pleased to provide detailed information
on contractual points.
Table 86. Supported order codes
Program memory
(bytes)
RAM
(bytes)
Sales type(1)(2)
Package
LQFP48
ST72F63BH6T1
ST72F63BD6U1
ST72F63BK6M1
ST72F63BK6B1
ST72F63BE6M1
ST72F63BH4T1
ST72F63BK4M1
ST72F63BK4B1
ST72F63BE4M1
QFN40
SO34
32K Flash
1024
512
SDIP32
SO24
LQFP48
SO34
16K Flash
SDIP32
SO24
Doc ID 7516 Rev 8
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Device configuration and ordering information
Table 86. Supported order codes (continued)
ST7263Bxx
Program memory
(bytes)
RAM
(bytes)
Sales type(1)(2)
Package
LQFP48
ST72F63BH2T1
ST72F63BK2U1
ST72F63BK2M1
ST72F63BK2B1
ST72F63BE2M1
ST72F63BK1M1
ST72F63BK1B1
ST72F63BE1M1
ST7263BK2M1/xxx
ST7263BK2B1/xxx
ST7263BK1M1/xxx
ST7263BK1B1/xxx
QFN40
SO34
8K Flash
384
384
SDIP32
SO24
SO34
4K Flash
SDIP32
SO24
SO34
8K ROM
4K ROM
384
384
SDIP32
SO34
SDIP32
1. /xxx stands for the ROM code name assigned by STMicroelectronics.
2. Contact ST sales office for FASTROM product availability.
15.3
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
15.3.1
Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow
you to evaluate microcontroller features and quickly start developing ST7 applications.
Starter kits are complete, affordable hardware/software tool packages that include features
and samples to to help you quickly start developing your application. ST evaluation boards
are open-design, embedded systems, which are developed and documented to serve as
references for your application design. They include sample application software to help you
demonstrate, learn about and implement your ST7’s features.
15.3.2
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to 16K of
code.
The range of hardware tools includes full-featured ST7-EMU3 series emulators and the
low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7
Toolset from STMicroelectronics, which includes the STVD7 integrated development
174/186
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ST7263Bxx
Device configuration and ordering information
environment (IDE) with high-level language debugger, editor, project manager and
integrated programming interface.
15.3.3
Programming tools
During the development cycle, the ST7-EMU3 series emulators and the RLink provide in-
circuit programming capability for programming the Flash microcontroller on your application
board.
In addition ST provides dedicated programming tools including the ST7-EPB programming
boards, which include all the sockets required to program any of the devices in a specific
ST7 sub-family.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
15.3.4
Order codes for ST7263Bx development tools
Table 87. Development tool order codes for the ST7263Bx family
Evaluation
board
In-circuit
Dedicated
MCU
Starter kit
Emulator
debugger/programmer programmer
ST72F63B- ST7MDTULS ST7MDTU3-
SK/RAIS -EVAL EMU3
ST7MDTU3-
ST7263Bx
STX-RLINK
EPB
For additional ordering codes for spare parts and accessories, refer to the online product
selector at www.st.com/mcu.
Doc ID 7516 Rev 8
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Device configuration and ordering information
Figure 84. Option list
ST7263Bxx
ST7263B MICROCONTROLLER OPTION LIST
(Last update: May 2009)
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROM code must be sent in .S19 format.
Hex extension cannot be processed.
STMicroelectronics references:
Device Type/Memory Size/Package (check only one option):
------------|----------------|----------------|----------------|----------------
|ROM DEVICE: |
4K
|
8K
|
16K
|
32K
|
-------------|----------------|----------------|----------------|----------------|
SDIP32:
SO34:
|[ ] ST7263BK1B1 |[ ] ST7263BK2B1 |
|[ ] ST7263BK1M1 |[ ] ST7263BK2M1 |
|
|
|
|
-------------|----------------|----------------|----------------|----------------|
FLASH
|
4K
|
8K
|
16K
|
32K
|
-------------|----------------|----------------|----------------|----------------|
SO24:
|[ ] ST72F63BE1M1|[ ] ST72F63BE2M1|[ ] ST72F63BE4M1|[ ] ST72F63BE6M1|
|[ ] ST72F63BK1B1|[ ] ST72F63BK2B1|[ ] ST72F63BK4B1|[ ] ST72F63BK6B1|
|[ ] ST72F63BK1M1|[ ] ST72F63BK2M1|[ ] ST72F63BK4M1|[ ] ST72F63BK6M1|
SDIP32:
SO34:
QFN40
|
|
|[ ] ST72F63BK2U1|
|[ ] ST72F63BD6U1|
LQFP48:
|[ ] ST72F63BH2T1|[ ] ST72F63BH4T1|[ ] ST72F63BH6T1|
-------------|----------------|----------------|----------------|----------------|
DIE FORM:
|
4K
|
8K
|
16K
|
32K
|
-------------|----------------|----------------|----------------|-----------------|
24-pin:
32-pin:
34-pin:
40-pin:
48-pin:
|[ ] (as E1M1)
|[ ] (as E2M1)
|[ ] (as K2B1)
|[ ] (as K2M1)
|[ ] (as H2U1)
|[ ] (as H2T1)
|[ ] (as E4M1)
|[ ] (as K4B1)
|[ ] (as K4M1)
|
|[ ] (as E6M1)
|[ ] (as K6B1)
|[ ] (as K6M1)
|[ ] (as D6U1)
|[ ] (as H6T1)
|
|
|
|
|
|[ ] (as K1B1)
|[ ] (as K1M1)
|
|
|[ ] (as H4T1)
Conditioning (check only one option)
--------------------------------------|-----------------------------------------
Packaged Product | Die Product (dice tested at 25°C only) |
:
--------------------------------------|-----------------------------------------
[ ] Tape & Reel (SO package only)
[ ] Tube
| [ ] Tape & Reel
| [ ] Inked wafer
| [ ] Sawn wafer on sticky foil
Special Marking ( ROM only): [ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _"
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
For marking, one line is possible with a maximum of 13 characters.
Watchdog Selection:
Halt when Watchdog on:
LVD Reset *
[ ] Software activation [ ] Hardware activation
[ ] Reset
[ ] No reset
[ ] Enabled*
[ ] Disabled*
* LVD is forced to 0 (LVD always enabled) for 4K and 8K ROM devices
(sales types ST7263BK1B1, ST7263BK2B1, ST7263BK1M1, ST72BK2M1 only)
Oscillator Selection:
Readout Protection:
[ ] 24 MHz.
[ ] Disabled
[ ] 12 MHz.
[ ] Enabled
Date
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
Signature
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Device configuration and ordering information
15.4
ST7 application notes
Table 88. ST7 application notes
Identification
Description
Application examples
AN1658
AN1720
AN1755
AN1756
Serial Numbering Implementation
Managing the Readout Protection in Flash Microcontrollers
A High Resolution/precision Thermometer Using ST7 and NE555
Choosing a DALI Implementation Strategy with ST7DALI
A High Precision, Low Cost, Single Supply ADC for Positive and Negative input
Voltages
AN1812
Example drivers
AN 969
AN 971
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI Communication Between ST7 and PC
I²C Communication Between ST7 and M24Cxx EEPROM
SCI Software Communication with a PC Using ST72251 16-Bit Timer
Real Time Clock with ST7 Timer output Compare
Driving a Buzzer Through ST7 Timer PWM Function
Driving an Analog Keyboard with the ST7 ADC
ST7 Keypad Decoding Techniques, Implementing wakeup on Keystroke
Using the ST7 Universal Serial Bus Microcontroller
Using ST7 PWM Signal to Generate Analog output (Sinusoïd)
ST7 Routine for I²C Slave mode Management
Multiple Interrupt Sources Management for ST7 MCUs
ST7 S/W Implementation of I²C Bus Master
UART Emulation Software
Managing Reception Errors with the ST7 SCI Peripherals
ST7 Software LCD Driver
PWM Duty Cycle Switch Implementing True 0% & 100% Duty Cycle
Description of the ST72141 Motor Control Peripherals registers
ST72141 BLDC Motor Control Software and Flowchart Example
ST7 pCAN Peripheral Driver
PWM Management for BLDC Motor Drives Using the ST72141
An Introduction to Sensorless Brushless DC Motor Drive Applications with the
ST72141
AN1130
AN1148
AN1149
AN1180
Using the ST7263 for Designing a USB Mouse
Handling Suspend mode on a USB Mouse
Using the ST7263 Kit to Implement a USB Game Pad
Doc ID 7516 Rev 8
177/186
Device configuration and ordering information
Table 88. ST7 application notes (continued)
ST7263Bxx
Identification
Description
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
BLDC Motor Start Routine for the ST72141 Microcontroller
Using the ST72141 Motor Control MCU in Sensor mode
Using the ST7 USB LOW-SPEED Firmware V4.x
Emulated 16-bit Slave SPI
Developing an ST7265X Mass Storage Application
Starting a PWM Signal Directly at High Level Using the ST7 16-bit Timer
16-bit Timing Operations Using ST7262 or ST7263B ST7 USB MCUs
Device Firmware Upgrade (DFU) Implementation in ST7 Non-USB Applications
Generating a High Resolution Sinewave Using ST7 PWMART
SMBus Slave Driver for ST7 I2C Peripherals
Software UART Using 12-bit ART
ST7MC PMAC Sine Wave Motor Control Software Library
General purpose
AN1476
AN1526
AN1709
AN1752
Low Cost Power Supply for Home Appliances
ST7FLITE0 Quick Reference Note
EMC Design for ST Microcontrollers
ST72324 Quick Reference Note
Product evaluation
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
Performance Benchmarking
ST7 Benefits vs Industry Standard
Overview of Enhanced CAN Controllers for ST7 and ST9 MCUs
U435 Can-Do Solutions for Car Multiplexing
Improved B-EMF detection for Low Speed, Low Voltage with ST72141
Benchmark ST72 vs PC16
Performance Comparison Between ST72254 & PC16F876
LIN (Local Interconnect Network) Solutions
Product migration
AN1131
AN1322
AN1365
AN1604
AN2200
Migrating Applications from ST72511/311/214/124 to ST72521/321/324
Migrating an Application from ST7263 Rev.B to ST7263B
Guidelines for Migrating ST72C254 Applications to ST72F264
How to Use ST7MDT1-TRAIN with ST72F264
Guidelines for Migrating ST7LITE1x Applications to ST7FLITE1xB
Product optimization
AN 982 Using ST7 with Ceramic Resonator
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ST7263Bxx
Device configuration and ordering information
Table 88. ST7 application notes (continued)
Identification
Description
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
How to Minimize the ST7 Power Consumption
Software Techniques for Improving Microcontroller EMC Performance
Monitoring the Vbus Signal for USB Self-Powered Devices
ST7 Checksum Self-Checking Capability
Electrostatic Discharge Sensitive Measurement
Calibrating the RC Oscillator of the ST7FLITE0 MCU Using the Mains
Emulated Data EEPROM with ST7 HDFLASH Memory
Extending the Current & Voltage Capability on the ST7265 VDDF Supply
Accurate Timebase for Low-cost ST7 Applications with Internal RC Oscillator
Using an Active RC to Wakeup the ST7LITE0 from Power Saving mode
Understanding and Minimizing ADC Conversion Errors
PIR (Passive Infrared) Detector Using the ST7FLITE05/09/SUPERLITE
Sensorless BLDC Motor Control and BEMF Sampling Methods with ST7MC
PFC for ST7MC Starter Kit
ST7LITE0 Microcontrolled Ballast
Programming and tools
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN1039
AN1071
AN1106
ST7 Visual DeVELOP Software Key Debugging Features
Key Features of the Cosmic ST7 C-Compiler Package
Executing Code In ST7 RAM
Using the Indirect Addressing mode with ST7
ST7 Serial Test Controller Programming
Starting with ST7 Assembly Tool Chain
ST7 Math Utility Routines
Half Duplex USB-to-Serial Bridge Using the ST72611 USB Microcontroller
Translating Assembly Code from HC05 to ST7
Programming ST7 Flash Microcontrollers in Remote ISP mode (In-situ
Programming)
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
Using the ST72521 Emulator to Debug an ST72324 Target Application
Emulated Data EEPROM with Xflash Memory
Developing a USB Smartcard Reader with ST7SCR
On-Board Programming Methods for XFLASH and HDFLASH ST7 MCUs
In-application Programming (IAP) Drivers for ST7 HDFLASH or XFLASH MCUs
Device Firmware Upgrade (DFU) Implementation for ST7 USB Applications
Software Implementation for ST7DALI-EVAL
Using the ST7 USB Device Firmware Upgrade Development Kit (DFU-DK)
Doc ID 7516 Rev 8
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Device configuration and ordering information
Table 88. ST7 application notes (continued)
ST7263Bxx
Identification
Description
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
ST7 Customer ROM Code Release Information
Data Logging Program for Testing ST7 Applications via I2C
Field Updates for FLASH Based ST7 Applications Using a PC Comm Port
Hardware Implementation for ST7DALI-EVAL
ST7MC Three-phase AC Induction Motor Control Software Library
ST7MC Three-phase BLDC Motor Control Software Library
System Optimization
AN1711
AN1827
AN2009
AN2030
Software Techniques for Compensating ST7 ADC Errors
Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
PWM Management for 3-Phase BLDC Motor Drives Using the ST7FMC
Back EMF Detection During PWM On Time by ST7MC
180/186
Doc ID 7516 Rev 8
ST7263Bxx
Known limitations
16
Known limitations
16.1
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F63Bxxxxx$x7);
it has been corrected in Rev W Flash devices (with Internal Sales Type 72F63Bxxxxx$x9).
Note:
Refer to Figure 85 on page 183
When output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, PA2 is switched to its alternate function mode, SCL. As a consequence, the
2
PA2 pin is forced to be floating (steady level of I C clock) even if port configuration
(PADDR+PADR) has set it as output low. However, it can be still used as an input or can be
2
2
controlled by the I C cell when enabled (where I C is available).
16.2
Unexpected RESET fetch
Description
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
16.3
16.4
USB behavior with LVD disabled
Description
If the LVD is disabled on 4K and 8K ROM devices (ST7263BK1M1, ST72BK2M1,
ST7263BKB1, ST7263BK2B1 only), the USB is disabled by hardware. The LVD is
consequently forced by ST to ‘0’ (LVD enabled). Refer to the ST7263Bx option list for details.
I2C multimaster
Description
2
2
In multimaster configurations, if the ST7 I C receives a START condition from another I C
master after the START bit is set in the I2CCR register and before the START condition is
2
2
generated by the ST7 I C, it may ignore the START condition from the other I C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a re-start and Slave address to re-initiate communication
Doc ID 7516 Rev 8
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Known limitations
ST7263Bxx
16.5
Halt mode power consumption with ADC on
Description
If the A/D converter is being used when Halt mode is entered, the power consumption in
Halt mode may exceed the maximum specified in the datasheet.
Workaround
Switch off the ADC by software (ADON=0) before executing a HALT instruction.
16.6
SCI wrong BREAK duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (fCPU=8MHz and SCIBRR=0xC9), the wrong break duration
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
1. Disable interrupts
2. Reset and Set TE (IDLE request)
3. Set and Reset SBK (Break Request)
4. Re-enable interrupts
182/186
Doc ID 7516 Rev 8
ST7263Bxx
Known limitations
Figure 85. Identifying silicon revision from device marking and box label
The silicon revision can be identified either by Rev letter or obtained via a trace code.
1. Identify the silicon revision letter from either the device package or the box label.
For example, “B”, etc.
2. If the revision letter is not present, obtain the silicon revision by contacting your local
ST office with the trace code information printed on either the box label or the device
Silicon Rev
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Trace code
ST7xxxxxxxxx
TYPE
xxxxxxxxxxx$x7
XX
Total Qty
XXXXXXXXX XX XX
Trace code
Marking XXXXXXXXXX
Bulk ID
B
Silicon Rev
XXXXXXXXXXXX
Device package (SO34 shown)
Example box label
Doc ID 7516 Rev 8
183/186
Revision history
ST7263Bxx
17
Revision history
Table 89. Document revision history
Date
Revision
Changes
New revision created by merging 32K Flash and non-32K Flash
datasheets together. Memory Map, Figure 7, expanded to handle all
devices and memory sizes. Operating conditions with LVD values
modified, Section 13.3.1: Operating conditions with low voltage
detector (LVD).
Supply current characteristics values and notes updated,
Section 13.4: Supply current characteristics. IDD Run and Wait
graphs replaced, Figure 55 and Figure 56 on page 143. Control
timing characteristics modified, Section Table 62.: Control timing
characteristics. Flash memory table notes and tPROG typical value
updated, Section 13.6.1: Flash memory. Notes added for I/O Port
Pin Characteristics table, Section Table 70.: General characteristics.
Note for RPU modified, removing reference to data characterization,
Section Table 70. IPU and RPU graphs added, Figure 61 and
Figure 62 on page 150. Notes updated for USB low speed electrical
characteristics. Output voltage/current graphs added, Figures Figure
63.-Figure 72.Thermal Characteristics added for SO24 and TQFP48
packages, Section 14.2: Thermal characteristics. Important note
added for OPT 3 Option Byte (LVD), Section 15.1: Option byte.
27-May-05
3
Supported Part Numbers table updated with full sales type codes,
Table 86. Option List updated with all device options.
Important notes updated with ‘USB behavior with LVD disabled’,
Section 16.3: USB behavior with LVD disabled. Clock block diagram
redrawn, Figure 18 on page 36. DFU added to title and features list.
Removed unnecessary notes related to Typical Values (already
mentioned in Section 13.1.2: Typical values) in electrical
characteristic tables sections: Section 13.3.1, Section 13.4,
Section 13.6.1, Section Table 70., Section Table 72. and
Section 13.11. Added note for max values in ADC Accuracy,
Section 13.11. Static Latch Up (LU) class tested only for TA=25°C,
Section : Static latchup (LU)
Flash memory minimum data retention increased to 40 years,
Section 13.6.1: Flash memory
AF bit text modified concerning SCL, I2C chapter Section 11.5.7:
Register description
Reference made to the Flash Programming Reference Manual for
Flash timing values
19-Sep-05
4
Reset pulse generated by WDG changed to 30 µs, Section 11.1:
Watchdog timer (WDG)
Modified text in Section 11.3: Serial communications interface (SCI),
adding Parity error as an interrupt
Added ECOPACK information in Section 14: Package characteristics
Modified IS value and corresponding note in Section Table 70.:
General characteristics
32K and 8K QFN40 Packages added
4K SO24 Package added
06-Apr-06
5
TQFP package renamed to LQFP
184/186
Doc ID 7516 Rev 8
ST7263Bxx
Revision history
Table 89. Document revision history (continued)
Date
Revision
Changes
Important Notes section renamed to Known Limitations, Section 16:
Known limitations
New PA2 limitation added, Section 16: Known limitations
Figure 85 on page 183 added for silicon revision identification
03-Oct-06
6
New 16K LQFP48 package added to product family.
Note added to VOH data in Section Table 71.: Output driving current
List of supported partnumber availability updated, Table 86
20-Aug-07
7
Download address updated in Section 15.3.4: Order codes for
ST7263Bx development tools and Option list.
Removed FASTROM devices as well as 32 and 16 Kbyte ROM
devices.
Added caution note in Section 6.1: Reset.
Replaced CCR by CC (Condition Code) register when the I bit is
concerned.
Updated alternate function condition for PB4 to PB7 in Table 13: Port
B description.
Renamed tDOG and TDOGL, tWDG and tWDGL
.
Removed EMC protective circuitry in Figure 74: RESET pin
protection when LVD is disabled (device works correctly without
these components).
12-Jun-2009
8
Removed all mentions to SPI interface.
Removed dynamic latchup in Section 13.7.3: Absolute maximum
ratings (electrical sensitivity).
Modified notes below Table 85: Thermal characteristics.
Update Table 86: Supported order codes and Figure 84: Option list.
Updated ECOPACK text, and removed recommended wave
soldering profile and recommended reflow soldering oven profile, in
Section 14: Package characteristics.
Doc ID 7516 Rev 8
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ST7263Bxx
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Doc ID 7516 Rev 8
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