ST72681 [STMICROELECTRONICS]
USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER; USB 2.0高速8位单片机闪存驱动器控制器
| 型号： | ST72681 |
| 厂家： | 
ST |
| 描述： | USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER |
| 文件： | 总12页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72681
USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE
CONTROLLER
PRELIMINARY DATA
■ USB 2.0 Interface compatible with Mass
Storage Device Class
– Integrated USB 2.0 PHY
– Supports USB High Speed and Full Speed
– Suspend and Resume operations
■ Mass Storage Controller Interface (MSCI)
– Supports all type of NAND Flash devices
– Reed-Solomon Encoder/Decoder for MLC
NAND Flash support: on-the-fly correction (4
bytes of a 512-byte block)
– Flash identification support
TQFP48
– 10MB/s for read and 8MB/s for write opera-
tions with one single NAND Flash device
– 10MB/s for read and 10MB/s for write opera-
tions in multi mode NAND Flash device topol-
ogy
■ Data Protection
– Write protect switch control
– Password-based security for data protection
■ Bootability support
■ Embedded ST7 8-bit MCU
■ Supply Management
■ Flexibility
– 3.3V operation
– Integrated 3.3V-1.8V voltage regulator
■ Very low power consumption
– Configurable Vendor ID/Product ID (VID/PID)
with production tool
– Patch code support with external EEPROM
device
■ TQFP48 7x7 lead-free package
– Less than 100mA during write operation with
two NAND Flash devices
– Less than 500µA in suspend mode
■ Clock Management
■ Development Support
– Complete reference design including sche-
matics, BOM and gerber files
■ Supports Windows ME, Windows 2K,
Windows XP, Linux and MacOS. Drivers
available for Windows 98 SE
– Integrated PLL for generating core and USB
2.0 clock sources using an external 12 MHz
crystal
■ Up to two configurable LED outputs
– Blinking on USB specific activity (idle, sus-
pend, data access)
Features
ST72681
USB interface
# of NAND devices supported
USB 2.0
up to 4
R/W speed
10MBps/8MBps (single NAND) / 10MBps/10MBps (multi NAND)
Operating Supply
Operating Temperature
Packages
3.0V to 3.6V
0°C to +70°C
TQFP48 7x7 / Die form
Rev. 1.1
1/12
May 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1
ST72681
1 INTRODUCTION
The ST72681 is a USB 2.0 high-speed Flash Drive
controller. The USB 2.0 high-speed interface in-
cluding PHY and function supports USB 2.0 Mass
Storage Device Class.
The internal 60 MHz PLL driven by the 12MHz os-
cillator is used to generate the 480MHz frequency
for the USB 2.0 PHY.
The ST7 8-bit CPU runs the application program
from the internal ROM and RAM. USB data and
patch code are stored in internal RAM.
The Mass Storage Controller Interface combined
with the Reed-Solomon Encoder/Decoder on-the-
fly correction (4-byte on 512-byte data blocks) pro-
vides a flexible, high transfer rate solution for inter-
facing a wide of range NAND Flash memory de-
vice types.
I/O ports provide functions for EEPROM connec-
tion, LEDs and write protect switch control.
The internal 3.3V to 1.8V voltage regulator pro-
vides the 1.8V supply voltage to the digital part of
the circuit.
Figure 1. Device Block Diagram
8-bit
CPU
12 MHz
OSC
ROM
RAM
Reed-
Mass
NAND
I/F
Solomon
Storage
Controller
Interface
USB 2.0
PHY
USB 2.0
Function
Error
Correction
3.3V to 1.8V
Voltage
Regulator
GPIO
2/12
1
ST72681
2 PIN DESCRIPTION
Figure 2. 48-Pin TQFP Package Pinout
48 47 46 45 44 43 42 41 40 39 38 37
NAND WP
VDDA
OSCIN
OSCOUT
VSSA
36
1
2
3
4
5
6
7
8
9
10
READ ONLY
EEPROM SCL
35
34
33
32
31
30
29
28
27
26
25
VSS_2
RREF
VDD33_2
VSSC
NC*
NC*
ST72681
VDDC
VDD3
RESET
LED2
USBDP
USBDM
VSSBL
VDDBL
LED1
NAND ALE/EEPROM SDA
VSS_3
11
12
24
13 14 15 16 17 18 19 20 21 22 23
* must remain NOT connected in the application
3/12
1
ST72681
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for tables:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
T = TTL 0.8V / 2V with Schmitt trigger
T
Output level:
D8 = 8mA drive
D4 = 4mA drive
D2 = 2mA drive
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt
OD = pseudo open drain, PP = push-pull
– Output:
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. Power Supply
Pin
Pin Name
Description
48 VSS_1
S
S
S
S
S
S
S
S
S
Ground
47 VDD33_1
33 VSS_2
IOs and Regulator supply voltage
Ground
32 VDD33_2
25 VSS_3
IOs and Regulator supply voltage
Ground
24 VDD33_3
14 VSS_4
IOs and Regulator supply voltage
Ground
15 VDD33_4
13 VDDOUSB
IOs and Regulator supply voltage
USB2 PHY, OSC and PLL power supply output (1.8V)
Table 2. Control & System
Pin
Level
Pin Name
Description
29 RESET
I/O 3.3 C
Reset input with filter with internal pull-up
T
4/12
ST72681
PIN DESCRIPTION (Cont’d)
Table 3. USB 2.0 Interface
Pin
Pin Name
Description
12 VDDBL
11 VSSBL
10 USBDM
S
S
Supply voltage for buffers and deserialisation flip flops (1.8V)
Ground for buffers and deserialisation flip flops (1.8V)
I/O USB2 DATA -
I/O USB2 DATA +
9
8
7
6
5
USBDP
VDD3
VDDC
VSSC
RREF
S
S
S
Supply voltage for the FS compliance (3.3V)
Supply voltage for DLL & xor tree (1.8V)
Ground for DLL & XOR tree (1.8V)
I/O Ref. resistor for integrated impedance process adaptation (11.3 kOhms 1% Pull Down)
Table 4. USB 2.0 and core Clock System
Pin
Pin Name
Description
4
3
2
1
VSSA
S
O
I
Ground for osc & PLL (1.8V)
12MHz oscillator output
OSCOUT
OSCIN
VDDA
12MHz oscillator input
S
Supply voltage for osc & PLL (1.8V)
5/12
ST72681
PIN DESCRIPTION (Cont’d)
Table 5. General Purpose IO Ports / Mass Storage IOs
Pin
Level
Alternate
function
Main
function
Pin Name
(after reset)
45 NAND D[0]
44 NAND D[1]
43 NAND D[2]
42 NAND D[3]
41 NAND D[4]
40 NAND D[5]
39 NAND D[6]
38 NAND D[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T
T
T
T
T
T
T
T
D4 NAND DATA [0]
D4 NAND DATA [1]
T
T
T
T
T
T
T
T
D4 NAND DATA [2]
D4 NAND DATA [3]
D4 NAND DATA [4]
D4 NAND DATA [5]
D4 NAND DATA [6]
D4 NAND DATA [7]
NAND ALE /
26
I/O
O
T
T
D8 NAND ADDRESS LATCH ENABLE EEPROM SERIAL DATA
T
T
EEPROM SDA
NAND COMMAND LATCH ENA-
22 NAND CLE
D8
BLE
21 NAND WE
20 NAND RE
19 NAND CE1
18 NAND CE2
17 NAND CE3
16 NAND CE4
37 NAND RnB
36 NAND WP
35 READ ONLY
34 EEPROM SCL
28 LED2
O
O
O
O
O
O
I
T
T
T
T
T
T
T
T
T
T
T
T
D8 NAND WRITE ENABLE
D8 NAND READ ENABLE
D4 NAND ENABLE 1
T
T
T
T
T
T
T
T
T
T
T
T
D4 NAND ENABLE 2
D4 NAND ENABLE 3
D4 NAND ENABLE 4
D2 NAND READY/BUSY
D2 NAND WRITE PROTECT
D2 READ ONLY SWITCH
D2 EEPROM SERIAL CLOCK
D8 GREEN LED (USB ACCESS)
D8 RED LED (NAND ACCESS)
O
I
O
O
O
27 LED1
6/12
ST72681
3 NAND FLASH DEVICE SUPPORT
Program Page Size
(in Bytes)
Type
Memory size
Samsung K9F2808U0C-Y
Samsung K9F5608U0C-Y
Samsung K9F1208U0A-Y
Toshiba TC58512FT
16M x 8b
32M x 8b
64M x 8b
64M x 8b
64M x 8b
128M x 8b
128M x 8b
256M x 8b
16M x 8b
32M x 8b
64M x 8b
128M x 8b
16M x 8b
32M x 8b
64M x 8b
128M x 8b
256M x 8b
256M x 8b
512M x 8b
512M x 8b
1G x 8b
528
528
528
528
Toshiba TC58DVM92A
Toshiba TC58DVG02A
Toshiba TC58DVG04B1FT00
Toshiba TC58DVG14B1FT00
ST NAND128W3A
528
528
528
528
528
ST NAND256W3A
528
ST NAND512W3A
528
ST NAND01GW3A
528
Hynix HY27US08281M
Hynix HY27US08561M
Hynix HY27US08121M
Samsung K9F1G08U0M-Y
Samsung K9F2G08U0M-Y
Samsung K9K2G08U0M-Y
Samsung K9K4G08U0M-Y
Samsung K9W4G08U1
Samsung K9W8G08U1
Toshiba TH58NVG0S3
Toshiba TH58NVG1S3
Toshiba TH58NVG2S3
ST NAND01GW3B
528
528
528
2112
2112
2112
2112
2112
2112
2112
2112
2112
2112
2112
2112
2112
128M x 8b
256M x 8b
512M x 8b
128M x 8b
256M x 8b
128M x 8b
256M x 8b
ST NAND02GW3B
Hynix HY27UA081G1M
Micron 29F2G08AA
7/12
ST72681
4 APPLICATION SCHEMATICS
Figure 3. Application Schematic Sheet 1/2
1
2
3
4
5
6
7
8
D
C
B
A
D
C
B
A
V33
V33
C12
10nF
C13
10nF
C14
10nF
C15
10nF
USB_V5
U1
Vin
1
2
3
5
4
Vout
GND
C8
4.7uF
+
INHIBIT BYPASS
LD3985M33R_SOT23-5L
C1
10nF
C10
220nF
NAND
NAND Sheet
NAND_VCC
R1
4.7K
NAND_RnB
V33
NAND_WP
S1
Read Only
U2ST72
R2
10K
V18_USB
C20
USB_V5
36
35
34
33
32
31
30
29
NAND WP
READ ONLY
EEPROM SCL
VSS_2
VDD33_2
NC
NC
XT1
CRYSTAL 12MHz_M49-12.000
18pF
V18_USB
1
2
3
4
5
6
7
8
9
VDDA
OSCIN
OSCOUT
VSSA
RREF
VSSC
VDDC
VDD3
USBDP
USBDM
VSSBL
VDDBL
V33
C21
NAND_VCC
C2
100nF
C19
1uF
C3
ST72681
RESET
RESET
R3
18pF
100nF
U3
E0 VCC
E1 nWC
E2 SCL
VSS SDA
R6
18K
11.3K 1%
28
27
PE2
PE3
V33
DP
DM
LED2
LED1
10
11
12
NAND_ALE
J1
VBUS
26
25
NAND_ALE
NAND ALE/EEPROM SDA
VSS_3
1
2
3
4
M24C32W_TSSOP8
D-
D+
GND
V18_USB
USB CON
R4
220
R5
220
C16
10nF
C17
10nF
C18
10nF
C22
470nF
LED1
RED LED
LED2
GREEN LED
V33
V33
Title
PFD/Ref 1B CPU
Number
Size
A3
Revision
1B
Release 1
1 2
Sheet of
Date:
File:
20-May-2005
7
Drawn By:
1
2
3
4
5
6
8
8/12
ST72681
Figure 4. Application Schematic Sheet 2/2
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC/#RES
NC
NC
NC
NC
GND/RB2/NC
#R/B
#RE
#CE
NC/#CE2
NC
NC
NC
NC
NC
I/O 7
I/O 6
I/O 5
I/O 4
NC
D7
D6
D5
D4
GND/NAND_RnB2
NAND_RnB
NAND_RE
NAND_CE1
NAND_CE3 10
11
NC
NC/PRE
VCC
VSS
NC
NC
NC
I/O 3
I/O 2
I/O 1
I/O 0
NC
12
13
14
15
VCC
VSS
NC
NC
NAND_CLE 16
NAND_ALE 17
NAND_WE 18
NAND_WP 19
CLE
ALE
#WE
#WP
NC
NC
NC
NC
NC
D3
D2
D1
D0
20
21
22
23
24
NC
NC
NC
NAND_FLASH_TSOP48
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC/#RES
NC
NC
NC
NC
GND/RB2/NC
#R/B
#RE
#CE
NC/#CE2
NC
NC
NC
NC
NC
I/O 7
I/O 6
I/O 5
I/O 4
NC
D7
D6
D5
D4
NAND_RnB2
NAND_RnB
NAND_RE
NAND_CE2
NAND_CE4 10
11
NC
NC/PRE
VCC
VSS
NC
NC
NC
I/O 3
I/O 2
I/O 1
I/O 0
NC
12
13
14
15
VCC
VSS
NC
NC
NAND_CLE 16
NAND_ALE 17
NAND_WE 18
NAND_WP 19
CLE
ALE
#WE
#WP
NC
NC
NC
NC
NC
D3
D2
D1
D0
20
21
22
23
24
NC
NC
NC
NAND_FLASH_TSOP48
9/12
ST72681
5 PACKAGE MECHANICAL DATA
Figure 5. 48-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
e
E1
E
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
48
L
θ
L1
N
10/12
ST72681
6 REVISION HISTORY
Table 6. Revision History
Date
Revision
Description of Changes
Changed status of the document
Changed description on 1st page
Removed unconnected pins in Table 5 on page 6
Changed Table 4, “USB 2.0 and core Clock System,” on page 5
Changed pin 5 description in Table 3, “USB 2.0 Interface,” on page 5
Changed section 3 on page 7
May-2005
1.1
Changed Figure 3 and Figure 4
11/12
ST72681
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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