ST72F262G2B5_技术文档

ST72260Gx, ST72262Gx,

ST72264Gx

8-BIT MCU WITH FLASH OR ROM MEMORY,

ADC, TWO 16-BIT TIMERS, I²C, SPI, SCI INTERFACES

■ Memories

– 4 K or 8 Kbytes Program memory: ROM or

Single voltage extended Flash (XFlash) with

read-out protection write protection and In-

Circuit Programming and In-Application Pro-

gramming (ICP and IAP). 10K write/erase cy-

cles guaranteed, data retention: 20 years at

55°C.

– 256 bytes RAM

■ Clock, Reset and Supply Management

SDIP32

– Enhanced reset system

– Enhanced low voltage supply supervisor

(LVD) with 3 programmable levels and auxil-

iary voltage detector (AVD) with interrupt ca-

pability for implementing safe power-down

procedures

SO28

LFBGA 6x6mm

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock

– PLL for 2x frequency multiplication

– Clock-out capability

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and Pulse generator modes

■ 3 Communication Interfaces

– SPI synchronous serial interface

– 4 Power Saving Modes: Halt, Active Halt,Wait

2

– I C multimaster interface (SMBus V1.1 Com-

and Slow

pliant)

■ Interrupt Management

– SCI asynchronous serial interface

■ 1 Analog peripheral

– 10-bit ADC with 6 input channels

■ Instruction Set

– Nested interrupt controller

– 10 interrupt vectors plus TRAP and RESET

– 22 external interrupt lines (on 2 vectors)

■ 22 I/O Ports

– 8-bit data manipulation

– 22 multifunctional bidirectional I/O lines

– 20 alternate function lines

– 8 high sink outputs

– 63 basic instructions with illegal opcode de-

tection

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

■ Development Tools

■ 4 Timers

– Main Clock Controller with Real time base and

Clock-out capabilities

– Full hardware/software development package

– Configurable watchdog timer

Device Summary

Features

ST72260G1

ST72262G1 ST72262G2 ST72264G1

ST72264G2

Program memory - bytes

RAM (stack) - bytes

4K

8K

4K

8K

256 (128)

Watchdogtimer,RTC,

Watchdog timer, RTC,

Two 16-bit timers, SPI, SCI, I C, ADC

Peripherals

2

Two16-bit timers, SPI Two 16-bit timers, SPI, ADC

2.7 V to 5.5 V

Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 MHz

Operating Supply

CPU Frequency

0° C to +70° C /

-40° C to +85° C

Operating Temperature

Packages

-40° C to +85° C

SO28 / SDIP32

-40° C to +85° C

SO28 / SDIP32

LFBGA

Rev. 3

June 2005

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1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

172

9.8 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Table of Contents

10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53

11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 153

13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

14.3 LEAD-FREE PACKAGE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 162

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 164

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

16.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

16.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

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ST72260Gx, ST72262Gx, ST72264Gx

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please note that the list of known limitations can be found at the end of this document on page 168.

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ST72260Gx, ST72262Gx, ST72264Gx

1 INTRODUCTION

The ST72260Gx, ST72262Gx and ST72264Gx

devices are members of the ST7 microcontroller

family. They can be grouped as follows :

Under software control, all devices can be placed

in WAIT, SLOW, Active-HALT or HALT mode, re-

ducing power consumption when the application is

in idle or stand-by state.

– ST72264Gx devices are designed for mid-range

2

applications with ADC, I C and SCI interface ca-

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

pabilities.

– ST72262Gx devices target the same range of

2

applications but without I C interface or SCI.

– ST72260Gx devices are for applications that do

2

not need ADC, I C peripherals or SCI.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set.

For easy reference, all parametric data is located

in Section 13 on page 126.

The ST72F260G, ST72F262G, and ST72F264G

versions feature single-voltage FLASH memory

with byte-by-byte In-Circuit Programming (ICP)

capabilities.

Related Documentation

AN1365: Guidelines for migrating ST72C254 ap-

plications to ST72F264

Figure 1. General Block Diagram

Internal

CLOCK

2

I C*

OSC1

MULTI OSC

OSC2

SCI*

PA7:0

(8 bits)

MCC/RTC

LVD

PORT A

ICD

V

DD

POWER

SUPPLY

V

SS

SPI

PB7:0

(8 bits)

RESET

CONTROL

PORT B

16-BIT TIMER A

PORT C

8-BIT CORE

ALU

PROGRAM

MEMORY

(4 or 8K Bytes)

PC5:0

(6 bits)

10-BIT ADC*

16-BIT TIMER B

WATCHDOG

RAM

(256 Bytes)

*Not available on some devices, see device summary on page 1.

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ST72260Gx, ST72262Gx, ST72264Gx

2 PIN DESCRIPTION

Figure 2. 28-Pin SO Package Pinout

RESET

V

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DD

OSC1

OSC2

2

SS

ICCSEL

3

SS/PB7

SCK/PB6

PA0 (HS)/ICCCLK

PA1 (HS)/ICCDATA

PA2 (HS)

4

5

MISO/PB5

6

MOSI/PB4

PA3 (HS)

7

ei1

ei0

3

OCMP2_A/PB3

PA4 (HS)/SCLI

8

3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

9

PA5(HS)/RDI

3

PA6 (HS)/SDAI

10

11

12

3

PA7 (HS)/TDO

2

AIN5/EXTCLK_A/PC5

PC0/ICAP1_B/AIN0

PC1/OCMP1_B/AIN1

2

AIN4 /OCMP2_B/PC4

1

13

14

ei0 or ei1

2

AIN3 /ICAP2_B/PC3

PC2/MCO/AIN2

(HS) 20mA high sink capability

eiX associated external interrupt vector

1

Configurable by option byte

2

Alternate function not available on ST72260

Alternate function not available on ST72260 and ST72262

3

Figure 3. 32-Pin SDIP Package Pinout

V

RESET

OSC1

1

DD

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

SS

OSC2

3

ICCSEL

PA0 (HS)/ICCCLK

PA1 (HS)/ICCDATA

SS/PB7

4

5

SCK/PB6

MISO/PB5

MOSI/PB4

NC

ei1

ei0

6

PA2 (HS)

PA3 (HS)

7

8

NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

9

3

PA4 (HS)/SCLI

10

11

12

13

14

15

16

3

PA5 (HS)/RDI

ei1

ei0

3

PA6 (HSI/SDAI

3

ICAP1_A/PB0

PA7 (HS)/TDO

2

PC0/ICAP1_B/AIN0

AIN5 /EXTCLK_A/PC5

2

1

PC1/OCMP1_B/AIN1

AIN4 /OCMP2_B/PC4

ei0 or ei1

2

PC2/MCO/AIN2

AIN3 /ICAP2_B/PC3

1

2

3

Configurable by option byte

Alternate function not available on ST72260

Alternate function not available on ST72260 and ST72262

(HS) 20mA high sink capability

eiX associated external interrupt vector

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ST72260Gx, ST72262Gx, ST72264Gx

PIN DESCRIPTION (Cont’d)

Figure 4. TFBGA Package Pinout (view through package)

1

2

3

4

5

6

A

B

C

D

E

F

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ST72260Gx, ST72262Gx, ST72264Gx

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page

126.

Legend / Abbreviations for Table 1:

Type:

I = input, O = output, S = supply

A = Dedicated analog input

Input level:

In/Output level: C = CMOS 0.3 V /0.7 V with input trigger

T

DD

Output level:

HS = 20 mA high sink (on N-buffer only)

Port and control configuration:

1)

– Input:

float = floating, wpu = weak pull-up, int = interrupt , ana = analog

2)

– Output:

OD = open drain , PP = push-pull

Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

Pin n°

Level

Port / Control

Main

Function

(after

Input

Output

Pin Name

Alternate Function

reset)

Top priority non maskable interrupt (ac-

tive low)

1

2

3

1

2

3

A3 RESET

I/O

I

C

X

T

External clock input or Resonator oscilla-

tor inverter input or resistor input for RC

oscillator

3)

C4 OSC1

B3 OSC2

Resonator oscillator inverter output or ca-

pacitor input for RC oscillator

O

4

5

6

7

8

9

4

5

6

7

A2 PB7/SS

A1 PB6/SCK

B1 PB5/MISO

B2 PB4/MOSI

C1 NC

I/O

C

X

ei1

X

Port B7 SPI Slave Select (active low)

Port B6 SPI Serial Clock

T

C

Port B5 SPI Master In/ Slave Out Data

Port B4 SPI Master Out / Slave In Data

C2 NC

Not Connected

D1 NC

10

11

8

9

C3 PB3/OCMP2_A

D2 PB2/ICAP2_A

I/O

C

X

ei1

X

Port B3 Timer A Output Compare 2

T

X

Port B2 Timer A Input Capture 2

Timer A Output Compare 1

Caution: Negative current

12 10 E1 PB1 /OCMP1_A

13 11 F1 PB0 /ICAP1_A

I/O

C

X

ei1

X

Port B1

T

injection not allowed on

4)

this pin .

Timer A Input Capture 1

Caution: Negative current

C

X

ei1

X

Port B0

T

injection not allowed on

4)

this pin .

Timer A Input Clock or ADC

Analog Input 5

14 12 F2 PC5/EXTCLK_A/AIN5 I/O

ei0/ei1 X

Port C5

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ST72260Gx, ST72262Gx, ST72264Gx

Pin n°

Level

Port / Control

Main

Function

(after

Input

Output

Pin Name

Alternate Function

reset)

Timer B Output Compare 2 or

ADC Analog Input 4

15 13 E2 PC4/OCMP2_B/AIN4 I/O

16 14 F3 PC3/ ICAP2_B/AIN3 I/O

C

X

ei0/ei1

X

Port C4

Port C3

Port C2

Port C1

Port C0

T

Timer B Input Capture 2 or

ADC Analog Input 3

Main clock output (f

) or

CPU

17 15 E3 PC2/MCO/AIN2

I/O

ADC Analog Input 2

Timer B Output Compare 1 or

ADC Analog Input 1

18 16 F4 PC1/OCMP1_B/AIN1 I/O

Timer B Input Capture 1 or

ADC Analog Input 0

19 17 D3 PC0/ICAP1_B/AIN0

I/O

X

T

20 18 E4 PA7/TDO

21 19 F5 PA6/SDAI

22 20 F6 PA5 /RDI

23 21 E6 PA4/SCLI

I/O

C

HS

X

ei0

X

T

X

T

Port A7 SCI output

T

2

Port A6 I C DATA

T

X

Port A5 SCI input

2

Port A4 I C CLOCK

24

25

E5 NC

D6 NC

D5 NC

Not Connected

26 22 C6 PA3

27 23 D4 PA2

C5 NC

I/O

C

HS

X

ei0

X

Port A3

Port A2

T

Not Connected

B6 NC

28 24 A6 PA1/ICCDATA

I/O

C

HS

X

ei0

X

Port A1 In Circuit Communication Data

T

In Circuit Communication

Clock

29 25 A5 PA0/ICCCLK

30 26 B5 ICCSEL

X

Port A0

I

ICC mode pin, must be tied low

Ground

31 27 A4 V

32 28 B4 V

S

SS

DD

Main power supply

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt in-

put, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V

are not implemented). See Section 9 "I/O PORTS" on page 38 for more details.

DD

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, or an external source to the on-chip os-

cillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLATOR (MO)" on

page 21 for more details.

4: For details refer to Section 13.8 on page 144

9/172

ST72260Gx, ST72262Gx, ST72264Gx

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

dressing space so the reset and interrupt vectors

are located in Sector 0 (F000h-FFFFh).

The available memory locations consist of 128

bytes of register location, 256 bytes of RAM and

up to 8 Kbytes of user program memory. The RAM

space includes up to 128 bytes for the stack from

0100h to 017Fh.

The size of Flash Sector 0 and other device op-

tions are configurable by Option byte (refer to Sec-

tion 15.1 on page 162).

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

seved area can have unpredictable effects on the

device.

The highest address bytes contain the user reset

and interrupt vectors.

The Flash memory contains two sectors (see Fig-

ure 5) mapped in the upper part of the ST7 ad-

Related Documentation

AN 985: Executing Code in ST7 RAM

Figure 5. Memory Map

0000h

HW Registers

(see Table 2)

0080h

Short Addressing RAM

007Fh

0080h

Zero page

(128 Bytes)

00FFh

0100h

RAM

(256 Bytes)

Stack or

16-bit Addressing RAM

017Fh

0180h

(128 Bytes)

017Fh

8K FLASH

Reserved

PROGRAM MEMORY

E000h

DFFFh

E000h

4 Kbytes

SECTOR 1

EFFFh

Program Memory

F000h

FFFFh

4 Kbytes

SECTOR 0

(4K, 8 KBytes)

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 5 on page 32)

FFFFh

10/172

ST72260Gx, ST72262Gx, ST72264Gx

Table 2. Hardware Register Map

Register

Reset

Status

Address

Block

Register Name

Remarks

Label

1)

2)

0000h

0001h

0002h

PCDR

PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

xx000000h R/W

2)

Port C

00h

R/W

0003h

Reserved (1 Byte)

1)

0004h

0005h

0006h

PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h

R/W

R/W.

Port B

Port A

00h

0007h

Reserved (1 Byte)

1)

R/W

0008h

0009h

000Ah

PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h

R/W

000Bh

to

Reserved (17 Bytes)

001Bh

001Ch

001Dh

001Eh

001Fh

ISPR0

ISPR1

ISPR2

ISPR3

Interrupt software priority register0

Interrupt software priority register1

Interrupt software priority register2

Interrupt software priority register3

FFh

R/W

ITC

SPI

0020h

MISCR1

Miscellanous register 1

00h

R/W

0021h

0022h

0023h

SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Status Register

xxh

0xh

00h

R/W

0024h

0025h

0026h

0027h

WATCHDOG WDGCR

SICSR

Watchdog Control Register

7Fh

R/W

System Integrity Control / Status Register

Main Clock Control / Status Register

Reserved (1 Byte)

000x 000x R/W

MCC

MCCSR

00h

R/W

2

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

I2CCR

I C Control Register

00h

40h

00h

R/W

2

I2CSR1

I2CSR2

I2CCCR

I2COAR1

I2COAR2

I2CDR

I C Status Register 1

Read Only

R/W

2

I C Status Register 2

2

I C

I C Clock Control Register

2

I C Own Address Register 1

2

I C Own Address Register2

2

I C Data Register

R/W

002Fh

0030h

Reserved (2 Bytes)

11/172

ST72260Gx, ST72262Gx, ST72264Gx

Register

Label

Reset

Status

Address

Block

Register Name

Remarks

R/W

Read Only

R/W

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TACR2

TACR1

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

TASCSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

R/W

TIMER A

Read Only

R/W

TACLR

Timer A Counter Low Register

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

R/W

0040h

MISCR2

Miscellanous register 2

00h

R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TBCR2

TBCR1

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

TBSCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

R/W

TIMER B

Read Only

R/W

TBCLR

Timer B Counter Low Register

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

R/W

0050h

0051h

0052h

0053h

0054h

0055h

0056h

SCISR

SCIDR

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register1

SCI Control Register2

SCI Extended Receive Prescaler Register

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

Read Only

R/W

SCIBRR

SCICR1

SCICR2

SCIERPR

SCIETPR

SCI

x000 0000h R/W

00h

R/W

0057h

to

Reserved (24 Bytes)

006Eh

3)

006Fh

0070h

0071h

ADCDRL

ADCDRH

ADCCSR

Data Register Low

00h

Read Only

R/W

3)

ADC

Data Register High

Control/Status Register

0072h

FLASH

FCSR

Flash Control Register

00h

R/W

0073h

to

Reserved (13 Bytes)

007Fh

12/172

ST72260Gx, ST72262Gx, ST72264Gx

Legend: x=Undefined, R/W=Read/Write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the

LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little En-

dian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two

char registers.

13/172

ST72260Gx, ST72262Gx, ST72264Gx

board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

4 FLASH PROGRAM MEMORY

ICP uses a protocol called ICC (In-Circuit Commu-

nication) which allows an ST7 plugged on a print-

ed circuit board (PCB) to communicate with an ex-

ternal programming device connected via cable.

ICP is performed in three steps:

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is

a non-volatile memory that can be electrically

erased and programmed either on a byte-by-byte

basis or up to 32 bytes in parallel.

Switch the ST7 to ICC mode (In-Circuit Communi-

cations). This is done by driving a specific signal

sequence on the ICCCLK/DATA pins while the

RESET pin is pulled low. When the ST7 enters

ICC mode, it fetches a specific RESET vector

which points to the ST7 System Memory contain-

ing the ICC protocol routine. This routine enables

the ST7 to receive bytes from the ICC interface.

The XFlash devices can be programmed off-board

(plugged in a programming tool) or on-board using

In-Circuit Programming or In-Application Program-

ming.

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

– Download ICP Driver code in RAM from the

ICCDATA pin

4.2 Main Features

– Execute ICP Driver code in RAM to program

the FLASH memory

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

Depending on the ICP Driver code downloaded in

RAM, FLASH memory programming can be fully

customized (number of bytes to program, program

locations, or selection of the serial communication

interface for downloading).

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection against piracy

4.3.2 In Application Programming (IAP)

4.3 PROGRAMMING MODES

This mode uses an IAP Driver program previously

programmed in Sector 0 by the user (in ICP

mode).

The ST7 can be programmed in three different

ways:

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the data to be stored etc.)

IAP mode can be used to program any memory ar-

eas except Sector 0, which is write/erase protect-

ed to allow recovery in case errors occur during

the programming operation.

– Insertion in a programming tool. In this mode,

FLASH sectors 0 and 1 and option byte row

can be programmed or erased.

– In-Circuit Programming. In this mode, FLASH

sectors 0 and 1 and option byte row can be

programmed or erased without removing the

device from the application board.

– In-Application Programming. In this mode,

sector 1 can be programmed or erased with-

out removing the device from the application

14/172

ST72260Gx, ST72262Gx, ST72264Gx

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface

Tool documentation for recommended resistor val-

ues.

ICP needs a minimum of 4 and up to 7 pins to be

connected to the programming tool. These pins

are:

2. During the ICP session, the programming tool

must control the RESET pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

In all cases the user must ensure that no external

reset is generated by the application during the

ICC session.

– RESET: device reset

– V : device power supply ground

SS

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input serial data pin

– ICCSEL: ICC selection (not required on devic-

es without ICCSEL pin)

– OSC1: main clock input for external source

(not required on devices without OSC1/OSC2

pins)

– V : application board power supply (option-

DD

al, see Note 3)

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to be implemented in case another de-

vice forces the signal. Refer to the Programming

4. Pin 9 has to be connected to the OSC1 pin of

the ST7 when the clock is not available in the ap-

plication or if the selected clock option is not pro-

grammed in the option byte. ST7 devices with mul-

ti-oscillator capability need to have OSC2 ground-

ed in this case.

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

(See Note 3)

OPTIONAL

(See Note 4)

APPLICATION BOARD

9

7

5

6

3

1

2

10

8

4

APPLICATION

RESET SOURCE

See Note 2

10kΩ

APPLICATION

POWER SUPPLY

C

L2

L1

APPLICATION

See Note 1

I/O

ST7

15/172

ST72260Gx, ST72262Gx, ST72264Gx

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

4.6 Related Documentation

There are two different types of memory protec-

tion: Read Out Protection and Write/Erase Protec-

tion which can be applied individually.

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual.

AN1477: Emulated data EEPROM with XFlash

memory

4.5.1 Read out Protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry. Even if no protection can be considered as to-

tally unbreakable, the feature provides a very high

level of protection for a general purpose microcon-

troller.

AN1576: IAP drivers for ST7 HDFlash or XFlash

MCUs

AN1575: On Board Programming methods for ST7

HDFlash or XFlash MCUs

AN1070: Checksum self checking capability

In flash devices, this protection is removed by re-

programming the option. In this case the program

memory is automatically erased and the device

can be reprogrammed.

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 000 0000 (00h)

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

Read-out protection selection depends on the de-

vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

7

0

4.5.2 Flash Write/Erase Protection

0

OPT

LAT

PGM

Write/erase protection, when set, makes it impos-

sible to both overwrite and erase program memo-

ry. Its purpose is to provide advanced security to

applications and prevent any change being made

to the memory content.

Note: This register is reserved for programming

using ICP, IAP or other programming methods. It

controls the XFlash programming and erasing op-

erations.

Warning: Once set, Write/erase protection can

never be removed. A write-protected flash device

is no longer reprogrammable.

When an EPB or another programming tool is

used (in socket or ICP mode), the RASS keys are

sent automatically.

Write/erase protection is enabled through the

FMP_W bit in the option byte.

16/172

ST72260Gx, ST72262Gx, ST72264Gx

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

5.3 CPU REGISTERS

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

The 6 CPU registers shown in Figure 7 are not

present in the memory mapping and are accessed

by specific instructions.

Accumulator (A)

5.2 MAIN FEATURES

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

Index Registers (X and Y)

addressing mode)

These 8-bit registers are used to create effective

addresses or as temporary storage areas for data

manipulation. (The Cross-Assembler generates a

precede instruction (PRE) to indicate that the fol-

lowing instruction refers to the Y register.)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

The Y register is not affected by the interrupt auto-

matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 7. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

I1 H I0 N Z C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

17/172

ST72260Gx, ST72262Gx, ST72264Gx

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

Reset Value: 111x1xxx

7

0

1

I1

H

I0

N

Z

C

This bit is accessed by the JREQ and JRNE test

instructions.

The 8-bit Condition Code register contains the in-

terrupt masks and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

These bits can be individually tested and/or con-

trolled by specific instructions.

Arithmetic Management Bits

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instructions. It is reset by hardware during

the same instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

0: No half carry has occurred.

1: A half carry has occurred.

The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Interrupt Software Priority

Level 0 (main)

I1

1

0

1

I0

0

1

0

1

Level 1

Bit 2 = N Negative.

Level 2

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It’s a copy of the re-

Level 3 (= interrupt disable)

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (IxSPR). They can be also set/

cleared by software with the RIM, SIM, IRET,

HALT, WFI and PUSH/POP instructions.

th

sult 7 bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

See the interrupt management chapter for more

details.

18/172

ST72260Gx, ST72262Gx, ST72264Gx

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Reset Value: 01 7Fh

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

15

8

1

0

7

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 8

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 8).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

Since the stack is 128 bytes deep, the 8 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP7 to SP0 bits are set) which is the stack

higher address.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Figure 8. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 017Fh

Stack Higher Address = 017Fh

0100h

Stack Lower Address =

19/172

ST72260Gx, ST72262Gx, ST72264Gx

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 10.

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the 2 to

4 MHz range, the PLL can be used to multiply the

frequency by two to obtain an f

of 4 to 8 MHz.

OSC2

The PLL is enabled by option byte. If the PLL is

disabled, then f /2.

For more details, refer to dedicated parametric

section.

f

OSC2 = OSC

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required. See

“PLL Characteristics” on page 139.

Main Features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

Figure 9. PLL Block Diagram

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 4 Crystal/Ceramic resonator oscillators

– 1 Internal RC oscillator

■ System Integrity Management (SI)

PLL x 2

/ 2

0

1

f

OSC

f

OSC2

– Main supply Low Voltage Detector (LVD)

PLL OPTION BIT

– Auxiliary Voltage Detector (AVD) with inter-

rupt capability for monitoring the main supply

Figure 10. Clock, Reset and Supply Block Diagram

MISCR1 Register

SLOW MODE

SELECTION

f

CPU

to CPU

and

Peripherals

MAIN CLOCK

CONTROLLER

WITH REALTIME

MULTI-

OSCILLATOR

(MO)

OSC2

OSC1

f

OSC

PLL

(option)

f

OSC2

CLOCK (MCC/RTC)

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

TIMER (WDG)

RESET SEQUENCE

MANAGER

AVD Interrupt Request

RESET

SICSR

AVD AVD

LVD

RF

WDG

RF

(RSM)

0

IE

F

LOW VOLTAGE

DETECTOR

(LVD)

V

SS

DD

AUXILIARY VOLTAGE

DETECTOR

(AVD)

20/172

ST72260Gx, ST72262Gx, ST72264Gx

6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by

four different source types coming from the multi-

oscillator block:

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Internal RC Oscillator

This oscillator allows a low cost solution for the

main clock of the ST7 using only an internal resis-

tor and capacitor. Internal RC oscillator mode has

the drawback of a lower frequency accuracy and

should not be used in applications that require ac-

curate timing.

Each oscillator is optimized for a given frequency

range in terms of consumption and is selectable

through the option byte. The associated hardware

configurations are shown in Table 3. Refer to the

electrical characteristics section for more details.

In this mode, the two oscillator pins have to be tied

to ground.

Related Documentation

AN1044: Multiple interrupt source management

for ST7 MCUs

Figure 18. Concurrent Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1

I0

TLI

3

1 1

IT0

3

IT1

3

IT2

3

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

Figure 19. Nested Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1

I0

TLI

3

1 1

0 0

0 1

1 1

IT0

3

IT1

IT2

2

IT2

1

IT3

3

RIM

IT4

3

MAIN

3/0

11 / 10

10

30/172

ST72260Gx, ST72262Gx, ST72264Gx

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write

Read/Write (bits 7:4 of ISPR3 are read only)

Reset Value: 111x 1010 (xAh)

Reset Value: 1111 1111 (FFh)

7

0

7

0

ISPR0

ISPR1

I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

1

I1

H

I0

N

Z

C

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt soft-

ware priority.

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

Interrupt Software Priority Level

I1

1

I0

0

ISPR3

1

I1_13 I0_13 I1_12 I0_12

Level 0 (main)

Level 1

Low

0

1

These four registers contain the interrupt software

priority of each interrupt vector.

Level 2

0

Level 3 (= interrupt disable*)

High

1

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondance is shown in the following table.

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt software pri-

ority registers (ISPRx).

Vector Address

ISPRx Bits

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

FFFBh-FFFAh

FFF9h-FFF8h

...

ei0

ei1

...

FFE1h-FFE0h

Not used

*Note: TRAP and RESET events are non maska-

ble sources and can interrupt a level 3 program.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The RESET and TRAP vectors have no software

priorities. When one is serviced, the I1 and I0 bits

of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

31/172

ST72260Gx, ST72262Gx, ST72264Gx

INTERRUPTS (Cont’d)

Table 5. Interrupt Mapping

Exit

from

HALT

Source

Block

Register Priority

Address

Vector

N°

Description

Label

Order

RESET

TRAP

ei0

Reset

Software Interrupt

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

Highest

Priority

N/A

1

0

1

External Interrupt Port A7..0 (C5..0 )

yes

1

ei1

External Interrupt Port B7..0 (C5..0 )

2

Not used

3

SPI

TIMER A

MCC

SPI Peripheral Interrupts

TIMER A Peripheral Interrupts

Time base interrupt

TIMER B Peripheral Interrupts

Auxiliary Voltage Detector interrupt

Not used

SPISR

TASR

yes

no

4

5

MCCSR

TBSR

yes

6

TIMER B

AVD

no

7

SICSR

8

9

Not used

10

11

12

13

SCI

SCI Peripheral Interrupt

SCISR

no

2

I C

I C Peripheral Interrupt

I2CSRx

Not Used

Lowest

Priority

Note 1. Configurable by option byte.

Table 6. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SPI

Not Used

EI1

EI0

001Ch

001Dh

001Eh

001Fh

ISPR0

Reset Value

I1_3

1

I0_3

1

I1_2

1

I0_2

1

I1_1

1

I0_1

1

I1_0

1

I0_0

1

AVD

TIMERB

MCC

TIMERA

ISPR1

Reset Value

I1_7

1

I0_7

1

I1_6

1

I0_6

1

I1_5

1

I0_5

1

I1_4

1

I0_4

1

2

I C

SCI

Not Used

ISPR2

Reset Value

I1_11

1

I0_11

1

I1_10

1

I0_10

1

I1_9

1

I0_9

1

I1_8

1

I0_8

1

Not Used

ISPR3

Reset Value

I1_13

1

I0_13

1

I1_12

1

I0_12

1

32/172

ST72260Gx, ST72262Gx, ST72264Gx

8 POWER SAVING MODES

8.1 INTRODUCTION

8.2 SLOW MODE

To give a large measure of flexibility to the applica-

tion in terms of power consumption, three main

power saving modes are implemented in the ST7

(see Figure 20).

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

the available supply voltage.

) to

CPU

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

SLOW mode is controlled by three bits in the

MISR1 register: the SMS bit which enables or dis-

ables Slow mode and two CPx bits which select

main oscillator frequency divided by 2 (f

).

CPU

the internal slow frequency (f

).

CPU

From Run mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

In this mode, the oscillator frequency can be divid-

ed by 4, 8, 16 or 32 instead of 2 in normal operat-

ing mode. The CPU and peripherals are clocked at

this lower frequency.

Note: SLOW-WAIT mode is activated when enter-

ring the WAIT mode while the device is already in

SLOW mode.

Figure 20. Power Saving Mode Transitions

High

RUN

Figure 21. SLOW Mode Clock Transitions

f

/2

f

/4

f

OSC2

f

CPU

SLOW

WAIT

f

OSC2

00

01

CP1:0

SMS

SLOW WAIT

HALT

NORMAL RUN MODE

REQUEST

NEW SLOW

FREQUENCY

REQUEST

Low

POWER CONSUMPTION

33/172

ST72260Gx, ST72262Gx, ST72264Gx

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

Figure 22. WAIT Mode Flowchart

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

0

WFI INSTRUCTION

This power saving mode is selected by calling the

“WFI” ST7 software instruction.

All peripherals remain active. During WAIT mode,

‘10b’

the I [1:0] bits in the CC register are forced to

,

to enable all interrupts. All other registers and

memory remain unchanged. The MCU remains in

WAIT mode until an interrupt or Reset occurs,

whereupon the Program Counter branches to the

starting address of the interrupt or Reset service

routine.

N

RESET

Y

N

INTERRUPT

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

Y

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

1

Refer to Figure 22.

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

1)

I[1:0] BITS

XX

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits in the CC reg-

ister are set during the interrupt routine and

cleared when the CC register is popped.

34/172

ST72260Gx, ST72262Gx, ST72264Gx

Figure 23. ACTIVE-HALT Timing Overview

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

ACTIVE

HALT

4096 CPU

CYCLE DELAY

RUN

1)

RESET

OR

INTERRUPT

HALT

INSTRUCTION

[MCCSR.OIE=1]

FETCH

VECTOR

MCCSR Power Saving Mode entered when HALT

OIE bit

instruction is executed

HALT mode

ACTIVE-HALT mode

Figure 24. ACTIVE-HALT Mode Flowchart

0

1

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

10

2)

HALT INSTRUCTION

(MCCSR.OIE=1)

8.4.1 ACTIVE-HALT MODE

I[1:0] BITS

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set.

N

RESET

N

Y

INTERRUPT ³⁾

The MCU can exit ACTIVE-HALT mode on recep-

tion of either an MCC/RTC interrupt, a specific in-

terrupt (see Table 5, “Interrupt Mapping,” on page

32) or a RESET. When exiting ACTIVE-HALT

mode by means of an interrupt, no 4096 CPU cy-

cle delay occurs. The CPU resumes operation by

servicing the interrupt or by fetching the reset vec-

tor which woke it up (see Figure 24).

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are forced to ‘10b’ to enable in-

terrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

OSCILLATOR

PERIPHERALS

CPU

ON

OFF

ON

Y

I[1:0] BITS

XX ⁴⁾

4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

I[1:0] BITS

XX ⁴⁾

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wake-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE-HALT mode while the Watchdog

is active does not generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

can still be active.

3. Only the MCC/RTC interrupt and some specific

interrupts can exit the MCU from ACTIVE-HALT

mode (such as external interrupt). Refer to Table

5, “Interrupt Mapping,” on page 32 for more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

register is popped.

35/172

ST72260Gx, ST72262Gx, ST72264Gx

POWER SAVING MODES (Cont’d)

8.5 HALT MODE

Figure 26. HALT Mode Flowchart

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

ST7 HALT instruction (see Figure 26).

HALT INSTRUCTION

ENABLE

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 32) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the oscillator is immediately turned on and the

4096 CPU cycle delay is used to stabilize the os-

cillator. After the start up delay, the CPU resumes

operation by servicing the interrupt or by fetching

the reset vector which woke it up (see Figure 25).

When entering HALT mode, the I[1:0] bits in the

CC register are forced to ‘10b’ to enable interrupts.

Therefore, if an interrupt is pending, the MCU

wakes immediately.

WATCHDOG

0

DISABLE

WDGHALT ¹⁾

1

WATCHDOG

RESET

OSCILLATOR

OFF

PERIPHERALS ²⁾

CPU

OFF

0

I[1:0] BITS

N

RESET

In the HALT mode the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

Y

N

INTERRUPT ³⁾

OSCILLATOR

PERIPHERALS

CPU

Y

ON

OFF

ON

1

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see

Section 15.1 "OPTION BYTES" on page 162 for

more details).

I[1:0] BITS

4096 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

ON

Figure 25. HALT Mode Timing Overview

ON

I[1:0] BITS

XX ⁴⁾

4096 CPU CYCLE

RUN

HALT

RUN

DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

HALT

INSTRUCTION

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 5, “Interrupt Mapping,” on page 32 for

more details.

RESET

OR

INTERRUPT

FETCH

VECTOR

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits in the CC reg-

ister are set during the interrupt routine and

cleared when the CC register is popped.

36/172

ST72260Gx, ST72262Gx, ST72264Gx

POWER SAVING MODES (Cont’d)

8.5.0.1 Halt Mode Recommendations

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user

may choose to clear all pending interrupt bits be-

fore executing the HALT instruction. This avoids

entering other peripheral interrupt routines after

executing the external interrupt routine corre-

sponding to the wake-up event (reset or external

interrupt).

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

Related Documentation

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

AN 980: ST7 Keypad Decoding Techniques, Im-

plementing Wake-Up on Keystroke

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

AN1014: How to Minimize the ST7 Power Con-

sumption

AN1605: Using an active RC to wakeup the

ST7LITE0 from power saving mode

37/172

ST72260Gx, ST72262Gx, ST72264Gx

9 I/O PORTS

9.1 INTRODUCTION

If several I/O interrupt pins on the same interrupt

vector are selected simultaneously, they are logi-

cally combined. For this reason if one of the inter-

rupt pins is tied low, it may mask the others.

The I/O ports allow data transfer. An I/O port can

contain up to 8 pins. Each pin can be programmed

independently either as a digital input or digital

output. In addition, specific pins may have several

other functions. These functions can include exter-

nal interrupt, alternate signal input/output for on-

chip peripherals or analog input.

External interrupts are hardware interrupts. Fetch-

ing the corresponding interrupt vector automatical-

ly clears the request latch. Modifying the sensitivity

bits will clear any pending interrupts.

9.2.2 Output Modes

9.2 FUNCTIONAL DESCRIPTION

Setting the DDRx bit selects output mode. Writing

to the DR bits applies a digital value to the I/O

through the latch. Reading the DR bits returns the

previously stored value.

A Data Register (DR) and a Data Direction Regis-

ter (DDR) are always associated with each port.

The Option Register (OR), which allows input/out-

put options, may or may not be implemented. The

following description takes into account the OR

register. Refer to the Port Configuration table for

device specific information.

If an OR bit is available, different output modes

can be selected by software: push-pull or open-

drain. Refer to I/O Port Implementation section for

configuration.

DR Value and Output Pin Status

An I/O pin is programmed using the corresponding

bits in the DDR, DR and OR registers: bit x corre-

sponding to pin x of the port.

DR

Push-Pull

Open-Drain

0

1

V

OL

Floating

OL

Figure 27 shows the generic I/O block diagram.

V

OH

9.2.1 Input Modes

9.2.3 Alternate Functions

Clearing the DDRx bit selects input mode. In this

mode, reading its DR bit returns the digital value

from that I/O pin.

Many ST7s I/Os have one or more alternate func-

tions. These may include output signals from, or

input signals to, on-chip peripherals. The Device

Pin Description table describes which peripheral

signals can be input/output to which ports.

If an OR bit is available, different input modes can

be configured by software: floating or pull-up. Re-

fer to I/O Port Implementation section for configu-

ration.

A signal coming from an on-chip peripheral can be

output on an I/O. To do this, enable the on-chip

peripheral as an output (enable bit in the peripher-

al’s control register). The peripheral configures the

I/O as an output and takes priority over standard I/

O programming. The I/O’s state is readable by ad-

dressing the corresponding I/O data register.

Notes:

1. Writing to the DR modifies the latch value but

does not change the state of the input pin.

2. Do not use read/modify/write instructions

(BSET/BRES) to modify the DR register.

External Interrupt Function

Configuring an I/O as floating enables alternate

function input. It is not recommended to configure

an I/O as pull-up as this will increase current con-

sumption. Before using an I/O as an alternate in-

put, configure it without interrupt. Otherwise spuri-

ous interrupts can occur.

Depending on the device, setting the ORx bit while

in input mode can configure an I/O as an input with

interrupt. In this configuration, a signal edge or lev-

el input on the I/O generates an interrupt request

via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed in-

dependently for each interrupt vector. The Exter-

nal Interrupt Control Register (EICR) or the Miscel-

laneous Register controls this sensitivity, depend-

ing on the device.

Configure an I/O as input floating for an on-chip

peripheral signal which can be input and output.

Caution:

I/Os which can be configured as both an analog

and digital alternate function need special atten-

tion. The user must control the peripherals so that

the signals do not arrive at the same time on the

same pin. If an external clock is used, only the

clock alternate function should be employed on

that I/O pin and not the other alternate function.

A device may have up to 7 external interrupts.

Several pins may be tied to one external interrupt

vector. Refer to Pin Description to see which ports

have external interrupts.

38/172

ST72260Gx, ST72262Gx, ST72264Gx

I/O PORTS (Cont’d)

Figure 27. I/O Port General Block Diagram

ALTERNATE

OUTPUT

From on-chip peripheral

1

0

REGISTER

ACCESS

P-BUFFER

(see table below)

V

DD

ALTERNATE

ENABLE

BIT

PULL-UP

(see table below)

DR

V

DD

DDR

OR

PULL-UP

CONDITION

PAD

If implemented

OR SEL

DDR SEL

DR SEL

N-BUFFER

DIODES

(see table below)

ANALOG

INPUT

CMOS

SCHMITT

TRIGGER

1

0

ALTERNATE

INPUT

To on-chip peripheral

EXTERNAL

INTERRUPT

REQUEST (ei )

Combinational

Logic

FROM

OTHER

BITS

x

SENSITIVITY

SELECTION

Note: Refer to the Port Configuration

table for device specific information.

Table 7. I/O Port Mode Options

Configuration Mode

Diodes

Pull-Up

P-Buffer

to V

SS

DD

Floating with/without Interrupt

Input

Off

On

Off

Pull-up with/without Interrupt

On

Push-pull

On

Off

NI

On

Off

NI

Output

Open Drain (logic level)

True Open Drain

NI (see note)

Legend:NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to V is not implemented in the

DD

true open drain pads. A local protection between

the pad and V is implemented to protect the de-

OL

vice against positive stress.

39/172

ST72260Gx, ST72262Gx, ST72264Gx

I/O PORTS (Cont’d)

Table 8. I/O Configurations

Hardware Configuration

DR REGISTER ACCESS

V

DD

NOTE 3

PULL-UP

CONDITION

R

W

R

PU

DR

REGISTER

DATA BUS

PAD

ALTERNATE INPUT

To on-chip peripheral

FROM

OTHER

PINS

EXTERNAL INTERRUPT

SOURCE (ei )

x

COMBINATIONAL

LOGIC

INTERRUPT

CONDITION

POLARITY

SELECTION

ANALOG INPUT

V

NOTE 3

DD

DR REGISTER ACCESS

R

PU

PAD

R/W

DR

REGISTER

DATA BUS

DR REGISTER ACCESS

NOTE 3

V

DD

R

PU

R/W

DR

REGISTER

DATA BUS

PAD

ALTERNATE

ENABLE

BIT

ALTERNATE

OUTPUT

From on-chip peripheral

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

3. For true open drain, these elements are not implemented.

40/172

ST72260Gx, ST72262Gx, ST72264Gx

I/O PORTS (Cont’d)

Analog alternate function

9.4 UNUSED I/O PINS

Configure the I/O as floating input to use an ADC

input. The analog multiplexer (controlled by the

ADC registers) switches the analog voltage

present on the selected pin to the common analog

rail, connected to the ADC input.

Unused I/O pins must be connected to fixed volt-

age levels. Refer to Section 13.8.

9.5 LOW POWER MODES

Analog Recommendations

Mode

WAIT

HALT

Description

Do not change the voltage level or loading on any

I/O while conversion is in progress. Do not have

clocking pins located close to a selected analog

pin.

No effect on I/O ports. External interrupts

cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts

cause the device to exit from HALT mode.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

9.6 INTERRUPTS

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and if the I bit in the CC

register is cleared (RIM instruction).

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-

pends on the settings in the DDR and OR registers

and specific I/O port features such as ADC input or

open drain.

Enable Exit

Control from

Exit

from

Halt

Event

Flag

Interrupt Event

Bit

Wait

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 28. Other transitions

are potentially risky and should be avoided, since

they may present unwanted side-effects such as

spurious interrupt generation.

External interrupt on

selected external

event

DDRx

ORx

-

Yes

Related Documentation

AN 970: SPI Communication between ST7 and

EEPROM

Figure 28. Interrupt I/O Port State Transitions

AN1045: S/W implementation of I2C bus master

AN1048: Software LCD driver

01

00

10

11

INPUT

floating/pull-up

interrupt

INPUT

floating

(reset state)

OUTPUT

open-drain

OUTPUT

push-pull

= DDR, OR

XX

41/172

ST72260Gx, ST72262Gx, ST72264Gx

I/O PORTS (Cont’d)

9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

The I/O port register configurations are summa-

rised as follows.

True Open Drain Interrupt Ports

PA6, PA4 (without pull-up)

Interrupt Ports

MODE

DDR

OR

PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)

floating input

0

1

0

1

X

MODE

DDR

OR

floating interrupt input

open drain (high sink ports)

floating input

0

1

0

1

0

1

pull-up interrupt input

open drain output

push-pull output

Table 9. Port Configuration

Input (DDR = 0)

Output (DDR = 1)

Port

Pin Name

PA7

OR = 0

OR = 1

OR = 0

OR = 1

High-Sink

floating

pull-up interrupt

floating interrupt

pull-up interrupt

floating interrupt

pull-up interrupt

open drain

push-pull

PA6

true open-drain

Port A

PA5

open drain

push-pull

Yes

PA4

true open-drain

PA3:0

PB7:0

PC5:0

open drain

push-pull

Port B

Port C

No

42/172

ST72260Gx, ST72262Gx, ST72264Gx

OPTION REGISTER (OR)

I/O PORTS (Cont’d)

9.8 I/O PORT REGISTER DESCRIPTION

DATA REGISTER (DR)

Port x Option Register

PxOR with x = A, B or C.

Port x Data Register

PxDR with x = A, B or C.

Read/Write

Reset Value: 0000 0000 (00h)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

7

0

O7

O6

O5

O4

O3

O2

O1

O0

D7

D6

D5

D4

D3

D2

D1

D0

Bits 7:0 = O[7:0] Option register 8 bits.

For specific I/O pins, this register is not implement-

ed. In this case the DDR register is enough to se-

lect the I/O pin configuration.

Bits 7:0 = D[7:0] Data register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken into account

even if the pin is configured as an input; this allows

always having the expected level on the pin when

toggling to output mode. Reading the DR register

returns either the DR register latch content (pin

configured as output) or the digital value applied to

the I/O pin (pin configured as input).

The OR register allows to distinguish: in input

mode if the pull-up with interrupt capability or the

basic pull-up configuration is selected, in output

mode if the push-pull or open drain configuration is

selected.

Each bit is set and cleared by software.

Input mode:

0: Floating input

1: Pull-up input with or without interrupt

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register

PxDDR with x = A, B or C.

Output mode:

0: Output open drain (with P-Buffer unactivated)

1: Output push-pull (when available)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

Bits 7:0 = DD[7:0] Data direction register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

43/172

ST72260Gx, ST72262Gx, ST72264Gx

I/O PORTS (Cont’d)

Table 10. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Reset Value

of all I/O port registers

0

0000h

0001h

0002h

0004h

0005h

0006h

0008h

0009h

000Ah

PCDR

PCDDR

PCOR

PBDR

PBDDR

PBOR

PADR

PADDR

PAOR

MSB

LSB

44/172

ST72260Gx, ST72262Gx, ST72264Gx

10 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over

several different features such as the external in-

terrupts or the I/O alternate functions.

Figure 29. Ext. Interrupt Sensitivity (EXTIT=0)

MISCR1

IS00 IS01

PA7

ei0

10.1 I/O PORT INTERRUPT SENSITIVITY

INTERRUPT

SOURCE

The external interrupt sensitivity is controlled by

the ISxx bits of the Miscellaneous register and the

OPTION BYTE. This control allows you to have

two fully independent external interrupt source

sensitivities with configurable sources (using the

EXTIT option bit) as shown in Figure 29 and Fig-

ure 30.

SENSITIVITY

CONTROL

PA0

PC5

PC0

MISCR1

IS10

IS11

ei1

Each external interrupt source can be generated

on four different events on the pin:

■ Falling edge

PB7

PB0

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

To guarantee correct functionality, the sensitivity

bits in the MISCR1 register must be modified only

when the I[1:0] bits in the CC register are set to 1

(interrupt masked). See Section 9.8 "I/O PORT

REGISTER DESCRIPTION" on page 43 and Sec-

tion 10.3 "MISCELLANEOUS REGISTER DE-

SCRIPTION" on page 46 for more details on the

programming.

Figure 30. Ext. Interrupt Sensitivity (EXTIT=1)

MISCR1

IS00

IS01

ei0

PA7

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

PA0

PB7

10.2 I/O PORT ALTERNATE FUNCTIONS

MISCR1

The MISCR registers manage four I/O port miscel-

laneous alternate functions:

IS10

IS11

ei1

INTERRUPT

SOURCE

SENSITIVITY

CONTROL

PB0

PC5

■ Main clock signal (f

) output on PC2

CPU

■ SPI pin configuration:

– SS pin internal control to use the PB7 I/O port

function while the SPI is active.

– Master output capability on the MOSI pin

(PB4) deactivated while the SPI is active.

PC0

– Slave output capability on the MISO pin (PB5)

deactivated while the SPI is active.

These functions are described in detail in the Sec-

tion 10.3 "MISCELLANEOUS REGISTER DE-

SCRIPTION" on page 46.

45/172

ST72260Gx, ST72262Gx, ST72264Gx

MISCELLANEOUS REGISTERS (Cont’d)

10.3 MISCELLANEOUS REGISTER DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write

Bits 2:1 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the various slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Reset Value: 0000 0000 (00h)

7

0

f

in SLOW mode

CP1

CP0

CPU

IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS

f

/ 2

/ 4

0

1

0

1

0

1

OSC2

/ 8

Bits 7:6 = IS1[1:0] ei1 sensitivity

f

/ 16

OSC2

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the ei1 external interrupts. These

two bits can be written only when the I[1:0] bits in

the CC register are set to 1 (interrupt masked).

Bit 0 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f = f

ei1: Port B (C optional)

OSC2

CPU

1: Slow mode. f

is given by CP1, CP0

CPU

External Interrupt Sensitivity

IS11 IS10

See low power consumption mode and MCC

chapters for more details.

Falling edge & low level

Rising edge only

0

1

0

1

0

1

Falling edge only

Rising and falling edge

Bit 5 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PC2 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

port)

on I/O

CPU

Bits 4:3 = IS0[1:0] ei0 sensitivity

The interrupt sensitivity, defined using the IS0[1:0]

bits, is applied to the ei0 external interrupts. These

two bits can be written only when the I[1:0] bits in-

the CC register are set to 1 (interrupt masked).

ei0: Port A (C optional)

External Interrupt Sensitivity

IS01 IS00

Falling edge & low level

Rising edge only

0

1

0

1

0

1

Falling edge only

Rising and falling edge

46/172

ST72260Gx, ST72262Gx, ST72264Gx

MISCELLANEOUS REGISTERS (Cont’d)

MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

MOD SOD SSM SSI

Caution: This register has been provided for com-

patibility with the ST72254 family only. The same

bits are available in the SPICSR register. New ap-

plications must use the SPICSR register. Do not

use both registers, this will cause the SPI to mal-

function.

Bits 7:4 = Reserved always read as 0

Bits 3 = MOD SPI Master Output Disable

This bit is set and cleared by software. When set, it

disables the SPI Master (MOSI) output signal.

0: SPI Master Output enabled.

1: SPI Master Output disabled.

Bit 2 = SOD SPI Slave Output Disable

This bit is set and cleared by software. When set it

disable the SPI Slave (MISO) output signal.

0: SPI Slave Output enabled.

1: SPI Slave Output disabled.

Bit 1 = SSM SS mode selection

This bit is set and cleared by software.

0: Normal mode - the level of the SPI SS signal is

input from the external SS pin.

1: I/O mode, the level of the SPI SS signal is read

from the SSI bit.

Bit 0 = SSI SS internal mode

This bit replaces the SS pin of the SPI when the

SSM bit is set to 1. (see SPI description). It is set

and cleared by software.

Table 11. Miscellaneous Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

MISCR1

Reset Value

IS11

0

IS10

0

MCO

0

IS01

0

IS00

0

CP1

0

CP0

0

SMS

0

0020h

0040h

MISCR2

Reset Value

MOD

0

SOD

0

SSM

0

SSI

0

47/172

ST72260Gx, ST72262Gx, ST72264Gx

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This down-

counter is free-running: it counts down even if the

watchdog is disabled. The value to be stored in the

WDGCR register must be between FFh and C0h:

11.1.2 Main Features

■ Programmable free-running downcounter

■ Programmable reset

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

■ Reset (if watchdog activated) when the T6 bit

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 32. Ap-

proximate Timeout Duration). The timing varies

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see Figure 33).

reaches zero

■ Optional

reset

on

HALT

instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

11.1.3 Functional Description

Following a reset, the watchdog is disabled. Once

activated it cannot be disabled, except by a reset.

The counter value stored in the Watchdog Control

register (WDGCR bits T[6:0]), is decremented

every 16384 f

cycles (approx.), and the

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

OSC2

length of the timeout period can be programmed

by the user in 64 increments.

If the watchdog is activated, the HALT instruction

will generate a Reset.

Figure 31. Watchdog Block Diagram

RESET

f

OSC2

MCC/RTC

WATCHDOG CONTROL REGISTER (WDGCR)

T5

DIV 64

WDGA T6

T1

T0

T4

T2

T3

6-BIT DOWNCOUNTER (CNT)

12-BIT MCC

RTC COUNTER

WDG PRESCALER

DIV 4

TB[1:0] bits

(MCCSR

Register)

MSB

LSB

0

6 5

11

48/172

ST72260Gx, ST72262Gx, ST72264Gx

WATCHDOG TIMER (Cont’d)

11.1.4 How to Program the Watchdog Timeout

more precision is needed, use the formulae in Fig-

ure 33.

Figure 32 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Coun-

ter (CNT) and the resulting timeout duration in mil-

liseconds. This can be used for a quick calculation

without taking the timing variations into account. If

Caution: When writing to the WDGCR register, al-

ways write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 32. Approximate Timeout Duration

3F

38

30

28

20

18

10

08

00

1.5

18

34

50

65

82

98

114

128

Watchdog timeout (ms) @ 8 MHz. f

OSC2

49/172

ST72260Gx, ST72262Gx, ST72264Gx

WATCHDOG TIMER (Cont’d)

Figure 33. Exact Timeout Duration (t

and t

)

max

min

WHERE:

t

= (LSB + 128) x 64 x t

min0

OSC2

= 16384 x t

= 125ns if f

max0

OSC2

=8 MHz

OSC2

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

TB1 Bit

TB0 Bit

Selected MCCSR

Timebase

MSB

LSB

(MCCSR Reg.) (MCCSR Reg.)

0

1

0

1

0

1

2ms

4ms

4

8

59

53

35

54

10ms

25ms

20

49

To calculate the minimum Watchdog Timeout (t ):

min

MSB

4

IF

THEN

ELSE

-------------

CNT <

t

= t_min0+ ¹⁶³⁸⁴× ^CNT× ^t

min

osc2

4CNT

----------------

4CNT

----------------

⎛

⎞

⎠

t

= t

+ 16384 × CNT –

+ (192 + LSB) × 64 ×

× t

osc2

min

min0

⎝

MSB

To calculate the maximum Watchdog Timeout (t

):

max

MSB

4

IF

-------------

THEN

ELSE

CNT ≤

t

= t_max0+ 16384 × CNT × t

osc2

max

4CNT

----------------

4CNT

----------------

⎛

⎞

t

= t

+ 16384 × CNT –

+ (192 + LSB) × 64 ×

× t

osc2

max

max0

⎝

⎠

MSB

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

Min. Watchdog

Timeout (ms)

Max. Watchdog

Timeout (ms)

Value of T[5:0] Bits in

WDGCR Register (Hex.)

t

min

max

00

3F

1.496

128

2.048

128.552

50/172

ST72260Gx, ST72262Gx, ST72264Gx

WATCHDOG TIMER (Cont’d)

11.1.5 Low Power Modes

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

OIE bit in

MCCSR

register

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

0

If an external interrupt is received, the Watchdog restarts counting after 256

or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 11.1.7 below.

HALT

0

1

x

A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

11.1.6 Hardware Watchdog Option

11.1.9 Register Description

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

11.1.7 Using Halt Mode with the WDG

(WDGHALT option)

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

The following recommendation applies if Halt

mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

11.1.8 Interrupts

None.

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

counter. It is decremented every 16384 f

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

cy-

OSC2

51/172

ST72260Gx, ST72262Gx, ST72264Gx

Table 12. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

Reset Value

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

0024h

52/172

ST72260Gx, ST72262Gx, ST72264Gx

11.2

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC)

The Main Clock Controller consists of a real time

clock timer with interrupt capability

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Section 8.4

"ACTIVE-HALT AND HALT MODES" on page 35

for more details.

11.2.1

Real Time Clock Timer (RTC)

The counter of the real time clock timer allows an

interrupt to be generated based on an accurate

real time clock. Four different time bases depend-

ing directly on f

are available. The whole

OSC2

functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

Figure 34. Main Clock Controller (MCC/RTC) Block Diagram

f_OSC2

TO WATCHDOG

RTC

COUNTER

TB1 TB0 OIE OIF

MCCSR

MCC/RTC INTERRUPT

53/172

ST72260Gx, ST72262Gx, ST72264Gx

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

11.2.2

Low Power Modes

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time

base. They are set and cleared by software.

Mode

Description

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

WAIT

Time Base

Counter

TB1 TB0

Prescaler

f

=4MHz

f

=8MHz

OSC2

No effect on MCC/RTC counter (OIE bit is

ACTIVE- set), the registers are frozen.

16000

32000

80000

200000

4ms

2ms

4ms

0

1

0

1

0

1

HALT

MCC/RTC interrupt cause the device to exit

8ms

20ms

50ms

from ACTIVE-HALT mode.

10ms

25ms

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

HALT

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real time clock.

11.2.3

Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of the MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

Enable Exit

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Time base overflow

event

1)

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

OIF

OIE

Yes

No

mode

.

Note:

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the CSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

11.2.4

Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

Reset Value: 0000 0000 (00h

)

7

0

TB1 TB0 OIE OIF

Bit 7:4 = reserved

Table 13. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SICSR

Reset Value

AVDIE

0

AVDF

0

LVDRF

x

WDGRF

x

0025h

0026h

0

MCCSR

Reset Value

TB1

0

TB0

0

OIE

0

OIF

0

54/172

ST72260Gx, ST72262Gx, ST72264Gx

11.3 16-BIT TIMER

11.3.1 Introduction

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

11.3.3 Functional Description

11.3.3.1 Counter

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Some devices of the ST7 family have two on-chip

16-bit timers. They are completely independent,

and do not share any resources. They are syn-

chronized after a Device reset as long as the timer

clock frequencies are not modified.

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

This description covers one or two 16-bit timers. In

the devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

11.3.2 Main Features

■ Programmableprescaler:f_CPUdividedby2,4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slowerthantheCPUclockspeed)withthechoice

of active edge

■ Output compare functions with

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

– 1 dedicated maskable interrupt

■ Input capture functions with

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 14 Clock

Control Bits. The value in the counter register re-

peats every 131 072, 262 144 or 524 288 CPU

clock cycles depending on the CC[1:0] bits.

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 35.

*Note: Some timer pins may not available (not

bonded) in some devices. Refer to the device pin

out description.

55/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Figure 35. Timer Block Diagram

INTERNAL BUS

f

CPU

16-BIT TIMER PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

EXEDG

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

0

ICF1 OCF1 TOF ICF2 OCF2

0

TIMD

(Control/Status Register)

OCMP2

CSR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See Device Interrupt Vector Table)

TIMER INTERRUPT

56/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

is buffered

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (Device awakened by an interrupt)

or from the reset count (Device awakened by a

Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

11.3.3.2 External Clock

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The external clock (where available) is selected if

CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronised with the falling edge

of the internal CPU clock.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

57/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Figure 36. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 37. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 38. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-

ning.

58/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

11.3.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 40).

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

LS Byte

ICiR

ICiHR

ICiLR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 14

Clock Control Bits).

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input).

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activate the input cap-

ture function.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input).

Moreover if one of the ICAPi pin is configured

as an input and the second one as an output,

an interrupt can be generated if the user toggle

the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer

range (FFFFh).

59/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Figure 39. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 40. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: The active edge is the rising edge.

Note: The time between an event on the ICAPi pin

and the appearance of the corresponding flag is

from 2 to 3 CPU clock cycles. This depends on the

moment when the ICAP event happens relative to

the timer clock.

60/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

11.3.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCIE bit is set

∆t f

* CPU

PRESC

∆ OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 14

Clock Control Bits)

PRESC

MS Byte

LS Byte

OCiR

OCiHR

OCiLR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Timing resolution is one count of the free running

Where:

counter: (f

).

CC[1:0]

CPU/

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

f

EXT

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 14

Clock Control Bits).

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

61/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

FOLVLi bits have no effect in both one pulse mode

and PWM mode.

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 42 on page

63). This behaviour is the same in OPM or

PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 43 on page 63).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 41. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

FOLV2 FOLV1OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

62/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Figure 42. Output Compare Timing Diagram, f

=f

/2

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 43. Output Compare Timing Diagram, f

=f

/4

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

63/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

11.3.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use one pulse mode:

CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 14

Clock Control Bits)

PRESC

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

OCiR = t f

-5

* EXT

Where:

t

3. Select the following in the CR2 register:

= Pulse period (in seconds)

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

f

= External timer clock frequency (in hertz)

EXT

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 44).

– Select the timer clock CC[1:0] (see Table 14

Clock Control Bits).

One pulse mode cycle

Notes:

ICR1 = Counter

When

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

When a valid event occurs on the ICAP1 pin, the

counter value is loaded in the ICR1 register. The

counter is then initialized to FFFCh, the OLVL2 bit

is output on the OCMP1 pin and the ICF1 bit is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

64/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Figure 44. One Pulse Mode Timing Example

2ED3

01F8

IC1R

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

01F8

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 45. Pulse Width Modulation Mode Timing Example

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

65/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

11.3.3.6 Pulse Width Modulation Mode

Clock Control Bits).

Pulse Width Modulation cycle

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

When

Counter

= OC1R

OCMP1 = OLVL1

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functionality can not be used when

PWM mode is activated.

OCMP1 = OLVL2

When

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are loaded in

their respective shadow registers (double buffer)

only at the end of the PWM period (OC2) to avoid

spikes on the PWM output pin (OCMP1). The

shadow registers contain the reference values for

comparison in PWM “double buffering” mode.

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Note: There is a locking mechanism for transfer-

ring the OCiR value to the buffer. After a write to

the OCiHR register, transfer of the new compare

value to the buffer is inhibited until OCiLR is also

written.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

Unlike in Output Compare mode, the compare

function is always enabled in PWM mode.

CPU

- 5

OCiR Value =

PRESC

Where:

t

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

Procedure

f

To use pulse width modulation mode:

CPU

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 14 Clock

Control Bits)

PRESC

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

If the timer clock is an external clock the formula is:

OCiR = t f

-5

* EXT

Where:

t

3. Select the following in the CR1 register:

= Signal or pulse period (in seconds)

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

f

= External timer clock frequency (in hertz)

EXT

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 45)

Notes:

4. Select the following in the CR2 register:

1. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

2. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Select the timer clock (CC[1:0]) (see Table 14

66/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

3. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

4. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

11.3.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

WAIT

Timer interrupts cause the Device to exit from WAIT mode.

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the Device is woken up by a RESET.

HALT

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

11.3.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

11.3.6 Summary of Timer modes

AVAILABLE RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1)

2)

3)

See note 4 in Section 11.3.3.5 "One Pulse Mode" on page 64

See note 5 in Section 11.3.3.5 "One Pulse Mode" on page 64

See note 4 in Section 11.3.3.6 "Pulse Width Modulation Mode" on page 66

67/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

11.3.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

68/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 14. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

69/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read Only

Note: Reading or writing the ACLR register does

not clear TOF.

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

7

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

0

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

ICF1 OCF1 TOF ICF2 OCF2 TIMD

0

Bit 7 = ICF1 Input Capture Flag 1.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: Timer prescaler, counter and outputs disabled

1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Bits 1:0 = Reserved, must be kept cleared.

70/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

7

0

7

0

MSB

LSB

MSB

LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

7

0

MSB

LSB

MSB

LSB

71/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

72/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Table 15. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

Timer A: 32 CR1

ICIE

0

OCIE

0

TOIE

0

FOLV2

0

FOLV1

0

OLVL2

0

IEDG1

0

OLVL1

0

Timer B: 42 Reset Value

Timer A: 31 CR2

OC1E

0

OC2E

0

OPM

0

PWM

0

CC1

0

CC0

0

IEDG2

0

EXEDG

0

Timer B: 41 Reset Value

Timer A: 33 CSR

ICF1

x

OCF1

x

TOF

x

ICF2

x

OCF2

x

TIMD

0

-

Timer B: 43 Reset Value

x

Timer A: 34 IC1HR

MSB

-

LSB

-

Timer B: 44 Reset Value

Timer A: 35 IC1LR

MSB

-

LSB

-

Timer B: 45 Reset Value

Timer A: 36 OC1HR

MSB

-

LSB

-

Timer B: 46 Reset Value

Timer A: 37 OC1LR

MSB

-

LSB

-

Timer B: 47 Reset Value

Timer A: 3E OC2HR

MSB

-

LSB

-

Timer B: 4E Reset Value

Timer A: 3F OC2LR

MSB

-

LSB

-

Timer B: 4F Reset Value

Timer A: 38 CHR

MSB

1

LSB

1

0

1

Timer B: 48 Reset Value

Timer A: 39 CLR

MSB

1

LSB

0

Timer B: 49 Reset Value

Timer A: 3A ACHR

MSB

1

LSB

1

Timer B: 4A Reset Value

Timer A: 3B ACLR

MSB

1

LSB

0

1

-

1

-

1

-

1

-

1

-

0

-

Timer B: 4B Reset Value

Timer A: 3C ICHR2

MSB

-

LSB

-

Timer B: 4C Reset Value

Timer A: 3D ICLR2

MSB

-

LSB

-

Timer B: 4D Reset Value

73/172

ST72260Gx, ST72262Gx, ST72264Gx

16-BIT TIMER (Cont’d)

Related Documentation

AN1041: Using ST7 PWM signal to generate ana-

log input (sinusoid)

AN 973: SCI software communications using 16-

bit timer

AN1046: UART emulation software

AN 974: Real Time Clock with ST7 Timer Output

Compare

AN1078: PWM duty cycle switch implementing

true 0 or 100 per cent duty cycle

AN 976: Driving a buzzer through the ST7 Timer

PWM function

AN1504: Starting a PWM signal directly at high

level using the ST7 16-Bit timer

74/172

ST72260Gx, ST72262Gx, ST72264Gx

11.4.3 General Description

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

Figure 46 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

11.4.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

■ Six master mode frequencies (f

/4 max.)

CPU

■ f

/2 max. slave mode frequency (see note)

CPU

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

■ SS Management by software or hardware

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

– SS: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master Device.

■ Write collision, Master Mode Fault and Overrun

flags

Note: In slave mode, continuous transmission is

not possible at maximum frequency due to the

software overhead for clearing status flags and to

initiate the next transmission sequence.

75/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

Figure 46. Serial Peripheral Interface Block Diagram

Data/Address Bus

Read

SPIDR

Interrupt

request

Read Buffer

MOSI

7

0

SPICSR

MISO

8-Bit Shift Register

SPIF WCOL OVR MODF

0

SOD SSM SSI

Write

SOD

bit

1

SS

SPI

STATE

0

SCK

CONTROL

7

0

SPICR

MSTR

SPR0

SPIE SPE SPR2

CPOL CPHA SPR1

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SS

76/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.1 Functional Description

sponds by sending data to the master device via

the MISO pin. This implies full duplex communica-

tion with both data out and data in synchronized

with the same clock signal (which is provided by

the master device via the SCK pin).

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 47.

The MOSI pins are connected together and the

MISO pins are connected together. In this way

data is transferred serially between master and

slave (most significant bit first).

To use a single data line, the MISO and MOSI pins

must be connected at each node ( in this case only

simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 50) but master and slave

must be programmed with the same timing mode.

The communication is always initiated by the mas-

ter. When the master device transmits data to a

slave device via MOSI pin, the slave device re-

Figure 47. Single Master/ Single Slave Application

SLAVE

MASTER

MSBit

LSBit

MSBit

LSBit

MISO

MOSI

MISO

MOSI

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

SCK

SS

+5V

Not used if SS is managed

by software

77/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.2 Slave Select Management

In Slave Mode:

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to

manage the Slave Select signal by software. This

is configured by the SSM bit in the SPICSR regis-

ter (see Figure 49)

There are two cases depending on the data/clock

timing relationship (see Figure 48):

If CPHA=1 (data latched on 2nd clock edge):

– SS internal must be held low during the entire

transmission. This implies that in single slave

applications the SS pin either can be tied to

In software management, the external SS pin is

free for other application uses and the internal SS

signal level is driven by writing to the SSI bit in the

SPICSR register.

V

, or made free for standard I/O by manag-

SS

ing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

In Master mode:

– SS internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to write to the shift reg-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see Section 11.4.5.3).

– SS internal must be held high continuously

Figure 48. Generic SS Timing Diagram

Byte 3

Byte 2

MOSI/MISO

Master SS

Byte 1

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Figure 49. Hardware/Software Slave Select Management

SSM bit

SSI bit

1

0

SS internal

SS external pin

78/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.3 Master Mode Operation

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

To operate the SPI in master mode, perform the

following steps in order (if the SPICSR register is

not written first, the SPICR register setting (MSTR

bit ) may be not taken into account):

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 50).

Note: The slave must have the same CPOL

and CPHA settings as the master.

1. Write to the SPICR register:

– Manage the SS pin as described in Section

11.4.3.2 and Figure 48. If CPHA=1 SS must

be held low continuously. If CPHA=0 SS must

be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

50 shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

11.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

The transmit sequence begins when software

writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequence

When data transfer is complete:

– The SPIF bit is set by hardware

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

– An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

When data transfer is complete:

– The SPIF bit is set by hardware

Clearing the SPIF bit is performed by the following

software sequence:

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

register is cleared.

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Clearing the SPIF bit is performed by the following

software sequence:

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

1. An access to the SPICSR register while the

SPIF bit is set

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an Overrun

condition (see Section 11.4.5.2).

2. A read to the SPIDR register.

79/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.4 Clock Phase and Clock Polarity

Figure 50, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 50).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge

Figure 50. Data Clock Timing Diagram

CPHA =1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MSBit

Bit 6

Bit 5

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

CPHA =0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Bit 4

Bit3

Bit 2

Bit 1

LSBit

MISO

(from master)

MSBit

Bit 6

Bit 5

Bit3

MOSI

(from slave)

MSBit

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

80/172

ST72260Gx, ST72262Gx, ST72264Gx

11.4.5.2 Overrun Condition (OVR)

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

An overrun condition occurs, when the master de-

vice has sent a data byte and the slave device has

not cleared the SPIF bit issued from the previously

transmitted byte.

Master mode fault occurs when the master device

has its SS pin pulled low.

When a Master mode fault occurs:

When an Overrun occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the Device and disables the SPI periph-

eral.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

– The MSTR bit is reset, thus forcing the Device

into slave mode.

The OVR bit is cleared by reading the SPICSR

register.

Clearing the MODF bit is done through a software

sequence:

11.4.5.3 Write Collision Error (WCOL)

1. A read access to the SPICSR register while the

MODF bit is set.

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted;

and the software write will be unsuccessful.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Write collisions can occur both in master and slave

mode. See also Section 11.4.3.2 "Slave Select

Management" on page 78.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the CPU oper-

ation.

In a slave device, the MODF bit can not be set, but

in a multi master configuration the Device can be in

slave mode with the MODF bit set.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

The MODF bit indicates that there might have

been a multi-master conflict and allows software to

handle this using an interrupt routine and either

perform to a reset or return to an application de-

fault state.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 51).

Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

RESULT

SPIF =0

WCOL=0

2nd Step

Read SPIDR

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

Note: Writing to the SPIDR regis-

ter instead of reading it does not

reset the WCOL bit

RESULT

2nd Step

Read SPIDR

WCOL=0

81/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5.4 Single Master and Multimaster

Configurations

For more security, the slave device may respond

to the master with the received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written to its SPIDR

register.

There are two types of SPI systems:

– Single Master System

– Multimaster System

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

Single Master System

A typical single master system may be configured,

using a device as the master and four devices as

slaves (see Figure 52).

Multi-Master System

A multi-master system may also be configured by

the user. Transfer of master control could be im-

plemented using a handshake method through the

I/O ports or by an exchange of code messages

through the serial peripheral interface system.

The master device selects the individual slave de-

vices by using four pins of a parallel port to control

the four SS pins of the slave devices.

The SS pins are pulled high during reset since the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

The multi-master system is principally handled by

the MSTR bit in the SPICR register and the MODF

bit in the SPICSR register.

Note: To prevent a bus conflict on the MISO line

the master allows only one active slave device

during a transmission.

Figure 52. Single Master / Multiple Slave Configuration

SS

SCK

Slave

SCK

Slave

SCK

Slave

Device

MOSI MISO

SCK

Master

Device

5V

SS

82/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.6 Low Power Modes

SS pin or the SSI bit in the SPICSR register) is low

when the Device enters Halt mode. So if Slave se-

lection is configured as external (see Section

11.4.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

Mode

Description

No effect on SPI.

WAIT

SPI interrupt events cause the Device to exit

from WAIT mode.

11.4.7 Interrupts

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the Device is woken up

by an interrupt with “exit from HALT mode”

capability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the Device.

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

SPI End of Trans-

fer Event

HALT

SPIF

Yes

Master Mode

Fault Event

SPIE

MODF

OVR

Yes

No

Overrun Error

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

11.4.6.1 Using the SPI to wake-up the Device

from Halt mode

In slave configuration, the SPI is able to wake-up

the Device from HALT mode through a SPIF inter-

rupt. The data received is subsequently read from

the SPIDR register when the software is running

(interrupt vector fetch). If multiple data transfers

have been performed before software clears the

SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode, if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake-up the Device from

Halt mode only if the Slave Select signal (external

83/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit de-

termines the idle state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

Reset Value: 0000 xxxx (0xh)

7

0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Over-

run error occurs (SPIF=1, MODF=1 or OVR=1

in the SPICSR register)

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 11.4.5.1 "Master Mode Fault

(MODF)" on page 81). The SPE bit is cleared by

reset, so the SPI peripheral is not initially connect-

ed to the external pins.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used

with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master

mode.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Note: These 2 bits have no effect in slave mode.

Bit 5 = SPR2 Divider Enable.

This bit is set and cleared by software and is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 16 SPI Master

mode SCK Frequency.

Table 16. SPI Master mode SCK Frequency

Serial Clock

SPR2 SPR1 SPR0

f

/4

/8

1

0

1

0

1

0

1

0

1

CPU

0: Divider by 2 enabled

1: Divider by 2 disabled

f

/16

/32

/64

CPU

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 11.4.5.1 "Master Mode Fault

(MODF)" on page 81).

f

/128

CPU

0: Slave mode

1: Master mode. The function of the SCK pin

changes from an input to an output and the func-

tions of the MISO and MOSI pins are reversed.

84/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 2 = SOD SPI Output Disable.

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

7

0

SPIF

WCOL OVR MODF

-

SOD SSM SSI

1: SPI output disabled

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

Bit 1 = SSM SS Management.

This bit is set and cleared by software. When set, it

disables the alternate function of the SPI SS pin

and uses the SSI bit value instead. See Section

11.4.3.2 "Slave Select Management" on page 78.

0: Hardware management (SS managed by exter-

nal pin)

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a

software sequence (an access to the SPICSR

register followed by a write or a read to the

SPIDR register).

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin free for gener-

al-purpose I/O)

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the Device and an exter-

nal device has been completed.

Bit 0 = SSI SS Internal Mode.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave

select signal when the SSM bit is set.

0 : Slave selected

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit se-

quence. It is cleared by a software sequence (see

Figure 51).

0: No write collision occurred

1: A write collision has been detected

1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware when the byte currently

being received in the shift register is ready to be

transferred into the SPIDR register while SPIF = 1

(See Section 11.4.5.2). An interrupt is generated if

SPIE = 1 in the SPICR register. The OVR bit is

cleared by software reading the SPICSR register.

0: No overrun error

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

register is moved to a buffer. When the user reads

the serial peripheral data I/O register, the buffer is

actually being read.

1: Overrun error detected

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 11.4.5.1

"Master Mode Fault (MODF)" on page 81). An SPI

interrupt can be generated if SPIE=1 in the SPICR

register. This bit is cleared by a software sequence

(An access to the SPICSR register while MODF=1

followed by a write to the SPICR register).

While the SPIF bit is set, all writes to the SPIDR

register are inhibited until the SPICSR register is

read.

Warning: A write to the SPIDR register places

data directly into the shift register for transmission.

A read to the SPIDR register returns the value lo-

cated in the buffer and not the content of the shift

register (see Figure 46).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

85/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 17. SPI Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

SPIDR

Reset Value

MSB

x

LSB

x

0021h

0022h

0023h

x

SPICR

Reset Value

SPIE

0

SPE

0

SPR2

0

MSTR

0

CPOL

x

CPHA

x

SPR1

x

SPR0

x

SPICSR

Reset Value

SPIF

0

WCOL

0

OR

0

MODF

0

SOD

0

SSM

0

SSI

0

86/172

ST72260Gx, ST72262Gx, ST72264Gx

11.5.3 General Description

11.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

11.5.1 Introduction

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI of-

fers a very wide range of baud rates using two

baud rate generator systems.

The interface is externally connected to another

device by two pins (see Figure 54):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin

returns to its I/O port configuration. When the

transmitter and/or the receiver are enabled and

nothing is to be transmitted, the TDO pin is at

high level.

11.5.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

■ Dual baud rate generator systems

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

■ Independently programmable transmit and

receive baud rates up to 500K baud.

Through these pins, serial data is transmitted and

received as frames comprising:

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

– An Idle Line prior to transmission or reception

– A start bit

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

Thisinterfaceusestwotypesofbaudrategenerator:

– Idle line

■ Mutingfunctionformultiprocessorconfigurations

– A conventional type for commonly-used baud

rates,

■ Separate enable bits for Transmitter and

Receiver

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard

oscillator frequencies.

■ Four error detection flags:

– Overrun error

– Noise error

– Frame error

– Parity error

■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

■ Parity control:

– Transmits parity bit

– Checks parity of received data byte

■ Reduced power consumption mode

87/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 53. SCI Block Diagram

Write

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Received Shift Register

Transmit Data Register (TDR)

TDO

Transmit Shift Register

RDI

CR1

R8 T8 SCID

M WAKE PCE PS PIE

WAKE

UP

TRANSMIT

CONTROL

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

CR2

SR

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF IDLE OR NF FE

PE

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

TRANSMITTER RATE

CONTROL

f

CPU

/PR

/16

BRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

88/172

ST72260Gx, ST72262Gx, ST72264Gx

11.5.4.1 Serial Data Format

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4 Functional Description

The block diagram of the Serial Control Interface,

is shown in Figure 53. It contains 6 dedicated reg-

isters:

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 53).

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

– A baud rate register (SCIBRR)

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

– An extended prescaler receiver register (SCIER-

PR)

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

11.5.7for the definitions of each bit.

Transmission and reception are driven by their

own baud rate generator.

Figure 54. Word Length Programming

9-bit Word length (M bit is set)

Possible

Next Data Frame

Parity

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit6

Bit3

Bit4

Bit5

Bit7

Bit8

Bit0 Bit1

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Frame

Data Frame

Bit

Start

Bit

Stop

Bit

Bit2

Bit1

Bit3

Bit4

Bit5

Bit6

Bit0

Bit7

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

89/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.2 Transmitter

When a frame transmission is complete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is set and

the I bit is cleared in the CCR register.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

register.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 53).

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 54).

Procedure

– Select the M bit to define the word length.

As long as the SBK bit is set, the SCI send break

frames to the TDO pin. After clearing this bit by

software the SCI insert a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first

transmission.

Idle Characters

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

register at the end of the current transmission.

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

90/172

ST72260Gx, ST72262Gx, ST72264Gx

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.4.3 Receiver

RDR register as long as the RDRF bit is not

cleared.

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

register.

When a overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

Character reception

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) be-

tween the internal bus and the received shift regis-

ter (see Figure 53).

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

Procedure

Noise Error

– Select the M bit to define the word length.

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise. Normal data bits are considered valid if

three consecutive samples (8th, 9th, 10th) have

the same bit value, otherwise the NF flag is set. In

the case of start bit detection, the NF flag is set on

the basis of an algorithm combining both valid

edge detection and three samples (8th, 9th, 10th).

Therefore, to prevent the NF flag getting set during

start bit reception, there should be a valid edge de-

tection as well as three valid samples.

– Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

When noise is detected in a frame:

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

– The NF flag is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

Clearing the RDRF bit is performed by the following

software sequence done by:

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

The NF flag is reset by a SCISR register read op-

eration followed by a SCIDR register read opera-

tion.

Break Character

During reception, if a false start bit is detected (e.g.

8th, 9th, 10th samples are 011,101,110), the

frame is discarded and the receiving sequence is

not started for this frame. There is no RDRF bit set

for this frame and the NF flag is set internally (not

accessible to the user). This NF flag is accessible

along with the RDRF bit when a next valid frame is

received.

When a break character is received, the SPI han-

dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CCR register.

Note: If the application Start Bit is not long enough

to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this

case, the NF flag may be ignored by the applica-

tion software when the first valid byte is received.

Overrun Error

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the


型号：	ST72F262G2B5
厂家：	ST
描述：	8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES 8位MCU的Flash或ROM存储器， ADC ，两个16位定时器， I2C ， SPI ， SCI INTERFACES 存储微控制器和处理器外围集成电路光电二极管时钟
文件：	总172页 (文件大小：1466K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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