ST72F344S4T6 [STMICROELECTRONICS]
8-BIT MCU WITH UP TO 16K FLASH MEMORY, 10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI; 8位MCU具有高达16K闪存， 10位ADC ， 2个16位定时器，2个I2C ， SPI ， SCI
| 型号： | ST72F344S4T6 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH UP TO 16K FLASH MEMORY, 10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI |
| 文件： | 总191页 (文件大小：3276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST72340, ST72344, ST72345
8-BIT MCU WITH UP TO 16K FLASH MEMORY,
10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI
■ Memories
– up to 16 Kbytes Program memory: Single volt-
age extended Flash (XFlash) with read-out
and write protection, In-Circuit and In-Applica-
tion Programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55°C.
LQFP44
10 x 10
LQFP48
7 x 7
– up to 1 Kbyte RAM
– 256 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management
LQFP32
7 x 7
– Power On / Power Off safe reset with 3 pro-
grammable threshold levels (LVD)
– 16-bit timer B with: 2 input captures, 2 output
compares, PWM and Pulse generator modes
■ 3 Communication Interfaces
– Auxiliary Voltage Detector (AVD)
– Clock sources: crystal/ceramic resonator os-
cillators, high-accuracy internal RC oscillator
or external clock
2
– I C Multi Master / Slave
2
– PLL for 4x or 8x frequency multiplication
– I C Slave 3 Addresses No Stretch with DMA
access and Byte Pair Coherency on I²C Read
– 5 Power Saving Modes: Slow, Wait, Halt,
Auto-Wakeup from Halt and Active Halt
– SCI asynchronous serial interface (LIN com-
patible)
– Clock output capability (f
)
CPU
– SPI synchronous serial interface
■ 1 Analog peripheral
■ Interrupt Management
– Nested interrupt controller
– 10-bit ADC with 12 input channels (8 on 32-
– 10 interrupt vectors plus TRAP and RESET
– 9 external interrupt lines on 4 vectors
■ Up to 34 I/O Ports
pin devices)
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode de-
– up to 34 multifunctional bidirectional I/O lines
– up to 12 high sink outputs (10 on 32-pin devic-
tection
es)
■ 4 Timers
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development tools
– Configurable window watchdog timer
– Realtime base
– 16-bit timer A with: 1 input capture, 1 output
compares, external clock input, PWM and
Pulse generator modes
– Full hardware/software development package
– On-Chip Debug Module
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
EEPROM data - bytes
Common peripherals
Other peripherals
ST72F340
ST72F344
ST72F345
16K
8K
16K
1K (256)
256
8K
16K
1K (256)
256
512 (256)
256
512 (256)
256
1K (256)
256
Window Watchdog, 2 16-bit Timers, SCI, SPI, I2CMMS
-
10-bit ADC
Present
I2C3SNS, 10-bit ADC
Present
Int high-accuracy 1MHz RC
CPU Frequency
Not present
8MHz @ 3.3V to 5.5V, 4MHz @ 2.7V to 5.5V
-40°C to +85 °C
Temperature Range
Package
LQFP32 7x7, LQFP44 10x10
LQFP48 7x7
Rev. 2
October 2006
1/191
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.5 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 42
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Table of Contents
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 65
11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5 SCI SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.7 I2C TRIPLE SLAVE INTERFACE WITH DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13.4 PLL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.5 INTERNAL RC OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 156
13.6 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.7 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.8 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.9 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.10 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13.11 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 174
13.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 181
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.1 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 188
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Table of Contents
16.3 16-BIT TIMER PWM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.4 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.5 IN-APPLICATION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.6 PROGRAMMING OF EEPROM DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
16.7 FLASH WRITE/ERASE PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Please pay special attention to the Section “KNOWN LIMITATIONS” on page 187
4/191
ST72340, ST72344, ST72345
1 INTRODUCTION
The ST7234x devices are members of the ST7 mi-
crocontroller family. All devices are based on a
common industry-standard 8-bit core, featuring an
enhanced instruction set.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
They feature single-voltage FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capabilities.
Under software control, all devices can be placed
in WAIT, SLOW, Auto-Wakeup from Halt, Active-
HALT or HALT mode, reducing power consump-
tion when the application is in idle or stand-by
state.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Figure 1. General Block Diagram
8-BIT CORE
ALU
PROGRAM
MEMORY
(16K - 32K Bytes)
RESET
CONTROL
RAM
(512- 1024 Bytes)
V
V
SS
DD
LVD
AVD
WATCHDOG
OSC1
OSC2
CLOCK CONTROL
INTERNAL RC
I2CMMS
PA
(5-bits)
PORT A
MCC/RTC/BEEP
PORT B
PB
(5-bits)
PORT F
TIMER A
BEEP
PWM ART
PORT C
PF
(6-bits)
PC
TIMER B
(8-bits)
I2C3SNS
SPI
PD
(6-bits)
PORT D
PORT E
10-BIT ADC
PE
(2-bits)
V
V
AREF
SCI
SSA
5/191
ST72340, ST72344, ST72345
2 PIN DESCRIPTION
Figure 2. LQFP32 Package Pinout
32 31 30 29 28 27 26 25
24
V
V
1
2
3
4
5
6
7
8
OSC1
OSC2
DDA
ei3 ei2 ei0
23
22
21
20
19
18
17
SSA
AIN8 / PF0
(HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
V
_2
SS
ei1
RESET
ICCSEL
PA7 (HS) / SCL
PA6 (HS) / SDA
PA4 (HS)
ei0
9 10 11 12 13 14 15 16
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 3. LQFP44 Package Pinout
44 43 42 41 40 39 38 37 36 35 34
ei0
RDI / PE1
PB0
1
V
V
33
SS_1
2
32
31
30
29
28
27
26
25
24
23
DD_1
PB1
PB2
PB3
3
PA3 (HS)
PC7 / SS / AIN15
ei0
ei2
ei3
4
5
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
6
7
8
9
10
11
ei1
12 13 14 15 16 17 18 19 20 21 22
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ST72340, ST72344, ST72345
PIN DESCRIPTION (Cont’d)
Figure 4. LQFP48 Package Pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
V
PE0/TD0
RDI / PE1
PB0
1
2
3
4
5
6
7
8
9
10
SS_1
V
ei0
ei2
ei3
35
34
33
32
31
30
29
28
27
26
25
DD_1
PA3 (HS)
ei0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
NC
NC
PB1
PB2
PB3
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
11
12
ei1
24
13 14 15 16 17 18 19 20 21 22 23
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ST72340, ST72344, ST72345
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 152.
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
A = Dedicated analog input
Input level:
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are set in in-
put pull-up configuration after reset through the option byte Package selection. The configuration of these
pads must be kept at reset state to avoid added current consumption.
Table 1. Device Pin Description
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
1
2
13 14
14 15
V
V
S
S
Analog Supply Voltage
Analog Ground Voltage
DDA
SSA
PF0/MCO/
AIN8
Main clock out
(f /2)
ADC Analog
Input 8
3
4
15 16
16 17
I/O C
X
ei1
ei1
X
X
X
Port F0
T
OSC
PF1 (HS)/
BEEP
I/O C
I/O C
HS
X
X
X
X
X
X
Port F1
Port F2
Beep signal output
T
T
17 18 PF2 (HS)
HS
ei1
PF4/
18 19 OCMP1_A/
AIN10
Timer A Output ADC Analog
Compare 1 Input 10
5
I/O C
X
X
X
X
X
Port F4
T
PF6 (HS)/
19 20
6
7
I/O C
I/O C
HS
HS
X
X
X
X
X
X
X
X
Port F6
Port F7
Timer A Input Capture 1
T
T
ICAP1_A
PF7 (HS)/
20 21
Timer A External Clock Source
EXTCLK_A
-
-
21 22
22 23
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_0
SS_0
PC0/
Timer B Output ADC Analog
Compare 2 Input 12
8
9
23 24 OCMP2_B/
AIN12
I/O C
X
X
X
X
X
X
Port C0
T
PC1/
24 27 OCMP1_B/
AIN13
Timer B Output ADC Analog
Compare 1 Input 13
I/O C
I/O C
X
X
X
X
X
X
X
X
Port C1
Port C2
T
T
PC2 (HS)/
ICAP2_B
10 25 28
HS
Timer B Input Capture 2
8/191
ST72340, ST72344, ST72345
Pin n°
Level
Port
Main
function
(after
Input
Output
Pin Name
Alternate Function
reset)
PC3 (HS)/
ICAP1_B
11 26 29
12 27 30
13 28 31
14 29 32
I/O C
I/O C
I/O C
I/O C
HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port C3
Port C4
Port C5
Port C6
Timer B Input Capture 1
T
T
T
T
PC4/MISO/
SPI Master In /
ICC Data In-
3)
ICCDATA
Slave Out Data put
PC5/MOSI/
AIN14
SPI Master Out / ADC Analog
X
X
Slave In Data
Input 14
PC6/SCK/
ICC Clock
Output
SPI Serial Clock
3)
ICCCLK
SPI Slave Select ADC Analog
(active low) Input 15
15 30 33 PC7/SS/AIN15 I/O C
X
X
X
X
X
X
Port C7
Port A3
T
T
16 31 34 PA3 (HS)
I/O C
HS
ei0
-
-
32 35
33 36
V
V
S
S
Digital Main Supply Voltage
Digital Ground Voltage
DD_1
SS_1
PD7/
SCL3SNS
-
-
-
-
37
38
I/O C
I/O C
HS
HS
X
X
T
T
Port D7
Port D6
I2C3SNS Serial Clock
I2C3SNS Serial Data
T
T
PD6/
SDA3SNS
17 34 39 PA4 (HS)
35 40 PA5 (HS)
I/O C
I/O C
HS
HS
HS
HS
X
X
X
X
X
X
X
X
T
T
X
X
Port A4
Port A5
Port A6
Port A7
T
T
T
T
18 36 41 PA6 (HS)/SDA I/O C
19 37 42 PA7 (HS)/SCL I/O C
I2C Serial Data
I2C Serial Clock
20 38 43 ICCSEL
21 39 44 RESET
I
ICC Mode selection
I/O C
Top priority non maskable interrupt.
Digital Ground Voltage
T
22 40 45
V
S
SS_2
23 41 46 OSC2
O
Resonator oscillator inverter output
External clock input or Resonator oscillator in-
verter input
24 42 47 OSC1
I
25 43 48
V
S
Digital Main Supply Voltage
DD_2
26 44
1
2
3
4
5
6
7
8
9
PE0/TDO
PE1/RDI
PB0
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E0
Port E1
Port B0
Port B1
Port B2
Port B3
Port B4
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
SCI Transmit Data Out
SCI Receive Data In
T
T
T
T
T
T
T
T
T
T
T
T
T
27
28
-
1
2
3
4
5
6
7
8
9
ei0
ei2
PB1
ei2
ei2
-
PB2
29
30
31
32
-
PB3
ei2
ei3
PB4 (HS)
PD0/AIN0
PD1/AIN1
HS
X
X
X
X
X
X
X
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
X
X
X
X
X
10 PD2/AIN2
-
10 11 PD3/AIN3
11 12 PD4/AIN4
12 13 PD5/AIN5
-
9/191
ST72340, ST72344, ST72345
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented).
DD
3. On the BGA package, ICCDATA and ICCCLK are bonded on pins E3 and A4 respectively. They are not
implemented as alternate functions on PC4 and PC6.
10/191
ST72340, ST72344, ST72345
3 REGISTER & MEMORY MAP
As shown in Figure 5, the MCU is capable of ad-
dressing 64 Kbytes of memories and I/O registers.
of user program memory. The RAM space in-
cludes up to 256 bytes for the stack from 0100h to
01FFh.
The available memory locations consist of 128
bytes of register locations, up to 1 Kbytes of RAM,
256 bytes of Data EEPROM and up to 16 Kbytes
The highest address bytes contain the user reset
and interrupt vectors.
Figure 5. Memory Map
0000h
0080h
HW Registers
See Table
Short Addressing
RAM (zero page)
007Fh
0080h
00FFh
0100h
RAM
(512 or 1K Bytes)
047Fh
0480h
256 Bytes Stack
01FFh
0200h
Reserved
16-bit Addressing
RAM
0BFFh
0C00h
Data EEPROM
(256 Bytes)
047Fh
C000h
0CFFh
0D00h
C000h
E000h
Reserved
SECTOR 2
SECTOR 1
SECTOR 0
BFFFh
C000h
16 KBytes
8 KBytes
Program Memory
(8 or 16 KBytes)
E000h
FFFFh
FFDFh
FFE0h
F000h (4k)
or FB00h (2k)
or FC00h (1k)
or FE00h (0.5k)
Interrupt & Reset Vectors
See Table 8
FFFFh
FFFFh
11/191
ST72340, ST72344, ST72345
REGISTER AND MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Register
Label
Address
Block
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset Status
Remarks
R/W
R/W
R/W
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
00h
2)
Port A
Port B
Port C
Port D
Port E
00h
00h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
2)
2)
2)
2)
00h
00h
1)
0006h
0007h
0008h
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h
R/W
R/W
R/W
00h
00h
1)
0009h
000Ah
000Bh
PDADR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h
R/W
R/W
R/W
00h
00h
1)
000Ch
000Dh
000Eh
PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h
R/W
R/W
R/W
00h
00h
1)
000Fh
0010h
0011h
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h
R/W
R/W
R/W
2)
Port F
00h
00h
0012h to
0016h
Reserved area (5 bytes)
0017h
0018h
RCCRH
RCCRL
RC oscillator Control Register High
RC oscillator Control Register Low
FFh
03h
R/W
R/W
RC
0019h
Reserved area (1 byte)
001Ah to
001Fh
3)
DM
Reserved area (6 bytes)
00020h EEPROM EECSR
Data EEPROM Control/Status Register
00h
R/W
0021h
0022h
0023h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
ITC
0024h
0025h
0026h
0027h
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0028h
00029h
002Ah
002Bh
EICR
External Interrupt Control Register
Flash Control/Status Register
00h
00h
R/W
R/W
R/W
R/W
FLASH
WWDG
SI
FCSR
WDGCR
SICSR
Watchdog Control Register
7Fh
System Integrity Control/Status Register
000x 000xb
12/191
ST72340, ST72344, ST72345
Register
Label
Address
Block
Register Name
Reset Status
Remarks
R/W
002Ch
002Dh
MCCSR
MCCBCR
Main Clock Control/Status Register
MCC Beep Control Register
00h
00h
MCC
R/W
002Eh
002Fh
AWUCSR
AWUPR
AWU Control/Status Register
AWU Prescaler Register
00h
FFh
R/W
R/W
AWU
0030h
WWDG
WDGWR
Window Watchdog Control Register
7Fh
R/W
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
TIMER A TACHR
TACLR
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer A Counter Low Register
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
R/W
0040h
Reserved Area (1 Byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
TBOC1HR
TBOC1LR
TIMER B TBCHR
TBCLR
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
Timer B Counter Low Register
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
Reserved area
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
Read Only
R/W
R/W
R/W
R/W
x000 0000b
00h
SCI
--
00h
00h
SCIERPR
SCIETPR
R/W
R/W
13/191
ST72340, ST72344, ST72345
Register
Label
Address
Block
Register Name
Reset Status
Remarks
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
2
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
I2CCR
I C Control Register
I C Status Register 1
I C Status Register 2
I C Clock Control Register
I C Own Address Register 1
I C Own Address Register2
I C Data Register
00h
00h
00h
00h
00h
40h
00h
2
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
2
2
2
I C
2
2
2
005Fh
Reserved area (1 byte)
2
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
I2C3SCR1
I2C3SCR2
I2C3SSR
I C3SNS Control Register 1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
2
I C3SNS Control Register 2
2
I C3SNS Status Register
2
I2C3SBCR
I C3SNS Byte Count Register
2
I2C3SSAR1 I C3SNS Slave Address 1 Register
2
I C3SNS
2
I2C3SCAR1 I C3SNS Current Address 1 Register
2
I2C3SSAR2 I C3SNS Slave Address 2 Register
2
I2C3SCAR2 I C3SNS Current Address 2 Register
2
I2C3SSAR3 I C3SNS Slave Address 3 Register
2
I2C3SCAR3 I C3SNS Current Address 3 Register
R/W
0070h
0071h
0072h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Data Low Register
00h
xxh
0000 00xxb
R/W
Read Only
Read Only
ADC
0073h to
007Fh
Reserved area (13 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.
14/191
ST72340, ST72344, ST72345
the device from the application board and
while the application is running.
4 FLASH PROGRAM MEMORY
4.3.1 In-Circuit Programming (ICP)
4.1 Introduction
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
– Download ICP Driver code in RAM from the
ICCDATA pin
4.2 Main Features
■ ICP (In-Circuit Programming)
■ IAP (In-Application Programming)
– Execute ICP Driver code in RAM to program
the FLASH memory
■ ICT (In-Circuit Testing) for downloading and
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection
4.3.2 In Application Programming (IAP)
4.3 PROGRAMMING MODES
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be pro-
grammed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
15/191
ST72340, ST72344, ST72345
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
ICP needs a minimum of 4 and up to 7 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– ICCSEL: ICC selection
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2
pins)
– V : application board power supply (option-
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
4. Pin 9 has to be connected to the OSC1 pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte. ST7 devices with mul-
ti-oscillator capability need to have OSC2 ground-
ed in this case.
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
10kΩ
APPLICATION
POWER SUPPLY
C
C
L2
L1
APPLICATION
I/O
See Note 1
ST7
16/191
ST72340, ST72344, ST72345
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
vent any change being made to the memory con-
tent.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
4.5.1 Read out Protection
Write/erase protection is enabled through the
FMP_W bit in the option byte.
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
4.6 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
2
Both program and data E memory are protected.
In flash devices, this protection is removed by re-
programming the option. In this case, both pro-
2
gram and data E memory are automatically
erased, and the device can be reprogrammed.
7
0
0
Read-out protection selection depends on the de-
vice type:
0
0
0
0
OPT
LAT
PGM
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations. For details on XFlash programming, refer
to the ST7 Flash Programming Reference Manual.
– In ROM devices it is enabled by mask option
specified in the Option List.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
2
ry. It does not apply to E data. Its purpose is to
provide advanced security to applications and pre-
17/191
ST72340, ST72344, ST72345
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non-volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Read-out protection
Figure 7. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
18/191
ST72340, ST72344, ST72345
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.
When E2PGM bit is set by the software, all the
previous bytes written in the data latches (up to
32) are programmed in the EEPROM cells. The ef-
fective high address (row) is determined by the
last EEPROM write sequence. To avoid wrong
programming, the user must take care that all the
bytes written between two programming sequenc-
es have the same high address: only the five Least
Significant Bits of the address can change.
Read Operation (E2LAT = 0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared.
The programming cycle is fully completed when
the E2PGM bit is cleared.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being execut-
ed.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8. Data EEPROM Programming Flowchart
READ MODE
E2LAT = 0
WRITE MODE
E2LAT = 1
E2PGM = 0
E2PGM = 0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2PGM
CLEARED BY HARDWARE
19/191
ST72340, ST72344, ST72345
DATA EEPROM (Cont’d)
2
Figure 9. Data E PROM Write Operation
⇓ Row / Byte ⇒
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
Byte 1 Byte 2
PHASE 1
Byte 32
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not
be guaranteed.
20/191
ST72340, ST72344, ST72345
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT = 1, then the
data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active Halt
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT = 0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory will not
be guaranteed.
5.6 DATA EEPROM READ-OUT PROTECTION
Active Halt mode
The read-out protection is enabled through an op-
tion bit (see option byte section).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Pro-
gram memory and EEPROM is first automatically
erased.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 10. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA
LATCHES
t
PROG
E2LAT
E2PGM
I bit in CC register
1)
ALL INTERRUPTS MUST BE MASKED
Note 1: refer to “Programming of EEPROM data” on page 189
21/191
ST72340, ST72344, ST72345
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed
22/191
ST72340, ST72344, ST72345
DATA EEPROM (Cont’d)
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
E2LAT
0
E2PGM
0
0020h
0
0
0
0
0
0
Reset Value
23/191
ST72340, ST72344, ST72345
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
6.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The six CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
6.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 11. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
24/191
ST72340, ST72344, ST72345
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Reset Value: 111x1xxx
7
0
This bit is accessed by the JREQ and JRNE test
instructions.
1
1
I1
H
I0
N
Z
C
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
0: No half carry has occurred.
1: A half carry has occurred.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Level 1
Level 2
Bit 2 = N Negative.
Level 3 (= interrupt disable)
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
See the interrupt management chapter for more
details.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 1 = Z Zero.
25/191
ST72340, ST72344, ST72345
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
7
0
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 12.
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 12).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 12. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
26/191
ST72340, ST72344, ST72345
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components.
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
Main features
■ Clock Management
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– 1 MHz high-accuracy internal RC oscillator
(enabled by option byte)
– Auxiliary Voltage Detector (AVD) with inter-
rupt capability for monitoring the main supply
(enabled by option byte)
– 1 to 16 MHz External crystal/ceramic resona-
tor (enabled by option byte)
Figure 13. Clock, Reset and Supply Block Diagram
RCCRH/RCCRL Register
MAIN CLOCK
CONTROLLER
f
CPU
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
WITH REAL TIME
CLOCK(MCC/RTC)
Tunable
RC Oscillator
External Clock (0.5-8MHz)
RC Clock (1MHz.)
1MHz
f
OSC2
8MHz
PLL 1MHz --> 8MHz
/2
DIVIDER
/2
4MHz
PLL 1MHz --> 4MHz
DIVIDER*
PLL Clock 8/4MHz
OSC Option bit
PLLx4x8
Option bit
DIV2EN
OSC, PLLOFF
Option bit*
OSCRANGE[2:0]
Option bits
OSC
1-16 MHz
OSC1
OSC2
Crystal OSC (0.5-8MHz)
/2
DIVIDER
*not available if PLLx4 is enabled
27/191
ST72340, ST72344, ST72345
7.1 PHASE LOCKED LOOP
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
clock after a delay of t
.
STARTUP
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
bled and the multiplication factor of 4 or 8 is select-
ed by 3 option bits. Refer to Table 4 for the PLL
configuration depending on the required frequency
and the application voltage. Refer to Section 15.1
for the option byte description.
is set. Full PLL accuracy (ACC ) is reached after
PLL
a stabilization time of t
(see Figure 14 )
STAB
Refer to Section 7.5.4 on page 35 for a description
of the LOCKED bit in the SICSR register.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required.
Table 4. PLL Configurations
Target Ratio
V
PLL Ratio
DIV2
OFF
ON
DD
1)
x4
2.7V - 3.65V
x4
x8
x8
x4
x8
3.3V - 5.5V
OFF
1)
For a target ratio of x4 between 3.3V - 3.65V,
this is the recommended configuration.
Figure 14. PLL Output Frequency Timing
Diagram
LOCKED bit set
4/8 x
input
freq.
t
STAB
t
LOCK
t
STARTUP
t
28/191
ST72340, ST72344, ST72345
7.2 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
three different source types coming from the multi-
oscillator block:
■ an external source
■ 4 crystal or ceramic resonator oscillators
■ an internal high-accuracy RC oscillator
tance values must be adjusted according to the
selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 5. ST7 Clock Sources
Hardware Configuration
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 5. Refer to the
electrical characteristics section for more details.
ST7
OSC1
OSC2
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con-
EXTERNAL
SOURCE
figuration, could generate an f
clock frequency
OSC
in excess of the allowed maximum (>16MHz.),
putting the ST7 in an unsafe/undefined state. The
product behaviour must therefore be considered
undefined when the OSC pins are left unconnect-
ed.
ST7
OSC1
OSC2
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
C
C
L2
L1
LOAD
CAPACITORS
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to Section 15.1 on page 181 for more details on
the frequency ranges). In this mode of the multi-
oscillator, the resonator and the load capacitors
have to be placed as close as possible to the oscil-
lator pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
ST7
OSC1
OSC2
29/191
ST72340, ST72344, ST72345
MULTI-OSCILLATOR (Cont’d)
Internal RC Oscillator
7.3 REGISTER DESCRIPTION
The device contains a high-precision internal RC
oscillator. It must be calibrated to obtain the fre-
quency required in the application. This is done by
software writing a calibration value in the RCCRH
and RCCRL Registers.
RC CONTROL REGISTER (RCCRH)
Read / Write
Reset Value: 1111 1111 (FFh)
7
0
Whenever the microcontroller is reset, the RCCR
returns to its default value (FF 03h), i.e. each time
the device is reset, the calibration value must be
loaded in the RCCRH and RCCRL registers. Pre-
defined calibration values are stored in XFLASH
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad-
justment Bits
for 3 and 5V V
supply voltages at 25°C, as
DD
shown in the following table.
RCCR
Conditions
=5V
T =25°C
Address
BEE0, BEE1
RC CONTROL REGISTER (RCCRL)
Read / Write
Reset Value: 0000 0011 (03h)
V
DD
RCCR0
A
f
=1MHz
RC
V
=3V
DD
7
0
0
RCCR1
T =25°C
BEE4, BEE5
A
f
=1MHz
RC
0
0
0
0
0
CR1 CR0
Note:
– To improve clock stability, it is recommended to
place a decoupling capacitor between the V
Bits 7:2 = Reserved, must be kept cleared.
DD
and V pins.
SS
Bits 1:0 = CR[1:0] RC Oscillator Frequency Ad-
justment Bits
– These two 10-bit values are systematically pro-
grammed by ST, including on FASTROM devic-
es. Consequently, customers intending to use
FASTROM service must not use these address-
es.
This 10-bit value must be written immediately after
reset to adjust the RC oscillator frequency in order
to obtain the specified accuracy. The application
can store the correct value for each voltage range
in EEPROM and write it to this register at start-up.
0000h = maximum available frequency
– RCCR0 and RCCR1 calibration values will be
erased if the read-out protection bit is reset after
it has been set. See “Memory Protection” on
page 17.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
03FFh = lowest available frequency
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 200h.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
30/191
ST72340, ST72344, ST72345
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
of the external oscillator used in the application
(see Section 15.1 on page 181).
The reset sequence manager includes three RE-
SET sources as shown in Figure 16:
■ External RESET source pulse
The RESET vector fetch phase duration is 2 clock
cycles.
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 15. RESET Sequence Phases
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Section 12.2.1 on page 149 for further de-
tails.
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Active Phase
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
7.4.2 Asynchronous External RESET pin
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
The basic RESET sequence consists of 3 phases
as shown in Figure 15:
■ Active Phase depending on the RESET source
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
■ 256 or 4096 CPU clock cycle delay (selected by
“ELECTRICAL
CHARACTERISTICS”
on
option byte)
page 152 for more details.
■ RESET vector fetch
A RESET signal originating from an external
source must have a duration of at least t in
order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
h(RSTL)in
Figure 16. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
WATCHDOG RESET
PULSE
GENERATOR
ILLEGAL OPCODE RESET 1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 149. for more details on illegal opcode reset conditions.
31/191
ST72340, ST72344, ST72345
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.4.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
If the external RESET pulse is shorter than
■ Voltage Drop RESET
t
(see short ext. Reset in Figure 17), the
w(RSTL)out
The device RESET pin acts as an output that is
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 17). Starting from the external RE-
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 17.
DD
IT-
The LVD filters spikes on V larger than t
to
DD
g(VDD)
avoid parasitic resets.
t
.
w(RSTL)out
Note:
7.4.3 External Power-On RESET
It is recommended to make sure that the V sup-
DD
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
signal is held low until V
is over the minimum
DD
7.4.5 Internal Watchdog RESET
level specified for the selected f
frequency.
OSC
(see “OPERATING CONDITIONS” on page 154)
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
A proper reset signal for a slow rising V supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 17. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
SHORT EXT.
RESET
LONG EXT.
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
t
t
w(RSTL)out
h(RSTL)in
w(RSTL)out
t
w(RSTL)out
t
h(RSTL)in
DELAY
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
32/191
ST72340, ST72344, ST72345
7.5 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
The LVD is an optional function which can be se-
lected by option byte.
Note: LVD Threshold Configuration
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Section 12.2.1 on page 149 for further de-
tails.
The voltage threshold can be configured by option
byte to be low, medium or high. The configuration
should be chosen depending on the f
and V
OSC
DD
parameters in the application. When correctly con-
figured, the LVD ensures safe power-on and pow-
er-off conditions for the microcontroller without us-
ing any external components.
7.5.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the V supply voltage is
DD
below a V reference value. This means that it
IT-
To determine which LVD thresholds to use:
secures the power-up as well as the power-down
keeping the ST7 in reset.
– Define the minimum operating voltage for the ap-
plication V
APP(min)
The V reference value for a voltage drop is lower
IT-
– Refer to the Electrical Characteristics section to
get the minimum operating voltage for the MCU
than the V reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
at the application frequency V
.
DD(min)
– Select the LVD threshold that ensures that the
internal RESET is released at V and ac-
The LVD Reset circuitry generates a reset when
DD
APP(min)
V
is below:
tivated at V
DD(MCUmin)
– V when V is rising
IT+
DD
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
– V when V is falling
IT-
DD
The LVD function is illustrated in Figure 18.
Figure 18. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+(LVD)
IT-((LVD)
RESET
33/191
ST72340, ST72344, ST72345
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.5.2 Auxiliary Voltage Detector (AVD)
old.
In the case of a drop in voltage below V
, the
The AVD is used to provide the application with an
early warning of a drop in voltage. If enabled, an
interrupt can be generated allowing software to
shut down safely before the LVD resets the micro-
controller. See Figure 19.
The AVD function is active only if the LVD is ena-
bled through the option byte (see Section 15.1 on
page 181). The activation level of the AVD is fixed
at around 0.5 mV above the selected LVD thresh-
IT-(PVD)
AVDF flag is set and an interrupt request is issued.
If V rises above the V
threshold voltage
DD
IT+(AVD)
the AVDF bit is cleared automatically by hardware.
No interrupt is generated, and therefore software
should poll the AVDF bit to detect when the volt-
age has risen, and resume normal processing.
Figure 19. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hys
V
IT+(AVD)
V
IT-(AVD)
V
IT-(LVD)
1
0
AVDF bit
0
RESET VALUE
1
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT PROCESS
LVD RESET
34/191
ST72340, ST72344, ST72345
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.5.3 Low Power Modes
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Mode
Description
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
WAIT
HALT
The SICSR register is frozen.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
7.5.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding AVDIE Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
0: PLL not locked
1: PLL locked
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bits 2:1 = Reserved, must be kept cleared.
Bit
Wait
AVD event
AVDF AVDIE
Yes
No
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
7.5.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS
REGISTER (SICSR)
Read/Write
Reset Value: 000x 000x (xxh)
Combined with the LVDRF flag information, the
flag description is given by the following table.
7
0
0
RESET Sources
LVDRF WDGRF
PDVD
IE
AVD LVD LOC
RF KED
WDG
RF
0
0
External RESET pin
Watchdog
0
0
1
0
1
F
LVD
X
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
goes from 0 to 1. The pending interrupt information
is automatically cleared when software enters the
AVD interrupt routine.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
0: PDVD interrupt disabled
1: PDVD interrupt enabled
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit goes from 0 to 1. Refer
to Figure 19 and to Section 7.5.2 for additional de-
tails.
0: V over V
threshold
threshold
IT-(AVD)
DD
IT+(AVD)
1: V under V
DD
35/191
ST72340, ST72344, ST72345
8 INTERRUPTS
8.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The ST7 enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
Table 6. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
8.2 MASKING AND PROCESSING FLOW
0
1
Level 2
0
0
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 20
Level 3 (= interrupt disable)
High
1
1
Figure 20. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TRAP
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
36/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
■ TRAP (Non Maskable Software Interrupt)
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 20.
Figure 21 describes this decision process.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
Figure 21. Priority Decision Process
PENDING
INTERRUPTS
See the RESET chapter for more details.
Maskable Sources
Different
Same
SOFTWARE
PRIORITY
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode. External interrupt sensitiv-
ity is software selectable through the External In-
terrupt Control register (EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Notes:
1. The hardware priority is exclusive while the soft-
ware one is not. This allows the previous process
to succeed with only one interrupt.
2. TLI, RESET and TRAP can be considered as
having the highest software priority in the decision
process.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table. A peripheral inter-
rupt occurs when a specific flag is set in the pe-
ripheral status registers and if the corresponding
enable bit is set in the peripheral control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 20). After stacking the PC, X, A and CC
37/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
8.3 INTERRUPTS AND LOW POWER MODES
8.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 21.
The following Figure 22 and Figure 23 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 23. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
SOFTWARE
PRIORITY
I1
I0
LEVEL
TRAP
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 23. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TRAP
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
38/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
8.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INTERRUPT BITS
Read/Write
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Reset Value: 111x 1010 (xAh)
Read/Write (bit 7:4 of ISPR3 are read only)
7
0
Reset Value: 1111 1111 (FFh)
7
0
1
1
I1
H
I0
N
Z
C
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-
ware priority.
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
Interrupt Software Priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
0
1
Level 2
0
0
These four registers contain the interrupt software
priority of each interrupt vector.
Level 3 (= interrupt disable*)
High
1
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondence is shown in the following table.
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
*Note: TRAP and RESET events can interrupt a
level 3 program.
FFE1h-FFE0h
I1_13 and I0_13 bits
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, and TRAP vectors have no software
priorities. When one is serviced, the I1 and I0 bits
of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
39/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
New Description
Entering Halt mode
Function/Example
I1
H
I0
N
Z
C
HALT
IRET
JRM
1
0
Interrupt routine return
Jump if I1:0=11 (level 3)
Jump if I1:0<>11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRNM
POP CC
RIM
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
Table 8. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
1
RESET
TRAP/ICD
AWU
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
N/A
Software or ICD Interrupt
0
1
Auto Wake Up Interrupt
AWUCSR
MCCSR
N/A
yes
yes
yes
yes
yes
yes
no
MCC/RTC
ei0
RTC Time base interrupt
2
External Interrupt Port PA3, PE1
External Interrupt Port PF2:0
External Interrupt Port PB3:0
External Interrupt Port PB4
I2C3SNS Address 3 Interrupt
I2C3SNS Address 1 & 2 Interrupt
SPI Peripheral Interrupts
3
ei1
N/A
4
ei2
N/A
5
ei3
N/A
6
I2C3SNS
I2C3SNS
SPI
I2C3SSR
7
no
2
8
SPISR
TASR
yes
9
TIMER A
TIMER B
SCI
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupt
no
no
no
no
no
10
11
12
13
TBSR
SCISR
SICSR
I2CSRx
AVD
Auxiliary Voltage Detector Interrupt
Lowest
Priority
2
2
I C
I C Peripheral Interrupt
Notes:
1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC interrupt source which exits from
ACTIVE-HALT mode only and AWU interrupt which exits from AWUFH mode only.
2. Exit from HALT possible when SPI is in slave mode.
40/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
8.6 EXTERNAL INTERRUPTS
8.6.1 I/O Port Interrupt Sensitivity
■ Falling edge and low level
■ Rising edge and high level (only for ei0 and ei2)
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 24). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
■ Falling and rising edge
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0], IPA or IPB bits of the
EICR.
Figure 24. External Interrupt Control bits
EICR
IS20 IS21
PORT A3, E1 INTERRUPTS
PAOR.3
PADDR.3
PA3
PE1
ei0 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PA3
IPA BIT
EICR
PORT F [2:0] INTERRUPTS
IS20
IS21
PFOR.2
PFDDR.2
SENSITIVITY
CONTROL
PF2
PF1
PF0
ei1 INTERRUPT SOURCE
PF2
EICR
PORT B [3:0] INTERRUPTS
IS10
IS11
PBOR.3
PBDDR.3
SENSITIVITY
CONTROL
PB3
PB2
PB1
PB0
PB3
ei2 INTERRUPT SOURCE
IPB BIT
EICR
PORT B4 INTERRUPT
IS10
IS11
PBOR.4
PBDDR.4
ei3 INTERRUPT SOURCE
SENSITIVITY
CONTROL
PB4
PB4
41/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
8.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)
Read/Write
Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:
Reset Value: 0000 0000 (00h)
7
0
0
IS11 IS10 IPB IS21 IS20 IPA
0
- ei0 (port A3, port E1)
Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
- ei2 (port B3..0)
External Interrupt Sensitivity
IS21 IS20
IPA bit =0
IPA bit =1
Falling edge &
low level
Rising edge
& high level
0
0
External Interrupt Sensitivity
IS11 IS10
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
IPB bit =0
IPB bit =1
Falling edge &
low level
Rising edge
& high level
0
0
Rising and falling edge
0
1
1
1
0
1
Rising edge only
Falling edge only
Falling edge only
Rising edge only
- ei1 (port F2..0)
Rising and falling edge
IS21 IS20
External Interrupt Sensitivity
- ei3 (port B4)
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
IS11 IS10
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
Falling edge only
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Rising and falling edge
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 2 = IPA Interrupt polarity for ports A3 and E1
This bit is used to invert the sensitivity of the port
A3 and E1 external interrupts. It can be set and
cleared by software only when I1 and I0 of the CC
register are both set to 1 (level 3).
Bit 5 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It can be set and cleared
by software only when I1 and I0 of the CC register
are both set to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
0: No sensitivity inversion
1: Sensitivity inversion
Bits 1:0 = Reserved, must always be kept cleared.
42/191
ST72340, ST72344, ST72345
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
ei0
MCC + SI
AWU
ei2
0024h
0025h
0026h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
I1_0
1
I0_0
1
ISPR0
Reset Value
I2C3SNS
I2C3SNS
ei3
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
SCI
TIMER B
TIMER A
SPI
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
I2C
AVD
0027h
0028h
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR
Reset Value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
0
0
43/191
ST72340, ST72344, ST72345
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 25):
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
SLOW mode is controlled by three bits in the
MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
■ Auto Wake up From Halt (AWUFH)
■ Halt
the internal slow frequency (f
).
CPU
In this mode, the master clock frequency (f
)
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
OSC2
can be divided by 2, 4, 8 or 16. The CPU and pe-
ripherals are clocked at this lower frequency
(f
).
CPU
Note: SLOW-WAIT mode is activated by entering
WAIT mode while the device is in SLOW mode.
(f
).
OSC2
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 26. SLOW Mode Clock Transitions
f
/2
f
/4
f
OSC2
OSC2
OSC2
f
CPU
Figure 25. Power Saving Mode Transitions
f
OSC2
High
RUN
00
01
CP1:0
SMS
NORMAL RUN MODE
REQUEST
SLOW
WAIT
NEW SLOW
FREQUENCY
REQUEST
SLOW WAIT
ACTIVE HALT
AUTO WAKE UP FROM HALT
HALT
Low
POWER CONSUMPTION
44/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
9.3 WAIT MODE
Figure 27. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
10
WFI INSTRUCTION
I[1:0] BITS
All peripherals remain active. During WAIT mode,
the I[1:0] bits of the CC register are forced to ‘10’,
to enable all interrupts. All other registers and
memory remain unchanged. The MCU remains in
WAIT mode until an interrupt or RESET occurs,
whereupon the Program Counter branches to the
starting address of the interrupt or Reset service
routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
10
Refer to Figure 27.
I[1:0] BITS
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
45/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
Figure 29. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 11.2 on page 65 for more de-
tails on the MCCSR register) and when the
AWUEN bit in the AWUCSR register is cleared.
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=0)
WATCHDOG
ENABLE
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 8, “Interrupt
Mapping,” on page 40) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 29).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
CPU
OFF
OFF
10
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 11.1 on page 58 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
Figure 28. HALT Timing Overview
FETCH RESET VECTOR
OR SERVICE INTERRUPT
256 OR 4096 CPU
CYCLE DELAY
Notes:
RUN
HALT
RUN
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 8, “Interrupt Mapping,” on page 40 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
46/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
Halt Mode Recommendations
9.5 ACTIVE-HALT MODE
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when MCC/RTC interrupt enable flag
(OIE bit in MCCSR register) is set and when the
AWUEN bit in the AWUCSR register is cleared
(See “Register Description” on page 51.)
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
HALT mode
ACTIVE-HALT mode
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
0
1
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
The MCU can exit ACTIVE-HALT mode on recep-
tion of the RTC interrupt and some specific inter-
rupts (see Table 8, “Interrupt Mapping,” on page
40) or a RESET. When exiting ACTIVE-HALT
mode by means of a RESET a 4096 or 256 CPU
cycle delay occurs (depending on the option byte).
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 31).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as active halt is enabled, executing
a HALT instruction while the Watchdog is active
does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
47/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
Figure 30. ACTIVE-HALT Timing Overview
Notes:
1. This delay occurs only if the MCU exits
ACTIVE
HALT
256 OR 4096 CYCLE
DELAY (AFTER RESET)
ACTIVE-HALT mode by means of a RESET.
RUN
RUN
2. Peripheral clocked with an external clock
source can still be active.
RESET
OR
INTERRUPT
3. Only the RTC interrupt and some specific inter-
rupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 40 for
more details.
HALT
INSTRUCTION
(Active Halt enabled)
FETCH
VECTOR
Figure 31. ACTIVE-HALT Mode Flow-chart
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
OFF
10
HALT INSTRUCTION
(MCCSR.OIE=1)
(AWUCSR.AWUEN=0)
2)
I[1:0] BITS
N
RESET
N
Y
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
Y
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
48/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
9.6 AUTO WAKE UP FROM HALT MODE
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of an internal RC
oscillator for wake-up. Compared to ACTIVE-
HALT mode, AWUFH has lower power consump-
tion because the main clock is not kept running,
but there is no accurate realtime clock available.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency f
and then
AWU_RC
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects in-
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set and the OIE bit in the MCCSR register is
cleared (see Section 11.2 on page 65 for more de-
tails).
ternally f
to the ICAP2 input of the 16-bit
AWU_RC
timer A, allowing the f
to be measured us-
AWU_RC
ing the main oscillator clock as a reference time-
base.
Figure 32. AWUFH Mode Block Diagram
Similarities with Halt mode
The following AWUFH mode behaviour is the
same as normal Halt mode:
AWU RC
oscillator
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 9.4 "HALT MODE" on page 46).
to Timer input capture
f
AWU_RC
– When entering AWUFH mode, the I[1:0] bits in
the CC register are forced to 10b to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
AWUFH
interrupt
AWUFH
/64
prescaler
divider
/1 .. 255
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(f
). Its frequency is divided by a fixed divid-
AWU_RC
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
Figure 33. AWUF Halt Timing Diagram
t
AWU
RUN MODE
HALT MODE
256 or 4096 t
RUN MODE
Clear
CPU
f
CPU
f
AWU_RC
by software
AWUFH interrupt
49/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
Figure 34. AWUFH Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 8, “Interrupt
Mapping,” on page 40 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS 2)
CPU
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
50/191
ST72340, ST72344, ST72345
POWER SAVING MODES (Cont’d)
9.6.0.1 Register Description
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write (except bit 2 read only)
Reset Value: 0000 0000 (00h)
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Reset Value: 1111 1111 (FFh)
7
0
7
0
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
AWU AWU AWU
EN
0
0
0
0
0
F
M
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
Bits 7:3 = Reserved.
AWUPR[7:0]
Dividing factor
Bit 2= AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR.
00h
01h
...
Forbidden (See note)
1
...
0: No AWU interrupt occurred
1: AWU interrupt occurred
FEh
FFh
254
255
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con-
nects internally its output to the ICAP2 input of 16-
bit timer A. This allows the timer to be used to
measure the AWU RC oscillator dispersion and
then compensate this dispersion by providing the
right value in the AWUPR register.
In AWU mode, the period that the MCU stays in
Halt Mode (t
in Figure 33) is defined by
AWU
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
AWU
f
AWURC
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
0: Measurement disabled
1: Measurement enabled
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
unchanged.
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
fined by the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
Table 10. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUCSR
Reset Value
AWUF
0
AWUM
0
AWUEN
0
002Eh
002Fh
0
0
0
0
0
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
1
1
1
1
1
1
1
1
51/191
ST72340, ST72344, ST72345
10 I/O PORTS
10.1 INTRODUCTION
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt sources, these
are first detected according to the sensitivity bits in
the EICR register and then logically ORed.
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
10.2 FUNCTIONAL DESCRIPTION
Each port has two main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
10.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: Bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 1
DR register value and output pin status:
DR
0
Push-pull
Open-drain
Vss
V
10.2.1 Input Modes
SS
1
V
Floating
DD
The input configuration is selected by clearing the
corresponding DDR register bit.
10.2.3 Alternate Functions
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.
Different input modes can be selected by software
through the OR register.
Notes:
When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.
When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.
3. Do not use read/modify/write instructions (BSET
or BRES) to modify the DR register as this might
corrupt the DR content for I/Os configured as input.
Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
52/191
ST72340, ST72344, ST72345
I/O PORTS (Cont’d)
Figure 35. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
x
Table 11. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Note: The diode to V is not implemented in the
DD
Off - implemented not activated
On - implemented and activated
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
SS
vice against positive stress.
53/191
ST72340, ST72344, ST72345
I/O PORTS (Cont’d)
Table 12. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
ANALOG INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
54/191
ST72340, ST72344, ST72345
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Figure 36. Interrupt I/O Port State Transitions
01
00
10
11
Analog alternate function
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
= DDR, OR
XX
10.4 LOW POWER MODES
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.5 INTERRUPTS
10.3 I/O PORT IMPLEMENTATION
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 2 on page 4. Other
transitions are potentially risky and should be
avoided, since they are likely to present unwanted
side-effects such as spurious interrupt generation.
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
55/191
ST72340, ST72344, ST72345
I/O PORTS (Cont’d)
10.5.1 I/O port implementation
The I/O port register configurations are summa-
rised as follows.
PA3, PE1, PB3, PF2 (without pull-up)
MODE
DDR
OR
0
Standard ports
floating input
0
0
1
1
floating interrupt input
open drain output
push-pull output
1
PA5:4, PC7:0, PD5:0,
PE0, PF7:6, 4
0
1
MODE
DDR
OR
0
floating input
pull-up input
0
0
1
1
1
True open drain ports
open drain output
push-pull output
0
PA7:6 , PD7:6
1
MODE
floating input
DDR
0
1
Interrupt ports
open drain (high sink ports)
PB4, PB2:0, PF1:0 (with pull-up)
MODE
floating input
DDR
OR
0
0
0
1
1
pull-up interrupt input
open drain output
push-pull output
1
0
1
Table 13. Port configuration
Input
floating
Output
Port
Pin name
PA7:6
OR = 0
OR = 1
OR = 0
OR = 1
true open-drain
Port A
PA5:4
PA3
floating
floating
floating
floating
floating
pull-up
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
floating interrupt
floating interrupt
pull-up interrupt
pull-up
PB3
Port B
Port C
Port D
PB4, PB2:0
PC7:0
PD7:6
PD5:0
PE1
floating
true open-drain
floating
floating
floating
floating
floating
floating
pull-up
floating interrupt
pull-up
open drain
open drain
open drain
open drain
open drain
open drain
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port E
Port F
PE0
PF7:6, 4
PF2
pull-up
floating interrupt
pull-up interrupt
PF1:0
CAUTION: In small packages, an internal pull-up is applied permanently to the non-bonded I/O pins. So they have to be
kept in input floating configuration to avoid unwanted consumption.
56/191
ST72340, ST72344, ST72345
I/O PORTS (Cont’d)
Table 14. I/O port register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
PEDDR
PEOR
PFDR
PFDDR
PFOR
57/191
ST72340, ST72344, ST72345
11 ON-CHIP PERIPHERALS
11.1 WINDOW WATCHDOG (WWDG)
11.1.1 Introduction
counter is reloaded outside the window (see
Figure 4)
The Window Watchdog is used to detect the oc-
currence of a software fault, usually generated by
external interference or by unforeseen logical con-
ditions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also gener-
ated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited win-
dow.
■ Hardware/Software
Watchdog
activation
(selectable by option byte)
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
11.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 f
cycles (approx.), and the length of the timeout pe-
riod can be programmed by the user in 64 incre-
ments.
OSC2
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
ically 30µs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
11.1.2 Main Features
■ Programmable free-running downcounter
■ Conditional reset
– Reset (if watchdog activated) when the down-
counter value becomes less than 40h
– Reset (if watchdog activated) if the down-
Figure 37. Watchdog Block Diagram
RESET
WATCHDOG WINDOW REGISTER (WDGWR)
-
W5
W0
W6
W1
W4
W2
W3
comparator
= 1 when
T6:0 > W6:0
CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
T5
T0
WDGA T6
T1
T4
T2
T3
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
f
OSC2
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
TB[1:0] bits
(MCCSR
Register)
MSB
LSB
0
6 5
11
58/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This operation
must occur only when the counter value is lower
than the window register value. The value to be
stored in the WDGCR register must be between
FFh and C0h (see Figure 2):
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see Figure 3).
The window register (WDGWR) contains the
high limit of the window: To prevent a reset, the
downcounter must be reloaded when its value is
lower than the window register value and greater
than 3Fh. Figure 4 describes the window watch-
dog process.
– Enabling the watchdog:
When Software Watchdog is selected (by option
byte), the watchdog is disabled after a reset. It is
enabled by setting the WDGA bit in the WDGCR
register, then it cannot be disabled again except
by a reset.
Note: The T6 bit can be used to generate a soft-
ware reset (the WDGA bit is set and the T6 bit is
cleared).
– Watchdog Reset on Halt option
When Hardware Watchdog is selected (by option
byte), the watchdog is always active and the
WDGA bit is not used.
If the watchdog is activated and the watchdog re-
set on halt option is selected, then the HALT in-
struction will generate a Reset.
– Controlling the downcounter:
11.1.4 Using Halt Mode with the WDG
This downcounter is free-running: It counts down
even if the watchdog is disabled. When the
watchdog is enabled, the T6 bit must be set to
prevent generating an immediate reset.
If Halt mode with Watchdog is enabled by option
byte (no watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see Figure 2. Ap-
proximate Timeout Duration). The timing varies
59/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG (Cont’d)
11.1.5 How to Program the Watchdog Timeout
more precision is needed, use the formulae in Fig-
ure 3.
Figure 2 shows the linear relationship between the
6-bit value to be loaded in the Watchdog Counter
(CNT) and the resulting timeout duration in milli-
seconds. This can be used for a quick calculation
without taking the timing variations into account. If
Caution: When writing to the WDGCR register, al-
ways write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 38. Approximate Timeout Duration
3F
38
30
28
20
18
10
08
00
1.5
18
34
50
65
82
98
114
128
Watchdog timeout (ms) @ 8 MHz f
OSC2
60/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG (Cont’d)
Figure 39. Exact Timeout Duration (t
and t
)
max
min
WHERE:
t
t
t
= (LSB + 128) x 64 x t
min0
OSC2
= 16384 x t
= 125ns if f
max0
OSC2
OSC2
= 8 MHz
OSC2
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
TB1 Bit
TB0 Bit
Selected MCCSR
Timebase
MSB
LSB
(MCCSR Reg.) (MCCSR Reg.)
0
0
1
1
0
1
0
1
2ms
4ms
4
8
59
53
35
54
10ms
25ms
20
49
To calculate the minimum Watchdog Timeout (t ):
min
MSB
4
IF
THEN
ELSE
-------------
CNT <
t
= tmin0 + 16384 × CNT × t
min
osc2
4CNT
----------------
4CNT
----------------
⎛
⎞
⎠
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
min
min0
⎝
MSB
MSB
To calculate the maximum Watchdog Timeout (t
):
max
MSB
4
IF
-------------
THEN
ELSE
CNT ≤
t
= tmax0 + 16384 × CNT × t
osc2
max
4CNT
----------------
4CNT
----------------
⎛
⎞
t
= t
+ 16384 × CNT –
+ (192 + LSB) × 64 ×
× t
osc2
max
max0
⎝
⎠
MSB
MSB
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
Min. Watchdog
Timeout (ms)
Max. Watchdog
Timeout (ms)
Value of T[5:0] Bits in
WDGCR Register (Hex.)
t
t
min
max
00
3F
1.496
128
2.048
128.552
61/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG (Cont’d)
Figure 40. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
time
(step = 16384/fOSC2
)
Refresh not allowed Refresh Window
T6 bit
Reset
11.1.6 Low Power Modes
Mode Description
SLOW No effect on Watchdog: The downcounter continues to decrement at normal speed.
WAIT No effect on Watchdog: The downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT bit
in Option
Byte
No Watchdog reset is generated. The MCU enters Halt mode. The Watch-
dog counter is decremented once and then stops counting and is no longer
able to generate a watchdog reset until the MCU receives an external inter-
rupt or a reset.
HALT
0
0
If an interrupt is received (refer to interrupt table mapping to see interrupts
which can occur in halt mode), the Watchdog restarts counting after 256 or
4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option byte. For applica-
tion recommendations see Section 0.1.8 below.
0
1
1
x
A reset is generated instead of entering halt mode.
No reset is generated. The MCU enters Active Halt mode. The Watchdog
counter is not decremented. It stop counting. When the MCU receives an
oscillator interrupt or external interrupt, the Watchdog restarts counting im-
mediately. When the MCU receives a reset the Watchdog restarts counting
after 256 or 4096 CPU clocks.
ACTIVE
HALT
11.1.7 Hardware Watchdog Option
11.1.8 Using Halt Mode with the WDG
(WDGHALT option)
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the WDGCR is not used. Refer to the Option Byte
description.
The following recommendation applies if Halt
mode is used when the watchdog is enabled.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
62/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG (Cont’d)
11.1.9 Interrupts
None.
WINDOW REGISTER (WDGWR)
Read/Write
Reset Value: 0111 1111 (7Fh)
11.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
7
0
-
W6
W5
W4
W3 W2 W1
W0
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
7
0
These bits contain the window value to be com-
pared to the downcounter.
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog
counter. It is decremented every 16384 f
cy-
OSC2
cles (approx.). A reset is produced when it rolls
over from 40h to 3Fh (T6 becomes cleared).
63/191
ST72340, ST72344, ST72345
WINDOW WATCHDOG(Cont’d)
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
2A
30
Reset Value
WDGWR
-
W6
1
W5
1
W4
1
W3
1
W2
1
W1
1
W0
1
Reset Value
0
64/191
ST72340, ST72344, ST72345
11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)
The Main Clock Controller consists of three differ-
ent functions:
external devices. It is controlled by the MCO bit in
the MCCSR register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.
■
a programmable CPU clock prescaler
■
a clock-out signal to supply external devices
11.2.3
Real Time Clock Timer (RTC)
■
a real time clock timer with interrupt capability
The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
Each function can be used independently and si-
multaneously.
11.2.1
Programmable CPU Clock Prescaler
ing directly on f
are available. The whole
OSC2
functionality is controlled by four bits of the MCC-
SR register: TB[1:0], OIE and OIF.
The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 9.2 "SLOW MODE" on page 44 for more
details).
When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 9.5
"ACTIVE-HALT MODE" on page 47 for more de-
tails.
The prescaler selects the f
main clock frequen-
CPU
cy and is controlled by three bits in the MCCSR
register: CP[1:0] and SMS.
11.2.4
Beeper
11.2.2
Clock-out Capability
The clock-out capability is an alternate function of
an I/O port pin that outputs a f clock to drive
The beep function is controlled by the MCCBCR
register. It can output three selectable frequencies
on the BEEP pin (I/O port alternate function).
OSC2
Figure 41.
Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0
MCCBCR
BEEP
MCO
BEEP SIGNAL
SELECTION
12-BIT MCC RTC
COUNTER
TO
DIV 64
WATCHDOG
TIMER
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
MCCSR
MCC/RTC INTERRUPT
fCPU
fOSC2
DIV 2, 4, 8, 16
1
0
CPU CLOCK
TO CPU AND
PERIPHERALS
65/191
ST72340, ST72344, ST72345
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
11.2.5
Low Power Modes
Bits 6:5 = CP[1:0] CPU clock prescaler
Mode
Description
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
WAIT
No effect on MCC/RTC counter (OIE bit is
f
in SLOW mode
CP1
CP0
ACTIVE- set), the registers are frozen.
CPU
HALT
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
f
f
f
/ 2
/ 4
0
0
1
1
0
1
0
1
OSC2
OSC2
OSC2
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit
from HALT” capability.
/ 8
HALT
f
/ 16
OSC2
11.2.6
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f = f
Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
OSC2
CPU
1: Slow mode. f
is given by CP1, CP0
CPU
See Section 9.2 "SLOW MODE" on page 44 and
Section 11.1 "WINDOW WATCHDOG (WWDG)"
on page 58 for more details.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
Bits 3:2 = TB[1:0] Time base control
Time base overflow
event
1)
OIF
OIE
Yes
No
These bits select the programmable divider time
base. They are set and cleared by software.
Note:
Time Base
Counter
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
TB1 TB0
Prescaler
f
=4MHz
f
=8MHz
OSC2
OSC2
16000
32000
80000
200000
4ms
2ms
4ms
0
0
1
1
0
1
0
1
8ms
20ms
50ms
11.2.7
10ms
25ms
Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read/Write
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Reset Value: 0000 0000 (00h
)
7
0
MCO CP1 CP0 SMS TB1 TB0 OIE OIF
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PF0 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
1: MCO alternate function enabled (f
port)
on I/O
CPU
mode
.
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
66/191
ST72340, ST72344, ST72345
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
MCC BEEP CONTROL REGISTER (MCCBCR)
Read/Write
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the MCCSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
Reset Value: 0000 0000 (00h)
7
0
0
0: Timeout not reached
1: Timeout reached
0
0
0
0
0
BC1 BC0
CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
BC1
BC0
Beep mode with f
=8MHz
OSC2
0
0
1
1
0
1
0
1
Off
~2-KHz
Output
Beep signal
~50% duty cycle
~1-KHz
~500-Hz
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Table 16. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
Reset Value
AVDIE
0
AVDF
0
LVDRF LOCKED
WDGRF
x
002Bh
002Ch
002Dh
0
x
0
0
0
MCCSR
Reset Value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
MCCBCR
Reset Value
BC1
0
BC0
0
0
0
0
0
0
0
67/191
ST72340, ST72344, ST72345
11.3 16-BIT TIMER
11.3.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
11.3.3 Functional Description
11.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some devices of the ST7 family have two on-chip
16-bit timers. They are completely independent,
and do not share any resources. They are syn-
chronized after a Device reset as long as the timer
clock frequencies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
the devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
11.3.2 Main Features
■ Programmableprescaler:fCPU dividedby2,4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 17 Clock
Control Bits. The value in the counter register re-
peats every 131 072, 262 144 or 524 288 CPU
clock cycles depending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 42.
*Note: Some timer pins may not available (not
bonded) in some devices. Refer to the device pin
out description.
68/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Figure 42. Timer Block Diagram
INTERNAL BUS
f
CPU
16-BIT TIMER PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See Device Interrupt Vector Table)
TIMER INTERRUPT
69/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (Device awakened by an interrupt)
or from the reset count (Device awakened by a
Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
11.3.3.2 External Clock
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
70/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Figure 43. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 44. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 45. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-
ning.
71/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
11.3.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 47).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 17
Clock Control Bits).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
72/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Figure 46. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 47. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The active edge is the rising edge.
Note: The time between an event on the ICAPi pin
and the appearance of the corresponding flag is
from 2 to 3 CPU clock cycles. This depends on the
moment when the ICAP event happens relative to
the timer clock.
73/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
11.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 17
Clock Control Bits)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Timing resolution is one count of the free running
Where:
counter: (f
).
CC[1:0]
CPU/
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
f
EXT
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 17
Clock Control Bits).
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
And select the following in the CR1 register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
74/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 49 on page
78). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 50 on page 78).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 48. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
75/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Figure 49. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 50. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
76/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
11.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 17
Clock Control Bits)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR2 register:
= Pulse period (in seconds)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
f
= External timer clock frequency (in hertz)
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 51).
– Select the timer clock CC[1:0] (see Table 17
Clock Control Bits).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
When a valid event occurs on the ICAP1 pin, the
counter value is loaded in the ICR1 register. The
counter is then initialized to FFFCh, the OLVL2 bit
is output on the OCMP1 pin and the ICF1 bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
77/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Figure 51. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 52. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
78/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
11.3.3.6 Pulse Width Modulation Mode
Clock Control Bits).
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
OCMP1 = OLVL2
When
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are loaded in
their respective shadow registers (double buffer)
only at the end of the PWM period (OC2) to avoid
spikes on the PWM output pin (OCMP1). The
shadow registers contain the reference values for
comparison in PWM “double buffering” mode.
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Note: There is a locking mechanism for transfer-
ring the OCiR value to the buffer. After a write to
the OCiHR register, transfer of the new compare
value to the buffer is inhibited until OCiLR is also
written.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
Unlike in Output Compare mode, the compare
function is always enabled in PWM mode.
CPU
- 5
OCiR Value =
PRESC
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
Procedure
f
To use pulse width modulation mode:
CPU
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 17 Clock
Control Bits)
PRESC
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
If the timer clock is an external clock the formula is:
OCiR = t f
-5
* EXT
Where:
t
3. Select the following in the CR1 register:
= Signal or pulse period (in seconds)
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
f
= External timer clock frequency (in hertz)
EXT
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 52)
Notes:
4. Select the following in the CR2 register:
1. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
2. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Select the timer clock (CC[1:0]) (see Table 17
79/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
3. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
4. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
11.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the Device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the Device is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
11.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 11.3.3.5 "One Pulse Mode" on page 79
See note 5 in Section 11.3.3.5 "One Pulse Mode" on page 79
See note 4 in Section 11.3.3.6 "Pulse Width Modulation Mode" on page 81
80/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
11.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
81/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 17. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
82/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only
Note: Reading or writing the ACLR register does
not clear TOF.
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
0
0
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: Timer prescaler, counter and outputs disabled
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Bits 1:0 = Reserved, must be kept cleared.
83/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
84/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
85/191
ST72340, ST72344, ST72345
16-BIT TIMER (Cont’d)
Table 18. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Timer A: 32 CR1
Timer B: 42 Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
1
Timer A: 31 CR2
Timer B: 41 Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer A: 33 CSR
Timer B: 43 Reset Value
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
-
x
-
x
Timer A: 34 IC1HR
Timer B: 44 Reset Value
MSB
x
LSB
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
0
1
0
x
x
Timer A: 35 IC1LR
Timer B: 45 Reset Value
MSB
x
LSB
x
Timer A: 36 OC1HR
Timer B: 46 Reset Value
MSB
1
LSB
0
Timer A: 37 OC1LR
Timer B: 47 Reset Value
MSB
0
LSB
0
Timer A: 3E OC2HR
Timer B: 4E Reset Value
MSB
1
LSB
0
Timer A: 3F OC2LR
Timer B: 4F Reset Value
MSB
0
LSB
0
Timer A: 38 CHR
Timer B: 48 Reset Value
MSB
1
LSB
1
Timer A: 39 CLR
Timer B: 49 Reset Value
MSB
1
LSB
0
Timer A: 3A ACHR
Timer B: 4A Reset Value
MSB
1
LSB
1
Timer A: 3B ACLR
Timer B: 4B Reset Value
MSB
1
LSB
0
Timer A: 3C IC2HR
Timer B: 4C Reset Value
MSB
x
LSB
x
Timer A: 3D IC2LR
Timer B: 4D Reset Value
MSB
x
LSB
x
86/191
ST72340, ST72344, ST72345
ON-CHIP PERIPHERALS (cont’d)
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 1 on page 3 shows the serial peripheral in-
terface (SPI) block diagram. There are three regis-
ters:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.4.2 Main Features
■ Full duplex synchronous transfers (on three
The SPI is connected to external devices through
four pins:
lines)
■ Simplex synchronous transfers (on two lines)
■ Master or slave operation
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ 6 master mode frequencies (f
/4 max.)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ f
/2 max. slave mode frequency (see note)
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
87/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (SPI) (cont’d)
Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
88/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.1 Functional Description
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 2.
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Four possible data/clock timing relationships may
be chosen (see Figure 5 on page 7) but master
and slave must be programmed with the same tim-
ing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
Figure 54. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
89/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 4).
There are two cases depending on the data/clock
timing relationship (see Figure 3):
If CPHA = 1 (data latched on second clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 0.1.5.3).
– SS internal must be held high continuously
Figure 55. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Figure 56. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
90/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
11.4.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
How to operate the SPI in master mode
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 5).
To operate the SPI in master mode, perform the
following steps in order:
Note: The slave must have the same CPOL
1. Write to the SPICR register:
and CPHA settings as the master.
– Select the clock frequency by configuring the
– Manage the SS pin as described in Section
0.1.3.2 and Figure 3. If CPHA = 1 SS must be
held low continuously. If CPHA = 0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
5 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
Important note: if the SPICSR register is not writ-
ten first, the SPICR register setting (MSTR bit)
may be not taken into account.
When data transfer is complete:
– The SPIF bit is set by hardware.
The transmit sequence begins when software
writes a byte in the SPIDR register.
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware.
1. An access to the SPICSR register while the
SPIF bit is set
2. A write or a read to the SPIDR register
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 0.1.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register
91/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.4 Clock Phase and Clock Polarity
Figure 5 shows an SPI transfer with the four com-
binations of the CPHA and CPOL bits. The dia-
gram may be interpreted as a master or slave tim-
ing diagram where the SCK pin, the MISO pin and
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 5).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if
CPOL = 0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge.
Figure 57. Data Clock Timing Diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit
Bit 6
Bit 6
Bit 5
Bit 5
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
92/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5 Error Flags
11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master de-
vice’s SS pin is pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted and
the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 0.1.3.2 Slave Select Man-
agement.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: A "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multimaster configuration the device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multimaster conflict and allows software to
handle this using an interrupt routine and either
perform a reset or return to an application default
state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 6).
Figure 58. Clearing the WCOL Bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF = 0
WCOL = 0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL = 0
93/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured
using a device as the master and four devices as
slaves (see Figure 7).
Multimaster System
A multimaster system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multimaster system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line,
the master allows only one active slave device
during a transmission.
Figure 59. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
Slave
Device
Device
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
94/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.6 Low Power Modes
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see Sec-
tion 0.1.3.2), make sure the master drives a low
level on the SS pin when the slave enters HALT
mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
HALT
11.4.7 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of
Transfer Event
SPIF
Yes
11.4.6.1 Using the SPI to wake up the device
from Halt mode
Master Mode
Fault Event
SPIE
Yes
MODF
OVR
No
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
95/191
ST72340, ST72344, ST72345
11.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
SPIE
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable
Table 19. SPI Master Mode SCK Frequency
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 1 SPI Master
Mode SCK Frequency.
Serial Clock
SPR2
SPR1
SPR0
f
f
/4
/8
1
CPU
CPU
0
1
0
1
0
0: Divider by 2 enabled
1: Divider by 2 disabled
0
1
0
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
1
f
/128
CPU
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see Section 0.1.5.1 Master Mode Fault
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
96/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
SPI CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
7
0
SPIF WCOL OVR MODF
-
SOD
SSM
SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only)
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
0.1.3.2 Slave Select Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE = 1 in the SPICR register. It is cleared by
a software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0: Slave selected
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 6).
0: No write collision occurred
1: A write collision has been detected
1: Slave deselected
SPI DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 0.1.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 0.1.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE = 1 in the SPICR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF = 1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 1).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
97/191
ST72340, ST72344, ST72345
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 20. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0021h
0022h
0023h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
98/191
ST72340, ST72344, ST72345
11.5 SCI SERIAL COMMUNICATION INTERFACE
11.5.1 Introduction
11.5.3 General Description
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The interface is externally connected to another
device by three pins (see Figure 1). Any SCI bidi-
rectional communication requires a minimum of
two pins: Receive Data In (RDI) and Transmit Data
Out (TDO):
– SCLK: Transmitter clock output. This pin outputs
the transmitter data clock for synchronous trans-
mission (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on
the last data bit). This can be used to control pe-
ripherals that have shift registers (e.g. LCD driv-
ers). The clock phase and polarity are software
programmable.
11.5.2 Main Features
■ Full duplex, asynchronous communications
■ NRZ standard format (Mark/Space)
■ Dual baud rate generator systems
■ Independently programmable transmit and
receive baud rates up to 500K baud
■ Programmable data word length (8 or 9 bits)
■ Receive buffer full, Transmit buffer empty and
End of Transmission flags
■ 2 receiver wake-up modes:
– Address bit (MSB)
– TDO: Transmit Data Output. When the transmit-
ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.
– Idle line
■ Mutingfunctionformultiprocessorconfigurations
■ Separate enable bits for Transmitter and
Receiver
■ 4 error detection flags:
– Overrun error
Through these pins, serial data is transmitted and
received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– Noise error
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
Thisinterfaceusestwotypesofbaudrategenerator:
– Frame error
– Parity error
■ 5 interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– A conventional type for commonly-used baud
rates,
– An extended type with a prescaler offering a very
wide range of baud rates even with non-standard
oscillator frequencies.
– Overrun error detected
■ Parity control:
– Transmits parity bit
– Checks parity of received data byte
■ Reduced power consumption mode
99/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
Figure 60. SCI Block Diagram
Write
Read
(DATA REGISTER) SCIDR
Receive Data Register (RDR)
Receive Shift Register
Transmit Data Register (TDR)
TDO
Transmit Shift Register
RDI
R8
T8 SCID
M
WAKE PCE PS PIE
SCICR1
WAKE
UP
TRANSMIT
CONTROL
RECEIVER
CLOCK
RECEIVER
CONTROL
UNIT
SCISR
SCICR2
TDRE TC RDRF IDLE OR NF FE PE
TIE TCIE RIE ILIE TE RE RWU SBK
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
CONTROL
f
CPU
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
100/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4 Functional Description
11.5.4.1 Serial Data Format
The block diagram of the Serial Control Interface,
is shown in Figure 1. It contains six dedicated reg-
isters:
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 2).
– 2 control registers (SCICR1 and SCICR2)
– A status register (SCISR)
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
– A baud rate register (SCIBRR)
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
– An extended prescaler receiver register
(SCIERPR)
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
– An extended prescaler transmitter register
(SCIETPR)
Refer to the register descriptions in Section 0.1.7
for the definitions of each bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 61. Word Length Programming
9-bit Word length (M bit is set)
Possible
Next Data Frame
Parity
Data Frame
Start
Bit
Next
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit8
Bit0
Bit
CLOCK
**
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
** LBCL bit controls last data clock pulse
8-bit Word length (M bit is reset)
Possible
Next Data Frame
Parity
Bit
Data Frame
Next
Start
Bit
Start
Bit
Stop
Bit
Bit2
Bit6
Bit1
Bit3
Bit4
Bit5
Bit7
Bit0
CLOCK
**
Start
Bit
Idle Frame
Start
Bit
Extra
’1’
Break Frame
** LBCL bit controls last data clock pulse
101/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.2 Transmitter
When a transmission is taking place, a write in-
struction to the SCIDR register stores the data in
the TDR register and which is copied in the shift
register at the end of the current transmission.
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the SCICR1
register.
When no transmission is taking place, a write in-
struction to the SCIDR register places the data di-
rectly in the shift register, the data transmission
starts, and the TDRE bit is immediately set.
When the transmit enable bit (TE) is set, the data
in the transmit shift register is output on the TDO
pin.
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the SCIDR register consists of a buffer (TDR) be-
tween the internal bus and the transmit shift regis-
ter (see Figure 2).
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Procedure
Note: The TDRE and TC bits are cleared by the
same software sequence.
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIETPR registers.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 2).
– Set the TE bit to send an idle frame as first trans-
mission.
– Access the SCISR register and write the data to
send in the SCIDR register (this sequence clears
the TDRE bit). Repeat this sequence for each
data to be transmitted.
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
– The data transfer is beginning.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set, that is, before writing the next byte in the
SCIDR.
– The next data can be written in the SCIDR regis-
ter without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
102/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.3 Receiver
– The RDR content is not lost.
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
– The shift register is overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 1).
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
Normal data bits are considered valid if three con-
secutive samples (8th, 9th, 10th) have the same
bit value, otherwise the NF flag is set. In the case
of start bit detection, the NF flag is set on the basis
of an algorithm combining both valid edge detec-
tion and three samples (8th, 9th, 10th). Therefore,
to prevent the NF flag getting set during start bit re-
ception, there should be a valid edge detection as
well as three valid samples.
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
When noise is detected in a frame:
– The NF flag is set at the rising edge of the RDRF
bit.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– Data is transferred from the Shift register to the
SCIDR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
Clearing the RDRF bit is performed by the following
software sequence done by:
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
1. An access to the SCISR register
2. A read to the SCIDR register.
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SCI han-
dles it as a framing error.
Idle Character
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
When an idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Overrun Error
See also Section 0.1.4.10 .
Framing Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can-
not be transferred from the shift register to the
RDR register until the RDRF bit is cleared.
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
When a overrun error occurs:
– The OR bit is set.
– A break is received.
103/191
ST72340, ST72344, ST72345
When the framing error is detected:
– the FE bit is set by hardware
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
– Data is transferred from the Shift register to the
SCIDR register.
The FE bit is reset by a SCISR register read oper-
ation followed by a SCIDR register read operation.
Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER
CLOCK
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
f
CPU
TRANSMITTER RATE
CONTROL
/PR
/16
SCIBRR
SCP1
SCT2
SCT1SCT0SCR2 SCR1SCR0
SCP0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
104/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.4 Conventional Baud Rate Generation
other than zero. The baud rates are calculated as
follows:
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows
f
f
CPU
CPU
Rx =
16 ERPR*(PR*RR)
Tx =
16 ETPR*(PR*TR)
:
*
*
f
f
CPU
CPU
Rx =
Tx =
with:
(16 PR) RR
(16 PR) TR
*
*
*
*
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
11.5.4.6 Receiver Muting and Wake-up Feature
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f is 8 MHz (normal mode) and if
The non-addressed devices may be placed in
sleep mode by means of the muting function.
CPU
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Setting the RWU bit by software puts the SCI in
sleep mode:
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
None of the reception status bits can be set.
All the receive interrupts are inhibited.
A muted receiver can be woken up in one of the
following two ways:
11.5.4.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
A receiver wakes-up by Idle Line detection when
the Receive line has recognized an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
The extended baud rate generator block diagram
is shown in Figure 3.
A receiver wakes-up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
The output clock rate sent to the transmitter or to
the receiver is the output from the 16 divider divid-
ed by a factor ranging from 1 to 255 set in the SCI-
ERPR or the SCIETPR register.
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
105/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.7 Parity control
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
Parity control (generation of parity bit in transmis-
sion and parity checking in reception) can be ena-
bled by setting the PCE bit in the SCICR1 register.
Depending on the frame length defined by the M
bit, the possible SCI frame formats are as listed in
Table 1.
11.5.4.8 SCI Clock Tolerance
Table 21. Frame Formats
During reception, each bit is sampled 16 times.
The majority of the 8th, 9th and 10th samples is
considered as the bit value. For a valid bit detec-
tion, all the three samples should have the same
value otherwise the noise flag (NF) is set. For ex-
ample: if the 8th, 9th and 10th samples are 0, 1
and 1 respectively, then the bit value is “1”, but the
Noise Flag bit is set because the three samples
values are not the same.
M bit
PCE bit
SCI frame
0
1
0
1
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
0
1
Legend:
SB: Start Bit
STB: Stop Bit
PB: Parity Bit
Consequently, the bit length must be long enough
so that the 8th, 9th and 10th samples have the de-
sired bit value. This means the clock frequency
should not vary more than 6/16 (37.5%) within one
bit. The sampling clock is resynchronized at each
start bit, so that when receiving 10 bits (one start
bit, 1 data byte, 1 stop bit), the clock deviation
must not exceed 3.75%.
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Note: The internal sampling clock of the microcon-
troller samples the pin value on every falling edge.
Therefore, the internal sampling clock and the time
the application expects the sampling to take place
may be out of sync. For example: If the baud rate
is 15.625 kbaud (bit length is 64µs), then the 8th,
9th and 10th samples will be at 28µs, 32µs and
36µs respectively (the first sample starting ideally
at 0µs). But if the falling edge of the internal clock
occurs just before the pin value changes, the sam-
ples would then be out of sync by ~4us. This
means the entire bit length must be at least 40µs
(36µs for the 10th sample + 4µs for synchroniza-
tion with the internal sampling clock).
Example: data = 00110101; 4 bits set => parity bit
is 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
106/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.9 Clock Deviation Causes
11.5.4.10 Noise Error Causes
The causes which contribute to the total deviation
are:
See also description of Noise error in Section
0.1.4.3 .
– D
: Deviation due to transmitter error (Local
Start bit
TRA
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
– D
: Error due to the baud rate quantiza-
QUANT
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the three con-
secutive samples before the falling edge occurs
are detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
tion of the receiver.
– D
: Deviation of the local oscillator of the
REC
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
: Deviation due to the transmission line
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
TCL
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
D
+ D
+ D
+ D
< 3.75%
TCL
TRA
QUANT
REC
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and 10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 63. Bit Sampling in Reception Mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
6/16
7/16
7/16
One bit time
107/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.5 Low Power Modes
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
Mode
Description
No effect on SCI.
Bit
Wait
Halt
TransmitDataRegister
Empty
TDRE
TC
TIE
WAIT
SCI interrupts cause the device to exit from
Wait mode.
Transmission Com-
plete
TCIE
RIE
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/re-
ceiving until Halt mode is exited.
Received Data Ready
to be Read
RDRF
OR
Yes
No
Overrun Error Detect-
ed
11.5.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
Idle Line Detected
Parity Error
IDLE
PE
ILIE
PIE
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
108/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.7 Register Description
Note: The IDLE bit is not set again until the RDRF
bit has been set itself (that is, a new idle line oc-
curs).
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 3 = OR Overrun error.
7
0
This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF = 1.
An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
TDRE
TC
RDRF IDLE
OR
NF
FE
PE
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE bit = 1
in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a write to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register con-
tent is not lost but the shift register is overwritten.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 2 = NF Noise flag.
Note: Data is not transferred to the shift register
This bit is set by hardware when noise is detected
on a received frame. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No noise is detected
until the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a
frame containing Data is complete. An interrupt is
generated if TCIE = 1 in the SCICR2 register. It is
cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR
register).
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
0: Transmission is not complete
1: Transmission is complete
Bit 1 = FE Framing error.
This bit is set by hardware when a desynchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate an interrupt as it
appears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it is transferred and only the OR bit
is set.
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error oc-
curs in receiver mode. It is cleared by a software
sequence (a read to the status register followed by
an access to the SCIDR data register). An inter-
rupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
0: No Idle Line is detected
1: Idle Line is detected
1: Parity error
109/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
CONTROL REGISTER 1 (SCICR1)
Read/Write
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
Reset Value: x000 0000 (x0h)
7
0
1: Address Mark
R8
T8
SCID
M
WAKE PCE
PS
PIE
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (gener-
ation and detection). When the parity control is en-
abled, the computed parity is inserted at the MSB
position (9th bit if M = 1; 8th bit if M = 0) and parity
is checked on the received data. This bit is set and
cleared by software. Once it is set, PCE is active
after the current byte (in reception and in transmis-
sion).
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received
word when M = 1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmit-
ted word when M = 1.
0: Parity control disabled
1: Parity control enabled
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs
are stopped and the end of the current byte trans-
fer in order to reduce power consumption.This bit
is set and cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the
parity generation/detection is enabled (PCE bit
set). It is set and cleared by software. The parity is
selected after the current byte.
0: Even parity
1: Odd parity
Bit 4 = M Word length.
This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hard-
ware parity control when a parity error is detected
(PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
Note: The M bit must not be modified during a data
transfer (both transmission and reception).
1: Parity error interrupt enabled
110/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
Read/Write
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
Reset Value: 0000 0000 (00h)
0: Receiver is disabled
7
0
1: Receiver is enabled and begins searching for a
start bit
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
Bit 1 = RWU Receiver wake-up.
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE = 1 in the SCISR register
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1
in the SCISR register
Notes:
– Before selecting Mute mode (by setting the RWU
bit) the SCI must first receive a data byte, other-
wise it cannot function in Mute mode with wake-
up by Idle line detection.
– In Address Mark Detection Wake-Up configura-
tion (WAKE bit = 1) the RWU bit cannot be mod-
ified by software while the RDRF bit is set.
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1
or RDRF = 1 in the SCISR register
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
IDLE = 1 in the SCISR register.
Note: If the SBK bit is set to “1” and then to “0”, the
transmitter sends a BREAK word at the end of the
current word.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
– During transmission, a “0” pulse on the TE bit
(“0” followed by “1”) sends a preamble (idle line)
after the current word.
– When TE is set there is a 1 bit-time delay before
the transmission starts.
111/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
TR dividing factor
SCT2
SCT1
SCT0
1
2
0
1
0
1
0
1
0
1
0
7
0
0
4
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1
0
1
8
16
32
64
128
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
1
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1).
Note: This TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the receive rate clock in conven-
tional Baud Rate Generator mode.
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
RR dividing factor
SCR2
SCR1
SCR0
1
2
0
1
0
1
0
1
0
1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
0
0
4
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
1
0
1
8
16
32
64
128
PR Prescaling factor
SCP1
SCP0
1
1
3
0
1
0
1
0
4
1
Note: This RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.
13
112/191
ST72340, ST72344, ST72345
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
7
0
7
0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR
ETPR ETPR ETPR ETPR ETPR ETPR ETPR ETPR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIERPR register (in the range 1 to 255).
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure 3) is divided by the binary factor set in the
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
The extended baud rate generator is not active af-
ter a reset.
Table 22. Baud Rate Selection
Conditions
Baud
Rate
Symbol
Parameter
Standard
Unit
Accuracy vs.
Standard
f
Prescaler
CPU
Conventional Mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR =13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
300
~300.48
1200 ~1201.92
2400 ~2403.84
4800 ~4807.69
9600 ~9615.38
10400 ~10416.67
19200 ~19230.77
38400 ~38461.54
~0.16%
~0.79%
f
Communication
frequency
Tx
8 MHz
Hz
f
Rx
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
14400 ~14285.71
113/191
ST72340, ST72344, ST72345
SERIAL COMMUNICATION INTERFACE (Cont’d)
Table 23. SCI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SCISR
Reset Value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0050h
0051h
0052h
0053h
0054h
0056h
0057h
SCIDR
Reset Value
MSB
x
LSB
x
x
x
x
x
x
x
SCIBRR
Reset Value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
SCICR1
Reset Value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
SCICR2
Reset Value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
SCIERPR
Reset Value
MSB
0
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
SCIPETPR
Reset Value
MSB
0
LSB
0
114/191
ST72340, ST72344, ST72345
2
11.6 I C BUS INTERFACE (I2C)
11.6.1 Introduction
handshake. The interrupts are enabled or disabled
2
2
by software. The interface is connected to the I C
The I C Bus Interface serves as an interface be-
2
bus by a data pin (SDAI) and by a clock pin (SCLI).
tween the microcontroller and the serial I C bus. It
2
It can be connected both with a standard I C bus
provides both multimaster and slave functions,
2
2
and a Fast I C bus. This selection is made by soft-
and controls all I C bus-specific sequencing, pro-
2
ware.
tocol, arbitration and timing. It supports fast I C
mode (400kHz).
Mode Selection
11.6.2 Main Features
■ Parallel-bus/I C protocol converter
The interface can operate in the four following
modes:
2
– Slave transmitter/receiver
■ Multi-master capability
– Master transmitter/receiver
By default, it operates in slave mode.
■ 7-bit/10-bit Addressing
■ Transmitter/Receiver flag
■ End-of-byte transmission flag
■ Transfer problem detection
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP generation, allowing then Multi-Master ca-
pability.
2
I C Master Features:
■ Clock generation
2
■ I C bus busy flag
Communication Flow
■ Arbitration Lost Flag
In Master mode, it initiates a data transfer and
generates the clock signal. A serial data transfer
always begins with a start condition and ends with
a stop condition. Both start and stop conditions are
generated in master mode by software.
■ End of byte transmission flag
■ Transmitter/Receiver Flag
■ Start bit detection flag
■ Start and Stop generation
In Slave mode, the interface is capable of recog-
nising its own address (7 or 10-bit), and the Gen-
eral Call address. The General Call address de-
tection may be enabled or disabled by software.
2
I C Slave Features:
■ Stop bit detection
2
■ I C bus busy flag
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte(s) following the start con-
dition contain the address (one in 7-bit mode, two
in 10-bit mode). The address is always transmitted
in Master mode.
■ Detection of misplaced start or stop condition
■ Programmable I C Address detection
■ Transfer problem detection
■ End-of-byte transmission flag
■ Transmitter/Receiver flag
11.6.3 General Description
2
A 9th clock pulse follows the 8 clock cycles of a
byte transfer, during which the receiver must send
an acknowledge bit to the transmitter. Refer to Fig-
ure 64.
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
2
Figure 64. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
115/191
ST72340, ST72344, ST72345
2
I C BUS INTERFACE (Cont’d)
Acknowledge may be enabled and disabled by
software.
The SCL frequency (F ) is controlled by a pro-
scl
grammable clock divider which depends on the
2
2
I C bus mode.
The I C interface address and/or general call ad-
2
dress can be selected by software.
When the I C cell is enabled, the SDA and SCL
2
ports must be configured as floating inputs. In this
case, the value of the external pull-up resistor
used depends on the application.
The speed of the I C interface may be selected
2
between Standard (up to 100KHz) and Fast I C
(up to 400KHz).
2
When the I C cell is disabled, the SDA and SCL
ports revert to being standard I/O port pins.
SDA/SCL Line Control
Transmitter mode: the interface holds the clock
line low before transmission to wait for the micro-
controller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
2
Figure 65. I C Interface Block Diagram
DATA REGISTER (DR)
DATA CONTROL
SDA or SDAI
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
OWN ADDRESS REGISTER 2 (OAR2)
CLOCK CONTROL
SCL or SCLI
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR)
STATUS REGISTER 1 (SR1)
STATUS REGISTER 2 (SR2)
CONTROL LOGIC
INTERRUPT
116/191
ST72340, ST72344, ST72345
2
I C BUS INTERFACE (Cont’d)
11.6.4 Functional Description
– EVF and BTF bits are set with an interrupt if the
ITE bit is set.
Refer to the CR, SR1 and SR2 registers in Section
11.6.7. for the bit definitions.
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV2).
2
By default the I C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First the interface frequency must be configured
using the FRi bits in the OAR2 register.
Slave Transmitter
Following the address reception and after SR1
register has been read, the slave sends bytes from
the DR register to the SDA line via the internal shift
register.
11.6.4.1 Slave Mode
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
The slave waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 66 Transfer sequencing
EV3).
Note: In 10-bit addressing mode, the comparision
includes the header sequence (11110xx0) and the
two most significant bits of the address.
When the acknowledge pulse is received:
Header matched (10-bit mode only): the interface
generates an acknowledge pulse if the ACK bit is
set.
– The EVF and BTF bits are set by hardware with
an interrupt if the ITE bit is set.
Address not matched: the interface ignores it
Closing slave communication
and waits for another Start condition.
After the last data byte is transferred a Stop Con-
dition is generated by the master. The interface
detects this condition and sets:
Address matched: the interface generates in se-
quence:
– Acknowledge pulse if the ACK bit is set.
– EVF and STOPF bits with an interrupt if the ITE
bit is set.
– EVF and ADSL bits are set with an interrupt if the
ITE bit is set.
Then the interface waits for a read of the SR2 reg-
ister (see Figure 66 Transfer sequencing EV4).
Then the interface waits for a read of the SR1 reg-
ister, holding the SCL line low (see Figure 66
Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to deter-
mine from the least significant bit (Data Direction
Bit) if the slave must enter Receiver or Transmitter
mode.
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
the BERR bits are set with an interrupt if the ITE
bit is set.
If it is a Stop then the interface discards the data,
released the lines and waits for another Start
condition.
In 10-bit mode, after receiving the address se-
quence the slave is always in receive mode. It will
enter transmit mode on receiving a repeated Start
condition followed by the header sequence with
matching address bits and the least significant bit
set (11110xx1) .
If it is a Start then the interface discards the data
and waits for the next slave address on the bus.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set with an inter-
rupt if the ITE bit is set.
Slave Receiver
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
Following the address reception and after SR1
register has been read, the slave receives bytes
from the SDA line into the DR register via the inter-
nal shift register. After each byte the interface gen-
erates in sequence:
– Acknowledge pulse if the ACK bit is set
117/191
ST72340, ST72344, ST72345
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV9).
Then the second address byte is sent by the inter-
face.
Note: In both cases, SCL line is not held low; how-
ever, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to re-
lease both lines by software. The SCL line is not
held low while AF=1 but by other flags (SB or BTF)
that are set at the same time.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
How to release the SDA / SCL lines
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Set and subsequently clear the STOP bit while
BTF is set. The SDA/SCL lines are released after
the transfer of the current byte.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the CR register (for exam-
ple set PE bit), holding the SCL line low (see Fig-
ure 66 Transfer sequencing EV6).
SMBus Compatibility
2
ST7 I C is compatible with SMBus V1.1 protocol. It
supports all SMBus adressing modes, SMBus bus
protocols and CRC-8 packet error checking. Refer
Next the master must enter Receiver or Transmit-
ter mode.
2
to AN1713: SMBus Slave Driver For ST7 I C Pe-
ripheral.
Note: In 10-bit addressing mode, to switch the
master to Receiver mode, software must generate
a repeated Start condition and resend the header
sequence with the least significant bit set
(11110xx1).
11.6.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Master Receiver
Start condition
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR reg-
ister via the internal shift register. After each byte
the interface generates in sequence:
Setting the START bit while the BUSY bit is
cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condi-
tion.
Once the Start condition is sent:
– Acknowledge pulse if the ACK bit is set
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address, holding the SCL line low (see
Figure 66 Transfer sequencing EV5).
Then the interface waits for a read of the SR1 reg-
ister followed by a read of the DR register, holding
the SCL line low (see Figure 66 Transfer se-
quencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit
cleared).
Slave address transmission
Then the slave address is sent to the SDA line via
the internal shift register.
In 7-bit addressing mode, one address byte is
sent.
Note: In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
In 10-bit addressing mode, sending the first byte
including the header sequence causes the follow-
ing event:
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
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2
I C BUS INTERFACE (Cont’d)
Master Transmitter
sion.
Multimaster Mode
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is-
sue will arise if an external master generates an
2
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see Figure 66 Transfer sequencing
EV8).
unauthorized Start or Stop while the I C master
is on the first pulse pulse of a 9-bit transaction. It
is possible to work around this by polling the
2
BUSY bit during I C master mode transmission.
The resetting of the BUSY bit can then be han-
dled in a similar manner as the BERR flag being
set.
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
– ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
Note that BERR will not be set if an error is de-
tected during the first pulse of each 9-bit transac-
tion:
Single Master Mode
If a Start or Stop is issued during the first pulse of
a 9-bit transaction, the BERR flag will not be set
and transfer will continue however the BUSY flag
will be reset. To work around this, slave devices
should issue a NACK when they receive a mis-
placed Start or Stop. The reception of a NACK or
BUSY by the master in the middle of communica-
tion gives the possibility to reinitiate transmis-
Note: In all these cases, the SCL line is not held
low; however,the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary
to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or
BTF) that are set at the same time.
119/191
ST72340, ST72344, ST72345
2
I C BUS INTERFACE (Cont’d)
Figure 66. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
Data1
Data1
Data2
EV3
A
Data2
Data2
DataN
A
P
.....
EV1
EV2
A
EV2
A
EV2
NA
EV4
7-bit Slave transmitter:
S
Address
A
DataN
P
.....
.....
EV1 EV3
EV3
EV3-1
EV4
7-bit Master receiver:
S
Address
A
A
A
DataN NA
P
EV5
EV6
EV7
A
EV7
A
EV7
A
7-bit Master transmitter:
S
Address
A
Data1
Data2
DataN
P
.....
EV5
EV6 EV8
EV8
EV8
EV8
10-bit Slave receiver:
S
Header
A
Address
A
Data1
A
DataN
A
P
.....
EV1
EV2
EV2
EV4
10-bit Slave transmitter:
S
Header
A
Data1
A
A
DataN
....
.
A
P
r
EV1 EV3
EV6 EV8
EV3
EV3-1
EV4
10-bit Master transmitter
S
Header
A
Address
A
Data1
DataN
A
P
.....
EV5
EV9
EV8
A
EV8
A
10-bit Master receiver:
S
Header
A
Data1
DataN
P
r
.....
EV5
EV6
EV7
EV7
Legend: S=Start, S = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
r
EVx=Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
120/191
ST72340, ST72344, ST72345
2
I C BUS INTERFACE (Cont’d)
11.6.5 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
HALT
2
I C interrupts cause the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.6.6 Interrupts
Figure 67. Event Flags and Interrupt Generation
ADD10
ITE
BTF
ADSL
SB
INTERRUPT
EVF
AF
STOPF
ARLO
BERR
*
* EVF can also be set by EV6 or an error from the SR2 register.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
ADD10
BTF
No
No
No
No
No
No
No
No
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
ADSL
SB
ITE
AF
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
STOPF
ARLO
BERR
2
Note: The I C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
121/191
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2
I C BUS INTERFACE (Cont’d)
11.6.7 Register Description
– In slave mode:
2
0: No start generation
I C CONTROL REGISTER (CR)
1: Start generation when the bus is free
Read / Write
Reset Value: 0000 0000 (00h)
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
7
0
0
0
PE
ENGC START ACK STOP
ITE
0: No acknowledge returned
1: Acknowledge returned after an address byte or
a data byte is received
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. Note: This
bit is not cleared when the interface is disabled
(PE=0).
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– In master mode:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
2
– To enable the I C interface, write the CR register
TWICE with PE=1 as the first write only activates
– In slave mode:
0: No stop generation
the interface (only PE is set).
1: Release the SCL and SDA lines after the cur-
rent byte transfer (BTF=1). In this mode the
STOP bit has to be cleared by software.
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0). The 00h General Call address is ac-
knowledged (01h ignored).
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: General Call disabled
1: General Call enabled
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 67 for the relationship between the
events and the interrupt.
SCL is held low when the ADD10, SB, BTF or
ADSL flags or an EV6 event (See Figure 66) is de-
tected.
Note: In accordance with the I2C standard, when
GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the
master.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
122/191
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2
I C BUS INTERFACE (Cont’d)
2
I C STATUS REGISTER 1 (SR1)
tection of Stop condition (STOPF=1), loss of bus
arbitration (ARLO=1) or when the interface is disa-
bled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Read Only
Reset Value: 0000 0000 (00h)
7
0
EVF ADD10 TRA BUSY BTF ADSL M/SL
SB
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. The BUSY flag of the I2CSR1
register is cleared if a Bus Error occurs.
0: No communication on the bus
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event oc-
curs. It is cleared by software reading SR2 register
in case of error event or as described in Figure 66.
It is also cleared by hardware when the interface is
disabled (PE=0).
1: Communication ongoing on the bus
0: No event
1: One of the following events has occurred:
Bit 3 = BTF Byte transfer finished.
– BTF=1 (Byte received or transmitted)
This bit is set by hardware as soon as a byte is cor-
rectly received or transmitted with interrupt gener-
ation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR reg-
ister. It is also cleared by hardware when the inter-
face is disabled (PE=0).
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– SB=1 (Start condition generated in Master
mode)
– AF=1 (No acknowledge received after byte
transmission)
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. In
case an address byte is sent, this bit is set only
after the EV6 event (See Figure 66). BTF is
cleared by reading SR1 register followed by writ-
ing the next byte in DR register.
– STOPF=1 (Stop condition detected in Slave
mode)
– ARLO=1 (Arbitration lost in Master mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
– ADD10=1 (Master has sent header byte)
– Address byte successfully transmitted in Mas-
ter mode.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has
sent the first byte in 10-bit address mode. It is
cleared by software reading SR2 register followed
by a write in the DR register of the second address
byte. It is also cleared by hardware when the pe-
ripheral is disabled (PE=0).
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received
slave address matched with the OAR register con-
tent or a general call is recognized. An interrupt is
generated if ITE=1. It is cleared by software read-
ing SR1 register or by hardware when the inter-
face is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
The SCL line is held low while ADSL=1.
Bit 5 = TRA Transmitter/Receiver.
0: Address mismatched or not received
1: Received address matched
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after de-
123/191
ST72340, ST72344, ST72345
2
I C BUS INTERFACE (Cont’d)
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface
is in Master mode (writing START=1). It is cleared
by hardware after detecting a Stop condition on
the bus or a loss of arbitration (ARLO=1). It is also
cleared when the interface is disabled (PE=0).
0: Slave mode
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface los-
es the arbitration of the bus to another master. An
interrupt is generated if ITE=1. It is cleared by soft-
ware reading SR2 register or by hardware when
the interface is disabled (PE=0).
1: Master mode
After an ARLO event the interface switches back
automatically to Slave mode (M/SL=0).
Bit 0 = SB Start bit (Master mode).
The SCL line is not held low while ARLO=1.
This bit is set by hardware as soon as the Start
condition is generated (following
a
write
0: No arbitration lost detected
START=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register followed
by writing the address byte in DR register. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
1: Arbitration lost detected
Note:
– In a Multimaster environment, when the interface
is configured in Master Receive mode it does not
perform arbitration during the reception of the
Acknowledge Bit. Mishandling of the ARLO bit
from the I2CSR2 register may occur when a sec-
ond master simultaneously requests the same
0: No Start condition
1: Start condition generated
2
2
data from the same slave and the I C master
does not acknowledge the data. The ARLO bit is
then left at 0 instead of being set.
I C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. An inter-
rupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the in-
terface is disabled (PE=0).
0
0
AF STOPF ARLO BERR GCAL
Bit 7:5 = Reserved. Forced to 0 by hardware.
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note:
– If a Bus Error occurs, a Stop or a repeated Start
condition should be generated by the Master to
re-synchronize communication, get the transmis-
sion acknowledged and the bus released for fur-
ther communication
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by oth-
er flags (SB or BTF) that are set at the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call ad-
dress is detected on the bus while ENGC=1. It is
cleared by hardware detecting a Stop condition
(STOPF=1) or when the interface is disabled
(PE=0).
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition
is detected on the bus after an acknowledge (if
ACK=1). An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
0: No general call address detected on bus
1: general call address detected on bus
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
124/191
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2
I C BUS INTERFACE (Cont’d)
2
2
I C CLOCK CONTROL REGISTER (CCR)
I C DATA REGISTER (DR)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
7
0
FM/SM CC6
CC5
CC4
CC3
CC2
CC1
CC0
D7
D6
D5
D4
D3
D2
D1
D0
2
Bit 7 = FM/SM Fast/Standard I C mode.
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
2
0: Standard I C mode
2
1: Fast I C mode
– Transmitter mode: Byte transmission start auto-
matically when the software writes in the DR reg-
ister.
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
) de-
SCL
– Receiver mode: the first data byte is received au-
tomatically in the DR register using the least sig-
nificant bit of the address.
2
pending on the I C mode. They are not cleared
when the interface is disabled (PE=0).
Refer to the Electrical Characteristics section for
the table of values.
Then, the following data bytes are received one
by one after reading the DR register.
Note: The programmed F
SCL and SDA lines.
assumes no load on
SCL
125/191
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2
I C BUS INTERFACE (Cont’d)
2
2
I C OWN ADDRESS REGISTER (OAR1)
I C OWN ADDRESS REGISTER (OAR2)
Read / Write
Reset Value: 0000 0000 (00h)
Read / Write
Reset Value: 0100 0000 (40h)
7
0
7
0
0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
FR1
FR0
0
0
0
ADD9 ADD8
7-bit Addressing Mode
Bit 7:6 = FR[1:0] Frequency bits.
Bit 7:1 = ADD[7:1] Interface address.
These bits are set by software only when the inter-
face is disabled (PE=0). To configure the interface
2
These bits define the I C bus address of the inter-
2
face. They are not cleared when the interface is
disabled (PE=0).
to I C specified delays select the value corre-
sponding to the microcontroller frequency F
.
CPU
f
FR1
0
FR0
0
1
CPU
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges
either 0 or 1. It is not cleared when the interface is
disabled (PE=0).
< 6 MHz
6 to 8 MHz
0
Note: Address 01h is always ignored.
Bit 5:3 = Reserved
10-bit Addressing Mode
Bit 2:1 = ADD[9:8] Interface address.
2
These are the most significant bits of the I C bus
address of the interface (10-bit mode only). They
are not cleared when the interface is disabled
(PE=0).
Bit 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I C bus
address of the interface. They are not cleared
when the interface is disabled (PE=0).
2
Bit 0 = Reserved.
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I²C BUS INTERFACE (Cont’d)
2
Table 24. I C Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
I2CCR
Reset Value
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
0
0
I2CSR1
Reset Value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
I2CSR2
Reset Value
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
0
0
0
I2CCCR
Reset Value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
I2COAR1
Reset Value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
I2COAR2
Reset Value
FR1
0
FR0
1
ADD9
0
ADD8
0
0
0
0
0
0
0
0
I2CDR
Reset Value
MSB
0
LSB
0
0
0
0
127/191
ST72340, ST72344, ST72345
11.7 I2C TRIPLE SLAVE INTERFACE WITH DMA (I2C3S)
11.7.1 Introduction
■ Fast Mode (transfers 256 bytes at up to 400
2
kHz)
The I C3S interface provides three I2C slave func-
■ Transfer error detection and handling
tions, supporting both standard (up to 100kHz)
2
and fast I C mode (100 to 400 kHz). Special fea-
■ 3 interrupt flags per address for maximum
flexibility
tures are provided for:
2
2
■ Two interrupt request lines (one for Slaves 1
■ Full-speed emulation of standard I C E PROMs
and 2, the other for Slave 3)
■ Receiving commands to perform user-defined
2
■ Full emulation of standard I C EEPROMs:
operations such as IAP
– Supports 5 read/write commands and com-
bined format
11.7.2 Main Features
■ Three user configurable independent slave
2
– No I C clock stretching
addresses can be individually enabled
■ 2x 256 bytes and 1x 128 bytes buffers with fixed
– Programmable page size (8/16 bytes) or full
buffer
addresses in RAM
■ 7-bit Addressing
■ DMA transfer to/from I C bus and RAM
■ Standard (transfers 256 bytes at up to 100 kHz)
– Configurable write protection
2
■ Data integrity and byte-pair coherency when
2
reading 16-bit words from I C bus
2
Figure 68. I C3S Interface Block Diagram
I2C SLAVE ADDRESS 1
I2C SLAVE ADDRESS 2
I2C SLAVE ADDRESS 3
2
DATA E PROM
256 BYTES
RAM
SLAVE 1 BUFFER
256 BYTES
COMPARATOR
8-BIT
SHIFT REGISTER
SDA or SDAI
SLAVE 2 BUFFER
256 BYTES
SCL or SCLI
SLAVE 3 BUFFER
128 BYTES
DMA
SHADOW
REGISTER
CONTROL LOGIC
Slave 1 or 2 Interrupt
Slave 3 Interrupt
CPU
128/191
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2
I C3S INTERFACE (Cont’d)
11.7.3 General Description
slave addresses which are user programmable.
2
The three I C slave addresses can be individually
In addition to receiving and transmitting data,
I2C3S converts it from serial to parallel format and
vice versa. The interrupts are enabled or disabled
enabled/disabled by software.
Since the I2C3S interface always acts as a slave it
does not generate a clock. Data and addresses
are transferred as 8-bit bytes, MSB first. The first
byte following the start condition contains the
slave address. A 9th clock pulse follows the 8
clock cycles of a byte transfer, during which the re-
ceiver must send an acknowledge bit to the trans-
mitter.
2
by software. The I2C3S is connected to the I C
bus by a data pin (SDA) and by a clock pin (SCL).
2
It can be connected both with a standard I C bus
2
and a Fast I C bus. The interface operates only in
Slave mode as transmitter/receiver.
2
In order to fully emulate standard I C EEPROM
devices with highest transfer speed, the peripheral
2
prevents I C clock signal stretching and performs
data transfer between the shift register and the
RAM buffers using DMA.
11.7.3.2 SDA/SCL Line Control
When the I2C3S interface is enabled, the SDA and
SCL ports must be configured as floating inputs. In
this case, the value of the external pull-up resistor
used depends on the application.
11.7.3.1 Communication Flow
A serial data transfer normally begins with a start
condition and ends with a stop condition. Both
start and stop conditions are generated by an ex-
ternal master. Refer to Figure 64 for the standard
protocol. The I2C3S is not a master and is not ca-
pable of generating a start/stop condition on the
SDA line. The I2C3S is capable of recognising 3
When the I2C3S interface is disabled, the SDA
and SCL ports revert to being standard I/O port
pins.
2
Figure 69. I C BUS Protocol
SDA
MSB
ACK
SCL
1
2
8
9
START
STOP
CONDITION
CONDITION
VR02119B
129/191
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2
I C3S INTERFACE (Cont’d)
11.7.4 Functional Description
A DMA request is issued to the DMA controller on
reception of a byte or just before transmission of a
byte.
The three slave addresses 1, 2 and 3 can be used
2
as general purpose I C slaves. They also support
2
all features of standard I C EEPROMs like the ST
When a byte is written by DMA in RAM, the CPU is
stalled for max. 2 cycles. When several bytes are
transferred from the I2C bus to RAM, the DMA re-
leases between each byte and the CPU resumes
processing until the DMA writes the next byte.
M24Cxx family and are able to fully emulate them.
Slaves 1 and 2 are mapped on the same interrupt
vector. Slave 3 has a separate interrupt vector with
higher priority.
11.7.4.3 RAM Buffer Write Protection
The three slave addresses are defined by writing
the 7 MSBs of the address in the I2C3SSAR1,
I2C3SSAR2 and I2C3SSAR3 registers. The
slaves are enabled by setting the enable bits in the
same registers.
By setting the WP1/WP2 bits in the I2C3SCR2
register it is possible to protect the RAM buffer of
Slaves 1/2 respectively against write access from
the master.
Each slave has its own RAM buffer at a fixed loca-
tion in the ST7 RAM area.
If a write operation is attempted, the slave address
is acknowledged, the current address register is
overwritten, data is also acknowledged but it is not
written to the RAM. Both the current address and
byte count registers are incremented as in normal
operation.
– Slaves 1 and 2 have 256-byte buffers which can
2
be individually protected from I C master write
accesses.
– Slave 3 has a 128-byte RAM buffer without write
protection feature.
In case of write access to a write protected ad-
dress, no interrupt is generated and the BusyW bit
in the I2C3SCR2 register is not set.
All three slaves have individual read flags (RF)
and write flags (WF) with maskable interrupts.
2
Only write operations are disabled/enabled. Read
operations are not affected.
These flags are set when the I C master has com-
pleted a read or write operation.
2
11.7.4.4 Byte-pair coherency for I C Read
11.7.4.1 Paged operation
operations
2
To allow emulation of Standard I C EEPROM de-
2
Byte-pair coherency allows the I C master to read
vices, pages can be defined in the RAM buffer.
The pages are configured using the PL[1:0] bits in
the I2C3SCR1 register. 8/16-Byte page length has
to be selected depending on the EEPROM device
to emulate. The Full Page option is to be used
when no paging of the RAM buffer is required. The
configuration is common to the 3 slave addresses.
The Full Page configuration corresponds to 256
bytes for address 1 and 2 and to 128 bytes for ad-
dress 3.
a 16-bit word and ensures that it is not corrupted
by a simultaneous CPU update. Two mechanisms
are implemented, covering the two possible cases:
1. CPU updates a word in RAM after the first byte
has been transferred to the I2C shift register
from RAM. In this case, the first byte read from
RAM would be the MSB of the old word and
2nd byte would be the LSB of the new word.
To prevent this corruption, the I2C3S uses
DMA to systematically read a 2-byte word when
Paging affects the handling of rollover when write
operations are performed. In case the bottom of
the page is reached, the write continues from the
first address of the same page. Page length does
not affect read operations: rollover is done on the
whole RAM buffer whatever the configured page
length.
2
it receives a read command from the I C mas-
ter. The MSB of the word should be at address
2n. Using DMA, the MSB is moved from RAM
address 2n to the I2C shift register and the LSB
from RAM address 2n+1 moved to a shadow
register in the I2C3S peripheral. The CPU is
stalled for a maximum of 2 cycles during word
transfer.
The Byte count register is reset when it reaches
256 bytes, whatever the page length, for all slave
addresses, including slave 3.
In case only one byte is read, the unused con-
tent of the shadow register will be automatically
overwritten when a new read operation is per-
formed.
11.7.4.2 DMA
2
The I C slaves use a DMA controller to write/read
2
In case a second byte is read in the same I C
data to/from their RAM buffer.
message (no Stop or Restart condition) the
content of the shadow register is transferred to
the shift register and transmitted to the master.
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2
I C3S INTERFACE (Cont’d)
2. Enable Word mode by setting the B/W and
BusyW bits in the I2C3SCR2 register. BusyW
bit is set to 1 when modifying any bits in Control
Register 2. Writing a 1 to this bit does not actu-
ally modify BusyW but prevents accidental
clearing of the bit.
3. Write Byte 1 in an even address in RAM. The
byte is not actually written in RAM but in a
shadow register. This address must be within
the I2C RAM buffer of slave addresses 1, 2 or
3.
4. Write Byte 2 in the next higher address in RAM.
This byte is actually written in RAM. During the
next cycle, the shadow register content is writ-
ten in the lower address. The DMA request is
disabled during this cycle.
This process continues until a Stop or Restart
condition occurs.
2. I2C3S attempts to read a word while the CPU is
updating the RAM buffer. To prevent data cor-
ruption, the CPU must switch operation to Word
mode prior to updating a word in the RAM
buffer. Word mode is enabled by software using
the B/W bit in the I2C3SCR2 register. In Word
mode, when the CPU writes the MSB of a word
to address 2n, it is stored in a shadow register
rather than being actually written in RAM. When
the CPU writes the second byte (the LSB) at
address 2n+1, it is directly written in RAM. The
next cycle after the write to address 2n+1, the
MSB is automatically written from the shadow
register to RAM address 2n. DMA is disabled
for a 1 cycle while the CPU is writing a word.
Word mode is disabled by hardware after the
word update is performed. It must be enabled
before each word update by CPU.
5. Byte mode resumes automatically after writing
byte 2 and DMA is re-enabled.
6. Enable interrupts
Note: Word mode does not guarantee byte-pair
coherency of words WRITTEN by the I2C master
in RAM and read by the ST7. Byte pair coherency
in this case must be handled by software.
Use the following procedure when the ST7 writes
a word in RAM:
1. Disable interrupts
Figure 70. 16-bit Word Write Operation Flowchart
HOST
ST7 I2C3SNS
ST7 CPU
SENDS ADDRESS
AND WRITE BIT
DECODES I2C3SNS ADDRESS
DECODES R/W BIT
NORMAL EXECUTION
SETS WRITE FLAG
UPDATES CURRENT ADDRESS-
REGISTER
SENDS WRITE ADDRESS
ISSUES DMA REQUEST
HALTS EXECUTION
N
WORD MODE?
Y
1 Cycle
Max
Repeat
DELAYS WHILE CPU
COMPLETES WORD WRITE
SENDS 1 BYTE OF DATA
STOP CONDITION
RESUMES EXECUTION
WRITES ONE BYTE TO RAM
1 Cycle
Max
SETS BUSYW IN CONTROL -
REGISTER + I2C3S DISABLED
ISSUES INTERRUPT
SERVICES I2C3SNS INTERRUPT
RESETS I2C3SNS WRITE FLAG
ENABLES I2C3SNS
READS I2C3SNS STATUS REGISTER
UPDATES CONTROL REGISTER
Byte-Pair Coherency ensured by setting Word Mode
RAM start address depends on slave address
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ST72340, ST72344, ST72345
Figure 71. 16-bit Word Read Operation Flowchart
HOST
ST7 I2C3SNS
ST7 CPU
SENDS ADDRESS
AND READ BIT
DECODES I2C3SNS ADDRESS
DECODES R/W BIT
NORMAL EXECUTION
SETS READ FLAG
UPDATES CURRENT ADDRESS-
REGISTER
SENDS READ ADDRESS
ISSUES DMA REQUEST
HALTS EXECUTION
N
WORD MODE?
Y
DELAYS WHILE CPU
COMPLETES WORD WRITE
3 Cycles
Max
Repeat
READS 1 WORD FROM RAM
BYTE 1 => SHIFT REG
BYTE 2 => SHADOW REG
RELEASES DMA
RESUMES EXECUTION
RECEIVES BYTE 1
Y
STOP?
N
SHADOW REG => SHIFT REG
RECEIVES BYTE 2
STOP CONDITION
UPDATES STATUS + DMA CNTL
RESETS READ FLAG
SERVICES I2C3SNS INTERRUPT
READS I2C3SNS STATUS REGISTER
Byte-Pair Coherency ensured by setting Word Mode + DMA on Words
RAM start address depends on slave address
11.7.4.5 Application Note
the shift register. Then it is compared with the
three addresses of the interface to decode which
slave of the interface is being addressed.
Taking full advantage of its higher interrupt priority
Slave 3 can be used to allow the addressing mas-
ter to send data bytes as commands to the ST7.
These commands can be decoded by the ST7
software to perform various operations such as
programming the Data E2PROM via IAP (In-Appli-
cation Programming).
Address not matched: the interface ignores it
and waits for another Start condition.
Address matched: the interface generates in se-
quence the following:
– An Acknowledge pulse
Slave 3 writes the command byte and other data in
the RAM and generates an interrupt. The ST7 then
decodes the command and processes the data as
decoded from the command byte. The ST7 also
writes a status byte in the RAM which the address-
ing master can poll.
– Depending on the LSB of the slave address sent
by the master, slaves enter transmitter or receiv-
er mode.
– Send an interrupt to the CPU after completion of
the read/write operation after detecting the Stop/
Restart condition on the SDA line.
11.7.5 Address Handling
As soon as a start condition is detected, the
address is received from the SDA line and sent to
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ST72340, ST72344, ST72345
Notes:
During this operation the I2C slave reads the data
pointed by the current address register. Refer to
Figure 75.
– The Status Register has to be read to clear the
event flag associated with the interrupt
– An interrupt will be generated only if the interrupt
enable bit is set in the Control Register
Random Read: Random read requires a dummy
byte write sequence to load in the byte address.
The addressing device then generates restart
condition and resends the device address similar
to current address read with the read/write bit high.
Refer to Figure 76. Some types of I2C masters
perform a dummy write with a stop condition and
then a current address read.
– Slaves 1 and 2 have a common interrupt and the
Slave 3 has a separate interrupt.
– At the end of write operation, I2C3S is temporar-
ily disabled by hardware by setting BusyW bit in
CR2. The byte count register, status register and
current address register should be saved before
resetting BusyW bit.
In either case, the slave generates a DMA request,
sends an acknowledge and serially clocks out the
data.
.
11.7.5.1 Slave Reception (Write operations)
When the memory address limit is reached the
current address will roll over and the random read
will continue till the addressing master sends a
stop condition.
Byte Write: The Slave address is followed by an
8-bit byte address. Upon receipt of this address an
acknowledge is generated, address is moved into
the current address register and the 8 bit data is
clocked in. Once the data is shifted in, a DMA
request is generated and the data is written in the
RAM. The addressing device will terminate the
write sequence with a stop condition. Refer to
Figure 73
Sequential Read: Sequential reads are initiated
by either a current address read or a random
address read. After the addressing master
receives the data byte it responds with an
acknowledge. As long as the slave receives an
acknowledge it will continue to increment the
current address register and clock out sequential
data bytes.
Page Write: A page write is initiated in similar way
to a byte write, but the addressing device does not
send a stop condition after the first data byte. The
page length is programmed using bits 7:6 (PL[1:0])
in the Control Register1.
When the memory address limit is reached the
current address will roll over and the sequential
read will continue till the addressing master sends
a stop condition. Refer to Figure 78
The current address register value is incremented
by one every time a byte is written. When this
address reaches the page boundary, the next byte
will be written at the beginning of the same page.
Refer to Figure 74.
11.7.5.3 Combined Format:
If a master wants to continue communication
either with another slave or by changing the
direction of transfer then the master would
generate a restart and provide a different slave
address or the same slave address with the R/W
bit reversed. Refer to Figure 79.
11.7.5.2 Slave Transmission (Read Operations)
Current Address Read: The current address
register maintains the last address accessed
during the last read or write operation incremented
by one.
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2
I C3S INTERFACE (Cont’d)
11.7.5.4 Rollover Handling
The page boundaries are defined based on page
size configuration using PL[1:0] bit in the
I2C3SCR1 register. If an 8-byte page size is
selected, the upper 5 bits of the RAM address are
fixed and the lower 3 bits are incremented. For
example, if the page write starts at register
address 0x0C, the write will follow the sequence
0x0C, 0x0D, 0x0E, 0x0F, 0x08, 0x09, 0x0A, 0x0B.
If a 16-byte page size is selected, the upper 4 bits
of the RAM address are fixed and the lower 4 bits
are incremented. For example if the page write
starts at register address 0x0C, the write will follow
the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,
0x01, etc.
The RAM buffer of each slave is divided into pages
whose length is defined according to PL1:0 bits in
I2C3SCR1. Rollover takes place in these pages as
described below.
In the case of Page Write, if the number of data
bytes transmitted is more than the page length, the
current address will roll over to the first byte of the
current page and the previous data will be
overwritten. This page size is configured using
PL[1:0] bit in the I2C3SCR1 register.
In case of Sequential Read, if the current address
register value reaches the memory address limit
the address will roll over to the first address of the
reserved area for the respective slave.
11.7.5.5 Error Conditions
– BERR: Detection of a Stop or a Start condition
during a byte transfer. In this case, the BERR bit
is set by hardware with an interrupt if ITER is set.
During a stop condition, the interface discards
the data, releases the lines and waits for another
Start condition. However, a BERR on a Start
condition will result in the interface discarding the
data and waiting for the next slave address on
the bus.
There is no status flag to indicate the roll over.
Note:
The reserved areas for slaves 1 and 2 have a limit
of 256 bytes. The area for slave 3 is 128 bytes.
The MSB of the address is hardwired, the
addressing master therefore needs to send only
an 8 bit address.
– NACK: Detection of a non-acknowledge bit not
followed by a Stop condition. In this case, NACK
bit is set by hardware with an interrupt if ITER is
set.
Figure 72. Transfer Sequencing
7-bit Slave receiver:
S
Address
A
Data1
A
A
Data2
Data2
A
A
DataN
DataN
A
P
.....
.....
WF
BusyW
7-bit Slave transmitter:
S
Address
A
Data1
NA P
RF
Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
WF = WF event, WFx bit is set (with interrupt if ITWEx=1, after Stop or Restart conditions), cleared by
reading the I2C3SSR register while no communication is ongoing.
RF = RF event, RFx is set (with interrupt if ITREx=1, after Stop or Restart conditions) , cleared by reading
the I2C3SSR register while no communication is ongoing.
BusyW = BusyW flag in the I2C3CR2 register set, cleared by software writing 0.
Note: The I2C3S supports a repeated start (S ) in place of a stop condition (P).
r
134/191
ST72340, ST72344, ST72345
Figure 73. Byte Write
Start
SA
W
Ack
BA
Ack
Data
Ack Stop
Figure 74. Page Write
Start
SA
W
Ack
BA
Ack
Data
Ack
Data
Ack
Stop
Figure 75. Current Address Read
Start SA
R
Ack
Data
Nack
Stop
Figure 76. Random Read (Dummy write + restart + current address read)
BA Ack
Data Nack
SA
Ack Start
Start
W Ack
SA
R
Stop
Figure 77. Random Read (Dummy write + stop + start + current address read)
Start
SA
W Ack
BA
Ack Stop Start
SA
R Ack Data Nack
Stop
Figure 78. Sequential Read
Ack
R
Data Ack
Start
SA
Ack
Data Nack
Stop
Data
Figure 79. Combined Format for Read
Start
SA
R
Ack Data
Nack
Stop
Nack
SA
Restart
R
Ack Data
Legend: SA - Slave Address
W: Write
R: Read
BA - Byte Address
135/191
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2
0.1.4I C3S INTERFACE (Cont’d)
11.7.6 Low Power Modes
Mode
Description
2
No effect on I C interface.
WAIT
I2C interrupts causes the device to exit from WAIT mode.
2
I C registers are frozen.
2
2
HALT
In HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
2
I C registers are frozen.
2
2
ACTIVE
HALT
In ACTIVE HALT mode, the I C interface is inactive and does not acknowledge data on the bus. The I C
interface resumes operation when the MCU is woken up by an interrupt with “exit from ACTIVE HALT mode”
capability.
11.7.7 Interrupt Generation
Figure 80. Event Flags and Interrupt Generation
Restart: Restart condition on SDA
Stop: Stop condition on SDA
Dummy Write: True if no data is written in RAM
Write Protect: True for Write operation and if slaves
are write protected (since this is applicable for
slaves 1 and 2. For slave 3 and for Read operation
write protect will always be 0)
Restart
Stop
Data Status Flag
Dummy Write
Write Protect
Data Status Flag: Actual Interrupt is produced when
this condition is true
Data Status Flag
RF1
RF2
ITRE1/2
NACK
INTERRUPT 1
(Slave address 1/2)
ITER
BERR
WF1
WF2
ITWE1/2
Data Status Flag
Data Status Flag
WF3
ITWE3
BERR
NACK
INTERRUPT 2
ITER
(Slave address 3)
RF3
ITRE3
Data Status Flag
136/191
ST72340, ST72344, ST72345
Note: Read/Write interrupts are generated only after stop or restart conditions. Figure 80 shows the con-
ditions for the generation of the two interrupts.
Enable
Control from
Bit
ITWE1
ITWE1
ITWE2
Exit
Exit
from
Halt
No
No
No
No
Interrupt Event
Flag
Wait
Yes
Yes
Yes
Yes
Interrupt on write to Slave 1
Interrupt on write to Slave 2
Interrupt on write to Slave 3
WF1
WF2
WF3
Interrupt on Read from Slave 1, Slave 2 or Slave 3.
RF1- RF3 ITREx
BERR,
ITER
Errors
Yes
No
NACK
11.7.8 Register Description
2
Bit 2 = ITRE1/2 Interrupt enable on read from
Slave 1 or 2
This bit is set and cleared by software It is also
cleared by hardware when interface is disabled
(PE =0)
I C 3S CONTROL REGISTER 1 (I2C3SCR1)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0: Interrupt on Read from Slave 1 or 2 disabled
1: Interrupt on Read from Slave 1 or 2 enabled
ITWE
1/2
ITRE1/
2
PL1
PL0
0
ITER ITRE3
ITWE3
Bit 1= ITWE3 Interrupt enable on write to Slave 3
This bit is set and cleared by software. It is also
cleared by hardware when interface is disabled.
0: Interrupt after write to Slave 3 disabled
1: Interrupt after write to Slave 3 enabled
Bits 7:6 = PL1:0 Page length configuration
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
Bit 0 = ITWE1/2 Interrupt enable on write to Slave
1 or 2
This bit is set and cleared by software. It is also
cleared by hardware when interface is disabled
software. It is also cleared by hardware when
when interface is disabled.
PL1
0
PL0
0
Page length
8
0
1
16
Full Page (256 bytes for slave 1 & 2, 128
bytes for slave 3)
1
1
0
1
NA
0: Interrupt after write to Slave 1 or 2 disabled
1: Interrupt after write to Slave 1 or 2 enabled
Bit 5 = Reserved, must be kept at 0.
I2C CONTROL REGISTER 2 (I2C3SCR2)
Read / Write
Bit 4 = ITER BERR / NACK Interrupt enable
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: BERR / NACK interrupt disabled
1: BERR / NACK interrupt enabled
Reset Value: 0000 0000 (00h)
7
0
0
0
0
WP2
WP1
PE BusyW B/W
Note: In case of error, if ITER is enabled either in-
terrupt 1 or 2 is generated depending on which
slave flags the error (see Figure 80).
Bits 7:5 = Reserved, must be kept at 0.
Bit 4= WP2 Write Protect enable for Slave 2
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0)
0: Write access to Slave 2 RAM buffer enabled
1: Write access to Slave 2 RAM buffer disabled
Bit 3= ITRE3 Interrupt enable on read from Slave 3
This bit is set and cleared by software It is also
cleared by hardware when interface is disabled
(PE =0).
0: Interrupt on Read from Slave 3 disabled
1: Interrupt on Read from Slave 3 enabled
137/191
ST72340, ST72344, ST72345
2
I C3S INTERFACE (Cont’d)
Note: When word mode is enabled, all interrupts
should be masked while the word is being written
in RAM.
Bit 3= WP1 Write Protect enable for Slave 1
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: Write access to Slave 1 RAM buffer enabled
1: Write access to Slave 1 RAM buffer disabled
2
I C3S STATUS REGISTER (I2C3SSR)
Read Only
Reset Value: 0000 0000 (00h)
7
0
Notes: (Applicable for both WP2/ WP1)
– Only write operations are disabled/enabled.
Read operations are not affected.
NACK BERR WF3
WF2
WF1
RF3
RF2
RF1
– If a write operation is attempted, the slave ad-
dress is acknowledged, the current address reg-
ister is overwritten, data is also acknowledged
but it is not written to the RAM.
Bit 7= NACK Non Acknowledge not followed by
Stop
This bit is set by hardware when a non acknowl-
edge returned by the master is not followed by a
Stop or Restart condition. It is cleared by software
reading the SR register or by hardware when the
interface is disabled (PE=0).
0: No NACK error occurred
1: Non Acknowledge not followed by Stop
– Both the current address and byte count regis-
ters are incremented as in normal operation.
– No interrupt generated if slave is write protected
– BusyW will not be set if slave is write protected
Bit 2= PE Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
Bit 6 = BERR Bus error
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. It is
cleared by software reading SR register or by
hardware when the interface is disabled (PE=0).
1: Slave capability enabled
2
Note: To enable the I C interface, write the CR
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
register TWICE with PE=1 as the first write only
activates the interface (only PE is set)
Bit 1 = BusyW Busy on Write to RAM Buffer
This bit is set by hardware when a STOP/ RE-
START is detected after a write operation. The
I2C3S peripheral is temporarily disabled till this bit
is reset. This bit is cleared by software. If this bit is
not cleared before the next slave address recep-
tion, further communication will be non-acknowl-
edged. This bit is set to 1 when modifying any bits
in Control Register 2. Writing a 1 to this bit does
not actually modify BusyW but prevents acciden-
tally clearing of the bit.
Bit 5 = WF3 Write operation to Slave 3
This bit is set by hardware on reception of the di-
2
rection bit in the I C address byte for Slave 3. This
bit is cleared when the status register is read when
there is no communication ongoing or when the
peripheral is disabled (PE = 0)
0: No write operation to Slave 3
1: Write operation performed to Slave 3
0: No BusyW event occurred
Bit 4 = WF2 Write operation to Slave 2
1: A STOP/ RESTART is detected after a write op-
eration
This bit is set by hardware on reception of the di-
2
rection bit in the I C address byte for Slave 2. This
bit is cleared when the status register is read when
there is no communication ongoing or when the
peripheral is disabled (PE = 0)
Bit 0 = B/W Byte / Word Mode
This control bit must be set by software before a
word is updated in the RAM buffer and cleared by
hardware after completion of the word update. In
Word mode the CPU cannot be interrupted when it
is modifying the LSB byte and MSB byte of the
word. This mode is to ensure the coherency of
data stored as words.
0: No write operation to Slave 2
1: Write operation performed to Slave 2
Bit 3 = WF1 Write operation to Slave 1
This bit is set by hardware on reception of the di-
2
0: Byte mode
1: Word mode
rection bit in the I C address byte for Slave 1. This
bit is cleared by software when the status register
is read when there is no communication ongoing
138/191
ST72340, ST72344, ST72345
or by hardware when the peripheral is disabled
(PE = 0).
is not limited by the full page length. It is also
cleared by hardware when interface is disabled
(PE =0).
0: No write operation to Slave 1
1: Write operation performed to Slave 1
2
I C3S INTERFACE (Cont’d)
I2C SLAVE 1 ADDRESS REGISTER
(I2C3SSAR1)
Read / Write
Reset Value : 0000 0000 (00h)
Bit 2 = RF3 Read operation from Slave 3
This bit is set by hardware on reception of the di-
2
rection bit in the I C address byte for Slave 3. It is
cleared by software reading the SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
7
0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR
EN1
7
6
5
4
3
2
1
0: No read operation from Slave 3
1: Read operation performed from Slave 3
Bits 7:1 = ADDR[7:1] Address of Slave 1
This register contains the first 7 bits of Slave 1 ad-
dress (excluding the LSB) and is user program-
mable. It is also cleared by hardware when inter-
face is disabled (PE =0).
Bit 1= RF2 Read operation from Slave 2
This bit is set by hardware on reception of the di-
2
rection bit in the I C address byte for Slave 2. It is
cleared by software reading the SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
Bit 0= EN1 Enable bit for Slave Address 1
This bit is used to enable/disable Slave Address 1.
It is also cleared by hardware when interface is
disabled (PE =0).
0: Slave Address 1 disabled
1: Slave Address 1 enabled
0: No read operation from Slave 2
1: Read operation performed from Slave 2
Bit 0= RF1 Read operation from Slave 1
I2C SLAVE 2 ADDRESS REGISTER
(I2C3SSAR2)
This bit is set by hardware on reception of the di-
2
rection bit in the I C address byte for Slave 1. It is
Read / Write
cleared by software reading SR register when
there is no communication ongoing. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
Reset Value: 0000 0000 (00h)
7
0
0: No read operation from Slave 1
1: Read operation performed from Slave 1
ADDR ADDR ADDR ADDR ADDR ADDR ADDR
EN2
7
6
5
4
3
2
1
2
Bits 7:1 = ADDR[7:1] Address of Slave 2.
I C BYTE COUNT REGISTER (I2C3SBCR)
This register contains the first 7 bits of Slave 2 ad-
dress (excluding the LSB) and is user programma-
ble. It is also cleared by hardware when interface
is disabled (PE =0).
Read only
Reset Value: 0000 0000 (00h)
7
0
NB7
NB6
NB5
NB4
NB3
NB2
NB1
NB0
Bit 0= EN2 Enable bit for Slave Address 2
This bit is used to enable/disable Slave Address 2.
It is also cleared by hardware when interface is
disabled (PE =0).
Bits 7:0 = NB [7:0] Byte Count Register
This register keeps a count of the number of bytes
received or transmitted through any of the three
addresses. This byte count is reset after reception
by a slave address of a new transfer and is incre-
mented after each byte is transferred. This register
0: Slave Address 2 disabled
1: Slave Address 2 enabled
139/191
ST72340, ST72344, ST72345
2
I C3S INTERFACE (Cont’d)
I2C SLAVE 3 ADDRESS REGISTER
(I2C3SSAR3)
I2C SLAVE 2 MEMORY CURRENT ADDRESS
REGISTER (I2C3SCAR2)
Read / Write
Read only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
EN3
7
6
5
4
3
2
1
Bit 7:0 = CA[7:0] Current address of Slave 2 buffer
This register contains the 8-bit offset of Slave Ad-
dress 2 reserved area in RAM. It is also cleared by
hardware when interface is disabled (PE =0).
Bit 7:1 = ADDR[7:1] Address of Slave 3
This register contains the first 7 bits of Slave 3 ad-
dress (excluding the LSB) and is user programma-
ble. It is also cleared by hardware when interface
is disabled (PE =0).
I2C SLAVE 3 MEMORY CURRENT ADDRESS
REGISTER (I2C3SCAR3)
Read only
Reset Value: 0000 0000 (00h)
Bit 0= EN3 Enable bit for Slave Address 3
This bit is used to enable/disable Slave Address 3.
It is also cleared by hardware when interface is
disabled (PE =0).
0: Slave Address 3 disabled
1: Slave Address 3 enabled
7
0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
I2C SLAVE 1 MEMORY CURRENT ADDRESS
REGISTER (I2C3SCAR1)
Bit 6:0 = CA[6:0] Current address of Slave 3 buffer
This register contains the 8-bit offset of slave ad-
dress 3 reserved area in RAM. It is also cleared by
hardware when interface is disabled (PE =0).
Read only
Reset Value: 0000 0000 (00h)
7
0
Note: Slave address 3 can store only 128 bytes.
For slave address 3, CA7 bit will remain 0. i.e. if
the Byte Address sent is 0x80 then the Current Ad-
dress register will hold the value 0x00 due to an
overflow.
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Bit 7:0 = CA[7:0] Current address of Slave 1 buffer
This register contains the 8 bit offset of Slave Ad-
dress 1 reserved area in RAM. It is also cleared by
hardware when interface is disabled (PE =0).
140/191
ST72340, ST72344, ST72345
2
Table 25. I C3S Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
0060h
0061h
0062h
0063h
I2C3SCR1
I2C3SCR2
I2C3SSR
PL1
0
PL0
0
0
ITER
WP2
WF2
NB4
ITRE3
WP1
WF1
NB3
ITRE1/2
PE
ITWE3
BusyW
RF2
ITWE1/2
B/W
0
NACK
NB7
BERR
NB6
WF3
NB5
RF3
RF1
I2C3SBCR
NB2
NB1
NB1
0064h
0065h
0066h
0067h
0068h
0069h
I2C3SSAR1 ADDR7
I2C3SCAR1
ADDR6
ADDR6
ADDR6
ADDR5
ADDR5
ADDR5
ADDR4
ADDR3
ADDR2
ADDR2
ADDR2
ADDR1
ADDR1
ADDR1
EN1
EN2
EN3
CA 7 .. CA0
I2C3SSAR2 ADDR7
I2C3SCAR2
ADDR4
ADDR3
CA 7 .. CA0
I2C3SSAR3 ADDR7
I2C3SCAR3
ADDR4
ADDR3
CA 7 .. CA0
141/191
ST72340, ST72344, ST72345
11.8 10-BIT A/D CONVERTER (ADC)
11.8.1 Introduction
11.8.2 Main Features
■ 10-bit conversion
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.
■ Up to 16 channels with multiplexed input
■ Linear successive approximation
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 81.
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
Figure 81. ADC Block Diagram
f
CPU
DIV 4
DIV 2
0
1
f
ADC
CH3
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
ADCDRH
D9 D8 D7 D6 D5 D4
D3
D2
ADCDRL
0
0
0
0
0
0
D1
D0
142/191
ST72340, ST72344, ST72345
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.8.3 Functional Description
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
automatically.
If the input voltage (V ) is greater than V
AIN
AREF
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.
If the input voltage (V ) is lower than V
(low-
SSA
AIN
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
2. Read the ADCDRH register. This clears EOC
automatically.
R
is the maximum recommended impedance
11.8.3.3 Changing the conversion channel
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
allotted time.
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
11.8.3.1 A/D Converter Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
11.8.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
channel to convert.
11.8.3.2 Starting the Conversion
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
In the ADCCSR register:
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
– Set the ADON bit to enable the A/D converter
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
HALT
t
(see Electrical Characteristics)
STAB
before accurate conversions can be
performed.
When a conversion is complete:
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
11.8.5 Interrupts
None.
143/191
ST72340, ST72344, ST72345
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH3 CH2 CH1 CH0
7
0
AIN0
AIN1
AIN2
AIN3
AIN4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
Bit 7 = EOC End of Conversion
AIN5
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
Reserved
Reserved
AIN8
Reserved
AIN10
Reserved
AIN12
AIN13
AIN14
AIN15
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: f
1: f
= f
= f
/4
/2
ADC
ADC
CPU
CPU
*The number of channels is device dependent. Refer to
the device pinout description.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
DATA REGISTER (ADCDRH)
Read Only
Bit 4 = Reserved. Must be kept cleared.
Reset Value: 0000 0000 (00h)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Bits 7:0 = D[9:2] MSB of Converted Analog Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
D1
D0
Bits7:2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Converted Analog Value
144/191
ST72340, ST72344, ST72345
10-BIT A/D CONVERTER (Cont’d)
Table 26. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH3
0
CH2
0
CH1
0
CH0
0
0070h
0071h
0072h
0
ADCDRH
Reset Value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
ADCDRL
Reset Value
D1
0
D0
0
0
0
0
0
0
0
145/191
ST72340, ST72344, ST72345
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two submodes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in seven main
groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
Immediate
Direct
ld A,#$55
ld A,$55
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Indexed
Indirect
ld A,($55,X)
ld A,([$55],X)
jrne loop
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
Table 27. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed ld A,($10,X)
Indexed ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
0000..FFFF
00..1FE
Indirect Indexed ld A,([$10],X)
Indirect Indexed ld A,([$10.w],X) 0000..FFFF
1)
1)
Direct
jrne loop
PC-128/PC+127
PC-128/PC+127
00..FF
Indirect
Direct
jrne [$10]
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Bit
Indirect Relative btjt [$10],#7,skip 00..FF
Note:
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
146/191
ST72340, ST72344, ST72345
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (Short)
NOP
The address is a byte, thus requires only 1 byte af-
ter the opcode, but only allows 00 - FF addressing
space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (Long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Subroutine Return
Interrupt Subroutine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
12.1.4 Indexed (No Offset, Short, Long)
SIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
RIM
SCF
The indirect addressing mode consists of three
submodes:
RCF
Reset Carry Flag
Reset Stack Pointer
Load
RSP
Indexed (No Offset)
LD
There is no offset (no extra byte after the opcode),
and allows 00 - FF addressing space.
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only 1 byte after
the opcode and allows 00 - 1FE addressing space.
CPL, NEG
MUL
Indexed (Long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
12.1.5 Indirect (Short, Long)
SWAP
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
12.1.2 Immediate
Immediate instructions have 2 bytes, the first byte
contains the opcode, the second byte contains the
operand value.
The pointer address follows the opcode. The indi-
rect addressing mode consists of two submodes:
Indirect (Short)
Immediate Instruction
Function
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
LD
Load
CP
Compare
BCP
Bit Compare
Indirect (Long)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
147/191
ST72340, ST72344, ST72345
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
12.1.7 Relative Mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
Indirect Instructions
JRxx
Conditional Jump
Call Relative
The indirect indexed addressing mode consists of
two submodes:
CALLR
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 28. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
148/191
ST72340, ST72344, ST72345
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a prebyte
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PIX 92 Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
149/191
ST72340, ST72344, ST72345
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
A
M
M
M
M
Addition
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
150/191
ST72340, ST72344, ST72345
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
151/191
ST72340, ST72344, ST72345
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 83.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 83. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and
V
=3.3V (for the
DD
3V≤V ≤3.6V voltage range). They are given only
DD
as design guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 82.
Figure 82. Pin loading conditions
ST7 PIN
C
L
152/191
ST72340, ST72344, ST72345
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
ESD(HBM)
see Section 13.9.3 on page 165
V
Electrostatic discharge voltage (Human Body Model)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
75
150
20
40
- 25
5
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
I
IO
mA
Injected current on RESET pin
5
2) & 4)
I
Injected current on OSC1 and OSC2 pins
5
INJ(PIN)
5)
Injected current on PB0 pin
+5
5
6)
Injected current on any other pin
2)
6)
ΣI
Total injected current (sum of all I/O and control pins)
20
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
Maximum junction temperature (see Table on page 180)
-65 to +150
°C
STG
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN DD
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
IN
SS
corresponding V maximum must always be respected
IN
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. No negative current injection allowed on PB0 pin.
6. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
153/191
ST72340, ST72344, ST72345
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Conditions
= 8 MHz. max.
Min
3.3
2.7
Max
5.5
Unit
f
f
CPU
V
Supply voltage
V
DD
= 4 MHz. max.
5.5
CPU
3.3V≤ V ≤5.5V
Up to 16
Up to 8
DD
f
External clock frequency
MHz
OSC
2.7V≤V <3.3V
DD
Note:
When the power supply is between 2.7 and 2.95V (V
max), the device is either in the guaranteed
IT+(LVD)
functional area or in reset state, thus allowing deterministic application behaviour. However the LVD may
generate a reset below 2.95V and the user should therefore not use the device below this level when the
LVD is enabled.
Figure 84. f
Maximum Operating Frequency Versus VDD Supply Voltage
CPU
f
[MHz]
8
CPU
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
4
2
0
FUNCTIONALITY
GUARANTEED
IN THIS AREA
CAUTION: RESET MAY
BE ACTIVATED BY LVD
IN THIS AREA
SUPPLY VOLTAGE [V]
5.5
2.7 3.3
3.6
4.0
4.5
5.0
13.3.2 Low Voltage Detector (LVD) Thresholds
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High Threshold
Med. Threshold
Low Threshold
3.85
3.24
2.60
4.20
3.56
2.88
4.61
3.90
3.14
Reset release threshold
V
IT+(LVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.66
3.04
2.45
3.98
3.36
2.71
4.36
3.66
2.95
Reset generation threshold
V
V
IT-(LVD)
hys(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
200
mV
ms/V
ns
IT+(LVD) IT-(LVD)
1)
1)
100
Vt
V
V
rise time rate
20
POR
DD
DD
t
glitches filtered by LVD
150
g(VDD)
Note:
1. Not tested in production, guaranteed by design
154/191
ST72340, ST72344, ST72345
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to +85°C unless otherwise specified
A
1)
1)
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
4.91
Unit
4.15
3.64
3.00
4.50
3.96
3.28
1=>0 AVDF flag toggle threshold
V
4.30
3.54
IT+(AVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.96
3.44
2.85
4.28
3.76
3.11
4.66
4.06
3.35
0=>1 AVDF flag toggle threshold
V
V
IT-(AVD)
hys(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
-V
200
mV
mV
IT+(AVD) IT-(AVD)
Voltage drop between ADV flag set
and LVD reset activated
∆V
V
-V
450
IT-
IT-(AVD) IT-(LVD)
Note:
1. Not tested in production, guaranteed by characterization.
155/191
ST72340, ST72344, ST72345
13.4 PLL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
= 2.7 to 3.65V
DD
0.95
1
1.05
PLL option x4 selected
2)
f
PLL Input frequency
MHz
PLLIN
V
= 3.3 to 5.5V
DD
0.90
1
1.10
PLL option x8 selected
PLL option x4 selected
PLL option x8 selected
1)
2.7
3.3
3.65
5.5
V
PLL operating range
PLL jitter period
V
kHz
%
DD(PLL)
t
f
= 1MHz
8
w(JIT)
RC
VDD = 3.0V
VDD = 5.0V
3.0
1.6
600
JIT
PLL jitter (∆f
/f
)
PLL
CPU CPU
I
PLL current consumption
T =25°C
µA
DD(PLL)
A
Note:
1. To obtain a x4 multiplication ratio in the range 3.3 to 5.5V, the DIV2EN option bit must enabled.
2. Guaranteed by design.
13.4.1 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Internal RC Oscillator operating voltage
Refer to operating range
2.7
5.5
DD(RC)
of V with T Section
13.3.1 on page 154
DD
A,
V
V
x4 PLL operating voltage
x8 PLL operating voltage
2.7
3.3
5.5
5.5
V
DD(x4PLL)
DD(x8PLL)
PLL
input
clock
t
PLL Startup time
60
STARTUP
(f
)
PLL
cycles
13.5 INTERNAL RC OSCILLATOR CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
625
Max
Unit
RCCR = FF (reset value), T =25°C,V =5V
Internal RC oscillator fre-
A
DD
f
kHz
1)
RC
2 )
quency
RCCR = RCCR0 ,T =25°C,V =5V
1000
A
DD
T =25°C,V =5V
-1
-1
+1
+1
%
%
%
%
%
A
DD
3)
T =25°C, V =4.5 to 5.5V
A
DD
Accuracy of Internal RC
oscillator with
RCCR=RCCR0
3)
ACC
T =25 to +85°C,V =5V
-3
+3
RC
A
DD
2)
3)
T =25 to +85°C,V =4.5 to 5.5V
-3.5
-3
+3.5
+7
A
DD
3)
T =-40 to +25°C,V =4.5 to 5.5V
A
DD
RC oscillator current con-
sumption
3)
I
t
T =25°C,V =5V
600
µA
µs
DD(RC)
A
DD
2)
RC oscillator setup time T =25°C,V =5V
10
su(RC)
A
DD
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V and V pins as close as possible to the ST7 device.
DD
SS
2. See “Internal RC Oscillator” on page 30
3. Expected results. Data based on characterization, not tested in production
156/191
ST72340, ST72344, ST72345
Figure 85. Typical RC Frequency vs RCCR
Typical Rc freq (MHz) = f(RCCR) @ 25°C
1.7
1.6
Rc @ 5V
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
Rc @ 3V
0
50
100
150
200
250
RCCR (decimal)
13.6 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.6.1 Supply Current
T = -40 to +85°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
8.5
3.7
4.1
2.2
1
Max
13
6
Unit
1)
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
f
f
f
f
=8MHz
CPU
CPU
CPU
CPU
2)
=8MHz
mA
3)
4)
7
=250kHz
=250kHz
3.5
10
60
700
I
DD
5)
Supply current in HALT mode
-40°C≤T ≤+85°C
A
6)7)
50
Supply current in AWUFH mode
T = +25°C
µA
A
6)7)
500
Supply current in Active Halt mode
T = +25°C
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
CPU
OSC DD
V
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
DD
SS
5. All I/O pins in output mode with a static value at V (no load), LVD disabled. Data based on characterization results,
SS
tested in production at V max and f
max.
DD
CPU
6. All I/O pins in input mode with a static value at V or V (no load). Data tested in production at V max. and f
DD
SS
DD
CPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
157/191
ST72340, ST72344, ST72345
SUPPLY CURRENT CHARACTERISTICS
Figure 86. Typical I in RUN vs. f
Figure 89. Typical I in WAIT vs. f
DD
CPU
DD
CPU
9
4
.5
8
1
2
3.5
3
0.5
1
7
4
2
6
5
4
3
2
1
0
6
8
4
2.5
2
6
8
1.5
1
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Note: Graph displays data beyond thVeddn(Vo) rmal operating range of 3V - 5.5V
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 87. Typical I in RUN at f
= 8MHz
CPU
DD
Figure 90. Typical I in WAIT at f
= 8MHz
DD
CPU
4
9
8
7
6
5
4
3
2
1
0
3.5
3
0.5
1
2
4
2.5
2
6
140°C
90°C
25°C
-5°C
8
1.5
1
0.5
-45°C
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Note: Graph displays data beyond thVeddn(Vo) rmal operating range of 3V - 5.5V
22.533.544.55 5.56 6.5
Vdd (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 91. Typical I in SLOW-WAIT vs. f
DD
CPU
Figure 88. Typical I in SLOW vs. f
0.60
DD
CPU
250KHz
0.50
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
125KHz
250KHz
125KHz
62KHz
62KHz
0.40
0.30
0.20
0.10
0.00
2.7
3.3
4
5
6
2.7
3.3
4
5
6
VDD (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
VDD (V)
Note: Graph displays data beyond the normal operating range of 3V - 5.5V
Figure 92. Typical I vs. Temp. at V = 5V and
DD
DD
f
= 8MHz
CPU
6.00
5.00
4.00
3.00
2.00
1.00
0.00
RUN
WAIT
SLOW
SLOW-WAIT
-45
25
90
110
Temperature (°C)
158/191
ST72340, ST72344, ST72345
13.6.2 On-chip peripherals
Symbol
Parameter
Conditions
Typ
20
Unit
f
f
f
f
f
f
f
f
f
f
=4MHz
=8MHz
=4MHz
=8MHz
=2MHz
=4MHz
=4MHz
=8MHz
=4MHz
=8MHz
V
V
V
V
V
V
V
V
V
V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
CPU
CPU
CPU
CPU
ADC
ADC
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
1)
I
16-bit Timer supply current
DD(16-b timer)
100
250
800
300
1000
100
500
250
800
2)
I
SPI supply current
DD(SPI)
3)
I
ADC supply current when converting
µA
DD(ADC)
4)
I
I2C supply current
DD(I2C)
DD(SCI)
5)
I
SCI supply current
Notes:
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f =8MHz.
cpu
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions.
DD
4. Data based on a differential I measurement between reset configuration (I2C disabled) and a permanent I2C master
DD
communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm
external pull-up on clock and data lines).
5. Data based on a differential I measurement between SCI low power state (SCID=1) and a permanent SCI data trans-
DD
mit sequence.
159/191
ST72340, ST72344, ST72345
13.7 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.7.1 General Timings
1)
3)
2)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
250
10
375
1500
22
tCPU
µs
Interrupt reaction time
t
=8MHz
v(IT)
CPU
t
= ∆t
+ 10
c(INST)
1.25
2.75
v(IT)
13.7.2 External Clock Source
Symbol
Parameter
Conditions
Min
0.7xV
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
V
DD
OSC1H
DD
V
V
V
0.3xV
DD
OSC1L
SS
t
t
4)
w(OSC1H)
see Figure 93
OSC1 high or low time
15
w(OSC1L)
ns
t
t
4)
r(OSC1)
OSC1 rise or fall time
15
1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
DD
µA
L
SS
IN
Figure 93. Typical Application with an External Clock Source
90%
V
OSC1H
OSC1L
10%
V
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
ST72XXX
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
4. Data based on design simulation and/or technology characteristics, not tested in production.
13.7.3 Auto Wakeup from Halt Oscillator (AWU)
Symbol
Parameter
Conditions
Min
Typ
Max
250
50
Unit
kHz
µs
f
t
AWU Oscillator Frequency
AWU Oscillator startup time
50
125
AWU
RCSRT
160/191
ST72340, ST72344, ST72345
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
13.7.4 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph is based on
characterization results with specified typical ex-
ternal components. In the application, the resona-
tor and the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).
Symbol
Parameter
Conditions
Min
1
Max
16
Unit
MHz
kΩ
1)
f
Oscillator Frequency
OSC
2)
R
Feedback resistor
20
40
F
f
f
f
f
= 1 to 2 MHz
20
20
15
15
60
50
35
35
OSC
OSC
OSC
OSC
Recommended load capacitance ver-
C
C
= 2 to 4 MHz
= 4 to 8 MHz
= 8 to 16 MHz
L1
L2
sus equivalent serial resistance of the
pF
3)
crystal or ceramic resonator (R )
S
Symbol
Parameter
Conditions
Typ
Max
Unit
V
=5V:
DD
f
f
f
f
= 2MHz, C0 = 6pF, Cl1 = Cl2 = 68pF
= 4MHz, C0 = 6pF, Cl1 = Cl2 = 68pF
= 8MHz, C0 = 6pF, Cl1 = Cl2 = 40pF
= 16MHz, C0 = 7pF, Cl1 = Cl2 = 20pF
426
425
456
660
OSC
OSC
OSC
OSC
i
OSC2 driving current
µA
2
Notes:
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R value.
S
Refer to crystal/ceramic resonator manufacturer for more details.
2. Data based on characterisation results, not tested in production. The relatively low value of the RF resistor, offers a
good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias con-
dition change. However, it is recommended to take this point into account if the µC is used in tough humidity conditions.
3. For C and C it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed
L1
L2
for high-frequency applications and selected to match the requirements of the crystal or resonator. C and C are usu-
L1
L2,
ally the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C . PCB and MCU pin capacitance must be included when sizing C and C (10 pF can be used as a rough esti-
L2
L1
L2
mate of the combined pin and board capacitance).
Figure 94. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
f
OSC
POWER DOWN
LOGIC
C
L1
OSC1
LINEAR
AMPLIFIER
FEEDBACK
LOOP
i
VDD/2
Ref
2
RESONATOR
OSC2
R
F
C
L2
ST72XXX
161/191
ST72340, ST72344, ST72345
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
f
OSC
2)
Supplier
Typical Ceramic Resonators
(MHz)
2
CSTCC2M00G56Z-R0
SMD CSTCR4M00G53Z-R0
Lead CSTLS4M00G53Z-R0
SMD CSTCE8M00G52Z-R0
Lead CSTLS4M0052Z-R0
SMD CSTCE16M0V51Z-R0
Lead CSTLS16M0X51Z-R0
4
8
16
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]
LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]
For more information on these resonators, please consult www.murata.com
162/191
ST72340, ST72344, ST72345
13.8 MEMORY CHARACTERISTICS
T = -40°C to 85°C, unless otherwise specified
A
13.8.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.8.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating range of
with T Section 13.3.1
on page 154
V
2.7
5.5
10
V
Operating voltage for Flash write/erase
V
DD
A,
DD
2)
T =−40 to +85°C
5
0
t
Programming time for 1~32 bytes
ms
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
cycles
RET
A
7)
N
Write erase cycles
T =+25°C
10K
RW
A
Read / Write / Erase modes
2.6
mA
f
= 8MHz, V = 5.5V
CPU
DD
6)
I
Supply current
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
µA
µA
13.8.3 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating range of V with
Operating voltage for EEPROM
write/erase
DD
5.5
10
V
t
2.7
V
DD
T
Section 13.3.1 on page 154
A,
Programming time for 1~32
bytes
T =−40 to +85°C
5
ms
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
ret
A
7)
N
Write erase cycles
T =+25°C
300K
cycles
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.
163/191
ST72340, ST72344, ST72345
13.9 EMC CHARACTERISTICS
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during product characterization.
13.9.1 Functional EMS (Electro Magnetic
Susceptibility)
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
■ FTB: A Burst of Fast Transient voltage (positive
– Critical Data corruption (control registers...)
Prequalification trials:
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
13.9.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
TBD
FESD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f =8MHz
DD
A
OSC
V
through 100pF on V and V pins to induce a func-
TBD
FFTB
DD DD
conforms to IEC 1000-4-4
tional disturbance
13.9.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the
product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
8/4MHz 16/8MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
=5V, T =+25°C,
A
DD
dBµV
S
Peak level
SO20 package,
conforming to SAE J 1752/3
EMI
-
Note:
1. Data based on characterization results, not tested in production.
164/191
ST72340, ST72344, ST72345
EMC CHARACTERISTICS (Cont’d)
13.9.3 Absolute Maximum Ratings (Electrical
Sensitivity)
13.9.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Human Body Model can be simulated.
This test conforms to the JESD22-A114A/A115A
standard.
Based on two different tests (ESD and LU) using
specific measurement methods, the product is
stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
>2000
V
A
ESD(HBM)
Note:
1. Data based on characterization results, not tested in production.
13.9.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards. For more details, refer to the
application note AN1181.
■ LU: 3 complementary static tests are required
on 6 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more details, refer to the application note
AN1181.
Electrical Sensitivities
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
DLU
V
=5.5V, f
=4MHz, T =+25°C
A
DD
OSC
A
165/191
ST72340, ST72344, ST72345
13.10 I/O PORT PIN CHARACTERISTICS
13.10.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Input low level voltage
VSS - 0.3
0.7xVDD
0.3xVDD
VDD + 0.3
IL
V
1)
V
Input high level voltage
IH
Schmitt trigger voltage
V
400
400
mV
1)
hys
hysteresis
I
Input leakage current
V
SS≤V ≤V
DD
1
L
IN
Static current consumption in-
µA
I
duced by each floating input Floating input mode
S
2)
pin
V
V
=5V
=3V
50
120
160
5
250
Weak pull-up equivalent
DD
DD
R
V =V
SS
kΩ
3)
PU
IN
resistor
C
I/O pin capacitance
pF
IO
Output high to low level fall
t
t
25
25
1)
f(IO)out
time
C =50pF
Between 10% and 90%
L
ns
Output low to high level rise
1)
r(IO)out
time
4)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 95). Static peak current value taken at a fixed V value,
IN
based on design simulation and technology characteristics, not tested in production. This value depends on V and tem-
DD
perature values.
3. The R pull-up equivalent resistor is based on a resistive transistor.
PU
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 95. Two typical Applications with unused I/O Pin
V
ST7XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
Caution: During normal operation the ICCCLK pin must be pulled-up, internally or externally
(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC
robustness and lower cost.
166/191
ST72340, ST72344, ST72345
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.10.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
I =+5mA
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 98)
1.0
IO
I =+2mA
0.4
1.3
IO
1)
V
OL
I =+20mA
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 101)
IO
I =+8mA
0.75
IO
I =-5mA
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure )
V
V
-1.5
IO
DD
DD
2)
V
OH
I =-2mA
-0.8
IO
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 97)
I =+2mA
0.7
0.5
IO
1)3)
2)3)
1)3)
2)3)
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
V
I =+8mA
IO
Output high level voltage for an I/O pin
when 4 pins are sourced at same time (Figure
108)
I =-2mA
V
V
DD
-0.8
IO
OH
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 99)
I =+2mA
0.9
0.6
IO
V
V
OL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
I =+8mA
IO
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see ...)
I =-2mA
V
-0.9
DD
IO
OH
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
3. Not tested in production, based on characterization results.
167/191
ST72340, ST72344, ST72345
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 96. Typical V at V =2.4V (std I/Os)
Figure 99. Typical V at V =2.4V (high-sink I/
OL DD
OL
DD
Os)
1000
800
600
400
200
0
1000
800
600
400
200
0
-45°C
25°C
-45°C
25°C
90°C
130°C
90°C
130°C
0
2
4
6
ILOAD (mA)
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
Figure 97. Typical V at V =3V (std I/Os)
OL
DD
Figure 100. Typical V at V =3V (high-sink
OL
DD
I/Os)
1000
800
600
400
200
0
1200
-45°C
1000
800
600
400
200
0
-45°C
25°C
25°C
90°C
130°C
90°C
130°C
0
2
4
6
ILOAD (mA)
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
Figure 98. Typical V at V =5V (std I/Os)
OL
DD
Figure 101. Typical V at V =5V (high-sink
OL
DD
I/Os)
1000
800
600
400
200
0
-45°C
700
25°C
90°C
130°C
600
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
0
2
4
6
ILOAD (mA)
0
2
4
6
8
10 12 14 16 18 20
ILOAD (mA)
168/191
ST72340, ST72344, ST72345
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 102. Typical V vs. V (std I/Os, 2mA)
Figure 105. Typical V
Iio=2mA)
vs. V
(HS I/Os,
OL
DD
OL
DD
200
160
120
80
1000
800
600
400
200
0
-45°C
25°C
-45°C
25°C
90°C
90°C
130°C
130°C
40
0
2.4
2.6
2.8
Ilo (mA)
3
5
2.5
3
3.5
Ilo (mA)
4
5
Figure 103. Typical V vs. V (std I/Os, 6mA)
OL
DD
Figure 106. Typical V
Iio=12mA)
vs. V
(HS I/Os,
OL
DD
500
400
300
200
100
0
000
800
600
400
200
0
-45°C
25°C
90°C
130°C
-45°C
25°C
90°C
130°C
2.5
3
3.5
Ilo (mA)
4
5
2.4
2.6
2.8
Ilo (mA)
3
5
Figure 104. Typical V
Iio=8mA)
vs. V
(HS I/Os,
OL
DD
Figure 107. Typical V -v at v =2.4V (std
DD OH
DD
I/Os)
1000
800
600
400
200
0
-45°C
1400
25°C
90°C
1200
1000
800
600
400
200
0
130°C
-45°C
25°C
90°C
130°C
2.4
2.6
2.8
Ilo (mA)
3
5
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
Figure 108. Typical V -V at V =3V (std
DD OH
DD
I/Os)
169/191
ST72340, ST72344, ST72345
1800
-45°C
25°C
1500
1200
900
600
300
0
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
170/191
ST72340, ST72344, ST72345
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 109. Typical V -V at V =4V (std)
Figure 110. Typical V -V at V =5V (std)
DD OH
DD
DD OH
DD
1000
900
800
700
600
500
400
300
200
100
0
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-45°C
25°C
-45°C
25°C
90°C
130°C
90°C
130°C
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
0
-2 -4 -6 -8 -10 -12 -14 -16 -18 -20
ILOAD (mA)
Figure 111. Typical V -V vs. V (High Sink)
DD OH
DD
200
160
120
80
500
400
300
200
100
0
-45°C
25°C
90°C
130°C
-45°C
25°C
90°C
130°C
40
0
2.5
3
3.5
Ilo (mA)
4
5
2.5
3
3.5
Ilo (mA)
4
5
171/191
ST72340, ST72344, ST72345
13.11 CONTROL PIN CHARACTERISTICS
13.11.1 Asynchronous RESET Pin
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
Vss - 0.3
0.7xVDD
0.3xVDD
VDD + 0.3
IL
V
Input high level voltage
IH
1)
V
Schmitt trigger voltage hysteresis
2
V
hys
I =+5mA
0.5
0.2
40
70
26
1.0
0.4
80
IO
2)
V
Output low level voltage
V
=5V
V
OL
DD
I =+2mA
IO
V
V
=5V
=3V
20
40
DD
DD
3) 1)
R
Pull-up equivalent resistor
kΩ
ON
120
t
Generated reset pulse duration
Internal reset sources
µs
µs
ns
w(RSTL)out
4)
t
t
External reset pulse hold time
20
h(RSTL)in
Filtered glitch duration
200
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
172/191
ST72340, ST72344, ST72345
CONTROL PIN CHARACTERISTICS (Cont’d)
1)2)3)4)
Figure 112. RESET pin protection when LVD is enabled.
V
ST72XXX
DD
Optional
(note 3)
Required
R
ON
Filter
INTERNAL
RESET
EXTERNAL
RESET
0.01µF
1MΩ
WATCHDOG
ILLEGALOPCODE 5)
LVD RESET
PULSE
GENERATOR
1)
Figure 113. RESET pin protection when LVD is disabled.
V
ST72XXX
DD
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01µF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE 5)
Required
Note 1:
– The reset network protects the device against parasitic resets.
– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go
below the V max. level specified in Section 13.11.1 on page 172. Otherwise the reset will not be taken into account
IL
internally.
– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-
sure that the current sunk on the RESET pin is less than the absolute maximum value specified for I
Section 13.2.2 on page 153.
in
INJ(RESET)
Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down
capacitor is required to filter noise on the reset line.
Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET
pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power
consumption of the MCU).
Note 4: Tips when using the LVD:
– 1. Check that all recommendations related to the reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and
AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.
In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to 20µF capacitor.”
Note 5: Please refer to “Illegal Opcode Reset” on page 149 for more details on illegal opcode reset conditions.
173/191
ST72340, ST72344, ST72345
13.12 COMMUNICATION INTERFACE CHARACTERISTICS
2
13.12.1 I C and I²C3SNS Interfaces
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
Subject to general operating conditions for V
,
DD
2
(SDAI and SCLI). The ST7 I C and I2C3SNS inter-
f
, and T unless otherwise specified.
OSC
A
faces meet the electrical and timing requirements
2
of the Standard I C communication protocol.
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
I²C SCL frequency
I²C3SNS SCL frequency
Conditions
Min
Max
400
400
Unit
kHz
kHz
1)
f
f
V
=4 MHz to 8 MHz
= 2.7V to 5.5V
,
SCL
CPU
f
DD
SCL3SNS
Note:
2
1. The I C and I2C3SNS interfaces will not function below the minimum clock speed of 4 MHz.
The following table gives the values to be written in
2
the I2CCCR register to obtain the required I C
SCL line frequency.
2
Table 29. SCL Frequency Table (Multimaster I C Interface)
I2CCCR Value
f
=4 MHz.
f
=8 MHz.
CPU
CPU
f
SCL
V
= 3.3 V
V
= 5 V
V
= 3.3 V
V
= 5 V
DD
DD
DD
DD
R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ R =3.3kΩ R =4.7kΩ
P
P
P
P
P
P
P
P
400
300
200
100
50
NA
NA
NA
NA
NA
NA
NA
NA
84h
86h
8Ah
25h
4Bh
FFh
84h
86h
8Ah
24h
4Ch
FFh
84h
85h
8Bh
28h
53h
FFh
84h
87h
8Ch
28h
54h
FFh
84h
11h
25h
60h
84h
10h
24h
5Fh
84h
11h
25h
60h
84h
11h
26h
62h
20
Legend:
R = External pull-up resistance
P
2
f
= I C speed
SCL
NA = Not achievable
Note:
– For speeds around 200 kHz, achieved speed can have ±5% tolerance
– For other speed ranges, achieved speed can have ±2% tolerance
The above variations depend on the accuracy of the external components used.
174/191
ST72340, ST72344, ST72345
13.13 10-BIT ADC CHARACTERISTICS
T = -40°C to 85°C, unless otherwise specified
A
ADC Accuracy
1)2)
3)
Symbol
Parameter
Total unadjusted error
Conditions
Typ
4
Max
8
Unit
|E |
T
f
f
R
=8 MHz,
=4 MHz
< 10kΩ,
CPU
ADC
|E |
Offset error
-1
-2
3
-2
-4
6
O
LSB
|E |
Gain Error
AIN
G
V
= 2.7V to 5.5V
DD
|E |
Differential linearity error
D
Note:
1. Data based on characterization results over the whole temperature range.
2. ADC accuracy vs negative injection current: Injecting negative current on any of the analog input pins may reduce the
accuracy of the conversion being performed on another analog input.
The effect of negative injection current on robust pins is specified in Section 13.11 on page 172
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 13.10 does not affect the ADC
INJ(PIN)
INJ(PIN)
3. Data based on characterization results, monitored in production to guarantee 99.73% within max value from -40°C
to +125°C ( 3σ distribution limits).
Figure 114. ADC Accuracy Characteristics
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
1023
1022
1021
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
7
1021 1022 1023 1024
V
V
DD
SS
175/191
ST72340, ST72344, ST72345
ADC Characteristics
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion voltage range
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
0.4
4
ADC
2)
V
R
V
V
AIN
SSA
DDA
3)
10
kΩ
AIN
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
STAB
4)
t
0
µs
3.5
f
=8MHz, f
=4MHz
CPU
ADC
t
- Sample capacitor loading time
- Hold conversion time
4
10
ADC
ADC
1/f
ADC
Analog Part
Digital Part
1
I
mA
0.2
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refers to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
Figure 115. Typical A/D Converter Application
V
DD
ST72XXX
V
T
0.6V
R
2kΩ(max)
AIN
AINx
10-Bit A/D
V
AIN
Conversion
C
V
0.6V
AIN
T
I
C
ADC
6pF
L
1µA
Notes:
1. C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
2. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization time and
AIN
AIN
decreased to allow the use of a larger serial resistor (R
.
AIN)
176/191
ST72340, ST72344, ST72345
14 PACKAGE CHARACTERISTICS
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
These packages have a Lead-free second level in-
terconnect. The category of second Level Inter-
connect is marked on the package and on the in-
ner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
14.1 PACKAGE MECHANICAL DATA
Figure 116. 32-Pin Low Profile Quad Flat Package (7x7)
1)
mm
inches
Dim.
D
D1
Min Typ Max Min Typ Max
A
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09 0.20 0.004 0.008
e
D
9.00
7.00
9.00
7.00
0.80
3.5°
0.354
0.276
0.354
0.276
0.031
3.5°
E1
E
D1
E
b
E1
e
c
L1
θ
0°
7°
0°
7°
L
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
32
h
L1
N
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
177/191
ST72340, ST72344, ST72345
PACKAGE CHARACTERISTICS (Cont’d)
Figure 117. 40-Lead Very thin Fine pitch Quad Flat No-Lead Package
A
SEATING
1)
A3
mm
inches
PLANE
Dim.
A1
Min Typ Max Min Typ Max
D
A
0.80 0.90 1.00 0.031 0.035 0.039
A1
A2
A3
b
0.02 0.05
0.65 1.00
0.20
0.001 0.002
0.026 0.039
0.008
0.18 0.25 0.30 0.007 0.010 0.012
5.85 6.00 6.15 0.230 0.236 0.242
2.75 2.9 3.05 0.108 0.114 0.120
D
D2
D2
E
5.85
2.75 2.9 3.05 0.108 0.114 0.120
0.50 0.020
6
6.15 0.230 0.236 0.242
E2
E
E2
e
PIN #1 ID TYPE C
RADIUS
L
0.30 0.40 0.50 0.012 0.016 0.020
2
1
Number of Pins
N
40
Note 1. Values in inches are converted from mm
and rounded to 3 decimal digits.
L
e
b
Figure 118. 44-Pin Low Profile Quad Flat Package
1)
mm
inches
Dim.
A
D
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1 0.05
0.15 0.002
A1
b
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.30 0.37 0.45 0.012 0.015 0.018
0.09
0.20 0.004 0.000 0.008
D
12.00
10.00
12.00
10.00
0.80
0.472
0.394
0.472
0.394
0.031
D1
E
e
E1
E
E1
e
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
44
c
L1
L1
L
h
N
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
178/191
ST72340, ST72344, ST72345
PACKAGE CHARACTERISTICS (Cont’d)
Figure 119. 48-Pin Low profile Quad Flat Package
1)
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
E1
E
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
48
L
θ
L1
N
Note 1. Values in inches are converted from
mm and rounded to 3 decimal digits.
179/191
ST72340, ST72344, ST72345
PACKAGE CHARACTERISTICS (Cont’d)
Table 30. THERMAL CHARACTERISTICS
3)
Symbol
Ratings
Value
60
Unit
°C/W
°C
LQFP32
R
Package thermal resistance (junction to ambient) LQFP44
LQFP48
54
thJA
Jmax
Dmax
73
1)
T
Maximum junction temperature
150
415
460
340
LQFP32
2)
P
Power dissipation
LQFP44
LQFP48
mW
Notes:
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula P = (T -T ) / R .
thJA
D
J
A
The power dissipation of an application can be defined by the user with the formula: P =P +P
where P
is the
D
INT
PORT
INT
chip internal power (I x V ) and P
is the port power dissipation depending on the ports used in the application.
DD
DD
PORT
3. Values given for a 4-layer board. P
computed for T = 125°C.
A
Dmax
180/191
ST72340, ST72344, ST72345
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (FASTROM).
ST72F34x FLASH devices are shipped to custom-
ers with a default content (FFh). This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes.
ST7P234x devices are Factory Advanced Service
Technique ROM (FASTROM) versions: they are
factory-programmed XFlash devices.
15.1 OPTION BYTES
The four option bytes allow the hardware configu-
ration of the microcontroller to be selected.
OPT3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
The option bytes can be accessed only in pro-
gramming mode (for example using a standard
ST7 programming tool).
Sector 0 Size
SEC1
SEC0
0.5k
1k
0
0
1
1
0
1
0
1
OPTION BYTE 0
2k
OPT7 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
4k
OPT1 = FMP_R Read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
Erasing the option bytes when the FMP_R option
is selected will cause the whole memory to be
erased first and the device can be reprogrammed.
Refer to the ST7 Flash Programming Reference
Manual and Section 4.5 on page 17 for more de-
tails
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
0: Read-out protection off
1: Read-out protection on
OPT5:4 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in Table 31.
OPT0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
Table 31. LVD Threshold Configuration
Configuration
LVD1 LVD0
1
1
0
0
1
0
1
0
LVD Off
1: Write protection on
Highest Voltage Threshold (∼4.1V)
Medium Voltage Threshold (∼3.5V)
Lowest Voltage Threshold (∼2.8V)
OPTION BYTE 0
OPTION BYTE 1
7
0
7
0
WDG WDG
HALT SW
FMP FMP RST
OSCRANGE
2:0
DIV2 PLL PLL
EN x4x8 OFF
LVD1 LVD0 SEC1 SEC0
OSC
0
R
W
C
Default
Value
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
181/191
ST72340, ST72344, ST72345
OPTION BYTES (Cont’d)
OPTION BYTE 1
OPT7 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
inserted during the RESET phase and when exit-
ing HALT mode. For resonator oscillators, it is ad-
vised to select 4096 due to the long crystal stabili-
zation time.
OPT2 = DIV2EN PLL Divide by 2 enable
0: PLL division by 2 enabled
1: PLL division by 2 disabled
Note: DIV2EN must be kept disabled when PLLx4
is enabled
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT1 = PLLx4x8 PLL Factor selection
0: PLLx4
1: PLLx8
OPT6:4 = OSCRANGE[2:0] Oscillator range
When the internal RC oscillator is not selected
(Option OSC=1), these option bits select the range
of the resonator oscillator current source or the ex-
ternal clock source.
OPT0 = PLLOFF PLL disable
0: PLL enabled
1: PLL disabled (by-passed)
OSCRANGE
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
These option bits must be configured as described
in Table 32 depending on the voltage range and
the expected CPU frequency
LP
1~2MHz
2~4MHz
4~8MHz
8~16MHz
Typ.
MP
MS
HS
frequency
range with
Resonator
Table 32. List of valid option combinations
Option Bits
Target
Ratio
Reserved
V
DIV2
EN
PLL
OFF
PLL
x4x8
0
1
1
DD
1)
x4
2.7V - 3.65V
3.3V - 5.5V
x
0
1
0
0
0
External Clock
x4
x8
Note:
OPT3 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
1. For a target ratio of x4 between 3.3V - 3.65V,
this is the recommended configuration.
182/191
ST72340, ST72344, ST72345
OPTION BYTES (Cont’d)
OPTION BYTE 2
OPTION BYTE 3
OPT7:0 = Reserved. Must be kept at 1.
OPT7:6= PKG1:0 Package selection
These option bits select the package.
Version
Selected Package
LQFP32
PKG 1 PKG 0
K
S
C
0
0
1
0
1
x
LQFP44
LQFP48
OPT5 = I2C3S I2C3SNS selection
0: I2C3SNS selected
1: I2C3SNS not selected
OPT4:0 = Reserved. Must be kept at 1.
OPTION BYTE 2
OPTION BYTE 3
7
0
7
0
Reserved
PKG1 PKG0 I2C3S
Reserved
1
Default
Value
1
1
1
1
1
1
1
1
x
x
x
1
1
1
1
183/191
ST72340, ST72344, ST72345
15.2 DEVICE ORDERING INFORMATION
Table 33. Supported part numbers
Program
Memory
(Bytes)
Data
EEPROM
(Bytes)
RAM
(Bytes)
Temp.
Range
Part Number
Peripherals
Package
ST72F340K2T6
ST72F340S2T6
ST72F340K4T6
ST72F340S4T6
ST72F344K2T6
ST72F344S2T6
ST72F344K4T6
ST72F344S4T6
LQFP32
LQFP44
LQFP32
LQFP44
LQFP32
LQFP44
LQFP32
LQFP44
8K FLASH
16K FLASH
8K FLASH
16K FLASH
512
1K
Common peripherals
Common peripherals
+
10-bit ADC,
int high-accuracy 1MHz RC
512
1K
256
-40°C to 85°C
Common peripherals
+
I²C3SNS
ST72F345C4T6
16K FLASH
1K
LQFP48
10-bit ADC,
int high-accuracy 1MHz RC
Contact ST sales office for product availability
184/191
ST72340, ST72344, ST72345
ST7234x FASTROM MICROCONTROLLER OPTION LIST
(Last update: October 2006)
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------------------------- ---------------------------------------------------
---------------------------------
FASTROM DEVICE:
---------------------------------
|
|
|
8K
16K
|
--------------------------------------------------- ---------------------------------------------------
LQFP32
LQFP44
LQFP48
|
|
|
[ ] ST72P344K4T
[ ] ST72P344S4T
[ ] ST72P345C4T
|
|
|
[ ] ST72P344K2T
[ ] ST72P344S2T
Conditioning for LQFP (check only one option): [ ] Tape & Reel
[ ] Tube
Version/ Temperature range (please refer to datasheet for specific sales conditions):
[ ] 0°C to +70°C
[ ] -10°C to +85°C
[ ] -40°C to +85°C
Special Marking:
[ ] No
[ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
LQFP32, LQFP48:
LQFP44:
7 char. max "_ _ _ _ _ _ _ "
10 char. max "_ _ _ _ _ _ _ _ _ _"
Clock Source Selection:
[ ] External resonator or quartz
[ ] Internal RC Oscillator
[ ] External Clock:
[ ] LP: Low power (1 to 2 MHz)
[ ] MP: Medium power (2 to 4 MHz)
[ ] MS: Medium speed (4 to 8 MHz)
[ ] HS: High speed (8 to 16 MHz)
PLL:
[ ] Disabled
[ ] Enabled
[ ] PLL x 4 (*)
[ ] PLL x 8
DIV2:
[ ] Disabled
[ ] Disabled
[ ] Enabled (*)
LVD Reset:
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
[ ] 4096 cycles
Reset delay:
[ ] 256 cycles
Watchdog Selection:
[ ] Software Activation
[ ] Disabled
[ ] Hardware Activation
[ ] Enabled
Watchdog Reset on Halt:
Readout Protection:
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
FLASH Write Protection (**):
FLASH Sector 0 size (**):
I2C3SNS (for ST72F345 only):
[ ] 0.5K
[ ] 1K
[ ]2K
[ ] 4K
[ ] Disabled
[ ] Enabled
(*) DIV2 and PLLx4 cannot be enabled at the same time
(**) not available on first silicon version with waiver (contact ST local marketing)
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date:
Signature:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
185/191
ST72340, ST72344, ST72345
15.3 DEVELOPMENT TOOLS
Development tools for the ST7 microcontrollers in-
clude a complete range of hardware systems and
software tools from STMicroelectronics and third-
party tool suppliers. The range of tools includes
solutions to help you evaluate microcontroller pe-
ripherals, develop and debug your application, and
program your microcontrollers.
RLink in-circuit debugger/programmer. These
tools are supported by the ST7 Toolset from
STMicroelectronics, which includes the STVD7 in-
tegrated development environment (IDE) with
high-level language debugger, editor, project man-
ager and integrated programming interface.
15.3.3 Programming tools
15.3.1 Starter kits
During the development cycle, the ST7-EMU3 se-
ries emulators and the RLink provide in-circuit
programming capability for programming the Flash
microcontroller on your application board.
ST offers complete, affordable starter kits. Starter
kits are complete, affordable hardware/software
tool packages that include features and samples
to help you quickly start developing your applica-
tion.
ST also provides a low-cost dedicated in-circuit
programmer, the ST7-STICK, as well as ST7
Socket Boards which provide all the sockets re-
quired for programming any of the devices in a
specific ST7 sub-family on a platform that can be
used with any tool with in-circuit programming ca-
pability for ST7.
15.3.2 Development and debugging tools
Application development for ST7 is supported by
fully optimizing C Compilers and the ST7 Assem-
bler-Linker toolchain, which are all seamlessly in-
tegrated in the ST7 integrated development envi-
ronments in order to facilitate the debugging and
fine-tuning of your application. The Cosmic C
Compiler is available in a free version that outputs
up to 16KBytes of code.
For production programming of ST7 devices, ST’s
third-party tool partners also provide a complete
range of gang and automated programming solu-
tions, which are ready to integrate into your pro-
duction environment.
The range of hardware tools includes full-featured
ST7-EMU3 series emulators and the low-cost
15.3.4 Order codes for ST72F34x development tools
Table 34. Development tool order codes
Programming Tool
Dedicated programmer
In-circuit debugger/
MCU
Starter kit
Emulator
programmer
ST72F340
ST72F344
ST72F345
2)
3)5)
STX-RLINK
ST7-STICK
ST7SB20J/xx
ST7SB40-QP48/xx
1)
ST72F34x-SK/RAIS
ST7MDT40-EMU3
3)4)
3)6)
Notes:
1. USB connection to PC
2. RLink with ST7 tool set
3. Add suffix /EU, /UK or /US for the power supply for your region
4. Parallel port connection to PC
5. Only available for LQFP32 and LQFP44 packages
6. Only available for LQFP48 package
For additional ordering codes for spare parts and
accessories, refer to the online product selector at
www.st.com/mcu.
186/191
ST72340, ST72344, ST72345
16 KNOWN LIMITATIONS
16.1 External interrupt missed
LD A,#01
LD sema,A
LD A,PFDR
AND A,#02
; set the semaphore to '1'
To avoid any risk if generating a parasitic interrupt,
the edge detector is automatically disabled for one
clock cycle during an access to either DDR and
OR. Any input signal edge during this period will
not be detected and will not generate an interrupt.
LD X,A
PxOR/PxDDR
; store the level before writing to
This case can typically occur if the application re-
freshes the port configuration registers at intervals
during runtime.
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
Workaround
The workaround is based on software checking
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the
IRET instruction at the end of the interrupt service
routine).
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A
PxOR/PxDDR
; store the level after writing to
LD A,X
; check for falling edge
cp A,#02
jrne OUT
TNZ Y
But detection of the level change does not make
sure that edge occurs during the critical 1 cycle du-
ration and the interrupt has been missed. This may
lead to occurrence of same interrupt twice (one
hardware and another with software call).
jrne OUT
LD A,sema ; check the semaphore status if
edge is detected
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
CP A,#01
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
There is another possible case i.e. if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
.ext1_rt
; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for for
Port PF1 with falling edge interrupt sensitivity. The
software sequence is given for both cases (global
interrupt disabled/enabled).
SIM
; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to
PxOR/PxDDR
Case 1: Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#$90
187/191
ST72340, ST72344, ST72345
LD PFDDR,A; Write into PFDDR
LD A,#$ff
16.2 Clearing active interrupts outside
interrupt routine
LD PFOR,A
LD A,PFDR
AND A,#$02
; Write to PFOR
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note: clearing the related interrupt mask will not
generate an unwanted reset
LD Y,A
PxDDR
; store the level after writing to PxOR/
; check for falling edge
Concurrent interrupt context
LD A,X
The symptom does not occur when the interrupts
are handled normally, i.e.
cp A,#$02
jrne OUT
TNZ Y
when:
– The interrupt flag is cleared within its own inter-
rupt routine
jrne OUT
LD A,#$01
– The interrupt flag is cleared within any interrupt
routine
LD sema,A ; set the semaphore to '1' if edge is
detected
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
RIM
; reset the interrupt mask
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
Perform SIM and RIM operation before and after
resetting an active interrupt request.
call call_routine; call the interrupt routine
RIM
Example:
SIM
OUT:
RIM
reset interrupt flag
RIM
JP while_loop
.call_routine ; entry to call_routine
PUSH A
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
PUSH X
PUSH CC
when:
.ext1_rt
; entry to interrupt routine
– The interrupt flag is cleared within its own inter-
rupt routine
LD A,#$00
LD sema,A
IRET
– The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
16.1.1 Unexpected Reset Fetch
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
PUSH CC
SIM
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
reset interrupt flag
POP CC
188/191
ST72340, ST72344, ST72345
16.3 16-bit Timer PWM Mode
16.5 In-Application Programming
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
Not available on the first silicon revision currently
in production (rev Z). This limitation will be correct-
ed on the next silicon revision. Refer to Table 35
Silicon revision identification.
16.6 Programming of EEPROM data
Description
16.4 SCI Wrong Break duration
Description
In user mode, when programming EEPROM data
memory, the read access to the program memory
between E000h and FFFFh can be corrupted.
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
Impact on application
The EEPROM programming routine must be locat-
ed outside this program memory area.
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1
Any access to the interrupt vector table can result
in an unexpected code being executed, so the in-
terrupts must be masked.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Workaround
The sequence to program the EEPROM data (re-
fer to Section 5.3 on page 19) must be executed
within C000h-DFFFh area or from the RAM. It is as
follows:
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy of 19200 baud (f
BRR=0xC9), the wrong break duration occurrence
is around 1%.
=8MHz and SCI-
CPU
set E2LAT bit
write up to 32 bytes in E2PROM area
SIM ; to disable the interrupts
set E2PGM bit
Workaround
wait for E2PGM=0
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
RIM ; to enable the interrupts
return to the program memory
16.7 Flash Write/Erase Protection
Not available on the first silicon revision currently
in production (rev Z). This limitation will be correct-
ed on the next silicon revision. Refer to Table 35
Silicon revision identification.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
Table 35. Silicon revision identification
Trace code
marked on device
internal sales types
on box label
Device
Status
72F344xxxx$x2
72F345xxxx$x2
In Production
“xxxxxxxxZ”
ST72F344xxxx
ST72F345xxxx
72F344xxxx$x4
72F345xxxx$x4
Under qualification
“xxxxxxxxX”
189/191
ST72340, ST72344, ST72345
17 REVISION HISTORY
Date
Revision
Main changes
29-April-2006
1
First release on internet
Removed references to BGA56 and QFN40 packages
TQFP package naming changed to LQFP (Low-profile Quad Flat)
Changed number of I/O ports on first page
PDVD (Power Down Voltage Detector) replaced by AVD (Auxiliary Voltage Detector)
Modified note 3 to Table 2 on page 12
Added PF4 to Figure 3 on page 6 and Figure 4 on page 7
“MEMORY ACCESS” on page 19
Modified Figure 8, Figure 9 on page 20 and Figure 10 on page 21
Changed RCCR table in Section 7.2 on page 29 (f =1MHz)
RC
References to PDVDF, PDVDIE corrected to AVDF, AVDIE: Section 7.5.2 on page 34
Current characteristics Section 13.2.2 on page 153 updated
General operating conditions table updated, Section 13.3.1 on page 154
Data updated in Section 13.3.2 on page 154, note replaced
Table modified in Section 13.3.3 on page 155
Notes adjusted for table in Section 13.4 on page 156
Modified Section 13.5 on page 156 (for V =5V)
DD
Table in Section 13.6.1 on page 157 modified
Updated Section 13.6.2 on page 159
23-Oct-2006
2
Added Section 13.7.2 and Figure 93 on page 160
Table in Section 13.8.2 on page 163 modified
Absolute maximum ratings and electrical sensitivity table updated, Section 13.9.3 on
page 165
Added note 1 to V and V in Section 13.10.1 on page 166
IL
IH
Table in Section 13.10.2 on page 167 modified (for V = 3.3V and V =2.7V)
DD
DD
Modified graphs in Section 13.10.2 on page 167
updated in Section 13.11 on page 172
t
g(RSTL)in
Updated Table 29 on page 174
Updated Table 30 on page 180
Modified default values for option byte 2 and 3 on page 183
Added option list on page 185
Added “DEVELOPMENT TOOLS” on page 186
Added known limitations: “In-Application Programming” on page 189, “Programming
of EEPROM data” on page 189, and “Flash Write/Erase Protection” on page 189
Modified Section 16.6 on page 189
Changed status of the document (datasheet instead of preliminary data)
190/191
ST72340, ST72344, ST72345
Notes:
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
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191/191
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