ST72F63BK4M1_技术文档

ST7263B

LOW SPEED USB 8-BIT MCU FAMILY WITH FLASH/ROM,

UP TO 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I²C

■ Memories

– 4, 8 or 16 Kbytes Program Memory: High

Density Flash (HDFlash) or ROM with Read-

out and Write Protection

– In-Application Programming (IAP) and In-Cir-

cuit programming (ICP) for HDFlash devices

– 384 or 512 bytes RAM memory (128-byte

stack)

PSDIP32

■ Clock, Reset and Supply Management

– Run, Wait, Slow and Halt CPU modes

– 12 or 24 MHz Oscillator

– RAM Retention mode

– Optional Low Voltage Detector (LVD)

■ USB (Universal Serial Bus) Interface

SO34 (Shrink)

■ 2 Communication Interfaces

– DMA for low speed applications compliant

with USB 1.5 Mbs (version 1.1) and HID spec-

ifications (version 1.0)

– Integrated 3.3 V voltage regulator and trans-

ceivers

– Suspend and Resume operations

– 3 Endpoints with programmable In/Out config-

uration

– Asynchronous Serial Communications Inter-

face (on K4 and K2 versions only)

– I²C Multi Master Interface up to 400 kHz

(on K4 versions only)

■ 1 Analog Peripheral

– 8-bit A/D Converter (ADC) with 8 channels

■ Instruction Set

■ 19 I/O Ports

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

– 8 high sink I/Os (10 mA at 1.3 V)

– 2 very high sink true open drain I/Os (25 mA

at 1.5 V)

– 8 lines individually programmable as interrupt

inputs

■ Development Tools

■ 2 Timers

– Versatile Development Tools (under Win-

dows) including assembler, linker, C-compil-

er, archiver, source level debugger, software

library, hardware emulator, programming

boards and gang programmers

– Programmable Watchdog

– 16-bit Timer with 2 Input Captures, 2 Output

Compares, PWM output and clock input

Table 1. Device Summary

ST72F63BK4

Features

ST7263BK2

ST7263BK1

16K

8K

4K

Program Memory -bytes-

RAM (stack) - bytes

(Flash or FASTROM)

(Flash, ROM or FASTROM)

512 (128)

384 (128)

Watchdog timer, 16-bit tim-

er, SCI, I²C, ADC, USB

Watchdog timer,

16-bit timer, SCI, ADC, USB

Watchdog, 16-bit timer, ADC,

USB

Peripherals

Operating Supply

CPU frequency

Operating temperature

Packages

4.0 V to 5.5 V

8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)

0 °C to +70 °C

SO34/SDIP32

Rev. 1.5

April 2003

1/132

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 INTERRUPT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.3 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.4 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.3 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.4 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11.5 I²C BUS INTERFACE (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

132

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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Table of Contents

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

13.10COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 116

13.118-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 124

15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

16.2 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 130

17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 130.

3/132

ST7263B

1 INTRODUCTION

The ST7263B Microcontrollers form a sub-family

of the ST7 MCUs dedicated to USB applications.

The devices are based on an industry-standard 8-

bit core and feature an enhanced instruction set.

They operate at a 24 MHz or 12 MHz oscillator fre-

quency. Under software control, the ST7263B

MCUs may be placed in either Wait or Halt modes,

thus reducing power consumption. The enhanced

instruction set and addressing modes afford real

programming potential. In addition to standard 8-

bit data management, the ST7263B MCUs feature

true bit manipulation, 8x8 unsigned multiplication

and indirect addressing modes. The devices in-

clude an ST7 Core, up to 16 Kbytes of program

memory, up to 512 bytes of RAM, 19 I/O lines and

the following on-chip peripherals:

– Industry standard asynchronous SCI serial inter-

face (not on all products - see Table 1 Device

Summary)

– Watchdog

– 16-bit Timer featuring an External clock input, 2

Input Captures, 2 Output Compares with Pulse

Generator capabilities

– Fast I²C Multi Master interface (not on all prod-

ucts - see device summary)

– Low voltage reset (LVD) ensuring proper power-

on or power-off of the device

The ST7263B devices are ROM versions.

The ST72P63B devices are Factory Advanced

Service Technique ROM (FASTROM) versions:

they are factory-programmed and are not repro-

grammable.

– USB low speed interface with 3 endpoints with

programmable in/out configuration using the

DMA architecture with embedded 3.3V voltage

regulator and transceivers (no external compo-

nents are needed).

The ST72F63B devices are Flash versions. They

support programming in IAP mode (In-application

programming) via the on-chip USB interface.

– 8-bit Analog-to-Digital converter (ADC) with 8

multiplexed analog inputs

Figure 1. General Block Diagram

INTERNAL

CLOCK

OSC/3

OSCIN

OSCILLATOR

OSCOUT

I²C*

OSC/4 or OSC/2

(for USB)

PA[7:0]

V

PORT A

(8 bits)

DD

POWER

V

SUPPLY

WATCHDOG

CONTROL

SS

16-BIT TIMER

PORT B

PB[7:0]

RESET

(8 bits)

ADC

8-BIT CORE

ALU

PORT C

LVD

PC[2:0]

(3 bits)

SCI*

(UART)

USB DMA

USBDP

USBDM

USBVCC

V

/TEST

USB SIE

PROGRAM

MEMORY

(4K/8K/16K Bytes)

PP

V

DDA

V

SSA

RAM

(384/512 Bytes)

* Not on all products (refer to Table 1: Device Summary)

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ST7263B

2 PIN DESCRIPTION

Figure 2. 34-Pin SO Package Pinout

V

DDA

34

33

32

V

DD

1

USBVCC

USBDM

OSCOUT

OSCIN

2

3

USBDP

V

31

30

29

28

27

26

25

24

23

22

21

20

19

18

4

SS

V

PC2/USBOE

PC1/TDO

PC0/RDI

RESET

SSA

5

PA0/MCO

6

PA1(25mA)/SDA/ICCDATA

7

NC

8

NC

AIN7/IT8PB7(10mA)

AIN6/PB6/IT7(10mA)

9

NC

10

11

12

PA2(25mA)/SCL/ICCCLK

V

/TEST

PA3/EXTCLK

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PP

AIN5/IT6/PB5(10mA)

AIN4/IT5/PB4(10mA)

AIN3/PB3(10mA)

AIN2/PB2(10mA)

AIN1/PB1(10mA)

13

14

PA6/OCMP1/IT3

PA7/OCMP2/IT4

PB0(10mA)/AIN0

15

16

17

* V on Flash versions only

PP

Figure 3. 32-Pin SDIP Package Pinout

V

DDA

DD

1

32

USBVCC

OSCOUT

OSCIN

2

3

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

USBDM

USBDP

V

4

SS

V

PC2/USBOE

PC1/TDO

PC0/RDI

RESET

5

SSA

PA0/MCO

6

PA1(25mA)/SDA/ICCDATA

7

NC

8

AIN7/IT8/PB7(10mA)

AIN6/IT7/PB6(10mA)

NC

9

PA2(25mA)/SCL/ICCCLK

10

11

12

13

14

15

16

V

/TEST*

PA3/EXTCLK

PP

AIN5/IT6/PB5(10mA)

AIN4/IT5/PB4(10mA)

AIN3/PB3(10mA)

AIN2/PB2(10mA)

AIN1/PB1/(10mA)

PA4/ICAP1/IT1

PA5/ICAP2/IT2

PA6/COMP1/IT3

PA7/COMP2/IT4

PB0(10mA)/AIN0

* V on Flash versions only

PP

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ST7263B

PIN DESCRIPTION (Cont’d)

RESET (see Note 1): Bidirectional. This active low

signal forces the initialization of the MCU. This

event is the top priority non maskable interrupt.

This pin is switched low when the Watchdog is trig-

Alternate Functions: Several pins of the I/O ports

assume software programmable alternate func-

tions as shown in the pin description.

Note 1: Adding two 100 nF decoupling capacitors

on the Reset pin (respectively connected to V_DD

and V_SS) will significantly improve product electro-

magnetic susceptibility performance.

gered or the V is low. It can be used to reset ex-

DD

ternal peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin.

These pins connect a parallel-resonant crystal, or

an external source, to the on-chip oscillator.

Note 2: To enhance the reliability of operation, it is

recommended that V_DDAand V_DDbe connected to-

gether on the application board. This also applies

V

/V

(see Note 2): Main Power Supply and

DD SS

Ground voltages.

to V_SSAand V .

SS

V

/V (see Note 2): Power Supply and

DDA SSA

Ground voltages for analog peripherals.

Table 2. Device Pin Description

Pin n°

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

Alternate Function

1

2

3

4

5

6

7

8

--

9

1

2

3

4

5

6

7

8

9

V

S

Power supply voltage (4V - 5.5V)

Oscillator output

DD

OSCOUT

OSCIN

O

I

Oscillator input

V

S

Digital ground

SS

PC2/USBOE

PC1/TDO

PC0/RDI

RESET

I/O

--

C

X

Port C2

Port C1

Port C0

Reset

USB Output Enable

T

X

SCI Transmit Data Output*

SCI Receive Data Input*

X

NC

Not connected

Port B7

Port B6

10 PB7/AIN7/IT8

I/O

S

C

10mA

X

ADC analog input 7

ADC analog input 6

T

10 11 PB6/AIN6/IT7

11 12 /TEST

V

Programming supply

PP

12 13 PB5/AIN5/IT6

13 14 PB4/AIN4/IT5

14 15 PB3/AIN3

I/O

C

10mA

X

Port B5

Port B4

Port B3

Port B2

Port B1

Port B0

Port A7

Port A6

Port A5

Port A4

ADC analog input 5

T

ADC analog input 4

ADC analog input 3

ADC analog input 2

ADC analog input 1

ADC Analog Input 0

Timer Output Compare 2

Timer Output Compare 1

Timer Input Capture 2

Timer Input Capture 1

15 16 PB2/AIN2

16 17 PB1/AIN1

17 18 PB0/AIN0

18 19 PA7/OCMP2/IT4

19 20 PA6/OCMP1/IT3

20 21 PA5/ICAP2/IT2

21 22 PA4/ICAP1/IT1

C

X

T

C

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ST7263B

Pin n°

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

Alternate Function

22 23 PA3/EXTCLK

23 24 PA2/SCL/ICCCLK

-- 25 NC

I/O

--

C

X

Port A3

Timer External Clock

T

C

25mA

X

T

Port A2

I²C serial clock*, ICC Clock

T

Not connected

Port A1

24 26 NC

--

25 27 NC

--

26 28 PA1/SDA/ICCDATA

27 29 PA0/MCO

I/O

S

C

25mA

T

I²C serial data*, ICC Data

Main Clock Output

C

X

Port A0

T

28 30

V

Analog ground

SSA

29 31 USBDP

30 32 USBDM

31 33 USBVCC

I/O

O

USB bidirectional data (data +)

USB bidirectional data (data -)

USB power supply

32 34

V

S

Analog supply voltage

DDA

Note (*): if the peripheral is present on the device (see Table 1, "Device Summary")

Legend / Abbreviations for Figure 2 and Table 2:

Type:

I = input, O = output, S = supply

In/Output level: C = CMOS 0.3V /0.7V with input trigger

T

DD

Output level:

10mA = 10mA high sink (on N-buffer only)

25mA = 25mA very high sink (on N-buffer only)

Port and control configuration:

– Input:

float = floating, wpu = weak pull-up, int = interrupt, ana = analog

OD = open drain, PP = push-pull, T = True open drain

– Output:

Refer to “I/O PORTS” on page 25 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is

under reset state.

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ST7263B

3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of ad-

dressing 64 Kbytes of memories and I/O registers.

The highest address bytes contain the user reset

and interrupt vectors.

The available memory locations consist of up to

512 bytes of RAM including 64 bytes of register lo-

cations, and up to 16K bytes of user program

memory in which the upper 32 bytes are reserved

for interrupt vectors. The RAM space includes up

to 128 bytes for the stack from 0100h to 017Fh.

IMPORTANT: Memory locations noted “Re-

served” must never be accessed. Accessing a re-

served area can have unpredictable effects on the

device.

Figure 4. Memory Map

0000h

0040h

HW Registers

Short Addressing

RAM (192 bytes)

(See Table 4)

003Fh

0040h

00FFh

0100h

RAM

(384/512 Bytes)

Stack

(128 Bytes)

017Fh

01BF/023Fh

01C0/0240h

0180h

16-bit Addressing

Reserved

RAM

BFFFh

C000h

01BF/023Fh

C000h

Program Memory*

(4/8/16 KBytes)

16 KBytes

FFDFh

FFE0h

Interrupt & Reset Vectors

(See Table 3)

E000h

FFFFh

8 KBytes

F000h

4 KBytes

FFDFh

* Program memory and RAM sizes are product dependent (see Table 1, "Device Summary")

Table 3. Interrupt Vector Map

Vector Address

Description

Masked by

Remarks

Exit from Halt Mode

FFE0h-FFEDh

FFEEh-FFEFh

FFF0h-FFF1h

FFF2h-FFF3h

FFF4h-FFF5h

FFF6h-FFF7h

Reserved Area

USB Interrupt Vector

SCI Interrupt Vector

I²C Interrupt Vector

I- bit

None

Internal Interrupt

External Interrupt

External Interrupts

Internal Interrupt

CPU Interrupt

No

TIMER Interrupt Vector

IT1 to IT8 Interrupt Vector

No

Yes

No

FFF8h-FFF9h USB End Suspend Mode Interrupt Vector

FFFAh-FFFBh Flash Start Programming Interrupt Vector

FFFCh-FFFDh

FFFEh-FFFFh

TRAP (software) Interrupt Vector

RESET Vector

Yes

8/132

ST7263B

Table 4. Hardware Register Memory Map

Address

Block

Register Label

Register name

Port A Data Register

Reset Status

Remarks

0000h

0001h

PADR

00h

R/W

Port A

PADDR

Port A Data Direction Register

R/W

0002h

0003h

PBDR

Port B Data Register

00h

R/W

Port B

Port C

PBDDR

Port B Data Direction Register

0004h

0005h

PCDR

Port C Data Register

1111 x000b

R/W

PCDDR

Port C Data Direction Register

0006h

0007h

Reserved (2 Bytes)

0008h

0009h

ITC

ITIFRE

MISCR

Interrupt Register

00h

R/W

MISC

Miscellaneous Register

000Ah

000Bh

ADCDR

ADC Data Register

00h

Read only

R/W

ADC

ADCCSR

ADC control Status register

000Ch

WDG

WDGCR

Watchdog Control Register

7Fh

R/W

000Dh

to

Reserved (4 bytes)

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

TCR2

Timer Control Register 2

00h

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

TCR1

Timer Control Register 1

R/W

TSR

Timer Status Register

Read only

R/W

TIC1HR

TIC1LR

TOC1HR

TOC1LR

TCHR

Timer Input Capture High Register 1

Timer Input Capture Low Register 1

Timer Output Compare High Register 1

Timer Output Compare Low Register 1

Timer Counter High Register

R/W

TIM

Read only

R/W

TCLR

Timer Counter Low Register

TACHR

TACLR

TIC2HR

TIC2LR

TOC2HR

TOC2LR

Timer Alternate Counter High Register

Timer Alternate Counter Low Register

Timer Input Capture High Register 2

Timer Input Capture Low Register 2

Timer Output Compare High Register 2

Timer Output Compare Low Register 2

Read only

R/W

Read only

R/W

0020h

0021h

0022h

0023h

0024h

SCISR

SCI Status Register

SCI Data Register

C0h

Read only

R/W

SCIDR

xxh

1)

SCI

SCIBRR

SCICR1

SCICR2

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

00h

R/W

x000 0000b

00h

R/W

9/132

ST7263B

Address

Block

Register Label

Register name

USB PID Register

Reset Status

Remarks

Read only

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

USBPIDR

x0h

USBDMAR

USBIDR

USB DMA address Register

USB Interrupt/DMA Register

USB Interrupt Status Register

USB Interrupt Mask Register

USB Control Register

xxh

R/W

x0h

USBISTR

00h

USBIMR

00h

USBCTLR

USBDADDR

USBEP0RA

USBEP0RB

USBEP1RA

USBEP1RB

USBEP2RA

USBEP2RB

06h

USB

USB Device Address Register

USB Endpoint 0 Register A

USB Endpoint 0 Register B

USB Endpoint 1 Register A

USB Endpoint 1 Register B

USB Endpoint 2 Register A

USB Endpoint 2 Register B

00h

0000 xxxxb

80h

0000 xxxxb

0032hto

0036h

Reserved (5 bytes)

Reserved (5 Bytes)

0032h

0036h

0037h

0038h

Flash

FCSR

Flash Control /Status Register

Reserved (1 byte)

00h

R/W

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

I2CDR

I²C Data Register

00h

-

R/W

Reserved

I2COAR

I2CCCR

I2CSR2

I2CSR1

I2CCR

I²C (7 Bits) Slave Address Register

I²C Clock Control Register

I²C 2nd Status Register

I²C 1st Status Register

I²C Control Register

00h

R/W

1)

I²C

R/W

Read only

R/W

Note 1. If the peripheral is present on the device (see Table 1, "Device Summary")

10/132

ST7263B

4 FLASH PROGRAM MEMORY

4.1 Introduction

Depending on the overall Flash memory size in the

microcontroller device, there are up to three user

sectors (see Table 5). Each of these sectors can

be erased independently to avoid unnecessary

erasing of the whole Flash memory when only a

partial erasing is required.

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be

electrically erased as a single block or by individu-

al sectors and programmed on a Byte-by-Byte ba-

sis using an external V supply.

PP

The first two sectors have a fixed size of 4 Kbytes

(see Figure 5). They are mapped in the upper part

of the ST7 addressing space so the reset and in-

terrupt vectors are located in Sector 0 (F000h-

FFFFh).

The HDFlash devices can be programmed and

erased off-board (plugged in a programming tool)

or on-board using ICP (In-Circuit Programming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

Table 5. Sectors available in Flash devices

Flash Size (bytes)

Available Sectors

4K

8K

Sector 0

Sectors 0,1

Sectors 0,1, 2

4.2 Main Features

■ Three Flash programming modes:

> 8K

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

4.3.1 Read-out Protection

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

Read-out protection, when selected, makes it im-

possible to extract the memory content from the

microcontroller, thus preventing piracy. Even ST

cannot access the user code.

In flash devices, this protection is removed by re-

programming the option. In this case, the entire

program memory is first automatically erased.

■ ICT (In-Circuit Testing) for downloading and

Read-out protection selection depends on the de-

vice type:

executing user application test patterns in RAM

■ Read-out protection against piracy

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

– In ROM devices it is enabled by mask option

specified in the Option List.

4.3 Structure

The Flash memory is organised in sectors and can

be used for both code and data storage.

Figure 5. Memory Map and Sector Address

4K

8K

10K

16K

24K

32K

48K

60K

FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

SECTOR 2

52 Kbytes

2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes

4 Kbytes

SECTOR 1

SECTOR 0

EFFFh

FFFFh

11/132

ST7263B

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

ICC needs a minimum of 4 and up to 6 pins to be

connected to the programming tool (see Figure 6).

These pins are:

– ICCSEL/V : programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

– RESET: device reset

– V : application board power supply (option-

DD

– V : device power supply ground

al, see Figure 6, Note 3)

SS

Figure 6. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

ICC CONNECTOR

OPTIONAL

(See Note 3)

OPTIONAL

(See Note 4)

HE10 CONNECTOR TYPE

9

7

5

6

3

1

2

10

8

4

APPLICATION

RESET SOURCE

See Note 2

10kΩ

APPLICATION

POWER SUPPLY

C

L2

See Notes 1 and 5

See Note 1

L1

APPLICATION

I/O

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the board, even if an ICC session is not

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the application, isolation such as a serial

resistor has to implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

In all cases the user must ensure that no external

reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS-

CIN pin of the ST7 when the clock is not available

in the application or if the selected clock option is

not programmed in the option byte. ST7 devices

with multi-oscillator capability need to have OSC2

grounded in this case.

2. During the ICC session, the programming tool

must control the RESET pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the appli-

cation RESET circuit in this case. When using a

classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

5. During normal operation, the ICCCLK pin must

be pulled-up, internally or externally, to avoid en-

tering ICC mode unexpectedly during a reset.

12/132

ST7263B

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

mode, choice of communications protocol used to

fetch the data to be stored, etc.). For example, it is

possible to download code from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP

mode can be used to program any of the Flash

sectors except Sector 0, which is write/erase pro-

tected to allow recovery in case errors occur dur-

ing the programming operation.

To perform ICP the microcontroller must be

switched to ICC (In-Circuit Communication) mode

by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully custom-

ized (number of bytes to program, program loca-

tions, or selection serial communication interface

for downloading).

4.6.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

When using an STMicroelectronics or third-party

programming tool that supports ICP and the spe-

cific microcontroller device, the user needs only to

implement the ICP hardware interface on the ap-

plication board (see Figure 6). For more details on

the pin locations, refer to the device pinout de-

scription.

Read/Write

Reset Value: 0000 0000 (00h)

7

0

4.6 IAP (In-Application Programming)

This register is reserved for use by Programming

Tool software. It controls the Flash programming

and erasing operations. For details on customizing

Flash programming methods and In-Circuit Test-

ing, refer to the ST7 Flash Programming Refer-

ence Manual.

This mode uses a BootLoader program previously

stored in Sector 0 by the user (in ICP mode or by

plugging the device in a programming tool).

This mode is fully controlled by user software. This

allows it to be adapted to the user application, (us-

er-defined strategy for entering programming

13/132

ST7263B

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and logic calculations and to manipulate

data.

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

Index Registers (X and Y)

5.2 MAIN FEATURES

In indexed addressing modes, these 8-bit registers

are used to create either effective addresses or

temporary storage areas for data manipulation.

(The Cross-Assembler generates a precede in-

struction (PRE) to indicate that the following in-

struction refers to the Y register.)

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

The Y register is not affected by the interrupt auto-

matic procedures (not pushed to and popped from

the stack).

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

Program Counter (PC)

The program counter is a 16-bit register containing

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not

present in the memory mapping and are accessed

by specific instructions.

Figure 7. CPU Registers

7

0

ACCUMULATOR

RESET VALUE = XXh

7

0

X INDEX REGISTER

Y INDEX REGISTER

RESET VALUE = XXh

7

RESET VALUE = XXh

PCL

PCH

7

8

15

0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

0

1

H I N Z

C

CONDITION CODE REGISTER

RESET VALUE =

8

1

X 1 X X X

0

15

7

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

14/132

ST7263B

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

because the I bit is set by hardware at the start of

the routine and reset by the IRET instruction at the

end of the routine. If the I bit is cleared by software

in the interrupt routine, pending interrupts are

serviced regardless of the priority level of the cur-

rent interrupt routine.

Reset Value: 111x1xxx

7

0

1

H

I

N

Z

C

Bit 2 = N Negative.

The 8-bit Condition Code register contains the in-

terrupt mask and four flags representative of the

result of the instruction just executed. This register

can also be handled by the PUSH and POP in-

structions.

This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It is a copy of the 7

th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

These bits can be individually tested and/or con-

trolled by specific instructions.

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instruction. It is reset by hardware during the

same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-

dicates that the result of the last arithmetic, logical

or data manipulation is zero.

0: The result of the last operation is different from

zero.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in inter-

rupt or by software to disable all interrupts except

the TRAP software interrupt. This bit is cleared by

software.

0: Interrupts are enabled.

1: Interrupts are disabled.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is controlled by the RIM, SIM and IRET in-

structions and is tested by the JRM and JRNM in-

structions.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instructions. It is

also affected by the “bit test and branch”, shift and

rotate instructions.

Note: Interrupts requested while I is set are

latched and can be processed when I is cleared.

By default an interrupt routine is not interruptable

15/132

ST7263B

CPU REGISTERS (Cont’d)

STACK POINTER (SP)

Read/Write

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

Reset Value: 017Fh

15

8

1

0

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH and POP instruc-

tions. In the case of an interrupt, the PCL is stored

at the first location pointed to by the SP. Then the

other registers are stored in the next locations as

shown in Figure 8.

0

7

0

SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is al-

ways pointing to the next free location in the stack.

It is then decremented after data has been pushed

onto the stack and incremented before data is

popped from the stack (see Figure 8).

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-

terrupt five locations in the stack area.

Since the stack is 128 bytes deep, the 9 most sig-

nificant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer contains its reset val-

ue (the SP6 to SP0 bits are set) which is the stack

higher address.

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Figure 8. Stack Manipulation Example

CALL

Subroutine

RET

or RSP

PUSH Y

POP Y

IRET

Interrupt

Event

@ 0100h

SP

Y

CC

A

CC

A

CC

A

X

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

SP

PCH

PCL

PCH

PCL

SP

@ 017Fh

Stack Higher Address = 017Fh

0100h

Stack Lower Address =

16/132

ST7263B

6 RESET AND CLOCK MANAGEMENT

6.1 RESET

The Reset procedure is used to provide an orderly

software start-up or to exit low power modes.

6.1.3 External Reset

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown in Figure 12, the RESET signal must

stay low for a minimum of one and a half CPU

clock cycles.

Three reset modes are provided: a low voltage

(LVD) reset, a watchdog reset and an external re-

set at the RESET pin.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

Figure 9. Low Voltage Detector functional Diagram

An internal circuitry provides a 4096 CPU clock cy-

cle delay from the time that the oscillator becomes

active.

RESET

LOW VOLTAGE

V

DD

DETECTOR

6.1.1 Low Voltage Detector (LVD)

INTERNAL

RESET

Low voltage reset circuitry generates a reset when

V

is:

DD

FROM

WATCHDOG

RESET

■ below V when V is rising,

IT+

DD

■ below V when V is falling.

IT-

DD

Figure 10. Low Voltage Reset Signal Output

During low voltage reset, the RESET pinisheld low,

thus permitting the MCU to reset other devices.

V

IT+

The Low Voltage Detector can be disabled by set-

ting bit 3 of the option byte.

V

IT-

V

DD

6.1.2 Watchdog Reset

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es in the same way as the low voltage reset (Fig-

ure 9).

RESET

Note: Hysteresis (V -V ) = V

IT+ IT-

hys

Figure 11. Temporization timing diagram after an internal Reset

V

IT+

V

DD

Temporization (4096 CPU clock cycles)

$FFFE

Addresses

17/132

ST7263B

RESET (Cont’d)

Figure 12. Reset Timing Diagram

t

DDR

V

DD

OSCIN

t

OXOV

f

CPU

FFFF

FFFE

PC

RESET

4096 CPU

CLOCK

CYCLES

DELAY

WATCHDOG RESET

Note: Refer to Electrical Characteristics for values of t

, t_OXOV, V , V and V

IT+ IT- hys

DDR

18/132

ST7263B

6.2 CLOCK SYSTEM

6.2.1 General Description

source should be used instead of t

tion 6.5 CONTROL TIMING).

Figure 13. External Clock Source Connections

(see Sec-

OXOV

The MCU accepts either a Crystal or Ceramic res-

onator, or an external clock signal to drive the in-

ternal oscillator. The internal clock (f

rived from the external oscillator frequency (f

) is de-

CPU

),

OSC

which is divided by 3 (and by 2 or 4 for USB, de-

pending on the external clock used). The internal

clock is further divided by 2 by setting the SMS bit

in the Miscellaneous Register.

Using the OSC24/12 bit in the option byte, a 12

MHz or a 24 MHz external clock can be used to

provide an internal frequency of either 2, 4 or 8

MHz while maintaining a 6 MHz for the USB (refer

to Figure 15).

OSCOUT

NC

OSCIN

EXTERNAL

CLOCK

The internal clock signal (f

) is also routed to

CPU

the on-chip peripherals. The CPU clock signal

consists of a square wave with a duty cycle of

50%.

Figure 14. Crystal/Ceramic Resonator

The internal oscillator is designed to operate with

an AT-cut parallel resonant quartz or ceramic res-

onator in the frequency range specified for f

.

osc

The circuit shown in Figure 14 is recommended

when using a crystal, and Table 6, "Recommend-

ed Values for 24 MHz Crystal Resonator" lists the

recommended capacitance. The crystal and asso-

ciated components should be mounted as close as

possible to the input pins in order to minimize out-

put distortion and start-up stabilisation time.

OSCIN

OSCOUT

R_P

C

OSCIN

OSCOUT

Table 6. Recommended Values for 24 MHz

Crystal Resonator

Figure 15. Clock Block Diagram

R

20 Ω

56pF

25 Ω

47pF

70 Ω

22pF

SMAX

C

OSCIN

8, 4 or 2 MHz

CPU and

peripherals)

0

1

C

56pF

47pF

22pF

OSCOUT

R_P

1-10 MΩ

%2

%3

Note: R

is the equivalent serial resistor of the

SMAX

crystal (see crystal specification).

SMS

6.2.2 External Clock

An external clock may be applied to the OSCIN in-

put with the OSCOUT pin not connected, as

1

0

6 MHz (USB)

%2

shown on Figure 13. The t

specifications do

24 or

12 MHz

Crystal

OXOV

not apply when using an external clock input. The

equivalent specification of the external clock

%2

OSC24/12

19/132

ST7263B

7 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 7, "Interrupt Mapping" and a non-

maskable software interrupt (TRAP). The Interrupt

processing flowchart is shown in Figure 16.

Interrupts and Low Power Mode

All interrupts allow the processor to leave the Wait

low power mode. Only external and specific men-

tioned interrupts allow the processor to leave the

Halt low power mode (refer to the “Exit from HALT“

column in Table 7, "Interrupt Mapping").

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

External Interrupts

The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5)

can generate an interrupt when a rising edge oc-

curs on this pin. Conversely, the ITl/PAn and ITm/

PBn pins (l=3,4; m= 7,8; n=6,7) can generate an

interrupt when a falling edge occurs on this pin.

When an interrupt has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

Interrupt generation will occur if it is enabled with

the ITiE bit (i=1 to 8) in the ITRFRE register and if

the I bit of the CCR is reset.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

Table 7, "Interrupt Mapping" for vector address-

es).

Peripheral Interrupts

Different peripheral interrupt flags in the status

register are able to cause an interrupt when they

are active if both:

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

– The I bit of the CC register is cleared.

– The corresponding enable bit is set in the control

register.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Clearing an interrupt request is done by one of the

two following operations:

Priority Management

– Writing “0” to the corresponding bit in the status

register.

By default, a servicing interrupt cannot be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

– Accessing the status register while the flag is set

followed by a read or write of an associated reg-

ister.

In the case several interrupts are simultaneously

pending, a hardware priority defines which one will

be serviced first (see Table 7, "Interrupt Map-

ping").

Notes:

1. The clearing sequence resets the internal latch.

A pending interrupt (i.e. waiting to be enabled) will

therefore be lost if the clear sequence is executed.

Non-maskable Software Interrupts

2. All interrupts allow the processor to leave the

Wait low power mode.

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 16.

3. Exit from Halt mode may only be triggered by an

External Interrupt on one of the ITi ports (PA4-PA7

and PB4-PB7), an end suspend mode Interrupt

coming from USB peripheral, or a reset.

20/132

ST7263B

INTERRUPTS (Cont’d)

Figure 16. Interrupt Processing Flowchart

FROM RESET

N

BIT I SET

Y

N

INTERRUPT

Y

FETCH NEXT INSTRUCTION

N

IRET

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

Table 7. Interrupt Mapping

Vector

Exit

from

HALT

Source

Block

Register Priority

N°

Description

Address

Label

Order

RESET

TRAP

FLASH

USB

Reset

yes

no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

Highest

Priority

N/A

Software Interrupt

Flash Start Programming Interrupt

End Suspend Mode

External Interrupts

yes

ISTR

ITRFRE

TIMSR

I²CSR1

I²CSR2

SCISR

ISTR

yes

1

2

ITi

TIMER

Timer Peripheral Interrupts

3

I²C

I²C Peripheral Interrupts

FFF2h-FFF3h

no

Lowest

Priority

4

5

SCI

SCI Peripheral Interrupts

USB Peripheral Interrupts

FFF0h-FFF1h

FFEEh-FFEFh

USB

21/132

ST7263B

INTERRUPTS (Cont’d)

7.1 Interrupt Register

INTERRUPTS REGISTER (ITRFRE)

Address: 0008h

Reset Value: 0000 0000 (00h)

—

Read/Write

If an ITiE bit is set, the corresponding interrupt is

generated when

– a rising edge occurs on the pin PA4/IT1 or PA5/

IT2 or PB4/IT5 or PB5/IT6

7

0

IT8E

IT7E

IT6E

IT5E

IT4E

IT3E

IT2E

IT1E

or

– a falling edge occurs on the pin PA6/IT3 or PA7/

IT4 or PB6/IT7 or PB7/IT8

Bit 7:0 = ITiE (i=1 to 8). Interrupt Enable Control

Bits.

No interrupt is generated elsewhere.

Note: Analog input must be disabled for interrupts

coming from port B.

22/132

ST7263B

8 POWER SAVING MODES

8.1 Introduction

To give a large measure of flexibility to the applica-

tion in terms of power consumption, two main pow-

er saving modes are implemented in the ST7.

Figure 17. HALT Mode Flow Chart

HALT INSTRUCTION

After a RESET, the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

OFF

main oscillator frequency divided by 3 (f

).

CPU

OFF

From Run mode, the different power saving

modes may be selected by setting the relevant

register bits or by calling the specific ST7 software

instruction whose action depends on the oscillator

status.

OFF

CLEARED

8.2 HALT Mode

N

RESET

The MCU consumes the least amount of power in

HALT mode. The HALT mode is entered by exe-

cuting the HALT instruction. The internal oscillator

is then turned off, causing all internal processing to

be stopped, including the operation of the on-chip

peripherals.

N

EXTERNAL

Y

INTERRUPT*

Y

When entering HALT mode, the I bit in the Condi-

tion Code Register is cleared. Thus, all external in-

terrupts (ITi or USB end suspend mode) are al-

lowed and if an interrupt occurs, the CPU clock be-

comes active.

OSCILLATOR

ON

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

SET

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on ITi, an end suspend

mode interrupt coming from USB peripheral, or a

reset. The oscillator is then turned on and a stabi-

lization time is provided before releasing CPU op-

eration. The stabilization time is 4096 CPU clock

cycles.

4096 CPU CLOCK

CYCLES DELAY

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

23/132

ST7263B

POWER SAVING MODES (Cont’d)

8.3 SLOW Mode

In Slow mode, the oscillator frequency can be di-

vided by 2 as selected by the SMS bit in the Mis-

cellaneous Register. The CPU and peripherals are

clocked at this lower frequency. Slow mode is

used to reduce power consumption, and enables

the user to adapt the clock frequency to the avail-

able supply voltage.

Figure 18. WAIT Mode Flow Chart

WFI INSTRUCTION

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

8.4 WAIT Mode

OFF

CLEARED

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

“WFI” ST7 software instruction.

All peripherals remain active. During WAIT mode,

the I bit of the CC register is forced to 0 to enable

all interrupts. All other registers and memory re-

main unchanged. The MCU remains in WAIT

mode until an interrupt or Reset occurs, whereup-

on the Program Counter branches to the starting

address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

N

RESET

N

Y

INTERRUPT

Refer to Figure 18.

Y

OSCILLATOR

ON

SET

PERIPH. CLOCK

CPU CLOCK

I-BIT

IF RESET

4096 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

24/132

ST7263B

9 I/O PORTS

9.1 Introduction

The I/O ports offer different functional modes:

tivity is given independently according to the de-

scription mentioned in the ITRFRE interrupt regis-

ter.

– Transfer of data through digital inputs and out-

puts and for specific pins

Each pin can independently generate an Interrupt

request.

– Analog signal input (ADC)

– Alternate signal input/output for the on-chip pe-

ripherals

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If more than one input pin is selected simul-

taneously as an interrupt source, this is logically

ORed. For this reason if one of the interrupt pins is

tied low, the other ones are masked.

– External interrupt generation

An I/O port consists of up to 8 pins. Each pin can

be programmed independently as a digital input

(with or without interrupt generation) or a digital

output.

Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit (see Table 7).

9.2 Functional description

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Therefore, the previously saved value is re-

stored when the DR register is read.

Each port is associated to 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

Each I/O pin may be programmed using the corre-

sponding register bits in DDR register: bit X corre-

sponding to pin X of the port. The same corre-

spondence is used for the DR register.

Note: The interrupt function is disabled in this

mode.

Digital Alternate Function

Table 8. I/O Pin Functions

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

DDR

MODE

Input

0

1

Output

Input Modes

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

Note 1: All the inputs are triggered by a Schmitt

trigger.

Note 2: When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

Warning: The alternate function must not be acti-

vated as long as the pin is configured as an input

with interrupt in order to avoid generating spurious

interrupts.

Interrupt function

When an I/O is configured as an Input with Inter-

rupt, an event on this I/O can generate an external

Interrupt request to the CPU. The interrupt sensi-

25/132

ST7263B

I/O PORTS (Cont’d)

Analog Alternate Function

have clocking pins located close to a selected an-

alog pin.

When the pin is used as an ADC input the I/O must

be configured as a floating input. The analog mul-

tiplexer (controlled by the ADC registers) switches

the analog voltage present on the selected pin to

the common analog rail which is connected to the

ADC input.

Warning: The analog input voltage level must be

within the limits stated in the Absolute Maximum

Ratings.

9.3 I/O Port Implementation

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

The hardware implementation on each I/O port de-

pends on the settings in the DDR register and spe-

cific feature of the I/O port such as ADC Input or

true open drain.

26/132

ST7263B

I/O PORTS (Cont’d)

9.3.1 Port A

Table 9. Port A0, A3, A4, A5, A6, A7 Description

I / O

Alternate Function

Condition

PORT A

Input*

Output

push-pull

Signal

PA0

PA3

with pull-up

MCO (Main Clock Output) MCO = 1 (MISCR)

CC1 =1

with pull-up

push-pull

Timer EXTCLK

CC0 = 1 (Timer CR2)

Timer ICAP1

PA4

PA5

PA6

push-pull

IT1 Schmitt triggered input IT1E = 1 (ITIFRE)

Timer ICAP2

IT2 Schmitt triggered input IT2E = 1 (ITIFRE)

Timer OCMP1

IT3 Schmitt triggered input IT3E = 1 (ITIFRE)

Timer OCMP2 OC2E = 1

IT4 Schmitt triggered input IT4E = 1 (ITIFRE)

OC1E = 1

PA7

*Reset State

Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 Configuration

ALTERNATE ENABLE

1

0

V_DD

ALTERNATE

OUTPUT

P-BUFFER

V

DD

DR

PULL-UP

LATCH

ALTERNATE ENABLE

DDR

LATCH

PAD

DDR SEL

N-BUFFER

DIODES

1

0

DR SEL

ALTERNATE ENABLE

V_SS

ALTERNATE INPUT

CMOS SCHMITT TRIGGER

27/132

ST7263B

I/O PORTS (Cont’d)

Table 10. PA1, PA2 Description

I / O

Alternate Function

Signal Condition

PORT A

Input*

Output

PA1

without pull-up

Very High Current open drain

SDA (I²C data)

SCL (I²C clock)

I²C enable

PA2

without pull-up

Very High Current open drain

*Reset State

Figure 20. PA1, PA2 Configuration

ALTERNATE ENABLE

1

ALTERNATE

OUTPUT

0

DR

LATCH

DDR

LATCH

PAD

DDR SEL

N-BUFFER

DR SEL

1

0

ALTERNATE ENABLE

V_SS

CMOS SCHMITT TRIGGER

28/132

ST7263B

I/O PORTS (Cont’d)

9.3.2 Port B

Table 11. Port B Description

PORT B

I/O

Alternate Function

Signal Condition

Input*

Output

push-pull

PB0

PB1

PB2

PB3

without pull-up

Analog input (ADC)

CH[2:0] = 000 (ADCCSR)

CH[2:0] = 001 (ADCCSR)

CH[2:0]= 010 (ADCCSR)

CH[2:0]= 011 (ADCCSR)

CH[2:0]= 100 (ADCCSR)

push-pull

PB4

PB5

PB6

without pull-up

push-pull

IT5 Schmitt triggered input IT4E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 101 (ADCCSR)

IT6 Schmitt triggered input IT5E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 110 (ADCCSR)

IT7 Schmitt triggered input IT6E = 1 (ITIFRE)

Analog input (ADC)

CH[2:0]= 111 (ADCCSR)

PB7

IT8 Schmitt triggered input IT7E = 1 (ITIFRE)

*Reset State

Figure 21. Port B Configuration

ALTERNATE ENABLE

V

ALTERNATE

OUTPUT

DD

1

0

V

DD

P-BUFFER

DR

LATCH

ALTERNATE ENABLE

DDR

PAD

LATCH

ANALOG ENABLE

(ADC)

DDR SEL

ANALOG

SWITCH

DIODES

N-BUFFER

1

DR SEL

ALTERNATE ENABLE

DIGITAL ENABLE

V

0

SS

ALTERNATE INPUT

29/132

ST7263B

I/O PORTS (Cont’d)

9.3.3 Port C

Table 12. Port C Description

I / O

Alternate Function

PORT C

Input*

Output

Signal

Condition

PC0

PC1

with pull-up

push-pull

RDI (SCI input)

TDO (SCI output)

SCI enable

USBOE =1

(MISCR)

USBOE (USB output ena-

ble)

PC2

with pull-up

push-pull

*Reset State

Figure 22. Port C Configuration

ALTERNATE ENABLE

1

0

V

ALTERNATE

OUTPUT

DD

P-BUFFER

V

DD

DR

PULL-UP

LATCH

ALTERNATE ENABLE

DDR

PAD

LATCH

DDR SEL

N-BUFFER

DIODES

1

0

DR SEL

ALTERNATE ENABLE

V

SS

ALTERNATE INPUT

CMOS SCHMITT TRIGGER

30/132

ST7263B

I/O PORTS (Cont’d)

9.3.4 Register Description

DATA DIRECTION REGISTER (PxDDR)

DATA REGISTERS (PxDR)

Port A Data Direction Register (PADDR): 0001h

Port B Data Direction Register (PBDDR): 0003h

Port C Data Direction Register (PCDDR): 0005h

Read/Write

Port A Data Register (PADR): 0000h

Port B Data Register (PBDR): 0002h

Port C Data Register (PCDR): 0004h

Read/Write

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Reset Value Port A: 0000 0000 (00h)

Reset Value Port B: 0000 0000 (00h)

Reset Value Port C: 1111 x000 (FXh)

Note: For Port C, unused bits (7-3) are not acces-

sible

Note: For Port C, unused bits (7-3) are not acces-

sible.

7

0

7

0

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7:0 = DD[7:0] Data Direction Register 8 bits.

Bit 7:0 = D[7:0] Data Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken into account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

Table 13. I/O Ports Register Map

Address

(Hex.)

00

Register

Label

7

6

5

4

3

2

1

0

PADR

PADDR

PBDR

MSB

LSB

01

02

03

PBDDR

PCDR

04

05

PCDDR

31/132

ST7263B

10 MISCELLANEOUS REGISTER

Address: 0009h

—

Read/Write

Bit 1 = USBOE USB enable.

Reset Value: 0000 0000 (00h)

If this bit is set, the port PC2 outputs the USB out-

put enable signal (at “1” when the ST7 USB is

transmitting data).

7

0

-

SMS USBOE MCO

Unused bits 7-4 are set.

Bit 7:3 = Reserved

Bit 2 = SMS Slow Mode Select.

Bit 0 = MCO Main Clock Out selection

This bit enables the MCO alternate function on the

PA0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

This bit is set by software and only cleared by hard-

ware after a reset. If this bit is set, it enables the use

of an internal divide-by-2 clock divider (refer to Fig-

ure 15 on page 19). The SMS bit has no effect on

the USB frequency.

1: MCO alternate function enabled (f

port)

on I/O

CPU

0: Divide-by-2 disabled and CPU clock frequency

is standard

1: Divide-by-2 enabled and CPU clock frequency is

halved.

32/132

ST7263B

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T6:T0) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 14, ". Watchdog Timing (fCPU = 8

MHz)"):

11.1.2 Main Features

■ Programmable timer (64 increments of 49,152

CPU cycles)

– The WDGA bit is set (watchdog enabled)

■ Programmable reset

– The T6 bit is set to prevent generating an imme-

diate reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional

reset

on

HALT

instruction

– The T5:T0 bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

(configurable by option byte)

■ Hardware Watchdog selectable by option byte.

11.1.3 Functional Description

The counter value stored in the CR register (bits

T6:T0), is decremented every 49,152 machine cy-

Figure 23. Watchdog Block Diagram

RESET

WATCHDOG CONTROL REGISTER (CR)

T5 T0

WDGA T6

T1

T4

T2

T3

7-BIT DOWNCOUNTER

CLOCK DIVIDER

f

CPU

÷49152

33/132

ST7263B

WATCHDOG TIMER (Cont’d)

Table 14. Watchdog Timing (f

= 8 MHz)

In this case, the HALT instruction stops the oscilla-

tor. When the oscillator is stopped, the WDG stops

counting and is no longer able to generate a reset

until the microcontroller receives an external inter-

rupt or a reset.

CPU

CR Register

initial value

WDG timeout period

(ms)

Max

Min

FFh

C0h

393.216

6.144

If an external interrupt is received, the WDG re-

starts counting after 4096 CPU clocks. If a reset is

generated, the WDG is disabled (reset state).

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcon-

troller.

11.1.4 Software Watchdog Option

If Software Watchdog is selected by option byte,

the watchdog is disabled following a reset. Once

activated it cannot be disabled, except by a reset.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Interrupt” before executing

the HALT instruction. The main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interference or by an unforeseen logical

condition.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

11.1.5 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the CR is not used.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

11.1.6 Low Power Modes

WAIT Instruction

No effect on Watchdog.

HALT Instruction

– As the HALT instruction clears the I bit in the CC

register to allow interrupts, the user may choose

to clear all pending interrupt bits before execut-

ing the HALT instruction. This avoids entering

other peripheral interrupt routines after executing

the external interrupt routine corresponding to

the wake-up event (reset or external interrupt).

If the Watchdog reset on HALT option is selected

by option byte, a HALT instruction causes an im-

mediate reset generation if the Watchdog is acti-

vated (WDGA bit is set).

11.1.6.1 Using Halt Mode with the WDG (option)

If the Watchdog reset on HALT option is not se-

lected by option byte, the Halt mode can be used

when the watchdog is enabled.

11.1.7 Interrupts

None.

34/132

ST7263B

WATCHDOG TIMER (Cont’d)

11.1.8 Register Description

CONTROL REGISTER (CR)

Read/Write

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Reset Value: 0111 1111 (7Fh)

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

7

0

WDGA T6

T5

T4

T3

T2

T1

T0

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

Table 15. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

WDGCR

WDGA

0

T6

1

T5

1

T4

1

T3

1

T2

1

T1

1

T0

1

0Ch

Reset Value

35/132

ST7263B

11.2 16-BIT TIMER

11.2.1 Introduction

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

11.2.3 Functional Description

11.2.3.1 Counter

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input capture) or generation of up to two out-

put waveforms (output compare and PWM).

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

11.2.2 Main Features

■ Programmableprescaler:f_CPUdividedby2, 4or8.

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least 4 times

slowerthan theCPUclockspeed)with thechoice

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16,

"Clock Control Bits". The value in the counter reg-

ister repeats every 131072, 262144 or 524288

CPU clock cycles depending on the CC[1:0] bits.

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

The timer frequency can be f

or an external frequency.

/2, f

/4, f

/8

CPU

■ Reduced Power Mode

■ 5 alternate functionson I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 24.

*Note: Some timer pins may not available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

36/132

ST7263B

16-BIT TIMER (Cont’d)

Figure 24. Timer Block Diagram

ST7 INTERNAL BUS

f

CPU

MCU-PERIPHERAL INTERFACE

8 low

8-bit

8 high

8

buffer

h

EXEDG

g

w

g

w

g

w

g

low

16

INPUT

CAPTURE

REGISTER

INPUT

CAPTURE

REGISTER

OUTPUT

COMPARE

REGISTER

OUTPUT

COMPARE

REGISTER

1/2

1/4

1/8

COUNTER

REGISTER

1

2

ALTERNATE

COUNTER

REGISTER

EXTCLK

16

CC[1:0]

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

EDGE DETECT

CIRCUIT1

OUTPUT COMPARE

CIRCUIT

ICAP1

CIRCUIT

6

EDGE DETECT

CIRCUIT2

ICAP2

OCMP1

LATCH1

LATCH2

0

ICF1 OCF1 TOF ICF2 OCF2

0

TIMD

(Control/Status Register)

OCMP2

CSR

EXEDG

ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1

OC1E

OPM PWM CC1 CC0 IEDG2

OC2E

(Control Register 1) CR1

(Control Register 2) CR2

(See note)

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

TIMER INTERRUPT

37/132

ST7263B

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Beginning of the sequence

Read

LS Byte

is buffered

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

MS Byte

At t0

Other

instructions

Returns the buffered

LS Byte value at t0

Read

LS Byte

At t0 +∆t

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

11.2.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

Whatever the timer mode used (input capture, out-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

The counter is synchronized with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

38/132

ST7263B

16-BIT TIMER (Cont’d)

Figure 25. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 26. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

FFFC

FFFD

0000

0001

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Figure 27. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

0000

FFFC

FFFD

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

39/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.3.3 Input Capture

When an input capture occurs:

In this section, the index, i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 29).

The two 16-bit input capture registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition is detected on the

ICAPi pin (see figure 5).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

MS Byte

ICiHR

LS Byte

ICiLR

ICiR

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

ICiR register is a read-only register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

Notes:

counter: (f

/CC[1:0]).

CPU

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

Procedure:

To use the input capture function select the follow-

ing in the CR2 register:

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

– Select the timer clock (CC[1:0]) (see Table 16,

"Clock Control Bits").

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as floating input or input with

pull-up without interrupt if this configuration is

available).

4. In One pulse Mode and PWM mode only Input

Capture 2 can be used.

And select the following in the CR1 register:

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activates the input

capture function.

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

Moreover if one of the ICAPi pins is configured

as an input and the second one as an output,

an interrupt can be generated if the user tog-

gles the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabled by reading the ICiHR (see note

1).

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input or input with pull-

up without interrupt if this configuration is availa-

ble).

6. The TOF bit can be used with interrupt genera-

tion in order to measure events that go beyond

the timer range (FFFFh).

40/132

ST7263B

16-BIT TIMER (Cont’d)

Figure 28. Input Capture Block Diagram

ICAP1

(Control Register 1) CR1

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

ICIE

IEDG1

ICAP2

(Status Register) SR

ICF1

ICF2

0

IC2R Register

IC1R Register

(Control Register 2) CR2

16-BIT

16-BIT FREE RUNNING

COUNTER

IEDG2

CC0

CC1

Figure 29. Input Capture Timing Diagram

TIMER CLOCK

FF01

FF02

FF03

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF03

ICAPi REGISTER

Note: The rising edge is the active edge.

41/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.3.4 Output Compare

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

In this section, the index, i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in

the CC register (CC).

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

When a match is found between the Output Com-

pare register and the free running counter, the out-

put compare function:

– Assigns pins with a programmable value if the

OCiE bit is set

∆t f

* CPU

PRESC

∆ OCiR =

– Sets a flag in the status register

– Generates an interrupt if enabled

Where:

∆t

= Output compare period (in seconds)

= CPU clock frequency (in hertz)

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

register each timer clock cycle.

f

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16,

"Clock Control Bits")

MS Byte

OCiHR

LS Byte

OCiLR

OCiR

If the timer clock is an external clock, the formula

is:

These registers are readable and writable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

∆ OCiR = ∆t f

* EXT

Timing resolution is one count of the free running

Where:

counter: (f

).

CC[1:0]

CPU/

∆t

= Output compare period (in seconds)

= External timer clock frequency (in hertz)

f

EXT

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

1. Reading the SR register while the OCFi bit is

set.

2. An access (read or write) to the OCiLR register.

– Select the timer clock (CC[1:0]) (see Table 16,

"Clock Control Bits").

The following procedure is recommended to pre-

vent the OCFi bit from being set between the time

it is read and the write to the OCiR register:

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Write to the OCiHR register (further compares

are inhibited).

– Set the OCIE bit to generate an interrupt if it is

needed.

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

When a match is found between OCRi register

and CR register:

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

– OCFi bit is set.

42/132

ST7263B

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to the OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is

generated.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

The FOLVLi bits have no effect in both one pulse

CPU

OCMPi are set while the counter value equals

the OCiR register value (see Figure 31 on page

44). This behaviour is the same in OPM or

PWM mode.

mode and PWM mode.

When the timer clock is f

/4, f

/8 or in

CPU

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 32 on page 44).

4. The output compare functions can be used both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in order to control an output

waveform or establish a new elapsed timeout.

Figure 30. Output Compare Block Diagram

16 BIT FREE RUNNING

OC1E

CC1 CC0

OC2E

COUNTER

(Control Register 2) CR2

16-bit

(Control Register 1) CR1

OUTPUT COMPARE

CIRCUIT

Latch

1

OCIE

FOLV2 FOLV1OLVL2

OLVL1

OCMP1

16-bit

Latch

2

OCMP2

OC1R Register

OCF1

OCF2

0

OC2R Register

(Status Register) SR

43/132

ST7263B

16-BIT TIMER (Cont’d)

Figure 31. Output Compare Timing Diagram, f

=f

/2

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

Figure 32. Output Compare Timing Diagram, f

=f

/4

CPU

TIMER

INTERNAL CPU CLOCK

TIMER CLOCK

2ECF 2ED0 2ED1 2ED2

2ED3

2ED4

2ED3

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

44/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.3.5 One Pulse Mode

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Procedure:

t _*f

To use one pulse mode:

CPU

- 5

OCiR Value =

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

PRESC

Where:

t

= Pulse period (in seconds)

2. Select the following in the CR1 register:

f

= CPU clock frequency (in hertz)

CPU

PRESC

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16,

"Clock Control Bits")

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

If the timer clock is an external clock the formula is:

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

OCiR = t f

-5

* EXT

Where:

t

3. Select the following in the CR2 register:

= Pulse period (in seconds)

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

f

= External timer clock frequency (in hertz)

EXT

– Set the OPM bit.

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 33).

– Select the timer clock CC[1:0] (see Table 16,

"Clock Control Bits").

One pulse mode cycle

Notes:

ICR1 = Counter

When

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

OCMP1 = OLVL2

event occurs

on ICAP1

Counter is reset

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

to FFFCh

ICF1 bit is set

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

When

Counter

OCMP1 = OLVL1

= OC1R

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin, the ICF1 bit is set and the val-

ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

45/132

ST7263B

16-BIT TIMER (Cont’d)

Figure 33. One Pulse Mode Timing Example

2ED3

01F8

IC1R

FFFC FFFD FFFE

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

01F8

COUNTER

ICAP1

OLVL2

OLVL1

OLVL2

OCMP1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 34. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

2ED0 2ED1 2ED2

34E2 FFFC

FFFC FFFD FFFE

34E2

COUNTER

OCMP1

OLVL2

OLVL1

OLVL2

compare2

compare1

compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated us-

ing the output compare and the counter overflow to define the pulse length.

46/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.3.6 Pulse Width Modulation Mode

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functionality can not be used when

PWM mode is activated.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

t _*f

CPU

PRESC

- 5

OCiR Value =

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are taken

into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

Where:

t

= Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

f

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16,

"Clock Control Bits")

Procedure

To use pulse width modulation mode:

If the timer clock is an external clock the formula is:

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

OCiR = t f

-5

* EXT

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

Where:

t

= Signal or pulse period (in seconds)

f

= External timer clock frequency (in hertz)

EXT

3. Select the following in the CR1 register:

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 34)

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC1R register.

Notes:

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC2R register.

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

4. Select the following in the CR2 register:

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

– Set the PWM bit.

– Select the timer clock (CC[1:0]) (see Table 16,

"Clock Control Bits").

Pulse Width Modulation cycle

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

When

Counter

= OC1R

OCMP1 = OLVL1

OCMP1 = OLVL2

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

When

Counter

= OC2R

Counter is reset

to FFFCh

ICF1 bit is set

47/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.4 Low Power Modes

Mode

Description

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

WAIT

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

11.2.5 Interrupts

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

ICF1

ICF2

No

ICIE

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

OCF1

OCF2

TOF

OCIE

TOIE

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

11.2.6 Summary of Timer modes

TIMER RESOURCES

MODES

Input Capture 1

Input Capture 2

Yes

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

Yes

No

Yes

No

Yes

1)

3)

2)

Not Recommended

Partially

No

PWM Mode

No

1) See note 4 in Section 11.2.3.5, "One Pulse Mode"

2) See note 5 in Section 11.2.3.5, "One Pulse Mode"

3) See note 4 in Section 11.2.3.6, "Pulse Width Modulation Mode"

48/132

ST7263B

16-BIT TIMER (Cont’d)

11.2.7 Register Description

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Each Timer is associated with three control and

status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

CONTROL REGISTER 1 (CR1)

Read/Write

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Reset Value: 0000 0000 (00h)

7

0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the OC2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied to the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

register.

49/132

ST7263B

16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depends on the value of OC2R regis-

ter.

Reset Value: 0000 0000 (00h)

7

0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 3, 2 = CC[1:0] Clock Control.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock

f_CPU/ 4

CC1

CC0

0

1

0

1

0

f_CPU/ 2

f_CPU/ 8

External Clock (where

available)

1

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: If the external clock pin is not available, pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

Bit 0 = EXEDG External Clock Edge.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

50/132

ST7263B

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W)

Reset Value: xxxx x0xx (xxh)

7

Note: Reading or writing the ACLR register does

not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

0

ICF1 OCF1 TOF ICF2 OCF2 TIMD

0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, first read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it

freezes the timer prescaler and counter and disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power consumption. Access to the

timer registers is still available, allowing the timer

configuration to be changed, or the counter reset,

while it is disabled.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

51/132

ST7263B

16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

OUTPUT COMPARE

(OC1HR)

1

HIGH REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

7

0

7

0

MSB

LSB

MSB

LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

OUTPUT COMPARE

(OC1LR)

1

LOW REGISTER

Read Only

Reset Value: Undefined

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

7

0

7

0

MSB

LSB

MSB

LSB

52/132

ST7263B

16-BIT TIMER (Cont’d)

OUTPUT COMPARE

(OC2HR)

2

HIGH REGISTER

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read/Write

Reset Value: 1000 0000 (80h)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

This is an 8-bit register that contains the high part

of the counter value.

7

0

7

0

MSB

LSB

MSB

LSB

OUTPUT COMPARE

(OC2LR)

2

LOW REGISTER

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read/Write

Reset Value: 0000 0000 (00h)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

7

0

MSB

LSB

7

0

COUNTER HIGH REGISTER (CHR)

MSB

LSB

Read Only

Reset Value: 1111 1111 (FFh)

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

This is an 8-bit register that contains the high part

of the counter value.

Read Only

Reset Value: Undefined

7

0

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB

7

0

MSB

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

7

0

MSB

LSB

7

0

MSB

LSB

53/132

ST7263B

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

CR2

OC1E

0

OC2E

OPM

0

PWM

CC1

CC0

IEDG2

EXEDG

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Reset Value

CR1

0

OCIE

0

FOLV2

0

FOLV1

0

OLVL2

0

ICIE

0

TOIE

0

IEDG1

OLVL1

Reset Value

SR

0

ICF1

0

OCF1

0

TOF

0

ICF2

0

OCF2

0

TIMD

0

Reset Value

IC1HR

MSB

LSB

Reset Value

IC1LR

Reset Value

OC1HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

OC1LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

CHR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

1

LSB

1

Reset Value

CLR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

0

LSB

0

Reset Value

ACHR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

1

LSB

1

Reset Value

ACLR

MSB

1

-

1

-

1

-

1

-

1

-

1

-

0

LSB

0

Reset Value

IC2HR

MSB

LSB

Reset Value

IC2LR

Reset Value

OC2HR

MSB

1

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

OC2LR

MSB

0

-

0

-

0

-

0

-

0

-

0

-

0

LSB

0

Reset Value

54/132

ST7263B

11.3 SERIAL COMMUNICATIONS INTERFACE (SCI)

11.3.1 Introduction

11.3.3 General Description

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format.

The interface is externally connected to another

device by two pins (see Figure 36):

– TDO: Transmit Data Output. When the transmit-

ter and the receiver are disabled, the output pin

returns to its I/O port configuration. When the

transmitter is enabled and nothing is to be trans-

mitted, the TDO pin is at high level.

11.3.2 Main Features

■ Full duplex, asynchronous communications

■ NRZ standard format (Mark/Space)

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-

covery by discriminating between valid incoming

data and noise.

■ Independently programmable transmit and

receive baud rates up to 250K baud.

■ Programmable data word length (8 or 9 bits)

■ Receive buffer full, Transmit buffer empty and

Through these pins, serial data is transmitted and

received as frames comprising:

End of Transmission flags

■ Two receiver wake-up modes:

– Address bit (MSB)

– An Idle Line prior to transmission or reception

– A start bit

– Idle line

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

■ Mutingfunctionformultiprocessorconfigurations

■ Separate enable bits for Transmitter and

Receiver

■ Four error detection flags:

– Overrun error

– Noise error

– Frame error

– Parity error

■ Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

■ Parity control:

– Transmits parity bit

– Checks parity of received data byte

■ Reduced power consumption mode

55/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 35. SCI Block Diagram

Write

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Received Shift Register

Transmit Data Register (TDR)

TDO

Transmit Shift Register

RDI

CR1

R8

T8 SCID

M WAKE PCE PS PIE

WAKE

UP

TRANSMIT

RECEIVER

CLOCK

RECEIVER

CONTROL

UNIT

CR2

SR

TIE TCIE RIE ILIE TE RE RWU SBK

TDRE TC RDRF IDLE OR NF FE

PE

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK

TRANSMITTER RATE

CONTROL

f

CPU

/PR

/16

BRR

SCP1

SCT2

SCT1SCT0SCR2 SCR1SCR0

SCP0

RECEIVER RATE

CONTROL

BAUD RATE GENERATOR

56/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.4 Functional Description

The TDO pin is in low state during the start bit.

The block diagram of the Serial Control Interface,

is shown in Figure 35. It contains 6 dedicated reg-

isters:

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

A Break character is interpreted on receiving “0”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

– A baud rate register (SCIBRR)

Refer to the register descriptions in Section

11.3.7for the definitions of each bit.

11.3.4.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 35).

Figure 36. Word Length Programming

9-bit Word length (M bit is set)

Possible

Next Data Frame

Parity

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit5

Bit6

Bit0

Bit1

Bit3

Bit4

Bit8

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

8-bit Word length (M bit is reset)

Possible

Parity

Next Data Frame

Data Frame

Start

Bit

Stop

Bit

Bit2

Bit6

Bit0

Bit1

Bit3

Bit4 Bit5

Bit7

Bit

Start

Bit

Idle Frame

Start

Bit

Extra

’1’

Break Frame

57/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.4.2 Transmitter

When a frame transmission is complete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is set and

the I bit is cleared in the CCR register.

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1

register.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Character Transmission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the internal bus and the transmit shift regis-

ter (see Figure 35).

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 36).

Procedure

– Select the M bit to define the word length.

As long as the SBK bit is set, the SCI send break

frames to the TDO pin. After clearing this bit by

software the SCI insert a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

– Select the desired baud rate using the SCIBRR

register.

– Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first

transmission.

Idle Characters

– Access the SCISR register and write the data to

send in the SCIDR register (this sequence clears

the TDRE bit). Repeat this sequence for each

data to be transmitted.

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and then setting the TE bit during a trans-

mission sends an idle frame after the current word.

Clearing the TDRE bit is always performed by the

following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

register at the end of the current transmission.

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

58/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.4.3 Receiver

Overrun Error

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

register.

An overrun error occurs when a character is re-

ceived when RDRF has not been reset. Data can

not be transferred from the shift register to the

RDR register as long as the RDRF bit is not

cleared.

Character Reception

When a overrun error occurs:

– The OR bit is set.

During a SCI reception, data shifts in least signifi-

cant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) be-

tween the internal bus and the received shift regis-

ter (see Figure 35).

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

Procedure

– Select the M bit to define the word length.

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

– Select the desired baud rate using the SCIBRR

register.

Noise Error

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise.

When a character is received:

– The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

When noise is detected in a frame:

– The NF is set at the rising edge of the RDRF bit.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

– Data is transferred from the Shift register to the

SCIDR register.

– The error flags can be set if a frame error, noise

or an overrun error has been detected during re-

ception.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

Clearing the RDRF bit is performed by the following

software sequence done by:

The NF bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

1. An access to the SCISR register

2. A read to the SCIDR register.

Framing Error

A framing error is detected when:

The RDRF bit must be cleared before the end of the

reception of the next character to avoid an overrun

error.

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

Break Character

– A break is received.

When a break character is received, the SPI han-

dles it as a framing error.

When the framing error is detected:

– the FE bit is set by hardware

Idle Character

– Data is transferred from the Shift register to the

SCIDR register.

When a idle frame is detected, there is the same

procedure as a data received character plus an in-

terrupt if the ILIE bit is set and the I bit is cleared in

the CCR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR register read operation.

59/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.4.4 Baud Rate Generation

The non addressed devices may be placed in

sleep mode by means of the muting function.

The baud rate for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

Setting the RWU bit by software puts the SCI in

Sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

f

CPU

Rx =

Tx =

(16 PR) RR

(16 PR) TR

*

A muted receiver may be awakened by one of the

following two ways:

with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame.

Then the RWU bit is reset by hardware but the

IDLE bit is not set.

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If f is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive

Receiver wakes-up by Address Mark detection

when it received a “1” as the most significant bit of

a word, thus indicating that the message is an ad-

dress. The reception of this particular word wakes

up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this

word normally and to use it as an address word.

CPU

baud rates are 38400 baud.

Note: The baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

Caution: In Mute mode, do not write to the

SCICR2 register. If the SCI is in Mute mode during

the read operation (RWU=1) and a address mark

wake up event occurs (RWU is reset) before the

write operation, the RWU bit will be set again by

this write operation. Consequently the address

byte is lost and the SCI is not woken up from Mute

mode.

11.3.4.5 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non addressed receivers.

60/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.4.6 Parity Control

(PS=0) or an odd number of “1s” if odd parity is se-

lected (PS=1). If the parity check fails, the PE flag

is set in the SCISR register and an interrupt is gen-

erated if PIE is set in the SCICR1 register.

Parity control (generation of parity bit in trasmis-

sion and and parity checking in reception) can be

enabled by setting the PCE bit in the SCICR1 reg-

ister. Depending on the frame length defined by

the M bit, the possible SCI frame formats are as

listed in Table 18.

11.3.5 Low Power Modes

Mode

Description

Table 18. Frame Formats

No effect on SCI.

M bit

PCE bit

SCI Frame

WAIT

SCI interrupts cause the device to exit

from Wait mode.

0

1

0

1

0

1

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

SCI registers are frozen.

In Halt mode, the SCI stops transmit-

ting/receiving until Halt mode is exit-

ed.

HALT

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

11.3.6 Interrupts

Interrupt Event

Enable Exit

Control from from

Exit

Event

Flag

Even parity: the parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Bit

Wait

Halt

Transmit Data Register

Empty

TDRE

TC

TIE

Yes

No

Transmission Com-

plete

TCIE

RIE

Yes

No

Ex: data=00110101; 4 bits set => parity bit will be

0 if even parity is selected (PS bit = 0).

Received Data Ready

to be Read

RDRF

Odd parity: the parity bit is calculated to obtain an

odd number of “1s” inside the frame made of the 7

or 8 LSB bits (depending on whether M is equal to

0 or 1) and the parity bit.

Overrun Error Detected OR

Yes

No

Idle Line Detected

Parity Error

IDLE

PE

ILIE

PIE

Ex: data=00110101; 4 bits set => parity bit will be

1 if odd parity is selected (PS bit = 1).

The SCI interrupt events are connected to the

same interrupt vector.

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmitted but is changed by the parity bit.

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

61/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.3.7 Register Description

curs). This bit is not set by an idle line when the re-

ceiver wakes up from wake-up mode.

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 3 = OR Overrun error.

This bit is set by hardware when the word currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the SCICR2

register. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

7

0

TDRE

TC

RDRF IDLE

OR

NF

FE

PE

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

register. An interrupt is generated if the TIE bit=1

in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a write to the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will

not be lost but the shift register will be overwritten.

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No noise is detected

Note: Data will not be transferred to the shift reg-

ister unless the TDRE bit is cleared.

Bit 6 = TC Transmission complete.

1: Noise is detected

This bit is set by hardware when transmission of a

frame containing Data, a Preamble or a Break is

complete. An interrupt is generated if TCIE=1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a write to the SCIDR register).

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

0: Transmission is not complete

1: Transmission is complete

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error is detected

1: Framing error or break character is detected

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR

register. An interrupt is generated if RIE=1 in the

SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when a Idle Line is de-

tected. An interrupt is generated if the ILIE=1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error oc-

curs in receiver mode. It is cleared by a software

sequence (a read to the status register followed by

an access to the SCIDR data register). An inter-

rupt is generated if PIE=1 in the SCICR1 register.

0: No parity error

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

1: Parity error

62/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (SCICR1)

Read/Write

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

Reset Value: x000 0000 (x0h)

1: Address Mark

7

0

R8

T8

SCID

M

WAKE PCE

PS

PIE

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (gener-

ation and detection). When the parity control is en-

abled, the computed parity is inserted at the MSB

position (9th bit if M=1; 8th bit if M=0) and parity is

checked on the received data. This bit is set and

cleared by software. Once it is set, PCE is active

after the current byte (in reception and in transmis-

sion).

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

0: Parity control disabled

1: Parity control enabled

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 4 = M Word length.

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled.

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

63/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 2 (SCICR2)

Read/Write

0: Transmitter is disabled

1: Transmitter is enabled

Note: During transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word.

Reset Value: 0000 0000 (00h)

7

0

Caution: The TDO pin is free for general purpose

I/O only when the TE and RE bits are both cleared

(or if TE is never set).

TIE

TCIE

RIE

ILIE

TE

RE

RWU

SBK

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a

start bit

Bit 6 = TCIE Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

the SCISR register

0: Receiver in active mode

1: Receiver in mute mode

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Note: Before selecting mute mode (setting the

RWU bit), the SCI must receive some data first,

otherwise it cannot function in mute mode with

wakeup by idle line detection.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Bit 3 = TE Transmitter enable.

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

This bit enables the transmitter and assigns the

TDO pin to the alternate function. It is set and

cleared by software.

64/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (SCIDR)

Read/Write

PR Prescaling factor

SCP1

SCP0

4

1

0

1

Reset Value: Undefined

13

Contains the Received or Transmitted data char-

acter, depending on whether it is read from or writ-

ten to.

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the transmit rate clock.

7

0

TR dividing factor

SCT2

SCT1

SCT0

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 35).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 35).

4

8

16

32

64

128

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP[1:0] bits

define the total division applied to the bus clock to

yield the receive rate clock.

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

RR dividing factor

SCR2

SCR1

SCR0

7

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

4

8

Bits 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

16

32

64

128

PR Prescaling factor

SCP1

SCP0

1

3

0

1

65/132

ST7263B

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Table 19. SCI Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

20

21

22

23

24

SCISR

TDRE

TC

1

RDRF

IDLE

0

OR

0

NF

0

FE

0

PE

0

Reset Value

SCIDR

1

DR7

x

0

DR5

x

DR6

x

DR4

x

DR3

x

DR2

x

DR1

x

DR0

x

Reset Value

SCIBRR

SCP1

0

SCP0

SCT2

x

SCT1

SCT0

SCR2

x

SCR1

SCR0

x

Reset Value

SCICR1

0

T8

x

M

x

WAKE

x

PS

0

R8

x

SCID

0

PCE

0

PIE

0

Reset Value

SCICR2

x

TIE

0

TCIE

0

RIE

0

ILIE

0

TE

0

RE

0

RWU

0

SBK

0

Reset Value

66/132

ST7263B

11.4 USB INTERFACE (USB)

11.4.1 Introduction

For general information on the USB, refer to the

“Universal Serial Bus Specifications” document

available at http//:www.usb.org.

The USB Interface implements a low-speed func-

tion interface between the USB and the ST7 mi-

crocontroller. It is a highly integrated circuit which

includes the transceiver, 3.3 voltage regulator, SIE

and DMA. No external components are needed

apart from the external pull-up on USBDM for low

speed recognition by the USB host. The use of

DMA architecture allows the endpoint definition to

be completely flexible. Endpoints can be config-

ured by software as in or out.

Serial Interface Engine

The SIE (Serial Interface Engine) interfaces with

the USB, via the transceiver.

The SIE processes tokens, handles data transmis-

sion/reception, and handshaking as required by

the USB standard. It also performs frame format-

ting, including CRC generation and checking.

Endpoints

11.4.2 Main Features

The Endpoint registers indicate if the microcontrol-

ler is ready to transmit/receive, and how many

bytes need to be transmitted.

■ USB Specification Version 1.1 Compliant

■ Supports Low-Speed USB Protocol

■ Two or Three Endpoints (including default one)

depending on the device (see device feature list

and register map)

DMA

When a token for a valid Endpoint is recognized by

the USB interface, the related data transfer takes

place, using DMA. At the end of the transaction, an

interrupt is generated.

■ CRC generation/checking, NRZI encoding/

decoding and bit-stuffing

■ USB Suspend/Resume operations

■ DMA Data transfers

Interrupts

By reading the Interrupt Status register, applica-

tion software can know which USB event has oc-

curred.

■ On-Chip 3.3V Regulator

■ On-Chip USB Transceiver

11.4.3 Functional Description

The block diagram in Figure 37, gives an overview

of the USB interface hardware.

Figure 37. USB Block Diagram

6 MHz

ENDPOINT

CPU

REGISTERS

USBDM

Address,

Transceiver

SIE

DMA

USBDP

data buses

and interrupts

3.3V

INTERRUPT

REGISTERS

USBVCC

USBGND

Voltage

Regulator

MEMORY

67/132

ST7263B

USB INTERFACE (Cont’d)

11.4.4 Register Description

DMA ADDRESS REGISTER (DMAR)

Read / Write

INTERRUPT/DMA REGISTER (IDR)

Read / Write

Reset Value: xxxx 0000 (x0h)

Reset Value: Undefined

7

0

7

0

DA7

DA6

EP1

EP0 CNT3 CNT2 CNT1 CNT0

DA15 DA14 DA13 DA12 DA11 DA10 DA9

DA8

Bits 7:6 = DA[7:6] DMA address bits 7-6.

Software must reset these bits. See the descrip-

tion of the DMAR register and Figure 38.

Bits 7:0=DA[15:8] DMA address bits 15-8.

Software must write the start address of the DMA

memory area whose most significant bits are given

by DA15-DA6. The remaining 6 address bits are

set by hardware. See the description of the IDR

register and Figure 38.

Bits 5:4 = EP[1:0] Endpoint number (read-only).

These bits identify the endpoint which required at-

tention.

00: Endpoint 0

01: Endpoint 1

10: Endpoint 2

When a CTR interrupt occurs (see register ISTR)

the software should read the EP bits to identify the

endpoint which has sent or received a packet.

Bits 3:0 = CNT[3:0] Byte count (read only).

This field shows how many data bytes have been

received during the last data reception.

Note: Not valid for data transmission.

Figure 38. DMA Buffers

101111

Endpoint 2 TX

Endpoint 2 RX

101000

100111

100000

011111

Endpoint 1 TX

Endpoint 1 RX

011000

010111

010000

001111

Endpoint 0 TX

Endpoint 0 RX

001000

000111

DA15-6,000000

000000

68/132

ST7263B

USB INTERFACE (Cont’d)

PID REGISTER (PIDR)

Read only

INTERRUPT STATUS REGISTER (ISTR)

Read / Write

Reset Value: xx00 0000 (x0h)

Reset Value: 0000 0000 (00h)

7

0

7

0

RX_

SEZ

SUSP DOVR CTR ERR IOVR ESUSP RESET SOF

TP3

TP2

0

RXD

When an interrupt occurs these bits are set by

hardware. Software must read them to determine

the interrupt type and clear them after servicing.

Note: These bits cannot be set by software.

Bits 7:6 = TP[3:2] Token PID bits 3 & 2.

USB token PIDs are encoded in four bits. TP[3:2]

correspond to the variable token PID bits 3 & 2.

Note: PID bits 1 & 0 have a fixed value of 01.

When a CTR interrupt occurs (see register ISTR)

the software should read the TP3 and TP2 bits to

retrieve the PID name of the token received.

The USB standard defines TP bits as:

Bit 7 = SUSP Suspend mode request.

This bit is set by hardware when a constant idle

state is present on the bus line for more than 3 ms,

indicating a suspend mode request from the USB

bus. The suspend request check is active immedi-

ately after each USB reset event and its disabled

by hardware when suspend mode is forced

(FSUSP bit of CTLR register) until the end of

resume sequence.

TP3

0

TP2

0

PID Name

OUT

1

0

IN

1

SETUP

Bits 5:3 Reserved. Forced by hardware to 0.

Bit 6 = DOVR DMA over/underrun.

This bit is set by hardware if the ST7 processor

can’t answer a DMA request in time.

0: No over/underrun detected

Bit 2 = RX_SEZ Received single-ended zero

This bit indicates the status of the RX_SEZ trans-

ceiver output.

0: No SE0 (single-ended zero) state

1: USB lines are in SE0 (single-ended zero) state

1: Over/underrun detected

Bit 5 = CTR Correct Transfer. This bit is set by

hardware when a correct transfer operation is per-

formed. The type of transfer can be determined by

looking at bits TP3-TP2 in register PIDR. The End-

point on which the transfer was made is identified

by bits EP1-EP0 in register IDR.

Bit 1 = RXD Received data

0: No K-state

1: USB lines are in K-state

This bit indicates the status of the RXD transceiver

output (differential receiver output).

0: No Correct Transfer detected

1: Correct Transfer detected

Note: If the environment is noisy, the RX_SEZ and

RXD bits can be used to secure the application. By

interpreting the status, software can distinguish a

valid End Suspend event from a spurious wake-up

due to noise on the external USB line. A valid End

Suspend is followed by a Resume or Reset se-

quence. A Resume is indicated by RXD=1, a Re-

set is indicated by RX_SEZ=1.

Note: A transfer where the device sent a NAK or

STALL handshake is considered not correct (the

host only sends ACK handshakes). A transfer is

considered correct if there are no errors in the PID

and CRC fields, if the DATA0/DATA1 PID is sent

as expected, if there were no data overruns, bit

stuffing or framing errors.

Bit 0 = Reserved. Forced by hardware to 0.

Bit 4 = ERR Error.

This bit is set by hardware whenever one of the er-

rors listed below has occurred:

0: No error detected

1: Timeout, CRC, bit stuffing or nonstandard

framing error detected

69/132

ST7263B

USB INTERFACE (Cont’d)

Bit 3 = IOVR Interrupt overrun.

of each bit, please refer to the corresponding bit

description in ISTR.

This bit is set when hardware tries to set ERR, or

SOF before they have been cleared by software.

0: No overrun detected

CONTROL REGISTER (CTLR)

Read / Write

1: Overrun detected

Reset Value: 0000 0110 (06h)

Bit 2 = ESUSP End suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB in-

terface up from suspend mode.

7

0

RESUME

PDWN FSUSP FRES

This interrupt is serviced by a specific vector, in or-

der to wake up the ST7 from HALT mode.

0: No End Suspend detected

Bits 7:4 = Reserved. Forced by hardware to 0.

1: End Suspend detected

Bit 3 = RESUME Resume.

Bit 1 = RESET USB reset.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

0: Resume signal not forced

This bit is set by hardware when the USB reset se-

quence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate

delay.

Note: The DADDR, EP0RA, EP0RB, EP1RA,

EP1RB, EP2RA and EP2RB registers are reset by

a USB reset.

Bit 2 = PDWN Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

Bit 0 = SOF Start of frame.

This bit is set by hardware when a low-speed SOF

indication (keep-alive strobe) is seen on the USB

bus. It is also issued at the end of a resume se-

quence.

0: No SOF signal detected

1: SOF signal detected

1: Voltage regulator off

Note: After turning on the voltage regulator, soft-

ware should allow at least 3 µs for stabilisation of

the power supply before using the USB interface.

Note: To avoid spurious clearing of some bits, it is

recommended to clear them using a load instruc-

tion where all bits which must not be altered are

set, and all bits to be cleared are reset. Avoid read-

modify-write instructions like AND , XOR..

Bit 1 = FSUSP Force suspend mode.

This bit is set by software to enter Suspend mode.

The ST7 should also be halted allowing at least

600 ns before issuing the HALT instruction.

0: Suspend mode inactive

INTERRUPT MASK REGISTER (IMR)

Read / Write

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Reset Value: 0000 0000 (00h)

7

0

Bit 0 = FRES Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

SUS

PM

DOV

RM

CTR

M

ERR IOVR ESU

SPM

RES

ETM

SOF

M

0: Reset not forced

1: USB interface reset forced.

Bits 7:0 = These bits are mask bits for all interrupt

condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit

is set, and the I bit in the CC register is cleared, an

interrupt request is generated. For an explanation

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET” in-

terrupt will be generated if enabled.

70/132

ST7263B

USB INTERFACE (Cont’d)

DEVICE ADDRESS REGISTER (DADDR)

Read / Write

Bit 6 = DTOG_TX Data Toggle, for transmission

transfers.

It contains the required value of the toggle bit

(0=DATA0, 1=DATA1) for the next transmitted

data packet. This bit is set by hardware at the re-

ception of a SETUP PID. DTOG_TX toggles only

when the transmitter has received the ACK signal

from the USB host. DTOG_TX and also

DTOG_RX (see EPnRB) are normally updated by

hardware, at the receipt of a relevant PID. They

can be also written by software.

Reset Value: 0000 0000 (00h)

7

0

ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0] Device address, 7 bits.

Bits 5:4 = STAT_TX[1:0] Status bits, for transmis-

sion transfers.

These bits contain the information about the end-

point status, which are listed below:

Software must write into this register the address

sent by the host during enumeration.

Note: This register is also reset when a USB reset

is received from the USB bus or forced through bit

FRES in the CTLR register.

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission

transfers cannot be executed.

0

STALL: the endpoint is stalled

and all transmission requests

result in a STALL handshake.

ENDPOINT n REGISTER A (EPnRA)

Read / Write

0

1

Reset Value: 0000 xxxx (0xh)

NAK: the endpoint is naked

and all transmission requests

result in a NAK handshake.

1

0

1

7

0

VALID: this endpoint is ena-

bled for transmission.

ST_

OUT

DTOG

_TX

STAT STAT TBC TBC TBC TBC

_TX1

_TX0

3

2

1

0

These bits are written by software. Hardware sets

the STAT_TX bits to NAK when a correct transfer

has occurred (CTR=1) related to a IN or SETUP

transaction addressed to this endpoint; this allows

the software to prepare the next set of data to be

transmitted.

These registers (EP0RA, EP1RA and EP2RA) are

used for controlling data transmission. They are

also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RA register are not

available on some devices (see device feature list

and register map).

Bits 3:0 = TBC[3:0] Transmit byte count for End-

point n.

Before transmission, after filling the transmit buff-

er, software must write in the TBC field the trans-

mit packet size expressed in bytes (in the range 0-

8).

Bit 7 = ST_OUT Status out.

This bit is set by software to indicate that a status

out packet is expected: in this case, all nonzero

OUT data transfers on the endpoint are STALLed

instead of being ACKed. When ST_OUT is reset,

OUT transactions can have any number of bytes,

as needed.

Warning: Any value outside the range 0-8 will-

induce undesired effects (such as continuous data

transmission).

71/132

ST7263B

USB INTERFACE (Cont’d)

ENDPOINT n REGISTER B (EPnRB)

Read / Write

STAT_RX1 STAT_RX0 Meaning

NAK: the endpoint is na-

ked and all reception re-

quests result in a NAK

handshake.

VALID: this endpoint is

enabled for reception.

Reset Value: 0000 xxxx (0xh)

1

0

1

7

0

DTOG

_RX

STAT

_RX1

STAT

_RX0

CTRL

EA3 EA2 EA1 EA0

These bits are written by software. Hardware sets

the STAT_RX bits to NAK when a correct transfer

has occurred (CTR=1) related to an OUT or SET-

UP transaction addressed to this endpoint, so the

software has the time to elaborate the received

data before acknowledging a new transaction.

These registers (EP1RB and EP2RB) are used for

controlling data reception on Endpoints 1 and 2.

They are also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RB register are not

available on some devices (see device feature list

and register map).

Bits 3:0 = EA[3:0] Endpoint address.

Software must write in this field the 4-bit address

used to identify the transactions directed to this

endpoint. Usually EP1RB contains “0001” and

EP2RB contains “0010”.

Bit 7 = CTRL Control.

This bit should be 0.

Note: If this bit is 1, the Endpoint is a control end-

point. (Endpoint 0 is always a control Endpoint, but

it is possible to have more than one control End-

point).

ENDPOINT 0 REGISTER B (EP0RB)

Read / Write

Reset Value: 1000 0000 (80h)

Bit 6 = DTOG_RX Data toggle, for reception trans-

fers.

7

1

0

It contains the expected value of the toggle bit

(0=DATA0, 1=DATA1) for the next data packet.

This bit is cleared by hardware in the first stage

(Setup Stage) of a control transfer (SETUP trans-

actions start always with DATA0 PID). The receiv-

er toggles DTOG_RX only if it receives a correct

data packet and the packet’s data PID matches

the receiver sequence bit.

DTOG STAT STAT

RX RX1 RX0

0

This register is used for controlling data reception

on Endpoint 0. It is also reset by the USB bus re-

set.

Bit 7 = Forced by hardware to 1.

Bits 5:4 = STAT_RX [1:0] Status bits, for reception

transfers.

These bits contain the information about the end-

point status, which are listed below:

Bits 6:4 = Refer to the EPnRB register for a de-

scription of these bits.

STAT_RX1 STAT_RX0 Meaning

DISABLED: reception

transfers cannot be exe-

cuted.

Bits 3:0 = Forced by hardware to 0.

0

1

STALL: the endpoint is

stalled and all reception

requests result in

STALL handshake.

a

72/132

ST7263B

USB INTERFACE (Cont’d)

11.4.5 Programming Considerations

tively) must not be modified by software, as the

hardware can change their value on the fly.

The interaction between the USB interface and the

application program is described below. Apart

from system reset, action is always initiated by the

USB interface, driven by one of the USB events

associated with the Interrupt Status Register (IS-

TR) bits.

When the operation is completed, they can be ac-

cessed again to enable a new operation.

11.4.5.4 Interrupt Handling

Start of Frame (SOF)

The interrupt service routine may monitor the SOF

events for a 1 ms synchronization event to the

USB bus. This interrupt is generated at the end of

a resume sequence and can also be used to de-

tect this event.

11.4.5.1 Initializing the Registers

At system reset, the software must initialize all reg-

isters to enable the USB interface to properly gen-

erate interrupts and DMA requests.

1. Initialize the DMAR, IDR, and IMR registers

(choice of enabled interrupts, address of DMA

buffers). Refer the paragraph titled initializing

the DMA Buffers.

USB Reset (RESET)

When this event occurs, the DADDR register is re-

set, and communication is disabled in all endpoint

registers (the USB interface will not respond to any

packet). Software is responsible for reenabling

endpoint 0 within 10 ms of the end of reset. To do

this, set the STAT_RX bits in the EP0RB register

to VALID.

2. Initialize the EP0RA and EP0RB registers to

enable accesses to address 0 and endpoint 0

to support USB enumeration. Refer to the para-

graph titled Endpoint Initialization.

3. When addresses are received through this

channel, update the content of the DADDR.

Suspend (SUSP)

The CPU is warned about the lack of bus activity

for more than 3 ms, which is a suspend request.

The software should set the USB interface to sus-

pend mode and execute an ST7 HALT instruction

to meet the USB-specified power constraints.

4. If needed, write the endpoint numbers in the EA

fields in the EP1RB and EP2RB register.

11.4.5.2 Initializing DMA buffers

The DMA buffers are a contiguous zone of memo-

ry whose maximum size is 48 bytes. They can be

placed anywhere in the memory space to enable

the reception of messages. The 10 most signifi-

cant bits of the start of this memory area are spec-

ified by bits DA15-DA6 in registers DMAR and

IDR, the remaining bits are 0. The memory map is

shown in Figure 38.

End Suspend (ESUSP)

The CPU is alerted by activity on the USB, which

causes an ESUSP interrupt. The ST7 automatical-

ly terminates HALT mode.

Correct Transfer (CTR)

1. When this event occurs, the hardware automat-

ically sets the STAT_TX or STAT_RX to NAK.

Note: Every valid endpoint is NAKed until soft-

ware clears the CTR bit in the ISTR register,

independently of the endpoint number

addressed by the transfer which generated the

CTR interrupt.

Each buffer is filled starting from the bottom (last 3

address bits=000) up.

11.4.5.3 Endpoint Initialization

To be ready to receive:

Set STAT_RX to VALID (11b) in EP0RB to enable

reception.

Note: If the event triggering the CTR interrupt is

a SETUP transaction, both STAT_TX and

STAT_RX are set to NAK.

To be ready to transmit:

1. Write the data in the DMA transmit buffer.

2. Read the PIDR to obtain the token and the IDR

to get the endpoint number related to the last

transfer.

2. In register EPnRA, specify the number of bytes

to be transmitted in the TBC field

Note: When a CTR interrupt occurs, the TP3-

TP2 bits in the PIDR register and EP1-EP0 bits

in the IDR register stay unchanged until the

CTR bit in the ISTR register is cleared.

3. Enable the endpoint by setting the STAT_TX

bits to VALID (11b) in EPnRA.

Note: Once transmission and/or reception are en-

abled, registers EPnRA and/or EPnRB (respec-

3. Clear the CTR bit in the ISTR register.

73/132

ST7263B

USB INTERFACE (Cont’d)

Table 20. USB Register Map and Reset Values

Address

(Hex.)

Register

Name

7

6

5

4

3

2

1

0

PIDR

TP3

TP2

0

RX_SEZ

RXD

0

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

Reset Value

DMAR

x

0

DA11

x

0

DA10

x

0

DA9

x

0

DA15

DA14

DA13

DA12

DA8

Reset Value

IDR

x

DA7

DA6

EP1

EP0

CNT3

0

CNT2

0

CNT1

0

CNT0

Reset Value

ISTR

x

0

SUSP

DOVR

CTR

ERR

IOVR

0

ESUSP

0

RESET

0

SOF

Reset Value

IMR

0

SUSPM

DOVRM

CTRM

ERRM

IOVRM ESUSPM RESETM

SOFM

Reset Value

CTLR

0

RESUME PDWN

FSUSP

FRES

Reset Value

DADDR

0

ADD6

0

ADD5

0

ADD4

0

1

0

ADD3

ADD2

ADD1

ADD0

Reset Value

EP0RA

0

ST_OUT

STAT_TX1 STAT_TX0

TBC3

TBC2

TBC1

TBC0

DTOG_TX

0

Reset Value

EP0RB

0

1

0

x

DTOG_RX STAT_RX1 STAT_RX0

0

Reset Value

EP1RA

0

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

EP1RB

0

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

EP2RA

0

ST_OUT DTOG_TX STAT_TX1 STAT_TX0

TBC3

x

TBC2

x

TBC1

x

TBC0

x

Reset Value

EP2RB

0

CTRL

0

DTOG_RX STAT_RX1 STAT_RX0

EA3

x

EA2

x

EA1

x

EA0

x

Reset Value

0

74/132

ST7263B

11.5 I²C BUS INTERFACE (I²C)

11.5.1 Introduction

handshake. The interrupts are enabled or disabled

by software. The interface is connected to the I²C

bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I²C bus

and a Fast I²C bus. This selection is made by soft-

ware.

The I²C Bus Interface serves as an interface be-

tween the microcontroller and the serial I²C bus. It

provides both multimaster and slave functions,

and controls all I²C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I²C

mode (400 kHz).

Mode Selection

11.5.2 Main Features

The interface can operate in the four following

modes:

■ Parallel-bus/I²C protocol converter

■ Multi-master capability

■ 7-bit Addressing

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

■ Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

I²C Master Features:

The interface automatically switches from slave to

master after it generates a START condition and

from master to slave in case of arbitration loss or a

STOP generation, this allows Multi-Master capa-

bility.

■ Clock generation

■ I²C bus busy flag

Communication Flow

■ Arbitration Lost Flag

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condition and ends with

a stop condition. Both start and stop conditions are

generated in master mode by software.

■ End of byte transmission flag

■ Transmitter/Receiver Flag

■ Start bit detection flag

■ Start and Stop generation

I²C Slave Features:

In Slave mode, the interface is capable of recog-

nising its own address (7-bit), and the General Call

address. The General Call address detection may

be enabled or disabled by software.

■ Stop bit detection

■ I²C bus busy flag

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte following the start condi-

tion is the address byte; it is always transmitted in

Master mode.

■ Detection of misplaced start or stop condition

■ Programmable I²C Address detection

■ Transfer problem detection

■ End-of-byte transmission flag

■ Transmitter/Receiver flag

11.5.3 General Description

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, during which the receiver must send

an acknowledge bit to the transmitter. Refer to Fig-

ure 39.

In addition to receiving and transmitting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

Figure 39. I²C BUS Protocol

SDA

MSB

ACK

SCL

1

2

8

9

START

STOP

CONDITION

VR02119B

75/132

ST7263B

I²C BUS INTERFACE (Cont’d)

The Acknowledge function may be enabled and

disabled by software.

The SCL frequency (F

grammable clock divider which depends on the I²C

bus mode.

) is controlled by a pro-

SCL

The I²C interface address and/or general call ad-

dress can be selected by software.

When the I²C cell is enabled, the SDA and SCL

ports must be configured as floating open-drain

output or floating input. In this case, the value of

the external pull-up resistor used depends on the

application.

The speed of the I²C interface may be selected be-

tween Standard (0-100 kHz) and Fast I²C (100-

400 kHz).

When the I²C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the microcontroller to

read the byte in the Data Register.

Figure 40. I²C Interface Block Diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

SDAI

DATA CONTROL

SDA

COMPARATOR

OWN ADDRESS REGISTER (OAR)

SCLI

CLOCK CONTROL

SCL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

CONTROL LOGIC

INTERRUPT

76/132

ST7263B

I²C BUS INTERFACE (Cont’d)

11.5.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

11.5.7. for the bit definitions.

The slave waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 41 Transfer sequencing

EV3).

By default the I²C interface operates in Slave

mode (M/SL bit is cleared) except when it initiates

a transmit or receive sequence.

When the acknowledge pulse is received:

11.5.4.1 Slave Mode

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

address of the interface or the General Call

address (if selected by software).

Closing Slave Communication

After the last data byte is transferred a Stop Con-

dition is generated by the master. The interface

detects this condition and sets:

Address not matched: the interface ignores it

and waits for another Start condition.

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Address matched: the interface generates in se-

quence:

Then the interface waits for a read of the SR2 reg-

ister (see Figure 41 Transfer sequencing EV4).

– An Acknowledge pulse is generated if the ACK

bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set with an interrupt if the ITE bit

is set.

If it is a Stop condition, then the interface dis-

cards the data, released the lines and waits for

another Start condition.

Then the interface waits for a read of the SR1 reg-

ister, holding the SCL line low (see Figure 41

Transfer sequencing EV1).

Next, software must read the DR register to deter-

mine from the least significant bit if the slave must

enter Receiver or Transmitter mode.

If it is a Start condition, then the interface dis-

cards the data and waits for the next slave ad-

dress on the bus.

Slave Receiver

Following the address reception and after SR1

register has been read, the slave receives bytes

from the SDA line into the DR register via the inter-

nal shift register. After each byte the interface gen-

erates in sequence:

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

Note: In both cases, the SCL line is not held low;

however, the SDA line can remain low due to pos-

sible “0” bits transmitted last. It is then necessary

to release both lines by software.

– An Acknowledge pulse is generated if the ACK

bit is set

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

How to Release the SDA / SCL lines

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 41 Transfer se-

quencing EV2).

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

Slave Transmitter

Following the address reception and after the SR1

register has been read, the slave sends bytes from

the DR register to the SDA line via the internal shift

register.

77/132

ST7263B

I²C BUS INTERFACE (Cont’d)

11.5.4.2 Master Mode

To close the communication: before reading the

last byte from the DR register, set the STOP bit to

generate the Stop condition. The interface returns

automatically to slave mode (M/SL bit cleared).

To switch from default Slave mode to Master

mode, a Start condition generation is needed.

Note: In order to generate the non-acknowledge

pulse after the last received data byte, the ACK bit

must be cleared just before reading the second

last data byte.

Start Condition and Transmit Slave Address

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condi-

tion.

Master Transmitter

Once the Start condition is sent:

Following the address transmission and after SR1

register has been read, the master sends bytes

from the DR register to the SDA line via the inter-

nal shift register.

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the DR register with the

Slave address byte, holding the SCL line low

(see Figure 41 Transfer sequencing EV5).

The master waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 41 Transfer sequencing

EV8).

Then the slave address byte is sent to the SDA

line via the internal shift register.

When the acknowledge bit is received, the

interface sets:

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

– EVF and BTF bits with an interrupt if the ITE bit

is set.

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

To close the communication: after writing the last

byte to the DR register, set the STOP bit to gener-

ate the Stop condition. The interface goes auto-

matically back to slave mode (M/SL bit cleared).

Then the master waits for a read of the SR1 regis-

ter followed by a write in the CR register (for exam-

ple set PE bit), holding the SCL line low (see Fig-

ure 41 Transfer sequencing EV6).

Next the master must enter Receiver or Transmit-

ter mode.

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt

if the ITE bit is set.

Master Receiver

Following the address transmission and after the

SR1 and CR registers have been accessed, the

master receives bytes from the SDA line into the

DR register via the internal shift register. After

each byte the interface generates in sequence:

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with

an interrupt if the ITE bit is set and the interface

goes automatically back to slave mode (the M/SL

bit is cleared).

– An Acknowledge pulse is generated if if the ACK

bit is set

– EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 41 Transfer se-

quencing EV7).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low due to

possible “0” bits transmitted last. It is then neces-

sary to release both lines by software.

78/132

ST7263B

I²C BUS INTERFACE (Cont’d)

Figure 41. Transfer Sequencing

Slave Receiver

S

Address

A

Data1

A

Data2

EV3

A

DataN

A

P

.....

EV1

EV2

A

EV2

A

EV2

NA

EV4

P

Slave Transmitter

S

Address

A

Data1

Data2

DataN

.....

EV1 EV3

EV3

EV3-1

EV4

Master Receiver

S

Address

A

Data1

A

Data2

A

DataN NA

P

EV5

EV6

EV7

A

EV7

A

EV7

A

Master Transmitter

S

Address

A

Data1

Data2

DataN

P

.....

EV5

EV6 EV8

EV8

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading the SR1 register.

EV2: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV3: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading the SR1 register. The BTF is cleared

by releasing the lines (STOP=1, STOP=0) or by writing the DR register (DR=FFh).

Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading the SR2 register.

EV5: EVF=1, SB=1, cleared by reading the SR1 register followed by writing the DR register.

EV6: EVF=1, cleared by reading the SR1 register followed by writing the CR register

(for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading the SR1 register followed by reading the DR register.

EV8: EVF=1, BTF=1, cleared by reading the SR1 register followed by writing the DR register.

79/132

ST7263B

I²C BUS INTERFACE (Cont’d)

11.5.5 Low Power Modes

Mode

Description

No effect on I²C interface.

I²C interrupts exit from Wait mode.

I²C registers are frozen.

WAIT

In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C

interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt

mode” capability.

HALT

11.5.6 Interrupts

Figure 42. Event Flags and Interrupt Generation

BTF

ADSL

SB

ITE

AF

INTERRUPT

EVF

STOPF

ARLO

BERR

*

* EVF can also be set by EV6 or an error from the SR2 register.

Enable

Control from

Bit

Exit

from

Halt

Event

Flag

Interrupt Event

Wait

Yes

End of Byte Transfer Event

BTF

ADSEL

SB

No

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

AF

ITE

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

STOPF

ARLO

BERR

The I²C interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC

register is reset (RIM instruction).

80/132

ST7263B

I²C BUS INTERFACE (Cont’d)

11.5.7 Register Description

Bit 2 = ACK Acknowledge enable.

I²C CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

7

0

0: No acknowledge returned

1: Acknowledge returned after an address byte or

a data byte is received

0

PE

ENGC START ACK STOP

ITE

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also

cleared by hardware in master mode. Note: This

bit is not cleared when the interface is disabled

(PE=0).

Bits 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Notes:

– When PE=0, all the bits of the CR register and

the SR register except the Stop bit are reset. All

outputs are released while PE=0

– In Master mode:

0: No stop generation

1: Stop generation after the current byte transfer

or after the current Start condition is sent. The

STOP bit is cleared by hardware when the Stop

condition is sent.

– When PE=1, the corresponding I/O pins are se-

lected by hardware as alternate functions.

– To enable the I²C interface, write the CR register

TWICE with PE=1 as the first write only activates

the interface (only PE is set).

– In Slave mode:

0: No stop generation

1: Release the SCL and SDA lines after the cur-

rent byte transfer (BTF=1). In this mode the

STOP bit has to be cleared by software.

Bit 4 = ENGC Enable General Call.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0). The 00h General Call address is ac-

knowledged (01h ignored).

0: General Call disabled

1: General Call enabled

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared

by hardware when the interface is disabled

(PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to Figure 42 for the relationship between the

events and the interrupt.

Bit 3 = START Generation of a Start condition.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0) or when the Start condition is sent

(with interrupt generation if ITE=1).

SCL is held low when the SB, BTF or ADSL flags

or an EV6 event (See Figure 41) is detected.

– In master mode:

0: No start generation

1: Repeated start generation

– In slave mode:

0: No start generation

1: Start generation when the bus is free

81/132

ST7263B

I²C BUS INTERFACE (Cont’d)

I²C STATUS REGISTER 1 (SR1)

Read Only

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is cor-

rectly received or transmitted with interrupt gener-

ation if ITE=1. It is cleared by software reading

SR1 register followed by a read or write of DR reg-

ister. It is also cleared by hardware when the inter-

face is disabled (PE=0).

Reset Value: 0000 0000 (00h)

7

0

EVF

0

TRA BUSY BTF ADSL M/SL

SB

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In

case an address byte is sent, this bit is set only

after the EV6 event (See Figure 41). BTF is

cleared by reading SR1 register followed by writ-

ing the next byte in DR register.

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event oc-

curs. It is cleared by software reading SR2 register

in case of error event or as described in Figure 41.

It is also cleared by hardware when the interface is

disabled (PE=0).

0: No event

1: One of the following events has occurred:

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

– BTF=1 (Byte received or transmitted)

The SCL line is held low while BTF=1.

– ADSL=1 (Address matched in Slave mode

while ACK=1)

0: Byte transfer not done

1: Byte transfer succeeded

– SB=1 (Start condition generated in Master

mode)

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received

slave address matched with the OAR register con-

tent or a general call is recognized. An interrupt is

generated if ITE=1. It is cleared by software read-

ing SR1 register or by hardware when the inter-

face is disabled (PE=0).

– AF=1 (No acknowledge received after byte

transmission)

– STOPF=1 (Stop condition detected in Slave

mode)

– ARLO=1 (Arbitration lost in Master mode)

– BERR=1 (Bus error, misplaced Start or Stop

condition detected)

The SCL line is held low while ADSL=1.

– Address byte successfully transmitted in Mas-

ter mode.

0: Address mismatched or not received

1: Received address matched

Bit 6 = Reserved. Forced to 0 by hardware.

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface

is in Master mode (writing START=1). It is cleared

by hardware after detecting a Stop condition on

the bus or a loss of arbitration (ARLO=1). It is also

cleared when the interface is disabled (PE=0).

0: Slave mode

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after de-

tection of Stop condition (STOPF=1), loss of bus

arbitration (ARLO=1) or when the interface is disa-

bled (PE=0).

1: Master mode

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start

condition is generated (following

a

write

START=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR1 register followed

by writing the address byte in DR register. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: No Start condition

1: Start condition generated

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start

condition and cleared by hardware on detection of

a Stop condition. It indicates a communication in

progress on the bus. This information is still updat-

ed when the interface is disabled (PE=0).

0: No communication on the bus

1: Communication ongoing on the bus

82/132

ST7263B

I²C BUS INTERFACE (Cont’d)

I²C STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

es the arbitration of the bus to another master. An

interrupt is generated if ITE=1. It is cleared by soft-

ware reading SR2 register or by hardware when

the interface is disabled (PE=0).

7

0

After an ARLO event the interface switches back

automatically to Slave mode (M/SL=0).

0

AF STOPF ARLO BERR GCAL

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Bits 7:5 = Reserved. Forced to 0 by hardware.

Bit 1 = BERR Bus error.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when the interface de-

tects a misplaced Start or Stop condition. An inter-

rupt is generated if ITE=1. It is cleared by software

reading SR2 register or by hardware when the in-

terface is disabled (PE=0).

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1.

The SCL line is not held low while BERR=1.

0: No acknowledge failure

1: Acknowledge failure

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition

is detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call ad-

dress is detected on the bus while ENGC=1. It is

cleared by hardware detecting a Stop condition

(STOPF=1) or when the interface is disabled

(PE=0).

The SCL line is not held low while STOPF=1.

0: No general call address detected on bus

1: general call address detected on bus

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface los-

83/132

ST7263B

I²C BUS INTERFACE (Cont’d)

I²C CLOCK CONTROL REGISTER (CCR)

I²C OWN ADDRESS REGISTER (OAR)

Read / Write

Reset Value: 0000 0000 (00h)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

7

0

FM/SM CC6

CC5

CC4

CC3

CC2

CC1

CC0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

Bit 7 = FM/SM Fast/Standard I²C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I²C mode

Bits 7:1 = ADD7-ADD1 Interface address.

These bits define the I²C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

1: Fast I²C mode

Bits 6:0 = CC6-CC0 7-bit clock divider.

These bits select the speed of the bus (F

pending on the I²C mode. They are not cleared

when the interface is disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

) de-

SCL

– Standard mode (FM/SM=0): F

<= 100kHz

SCL

Note: Address 01h is always ignored.

F

= f

/(2x([CC6..CC0]+2))

CPU

SCL

– Fast mode (FM/SM=1): F

> 100kHz

SCL

F

= f

/(3x([CC6..CC0]+2))

CPU

SCL

Note: The programmed F

SCL and SDA lines.

assumes no load on

SCL

I²C DATA REGISTER (DR)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

D7

D6

D5

D4

D3

D2

D1

D0

Bits 7:0 = D7-D0 8-bit Data Register.

These bits contains the byte to be received or

transmitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the next data bytes are received one by

one after reading the DR register.

84/132

ST7263B

Table 21. I²C Register Map

Address

(Hex.)

39

Register

Name

7

6

5

4

3

2

1

0

DR

OAR

CCR

SR2

SR1

CR

DR7 .. DR0

ADD7 .. ADD0

CC6 .. CC0

3B

3C

FM/SM

EVF

3D

AF

STOPF

BTF

ARLO

ADSL

ACK

BERR

M/SL

GCAL

SB

3E

TRA

PE

BUSY

ENGC

3F

START

STOP

ITE

85/132

ST7263B

11.6 8-BIT A/D CONVERTER (ADC)

11.6.1 Introduction

11.6.3 Functional Description

11.6.3.1 Analog Power Supply

The on-chip Analog to Digital Converter (ADC) pe-

ripheral is a 8-bit, successive approximation con-

verter with internal sample and hold circuitry. This

peripheral has up to 16 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 16 different sources.

V

and V

are the high and low level refer-

SSA

DDA

ence voltage pins. In some devices (refer to device

pin out description) they are internally connected

to the V and V pins.

DD

SS

Conversion accuracy may therefore be impacted

by voltage drops and noise in the event of heavily

loaded or badly decoupled power supply lines.

The result of the conversion is stored in a 8-bit

Data Register. The A/D converter is controlled

through a Control/Status Register.

See electrical characteristics section for more de-

tails.

11.6.2 Main Features

■ 8-bit conversion

■ Up to 16 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 43.

Figure 43. ADC Block Diagram

f

ADC

CPU

DIV 4

COCO

0

ADON

4

0

CH3 CH2 CH1 CH0

ADCCSR

AIN0

AIN1

HOLD CONTROL

R

ADC

ANALOG TO DIGITAL

CONVERTER

ANALOG

MUX

AINx

C

ADC

ADCDR

D7

D6

D5

D4

D3

D2

D1

D0

86/132

ST7263B

8-BIT A/D CONVERTER (ADC) (Cont’d)

11.6.3.2 Digital A/D Conversion Result

The analog input ports must be configured as in-

put, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input.

The conversion is monotonic, meaning that the re-

sult never decreases if the analog input does not

and never increases if the analog input does not.

If the input voltage (V ) is greater than or equal

AIN

In the CSR register:

to V

(high-level voltage reference) then the

DDA

conversion result in the DR register is FFh (full

scale) without overflow indication.

– Select the CH[3:0] bits to assign the analog

channel to be converted.

ADC Conversion

If input voltage (V ) is lower than or equal to

AIN

V

(low-level voltage reference) then the con-

version result in the DR register is 00h.

SSA

In the CSR register:

– Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conver-

sion of the selected channel.

The A/D converter is linear and the digital result of

the conversion is stored in the ADCDR register.

The accuracy of the conversion is described in the

parametric section.

When a conversion is complete

R

is the maximum recommended impedance

– The COCO bit is set by hardware.

– No interrupt is generated.

– The result is in the DR register and remains

valid until the next conversion has ended.

AIN

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

A write to the CSR register (with ADON set) aborts

the current conversion, resets the COCO bit and

starts a new conversion.

11.6.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion

phases as shown in Figure 44:

Figure 44. ADC Conversion Timings

■ Sample capacitor loading [duration: t

]

LOAD

During this phase, the V

input voltage to be

AIN

ADON

measured is loaded into the C

capacitor.

sample

ADC

ADCCSR WRITE

OPERATION

t

CONV

■ A/D conversion [duration: t

]

CONV

During this phase, the A/D conversion is

computed (8 successive approximations cycles)

HOLD

CONTROL

and the C

sample capacitor is disconnected

ADC

from the analog input pin to get the optimum

analog to digital conversion accuracy.

t

LOAD

COCO BIT SET

While the ADC is on, these two phases are contin-

uously repeated.

11.6.4 Low Power Modes

At the end of each conversion, the sample capaci-

tor is kept loaded with the previous measurement

load. The advantage of this behaviour is that it

minimizes the current consumption on the analog

pin in case of single input channel measurement.

Mode

WAIT

Description

No effect on A/D Converter

A/D Converter disabled.

After wakeup from Halt mode, the A/D Con-

verter requires a stabilisation time before ac-

curate conversions can be performed.

HALT

11.6.3.4 Software Procedure

Refer to the control/status register (CSR) and data

register (DR) in Section 11.6.6 for the bit defini-

tions and to Figure 44 for the timings.

Note: The A/D converter may be disabled by reset-

ting the ADON bit. This feature allows reduced

power consumption when no conversion is needed

and between single shot conversions.

ADC Configuration

The total duration of the A/D conversion is 12 ADC

11.6.5 Interrupts

clock periods (1/f

=4/f

).

ADC

CPU

None

87/132

ST7263B

8-BIT A/D CONVERTER (ADC) (Cont’d)

11.6.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

7

0

7

0

COCO

0

ADON

0

CH3

CH2

CH1

CH0

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7 = COCO Conversion Complete

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete

1: Conversion can be read from the DR register

Bits 7:0 = D[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Note: Reading this register reset the COCO flag.

Bit 6 = Reserved. must always be cleared.

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 4 = Reserved. must always be cleared.

Bits 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Channel Pin*

CH3 CH2 CH1 CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

*Note: The number of pins AND the channel selec-

tion varies according to the device. Refer to the de-

vice pinout.

88/132

ST7263B

8-BIT A/D CONVERTER (ADC) (Cont’d)

Table 22. ADC Register Map

Address

(Hex.)

0Ah

Register

Name

7

6

0

5

4

3

2

1

0

DR

AD7 .. AD0

0Bh

CSR

COCO

ADON

0

CH2

CH1

CH0

89/132

ST7263B

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

The ST7 Core features 17 different addressing

modes which can be classified in 7 main groups:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

Addressing Mode

Inherent

Example

nop

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

Immediate

Direct

ld A,#$55

ld A,$55

Indexed

ld A,($55,X)

ld A,([$55],X)

jrne loop

Indirect

Relative

Bit operation

bset byte,#5

The ST7 Assembler optimizes the use of long and

short addressing modes.

The ST7 Instruction set is designed to minimize

the number of bytes required per instruction: To do

Table 23. ST7 Addressing Mode Overview

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Destination/

Source

Length

(Bytes)

Mode

Syntax

Inherent

Immediate

Short

nop

+ 0

+ 1

+ 2

ld A,#$55

ld A,$10

Direct

00..FF

Long

ld A,$1000

0000..FFFF

+ 0 (with X register)

+ 1 (with Y register)

No Offset

Direct

Indexed

ld A,(X)

00..FF

Short

Long

Short

Long

Short

Long

Relative

Bit

Direct

Indexed

ld A,($10,X)

ld A,($1000,X)

ld A,[$10]

00..1FE

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

Direct

0000..FFFF

00..FF

Indirect

Direct

00..FF

byte

word

byte

word

ld A,[$10.w]

ld A,([$10],X)

0000..FFFF

00..1FE

Indexed

ld A,([$10.w],X) 0000..FFFF

1)

jrne loop

PC-128/PC+127

Indirect

Direct

jrne [$10]

PC-128/PC+127

00..FF

byte

bset $10,#7

bset [$10],#7

Bit

Indirect

Direct

00..FF

Bit

Relative btjt $10,#7,skip 00..FF

Relative btjt [$10],#7,skip 00..FF

Bit

Indirect

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-

ing JRxx.

90/132

ST7263B

ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent

12.1.3 Direct

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to process the operation.

In Direct instructions, the operands are referenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Inherent Instruction

Function

No operation

Direct (short)

NOP

The address is a byte, thus requires only one byte

after the opcode, but only allows 00 - FF address-

ing space.

TRAP

S/W Interrupt

Wait For Interrupt (Low Power

Mode)

WFI

Direct (long)

Halt Oscillator (Lowest Power

Mode)

HALT

The address is a word, thus allowing 64 Kbyte ad-

dressing space, but requires 2 bytes after the op-

code.

RET

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask

Reset Interrupt Mask

Set Carry Flag

IRET

SIM

12.1.4 Indexed (No Offset, Short, Long)

RIM

In this mode, the operand is referenced by its

memory address, which is defined by the unsigned

addition of an index register (X or Y) with an offset.

SCF

RCF

Reset Carry Flag

Reset Stack Pointer

Load

The indirect addressing mode consists of three

sub-modes:

RSP

LD

Indexed (No Offset)

CLR

Clear

There is no offset, (no extra byte after the opcode),

and allows 00 - FF addressing space.

PUSH/POP

INC/DEC

TNZ

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Indexed (Short)

The offset is a byte, thus requires only one byte af-

ter the opcode and allows 00 - 1FE addressing

space.

CPL, NEG

MUL

Indexed (long)

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

Swap Nibbles

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

SWAP

12.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found

by its memory address, located in memory (point-

er).

Immediate Instruction

Function

The pointer address follows the opcode. The indi-

rect addressing mode consists of two sub-modes:

LD

Load

CP

Compare

Indirect (short)

BCP

Bit Compare

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

AND, OR, XOR

ADC, ADD, SUB, SBC

Logical Operations

Arithmetic Operations

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

91/132

ST7263B

ST7 ADDRESSING MODES (Cont’d)

12.1.6 Indirect Indexed (Short, Long)

SWAP

Swap Nibbles

This is a combination of indirect and short indexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

CALL, JP

Call or Jump subroutine

12.1.7 Relative Mode (Direct, Indirect)

This addressing mode is used to modify the PC

register value by adding an 8-bit signed offset to it.

Available Relative Direct/

Function

The indirect indexed addressing mode consists of

two sub-modes:

Indirect Instructions

JRxx

Conditional Jump

Call Relative

Indirect Indexed (Short)

CALLR

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and requires 1 byte after the opcode.

The relative addressing mode consists of two sub-

modes:

Indirect Indexed (Long)

Relative (Direct)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requires 1 byte after the opcode.

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory, of which the ad-

dress follows the opcode.

Table 24. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Function

Instructions

LD

Load

CP

Compare

AND, OR, XOR

Logical Operations

Arithmetic Addition/subtrac-

tion operations

ADC, ADD, SUB, SBC

BCP

Bit Compare

Short Instructions Only

CLR

Function

Clear

INC, DEC

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

TNZ

CPL, NEG

BSET, BRES

Bit Test and Jump Opera-

tions

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations

92/132

ST7263B

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in

the following table:

Load and Transfer

LD

CLR

POP

DEC

TNZ

OR

Stack operation

PUSH

INC

RSP

BCP

Increment/Decrement

Compare and Tests

Logical operations

CP

AND

BSET

BTJT

ADC

SLL

XOR

CPL

NEG

Bit Operation

BRES

BTJF

ADD

SRL

JRT

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

SUB

SRA

JRF

SBC

RLC

JP

MUL

RRC

CALL

SWAP

CALLR

SLA

Unconditional Jump or Call

Conditional Branch

JRA

JRxx

TRAP

SIM

NOP

RET

Interruption management

Condition Code Flag modification

WFI

RIM

HALT

SCF

IRET

RCF

Using a pre-byte

The instructions are described with one to four

bytes.

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or

the instruction using direct addressing mode. The

prebytes are:

In order to extend the number of available op-

codes for an 8-bit CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

PDY 90 Replace an X based instruction using

immediate, direct, indexed, or inherent

addressing mode by a Y one.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PIX 92 Replace an instruction using direct, di-

rect bit, or direct relative addressing

mode to an instruction using the corre-

sponding indirect addressing mode.

It also changes an instruction using X

indexed addressing mode to an instruc-

tion using indirect X indexed addressing

mode.

PC

Opcode

PC+1 Additional word (0 to 2) according to the

number of bytes required to compute the

effective address

PIY 91 Replace an instruction using X indirect

indexed addressing mode by a Y one.

93/132

ST7263B

INSTRUCTION GROUPS (Cont’d)

Mnemo

ADC

ADD

AND

BCP

Description

Add with Carry

Function/Example

A = A + M + C

A = A + M

Dst

Src

H

I

N

Z

C

A

M

Addition

A

Logical And

A = A . M

A

Bit compare A, Memory

Bit Reset

tst (A . M)

A

BRES

BSET

BTJF

BTJT

CALL

CALLR

CLR

bres Byte, #3

bset Byte, #3

btjf Byte, #3, Jmp1

btjt Byte, #3, Jmp1

M

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Call subroutine relative

Clear

C

reg, M

reg

0

N

1

Z

CP

Arithmetic Compare

One Complement

Decrement

tst(Reg - M)

A = FFH-A

dec Y

M

C

1

CPL

reg, M

DEC

HALT

IRET

INC

Halt

0

I

Interrupt routine return

Increment

Pop CC, A, X, PC

inc X

H

N

Z

C

reg, M

JP

Absolute Jump

Jump relative always

Jump relative

jp [TBL.w]

JRA

JRT

JRF

Never jump

jrf *

JRIH

JRIL

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

JRH

H = 1 ?

JRNH

JRM

Jump if H = 0

H = 0 ?

Jump if I = 1

I = 1 ?

JRNM

JRMI

JRPL

JREQ

JRNE

JRC

Jump if I = 0

I = 0 ?

Jump if N = 1 (minus)

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

JRNC

JRULT

Jump if C = 0

C = 0 ?

Jump if C = 1

Unsigned <

Jmp if unsigned >=

Unsigned >

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

94/132

ST7263B

INSTRUCTION GROUPS (Cont’d)

Mnemo

JRULE

LD

Description

Jump if (C + Z = 1)

Load

Function/Example

Unsigned <=

dst <= src

Dst

Src

H

I

N

Z

C

reg, M

A, X, Y

reg, M

M, reg

X, Y, A

MUL

NEG

NOP

OR

Multiply

X,A = X * A

0

Negate (2’s compl)

No Operation

OR operation

Pop from the Stack

neg $10

C

A = A + M

pop reg

pop CC

push Y

C = 0

A

M

POP

reg

CC

M

H

I

C

0

PUSH

RCF

RET

RIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with Carry

Set carry flag

reg, CC

I = 0

0

RLC

RRC

RSP

SBC

SCF

SIM

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

reg, M

N

Z

C

A

M

N

Z

C

1

Disable Interrupts

Shift left Arithmetic

Shift left Logic

I = 1

1

SLA

C <= Dst <= 0

0 => Dst => C

Dst7 => Dst => C

A = A - M

reg, M

A

N

0

Z

C

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

Shift right Logic

Shift right Arithmetic

Subtraction

N

M

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

tnz lbl1

Test for Neg & Zero

S/W trap

S/W interrupt

1

0

Wait for Interrupt

Exclusive OR

XOR

A = A XOR M

A

M

N

Z

95/132

ST7263B

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-

Figure 46. Pin input voltage

ferred to V

.

SS

13.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and max-

imum values are guaranteed in the worst condi-

tions of ambient temperature, supply voltage and

frequencies by tests in production on 100% of the

ST7 PIN

V

IN

devices with an ambient temperature at T =25°C

A

and T =T max (given by the selected temperature

A

range).

Data based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. Based on characterization, the min-

imum and maximum values refer to sample tests

and represent the mean value plus or minus three

times the standard deviation (mean±3Σ).

13.1.2 Typical values

Unless otherwise specified, typical data are based

on T =25°C, V =5V. They are given only as de-

A

DD

sign guidelines and are not tested.

13.1.3 Typical curves

Unless otherwise specified, all typical curves are

given only as design guidelines and are not tested.

13.1.4 Loading capacitor

The loading conditions used for pin parameter

measurement are shown in Figure 45.

Figure 45. Pin loading conditions

ST7 PIN

C

L

13.1.5 Pin input voltage

The input voltage measurement on a pin of the de-

vice is described in Figure 46.

96/132

ST7263B

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

13.2.1 Voltage Characteristics

Symbol

- V

Ratings

Maximum value

6.0

Unit

V

Supply voltage

DD

SS

Input voltage on true open drain pins

Input voltage on any other pin

V_SS-0.3 to 6.0

V

1) & 2)

V

IN

V

_SS-0.3 to V_DD+0.3

See “Absolute Electrical Sensitivity”

on page 105.

V

Electro-static discharge voltage (Human Body Model)

ESD(HBM)

13.2.2 Current Characteristics

Symbol

Ratings

Maximum value

Unit

3)

I

Total current into V power lines (source)

80

VDD

DD

I

Total current out of V ground lines (sink)

SS

VSS

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

25

I

50

IO

Output current source by any I/Os and control pin

- 25

TBD

± 5

TBD

± 20

mA

Injected current on V pin

PP

Injected current on RESET pin

2) & 4)

I

INJ(PIN)

Injected current on OSCIN and OSCOUT pins

5) & 6)

Injected current on any other pin

2)

5)

ΣI

Total injected current (sum of all I/O and control pins)

INJ(PIN)

Notes:

1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset

DD

SS

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.

DD

SS

2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to

IN

I

specification. A positive injection is induced by V >V while a negative injection is induced by V <V

.

INJ(PIN)

IN

DD

IN

SS

3. All power (V ) and ground (V ) lines must always be connected to the external supply.

DD

SS

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout

the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage

is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as

far as possible from the analog input pins.

5. When several inputs are submitted to a current injection, the maximum ΣI

is the absolute sum of the positive

INJ(PIN)

and negative injected currents (instantaneous values). These results are based on characterisation with ΣI

maxi-

INJ(PIN)

mum current injection on four I/O port pins of the device.

6. True open drain I/O port pins do not accept positive injection.

13.2.3 Thermal Characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

-65 to +150

TBD

Unit

T

°C

STG

T

J

97/132

ST7263B

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Operating Supply Voltage

(No USB)

V

f

= 8 MHz

CPU

4

5

5.5

DD

V

Analog reference voltage

V

DDA

DD

V

SSA

SS

f

= 24 MHz

= 12 MHz

8

4

OSC

Operating frequency

f

MHz

CPU

OSC

Ambient temperature range

T

0

70

°C

A

Figure 47. f

Maximum Operating Frequency Versus V_DDSupply Voltage

CPU

f

[MHz]

8

CPU

FUNCTIONALITY

GUARANTEED

FROM 4 TO 5.5 V

4

2

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

0

SUPPLY VOLTAGE [V]

2.5

3.0

3.5

4

4.5

5

5.5

98/132

ST7263B

OPERATING CONDITIONS (Cont’d)

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V , f

, and T . Refer to Figure 9 on page 17.

DD CPU

A

1)

Symbol

Parameter

Conditions

Min

3.6

3.3

180

0.5

Typ

3.7

Max Unit

Low Voltage Reset Threshold (V rising)

V

Max. Variation 50V/ms

3.8

3.7

220

50

V

DD

IT+

Low Voltage Reset Threshold (V falling)

3.5

V

DD

IT-

Hysteresis (V - V

)

200

mV

V/ms

IT+

IT-

2)

hyst

Vt

V

rise time rate

POR

DD

Notes:

1. Not tested, guaranteed by design.

2. The V rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

DD

99/132

ST7263B

13.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for

the ST7 functional operating modes over tempera-

ture range does not take into account the clock

source current consumption. To get the total de-

vice consumption, the two current values must be

added (except for HALT mode for which the clock

is stopped).

1)

Symbol

∆I

Parameter

Supply current variation vs. temperature Constant V and f

CPU

Conditions

Typ

Max

Unit

10

%

DD(∆Ta)

DD

2)

f

= 4 MHz

= 8 MHz

= 4 MHz

= 8 MHz

7.5

12

9

CPU

CPU RUN mode

CPU WAIT mode

I/Os in input mode

mA

2)

13.5

7.5

6

2)

I

8.5

120

20

9.5

DD

3)

with LVD

150

30

CPU HALT mode

µA

3)

without LVD

4)

USB Suspend mode

120

150

Note 1: Typical data are based on T =25°C and not tested in production

A

Note 2: Oscillator and watchdog running.

All others peripherals disabled.

Note 3: USB Transceiver and ADC are powered down.

Note 4: Low voltage reset function enabled.

CPU in HALT mode.

Current consumption of external pull-up (1.5Kohms to USBVCC) and pull-down (15Kohms to V

)

SSA

not included.

Figure 48. Typ. I in RUN at 4 and 8 MHz f

Figure 49. Typ. I in WAIT at 4 and 8 MHz f

CPU

DD

CPU

DD

10

9

14

12

10

8

7

6

5

6

4

3

4

4 mHz

8 mHz

2

1

8 mHz

2

0

4

4.5

5

5.5

4

4.5

5

5.5

Vdd (V)

100/132

ST7263B

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V , f

, and T .

DD CPU

A

13.5.1 General Timings

1)

Symbol

Parameter

Conditions

Min

2

Typ

Max

12

Unit

t_CPU

ns

3

t

Instruction cycle time

f

=8MHz

c(INST)

CPU

250

10

375

1500

22

2)

t_CPU

µs

Interrupt reaction time

t

=8MHz

v(IT)

CPU

t

= ∆t

+ 10 t

1.25

2.75

v(IT)

c(INST) CPU

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch. ∆t_c(INST)is the number of t_CPUcycles needed to finish

the current instruction execution.

13.5.2 CONTROL TIMING CHARACTERISTICS

CONTROL TIMINGS

Value

Symbol

Parameter

Conditions

Unit

Min

Typ.

Max

24

8

f_OSC

f_CPU

Oscillator Frequency

Operating Frequency

External RESET

MHz

t_RL

1.5

514

200

t_CPU

ns

Input pulse Width

t_PORL

T_DOGL

Internal Power Reset Duration

Watchdog or Low Voltage Reset

Output Pulse Width

49152

6.144

3145728

393.216

t_CPU

ms

t_DOG

Watchdog Time-out

f_cpu= 8MHz

Crystal Oscillator

Start-up Time

t

20

30

40

ms

OXOV

t_DDR

Power up rise time

from V = 0 to 4V

100

DD

Note 1: The minimum period t_ILILshould not be less than the number of cycle times it takes to execute the

interrupt service routine plus 21 cycles.

101/132

ST7263B

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

13.5.3 External Clock Source

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V

OSCIN input pin high level voltage

OSCIN input pin low level voltage

0.7xV

V

DD

OSCINH

DD

V

0.3xV

DD

OSCINL

SS

t

1)

w(OSCINH)

see Figure 50

OSCIN high or low time

15

w(OSCINL)

ns

t

1)

r(OSCIN)

OSCIN rise or fall time

15

f(OSCIN)

I

OSCx Input leakage current

V

≤V ≤V

DD

±1

µA

L

SS

IN

Figure 50. Typical Application with an External Clock Source

90%

V

OSCINH

OSCINL

10%

t

w(OSCINH)

t

w(OSCINL)

f(OSCIN)

r(OSCIN)

OSCOUT

OSCIN

Not connected internally

f

OSC

EXTERNAL

CLOCK SOURCE

I

L

ST72XXX

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 51. Typical Application with a Crystal Resonator

i

2

f

OSC

C

L1

OSCIN

RESONATOR

R

F

C

L2

OSCOUT

ST72XXX

102/132

ST7263B

13.6 MEMORY CHARACTERISTICS

Subject to general operating conditions for f

, and T unless otherwise specified.

A

CPU

13.6.1 RAM and Hardware Registers

Symbol

Parameter

Conditions

HALT mode (or RESET)

Min

Typ

Max

Unit

1)

V

Data retention mode

2.0

V

RM

Note 1: Guaranteed by design. Not tested in production.

13.6.2 Flash Memory

Operating Conditions: f

= 8 MHz.

CPU

DUAL VOLTAGE FLASH MEMORY

Symbol

Parameter

Operating Frequency

Conditions

Read mode

Write / Erase mode,

T =25°C

Min

Typ

Max

Unit

8

f

MHz

CPU

8

A

V

Programming Voltage

Current

4.0V ≤V ≤ 5.5V

11.4

12.6

30

V

PP

DD

I

V

Write / Erase

mA

µs

PP

Byte Programming Time

330

0.8

2

t

PROG

Block Programming Time (16KB)

Sector Erasing Time (sector 0 ; 4KB)

Sector Erasing Time (sector 1 ; 4KB)

Sector Erasing Time (sector 2 ; 8KB)

T =25°C

A

s

t

2

ERASE

2.5

10

t

Internal V Stabilization Time

µs

VPP

PP

Data Retention

T

≤ 55°C

20

years

cycles

RET

A

N

Write Erase Cycles

T =25°C

100

RW

A

1)

Figure 52. Two typical Applications with V Pin

PP

V

PP

PROGRAMMING

TOOL

10kΩ

ST72XXX

Note 1: When the ICP mode is not required by the application, V pin must be tied to V

.

PP

SS

103/132

ST7263B

13.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-

sis during product characterization.

■ ESD: Electro-Static Discharge (positive and

negative) is applied on all pins of the device until

a functional disturbance occurs. This test

conforms with the IEC 1000-4-2 standard.

13.7.1 Functional EMS

(Electro Magnetic Susceptibility)

■ FTB: A Burst of Fast Transient voltage (positive

Based on a simple running application on the

product (toggling 2 LEDs through I/O ports), the

product is stressed by two electro magnetic events

until a failure occurs (indicated by the LEDs).

and negative) is applied to V and V through

DD

SS

a 100pF capacitor, until a functional disturbance

occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be re-

sumed.

1)

Symbol

Parameter

Conditions

=5V, T =+25°C, f

conforms to IEC 1000-4-2

Neg

Pos

Unit

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V

=8MHz

OSC

DD

A

V

1.5

1

FESD

kV

Fast transient voltage burst limits to be ap-

V

=5V, T =+25°C, f

=8MHz

OSC

DD

A

V

plied through 100pF on V and V pins

1.8

FFTB

DD

conforms to IEC 1000-4-4

to induce a functional disturbance

2)

Figure 53. EMC Recommended star network power supply connection

ST72XXX

10µF 0.1µF

V

DD

SS

ST7

DIGITAL NOISE

FILTERING

V

DD

POWER

SUPPLY

SOURCE

V

SSA

DDA

EXTERNAL

NOISE

FILTERING

0.1µF

Notes:

1. Data based on characterization results, not tested in production.

2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommen-

dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

104/132

ST7263B

EMC CHARACTERISTICS (Cont’d)

13.7.2 Absolute Electrical Sensitivity

– A discharge from C through R (body resistance)

to the ST7 occurs.

L

Based on three different tests (ESD, LU and DLU)

using specific measurement methods, the product

is stressed in order to determine its performance in

terms of electrical sensitivity. For more details, re-

fer to the AN1181 ST7 application note.

– S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in

charge state. S2 must be opened at least 10ms

prior to the delivery of the next pulse.

13.7.2.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (1 positive then 1 nega-

tive pulse separated by 1 second) are applied to

the pins of each sample according to each pin

combination. The sample size depends of the

number of supply pins of the device (3 parts*(n+1)

supply pin). The Human Body Model is simulated.

This test conforms to the JESD22-A114A stand-

ard. See Figure 54 and the following test sequenc-

es.

Human Body Model Test Sequence

– C is loaded through S1 by the HV pulse gener-

L

ator.

– S1 switches position from generator to R.

Absolute Maximum Ratings

1)

Symbol

Ratings

Conditions

Maximum value

Unit

Electro-static discharge voltage

(Human Body Model)

T =+25°C

V

2000

V

A

ESD(HBM)

Figure 54. Typical Equivalent ESD Circuits

S1

R=1500Ω

HIGH VOLTAGE

PULSE

GENERATOR

ST7

C =100pF

S2

L

HUMAN BODY MODEL

Notes:

1. Data based on characterization results, not tested in production.

105/132

ST7263B

EMC CHARACTERISTICS (Cont’d)

13.7.2.2 Static and Dynamic Latch-Up

■ DLU: Electro-Static Discharges (one positive

then one negative test) are applied to each pin

of 3 samples when the micro is running to

assess the latch-up performance in dynamic

mode. Power supplies are set to the typical

values, the oscillator is connected as near as

possible to the pins of the micro and the

component is put in reset mode. This test

conforms to the IEC1000-4-2 and SAEJ1752/3

standards and is described in Figure 55. For

more details, refer to the AN1181 ST7

application note.

■ LU: 3 complementary static tests are required

on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power

supply pin), a current injection (applied to each

input, output and configurable I/O pin) and a

power supply switch sequence are performed

on each sample. This test conforms to the EIA/

JESD 78 IC latch-up standard. For more details,

refer to the AN1181 ST7 application note.

Electrical Sensitivities

1)

Symbol

LU

Parameter

Static latch-up class

Dynamic latch-up class

Conditions

Class

T =+25°C

A

T =+85°C

A

V

=5.5V, f

=4MHz, T =+25°C

DLU

A

DD

OSC

A

Figure 55. Simplified Diagram of the ESD Generator for DLU

R

=50MΩ

R =330Ω

D

CH

DISCHARGE TIP

V

DD

SS

HV RELAY

C =150pF

S

ST7

ESD

2)

DISCHARGE

RETURN CONNECTION

GENERATOR

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

2. Schaffner NSG435 with a pointed test finger.

106/132

ST7263B

EMC CHARACTERISTICS (Cont’d)

13.7.3 ESD Pin Protection Strategy

Standard Pin Protection

To protect an integrated circuit against Electro-

Static Discharge the stress must be controlled to

prevent degradation or destruction of the circuit el-

ements. The stress generally affects the circuit el-

ements which are connected to the pads but can

also affect the internal devices when the supply

pads receive the stress. The elements to be pro-

tected must not receive excessive current, voltage

or heating within their structure.

To protect the output structure the following ele-

ments are added:

– A diode to V (3a) and a diode from V (3b)

DD

SS

– A protection device between V and V (4)

DD

SS

To protect the input structure the following ele-

ments are added:

– A resistor in series with the pad (1)

– A diode to V (2a) and a diode from V (2b)

DD

SS

– A protection device between V and V (4)

DD

SS

An ESD network combines the different input and

output ESD protections. This network works, by al-

lowing safe discharge paths for the pins subjected

to ESD stress. Two critical ESD stress cases are

presented in Figure 56 and Figure 57 for standard

pins and in Figure 58 and Figure 59 for true open

drain pins.

Figure 56. Positive Stress on a Standard Pad vs. V

SS

V

DD

(3a)

(3b)

(2a)

(1)

(4)

OUT

IN

Main path

(2b)

Path to avoid

V

SS

Figure 57. Negative Stress on a Standard Pad vs. V

DD

V

DD

(3a)

(3b)

(2a)

(1)

(4)

OUT

IN

Main path

(2b)

V

SS

107/132

ST7263B

EMC CHARACTERISTICS (Cont’d)

True Open Drain Pin Protection

Multisupply Configuration

When several types of ground (V , V

The centralized protection (4) is not involved in the

discharge of the ESD stresses applied to true

open drain pads due to the fact that a P-Buffer and

, ...) and

SSA

SS

power supply (V , V

, ...) are available for any

DD

DDA

reason (better noise immunity...), the structure

shown in Figure 60 is implemented to protect the

device against ESD.

diode to V

local protection between the pad and V

are not implemented. An additional

DD

(5a &

SS

5b) is implemented to completely absorb the posi-

tive ESD discharge.

Figure 58. Positive Stress on a True Open Drain Pad vs. V

SS

V

DD

Main path

(1)

Path to avoid

OUT

(4)

IN

(5a)

(5b)

(3b)

(2b)

V

SS

Figure 59. Negative Stress on a True Open Drain Pad vs. V

DD

V

DD

Main path

(1)

OUT

(4)

IN

(3b)

(2b)

V

SS

Figure 60. Multisupply Configuration

V

DD

V

DDA

V

DDA

V

SS

BACK TO BACK DIODE

BETWEEN GROUNDS

V

SSA

V

SSA

108/132

ST7263B

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD CPU

A

1)

Symbol

Parameter

Input low level voltage

Input high level voltage

Conditions

Min

Typ

Max

Unit

V

0.3xV_DD

IL

V

0.7xV_DD

IH

True open drain I/O pins

Other I/O pins

6.0

V

Input voltage

V

IN

SS

V

DD

V

Schmitt trigger voltage hysteresis

Input leakage current

400

mV

µA

hys

I

V

_SS≤V ≤V

DD

±1

L

IN

2)

I

Static current consumption

Floating input mode

V =V =5V

200

120

S

3)

R

Weak pull-up equivalent resistor

I/O pin capacitance

V

DD

50

90

5

kΩ

PU

IN

SS

C

pF

IO

t

Output high to low level fall time

Output low to high level rise time

25

C =50pF

Between 10% and 90%

f(IO)out

r(IO)out

L

ns

t

4)

t

External interrupt pulse time

1

t

CPU

w(IT)in

Figure 61. Two typical Applications with unused I/O Pin

V

ST72XXX

DD

UNUSED I/O PORT

10kΩ

UNUSED I/O PORT

ST72XXX

Figure 62. Typical I vs. V with V =V

Figure 63. Typical R vs. V with V =V

PU DD IN SS

PU

DD

IN

SS

100

90

80

70

60

50

40

30

20

10

0

170

160

150

140

130

120

110

100

90

-45°C

25°C

75°C

-45°C

25°C

75°C

80

70

60

Vdd (V)

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V =5V, not tested in production.

A

DD

2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 61). Data based on design simulation and/or technology

characteristics, not tested in production.

3. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-

PU

scribed in Figure 62). This data is based on characterization results.

4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

109/132

ST7263B

I/O PORT PIN CHARACTERISTICS (Cont’d)

13.8.2 Output Driving Current

Subject to general operating condition for V , f

, and T unless otherwise specified.

A

DD CPU

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for a standard I/O pin

when up to 8 pins are sunk at the same time, Port

A0, Port A(3:7), Port C(0:2)

I

=+1.6mA

0.4

IO

(see Figure 64)

Output low level voltage for a high sink I/O pin

when up to 4 pins are sunk at the same time, Port

B(0:7)

1)

V

OL

I

=+10mA

=+25mA

1.3

1.5

IO

V

(see Figure 65)

Output low level voltage for a very high sink I/O

pin when up to 2 pins are sunk at the same time,

Port A1, Port A2

IO

Output high level voltage for an I/O pin

when up to 8 pins are sourced at same time

(see Figure 66)

I

=-10mA

=-1.6mA

V

-1.3

IO

DD

2)

V

OH

-0.8

IO

Notes:

1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of I (I/

IO

O ports and control pins) must not exceed I

.

VSS

2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2 and the sum of I

IO

(I/O ports and control pins) must not exceed I

. True open drain I/O pins does not have V

.

VDD

OH

Figure 64. Typical V at V =5V (standard)

Figure 65. Typical V at V =5V (high-sink)

OL DD

OL

DD

3

2.5

2

0.3

0.25

0.2

1.5

1

0.15

0.1

0.5

0

0.05

0

5

10

15

20

25

1.5

2

2.5

3

3.5

4

Iio (mA)

110/132

ST7263B

Figure 66. Typical V at V =5V (very high-sink)

OL

DD

2

1.5

1

0.5

0

15

20

25

30

35

40

Iio (mA)

111/132

ST7263B

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 67. Typical V -V at V = 5V

DD OH

DD

0.35

0.3

2.5

2

0.25

0.2

1.5

1

0.15

0.1

0.5

0

0.05

0

-4

-3.5

-3

-2.5

Iio (mA)

-2

-1.5

-1

-25

-20

-15

-10

-5

Iio (mA)

Figure 68. Typical V vs. V (standard I/Os)

Figure 69. Typical V vs. V (high-sink I/Os)

OL DD

OL

DD

0.134

0.132

0.130

0.128

0.126

0.124

0.122

0.120

0.75

0.7

0.65

0.6

0.55

0.5

4

4.25

4.5

4.75

Vdd (V )

5

5.25

5.5

4

4.25

4.5

4.75

5

5.25

5.5

Vdd ( V )

Figure 70. Typical V vs. V (very high-sink I/Os)

OL

DD

0.95

0.9

0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5

4

4.25

4.5

4.75

Vdd ( V )

5

5.25

5.5

112/132

ST7263B

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 71. Typical V -V vs. V

DD OH

DD

0.165

0.16

0.9

0.85

0.8

0.155

0.15

0.75

0.7

0.65

0.6

0.145

0.14

0.55

0.5

0.135

4

4.25

4.5

4.75

Vdd ( V )

5

5.25

5.5

4

4.25

4.5

4.75

Vdd ( V )

5

5.25

5.5

113/132

ST7263B

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD CPÜ

A

1)

Symbol

Parameter

Input High Level Voltage

Input Low Voltage

Conditions

Min

0.7xV

Typ

400

80

Max

Unit

V

DD

IH

DD

SS

V

0.3xV

V

IL

DD

3)

V

Schmitt trigger voltage hysteresis

mV

hys

4)

I

=5mA

=7.5mA

=5V

0.8

1.3

Output low level voltage

IO

V

R

V

=5V

DD

V

OL

(see Figure 74, Figure 75)

IO

5)

Weak pull-up equivalent resistor

Generated reset pulse duration

V =V

V

50

100

kΩ

ON

IN

SS

DD

External pin or

internal reset sources

6

1/f

SFOSC

t

w(RSTL)out

30

µs

6)

t

External reset pulse hold time

5

µs

h(RSTL)in

7)

Figure 72. Typical Application with RESET pin

ST72XXX

V

DD

V

DD

INTERNAL

RESET CONTROL

R

ON

0.1µF

4.7kΩ

USER

EXTERNAL

RESET

8)

CIRCUIT

WATCHDOG RESET

LVD RESET

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V =5V, not tested in production.

A

DD

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The I current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of I (I/

IO

O ports and control pins) must not exceed I

.

VSS

5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current characteristics de-

ON

scribed in Figure 73). This data is based on characterization results, not tested in production.

6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below t can be ignored.

h(RSTL)in

7. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

114/132

ST7263B

CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 73. Typical I vs. V with V =V

Figure 74. Typical V at V =5V (RESET)

OL DD

ON

DD

IN

SS

1.4

1.2

1

120

100

80

60

40

20

0

0.8

0.6

0.4

0.2

0

-45°C

25°C

75°C

3.5

4

4.5

5

5.5

Iio (mA)

6

6.5

7

7.5

Vdd (V)

Figure 75. Typical V vs. V (RESET)

OL

DD

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.75

0.7

0.65

0.6

0.55

0.5

4

4.25

4.5

4.75

Vdd (V )

5

5.25

5.5

4

4.25

4.5

4.75

Vdd (V )

5

5.25

5.5

115/132

ST7263B

13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 USB - Universal Bus Interface

(Operating conditions T_A= 0 to +70°C, V = 4.0 to 5.25V unless otherwise specified)

DD

USB DC Electrical Characteristics

Parameter

Symbol

VDI

Conditions

I(D+, D-)

Min.

0.2

Max.

Unit

V

Differential Input Sensitivity

Differential Common Mode Range

Single Ended Receiver Threshold

Static Output Low

VCM

VSE

Includes VDI range

0.8

2.5

2.0

V

0.8

V

VOL

RL of 1.5K ohms to 3.6v

0.3

V

Static Output High

VOH

USBV

RL of 15K ohms to V

2.8

3.6

V

SS

3

USBVCC: voltage level

V

=5v

3.00

3.60

V

DD

Note 1: RL is the load connected on the USB drivers.

Note 2: All the voltages are measured from the local ground potential.

Note 3: To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor

to the USBVCC pin.

Figure 76. USB: Data Signal Rise and Fall Time

Differential

Data Lines

Crossover

points

VCRS

V_SS

tr

tf

Table 25. USB: Low-speed Electrical Characteristics

Parameter

Driver characteristics:

Rise time

Symbol

Conditions

Min

75

Max

Unit

tr

tf

Note 1,CL=50 pF

Note 1, CL=600 pF

Note 1, CL=50 pF

Note 1, CL=600 pF

tr/tf

ns

%

300

Fall Time

75

300

120

Rise/ Fall Time matching

trfm

80

Output signal Crossover

Voltage

VCRS

1.3

2.0

V

Note 1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to

Chapter 7 (Electrical) of the USB specification (version 1.1).

116/132

ST7263B

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

13.10.2 SCI - Serial Communications Interface

Subject to general operating condition for V

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(RDI and TDO).

,

DD

f

, and T unless otherwise specified.

CPU

A

Conditions

Baud

Rate

Symbol

Parameter

Standard

Unit

Accuracy

vs. Standard

Prescaler

f

CPU

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

300

~300.48

1200 ~1201.92

2400 ~2403.84

4800 ~4807.69 Hz

9600 ~9615.38

10400 ~10416.67

19200 ~19230.77

38400 ~38461.54

f

Tx

Communication frequency 8MHz ~0.16%

Rx

2

13.10.3 I C - Inter IC Control Interface

2

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SDAI and SCLI).

The ST7 I C interface meets the requirements of

2

the Standard I C communication protocol de-

scribed in the following table.

(Subject to general operating conditions for V , f

, and T unless otherwise specified)

DD OSC

A

2

Standard mode I C

Fast mode I C

Symbol

Parameter

Unit

1)

Min

Max

Min

Max

t

SCL clock low time

SCL clock high time

SDA setup time

4.7

4.0

250

1.3

0.6

100

w(SCLL)

µs

t

w(SCLH)

t

su(SDA)

3)

2)

3)

t

SDA data hold time

0

900

h(SDA)

t

r(SDA)

ns

SDA and SCL rise time

SDA and SCL fall time

1000

300

20+0.1C

300

b

r(SCL)

t

f(SDA)

f(SCL)

t

START condition hold time

4.0

4.7

4.0

4.7

0.6

1.3

h(STA)

µs

t

Repeated START condition setup time

STOP condition setup time

su(STA)

su(STO)

t

ns

ms

pF

t

STOP to START condition time (bus free)

Capacitive load for each bus line

w(STO:STA)

C

400

b

Notes:

2

1. Data based on standard I C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal.

117/132

ST7263B

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

2

Figure 77. Typical Application with I C Bus and Timing Diagram ¹⁾

V

DD

4.7kΩ

100Ω

SDAI

SCLI

2

I C BUS

ST72XXX

REPEATED START

START

t

w(STO:STA)

su(STA)

START

SDA

t

r(SDA)

f(SDA)

STOP

t

h(SDA)

su(SDA)

SCK

t

su(STO)

t

h(STA)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

Note 1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV

.

DD

118/132

ST7263B

13.11 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V , f

, and T unless otherwise specified.

DD OSC

A

1)

Symbol

Parameter

ADC clock frequency

Conversion range voltage

External input resistor

Conditions

Min

Typ

Max

Unit

MHz

V

f

4

ADC

2)

V

R

V

AIN

SSA

DDA

3)

10

kΩ

C

Internal sample and hold capacitor

Stabilization time after ADC enable

Conversion time (Sample+Hold)

6

pF

ADC

4)

t

0

STAB

µs

6

f

=8MHz, f

=2MHz

ADC

CPU

t

- Sample capacitor loading time

- Hold conversion time

4

8

ADC

1/f

ADC

Figure 78. Typical Application with ADC

V

DD

V

T

0.6V

R

AIN

AINx

V

AIN

ADC

V

0.6V

T

C

~2pF

I

L

±1µA

IO

V

DD

V

DDA

SSA

0.1µF

ST72XXX

Notes:

1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-

A

DD SS

lines and are not tested.

2. When V and V

pins are not available on the pinout, the ADC refer to V and V .

SS

DDA

SSA

DD

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first t

always valid.

. The first conversion after the enable is then

LOAD

119/132

ST7263B

8-BIT ADC CHARACTERISTICS (Cont’d)

ADC Accuracy with V =5V, f

=8 MHz, f

=4 MHz R < 10kΩ

DD

CPU

ADC

AIN

Symbol

|E |

Parameter

Min

Max

2

1)

Total unadjusted error

T

1)

-0.5

-1.5

1

E

Offset error

O

G

1)

0

Gain Error

1)

1.5

|E |

Differential linearity error

D

1)

|E |

Integral linearity error

L

Figure 79. ADC Accuracy Characteristics

Digital Result ADCDR

E

G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

255

V

– V

254

253

DDA

SSA

1LSB

= ----------------------------------------

IDEAL

256

(2)

E =Total Unadjusted Error: maximum deviation

T

E

between the actual and the ideal transfer curves.

T

(3)

7

6

5

4

3

2

1

E =Offset Error: deviation between the first actual

O

transition and the first ideal one.

(1)

E =Gain Error: deviation between the last ideal

G

transition and the last actual one.

E

O

E

L

E =Differential Linearity Error: maximum deviation

D

between actual steps and the ideal one.

E =Integral Linearity Error: maximum deviation

L

E

between any actual transition and the end point

correlation line.

D

1 LSB

IDEAL

V

(LSB

)

IDEAL

in

0

1

2

3

4

5

6

7

253 254 255 256

V

DDA

SSA

Notes:

1. ADC Accuracy vs. Negative Injection Current:

For I

=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB

INJ-

for each 10KΩ increase of the external analog source impedance. This effect on the ADC accuracy has been observed

under worst-case conditions for injection:

- negative injection

- injection to an Input with analog capability, adjacent to the enabled Analog Input

- at 5V V supply, and worst case temperature.

DD

2. Data based on characterization results with T =25°C.

A

3. Data based on characterization results over the whole temperature range, monitored in production.

120/132

ST7263B

14 PACKAGE CHARACTERISTICS

14.1 PACKAGE MECHANICAL DATA

Figure 80. 34-Pin Shrink Plastic Small Outline Package, 300-mil Width

mm

inches

Dim.

Min Typ Max Min Typ Max

A

2.46

2.64 0.097

0.29 0.005

0.48 0.014

0.32 0.0091

18.06 0.698

7.59 0.292

0.104

0.0115

0.019

0.0125

0.711

0.299

A1 0.13

B

C

D

E

e

0.36

0.23

0.10mm

.004

seating plane

17.73

7.42

1.02

0.040

H

h

10.16

0.64

10.41 0.400

0.74 0.025

0°

0.410

0.029

8°

K

L

0.61

1.02 0.024

0.040

Number of Pins

N

34

SO34S

Figure 81. 32-Pin Shrink Plastic Dual in Line Package, 400-mil Width

E

mm

inches

Dim.

Min Typ Max Min Typ Max

See Lead Detail

A

3.56 3.76 5.08 0.140 0.148 0.200

A1 0.51

A2 3.05 3.56 4.57 0.120 0.140 0.180

0.36 0.46 0.58 0.014 0.018 0.023

b1 0.76 1.02 1.40 0.030 0.040 0.055

0.020

C

e_A

b

b1

b

e

B

e

C

D

E

0.20 0.25 0.36 0.008 0.010 0.014

27.43 27.94 28.45 1.080 1.100 1.120

9.91 10.41 11.05 0.390 0.410 0.435

3

D

A

2

N

E1 7.62 8.89 9.40 0.300 0.350 0.370

A

L

e

1.78

0.070

0.400

E

1

A

eA

eB

L

10.16

1

12.70

0.500

e

VR01725J

2.54 3.05 3.81 0.100 0.120 0.150

1

N/2

Number of Pins

N

32

121/132

ST7263B

14.2 THERMAL CHARACTERISTICS

Symbol

Ratings

Value

Unit

Package thermal resistance (junction to ambient)

SDIP32

SO34

R

60

75

°C/W

thJA

1)

P

Power dissipation

Maximum junction temperature

500

150

mW

°C

D

2)

T

Jmax

Notes:

1. The power dissipation is obtained from the formula P =P +P

where P

is the chip internal power (I xV

)

D

INT

PORT

INT

DD DD

and P

is the port power dissipation determined by the user.

PORT

2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.

J

A

D

122/132

ST7263B

14.3 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only

as design guidelines in Figure 82 and Figure 83.

Recommended glue for SMD plastic packages

dedicated to molding compound with silicone:

■ Heraeus: PD945, PD955

■ Loctite: 3615, 3298

Figure 82. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)

250

COOLING PHASE

(ROOM TEMPERATURE)

5 sec

200

150

100

50

SOLDERING

PHASE

80°C

Temp. [°C]

PREHEATING

PHASE

Time [sec]

0

20

40

60

80

100

120

140

160

Figure 83. Recommended Reflow Soldering Oven Profile (MID JEDEC)

250

Tmax=220+/-5°C

for 25 sec

200

150

100

50

150 sec above 183°C

90 sec at 125°C

Temp. [°C]

ramp down natural

2°C/sec max

ramp up

2°C/sec for 50sec

Time [sec]

0

100

200

300

400

123/132

ST7263B

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in ROM

versions, in user programmable versions (FLASH)

as well as in factory coded versions (FASTROM).

FLASH devices are shipped to customers with a

default content (FFh), while ROM factory coded

parts contain the code supplied by the customer.

This implies that FLASH devices have to be con-

figured by the customer using the Option Byte

while the ROM devices are factory-configured.

The FASTROM or ROM contents are to be sent on

diskette, or by electronic means, with the hexadec-

imal file in .S19 format generated by the develop-

ment tool. All unused bytes must be set to FFh.

The selected options are communicated to STMi-

croelectronics using the correctly completed OP-

TION LIST appended.

OPT 5 = WDGSW Hardware or Software Watch-

dog

This option bit selects the watchdog type.

0: Hardware enabled

1: Software enabled

OPT 4 = WDHALT Watchdog and HALT mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT 3 = LVD Low Voltage Detector selection

This option bit selects the LVD.

0: LVD enabled

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on con-

tractual points.

1: LVD disabled

OPT 2 = Reserved.

15.1 OPTION BYTE

The Option Byte allows the hardware configuration

of the microcontroller to be selected.

OPT 1 = OSC24/12 Oscillator Selection

This option bit selects the clock divider used to

drive the USB interface at 6MHz.

0: 24 MHz oscillator

The Option Byte has no address in the memory

map and can be accessed only in programming

mode using a standard ST7 programming tool.

The default contents of the FLASH is fixed to FFh.

This means that all the options have “1” as their

default value.

1: 12 Mhz oscillator

OPT 0 = FMP_R Flash memory read-out protec-

tion

In ROM devices, the Option Byte is fixed in hard-

ware by the ROM code.

This option indicates if the user flash memory is

protected against read-out piracy. This protection

is based on a read and write protection of the

memory in test modes and IAP. Erasing the option

bytes when the FMP_R option is selected, causes

the whole user memory to be erased first.

0: Read-out protection enabled

OPTION BYTE

7

0

WDG WD

SW HALT

OSC FMP_

--

LVD

--

24/12

R

1: Read-out protection disabled

OPT 7:6 = Reserved.

124/132

ST7263B

15.2 DEVICE ORDERING INFORMATION

Table 26. Supported Part Numbers

Program Memory

RAM

(bytes)

1)

Sales Type

Package

(bytes)

ST72F63BK4M1

ST72F63BK4B1

ST72F63BK2M1

ST72F63BK2B1

ST72F63BK1M1

ST72F63BK1B1

ST7263BK2M1/xxx

ST7263BK2B1/xxx

ST7263BK1M1/xxx

ST7263BK1B1/xxx

ST72P63BK4M1

ST72P63BK4B1

ST72P63BK2M1

ST72P63BK2B1

ST72P63BK1M1

ST72P63BK1B1

16K Flash

SO34

PSDIP32

SO34

512

16K Flash

8K Flash

PSDIP32

SO34

4K Flash

PSDIP32

SO34

384

8K ROM

PSDIP32

SO34

4K ROM

PSDIP32

SO34

16K FASTROM

8K FASTROM

4K FASTROM

512

384

PSDIP32

SO34

PSDIP32

SO34

PSDIP32

Note: /xxx stands for the ROM code name assigned by STMicroelectronics.

Contact ST sales office for product availability

125/132

ST7263B

15.3 DEVELOPMENT TOOLS

STmicroelectronics offers a range of hardware

and software development tools for the ST7 micro-

controller family. Full details of tools available for

the ST7 from third party manufacturers can be ob-

tain from the STMicroelectronics Internet site:

➟ http//mcu.st.com.

Tools from these manufacturers include C compli-

ers, emulators and gang programmers.

STMicroelectronics Tools

Three types of development tool are offered by ST

see Table 27 and Table 28 for more details.

Table 27. STMicroelectronics Tools Features

1)

In-Circuit Emulation

Programming Capability

Software Included

ST7 CD ROM with:

Yes, powerful emulation

ST7 Emulator

features including trace/

logic analyzer

No

– ST7 Assembly toolchain

– STVD7 powerful Source Level

Debugger for Win 3.1, Win 9x

and NT

– C compiler demo versions

– Windows Programming Tools

for Win 3.1, Win 9x and NT

ST7 Programming Board

No

Yes (All packages)

Note:

1. In-Circuit Programming (ICP) interface for FLASH devices.

Table 28. Dedicated STMicroelectronics Development Tools

ST7 Programming Active Probe & Target

Supported Products

ST7263B

Evaluation Board

ST7 Emulator

Board

ST7MDTULS-EVAL ST7MDTU3-EMU2B ST7MDTU3-EPB

Emulation Board

1)

ST7MDTU2-DBE2B

Note:

1. Add Suffix /EU or /US for the power supply for your region.

126/132

ST7263B

ST7263B MICROCONTROLLER OPTION LIST

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address:

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact:

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.

STMicroelectronics references:

Device Type/Memory Size/Package (check only one option):

-----------------------------------------------------------------------------------------

ROM DEVICE:

|

4K

|

8K

|

-----------------------------------------------------------------------------------------

PSDIP32:

SO34:

| [ ] ST7263BK1B1 | [ ] ST7263BK2B1

| [ ] ST7263BK1M1 | [ ] ST7263BK2M1

|

----------------------------------------------------------------------------------------------------------------------

FASTROM DEVICE: | 4K 8K 16K

|

----------------------------------------------------------------------------------------------------------------------

PSDIP32:

| [ ] ST72P63BK1B1 | [ ] ST72P63BK2B1 | [ ] ST72P63BK4B1

SO34:

| [ ] ST72P63BK1M1 | [ ] ST72P63BK2M1 | [ ] ST72P63BK4M1

----------------------------------------------------------------------------------------------------------------------

DIE FORM: 4K 8K 16K

|

----------------------------------------------------------------------------------------------------------------------

32-pin:

34-pin:

| [ ] (as K1B1)

| [ ] (as K1M1)

| [ ] (as K2B1)

| [ ] (as K2M1)

| [ ] (as K4B1)

| [ ] (as K4M1)

Conditioning (check only one option):

Packaged Product

|

Die Product (dice tested at 25°C only)

----------------------------------------------------------------------------------------------------------------------

[ ] Tape & Reel (SO package only)

[ ] Tube

|

[ ] Tape & Reel

[ ] Inked wafer

[ ] Sawn wafer on sticky foil

Special Marking ( ROM only): [ ] No

[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _"

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

For marking, one line is possible with a maximum of 13 characters.

Watchdog Selection:

Halt when Watchdog on:

LVD Reset

[ ] Software activation

[ ] Reset

[ ] Hardware activation

[ ] No reset

[ ] Disabled

[ ] Enabled

Oscillator Selection:

Readout Protection:

[ ] 24 MHz.

[ ] 12 MHz.

[ ] Disabled

[ ] Enabled

Date

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . .

127/132

ST7263B

15.4 ST7 APPLICATION NOTES

IDENTIFICATION

DESCRIPTION

EXAMPLE DRIVERS

AN 969

AN 970

AN 971

AN 972

AN 973

AN 974

AN 976

AN 979

AN 980

AN1017

AN1041

AN1042

AN1044

AN1045

AN1046

AN1047

AN1048

AN1078

AN1082

AN1083

AN1105

AN1129

SCI COMMUNICATION BETWEEN ST7 AND PC

SPI COMMUNICATION BETWEEN ST7 AND EEPROM

I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM

ST7 SOFTWARE SPI MASTER COMMUNICATION

SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE

DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION

DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER

USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)

ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT

MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

ST7 S/W IMPLEMENTATION OF I²C BUS MASTER

UART EMULATION SOFTWARE

MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS

ST7 SOFTWARE LCD DRIVER

PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE

DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS

ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

ST7 PCAN PERIPHERAL DRIVER

PERMANENT MAGNET DC MOTOR DRIVE.

AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS

WITH THE ST72141

AN1130

AN1148

AN1149

AN1180

AN1276

AN1321

AN1325

AN1445

AN1475

AN1504

USING THE ST7263 FOR DESIGNING A USB MOUSE

HANDLING SUSPEND MODE ON A USB MOUSE

USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER

USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE

USING THE ST7 USB LOW-SPEED FIRMWARE V4.X

USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE

DEVELOPING AN ST7265X MASS STORAGE APPLICATION

STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER

PRODUCT EVALUATION

AN 910

AN 990

AN1077

AN1086

AN1150

AN1151

AN1278

PERFORMANCE BENCHMARKING

ST7 BENEFITS VERSUS INDUSTRY STANDARD

OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS

U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING

BENCHMARK ST72 VS PC16

PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876

LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS

PRODUCT MIGRATION

AN1131

AN1322

AN1365

MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324

MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B

GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264

PRODUCT OPTIMIZATION

128/132

ST7263B

IDENTIFICATION

AN 982

DESCRIPTION

USING ST7 WITH CERAMIC RESONATOR

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

AN1014

AN1015

SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE

MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES

ST7 CHECKSUM SELF-CHECKING CAPABILITY

AN1040

AN1070

AN1324

CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS

EMULATED DATA EEPROM WITH XFLASH MEMORY

AN1477

AN1502

EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY

AN1529

EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY

ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-

LATOR

AN1530

PROGRAMMING AND TOOLS

AN 978

AN 983

AN 985

AN 986

AN 987

AN 988

AN 989

AN1039

AN1064

AN1071

AN1106

KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE

KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE

EXECUTING CODE IN ST7 RAM

USING THE INDIRECT ADDRESSING MODE WITH ST7

ST7 SERIAL TEST CONTROLLER PROGRAMMING

STARTING WITH ST7 ASSEMBLY TOOL CHAIN

GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN

ST7 MATH UTILITY ROUTINES

WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER

TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-

GRAMMING)

AN1179

AN1446

AN1478

AN1527

AN1575

USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION

PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE

DEVELOPING A USB SMARTCARD READER WITH ST7SCR

ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

129/132

ST7263B

16 IMPORTANT NOTES

16.1 UNEXPECTED RESET FETCH

16.2 HALT MODE POWER CONSUMPTION

WITH ADC ON

If an interrupt request occurs while a "POP CC" in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

If the A/D converter is being used when Halt mode

is entered, the power consumption in Halt Mode

may exceed the maximum specified in the datash-

eet.

Workaround

To solve this issue, a "POP CC" instruction must

always be preceded by a "SIM" instruction.

Switch off the ADC by software (ADON=0) before

executing a HALT instruction.

130/132

ST7263B

17 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one.

Revision

Main Changes

Date

Modified option list on page 127 (removed 16K for ROM devices)

Changed title of section 16 on page 130

1.5

April 03

Please read carefully the Section “IMPORTANT NOTES” on page 130

131/132

ST7263B

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

STMicroelectronics Group of Companies

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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

132/132


型号：	ST72F63BK4M1
厂家：	ST
描述：	LOW SPEED USB 8-BIT MCU FAMILY WITH FLASH/ROM, UP TO 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & IC 低速USB 8位单片机系列闪存/ ROM ，高达512字节的RAM ， 8位ADC ， WDG ，定时器， SCI和IC 闪存
文件：	总132页 (文件大小：1497K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST72F63BK4M1 [STMICROELECTRONICS]

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