ST72F651R4T1 [STMICROELECTRONICS]

8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, TQFP-64;


型号：	ST72F651R4T1
厂家：	ST
描述：	8-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, TQFP-64
文件：	总9页 (文件大小：70K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ST7265

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K

FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I C

DATA BRIEFING

■ Memories

– Up to 32K of ROM or Flash program memory

with read/write protection

– For Flash devices, In-Application Program-

ming (IAP) via USB and In-Circuit program-

ming (ICP)

TQFP64 10x10

TQFP64 14x14

– Up to 5 Kbytes of RAM with up to 256 bytes

stack

■ Clock, Reset and Supply Management

– PLL for generating 48 MHz USB clock using a

■ Mass Storage Interface

12 MHz crystal

– DTC (Data Transfer Coprocessor): Universal

Serial/Parallel communications interface, with

software plug-ins for current and future proto-

col standards:

– Low Voltage Reset (optional)

– Dual supply management: analog voltage de-

tector on the USB power line to enable smart

power switching from USB power to battery.

– Programmable Internal Voltage Regulator for

Memory cards (2.4V to 3.3V) supplying:

Flash Card I/O lines (voltage shifting)

Up to 50 mA for Flash card supply

16-bit IDE mode Compact Flash

Multimedia Card (MMC protocol)

SmartMediaCard

Secure Digital Card

■ 2 Timers

– Clock-out capability

– Configurable Watchdog for system reliability

– 16-bit Timer with 2 output compare functions.

■ 1 Communication Interface

■ 47 programmable I/O lines

– 11 high sink I/Os (10mA at 1V)

– 5 true open drain outputs

– 16 lines programmable as interrupt inputs

■ USB (Universal Serial Bus) Interface

– I C Single Master Interface up to 400 KHz

■ D/A and A/D Peripherals

– PWM/BRM Generator (with 2 10-bit PWM/

BRM outputs)

– 8-bit A/D Converter (ADC) with 2 channels

– with DMA for full speed bulk applications com-

pliant with USB 12 Mbs specification (version

1.1)

■ Instruction Set

– On-Chip 3.3V USB voltage regulator and

transceivers with software power-down

– 8-bit data manipulation

– 63 basic instructions

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

– True bit manipulation

– 5 USB endpoints:

1 control endpoint

2 IN endpoints supporting interrupt and bulk

2 OUT endpoints supporting interrupt and

bulk

– Hardware conversion between USB bulk

■ Development Tools

packets and 512-byte blocks

– Full hardware/software development package

Device Summary

Features

ST72651

ST72F651

ST72652

ST72F652

Program memory

User RAM (stack) - bytes

32K ROM

32K FLASH

16K ROM

16K FLASH

5K (256)

1K (256)

Peripherals

USB, DTC, Timer, ADC, I C, PWM

Dual 2.4V to 5.5V or 4.0V to 5.5V (for USB)

6 or 3 MHz (8 MHz in USB mode)

TQFP64 (10 x10 or 14 x14)

USB, DTC, Timer

Single 4.0V to 5.5V

8, 6 or 3 MHz

Operating Supply

CPU Frequency

Package

TQFP64 (14 x14)

Operating Temperature

0°C to +70°C

Rev. 1.2

1/9

September 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

ST7265

1 INTRODUCTION

The ST7265 MCU supports volume data ex-

change with a host (computer or kiosk) via a full

speed USB interface. The MCU is capable of

handing various transfer protocols, with a particu-

lar emphasis on FLASH media card mass storage

applications.

– A dedicated 24 MHz Data Buffer Manager state

machine for handling 512-byte data blocks (this

size corresponds to a sector both on computers

and FLASH media cards).

– A Data Transfer Coprocessor (DTC), able to

handle fast data transfer with external devices.

This DTC also computes the CRC or ECC re-

quired to handle Mass storage media.

ST7265 is compliant with the USB Mass Storage

Class specifications, and supports related proto-

cols such as BOT (Bulk Only Transfer) and CBI

(Control, Bulk, Interrupt).

– An Arbitration block gives the ST7 core priority

over the USB and DTC when accessing the Data

Buffer. In USB mode, the USB interface is serv-

iced before the DTC.

It is based on the ST7 standard 8-bit core, with

specific peripherals for managing USB full speed

data transfer between the host and most types of

FLASH media card:

– A FLASH Supply Block able to provide program-

mable supply voltage and I/O electrical levels to

the FLASH media card.

– A full speed USB interface with Serial Interface

Engine, and on-chip 3.3V regulator and trans-

ceivers.

Figure 1. USB Data Transfer Block Diagram

USB

SIE

USB DATA

TRANSFER

DATA TRANSFER

BUFFER

512-byte RAM

Buffer

BUFFER ACCESS

ST7 CORE

ARBITRATION

512-byte RAM

Buffer

DATA

TRANSFER

COPROCESSOR

(DTC)

LEVEL

SHIFTERS

MASS

STORAGE

DEVICE

2/9

ST7265

INTRODUCTION (Cont’d)

In addition to the peripherals for USB full speed

data transfer, the ST7265 includes all the necess-

cary features for stand-alone applications with

FLASH mass storage.

– Fast I C Single Master interface (not on all prod-

ucts - see device summary)

– 8-bit Analog-to-Digital converter (ADC) with 2

multiplexed analog inputs (not on all products -

see device summary)

– Low voltage reset ensuring proper power-on or

power-off of the device (selectable by option)

The ST72F65x are the Flash versions of the

ST7265x in a TQFP64 package.

– Digital Watchdog

– 16-bit Timer with 2 output compare functions.

The ST7265x are the ROM versions in a TQFP64

package.

– Two 10-bit PWM outputs (not on all products -

see device summary)

Figure 2. Digital Audio Player Application Example in Play Mode

DATA TRANSFER

BUFFER

512-byte RAM

Buffer

512-byte RAM

Buffer

BUFFER ACCESS

ARBITRATION

ST7 CORE

DATA

TRANSFER

COPROCESSOR

(DTC)

I2C

LEVEL SHIFTERS

MASS

STORAGE

DEVICE

DIGITAL

AUDIO DEVICE

3/9

ST7265

INTRODUCTION (Cont’d)

Figure 3. ST7265 Block Diagram

OSCIN

12MHz

OSC

OSCOUT

PA[7:0]

(8 bits)

CLOCK

DIVIDER

PORT A

PORT B

48MHz

PLL

PB[7:0]

(8 bits)

CPU

PC[7:0]

(8 bits)

PORT C

DATA

TRANSFER

BUFFER

(1280 bytes)

DATA

TRANSFER

COPROCESSOR

DTC S/W RAM

(256 Bytes)

PE[7:0]

(8 bits)

PORT E

PWM*

USBDP

USBDM

USBVCC

PORT F

USB

PD[7:0] or PD[3:0]

(8 or 4 bits)

PF[6:0]

(7 bits)

I C*

PORT D

16-BIT TIMER

WATCHDOG

8-BIT ADC*

DDF

FLASH SUPPLY

BLOCK

RESET

CONTROL

SSF

8-BIT CORE

ALU

DDA

POWER SUPPLY

REGULATOR

SSA

LVD

DD1, DD2

DUAL SUPPLY

MANAGER *

SS1, SS2

RAM

(1/5 KBytes)

USBV

PROGRAM

MEMORY

(16K/32 Kbytes)

* not on all products (refer to Table 1: Device Summary)

4/9

ST7265

2 PIN DESCRIPTION

Figure 4. 64-Pin TQFP Package Pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PE3 / PWM0 / DTC

PE2 (HS) / DTC

PE1 (HS) / DTC

PE0 (HS) / DTC

PD7

USBV

USBDM

USBDP

USBVCC

USBV

PD6

DDF

PD5/OCMP2

PD4/OCMP1

PD3

PD2

PD1

PD0

PC7

PC6

PC5

SSF

DTC / PE5 (HS)

DTC / PE6 (HS)

DTC / PE7 (HS)

DTC / PB0

ei1

DTC / PB1

DTC / PB2

DTC / PB3

DTC / PB4

ei0

PC4

DTC / PB5

17 18 19 20 21 22 23 24

29 30 31 32

25 26 27 28

I/O pin supplied by V

DDF

/ V

SSF

(HS) 10mA high sink capability

associated external interrupt vector

5/9

ST7265

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:

– Input:float = floating, wpu = weak pull-up, int = in-

terrupt

Type: I = input, O = output, S = supply

– Output: OD = open drain, T = true open drain, PP

= push-pull, OP = pull-up enabled by option byte.

powered: I/O powered by the alternate sup-

DDF

ply rail, supplied by V

and V

DDF

SSF

Refer to “I/O Port Implementation” on page 51 of

the datasheet for more details on the software

configuration of the

In/Output level: C = CMOS 0.3V /0.7V with

input trigger

Output level: HS = 10mA high sink (on N-buffer

only)

I/O ports.

The RESET configuration of each pin is shown in

bold.

Port and control configuration:

Table 1. Device Pin Description

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

Alternate Function

USBV

USB Digital ground

USBDM

I/O

USB bidirectional data (data -)

USB bidirectional data (data +)

USBDP

USB power supply, output by the on-chip USB

3.3V linear regulator.

USBVCC

USBV

USB Power supply voltage (4V - 5.5V)

Power Line for alternate supply rail. Can be

used as input (with external supply) or output

(when using the on-chip voltage regulator).

Note: An external decoupling capacitor (min.

20nF) must be connected to this pin to stabilize

the regulator.

DDF

Ground Line for alternate supply rail. Can be

used as input (with external supply) or output

(when using the on-chip voltage regulator)

SSF

DTC I/O with serial capability

(MMC_CMD)

PE5/DTC

PE6/DTC

I/O

HS X

Port E5

DTC I/O with serial capability

(MMC_DAT)

Port E6

DTC I/O with serial capability

(MMC_CLK)

10 PE7/DTC

Port E7

11 PB0/DTC

12 PB1/DTC

13 PB2/DTC

14 PB3/DTC

15 PB4/DTC

16 PB5/DTC

17 PB6/DTC

I/O

Port B0

Port B1

Port B2

Port B3

Port B4

Port B5

Port B6

DTC

6/9

ST7265

Level

Port / Control

Input Output

Main

Pin Name

Function

(after reset)

Alternate Function

18 PB7/DTC

19 PA0/DTC

20 PA1/DTC

21 PA2/DTC

22 PA3/DTC

23 PA4/DTC

24 PA5/DTC

25 PA6/DTC

26 PA7/DTC

27 PC0/MCO

I/O

Port B7

Port A0

Port A1

Port A2

Port A3

Port A4

Port A5

Port A6

Port A7

Port C0

DTC

ei0

Main Clock Output

DTC I/O with serial capability

(DATARQ)

28 PC1/DTC

29 PC2/DTC

30 PC3/DTC

I/O

Port C1

Port C2

Port C3

DTC I/O with serial capability

(SDAT)

DTC I/O with serial capability

(SCLK)

Power supply voltage (2.4V - 5.5V)

Digital ground

DD1

SS1

33 PC4/DTC

34 PC5/DTC

35 PC6/DTC

36 PC7/DTC

37 PD0

I/O

Port C4

Port C5

Port C6

Port C7

Port D0

Port D1

Port D2

Port D3

Port D4

Port D5

Port D6

Port D7

Port E0

Port E1

Port E2

Port E3

DTC

38 PD1

39 PD2

40 PD3

ei1

41 PD4/OCMP1

42 PD5/OCMP2

43 PD6

Timer Output Compare 1

Timer Output Compare 2

44 PD7

45 PE0/DTC

46 PE1/DTC

47 PE2/DTC

48 PE3/DTC/PWM0

CT HS

DTC

DTC / PWM Output 0

7/9

ST7265

Level

Port / Control

Main

Function

(after reset)

Input

Output

Pin Name

Alternate Function

49 PE4/PWM1

I/O

Port E4

PWM Output 1

Flash programming voltage. Must be held low

in normal operating mode.

Bidirectional. This active low signal forces the

initialization of the MCU. This event is the top

priority non maskable interrupt. This pin is

switched low when the Watchdog has triggered

51 RESET

I/O

or V is low. It can be used to reset external

peripherals.

52 PF0 / SCL

53 PF1 / SDA

54 PF2 / AIN0

55 PF3 / AIN1

I/O

Port F0

Port F1

Port F2

Port F3

I C Serial Clock

I C Serial Data

Analog Input 0

Analog Input 1

USB Power Management USB

Enable (alternate function se-

lected by option bit)

56 PF4 / USBEN

I/O

Port F4

57 PF5

58 PF6

I/O

Port F5

Port F6

Main Power supply voltage (2.4V - 5.5V)

Analog supply voltage

Analog ground

DD2

DDA

SSA

SS2

Digital ground

Input/Output Oscillator pins. These pins con-

nect a 12 MHz parallel-resonant crystal, or an

external source to the on-chip oscillator.

63 OSCIN

64 OSCOUT

If the peripheral is present on the device (see Table –)

A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register

and depending on the PE5PU bit in the option byte.

8/9

ST7265

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I²C Components by STMicroelectronics conveys a license under the Philips I²C Patent. Rights to use these components in an

I²C system is granted provided that the system conforms to the I²C Standard Specification as defined by Philips.

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9/9

ST72F651R4T1 [STMICROELECTRONICS]

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