ST75C520PQFP [STMICROELECTRONICS]
HIGH SPEED FAX MODEM DATA PUMP; 高速传真调制解调器数据泵
| 型号： | ST75C520PQFP |
| 厂家： | 
ST |
| 描述： | HIGH SPEED FAX MODEM DATA PUMP |
| 文件： | 总45页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST75C520
HIGH SPEED FAX MODEM DATA PUMP
PRELIMINARY DATA
.
ITU-T V.17, V.29, V.27ter, V.21 WITH FAX
SUPPORT
DESCRIPTION
The SGS-THOMSON Microelectronics ST75C520
chip is a highly integrated modem engine, which
can operate with all currently used FAX group III
standards up to 14400bps. Full V.21, V.23 and Bell
103 full duplex modem standards are imple-
mented.
.
.
.
.
.
.
ITU-T V.23, V.21, BELL 103
V.17, V.29 (T104), V.27ter SHORT TRAINS
V.33 HALF-DUPLEX
1800Hz OR 1700Hz CARRIER
SINGLE CHIP COMPLETE DATA PUMP
SINGLE 5V POWER SUPPLY :
-
TYPICAL ACTIVE POWER CONSUMPTION :
375mW
-
LOW POWER MODE (typ. 5mW)
.
EXTENDED MODES OF OPERATIONS :
-
-
-
FULL IMPLEMENTATION OF THE V.17,
V.33, V.29 AND V.27ter HANDSHAKES
AUTODIAL AND AUTOANSWER CAPABIL-
ITY
PROGRAMMABLE TONE DETECTION AND
FSK V.21 FLAG PATTERN DETECTION
DURING HIGH SPEED RECEPTION
PROGRAMMABLE CALL PROGRESS AND
CALL WAITING TONE DETECTORS IN-
CLUDING DTMF
-
-
PQFP64
(Plastic Quad Flat Pack)
PROGRAMMABLE CLASS
CAPABILITY
DETECTION
-
-
ORDER CODE : ST75C520 PQFP
WIDE DYNAMIC RANGE (>48dB)
A-LAW VOICE PCM MODE
.
VERSATILE INTERFACES :
-
PARALLEL 64 x 8-BIT DUAL PORT RAM
SYNCHRONOUS/HDLC PARALLEL DATA
HANDLING
-
-
-
-
HDLC FRAMING SUPPORT
V.24 INTERFACE
FULL OPERATING STATUS REAL TIME
MONITORING
-
-
FULL DIAGNOSTIC CAPABILITY
DUAL 8-BIT DAC FOR CONSTELLATION
DISPLAY
1/45
June 1995
This is advance information on a new product now in development or undergoing evaluation. Detailsare subject to change without notice.
ST75C520
CONTENTS
Page
I
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
I.1
I.2
I.3
I.4
I.5
I.6
I.7
PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V.24 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MISCELLANOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOUNDARY SCAN INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
4
4
4
5
II
BLOCK DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
6
III
III.1
III.2
III.3
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
8
IV
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
IV.1
IV.2
IV.3
SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
11
V.
USER INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
V.1
V.2
V.3
V.4
V.5
DUAL PORT RAM DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA EXCHANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
14
16
17
17
VI
COMMAND SET DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATUS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
27
VII
VII.1
VII.2
COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
VIII
TONE DETECTORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
VIII.1
VIII.2
VIII.3
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
34
38
IX
BUFFER OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
IX.1
IX.2
IX.3
IX.4
IX.5
IX.6
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE OPERATIONS OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMIT OPERATIONS OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFFER STATUS AND FORMAT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA BUFFER MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
39
40
40
40
X
DEFAULT CALL PROGRESS TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEFAULT ANSWER TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB DESIGN GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
42
43
XI
XII
XIII
2/45
ST75C520
I - PIN DESCRIPTION
I.1 - Pin Connections
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
64
63
62
61
60
59
SA0
SA1
SA2
SA3
SA4
SA5
AGNDT
VCM
AVDD
RXA2
RXA1
AGNDR
VREFP
VREFN
EXTAL
XTAL
23
24
25
58
57
56
SA6
GND
VDD
SD0
SD1
SD2
SD3
26
27
28
29
30
31
32
55
54
53
52
51
50
49
CLKOUT
HALT
RESET
SD4
SD5
SCOUT
BOS
SD6
EOS
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
I.2 - Host Interface
The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between
the ST75C520 and the Host. The signals associated with this interface are :
Pin Name
Type
Description
SD0..SD7
I/O
System Data Bus. 8-bit data bus used for asynchronous exchanges between the ST75C520
and the Host through the dual port RAM. High impedance when exchanges are not active.
SA0..SA6
I
I
System Address Bus. 7-bit address bus for dual port RAM.
SDS (SRD)
System Data Strobe. Active low. Synchronizes all the exchanges. In Motorola mode initiates
the exchange, active low. In Intel mode initiates a read exchange, active low.
SR/W (SWR)
I
System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel
mode initiates a write exchange, active low.
SCS
I
System Chip Select. Active low.
SDTACK
SINTR
OD
OD
System Bus Data Acknowledge. Active low. Open drain.
System Interrupt Request. Active low. This signal is asserted by the ST75C520 and
negated by the host. Open drain.
RESET
RING
I
I
I
Reset. Active low.
Ring Detect Signal. Active low.
Select Intel/Motorola Interface.
INT/MOT
3/45
ST75C520
I.3 - Analog Interface
Pin
Type
Name
Description
TXA1
TXA2
O
O
Transmit Analog Output 1
Transmit Analog Output 2. Outputs TXA1 and TXA2 provide analog signals with maximum peak to peak
amplitude 2 x VREF, and must be followed by an external continous-time two pole smoothing filter (where
VREF = VREFP - VREFN).
RXA1
RXA2
I
I
Receive Analog Input 1
Receive Analog Input 2. The analog differential input peak to peak signal must be less than 2 x VREF. It
must be preceded by an external continous-time single pole anti-aliasing filter. This filter must be as
close as possible to the RXA1 and RXA2 Pins (where VREF = VREFP - VREFN).
VCM
I/O
Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND.
VREFN
VREFP
I
I
Analog Negative Reference (nominal VCM - 1.25V). This input must be decoupled with respect to VCM
Analog Positive Reference (nominal VCM+1.25V). This input must be decoupled with respect to VCM
.
.
I.4 - V.24 Interface
Pin Name
RTS
Type
Description
I
Request to Send. Active low.
CLK
O
O
O
I
Data Bit Clock. Falling edge coïncides with DATA change.
Clear to Send. Active low.
CTS
RxD
Receive Data
TxD
Transmit Data sampled with rising edge of CLK
Carrier Detect. Active low.
CD
O
I.5 - Miscellaneous
Pin Name
XTAL
Type
Description
Internal Oscillator Output. Left open if not used.
Internal Oscillator Input, or External Clock
Constellation X analog coordinate
Constellation Y analog coordinate
To be left open
O
I
EXTAL
EYEX
O
O
EYEY
TEST1
TEST2
To be left open
Note : The nominal external clock frequency of the ST75C520 is 29.4912MHz with a precision better than ± 5.10-5
I.6 - Boundary Scan Interface
A set of 13 signals are dedicated for Testing the ST75C520 Component. These signals can be used in a
development phase, associated with the SGS-THOMSON ST18932 Boundary Scan Development Tools,
to Debug the application Hardware and Software. If not used all input signals must be grounded and all
output signals left open.
Pin Name
SCIN
Type
Description
I
I
Scan Data Input
Scan Clock
SCCLK
SCOUT
BOS
O
I
Scan Data Output
Begin of Scan Control
End of Scan
EOS
I
MC0..MC2
HALT
I
Mode Control
I
Stop ST75C520 Execution
Multicycle Instruction
Ready to Scan Flag
MCI
O
O
I
RDYS
EBS
Enable Boundary Scan. Active low (must be set low in normal mode).
Internal ST75C520 Clock (XTAL frequency divided by 2)
CLKOUT
O
4/45
ST75C520
I.7 - Power Supply
Symbol
Parameter
VDD
Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below).
Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below).
Analog +5V (Pin 62). To be connected to VDD (see below).
GND
AVDD
AGNDT
AGNDR
Analog Transmit Ground (Pin 64). To be connected to GND (see below).
Analog Receive Ground (Pin 59). To be connected to GND (see below).
AGNDT and AGNDR must be connected together as close as possible to the chip.
GND and AGNDR board plans should be separated, then connectedtogether as close as possible to the
chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a
single point.
II - BLOCK DIAGRAMS
II.1 - Functional Block Diagram
15
16
14
ST75C520
1
2
TXA2
TXA1
HDLC
TX
V.17, V.29, V.27
FAX TRANSMITTER
TX
ANALOG
MUX
SD [0..7]
(26 to 33)
DUAL RAM
INTERFACE
DPLL
60 RXA1
RXA2
HDLC
RX
V.17, V.29, V.27
FAX RECEIVER
RX
ANALOG
61
TONE
DETECTOR
HANDSHAKE AND
STATUS REPORT
SINTR 38
V.21 FLAG
DETECTOR
V.24
INTERFACE
RING
DETECTOR
13 12 11
10
5/45
ST75C520
II.2 - Hardware Block Diagram
ST75C520
PROGRAM ROM 8K x 32
XTAL
55
56
EXTAL
12
ST18932
DSP CORE
RAM
2K x 16
BOUNDARY SCAN
(42 to 51 - 53-54)
TXA2
TXA1
1
2
FIFO
8 x 16
IIR
FIR
EBS
3
RESET 52
58 VREFP
63 VCM
7
DPLL AND CONTROL
SA [0..6]
(17 to 23)
57 VREFN
60 RXA1
61 RXA2
SD [0..7]
(26 to 33)
8
DUAL
PORT
RAM
FIFO
8 x 16
SDS (SDR) 34
SR/W (SWR) 35
SCS 36
FIR
IIR
FIR
P
A
G
E
S
S
S
I
64 x 8
E
Y
E
CROM
8K x 16
SDTACK 37
SINTR 38
O
V.24 INTERFACE
INT/MOT 39
8-24
40
9-25
41
11 12 13 14 10
16 15
7
6
5
4
59 62 64
III - ELECTRICAL SPECIFICATIONS
Unless otherwise noted, electrical characteristics are specified over the operating range. Typical value are
given for VDD = +5V and tamb = 25°C.
III.1 - MaximumRatings (referenced to GND)
Symbol
VDD
Parameter
Value
Unit
V
DC Supply Voltage
-0.3 to 7.0
VI, VIN
II, IIN
IO
Digital or Analog Input Voltage
Digital or Analog Input Current
Digital Output Current
-0.3 to (VDD + 0.3)
V
±
mA
mA
mA
°C
1
±
±
20
10
IOUT
Analog Output Current
Toper
Tstg
Operating Temperature
0, + 70
- 40, + 125
1000
Storage Temperature (plastic)
Maximum Power Dissipation
°C
Ptot
mW
Stresses above those hereby listed may cause damage to the device. The ratings are stress related only and functional operation of the device
at conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the
device.
III.2 - DC Characteristics
V
DD = 5.0V ± 5%, GND = 0V, Tamb = 0 to 70°C (unless otherwise specified).
III.2.1 - Power Supply and Common Mode Voltage
Symbol
VDD
Parameter
Min.
Typ.
5
Max.
5.25
100
Unit
V
Supply Voltage
4.75
IDD
Supply Current (internal oscillator)
Supply Current in Low Power Mode
Common Mode Voltage
75
mA
mA
V
IDD-lp
VCM
1
VDD/2 -5%
VDD/2
VDD/2 + 5%
6/45
ST75C520
III.2.2 - Digital Interface
All digital pins except XTAL Pins.
Symbol
Parameter
Min.
-0.3
2.2
Typ.
Max.
Unit
V
VIL
VIH
II
Low Level Input Voltage
High Level Input Voltage
0.8
V
Input Current VI = VDD or VI = GND
-10
0
+10
µA
V
VOH
VOL
IOZ
High Level Output Voltage (Iload = 2mA)
Low Level Output Voltage (Iload = 2mA)
2.4
0.4
50
V
Three State Input Leakage Current (GND < VO < VDD
)
-50
0
5
µ
A
CIN
Input Capacitance
pF
Crystal oscillator interface (XTAL, EXTAL).
Symbol
VIL
Parameter
Min.
Typ.
Max.
Unit
V
Low Level Input Voltage
1.5
VIH
High Level Input Voltage
3.5
-15
V
IL
Low Level Input Current GND < VI < VILmax
High Level Input Current VIHmin < VI < VDD
µ
µ
A
A
IH
15
III.2.3 - Analog Interface
Symbol
Parameter
Min.
Typ.
2.50
Max.
Unit
V
VREF
Differential Reference Voltage Input = VREFP - VREFN
Input Common Mode Offset, v = (RXA1+RXA2)/2 - VCM
Differential Input Voltage RXA1 - RXA2
2.40
-300
2.60
300
VCMOin
VDIFin
VCMOout
VDIFout
VOFFOut
Rin
mV
VPP
mV
VPP
mV
kΩ
Ω
2 x VREF
200
Output Common Mode Voltage Offset = (TXA1+TXA2)/2 - VCM
Differential Output Voltage TXA1 - TXA2
-200
2 x VREF
100
Differential Output DC Offset (TXA1 - TXA2)
-100
100
Input Resistance
Output Resistance
Load Resistance
Load Capacitance
RXAx
TXAx
TXAx
TXAx
Rout
20
50
RL
10
kΩ
CL
pF
7/45
ST75C520
III.3 - AC Electrical Characteristics
III.3.1 - Dual Port RAM Host Timing
WRITE-CYCLE TIMING
READ-CYCLE TIMING
NSCS
SA[0..6]
SR/NW
Valid Address
Valid Address
1
7
4
5
1
9
4
5
NSDS
8
12
3
10
Valid Data
IN
Valid Data
OUT
SD[0..7]
2
6
2
6
NSDTACK
NSINTR
11
SR/NW (= NWRITE)
NSDS (= NREAD)
Number
Description
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
Address and Control Set-up Time
SDTACK Acknowledge
Data Set-up Time
5
20
3
10
0
4
Address and Control Hold Time
Data Hold Time
5
5
6
SDTACK Hold Time
0
7
Write Enable Low State
Access Inhibition High State (see Note)
Read Enable Low State
Read Data Access
45
70
45
8
9
10
11
12
35
50
15
SINTR Clear Delay
Data Valid to Tristate
Note : A minimum delay of 70ns is required only from the rizing edge of NWRITE to the falling edge of the next selected NREAD or NWRITE.
8/45
ST75C520
III.3.2 - Serial V.24 Interface Timing
CLK
1
2
TXD
RXD
Valid Data In
3
Valid Data Out
4
Number
Description
Min.
30
Typ.
Max.
Unit
ns
1
2
3
4
TXD to CLK Set-up Time
TXD to CLK Hold Time
10
ns
RXD Valid to CLK Delay Time
RXD Valid to CLK Hold Time
100
ns
0
ns
9/45
ST75C520
IV - FUNCTIONAL DESCRIPTION
IV.1 - System Architecture
IV.2.6 - DTMF Detector Description
A DTMF Detector is included in the ST75C520, it
allows detectionofvalid DTMF Digits. AvalidDTMF
Digit is defined as a dual Tone with a total power
higher than -35dBm, a duration higher than 40ms
and a differential amplitude within 8dB (negativeor
positive).
The chip allows the design of a complete FAX
data-pump without any externalcomponent. Aver-
satile dual port RAM allows an easy interface with
most micro-controllers.
IV.2 - Operation
IV.2.1 - Modes
IV.2.7 - Voice Mode
The ST75C520 voice mode allows the implemen-
tation of enhanced telephone functions like an-
swering machines. The incoming samples
(9600Hz), received from the line are PCM A-law
coded and writen into the dual port RAM. The
outpoing samples are decompressed using the
same A-law and output to the telephone line.
The modem implementationisfullycompatible with
FAX modulation recommendations. The modula-
tion can be either Trellis Coded Modulation (TCM)
as in V.17 14400, 12000, 9600, 7200bps rates,
Quadrature Amplitude Modulation (QAM) as in
V.29 9600, 7200, 4800 and V.27ter 4800 and
2400bps. Other modes of operation include tone
and DTMF detection or generation, or speech
mode.
The voice mode is entered using a CONF com-
mand, it can be either transmit voice from the dual
RAM Tx buffer to the telephone line, receive voice
from the telephone line to the dual RAM buffer, or
both of these functions simultaneously. The format
of the signal is A-law coded without complementa-
tion of the even bits. The buffer mechanism, be-
tween the host micro-controler and the ST75C520,
is identicalto the mechanism used for parallel data
exchanges except that it starts immediately after
CONF command, the size of the transmit and
received buffer, are and must be 8 bytes, there is
no need for a XMIT command, and if an overrun or
underrun condition occurs no error will be reported
to the host processor.
IV.2.2 - Transmitter Description
The signal pulses are shaped in a dedicated filter
further combined with a compromise transmit
equalizersuited for transmission over strongly dis-
torted lines. 3 different compromise equalizers are
available and can be selected by software.
IV.2.3 - ReceiverDescription
The receiver section handlescomplex signals and
uses a fractionally spaced complex equalizer. It is
able to cope with distant modem timing drifts up to
10-4 as specified in the ITU-T recommendations. It
also compensatefor frequencydrift up to 10Hzand
for phase jitter at multiple and simultaneous fre-
quencies.
IV.2.8 - Analog Loop Back Test Mode
In any transmission standard and serial data for-
mat, the ST75C520 can be configured for analog
loop back test.
IV.2.4 - Tone Generator Description
IV.2.9 - Low Power Mode
Four tonescan besimultaneouslygeneratedbythe
ST75C520. The tones are determined by their
frequenciesandby theoutputamplitudelevel.Aset
of specific commands are also available for DTMF
generation(using two of the four generatorsavail-
able).
Sleep state can be attainedby a SLEEPcommand.
Activating the reset signal will wake up the data-
pump. When in sleep mode, the dual port RAM is
unavailableand the clocks are disabled.
When enteringthe lowpowermode, the ST75C520
stops its oscillator, all the peripherals of the DSP
core are stopped in order to reduce the power
consumption. The dual RAM is made inacessible.
IV.2.5 - Tone Detector Description
Sixteen tones can be simultaneously detected by
the ST75C520. Each of the tones to bedetected is
defined by the coefficients of a 4th order program-
mable IIR. Detectionthresholds are also program-
mable from-45dBm up to -10dBm.DTMF detection
is also availableand is performed by a specificfilter
section (that requires no programming).
The ST75C520 can be awakened by a hardware
reset.
There is a maximum time of 20ms to restart the
oscillator after waking up and an additional 5ms
after the interrupt to be able to accept any com-
mand coming from the host.
10/45
ST75C520
IV.2.10 - Reset
V.1.1 - Mapping
After a hardware reset, or an INIT command, the
ST75C520 clears all its internal memories, clears
the whole dual RAM and starts to initialize the delta
sigma analog converters. As soon as these initiali-
zations are completed, the ST75C520 clears the
dual RAM address 0 (COMSYS), generates an
interrupt IT6 (command acknoledge) and is pro-
grammed to send and receive tones, the bit clock
and the sample clock are programmed to 9600Hz.
The total duration of the reset sequence is about
5ms. After that time the ST75C520 is ready to
execute commands sent by the host micro-control-
ler. Thedurationofthe resetsignalshouldbegreater
than 700ns.
V.1.1.1 - Command Area
The command area is located from $00 to $04.
Address $00 holds the command byte COMSYS,
and the next four locations hold the parameters
COMPAR[0..3]. The command parameters must
be entered before the command word is issued.
Once the command has been entered, the com-
mand byte is reset and an acknowledge report is
issued. A new command should not be issued
before theacknowledgecounterCOMACK isincre-
mented.
V.1.1.2 - Report Area
The report area is located from address $05 to
address $07. Location $05 holds the acknowledge
counter COMACK. Each time a command is ac-
knowledged, the report bytes COMREP[0..1] (if
any) are written by the ST75C520 into locations
$06 and $07, and the content of COMACK is
incremented. This counter allows the ST75C520 to
accurately monitor the command processing.
IV.3 - Modem Interface
IV.3.1 - Analog Interface
The modemdesigner must provide a proper hybrid
interface to the ST75C520. An example of hybrid
design is given in paragraphs XII and XIII. The
inputs and outputs of the MAFE are differential,
achieving thus a better noise immunity. The D/A
converter output amplifier includes a single pole
low-pass filter, its cut-off frequencyis :
V.1.1.3 - Status Area
Fc - 3dB # 19200Hz.
The statusarea islocated from address$08to $0A.
The error status word SYSERR is located at ad-
dress $08. This error status word is updated each
time anerrorcondition occurs. An optionalinterrup-
tion IT0 may additionally be triggered in the case
of an error condition. Locations $09 and $0A hold
the general status bytes STATUS[0..1]. The mean-
ing of the bits depends on the mode of operation,
and is described in Chapter VII. The third byte at
address $0B holds the Quality Monitor byte
STAQUA.
Continuous-time filtering of the analog differential
output is necessary using an off-chip amplifier and
a few external passive components.
IV.3.2 - Host Interface
The host interface is seen by the micro as a 64x8
RAM, with additional registers accessible through
an 8-bit address space. A selection Pin (INT/MOT)
allows to configure the host bus for either INTEL or
MOTOROLA type control signals.
V.1.1.4 - Optional Status Area
V - USER INTERFACE
The user can program (through the DOSR com-
mand) the three locations STAOPT[0..2] of the
Optional Status Area ($0C to $0E) for the real time
monitoring of three arbitrary memory locations.
V.1 - Dual Port Ram Description
Thedual port RAM is thestandard interfacebetween
the controller and the ST75C520, for either com-
mands ordata.This memory is addressedthrougha
7-bit address bus. The locationsfrom $00 to $3F are
RAM locations, while locations from $40 to $50 are
control registers dedicated to the interrupt handling.
Severalfunctionalareasare definedin thedualport
RAM, namely :
- the command area,
V.1.1.5 - Data Buffer Area
The data area is made of four 8-byte buffers. Two
are dedicated to transmission and the two others
to reception. Each of the four buffers is attached to
a status byte. the meaning of the status byte de-
pends on the selected format of transmission.
Within each buffer, D0 represents the first bit in
time.
- the report area,
- the status area,
- the data buffer area.
11/45
ST75C520
V.1.2 - Interruptions
- IT3 : Rx Buffer
Each time the ST75C520 has filled a buffer, this
interrupt is generated.
The ST75C520 can generate 5 interrupts for the
controller. The interrupt handlingis made with a set
of registers located from $40 to $50.
The interruptions generated by the ST75C520
come from several different sources. Once the
ST75C520 raises an interrupt, a signal is sent to
the controller. The controller has then to process
the interrupt and clear it. The interrupt source can
be examined in the Interrupt Source Register
ITSRCR located at $50. According to this status
byte, the interrupt sourcecan be determined.Then,
writing a zero at one of the memory location $40 to
$46 (Reset Interrupt Registers ITREST[0..6]) will
reset the corresponding interrupt (and thus ac-
knowledge it). These sources of interruptions can
be masked globally or individually using the Inter-
rupt Mask Register ITMASK located at $4F.
- IT4 : Status Byte
This signifies that the status byte has changed
and must be checked by the controller.
- IT6 : Command Acknowledge
This signifies thatthe ST75C520hasreadthelast
command entered by the host, incremented the
command counter COMACK, and is ready for a
new command.
ITSRCR
X
D6
X
D4 D3 D2
X
D0
D0 = 1
D2 = 1
Dn = 1
IT0 Pending
IT2 Pending
ITn Pending
The interrupt sources are :
- IT0 : Error/Warning
This signifies that an error has occurred and the
error code is available in the error status byte
SYSERR.This byte can be selectivelycleared by
the CSE command.
ITMASK D7 D6
X
D4 D3 D2
X
D0
D7 and D0 = 1 IT0 EnableD
D7 and D2 = 1 IT2 EnableD
...................... .....................
D7 and D6 = 1 IT6 EnableD
- IT2 : Tx Buffer
Each time the ST75C520 frees a buffer, this
interrupt is generated.
12/45
ST75C520
V.1.3 - Host Interface Summary
Address (hex)
Description
Size (Byte)
Mnemonic
COMMAND AREA
$00
Command
1
4
COMSYS
$01-$04
Command Parameters
COMPAR[0..3]
REPORT AREA
$05
Acknowledge Counter
Report
1
2
COMACK
$06-$07
COMREP[0..1]
STATUS AREA
$08
Error Status
1
2
1
3
SYSERR
$09-$0A
$0B
General Status
Quality Monitor
Optional Report
STATUS[0..1]
STAQUA
$0C-$0E
STAOPT[0..2]
DATA AREA
$1C
Data Rx Buffer 0 Status
Data Rx Buffer 0
1
8
1
8
1
8
1
8
DTRBS0
$1D-$24
$25
DTRBF0[0..7]
DTRBS1
Data Rx Buffer 1 Status
Data Rx Buffer 1
$26-$2D
$2E
DTRBF1[0..7]
DTTBS0
Data Tx Buffer 0 Status
Data Tx Buffer 0
$2F-$36
$37
DTTBF0[0..7]
DTTBS1
Data Tx Buffer 1 Status
Data Tx Buffer 1
$38-$3F
DTTBF1[0..7]
INTERRUPT AREA
$40-$46
$4F
Reset Interrupt Reg.
Interrupt Mask Reg.
Interrupt Source Reg.
7
1
1
ITREST[0..6]
ITMASK
$50
ITSRCR
13/45
ST75C520
V.2 - Command Set
The Command Set has the following attractive
features :
SETGN Set Gain. This command sets the global
gain factor, which is used for thetransmit
samples. Parametric command.
- user friendly with easy to remember mnemonics,
- possibility of straightforwardexpansion with new
commands to suit specific customer require-
ments,
- easy upgradeof existing software using previous
modem based SGS-THOMSON products.
V.2.1.2 - Data Communication Commands
XMIT
Tra nsmit Data. Start/stop the
transmission of data in parallel mode.
After a XMIT command, the ST75C520
sends the data contained in its dual port
RAM.
The command set has been designed to provide
the necessary functional controlon the ST75C520.
Each command is classified according to its syntax
and the presence/absence of parameters. In the
case of a parametric command, parameters must
first be written into the dual port RAM before the
command is issued. Acknowledge and error report
is issued for each command entered.
SERIAL Select Serial or Parallel Mode. This
command selects the data source, i.e.
either parallel or serial. The parallel
mode uses a part of the dual port RAM
as a double buffer. Theserial mode uses
the serial synchronous I/O. Parametric
command.
V.2.1 - Command Set Summary
FORM SelectstheTransmission Format(only in
para llel mode). Th is comma nd
configures the data interface for both
receiver and transmitter according to the
selected data format. Parametric
command (HDLC or synchronous). In
serial mode, format is always
synchronous.
V.2.1.1 - Operational Control Commands
INIT
Initialize. Initialize the modem engine.
Set all parameters to their default values
and wait for commands of the control
processor. Non parametric command.
IDT
Identify. Return the product identification
code. Non parametric command.
SLEEP Turn to low power mode, the ST75C520
enters the low power mode and stops its
crystal oscillator to reduce power
consumption. In this mode all the clocks
are stopped and the dual RAM is
unreachable.
V.2.1.3 - Memory Handling Commands
MW
MR
CR
Memory Write. This command is used to
write an arbitrary 16-bit value into the
writable memory location currently
specified by a parameter. Parametric
command.
Memory Read.Thiscommand allows the
controller to read any of the ERAM or
CROM (ST75C520 memory spaces)
location without interrupting the
processor. Parametric command.
Complex Read. This command allows
the controller to read at the same time
the real and imaginary part of a complex
value stored in a double ERAM or
CROM location. This feature is very
interesting for eye pattern software
control and for equalization monitoring.
This command insures that the real and
imaginary parts are sampled in the
memory at the same time (integrity).
Parametric command.
HSHK
Handshake. Begins the handshake
sequence. The modem engine
generates all the sequences defined in
the ITU-T recommendations. A status
report indicates to the control processor
the state of the handshake. This
command only applies to modes where
a handshake sequence is defined. A
CONF commandmust havebeen issued
prior to the use of HSHK. Non parametric
command.
STOP
SYNC
FAX Stop. Stop FAX Half-duplex
transmitter. Non parametric command.
FAX Synchronize. Start/Stop of FAX
Half-duplex receiver. Parametric
command.
CSE
Clear Status Error. Selectivelyclears the
Error status byte SYSERR. Parametric
command.
14/45
ST75C520
V.2.1.4 - Configuration Control Commands
DEFT
TGEN
Define Tone. Programs the tone
generator(s)for arbitrary tone synthesis.
Parametric command.
Tone Generator Control. Enables or
disables the tone generator(s).
Parametric command.
CONF
Configure.This commandconfiguresthe
modemenginefor datatransmission and
handshake procedures (if any) in any of
the supported modes. The transmission
parametersare set to theirdefaultvalues
and can be modified with the MODC
command. Parametric command.
IV.2.1.6 - Tone Detection Commands
TDRC Read Tone Detector Coefficient. Read
one Tone Detector Coefficient.
Parametric command.
TDWC Write Tone Detector Coefficient. Write
one Tone Detector Coefficient.
Parametric command.
TDRW Read Tone Detector Wiring. Read one
Tone Detector Wiring connection.
Parametric command.
TDWW Write Tone Detector Wiring. Write one
Tone Detector Wiring connection.
Parametric command.
MODC Modify Configuration. This command
allows modification of some of the
parameters which have been set up by
the CONF command. It can also be used
to alter the mode of operations (short
train). Parametric command.
DOSR
Define Optional Status Report. This
command allows the modification of the
optional status report located in the
status area of the dual port RAM. One
can thus select a particular parameter to
be monitored during all modes of
operation. Parametric command.
DSIT
Define Status Interrupt. This command
allows the programming of the status
word bit that will generate an Interrupt to
the controller. Parametric command.
TDZ
Clear Tone Detector Cell. Clear internal
variables of a Tone Detector Cell.
Parametric command.
V.2.1.5 - Tone Generation Commands
TONE Select Tone. Programs the tone
V.2.1.7 - MiscellaneousCommands
CALL
Call a Subroutine. Call a subroutine with
one Parameter. Parametric command.
generator(s) for the desired default
tone(s). Additional mnemonics provide
quick programming of DTMF tones or
other currently used tones. Parametric
command.
JSR
Call a Low Level Subroutine. Call an
internal subroutine with one parameter.
Parametric command.
15/45
ST75C520
V.3 - Command Set Short Form
CCI Command
Mnemonic
XMIT
Value
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x09
0x0A
0x0C
0x0D
0x0E
0x10
0x11
0x12
0x13
0x14
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x25
0x26
Description
Transmit Data
SETGN
SLEEP
HSHK
INIT
Set Transmit Gain
Power Down the ST75C520
Start Handshake
Initialize (Software Master RESET)
Enable/disable Data Serial Mode
Clear Error Status Word
Define Parallel Data Format
Define Optional Status Report
Generate Predefined Tones
Enable Tone Generator
Define Arbitrary Tone
SERIAL
CSE
FORM
DOSR
TONE
TGEN
DEFT
MR
Memory Read
CR
Complex Read
MW
Memory Write
DSIT
Define Status Interrupt
Return Product Identification Code
Call a Low Level Subroutine
Call a Subroutine
IDT
JSR
CALL
TDRC
TDRW
TDWC
TDWW
TDZ
Tone Detector Read Coefficient
Tone Detector Read Wiring
Tone Detector Write Coefficient
Tone Detector Write Wiring
Tone Detector Clear Cell
Configure
CONF
MODC
STOP
SYNC
Modify Default Configuration
FAX Stop Transmitter
FAX Synchronize Receiver
16/45
ST75C520
V.4 - Status - Reports
V.4.1 - Status
V.5.1.1 - Transmit
Thecontrollermust firstfill atleastthefirstbufferof data
(Tx Buffer0) with the bits to be transmitted. In orderto
perform this operation, the controller must first check
the Tx Buffer 0 status word DTTBS0. If this buffer is
empty, the controller fills the data buffer locations(up
to 64 bits), and then writes in DTTBS0 the number of
bytescontained in the buffer. The controllercan then
either proceed with the second buffer or initiate the
transmission with a XMIT command.
The ST75C520 copies the contents of the data
buffer and then clears the buffer status word in
order to make it again available, then generatesan
IT2 interrupt. The number of bytes specified by the
status word is then queued for transmission. The
process goes on with the two buffers until an XMIT
command stops the transmission. After the finish-
ing XMIT command has been issued, the last buff-
ers are emptied by the ST75C520.
The ST75C520 has a dedicated status reporting
area located in its dual port RAM. This allow a
continuous monitoring of the status variables with-
out interrupting the ST75C520.
The first status byte gives the error status. Issuing
of an error status can also be flagged by a mask-
able interrupt for the controller. The signification of
the error codes are given in Chapter VII.
The second and third status bytes give the general
status of the modem. These status include for
example the ITU-T circuit status and other items
described in appendix. These two status can gen-
erate, when a change occurs, an interrupt to the
controller ; each bit of the two byte word can be
masked independently.
The forth byte gives in real time a measure of the
reception quality. This information may be used by
the controller to monitor the quality of the received
bits.
Errors occur when bothbuffers are empty while the
transmit bit queue is also empty. Error is signalled
with an IT0 interruption to the controller.
Three other locations are dedicated for custom
status reporting. The controller can program the
ST75C520 for a real time monitoring of any of its
internal RAM location. High byte or low byte of any
word can thus be monitored.
V.5.1.2 - Receive
The controller should take care of releasing the Rx
buffers before the Data Carrier Detect goes true.
This is made by writing zero in the Rx Buffer Status
0 and 1. The ST75C520 then fills the first buffer,
and oncefilled setsthe statusword withthe number
of bytes received and then generates an IT3 inter-
rupt. It then takes control of the second buffer and
operates the same way. The controller must check
the statusof the buffers and empty them. Once the
data read, the controller must release the used
buffer and wait for the next buffer to be filled.
Error occurs when both buffers are declared full,
and incoming bits continue to arrive from the line.
Error is signaled by an IT0 interrupt.
V.4.2 - Reports
The ST75C520 features an acknowledge and re-
port facility. The acknowledge of a command is
monitored by a counter COMACK located in the
dual port RAM. Each time a command is read from
the command area, the ST75C520 will increment
this counter. For instance, when a MR (Memory
Read) command is issued, the data is first written
in the report area, and the counter is incremented
afterwards. This way of processing insures data
integrity and gives additional synchronization be-
tween the controller and the data pump.
V.5.2 - HDLC Parallel Mode
This mode implements part of the High Level Data
Link Control formats and procedures. It is well
suited for error correcting protocols like ECM or
FAXT4/T30 recommendations.It supportstheflag-
ging generation,16-bitFrame Check Sequence,as
well as the Zero insertion/deletionmechanism.
V.5 - Data Exchanges
The ST75C520 accepts many kinds of data ex-
change : the default mode uses the synchronous
serial exchange. Other modes include HDLC fram-
ing support and synchronous parallel exchanges.
Detailed description of the Data Buffer Exchanges
modes is available in the paragraph IX.
V.5.3 - Serial Exchanges
The other mode of operation for data exchangesis
the Serial Synchronous Mode. In this mode, the
data I/O is made through the V.24 interface (page
4). Even when using the parallel mode described
above, the received bits are available on the
ST75C520 RxD Pin. See paragraph VII.2.1 table
for clock values.
V.5.1 - Synchronous Parallel Mode
The data exchanges are made through the dual
port RAM and are byte synchronous oriented. The
double buffer facilities of the ST75C520 allow an
efficient buffering of the data.
17/45
ST75C520
VI - COMMAND SET DESCRIPTION
The appendixAcontainsthe descriptionofthecomplete command set.Commandsare presentedaccording
to the following form :
COMMAND
Command Name Meaning
COMMAND
Opcode
Hexadecimal digit
X
X
X
X
X
X
X
X
Synopsis
Short description of the functions performed by the command.
Parameters
Field
Byte
Pos.
Value
Definition
Name
X
b..a
Explanation of the parameter
Default value
xx *
Field
Byte
Pos.
Name of the addressed bit field.
Index (or address in the dual port RAM) of the parameter byte (from 1 to 4).
Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0
being LSB) or a range.
Value
Possible values for the bit (resp. bit field). Range means all values are allowed. A star
means a defaultvalue. Values are expressed either under the form of a bit string, or under
hexadecimal format.
CALL
Opcode:
Call a Subroutine
CALL
19
0
0
0
1
1
0
0
1
Synopsis
CALL allows to executea part of the ST75C520 firmware with a specificargument.
Parameters
Field
Byte
Pos.
7..0
7..0
7..0
7..0
Value
Definition
Low byte of the call address
High byte of the call address
Low byte of the argument
High byte of the argument
C_ADDR_L
C_ADDR_H
C_DATA_L
C_DATA_H
1
2
3
4
18/45
ST75C520
CONF
Configure for Operations
CONF
Opcode
20
0
0
1
0
0
0
0
0
Synopsis
CONF allows the complete definition of the ST75C520 operation, including the mode of
operation(tone, FAX transmit, FAX receive, voice transmit, voice receive, DTMF receive, ...)
and the modem parameters (standard, speed, ...).
Field
Byte
Pos.
3..0
4
Value
Definition
Parameters
CONF_OPER
CONF_ANAL
1
1
-
Mode of operation, see below
0
1
Normal mode
Analog loop back (test mode only)
CONF_PSTN
CONF_AO
1
1
1
2
5
6
0
1
PSTN (carrier detect set to -43/-48dBm)
Leased line (carrier detect -33/-38dBm)
0
1
Answer mode (FSK full duplex only)
Originate mode (FSK full duplex only)
CONF_V24
CONF_MODE
7
0
1
Do not use RTS pin signal
Use RTS pin signal
5..0
1
Bell 103 (full duplex)
V.21 (full duplex)
V.23 (full duplex)
V.27ter
V.29
V.17
V.33 (half duplex)
V.21 channel 2
Reserved
3
4
7
8
9
C
D
Other
CONF_TXEQ
2
7..6
0
1
2
3
No transmit equalizer
Transmit equalizer #1
Transmit equalizer #2
Transmit equalizer #3
CONF_CAR
CONF_SP0
3
3
0
0
1
1800Hz carrier (V.17/V.33 only)
1700Hz carrier (V.17/V.33 only)
7..5
xx1
x1x
1xx
2400bps allowed (V.27)
4800bps allowed (V.27, V.29)
7200bps allowed (V.29, V.17)
CONF_SP1
4
2..0
xx1
x1x
1xx
9600bps allowed (V.29, V.17)
12000bps allowed (V.17, V.33)
14400bps allowed (V.17, V.33)
According with the 4 first bits of the CONF_OPER the ST75C520 is put into the following
mode of operation.
CONF_OPER
0000*
0010
Transmit
Received
Tones
Voice
Tone
Tones
Tones
DTMF
DTMF
Voice
0100
0110
Voice
Tones
Voice
Modem
1000
1010
Voice
1111
Modem
Other
Not allowed
Not allowed
19/45
ST75C520
CR
Complex Read
CR
Opcode:
11
0
0
0
1
0
0
0
1
Synopsis
CR allows the reading of a complex parameter. The parameter specifies the parameter
address (for the real part : the imaginary part is next location). CR returns the high byte
value of both real and imaginary part of the addressed complex parameter.
Field
Byte
Pos.
7..0
7..0
Value
Definition
Low byte of the 16-bit address
High byte of the 16-bit address
Parameters
CR_ADDR_L
CR_ADDR_H
1
2
CSE
Clear Error Status
CSE
Opcode:
08
0
0
0
0
1
0
0
0
Synopsis
CSE is used to clear the ST75C520 error status SYSERR byte. It is also used as an
acknowledge to the error condition handler. For details, please refer to the corresponding
appendix.
Field
Byte
Pos.
Value
Definition
Parameters
ERR_MASK
1
7..0
Error mask
See report appendix for detailed meaning
DEFT
Define Arbitrary Tone
DEFT
Opcode:
0E
0
0
0
0
1
1
1
0
Synopsis
DEFT programsoneof the fourtone generatorforarbitrarytone generation.The parameter
is the frequency of the generated tone expressed in Hertz between 0 and 3600Hz.
Field
Byte
Pos.
1..0
7..0
7..0
Value
Definition
Index of the tone generator (3..0)
Low byte of the frequency
Parameters
TONE_GEN_SL
TONE_FREQ_L
TONE_FREQ_H
1
2
3
High byte of the frequency
(internally masked with 0F)
TONE_SCALE
4
7..0
Amplitude scaling factor (high byte)
3F gives the nominal amplitude
DOSR
Define Optional Status Report
DOSR
Opcode:
0A
0
0
0
0
1
0
1
0
Synopsis
DOSR specifies the address of the RAM variables to be monitored in the 3 locations
STAOPT[0..2] of the dual port RAM. It also specifiesthe assignment within the 3 locations.
Field
Byte
Pos.
1..0
7..0
3..0
7
Value
Definition
Index of the STAOPT destination
Low byte of source address
High byte of source address
Parameters
STA_OPT_ASS
STA_OPT_ADL
STA_OPT_ADH
STA_OPT_HL
1
2
3
3
0..2
0
1
Select low byte of source
Select high byte of source
20/45
ST75C520
DSIT
Opcode:
Define Status Interrupt
DSIT
13
0
0
0
1
0
0
1
1
Synopsis
DSIT specifies the bit mask used with the STATUS[0] and STATUS[1] byte to generate an
interrupt IT4 to controller. Each time a bit change happens in the status words, assuming
the corresponding bit mask will be set, an interrupt will be generated.
Parameters
Field
Byte
Pos.
7..0
7..0
Value
Definition
Status[0] bit mask pattern
Status[1] bit mask pattern
STA_IT_MSK0
STA_IT_MSK1
1
2
Notes :
The default IT Status is 0x3F for STATUS[0] and 0xFF for STATUS[1].
FORM
Opcode:
Select Transmission Format
FORM
09
0
0
0
0
1
0
0
1
Synopsis
FORM defines the type of transmission used. This format is valid only in the parallel data
mode. The default format, unless specified, is synchronous.
Parameters
Field
Byte
Pos.
Value
Definition
X_SYNC
1
1..0
00*
01
10
11
Synchronous format
Transmit continous ”1” (1)
HDLC framing
Transmit continous ”0” (1)
Notes :
1. This format is only valid for the transmiter.
HSHK
Opcode:
Handshake
HSHK
04
0
0
0
0
0
1
0
0
Synopsis
HSHK is used to command the ST75C520 to begin the transmit handshake sequence
processing. The progress of the handshake is reported to the control processor.
Parameter
Non parametric command.
IDT
Opcode:
Identify
IDT
14
0
0
0
1
0
1
0
0
Synopsis
Parameter
IDTReturn the ST75C520HardwareandSoftwarerelease number.See paragraph VII.1.4.
Non parametric command.
INIT
Opcode:
Initialization
INIT
06
0
0
0
0
0
1
1
0
Synopsis
INIT forces the ST75C520 to reset all parameters to their default conditions and restart
operations.
Parameter
Non parametric command.
Notes :
This command makes a software reset of the ST75C520 and so cannot have the regular handshake protocol. It does
not increment the COMACK, neither generate an Interrupt.
21/45
ST75C520
JSR
Call a Low Level Subroutine
JSR
Opcode:
18
0
0
0
1
1
0
0
0
Synopsis
JSR allows to execute a part of the ST75C520 firmware with a specific argument.
Parameters
Field
Byte
Pos.
7..0
7..0
7..0
7..0
Value
Definition
Low byte of the call address
High byte of the call address
Low byte of the argument
High byte of the argument
C_ADDR_L
C_ADDR_H
C_DATA_L
C_DATA_H
1
2
3
4
MODC
Modify Configuration
MODC
Opcode:
21
0
0
1
0
0
0
0
1
Synopsis
MODC allows modification of the configuration for special purpose. This command has no
effect while in data mode, the parameters are just sampled when starting to transmit or
receive. The value of these parameters are notaffected when sending a CONF command.
Parameters
Field
Byte
Pos.
Value
Definition
MODC_SH
1
6
0*
1
Normal training sequence
Short training (1) sequence
MODC_FPT
2
3..2
00*
01
10
No echo protection tone
Long echo protection tone (180ms)
Short echo protection tone (30ms)
Notes :
1. Short train sequence must be preceded by at least one normal training sequence.
MR
Memory Read
MR
Opcode:
10
0
0
0
1
0
0
0
0
Synopsis
MR allows the reading of a 16-bit parameter. The parameter specifies the parameter
address.
Parameters
Field
Byte
Pos.
7..0
7..0
Value
Definition
Low byte of the 16-bit address
High byte of the 16-bit address
MR_ADDR_L
MR_ADDR_H
1
2
MW
Memory Write
MW
Opcode:
12
0
0
0
1
0
0
1
0
Synopsis
MW allows the writing of a 16-bit parameter. The parameter specifies the address as well
as the value to be transferred.
Parameters
Field
Byte
Pos.
7..0
7..0
7..0
7..0
Value
Definition
Low byte of the 16-bit address
High byte of the 16-bit address
Low byte of the 16-bit value
High byte of the 16-bit value
MW_ADDR_L
MW_ADDR_H
MW_VALUE_L
MW_VALUE_H
1
2
3
4
22/45
ST75C520
SERIAL
Opcode:
Select Serial or Parallel Mode
SERIAL
07
0
0
0
0
0
1
1
1
Synopsis
SERIAL defines the data path, i.e. either serial or parallel.
Parameters
Field
Byte
Pos.
Value
Definition
TX_SDATA
1
0
0*
1
Use serial link for Tx Data
Use parallel link for Tx Data
RX_SDATA
1
1
0*
1
Use only serial link for Rx Data
Use also parallel link for Rx Data
Notes :
The received Bits always go to the output pin RXD, even when the RX_SDATA bit is set.
Set Output Gain
SETGN
Opcode:
SETGN
02
0
0
0
0
0
0
1
0
Synopsis
SETGN is a command which sets the scaling factor of the transmit samples. It is used for
setting the output level or for setting the level of the tone generators. The gain value is
given in the form of a 2’s complement 16-bit value.
Parameters
Field
Byte
Pos.
7..0
7..0
Value
Definition
GAIN_L
GAIN_H
1
2
range FF*
range 7F*
Low byte of the 16-bit gain value
High byte of the 16-bit gain value
Example
Gain (dB)
Gain (Hex)
Gain (dB)
Gain (Hex)
47FA
Gain (dB)
-10
Gain (Hex)
287A
0
7FFF
7214
65AC
5A9D
50C3
-5
-6
-7
-8
-9
-1
-2
-3
-4
4026
-11
2413
392C
-12
2026
32F5
-13
1CA7
2D6A
-14
198A
SLEEP
Opcode:
Turn to Sleep Mode
SLEEP
03
0
0
0
0
0
0
1
1
Synopsis
SLEEP is used to force the ST75C520 to turn to low power mode.
Non parametric command.
Parameter
Notes :
When receiving this command the ST75C520 will stop processing and so cannot have theregular handshake protocol.
It does not increment the COMACK, neither generate an Interrupt.
STOP
Opcode:
FAX Stop Transmitter
STOP
25
0
0
1
0
0
1
0
1
Synopsis
STOP is used, in FAX Modes, to force the ST75C520 to turn off the transmitter in
accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.
Parameter
Non parametric command.
Notes :
When receiving this command the ST75C520 will stop sending regular Data. In parallel mode this command must be
preceded by a XMIT Stop command. In parallel mode the ST75C520 will wait until all the transmit buffers are sent before
starting the Stop sequence.
23/45
ST75C520
SYNC
Opcode:
FAX Synchronize the Receiver
SYNC
26
0
0
1
0
0
1
1
0
Synopsis
SYNC is used, in FAX Modes, to force the ST75C520 to Start/Stop the receiver in
accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.As soon
as the ST75C520 receives the SYNC Start command it sets its receiver to detect the FAX
synchronizationsignal.This command is the equivalentHSHK command for the receiver.
Parameters
Field
Byte
Pos.
Value
Definition
RX_SYNC
1
0
0*
1
Stop receiver
Start receiver synchronization
TDRC
Opcode:
Tone Detector Read Coefficient
TDRC
1A
0
0
0
1
1
0
1
0
Synopsis
TDRC Read one Coefficient of the selected Tone Detector Cell.
Parameters
Field
Byte
Pos.
3..0
7..0
Value
Definition
TD_CELL
1
2
0..F
Tone detector cell number
TD_C_ADDR
0..B
10
20
Other
Biquad coefficient
Energy coefficient
Static level
Reserved
The command answer is : Low Byte of Coefficient followed by High Byte of Coefficient.
TDRW
Opcode:
Tone Detector Read Wiring
TDRW
1B
0
0
0
1
1
0
1
1
Synopsis
TDRC Read Wiring of the selected Tone Detector Cell.
Parameters
Field
Byte
Pos.
3..0
0
Value
Definition
TD_CELL
1
2
0..F
Tone detector cell number
TD_W_ADDR
0
1
Biquad and energy input
Comparator inputs
Reserved
Other
The command answer is:
a) If TD_W_ADDR = 0 :
- First Byte is the Node Number of the Signal connected to Biquadratic Filter input.
- Second Byte is the Node Number of the Signal connected to the Energy estimator input.
b) if TD_W_ADDR = 1 :
- First Byte is the Node Number of the Signal connected to Comparator Negative input.
- SecondByte istheNode Number of theSignal connectedto the ComparatorPositive input.
24/45
ST75C520
TDWC
Opcode:
Tone Detector Write Coefficient
TDWC
1C
0
0
0
1
1
1
0
0
Synopsis
TDWC Write one Coefficient of the selected Tone Detector Cell.
Parameters
Field
Byte
Pos.
3..0
7..0
Value
Definition
TD_CELL
1
2
0..F
Tone detector cell number
TD_C_ADDR
0..B
10
Biquad coefficient
Energy coefficient
Static level
20
Other
Reserved
TD_COEFL
TD_COEFH
3
4
7..0
7..0
Low byte of coefficient
High byte of coefficient
TDWW
Opcode:
Tone Detector Write Wiring
TDWW
1D
0
0
0
1
1
1
0
1
Synopsis
TDRC Write Wiring of the selected Tone Detector Cell.
Parameters
Field
Byte
Pos.
3..0
0
Value
Definition
TD_CELL
1
2
0..F
Tone detector cell number
TD_W_ADDR
0
1
Biquad and energy input
Comparator inputs
Reserved
Other
If TD_W_ADDR = 0 (Select Biquad and Energy Inputs)
Parameters
Parameters
Field
Byte
Pos.
Value
0..3F
0..3F
Definition
Energy estimator signal input
Biquad filter signal input
TD_W_ERN
TD_W_BIQ
3
4
If TD_W_ADDR = 1 (Select Comparator Inputs)
Field
Byte
Pos.
Value
0..3F
0..3F
Definition
TD_W_CN
TD_W_CP
3
4
Negative comparator signal input
Positive comparator signal input
TDZ
Opcode:
Tone Detector Clear Cell
TDZ
1E
0
0
0
1
1
1
1
0
Synopsis
TDZ Clears all internal variables of one Tone detector cell including Filter local variables
and energy estimator. This command must be sent after changingcoefficients of a cell to
avoid instability.
Parameters
Field
Byte
Pos.
Value
Definition
TD_CELL
1
3..0
0..F
Tone detector cell number
25/45
ST75C520
TGEN
Opcode:
Enable/disable Tone Generators
TGEN
0D
0
0
0
0
1
1
0
1
Synopsis
TGEN causes the ST75C520 to enable or disable the four tone generators.
Parameters
Field
Byte
Pos.
Value
Definition
TONE_0_ENA
1
0
0*
1
Generator #0 disabled
Generator #0 enabled
TONE_1_ENA
TONE_2_ENA
TONE_3_ENA
1
1
1
1
2
3
0*
1
Generator #1 disabled
Generator #1 enabled
0*
1
Generator #2 disabled
Generator #2 enabled
0*
1
Generator #3 disabled
Generator #3 enabled
TONE
Opcode:
Predefined Tones
TONE
0C
0
0
0
0
1
1
0
0
Synopsis
TONE programs the tone generatorsfor the predefinedtones. Thetone generators#0 and
eventually #1 are reprogrammed with this command. Eventually the tone generator #0
and #1 are enabled. Using a value not in the following table will disable tone generator #0
and #1.
Parameters
Field
Byte
Pos.
Value
Definition
DTMF 0 (941 & 1336Hz)
TONE_SELECT
1
5..0
0
1
DTMF 1 (697 & 1209Hz)
DTMF 2 (697 & 1336Hz)
DTMF 3 (697 & 1477Hz)
DTMF 4 (770 & 1209Hz)
DTMF 5 (770 & 1336Hz)
DTMF 6 (770 & 1477Hz)
DTMF 7 (852 & 1209Hz)
DTMF 8 (852 & 1336Hz)
DTMF 9 (852 & 1477Hz)
DTMF A (697 & 1633Hz)
DTMF B (770 & 1633Hz)
DTMF C (852 & 1633Hz)
DTMF D (941 & 1633Hz)
DTMF * (941 & 1209Hz)
DTMF # (941 & 1477Hz)
Answer tone (2100Hz)
Tone (1650Hz)
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
Answer tone (2225Hz)
Tone (1300Hz)
XMIT
Opcode:
Start/stop Transmission
XMIT
01
0
0
0
0
0
0
0
1
Synopsis
XMIT start or stop the transmission ofthe Parallel Transmit Data. This command work only
if the Parallel Transmit Data mode has been selected with a SERIAL command.
Parameters
Field
Byte
Pos.
Value
Definition
TX_START
1
0
0*
1
Stop transmission
Start transmission
26/45
ST75C520
VII - STATUS DESCRIPTION
In the case of a memory reading command (CR,
TDRC, TDRW, IDT or MR) once the command
entered is executed, the report areais filled and the
acknowledge counter is incremented afterwards.
This insures that the controller will read the value
corresponding to its request.
This appendix is dedicated to the ST75C520 re-
porting features. in the following sections the com-
mand acknowledge process and the report and
status definitions are explained.
VII.1 - Command Acknowledge and Report
Furthermore, theST75C520 resets thevalueof the
COMSYS register once the command has been
read. The interruption IT6 is raised just after the
counter is incremented.
VII.1.1 - Command Acknowledge Process
(see Figure 1)
The ST75C520 features an acknowledge process
based on a counter COMACK. On power-on reset
(or INIT command), this counter’s value is set to 0.
Each time a command is successfully executed by
the ST75C520, the acknowledge counter CO-
MACK is incremented. This allows a precise moni-
toring of the command entered and avoids
command collision.
VII.1.2 - Reports Specification
The report section of the Dual Port RAM is dedi-
cated tomemory reading. Inresponseto a CR, MR,
TDRC, TDRW, IDT commands, the value read is
transferred to the report registers COMREP[0..1].
Figure 1 : Command Acknowledge Process
BEGIN
Yes
No
COMSYS = 0
Yes
No
COMMAND EXIST
CLEAR
ANSWER
EXECUTE
COMMAND
COPY ANSWER
INTO
SET SYSERR
ERR_IPRM
SET SYSERR
ERR_IOCD
COMREP
ASSERT
INTERRUPT
IT0
ASSERT
INTERRUPT
IT0
INCREMENT
COMACK
CLEAR
COMSYS
ASSERT
INTERRUPT
IT6
END
27/45
ST75C520
VII.1.3 - CR Command
Issuing a CR command causes the ST75C520 to dump a specific memory location in complex mode. This
instruction is particularlyuseful for equalizer state analysis or for software eye-pattern display. The report
area has this meaning :
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
COMREP[0]
IP7
IP6
IP5
IP4
IP3
IP2
IP1
IP0
COMREP[1]
RP0..RP7 is the MSB part of the 16-bit value of the real part and IP0..IP7 is the MSB part of the imaginary
part. The CR command insures that the real and imaginary part of the desired complex value are sampled
internally at the same time. The address given in the parameter field of CR is the address of the real part.
VII.1.4 - MR/TDRC/TDRW/IDT Commands
The report issued by the MR/TDRC/TDRW/IDT commands follow the same rules as for CR. The report
meaning is :
D7
D6
D5
D4
D3
D2
D1
D0
COMREP[0]
D15
D14
D13
D12
D11
D10
D9
D8
COMREP[1]
D0..D15 is the 16-bit value required by the MR/TDRC command.
In the case of IDT, D15..D12 contains the product identification (2 for ST75C520), D11..D8 contains the
hardware revision identification and D7..D0 contains the software revision identification.
VII.2 - Modem Status
VII.2.1 - Modem Status Description
The Status of ST75C520 is divided into 4 fields :
- The error status byte SYSERR that provides information about error. This status can trigger an IT0
interrupt,
- The general status byte STATUS[0] and STATUS[1] that contains all the modem signals. These status
bytes can trigger an IT4 interrupt,
- The quality status STAQUA, that contains the quality of the received transmission,
- The optional status bytes STAOP[0], STAOP[1] and STAOP[2], that contains additional information
regardingthe ST75C520 operatingmode. This defaultinformationcan be changedto monitor any internal
variables using the DOSR command.
All these informations are updated on a Baud basis :
Mode
Tone, DTMF, Voice
Baud Rate (2) (Hz)
CLK (Hz)
2400
9600
Bell 103 (full duplex)
V.21 (full duplex)
V.23 (full duplex)
V.27ter 2400bps
V.27ter 4800bps
V.29
2400
9600
2400
9600
9600
2400
1200
1600 (1)
2400
4800
2400
9600/7200/4800
14400/12000/9600/7200
14400/12000
300
V.17
2400
V.33
2400
V.21 channel 2
2400
Notes : 1. The tone detectors outputs are update 800 times by second.
2. This baud rate defines also, the maximum command rate. Each baud time the ST75C520 looks at the COMSYS location
(addesss $00) to see if a command have been sent by the host processor. If the content of this location is different from zero the
ST75C520 execute the command.
28/45
ST75C520
Starting at the adddress $08 the status area have the following format :
Bit
Add.
Name
7
6
5
4
3
2
1
0
$08 SYSERR ERR_RTK
-
-
ERR_IPRM ERR_IOCD
-
ERR_RX ERR_TX
$09 STATUS0 STA_109F STA_CPT10 STA_CPT1 STA_CPT0 STA_RING STA_106 STA_107 STA_109
$0A STATUS1 STA_DTMF STA_FLAG
-
STA_HR
STA_AT STA_CCITT
Quality
-
STA_H
$0B STAQUA
$0C STAOP0
$0D STAOP1
$0E STAOP2
-
Depend on operating mode (see below)
VII.2.2 - Error Status
The error status changes each time an error occurs. When the ST75C520 signals an error by setting one
of the SYSERR bit, it generatesan interrupt IT0. These bits can only be cleared by the host controler using
the CSE command.
The meaning of the different bits of the SYSERR byte is discribed below :
SYSERR
Field
Pos.
Meaning when set
ERR_TX
0
Transmit buffer underflow. Loss of synchronisation between the host and ST75C520
transmit data buffer managment.
ERR_RX
1
Receive buffer overflow. Loss of synchronisation between the host and ST75C520 receive
data buffer managment.
ERR_IOCD
ERR_IPRM
ERR_RTK
3
4
7
Incorrect CCI command
Incorrect parameter for the CCI command
Real time kernel error. ST75C520 not able to perform all its tasks within the baud period
(transmit or receive samples lost).
VII.2.3 - Modem General Status
The modem general status word is composed of two bytes STATUS[0] and STATUS[1]. Any bit change can
generate an IT4 interrupt. Using the DSIT command allows the selection of the corresponding bit that will
generate an interrupt each time they will change. The default pattern is $3F for STATUS[0] and $FF for
STATUS[1].
The different bits have the following meaning :
STATUS[0]
Field
Pos.
Meaning when set
STA_109
0
CCITT circuit 109 (carrier detect). Indicates that valid data are received. When 0 the output
data RxD are clamped to constant mark. Valid only in modem mode.
STA_107
STA_106
1
2
CCITT circuit 107 (data set ready). Valid only in modem mode.
CCITT circuit 106 (clear to send). Indicates that the training sequence has been completed
and that any data at TxD pin (serial mode) or in the transmit buffer (parallel mode) will be
transmitted. valid only in modem mode.
STA_RING
3
Ring detected. A ring signal (from 15Hz to 68Hz) is present at the RING pin. Valid only in
tones modes. The precise frequency can be read in the optional status byte STAOP2. The
detection time is 1 period of the ring signal. The detection lost time in 20ms after the last
transition on the ring signal.
STA_CPT0
STA_CPT1
STA_CPT10
STA_109F
4
5
6
7
Call progress tone detector #0. Low pass filter 650Hz. Valid only in tones modes.
Call progress tone detector #1. High pass filter 600Hz. Valid only in tones modes.
Signal in filter #0 is highter than #1. Valid only in tones modes.
Fast Carrier Detect. Valid only in modem mode.
29/45
ST75C520
STATUS[1]
Field
STA_H
Pos.
Meaning
0
2
Transmit synchronisation in progress. Valid only in modem mode.
STA_CCITT
CCITT 2100Hz versus 2225Hz answer tone detect. Valid if STA_AT is set. Valid only in
tones modes.
STA_AT
3
4
6
7
Answer tone (either 2100Hz or 2225Hz) detected. Valid only in tones modes.
Receive synchronisation in progress. Valid only in modem mode.
STA_HR
STA_FLAG
STA_DTMF
V.21 channel 2 flag detect. Valid only in FAX modem mode and tone mode.
DTMF digit detect. The digit itself is available in the optional status byte STAOP2. Valid
only in DTMF receive mode.
VII.2.4 - Quality Status
The quality byte STAQUA monitors an evaluation of the line quality. It is updated once per baud and its
value ranges from 127 (perfect quality) to 0 (terrible quality).This value is automaticalyadjusted according
to the current receiving mode. Refer to the following chart to convert the value into its Bit Error Rate
equivalence.
BER
1e-2
1e-3
1e-4
1e-5
1e-6
1e-7
1e-8
STAQUA
1e-9
0
31
63
95
127
VII.2.5 - Optional Status
According to the operating mode of the ST75C520 the optionalstatus is displaying different informations.
The optional status are automatically reprogrammed after each CONF command with the address of the
variablesto monitor according with theoperatingmode selected(CONF_OPER). After the CONF command
the user must overwrite this default programming by using the DOSR command.
VII.2.6 - Default Optional Status in Tone Mode
While in tone mode the format of the STAOP word is as follows :
Bit
Add.
Name
7
6
5
4
3
2
1
0
$0C
$0D
$0E
STAOP0
STAOP1
STAOP2
TDT7
TDT15
TDT6
TDT14
TDT5
TDT13
TDT4
TDT12
TDT3
TDT2
TDT10
TDT1
TDT9
TDT0
TDT8
TDT11
(1)
RING_PERIOD
Notes : 1. RING_PERIOD is valid when the bit 3 of the STATUS[0] (STA_RING) goes high. This value is updated at each falling edge of
the RING signal. The RING_PERIOD value must be divided by 2400 to obtain the period in seconds.
2. TDTx is the output of the tone detector x.
30/45
ST75C520
VII.2.7 - Default Optional Status in DTMF Receiver Mode
While in DTMF receiver mode the format of the STAOP word is as follows :
Bit
Add.
Name
7
6
5
4
3
2
1
0
(1)
(1)
$0C
$0D
$0E
STAOP0
STAOP1
STAOP2
TDT7 (1)
TDT6
TDT5 (1)
TDT4
TDT3
TDT2
TDT1
TDT0
(1)
TDT15 (1) TDT14 (1) TDT13 (1) TDT12 (1) TDT11 (1) TDT10 (1) TDT9 (1)
DTMF_DIGIT (2)
TDT8
Notes : 1. These cells are used by the DTMF detector.
2. DTMF_DIGIT is valid when the bit 7 of STATUS[1] (STA_DTMF) goes high. This value remains unchanged until a new DTMF
digit is detected.
VII.2.8 - Default Optional Status in Modem Mode
While in modem mode the format of the STAOP word is as follows :
Bit
Add.
Name
7
6
5
4
3
2
1
0
$0C
$0D
$0E
STAOP0
STAOP1
STAOP2
x
x
x
SPEED (2)
SPVAL (1)
Not used
SCR1s PRs
PNSUCs PRDETs PNDETs
PNs
P2s
P1s
Notes : 1. SPVALis active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. Went SPVALis set, it
indicates that the SPEED bits contain the data speed information.
2. SPEED is valid in V.33 receiver only. It can have 2 values, after the SCR1s signal goes high : 1000 for 14400bps and 0111 for
12000bps.
3. The STAOP2 bit reflects the progression of the synchronization. The STAOP2 bits have the following meaning :
Name
P1s
Position
Description
Unmodulated carrier sequence. Optional, used for echo protection.
Continuous 180° phase reversal sequence
Equalizer trainning sequence
Tx
X
Rx
0
1
2
3
4
5
6
7
P2s
X
X
X
PNs
X
PRs
V.33 and V.17 rate sequence
X
SCR1s
PNDETs
PRDETs
PNSUCs
Continuous scrambled 1 sequence
X
X
X
X
X
Turned on after PN sequence detection
Turned on after PR sequence detection (V.33 and V.17 only)
Turned on after succesfull training of the receive equalizer. When on at
the end of the synchronization, the transmition BER is statisticaly
bellow 10ppm.
31/45
ST75C520
With the following timing :
P1
T1
P2
T 3
PN
T4
R
SCR1
T6
Data
T2
T 5
Transmit
STA_H
P1s
P2s
PNs
PRs
(6)
SCR1s
T7
T7
T 8
T 8
T 8
T 8
Receive
(7)
STA_HR
STA_109F
P2s
PNDETs
PNs
(1)
PRDETs
(2)
PNSUCs
SCR1s
STA_109
RxData
Mode
V.17
T1 (4)
192
192
192
192
192
192
192
192
T1p (5)
30
T2
22
22
22
22
22
22
22
22
T3
107
107
53
41
31
9
T4
T5
T6
T7
T8
7
Unit
ms
ms
ms
ms
ms
ms
ms
ms
1240
16
27
0
20
20
20
8
5
5
5
5
5
5
6
6
V.17 short
V.29
30
7
30
160
26
0
7
V.29 short
V.27 4800
V.27 4800 short
V.27 2400
V.27 2400 short
30
0
7
30
670
36
0
5
7
30
0
5
7
30
42
12
895
48
0
7
7
30
0
7
7
32/45
ST75C520
Data
SCR1
T10
T11 min
Transmit
STA_H
P1s
P2s
PNs
PRs
(6)
SCR1s
T12
Receive
(3)
T13
STA_HR
STA_109F
(3)
PNDETs
PNs
(3)
(3)
PRDETs
PNSUCs
STA_109
RxData
Mode
T10
13
13
13
13
20
20
27
27
T11
20
20
20
20
30
30
40
40
T12
8
T13
Unit
ms
ms
ms
ms
ms
ms
ms
ms
V.17
25
25
25
25
25
25
25
25
V.17 short
V.29
8
8
V.29 short
8
V.27 4800
8
V.27 4800 short
V.27 2400
8
8
V.27 2400 short
8
Notes : 1. In the case of V.29 or V.27, PRs and PRDETs bits are not active.
2. PNSUCs indicates the quality of the Rx signal that will give a ber of approximation of 1e-5.
3. After sending the command SYNC0, all bits are reset.
4. When using long echo protection tone, otherwise 0.
5. When using short echo protection tone, otherwise 0.
6. STA-106 is set at the end of T6 and reset at the beginning of T10.
7. After sending the command SYNC1, this bit is set.
33/45
ST75C520
VIII - TONE DETECTORS
VIII.1 - Overview
Each BiquadraticFilter, Power Estimator andStatic
Level can be programmed using a complete set of
Commands(TDRC, TDRW, TDWC, TDWW, TDZ).
The wiring between the different Cells can be de-
fined by the user, using the associatedCommand
allowing a wide range of applications.
The general purpose TS75C520 tone detectors
block is a powerful module that covers a lot of
applications :
The 16 Comparator Outputs give, on a baud basis,
the information into two 8 bits words TONEDET0
(for cells number 0 to 7) and TONEDET1 (for cells
number 8 to F). These TONEDET variables can be
accessed using a MR command or, more easily,
monitored on a baud basis using the DOSR com-
mand.
- call progress tone detection, fully programmable
for all countries,
- DTMF detection,
- FAX, voice, data automatic detection,
- callwaiting detection,while invoiceordata mode.
VIII.2 - Description
VIII.2.1 - Biquadratic Filters
The tonedetectorblock is a set of 16identicalCells.
Each cell is composed of a Double Biquadratic
Filter, a Power estimator section, a Static level and
a Level comparator.
Each Biquadratic Filter is a double regular section
that can performany Transfer function with 4 Poles
and 4 Zeros. This routine is run on a sample basis.
Figure 2 : BiquadraticIIR Filter
-1
IN
C0
C5
C6
CB
OUT
Z
2
2
-1
-1
Z
Z
Z
Z
C1
C2
C3
C7
C8
C9
-1
-1
C4
CA
The corresponding transfer function is :
C5 + 2 C3 z±1 + 2 C4 z±2
CB+ 2 C9 z±1 + 2 CA z±2
1 ± 2 C7 z±1 ± 2 C8 z±2
Out
Input
±1
= C0
C6
z
±2
1 ± 2 C1
z
±1 ± 2 C2 z
Note : All coefficients are coded on 16 bits 2’s complement in the range +1, -1 (Q15). To avoid the possibility of overflow the user must check
that the internal node must not be higher that 0.5 (in Q15 representation).
34/45
ST75C520
VIII.2.2 - Power Estimation
corresponding bit into the TONEDET[0..1] word; if
not it clear this bit.
The Power estimation Cell is needed to measure
the amplitude of the different tones. It is run on a
sample basis.
VIII.2.5 - Wiring
The user must specify the connection (wiring) be-
tween theinput/outputof theFilter, the input/output
of the Power estimator, the output of the static
levels and the two inputs of the Comparators.
Figure 3 : Power Estimator
OUT
IN
+
-1
ABS(.)
P1
Z
The output signals have an absolute address:
Node Address
Signal
-1
Z
Address
Description
Name
Ground
RxSig
00
01
Signal always equal to 0000
The corresponding transfer function is :
Receive signal from the
Analog front end
P1
Out = |Input| z±1
RxSig2
RxSig4
02
03
Receive signal multiplied by 2
Receive signal multiplied by 4
1 ± (1 ± P1) z±1
04..0F Reserved
VIII.2.3 - Static Level
Filter[0..F]
10..1F Biquadratic Filter Outputs
A single Threshold level is associated with each
Cell. It can be useto comparethe outputof aPower
Estimation with an Absolute Value.
Power[0..F] 20..2F Power Estimator Outputs
Level[0..F] 30..3F Static Levels
The user will specify the inputs of the filters, Power
and Comparator. At leastone inputmust come from
the RxSig (node 01, 02 or 03). It is mandatory to
connect all unusedcell inputs to the Ground signal
(node 00).
VIII.2.4 - Comparator
The Comparator computes, on a baud basis, the
difference of the signal on its Positive and Negative
Inputs. If the result is Higher that zero it sets the
35/45
ST75C520
Figure 4 : Tone Detector Wiring Address (first half)
BIQUADRATIC
FILTER
#0
@10
@20
@30
POWER
#0
COMP.
#0
LEVEL #0
BIQUADRATIC @11
@21
@31
POWER
#1
FILTER
#1
COMP.
#1
LEVEL #1
BIQUADRATIC @12
@22
@32
POWER
#2
FILTER
#2
COMP.
#2
LEVEL #2
@00
D0
D1
D2
D3
D4
BIQUADRATIC
FILTER
#3
@13
@14
@15
@16
@17
@23
@33
GROUND
POWER
#3
COMP.
#3
LEVEL #3
@01
@02
@03
RX SIGNAL
BIQUADRATIC
@24
@34
POWER
#4
FILTER
#4
COMP.
#4
D5
D6
D7
2
2
LEVEL #4
BIQUADRATIC
@25
@35
POWER
#5
TONEDET0
FILTER
#5
COMP.
#5
LEVEL #5
BIQUADRATIC
@26
@36
POWER
#6
FILTER
#6
COMP.
#6
LEVEL #6
BIQUADRATIC
@27
@37
POWER
#7
FILTER
#7
COMP.
#7
LEVEL #7
36/45
ST75C520
Figure 5 : Tone Detector Wiring Address (second half)
BIQUADRATIC @18
@28
@38
POWER
FILTER
#8
#8
COMP.
#8
LEVEL #8
BIQUADRATIC @19
POWER
@29
@39
FILTER
#9
COMP.
#9
#9
LEVEL#9
BIQUADRATIC @1A
@2A
@3A
POWER
FILTER
#A
#A
COMP.
#A
LEVEL#A
D0
D1
D2
D3
D4
D5
D6
D7
BIQU ADRATIC
FILTER
@1B
@1C
@1D
@1E
@1F
@2B
@3B
POWER
#B
#B
COMP.
#B
LEVEL #B
BIQUADRATIC
FILTER
@2C
@3C
POWER
#C
#C
COMP.
#C
LEVEL #C
BIQUADRATIC
FILTER
@2D
@3D
POWER
#D
TONEDET1
#D
COMP.
#D
LEVEL #D
BIQUADRATIC
FILTER
@2E
@3E
POWER
#E
#E
COMP.
#E
LEVEL#E
BIQUADRATIC
FILTER
@2F
@3F
POWER
#F
#F
COMP.
#F
LEVEL#F
37/45
ST75C520
VIII.3 - Example
Hereunder is an example of programming a single
Tone detection (using Cell #3) and a complex dif-
ferential tone detection (using Cell #4 and #5).
Bit 3 of the TONEDET variable will be triggered
eachtime the energy of that filtered signal is higher
than Static Level number 3.
Bit 4 of the TONEDET variable will be on each time
a receive signal has an energy higher than the
Static Level number 4. Bit 5 will be on only when
the Filtered (Filter section 4 and 5) received signal
higher than the energy of the wide-band signal
number 4 ; this prevents triggering on noise.
Figure 6 : Wiring Example
@00
BIQUADRATIC @13
@23
@33
POWER
#3
GROUND
FILTER
#3
COMP.
#3
LEVEL #3
@01
RX SIGNAL
@14
@24
@34
BIQUADRATIC
FILTER
#4
POWER
#4
D3
D4
@02
@03
COMP.
#4
2
2
LEVEL #4
D5
BIQUADRATIC @15
@25
@35
TONEDET0
POWER
#5
FILTER
#5
COMP.
#5
LEVEL #5
Program Cell #3 :
TDWW
03
00
13
01
Connect Received signal to Filter and Filter to Energy.
TDWW 03 01
Connect Level to Comparator Neg Input and Energy to Pos Input.
33
23
Program Cell #4 and #5 :
TDWW
Connect Received Signal to Filter and Energy.
TDWW 04 01
04
00
01
34
01
24
14
25
Connect Level to Comparator Neg Input and Energy to Pos Input.
TDWW
Connect Filter#4 Output to Filter and Filter to Energy.
TDWW 05 01
05
00
15
24
Connect Wide-band Energy to Neg Input and Energy to Pos Input.
IX - BUFFER OPERATIONS
IX.1 - Introduction
Thisappendixis dedicatedto bufferoperation, eitherthe data buffersused in data exchangesor inparticular
Modes (like Voice).
The first part is oriented towards a functionaldescription of the buffer operation, while the second section
is more oriented towards the management of the buffers.
38/45
ST75C520
IX.2 - Receive Operations Overview
fill them. This further means that the host must not
perform any bufferoperation on the data part while
the status remains 0.
Figure 7 describes the receive data flow.
The ST75C520 can handle the following types of
format for the data :
- parallel synchronous mode : 8-bit words are syn-
chronously available in the receive buffers. The
buffer status holds the number of valid bytes
received,
- parallel HDLC framing mode : 8-bit data is avail-
able in the receive buffers. Framing information
(like flags, CRC, additional ”0”) is interpreted by
the ST75C520 and reported when necessary in
the receive buffer status (CRC error, aborted
frame, framing error, etc). This feature greatly
eases the implementation of protocols as well as
FAX data management.
IX.3 - Transmit Operations Overview
Figure 8 describes the transmit data flow. The
following modes are available :
- parallel synchronous mode : 8-bit words are syn-
chronously read from the transmit buffers. The
transmit status buffer holds the number of valid
bytes to be transmitted (up to 8 per buffer),
- parallel HDLC framing mode : 8-bit data is re-
ceived from the transmit buffers. Framing infor-
mation (frame open, frame close, frame abort,
number of byte per buffer) is carried by the trans-
mit buffer status and processed by the
ST75C520. CRC, padding and other operations
are automaticallyhandled by the ST75C520.
Each time the receive deframerhas filled up a new
buffer, itsets the correspondingflag with the proper
status then generates the IT3 interrupt. The avail-
ability of the buffers is tested just before starting to
Each time the transmit framerhas emptied a buffer,
the IT2 interrupt is raised.
Figure 7 : Rx Buffer Schematics
ER ROR R X
(SYSERR )
DATA
FORMAT
R EC EIVER
IT3
S TA TU S
RX BUFFER
STATUS
RECEIVE
DEFRAMER
R EC EIVER
RX DATA
BUFFER
D ATA
SERIAL
R X D
OUT
RX C LK
Figure 8 : Tx Buffer Schematics
ERROR TX
(SYSERR)
DATA
FO RMAT
TRANSMITTER
IT2
STATUS
TX BUFFER
STA TUS
SERIAL
TRANSMITTER
FRAMER
TRANSMITTER
MU X
DATA
TX DATA
BUFFER
SERIAL
T X D
I N
T XC LK
39/45
ST75C520
IX.4 - Buffer Status and Format Description
The following section describes the meaning and
use of the buffer status words.
DTRBS1 (see the Host Interface Summary sec-
tion in the main document). These flags are set by
the ST75C520 and must be reset by the host. The
data buffer exchanges are synchronized through
these status words, an improper resetting will trig-
ger the error Err_Rx in the error status SYSERR.A
value of 0 for DTRBS0 or DTRBS1 means that the
corresponding buffers are empty : this value must
be written by the host.
IX.4.1 - Transmit Buffer
The transmit buffer status words are DTTBS0 and
DTTBS1 (see the Host Interface Summary sec-
tion in the main document) and are more likely to
be seen ascontrol words. These words must be set
by the host and are reset by the ST75C520. The
data buffer exchanges are synchronized through
these status words, (see Buffer Status and format
description)an impropersettingwill triggerthe error
Err_Tx in the error status SYSERR. A value of 0 for
DTTBS0 orDTTBS1 meansthatthe corresponding
buffers are empty : this value is written by the
ST75C520. The unused bits of DTTBSx must be
set to 0 by the host.
In FSK or V.21 Channel 2 Mode, when working in
the parallel data mode, the receiver extract each
bit using the nominal baud rate
(1200Hz/300Hz/75Hz).
IX.5.1 - Synchronous Mode
Field
Pos.
Val.
Description
BUFF_LENG
3..0
1..8
Number of valid
bytes in the buffer
In FSK Mode, when working in the parallel data
mode, the transmitter expands each bit to the
nominal baud time (1200Hz/300Hz/75Hz).
IX.5.2 - HDLC Framing Mode
Field
Pos.
Val.
Description
IX.4.2 - Synchronous Mode
BUFF_LENG
3..0
1..8
Number of valid
bytes in the buffer
Field
Pos.
Val.
Description
BUFF_ERRS
5..4
00
01
10
No error
BUFF_LENG
3..0
1..8
Number of valid
bytes in the buffer
CRC error
Non byte-aligned
frame
11
Aborted frame
IX.4.3 - HDLC Framing Mode
BUFF_SFRM
BUFF_EFRM
6
7
0
1
Data stream
Field
Pos.
Val.
Description
Start of frame
BUFF_LENG
3..0
1..8
Number of valid
bytes in the buffer
0
1
Data stream
End of frame
BUFF_SFRM
BUFF_EFRM
BUFF_FRAB
4
5
6
0
1
Data stream
Start of frame
IX.6 - Data Buffer Management
0
1
Data stream
End of frame
Figure 9 shows the general flow chart for transmit
data buffer management. In the transmit path, the
data buffer exchanges should always begin with
the filling of buffer 0, then with the update of the
buffer 0 status word. The initiation of the data
exchanges is initiated then with the XMIT com-
mand.
0
1
Normal process
Abort frame (no
data in buffer)
IX.5 Receive Buffer
The receive buffer status words are DTRBS0 and
40/45
ST75C520
Figure 9 : Buffer Operations Synchronization
Tx MAIN PROGRAM
INTERRUPT ROUTINE
BEGIN
INTERRUPT
N
NEED TO
TRANSMIT
N
106 ON
Y
Y
FILL BUFFER
#IBUFF
FILL BUFFER #0
UPDATE STATUS
BUFFER #IBUFF
UPDATESTATUS
BUFFER #0
CLEAR IT2
IBUFF = 1
XMIT ON
TOGGLE IBUFF
ENABLE IT2
RETURN
N
Y
106 OFF or
ERROR TX
DISABLE IT2
XMIT OFF
CSE ERRTX
(only if ERR)
Rx MAIN PROGRAM
INTERRUPT ROUTINE
BEGIN
INTERRUPT
READ BUFFER
#IBUFF
N
109 ON
Y
WRITE $00
IN DATA STATUS
BUFFER #IBUFF
WRITE $00 IN
DATA STATUS
BUFFER #0 AND #1
CLEAR IT3
TOGGLE IBUFF
RETURN
IBUFF = 0
ENABLE IT3
Y
N
109 ON
DISABLE IT3
CSE ERRRX
(only if ERR)
41/45
ST75C520
X - DEFAULT CALL PROGRESS TONE DETEC-
TORS
XI - DEFAULT ANSWER TONE DETECTORS
Figure 10 : Call Progress Tone Detector Band 1
Figure 12 : 2100Hz Answer Tone Detector
Figure 11 : Call Progress Tone Detector Band 2
Figure 13 : 2225Hz Answer Tone Detector
XII - ELECTRICAL SCHEMATICS
Oscillator
When using a third harmoniccrystal oscillator in series resonancemode (RS < 40Ω, C0 = 6pF, Pe = 0.1mW),
we recommend the following schematic :
EX TA L
5 6
X TAL
55
29.4 912MHz
33pF
1µH
5pF
(opti onal)
10n F
42/45
ST75C520
XII - ELECTRICAL SCHEMATICS (continued)
Figure 14
22kΩ
220pF
Ω
40k
8
4
1.2kΩ
15kΩ
13.2kΩ
22kΩ
3
2
4
8
1
RXA2
TXA1
2
3
1
20kΩ
TL072
320Ω
2.2nF
TL072
680pF
82kΩ
20k
Ω
8
4
TL072
220Ω
15k
Ω
2.2nF
TL072
5
6
4
8
13.2kΩ
22kΩ
7
6
5
TXA2
7
RXA1
1.2kΩ
40kΩ
TIP
22k
Ω
220pF
AVDD
RING
TRANSFORMER
1kΩ
V
REFP
10µF
10µF
1k
Ω
100nF
100nF
VCM
1kΩ
1kΩ
10µF
V
REFN
100nF
AGND
AGND
AGND
XIII - PCB DESIGN GUIDELINES
Performances of the FAX modem depends on the
ST75C520 intrinsic performances and on the
proper PC board layout. All aspects of the proper
engineering practices, for PC board design, are
beyond the scope of this paragraph.
under componentson both sides of the band and
connect to avoid small islands,
- both AGNDR and AGNDT must be connected
with very low impedance to a single point, (see
Chapter I.7, Power Supply),
- thetwo2.2nFcapacitorsconnectedtotheRXA1and
RXA2 Pins must be as close as possible to them,
- thetwo 100nFcapacitorsconnectedtotheVREFPand
We recommend the following points :
- in a 4-layer PC board :
Separated digital ground and analog ground,
connected together at one point, as close as
possible to the ST75C520,
V
REFN pins must be as close as possible to them,
- analog and digital supplies must be connected
together,at a single point, as close as possible to
the chip (see Chapter I.7, Power Supply).
- in a 2-layer PC board :
Provide a ground grid in all space around and
43/45
ST75C520
TYPICAL APPLICATION
(third harmonic series
resonance oscillator)
L1 1µH
29.4912MHz
Y1
C1
5pF
C3
10nF
C2
33pF
+5VA
C5
43
49
56
55
SCCLK
EOS
EXTAL
XTAL
* C4
100nF
µ
F
10
50
45
51
42
44
53
2
+5V
BOS
HALT/NOP
TXA1
TXA1
TXA2
RDYS
SCOUT
SCIN
MCI
1
+5V
R8
+5V
TXA2
DAA
60
61
RXA1
RXA1
RXA2
R1 1.2kΩ
54
48
47
CLKOUT
MC0
470Ω
R7
62
MC1
AVDD
10kΩ
REFP
*C6
V
46
26
27
58
63
57
MC2
2.2µF
D0
SD0
VCM
*C7
D1
D2
D3
D4
D5
D6
D7
SD1
V
REFN
2.2µF
RXA2
28
29
30
31
32
33
59
SD2
AGNDR
R2 1.2kΩ
SD3
64
SD4
AGNDT
SD5
7
6
SD6
TP1
TP2
EYEX
EYEY
R3
1.2kΩ
SD7
DTACKl
INTRl
37
38
36
4
5
SDTACK
SINTR
SCS
EYESYNC
EYECLK
*
*
C10
R4
1.2kΩ
CSl
1µF
C9
100nF
35
34
16
14
SR/W(WRl)
SDSl (RDl)
SR/W
SDS
TXD
CLK
RXD
CD
VCM
R5
1.2kΩ
C11
1µF
C8
100nF
39
17
18
19
15
13
11
12
10
INT/MOT
SA0
A0
A1
R6
1.2k
SA1
RTS
CTS
RING
Ω
A2
SA2
AGND
20
21
22
A3
SA3
(connect close
to the ST75C52)
A4
SA4
TxD
RxD
CLK
3
A5
SA5
EBS
23
52
A6
SA6
8
RESETl
RESET
DV DD
DV DD
DV DD
DGND
DGND
DGND
+5V
CDl
RTSl
CTSl
RINGl
V.24/RS232
9
24
40
+5V
INTEL mode
25
41
MOTOROLA mode
*C12 *C13 *C14
10nF 10nF 10nF
10µF
(select one
of the two)
Notes : All capacitor with a ”*” must be implanted close to the ST75C520 pin.
All signal name ending with a ”1” are active low.
R3, R4, R5, R6 are needed if the hybrid will sink a current on VCM
.
44/45
ST75C520
PACKAGE MECHANICAL DATA
64 PINS - PLASTIC QUAD FLAT PACK
A
A2
e
A1
16
17
1
64
32
33
49
48
C
E2
E1
E
K
Millimeters
Typ.
Inches
Typ.
Dimensions
Min.
Max.
Min.
Max.
A
A1
A2
B
3.40
0.134
0.25
2.55
0.01
0.10
2.80
3.05
0.45
0.11
0.12
0.018
0.009
0.687
0.555
0.30
0.012
0.005
0.667
0.547
C
0.13
0.23
D
16.95
13.90
17.20
14.00
12.00
0.80
17.45
14.10
0.677
0.551
0.472
0.031
0.677
0.551
0.472
0.063
D1
D2
e
E
16.95
13.90
17.20
14.00
12.00
1.60
17.45
14.10
0.667
0.547
0.687
0.555
E1
E2
F
K
0o (min.), 7o (max.)
0.95 0.025
L
0.65
0.80
0.031
0.037
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of suchinformation nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwiseunder anypatent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
1995 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.
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