ST7FLITE29 [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI; 8位MCU单电压闪存存储器，数据EEPROM ， ADC ，定时器， SPI
| 型号： | ST7FLITE29 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| 文件： | 总131页 (文件大小：1673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7LITE2
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, TIMERS, SPI
■ Memories
– 8 Kbytes single voltage Flash Program mem-
ory with read-out protection, In-Circuit Pro-
gramming and In-Application programming
(ICP and IAP). 10K write/erase cycles guar-
anteed, data retention: 20 years at 55°C.
– 384 bytes RAM
SO20
DIP20
– 256 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
300”
outputs, input capture and output compare
functions
■ Clock, Reset and Supply Management
■ 1 Communication Interface
– SPI synchronous serial interface
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
■ A/D Converter
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal 1% RC oscillator,
crystal/ceramic resonator or external clock
– Internal 32-MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– 7 input channels
– Fixed gain Op-amp
– 13-bit resolution for 0 to 430 mV (@ 5V V
)
DD
– 10-bit resolution for 430 mV to 5V (@ 5V V
■ Instruction Set
)
DD
– Five Power Saving Modes: Halt, Active-Halt,
Wait and Slow, Auto Wake Up From Halt
– 8-bit data manipulation
■ I/O Ports
– 63 basic instructions
– Up to 15 multifunctional bidirectional I/O lines
– 7 high sink outputs
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
■ Development Tools
■ 4 Timers
– Configurable Watchdog Timer
– Full hardware/software development package
– DM (Debug Module)
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– One 12-bit Auto-reload Timer with 4 PWM
Device Summary
Features
ST7LITE20
ST7LITE25
ST7LITE29
Program memory - bytes
RAM (stack) - bytes
8K
384 (128)
-
Data EEPROM - bytes
-
256
Lite Timer with Watchdog,
Lite Timer with Watchdog,
Autoreload Timer, SPI,
10-bit ADC with Op-Amp
Autoreload Timer with 32-MHz input clock,
SPI, 10-bit ADC with Op-Amp
2.4V to 5.5V
Peripherals
Operating Supply
CPU Frequency
Up to 8Mhz
(w/ ext OSC up to 16MHz)
Up to 8Mhz (w/ ext OSC up to 16MHz
and int 1MHz RC 1% PLLx8/4MHz)
Operating Temperature
-40°C to +85°C
Packages
SO20 300”, DIP20
Rev. 2.0
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1
August 2003
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 34
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Table of Contents
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 114
13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 123
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 129
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ST7LITE2
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please also pay special attention to the Section “IMPORTANT NOTES” on page 129.
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ST7LITE2
1 INTRODUCTION
The ST7LITE2 is a member of the ST7 microcon-
troller family. All ST7 devices are based on a com-
mon industry-standard 8-bit core, featuring an en-
hanced instruction set.
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The ST7LITE2 features FLASH memory with
byte-by-byte In-Circuit Programming (ICP) and In-
Application Programming (IAP) capability.
For easy reference, all parametric data are located
in section 13 on page 91.
Under software control, the ST7LITE2 device can
be placed in WAIT, SLOW, or HALT mode, reduc-
ing power consumption when the application is in
idle or standby state.
The devices feature an on-chip Debug Module
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
Figure 1. General Block Diagram
PLL
8MHz -> 32MHz
Int.
1% RC
1MHz
12-Bit
PLL x 8
Auto-Reload
TIMER 2
or PLL X4
CLKIN
8-Bit
LITE TIMER 2
/ 2
OSC1
OSC2
Ext.
OSC
Internal
CLOCK
1MHz
PA7:0
(8 bits)
PB6:0
(7 bits)
to
PORT A
16MHz
PORT B
LVD
ADC
V
POWER
SUPPLY
DD
+ OpAmp
V
SS
SPI
RESET
CONTROL
8-BIT CORE
ALU
Debug Module
PROGRAM
MEMORY
(8K Bytes)
DATA EEPROM
(256 Bytes)
RAM
(384 Bytes)
WATCHDOG
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1
ST7LITE2
2 PIN DESCRIPTION
Figure 2. 20-Pin SO Package Pinout
V
V
OSC1/CLKIN
OSC2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SS
DD
RESET
PA0 (HS)/LTIC
SS/AIN0/PB0
PA1 (HS)/ATIC
ei0
ei1
ei3
ei2
PA2 (HS)/ATPWM0
PA3 (HS)/ATPWM1
PA4 (HS)/ATPWM2
PA5 (HS)/ATPWM3/ICCDATA
PA6/MCO/ICCCLK/BREAK
PA7(HS)
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
AIN5/PB5
AIN6/PB6
(HS) 20mA high sink capability
eix associated external interrupt vector
Figure 3. 20-Pin DIP Package Pinout
ei3
MISO/AIN2/PB2
SCK/AIN1/PB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ei3
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
SS/AIN0/PB0
RESET
ei2
AIN5/PB5
V
DD
V
AIN6/PB6
PA7(HS)
SS
OSC1/CLKIN
OSC2
MCO/ICCCLK/BREAK/PA6
ATPWM3/ICCDATA/PA5(HS)
ATPWM2/PA4(HS)
ei1
ei0
PA0(HS)/LTIC
PA1(HS)/ATIC
PA2(HS)/ATPWM0
ei0
ATPWM1/PA3(HS)
(HS) 20mA high sink capability
eix associated external interrupt vector
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1
ST7LITE2
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt, ana = analog
OD = open drain, PP = push-pull
– Output:
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 1. Device Pin Description
Pin No.
Level
Port / Control
Main
Function
(after reset)
Input
Output
Pin Name
Alternate Function
1
2
16
17
V
V
S
S
Ground
SS
Main power supply
DD
Top priority non maskable interrupt (active
low)
3
4
5
6
7
8
18 RESET
I/O C
X
X
X
X
X
X
X
T
ADC Analog Input 0 or SPI
Port B0
19 PB0/AIN0/SS
20 PB1/AIN1/SCK
I/O
C
C
C
C
C
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T
T
T
T
T
Slave Select (active low)
ei3
ADC Analog Input 1 or SPI Se-
rial Clock
I/O
Port B1
ADC Analog Input 2 or SPI
Port B2
1
2
3
PB2/AIN2/MISO I/O
Master In/ Slave Out Data
ADC Analog Input 3 or SPI
Port B3
PB3/AIN3/MOSI I/O
PB4/AIN4/CLKIN I/O
Master Out / Slave In Data
ADC Analog Input 4 or Exter-
nal clock input
ei2
ei1
Port B4
9
4
5
6
PB5/AIN5
PB6/AIN6
PA7
I/O
I/O
C
C
X
X
X
X
X
X
X
X
X
X
X
Port B5
Port B6
Port A7
ADC Analog Input 5
ADC Analog Input 6
T
10
11
T
I/O C HS
T
Main Clock Output or In Circuit
Communication Clock or Ex-
ternal BREAK
Caution: During reset, this pin
must be held at high level to
avoid entering ICC mode un-
expectedly (this is guaranteed
by the internal pull-up if the ap-
plication leaves the pin float-
ing).
PA6 /MCO/
ICCCLK/BREAK
12
7
I/O
C
X
ei1
X
X
Port A6
T
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1
ST7LITE2
Pin No.
Level
Port / Control
Main
Function
(after reset)
Input
Output
Pin Name
Alternate Function
PA5 /ATPWM3/
ICCDATA
Auto-Reload Timer PWM3 or
In Circuit Communication Data
13
14
8
9
I/O C HS
X
X
X
Port A5
T
ei1
PA4/ATPWM2
I/O C HS
X
X
X
X
X
X
X
X
X
Port A4
Port A3
Port A2
Auto-Reload Timer PWM2
Auto-Reload Timer PWM1
Auto-Reload Timer PWM0
T
15 10 PA3/ATPWM1
16 11 PA2/ATPWM0
I/O C HS
T
I/O C HS
T
ei0
Auto-Reload Timer Input Cap-
ture
17 12 PA1/ATIC
I/O C HS
X
X
X
X
X
X
Port A1
Port A0
T
18 13 PA0/LTIC
19 14 OSC2
I/O C HS
Lite Timer Input Capture
T
O
I
Resonator oscillator inverter output
Resonator oscillator inverter input or Exter-
nal clock input
20 15 OSC1/CLKIN
8/131
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ST7LITE2
3 REGISTER & MEMORY MAP
As shown in Figure 4, the MCU is capable of ad-
dressing 64K bytes of memories and I/O registers.
dressing space so the reset and interrupt vectors
are located in Sector 0 (F000h-FFFFh).
The available memory locations consist of 128
bytes of register locations, 384 bytes of RAM, 256
bytes of data EEPROM and 8 Kbytes of user pro-
gram memory. The RAM space includes up to 128
bytes for the stack from 180h to 1FFh.
The size of Flash Sector 0 and other device op-
tions are configurable by Option byte (refer to sec-
tion 15.1 on page 123).
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.l
The highest address bytes contain the user reset
and interrupt vectors.
The Flash memory contains two sectors (see Fig-
ure 4) mapped in the upper part of the ST7 ad-
Figure 4. Memory Map
0080h
Short Addressing
RAM (zero page)
00FFh
0100h
0000h
HW Registers
(see Table 2)
16-bit Addressing
RAM
007Fh
0080h
017Fh
0180h
RAM
(384 Bytes)
01FFh
0200h
128 Bytes Stack
01FFh
Reserved
0FFFh
1000h
1000h
Data EEPROM
(256 Bytes)
RCCR0
10FFh
1100h
RCCR1
1001h
see section 7.1 on page 23
8K FLASH
Reserved
PROGRAM MEMORY
DFFFh
E000h
E000h
7 Kbytes
SECTOR 1
FBFFh
FC00h
Flash Memory
(8K)
1 Kbyte
SECTOR 0
FFFFh
FFDFh
FFE0h
FFDEh
Interrupt & Reset Vectors
(see Table 5)
RCCR0
RCCR1
FFDFh
FFFFh
see section 7.1 on page 23
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ST7LITE2
Table 2. Hardware Register Map
Address
Block
Register Label
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reset Status
Remarks
R/W
R/W
R/W
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
FFh
Port A
00h
40h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
FFh
R/W
R/W
R/W
Port B
00h
00h
2)
0006h
0007h
Reserved Area (2 bytes)
0008h
0009h
000Ah
000Bh
000Ch
LTCSR2
LTARR
LTCNTR
LTCSR1
LTICR
Lite Timer Control/Status Register 2
Lite Timer Auto-reload Register
Lite Timer Counter Register
Lite Timer Control/Status Register 1
Lite Timer Input Capture Register
0Fh
00h
00h
R/W
R/W
Read Only
R/W
LITE
TIMER 2
0X00 0000h
xxh
Read Only
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
0X00 0000h
00h
R/W
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
PWM1CSR
PWM2CSR
PWM3CSR
DCR0H
DCR0L
DCR1H
DCR1L
DCR2H
DCR2L
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
PWM Output Control Register
PWM 0 Control/Status Register
PWM 1 Control/Status Register
PWM 2 Control/Status Register
PWM 3 Control/Status Register
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
PWM 1 Duty Cycle Register High
PWM 1 Duty Cycle Register Low
PWM 2 Duty Cycle Register High
PWM 2 Duty Cycle Register Low
PWM 3 Duty Cycle Register High
PWM 3 Duty Cycle Register Low
Input Capture Register High
Input Capture Register Low
Transfer Control Register
AUTO-
RELOAD
TIMER 2
DCR3H
DCR3L
ATICRH
ATICRL
TRANCR
BREAKCR
00h
00h
01h
00h
Read Only
Read Only
R/W
Break Control Register
R/W
0023h to
002Dh
Reserved area (11 bytes)
002Eh
0002Fh
00030h
WDG
WDGCR
FCSR
Watchdog Control Register
7Fh
00h
00h
R/W
R/W
R/W
FLASH
Flash Control/Status Register
Data EEPROM Control/Status Register
EEPROM EECSR
0031h
0032h
0033h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0034h
0035h
0036h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Amplifier Control/Data Low Register
00h
xxh
0xh
R/W
Read Only
R/W
ADC
10/131
1
ST7LITE2
Address
Block
Register Label
Register Name
Reset Status
Remarks
0037h
0038h
ITC
EICR
External Interrupt Control Register
Main Clock Control/Status Register
00h
00h
R/W
R/W
MCC
MCCSR
0039h
003Ah
Clock and RCCR
RC oscillator Control Register
System Integrity Control/Status Register
FFh
0000 0XX0h
R/W
R/W
Reset
SICSR
003Bh
003Ch
Reserved area (1 byte)
ITC
EISR
External Interrupt Selection Register
0Ch
R/W
003Dh to
0048h
Reserved area (12 bytes)
0049h
004Ah
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
AWU
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
3)
DM
0051h to
007Fh
Reserved area (47 bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
3. For a description of the Debug Module registers, see ICC reference manual.
11/131
1
ST7LITE2
the device from the application board and
while the application is running.
4 FLASH PROGRAM MEMORY
4.3.1 In-Circuit Programming (ICP)
4.1 Introduction
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
– Download ICP Driver code in RAM from the
ICCDATA pin
4.2 Main Features
■ ICP (In-Circuit Programming)
– Execute ICP Driver code in RAM to program
the FLASH memory
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection against piracy
4.3.2 In Application Programming (IAP)
4.3 PROGRAMMING MODES
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM (if present) can be pro-
grammed or erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM (if present) can be programmed or
erased without removing the device from the
application board.
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
– In-Application Programming. In this mode,
sector 1 and data EEPROM (if present) can
be programmed or erased without removing
12/131
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ST7LITE2
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– OSC1: main clock input for external source
(not required on devices without OSC1/OSC2
pins)
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
– V : application board power supply (option-
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
4. Pin 9 has to be connected to the OSC1 pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte. ST7 devices with mul-
ti-oscillator capability need to have OSC2 ground-
ed in this case.
5. During reset, this pin must be held at high level
to avoid entering ICC mode unexpectedly (this is
guaranteed by the internal pull-up if the application
leaves the pin floating).
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
Figure 5. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
C
C
L2
See Notes 1 and 5
L1
APPLICATION
I/O
See Note 1
ST7
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ST7LITE2
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
Write/erase protection is enabled through the
FMP_W bit in the option byte.
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
4.6 Related Documentation
4.5.1 Read out Protection
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
Read out protection, when selected, makes it im-
possible to extract the memory content from the
microcontroller, thus preventing piracy. Both pro-
2
gram and data E memory are protected.
4.7 Register Description
In flash devices, this protection is removed by re-
programming the option. In this case, both pro-
gram and data E memory are automatically
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
2
erased and the device can be reprogrammed.
Read-out protection selection depends on the de-
vice type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
7
0
0
– In ROM devices it is enabled by mask option
specified in the Option List.
0
0
0
0
OPT
LAT
PGM
4.5.2 Flash Write/Erase Protection
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations.
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
2
ry. It does not apply to E data. Its purpose is to
provide advanced security to applications and pre-
vent any change being made to the memory con-
tent.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
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ST7LITE2
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection against piracy
Figure 6. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
15/131
1
ST7LITE2
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 7 describes these different memory
access modes.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
WRITE MODE
E2LAT=1
E2PGM=0
E2PGM=0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2LAT
CLEARED BY HARDWARE
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1
ST7LITE2
DATA EEPROM (Cont’d)
2
Figure 8. Data E PROM Write Operation
Row / Byte
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
Byte 1 Byte 2
PHASE 1
Byte 32
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem-
ory is not guaranteed.
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ST7LITE2
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
5.6 Data EEPROM Read-out Protection
Active-Halt mode
The read-out protection is enabled through an op-
tion bit (see section 15.1 on page 123).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out piracy (including a re-write pro-
tection). In Flash devices, when this protection is
removed by reprogramming the Option Byte, the
entire Program memeory and EEPROM is first au-
tomatically erased.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
18/131
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ST7LITE2
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
E2LAT
0
E2PGM
0
0030h
0
0
0
0
0
0
Reset Value
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ST7LITE2
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
6.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
6.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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1
ST7LITE2
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative.
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
21/131
1
ST7LITE2
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
Reset Value: 01FFh
15
8
1
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
0
7
1
0
0
0
0
0
0
SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Since the stack is 128 bytes deep, the 9 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Figure 11. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0180h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0180h
Stack Lower Address =
22/131
1
ST7LITE2
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components.
ST7LITE29
Address
ST7LITE25
Address
RCCR Conditions
=5V
V
DD
1000h
and FFDEh
Main features
RCCR0 T =25°C
FFDEh
FFDFh
A
f
=1MHz
■ Clock Management
RC
V
=3V
DD
– 1 MHz internal RC oscillator (enabled by op-
tion byte, available on ST7LITE25 and
ST7LITE29 devices only)
1001h
and FFDFh
RCCR1 T =25°C
A
f
=700KHz
RC
– 1 to 16 MHz or 32kHz External crystal/ceramic
resonator (selected by option byte)
Note:
– See “ELECTRICAL CHARACTERISTICS” on
page 91. for more information on the frequency
and accuracy of the RC oscillator.
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 8 or 4
(enabled by option byte)
– To improve clock stability, it is recommended to
place a decoupling capacitor between the V
– For clock ART counter only: PLL32 for multi-
plying the 8 MHz frequency by 4 (enabled by
option byte). The 8 MHz input frequency is
mandatory and can be obtained in the follow-
ing ways:
DD
and V pins.
SS
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these two bytes.
–1 MHz RC + PLLx8
–16 MHz external clock (internally divided
by 2)
– RCCR0 and RCCR1 calibration values will be
erased if the read-out protection bit is reset after
it has been set. See “Read out Protection” on
page 14.
–2 MHz. external clock (internally divided by
2) + PLLx8
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
–Crystal oscillator with 16 MHz output fre-
quency (internally divided by 2)
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
7.2 PHASE LOCKED LOOP
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The device contains an internal RC oscillator with
an accuracy of 1% for a given device, temperature
and voltage range (4.5V-5.5V). It must be calibrat-
ed to obtain the frequency required in the applica-
tion. This is done by software writing a calibration
value in the RCCR (RC Control Register).
– The x4 PLL is intended for operation with V in
the 2.4V to 3.3V range
DD
– The x8 PLL is intended for operation with V in
DD
the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte descrip-
tion.
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be load-
ed in the RCCR. Predefined calibration values are
If the PLL is disabled and the RC oscillator is ena-
bled, then f
1MHz.
OSC =
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
stored in EEPROM for 3 and 5V V supply volt-
DD
f
ages at 25°C, as shown in the following table.
OSC
23/131
1
ST7LITE2
PHASE LOCKED LOOP (Cont’d)
Figure 12. PLL Output Frequency Timing
Diagram
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
LOCKED bit set
Read / Write
Reset Value: 0000 0000 (00h)
4/8 x
input
freq.
7
0
0
t
STAB
MCO SMS
0
0
0
0
0
t
LOCK
Bits 7:2 = Reserved, must be kept cleared.
t
STARTUP
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
t
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
clock after a delay of t
.
STARTUP
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC ) is reached after
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
PLL
a stabilization time of t
(see Figure 12 and
STAB
13.3.4 Internal RC Oscillator and PLL)
clock f
0: Normal mode (f
1: Slow mode (f
or f
/32.
Refer to section 7.6.4 on page 33 for a description
of the LOCKED bit in the SICSR register.
OSC
OSC
f
CPU = OSC
f
/32)
CPU = OSC
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh)
7
0
CR0
CR70 CR60 CR50 CR40 CR30 CR20 CR10
Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
24/131
1
ST7LITE2
Figure 13. Clock Management Block Diagram
CR7 CR6 CR5 CR4 CR3 CR2 CR1
CR0
RCCR
PLL
12-BIT
AT TIMER 2
f
Tunable
1% RC Oscillator
CPU
8MHz -> 32MHz
OSC,PLLOFF,
RC OSC
OSCRANGE[2:0]
Option bits
PLLx4x8
CLKIN
CLKIN
CLKIN
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
f
OSC
/2
CLKIN/2
DIVIDER
CLKIN/2
OSC/2
CLKIN
/OSC1
OSC
1-16 MHZ
or 32kHz
OSC
/2
DIVIDER
OSC2
OSC,PLLOFF,
OSCRANGE[2:0]
Option bits
f
LTIMER
8-BIT
LITE TIMER 2 COUNTER
(1ms timebase @ 8 MHz f
)
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
MCCSR
SMS
MCO
f
CPU
MCO
25/131
1
ST7LITE2
7.4 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block (1 to 16MHz or 32kHz):
Table 4. ST7 Clock Sources
Hardware Configuration
■ an external source
■ 5 crystal or ceramic resonator oscillators
■ an internal high frequency RC oscillator
ST7
OSC1
OSC2
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configurations are shown in Table 4. Refer to the
electrical characteristics section for more details.
EXTERNAL
SOURCE
External Clock Source
In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
ST7
OSC1
OSC2
Note: when the Multi-Oscillator is not used, PB4 is
selected by default as external clock.
Crystal/Ceramic Oscillators
C
C
L2
L1
This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption (refer
to section 15.1 on page 123 for more details on the
frequency ranges). In this mode of the multi-oscil-
lator, the resonator and the load capacitors have
to be placed as close as possible to the oscillator
pins in order to minimize output distortion and
start-up stabilization time. The loading capaci-
tance values must be adjusted according to the
selected oscillator.
LOAD
CAPACITORS
ST7
OSC1
OSC2
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Internal RC Oscillator
In this mode, the tunable 1%RC oscillator is used
as main clock source. The two oscillator pins have
to be tied to ground.
26/131
1
ST7LITE2
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 12).
(see
STARTUP
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 14. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
Active Phase
FETCH
256 or 4096 CLOCK CYCLES
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
■ 256 or 4096 CPU clock cycle delay (see table
below)
ON
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
A RESET signal originating from an external
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
CPU clock
Clock Source
cycle delay
Internal RC Oscillator
256
256
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
4096
Figure 15. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
27/131
1
ST7LITE2
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.5.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
7.5.3 External Power-On RESET
■ Voltage Drop RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 16.
DD
IT-
signal is held low until V
level specified for the selected f
is over the minimum
DD
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
g(VDD)
frequency.
DD
OSC
A proper reset signal for a slow rising V
supply
DD
can generally be provided by an external RC net-
work connected to the RESET pin.
7.5.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
w(RSTL)out
Figure 16. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 TCPU
VECTOR FETCH
)
28/131
1
ST7LITE2
7.6 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum V
value (guaranteed for
DD
the oscillator frequency) is above V
MCU can only be in two modes:
, the
IT-(LVD)
7.6.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
– under full software control
– in static safe reset
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
lower than the V
reference value for a voltage drop is
IT-(LVD)
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
reference value for power-
IT+(LVD)
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
Notes:
V
is below:
DD
The LVD allows the device to be used without any
external RESET circuitry.
– V
when V is rising
IT+(LVD)
DD
– V
when V is falling
The LVD is an optional function which can be se-
lected by option byte.
IT-(LVD)
DD
The LVD function is illustrated in Figure 17.
Figure 17. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
(LVD)
IT-
(LVD)
RESET
29/131
1
ST7LITE2
Figure 18. Reset and Supply Management Block Diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
AVD Interrupt Request
RESET
SICSR
(RSM)
0
0
0
WDGRFLOCKED LVDRFAVDF AVDIE
LOW VOLTAGE
DETECTOR
(LVD)
V
SS
V
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
30/131
1
ST7LITE2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.2 Auxiliary Voltage Detector (AVD)
abled through the option byte.
7.6.2.1 Monitoring the V Main Supply
The Voltage Detector function (AVD) is based on
DD
an analog comparison between a V
and
main sup-
IT-(AVD)
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 15.1 on page 123).
V
reference value and the V
IT+(AVD)
DD
ply voltage (V
for falling voltage is lower than the V
ence value for rising voltage in order to avoid par-
). The V
reference value
AVD
IT-(AVD)
refer-
IT+(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
or
IT+(LVD)
asitic detection (hysteresis).
V
threshold (AVDF bit is set).
IT-(AVD)
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 19.
Caution: The AVD functions only if the LVD is en-
Figure 19. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
AVDF bit
0
1
1
RESET
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
31/131
1
ST7LITE2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.3 Low Power Modes
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
WAIT
HALT
Description
Enable Exit
Control from
Exit
from
Halt
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Event
Flag
Interrupt Event
Bit
Wait
The CRSR register is frozen.
The AVD remains active.
AVD event
AVDF AVDIE
Yes
No
7.6.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
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1
ST7LITE2
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Reset Value: 0000 0xx0 (0xh)
7
0
WDG
RF
0
0
0
LOCKED LVDRF AVDF AVDIE
Bit 1 = AVDF Voltage Detector flag
Bit 7:5 = Reserved, must be kept cleared.
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to Figure
19 and to Section 7.6.2.1 for additional details.
Bit 4 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
0: V over AVD threshold
DD
1: V under AVD threshold
DD
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET Sources
LVDRF WDGRF
External RESET pin
Watchdog
0
0
1
0
1
0: AVD interrupt disabled
1: AVD interrupt enabled
LVD
X
Application notes
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
33/131
1
ST7LITE2
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 20.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
It will be serviced according to the flowchart on
Figure 20.
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically NANDed before entering the
edge/level detection block.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
8.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Interrupts and Low Power Mode
– Writing “0” to the corresponding bit in the status
register or
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
8.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
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ST7LITE2
INTERRUPTS (Cont’d)
Figure 20. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
Exit
from
Exit
from
Source
Block
Register Priority
Label
Address
Vector
N°
Description
Order HALT or ACTIVE
AWUFH -HALT
RESET
TRAP
AWU
ei0
Reset
yes
no
yes
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
N/A
Highest
Priority
Software Interrupt
Auto Wake Up Interrupt
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
1)
0
1
2
3
4
5
6
7
AWUCSR
yes
yes
no
ei1
no
N/A
ei2
ei3
LITE TIMER LITE TIMER RTC2 interrupt
Not used
LTCSR2
SICSR
SI
AVD interrupt
no
AT TIMER Output Compare Interrupt PWMxCSR
8
FFEAh-FFEBh
or Input Capture Interrupt
AT TIMER Overflow Interrupt
LITE TIMER Input Capture Interrupt
LITE TIMER RTC1 Interrupt
SPI Peripheral Interrupts
Not usedNot used
or ATCSR
ATCSR
LTCSR
AT TIMER
no
9
yes
no
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
10
11
12
13
LITE TIMER
SPI
LTCSR
yes
no
Lowest
Priority
SPICSR
yes
Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
35/131
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ST7LITE2
INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
EXTERNAL INTERRUPT SELECTION REGIS-
TER (EISR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 1100 (0Ch)
7
0
7
0
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00
Bit 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3
(Port B0) according to Table 6.
Bit 7:6 = ei3[1:0] ei3 pin selection
These bits are written by software. They select the
Port B I/O pin used for the ei3 external interrupt ac-
cording to the table below.
External Interrupt I/O pin selection
Bit 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
(Port B3) according to Table 6.
ei31
ei30
I/O Pin
0
0
1
0
1
0
PB0 *
PB1
Bit 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1
PB2
(Port A7) according to Table 6.
* Reset State
Bit 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
(Port A0) according to Table 6.
Bit 5:4 = ei2[1:0] ei2 pin selection
These bits are written by software. They select the
Port B I/O pin used for the ei2 external interrupt ac-
cording to the table below.
Note: These 8 bits can be written only when the I
bit in the CC register is set.
External Interrupt I/O pin selection
ei21
ei20
I/O Pin
Table 6. Interrupt Sensitivity Bits
0
0
1
1
0
1
0
1
PB3 *
PB4
PB5
PB6
ISx1 ISx0
External Interrupt Sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
* Reset State
Rising and falling edge
.
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1
ST7LITE2
INTERRUPTS (Cont’d)
Bit 3:2 = ei1[1:0] ei1 pin selection
Port A I/O pin used for the ei0 external interrupt ac-
cording to the table below.
These bits are written by software. They select the
Port A I/O pin used for the ei1 external interrupt ac-
cording to the table below.
External Interrupt I/O pin selection
External Interrupt I/O pin selection
ei01
ei00
I/O Pin
0
0
1
1
0
1
0
1
PA0 *
PA1
PA2
PA3
ei11
ei10
I/O Pin
0
0
1
1
0
1
0
1
PA4
PA5
PA6
PA7*
* Reset State
* Reset State
Bits 1:0 = Reserved.
Bit 1:0 = ei0[1:0] ei0 pin selection
These bits are written by software. They select the
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ST7LITE2
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the ST7 (see
Figure 21):
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
■ Slow
■ Wait (and Slow-Wait)
■ Active Halt
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
■ Auto Wake up From Halt (AWUFH)
■ Halt
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided or multiplied by 2
lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ing WAIT mode while the device is already in
SLOW mode.
(f
).
OSC2
Figure 22. SLOW Mode Clock Transition
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
f
/32
f
OSC
OSC
f
CPU
Figure 21. Power Saving Mode Transitions
f
OSC
High
RUN
SMS
NORMAL RUN MODE
REQUEST
SLOW
WAIT
SLOW WAIT
ACTIVE HALT
AUTO WAKE UP FROM HALT
HALT
Low
POWER CONSUMPTION
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ST7LITE2
POWER SAVING MODES (Cont’d)
9.3 WAIT MODE
Figure 23. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
‘WFI’ instruction.
I BIT
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
Refer to Figure 23.
I BIT
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 1)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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ST7LITE2
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
Figure 25. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE-HALT is disabled
(see section 9.5 on page 41 for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
WATCHDOG
ENABLE
0
DISABLE
WDGHALT 1)
1
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 25).
OSCILLATOR
OFF
WATCHDOG
RESET
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
I BIT
X 4)
256 OR 4096 CPU CLOCK
5)
CYCLE DELAY
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 123 for more details).
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Figure 24. HALT Timing Overview
Notes:
256 OR 4096 CPU
CYCLE DELAY
RUN
HALT
RUN
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
RESET
OR
INTERRUPT
can still be active.
HALT
INSTRUCTION
[Active Halt disabled]
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5 Interrupt Mapping for more details.
FETCH
VECTOR
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when-
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
(see Figure 12).
STARTUP
40/131
1
ST7LITE2
POWER SAVING MODES (Cont’d)
9.4.1 Halt Mode Recommendations
9.5 ACTIVE-HALT MODE
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction. The decision to enter either in ACTIVE-
HALT or HALT mode is given by the LTCSR/ATC-
SR register status as shown in the following table:
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
ATCSR
OVFIE
bit
LTCSR1
TB1IE bit
ATCSR ATCSR
CK1 bit CK0 bit
Meaning
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
0
0
1
x
x
0
x
1
x
x
x
0
0
x
x
1
ACTIVE-HALT
mode disabled
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in pro-
gram memory with the value 0x8E.
ACTIVE-HALT
mode enabled
The MCU can exit ACTIVE-HALT mode on recep-
tion of a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 35) or a RESET.
– As the HALT instruction clears the interrupt mask
in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits be-
fore executing the HALT instruction. This avoids
entering other peripheral interrupt routines after
executing the external interrupt routine corre-
sponding to the wake-up event (reset or external
interrupt).
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 or 4096 CPU cycle delay oc-
curs. After the start up delay, the CPU resumes
operation by fetching the reset vector which
woke it up (see Figure 27).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 27).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately (see Note 3).
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Note: As soon as ACTIVE-HALT is enabled, exe-
cuting a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
41/131
1
ST7LITE2
POWER SAVING MODES (Cont’d)
Figure 26. ACTIVE-HALT Timing Overview
9.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of a specific in-
ternal RC oscillator for wake-up (Auto Wake Up
from Halt Oscillator). Compared to ACTIVE-HALT
mode, AWUFH has lower power consumption (the
main clock is not kept running, but there is no ac-
curate realtime clock available.
ACTIVE
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
HALT
INSTRUCTION
[Active Halt Enabled]
INTERRUPT
FETCH
VECTOR
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 27. ACTIVE-HALT Mode Flow-chart
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
Figure 28. AWUFH Mode Block Diagram
HALT INSTRUCTION
(Active Halt enabled)
(AWUCSR.AWUEN=0)
AWU RC
oscillator
I BIT
to Timer input capture
f
AWU_RC
N
RESET
Y
AWUFH
interrupt
N
INTERRUPT 3)
/64
divider
AWUFH
prescaler/1 .. 255
(ei0 source)
OSCILLATOR
PERIPHERALS 2)
CPU
Y
ON
OFF
ON
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
I BIT
X 4)
(f
). Its frequency is divided by a fixed divid-
AWU_RC
256 OR 4096 CPU CLOCK
CYCLE DELAY
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the RTC1 interrupt and some specific inter-
rupts can exit the MCU from ACTIVE-HALT mode.
Refer to Table 5, “Interrupt Mapping,” on page 35
for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
measuring the clock frequency f
and then
AWU_RC
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
to the input capture of the 12-bit Auto-Re-
AWU_RC
load timer, allowing the f
to be measured
AWU_RC
using the main oscillator clock as a reference time-
base.
42/131
1
ST7LITE2
POWER SAVING MODES (Cont’d)
Similarities with Halt mode
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
The following AWUFH mode behaviour is the
same as normal Halt mode:
– The MCU can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 9.4 HALT MODE).
– When entering AWUFH mode, the I bit in the CC
register is forced to 0 to enable interrupts. There-
fore, if an interrupt is pending, the MCU wakes
up immediately.
– The compatibility of Watchdog operation with
AWUFH mode is configured by the WDGHALT
option bit in the option byte. Depending on this
setting, the HALT instruction when executed
while the Watchdog system is enabled, can gen-
erate a Watchdog RESET.
Figure 29. AWUF Halt Timing Diagram
t
AWU
RUN MODE
HALT MODE
256 OR 4096 t
RUN MODE
CPU
f
CPU
f
AWU_RC
Clear
by software
AWUFH interrupt
43/131
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ST7LITE2
POWER SAVING MODES (Cont’d)
Figure 30. AWUFH Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 5, “Interrupt
Mapping,” on page 35 for more details.
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
AWU RC OSC
MAIN OSC
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
PERIPHERALS 2)
CPU
5. If the PLL is enabled by option byte, it outputs
the clock after an additional delay of t
Figure 12).
(see
STARTUP
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 OR 4096 CPU CLOCK
5)
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
44/131
1
ST7LITE2
POWER SAVING MODES (Cont’d)
9.6.0.1 Register Description
7
0
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Reset Value: 0000 0000 (00h)
Bits 7:0= AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
7
0
AWU AWU AWU
EN
0
0
0
0
0
AWUPR[7:0]
Dividing factor
F
M
00h
01h
...
Forbidden
Bits 7:3 = Reserved.
1
...
FEh
FFh
254
255
Bit 1= AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR. Writing to this bit does not
change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
In AWU mode, the period that the MCU stays in
Halt Mode (t
fined by
in Figure 29 on page 43) is de-
AWU
1
t
= 64 × AWUPR × ------------------------- + t
RCSTRT
AWU
f
AWURC
Bit 1= AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the inputcapture of the 12-bit
Auto-Reload timer. This allows the timer to be
used to measure the AWU RC oscillator disper-
sion and then compensate this dispersion by pro-
viding the right value in the AWUPRE register.
0: Measurement disabled
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Note: If 00h is written to AWUPR, depending on
the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains
inchanged.
1: Measurement enabled
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the microcontroller after a time delay de-
pendent on the AWU prescaler value. It is set and
cleared by software.
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Table 7. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
004Ah
1
1
1
1
1
1
1
1
AWUCSR
Reset Value
0
0
0
0
0
AWUF
AWUM
AWUEN
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ST7LITE2
10 I/O PORTS
10.1 INTRODUCTION
If several I/O interrupt pins on the same interrupt
vector are selected simultaneously, they are logi-
cally combined. For this reason if one of the inter-
rupt pins is tied low, it may mask the others.
The I/O ports allow data transfer. An I/O port can
contain up to 8 pins. Each pin can be programmed
independently either as a digital input or digital
output. In addition, specific pins may have several
other functions. These functions can include exter-
nal interrupt, alternate signal input/output for on-
chip peripherals or analog input.
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Modifying the sensitivity
bits will clear any pending interrupts.
10.2.2 Output Modes
10.2 FUNCTIONAL DESCRIPTION
Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
through the latch. Reading the DR bits returns the
previously stored value.
A Data Register (DR) and a Data Direction Regis-
ter (DDR) are always associated with each port.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The
following description takes into account the OR
register. Refer to the Port Configuration table for
device specific information.
If an OR bit is available, different output modes
can be selected by software: push-pull or open-
drain. Refer to I/O Port Implementation section for
configuration.
DR Value and Output Pin Status
An I/O pin is programmed using the corresponding
bits in the DDR, DR and OR registers: bit x corre-
sponding to pin x of the port.
DR
Push-Pull
Open-Drain
0
1
V
V
OL
Floating
OL
Figure 31 shows the generic I/O block diagram.
V
OH
10.2.1 Input Modes
10.2.3 Alternate Functions
Clearing the DDRx bit selects input mode. In this
mode, reading its DR bit returns the digital value
from that I/O pin.
Many ST7s I/Os have one or more alternate func-
tions. These may include output signals from, or
input signals to, on-chip peripherals. The Device
Pin Description table describes which peripheral
signals can be input/output to which ports.
If an OR bit is available, different input modes can
be configured by software: floating or pull-up. Re-
fer to I/O Port Implementation section for configu-
ration.
A signal coming from an on-chip peripheral can be
output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
al’s control register). The peripheral configures the
I/O as an output and takes priority over standard I/
O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
Notes:
1. Writing to the DR modifies the latch value but
does not change the state of the input pin.
2. Do not use read/modify/write instructions
(BSET/BRES) to modify the DR register.
External Interrupt Function
Configuring an I/O as floating enables alternate
function input. It is not recommended to configure
an I/O as pull-up as this will increase current con-
sumption. Before using an I/O as an alternate in-
put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
Depending on the device, setting the ORx bit while
in input mode can configure an I/O as an input with
interrupt. In this configuration, a signal edge or lev-
el input on the I/O generates an interrupt request
via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter-
nal Interrupt Control Register (EICR) or the Miscel-
laneous Register controls this sensitivity, depend-
ing on the device.
Configure an I/O as input floating for an on-chip
peripheral signal which can be input and output.
Caution:
I/Os which can be configured as both an analog
and digital alternate function need special atten-
tion. The user must control the peripherals so that
the signals do not arrive at the same time on the
same pin. If an external clock is used, only the
clock alternate function should be employed on
that I/O pin and not the other alternate function.
A device may have up to 7 external interrupts.
Several pins may be tied to one external interrupt
vector. Refer to Pin Description to see which ports
have external interrupts.
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ST7LITE2
I/O PORTS (Cont’d)
Figure 31. I/O Port General Block Diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
Table 8. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Input
Off
On
Off
Pull-up with/without Interrupt
On
Push-pull
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
is not implemented in the
DD
true open drain pads. A local protection between
the pad and V is implemented to protect the de-
OL
vice against positive stress.
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1
ST7LITE2
I/O PORTS (Cont’d)
Table 9. I/O Configurations
Hardware Configuration
DR REGISTER ACCESS
V
DD
R
NOTE 3
PULL-UP
CONDITION
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
V
NOTE 3
DD
DR REGISTER ACCESS
R
PU
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
NOTE 3
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
3. For true open drain, these elements are not implemented.
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ST7LITE2
I/O PORTS (Cont’d)
Analog alternate function
Figure 32. Interrupt I/O Port State Transitions
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
Analog Recommendations
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
= DDR, OR
XX
10.4 UNUSED I/O PINS
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
10.5 LOW POWER MODES
10.3 I/O PORT IMPLEMENTATION
Mode
WAIT
HALT
Description
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 32. Other transitions
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
10.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
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ST7LITE2
I/O PORTS (Cont’d)
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
The I/O port register configurations are summa-
rised as follows.
Interrupt Ports
Ports where the external interrupt capability is
selected using the EISR register
Standard Ports
PA7:0, PB6:0
MODE
DDR
OR
0
floating input
0
0
1
1
MODE
DDR
OR
0
pull-up interrupt input
open drain output
push-pull output
1
floating input
pull-up input
0
0
1
1
0
1
1
open drain output
push-pull output
0
1
Table 10. Port Configuration (Standard ports)
Input
Output
Port
Pin name
OR = 0
floating
floating
OR = 1
OR = 0
OR = 1
Port A
Port B
PA7:0
PB6:0
open drain
open drain
push-pull
push-pull
pull-up
pull-up
Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Input
Output
Port
Pin name
OR = 0
floating
floating
OR = 1
OR = 0
OR = 1
push-pull
push-pull
Port A
Port B
PA7:0
PB6:0
pull-up interrupt
pull-up interrupt
open drain
open drain
Table 11. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
MSB
1
LSB
1
0000h
0001h
0002h
0003h
0004h
0005h
Reset Value
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
PADDR
MSB
0
LSB
0
Reset Value
0
1
1
0
0
PAOR
MSB
0
LSB
0
Reset Value
PBDR
MSB
1
LSB
1
Reset Value
PBDDR
MSB
0
LSB
0
Reset Value
PBOR
MSB
0
LSB
0
Reset Value
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ST7LITE2
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
■ Optional
reset
on
HALT
instruction
(configurable by option byte)
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
■ Hardware Watchdog selectable by option byte
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
11.1.2 Main Features
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
36µs.
■ Programmable free-running downcounter (64
increments of 16000 CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 33. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
T5
T0
T6
WDGA
T1
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷16000
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ST7LITE2
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see Table 12
.Watchdog Timing):
Notes:
1. The timing variation shown in Table 12 is due to
the unknown status of the prescaler when writing
to the CR register.
2. The number of CPU clock cycles applied during
the RESET phase (256 or 4096) must be taken
into account in addition to these timings.
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
Refer to the Option Byte description in section 15
on page 123.
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller. Same behavior in active-halt
mode.
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 12.Watchdog Timing
f
= 8MHz
CPU
WDG
Counter
Code
min
[ms]
max
[ms]
C0h
FFh
1
2
127
128
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ST7LITE2
WATCHDOG TIMER (Cont’d)
11.1.5 Interrupts
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
None.
11.1.6 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
7
0
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
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ST7LITE2
WATCHDOG TIMER (Cont’d)
Table 13. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
002Eh
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ST7LITE2
11.2 12-BIT AUTORELOAD TIMER 2 (AT2)
11.2.1 Introduction
■ Maskable overflow interrupt
■ Generation of four independent PWMx signals
The 12-bit Autoreload Timer can be used for gen-
eral-purpose timing functions. It is based on a free-
running 12-bit upcounter with an input capture reg-
ister and four PWM output channels. There are 6
external pins:
■ Frequency 2KHz-4MHz (@ 8 MHz f
)
CPU
– Programmable duty-cycles
– Polarity control
– Programmable output modes
– Maskable Compare interrupt
■ Input Capture
– Four PWM outputs
– ATIC pin for the Input Capture function
– BREAK pin for forcing a break condition on the
PWM outputs
– 12-bit input capture register (ATICR)
– Triggered by rising and falling edges
– Maskable IC interrupt
11.2.2 Main Features
■ 12-bit upcounter with 12-bit autoreload register
(ATR)
Figure 34. Block Diagram
ATIC
12-BIT INPUT CAPTURE REGISTER
ATICR
ATCSR
IC INTERRUPT
REQUEST
OVF INTERRUPT
REQUEST
0
ICF
ICIE
CK1 CK0 OVF OVFIECMPIE
CMP
INTERRUPT
REQUEST
f
CMPF0
CMPF1
CMPF2
CMPF3
LTIMER
(1 ms
timebase
@ 8MHz)
f
COUNTER
12-BIT UPCOUNTER
f
CPU
CNTR
ATR
32 MHz
12-BIT AUTORELOAD REGISTER
OEx bit
DCR0L
DCR0H
CMPFx bit
OPx bit
Preload
Preload
PWMx
f
POL-
ARITY
COMP-
PARE
PWM
on OVF Event
IF TRAN=1
12-BIT DUTY CYCLE VALUE (shadow)
4 PWM Channels
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.3 Functional Description
PWM Mode
contents of the corresponding DCRx register must
be greater than the contents of the ATR register.
The polarity bits can be used to invert any of the
four output signals. The inversion is synchronized
with the counter overflow if the TRAN bit in the
TRANCR register is set (reset value). See Figure
35.
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins. The PWMx output signals can be enabled or
disabled using the OEx bits in the PWMCR regis-
ter.
PWM Frequency and Duty Cycle
Figure 35. PWM Inversion Diagram
The four PWM signals have the same frequency
inverter
(f
) which is controlled by the counter period
PWMx
PWM
PWMx
PIN
and the ATR register value.
f
= f / (4096 - ATR)
PWM
COUNTER
PWMxCSR Register
OPx
Following the above formula,
– If f is 32 MHz, the maximum value of
COUNTER
PWM
f
is 8 MHz (ATR register value = 4092), the
minimum value is 8 KHz (ATR register value = 0)
DFF
– If f is 4 Mhz the maximum value of f
is 2 MHz (ATR register value = 4094),the mini-
mum value is 1 KHz (ATR register value = 0).
TRAN
COUNTER
,
PWM
TRANCR Register
counter
overflow
Note: The maximum value of ATR is 4094 be-
cause it must be lower than the DCR value which
must be 4095 in this case.
The maximum available resolution for the PWMx
duty cycle is:
At reset, the counter starts counting from 0.
Resolution = 1 / (4096 - ATR)
When a upcounter overflow occurs (OVF event),
the preloaded Duty cycle values are transferred to
the Duty Cycle registers and the PWMx signals
are set to a high level. When the upcounter match-
es the DCRx value the PWMx signals are set to a
low level. To obtain a signal on a PWMx pin, the
Note: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum reso-
lution, 0% and 100% can be obtained by changing
the polarity.
Figure 36. PWM Function
4095
DUTY CYCLE
REGISTER
(DCRx)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE=1
AND OPx=0
WITH OE=1
AND OPx=1
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
Figure 37. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER
ATR= FFDh
COUNTER
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCRx=000h
DCRx=FFDh
DCRx=FFEh
DCRx=000h
t
Output Compare Mode
When a low level is detected on the BREAK pin,
the BA bit is set and the break function is activat-
ed.
This mode is always available.
To use this function, load a 12-bit value in the
DCRxH and DCRxL registers.
Software can set the BA bit to activate the break
function without using the BREAK pin.
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCRxH and DCRxL registers,
the CMPF bit in the PWMxCSR register is set and
an interrupt request is generated if the CMPIE bit
is set.
When the break function is activated (BA bit =1):
– The break pattern (PWM[3:0] bits in the BREAK-
CR) is forced directly on the PWMx output pins
(after the inverter).
Note: The output compare function is only availa-
– The 12-bit PWM counter is set to its reset value.
ble for DCRx values other than 0 (reset value).
– The ARR, DCRx and the corresponding shadow
registers are set to their reset values.
– The PWMCR register is reset.
Break Function
When the break function is deactivated after ap-
plying the break (BA bit goes from 1 to 0 by soft-
ware):
The break function is used to perform an emergen-
cy shutdown of the power converter.
The break function is activated by the external
BREAK pin (active low). In order to use the
BREAK pin it must be previously enabled by soft-
ware setting the BPEN bit in the BREAKCR regis-
ter.
– The control of PWM outputs is transferred to the
port registers.
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ST7LITE2
Figure 38. Block Diagram of Break Function
BREAK pin (Active Low)
BREAKCR Register
BA
BPEN PWM3 PWM2 PWM1 PWM0
PWM0
PWM1
PWM2
PWM3
1
PWM0
PWM1
0
PWM2
PWM3
(Inverters)
When BA is set:
PWM counter -> Reset value
ARR & DCRx -> Reset value
PWM Mode -> Reset value
Note:
The BREAK pin value is latched by the BA bit.
free running upcounter. An IC interrupt is generat-
ed if the ICIE bit is set. The ICF bit is reset by read-
ing the ATICR register when the ICF bit is set. The
ATICR is a read only register and always contains
the free running upcounter value which corre-
sponds to the most recent input capture. Any fur-
ther input capture is inhibited while the ICF bit is
set.
11.2.3.1 Input Capture
The 12-bit ATICR register is used to latch the val-
ue of the 12-bit free running upcounter after a ris-
ing or falling edge is detected on the ATIC pin.
When an input capture occurs, the ICF bit is set
and the ATICR register contains the value of the
Figure 39. Input Capture Timing Diagram
fCOUNTER
COUNTER
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
ATIC PIN
INTERRUPT
ATICR READ
INTERRUPT
ICF FLAG
ICR REGISTER
09h
xxh
04h
t
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.4 Low Power Modes
The OVF event is mapped on a separate vector
(see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Mode
Description
The input frequency is divided
by 32
SLOW
Note 2: Only if CK0=1 and CK1=0
WAIT
No effect on AT timer
AT timer halted except if CK0=1,
CK1=0 and OVFIE=1
AT timer halted
ACTIVE-HALT
HALT
11.2.5 Interrupts
Exit
Enable Exit
Control from from
Exit
Interrupt
Event
Event
Flag
from
Active-
Halt
1)
Bit
Wait Halt
Overflow
Event
2)
OVF
ICF
OVIE
ICIE
Yes
Yes
No
Yes
IC Event
No
No
No
No
CMP Event CMPF0 CMPIE Yes
Note 1: The CMP and IC events are connected to
the same interrupt vector.
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.6 Register Description
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the tran-
sition of the counter from FFh to ATR value.
0: No counter overflow occurred
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
1: Counter overflow occurred
7
6
0
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
0
ICF
ICIE
CK1
CK0
OVF OVFIE CMPIE
0: OVF interrupt disabled.
1: OVF interrupt enabled.
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when the CMPF bit is set.
0: CMPF interrupt disabled.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: CMPF interrupt enabled.
1: An input capture has occurred
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (000h)
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
15
8
CNTR CNTR
0
0
0
0
CNTR9 CNTR8
11
10
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter. The change be-
comes effective after an overflow.
COUNTER REGISTER LOW (CNTRL)
Read only
Reset Value: 0000 0000 (000h)
Counter Clock Selection
CK1 CK0
OFF
0
0
1
1
0
1
0
1
7
0
1)
f
(1 ms timebase @ 8 MHz)
LTIMER
f
CPU
CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0
2)
32 MHz
Bits 15:12 = Reserved.
Note 1: PWM mode is not available at this fre-
quency.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clok is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations, LSB first. When a counter over-
flow occurs, the counter restarts from the value
specified in the ATR register.
Note 2: ATICR counter may return inaccurate re-
sults when read. It is therefore not recommended
to use Input Capture mode at this frequency.
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
AUTORELOAD REGISTER (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
PWMx CONTROL STATUS REGISTER
(PWMxCSR)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
7
0
6
0
0
0
0
0
0
ATR11 ATR10 ATR9 ATR8
0
0
0
0
OPx CMPFx
AUTORELOAD REGISTER (ATRL)
Read / Write
Bits 7:2= Reserved, must be kept cleared.
Reset Value: 0000 0000 (00h)
7
0
Bit 1 = OPx PWMx Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM signal.
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
0: The PWM signal is not inverted.
1: The PWM signal is inverted.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by soft-
ware. The ATR register value is automatically
loaded into the upcounter when an overflow oc-
curs. The register value is used to set the PWM
frequency.
Bit 0 = CMPFx PWMx Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWMxCSR register. It indicates
that the upcounter value matches the DCRx regis-
ter value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
PWM OUTPUT CONTROL REGISTER
(PWMCR)
Read/Write
Reset Value: 0000 0000 (00h)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
7
0
Reset Value: 0000 0000 (00h)
0
OE3
0
OE2
0
OE1
0
OE0
7
0
0
0
BA
BPEN PWM3 PWM2 PWM1 PWM0
Bits 7:0 = OE[3:0] PWMx output enable.
These bits are set and cleared by software and
cleared by hardware after a reset.
0: PWM mode disabled. PWMx Output Alternate
Function disabled (I/O pin free for general pur-
pose I/O)
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = BA Break Active.
1: PWM mode enabled
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
Bit 4 = BPEN Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
0: Break pin disabled
1: Break pin enabled
15
8
0
0
0
0
ICR11 ICR10 ICR9 ICR8
Bit 3:0 = PWM[3:0] Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active.
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
0
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
15
0
8
Bits 15:12 = Reserved.
0
0
0
DCR11 DCR10 DCR9 DCR8
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR register when a rising or falling edge
occurs on the ATIC pin. Capture will only be per-
formed when the ICF flag is cleared.
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
TRANSFER CONTROL REGISTER (TRANCR)
Read/Write
Reset Value: 0000 0001 (01h)
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
7
0
Bits 15:12 = Reserved.
0
0
0
0
0
0
0
TRAN
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defin-
esthe duty cycle of the corresponding PWM output
signal (see Figure 36).
Bits 7:1 Reserved. Forced by hardware to 0.
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 36). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
Bit 0 = TRAN Transfer enable
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset.
It allows the value of the DCRx registers to be
transferred to the DCRx shadow registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
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ST7LITE2
12-BIT AUTORELOAD TIMER (Cont’d)
Table 14. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
ICF
0
ICIE
0
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
0
0
CNTRH
Reset Value
CNTR11 CNTR10 CNTR9
CNTR8
0
0
0
0
0
0
0
CNTRL
Reset Value
CNTR7
0
CNTR8
0
CNTR7
0
CNTR6
0
CNTR3
0
CNTR2
0
CNTR1
0
CNTR0
0
ATRH
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE3
0
OE2
0
OE1
0
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP0
0
CMPF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM1CSR
Reset Value
OP1
0
CMPF1
0
PWM2CSR
Reset Value
OP2
0
CMPF2
0
PWM3CSR
Reset Value
OP3
0
CMPF3
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR1H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR1L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR2H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR2L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
DCR3H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
0
0
0
0
DCR3L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
ATICRH
Reset Value
ICR11
0
ICR10
0
ICR9
0
ICR8
0
0
0
0
0
ATICRL
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
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1
ST7LITE2
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
TRANCR
Reset Value
TRAN
1
21
22
0
0
0
0
0
0
0
0
0
BREAKCR
Reset Value
BA
0
BPEN
0
PWM3
0
PWM2
0
PWM1
0
PWM0
0
64/131
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ST7LITE2
11.3 LITE TIMER 2 (LT2)
11.3.1 Introduction
– One 8-bit upcounter with autoreload and pro-
grammable timebase period from 4µs to
The Lite Timer can be used for general-purpose
timing functions. It is based on two free-running 8-
bit upcounters, an 8-bit input capture register.
1.024ms in 4µs increments (@ 8 MHz f
– 2 Maskable timebase interrupts
■ Input Capture
)
OSC
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
11.3.2 Main Features
■ Realtime Clock
– One 8-bit upcounter 1 ms or 2 ms timebase
period (@ 8 MHz f
)
OSC
Figure 40. Lite Timer 2 Block Diagram
f
/32
OSC
LTTB2
LTCNTR
Interrupt request
LTCSR2
8-bit TIMEBASE
COUNTER 2
8
0
0
0
0
0
0
TB2IE TB2F
LTARR
f
LTIMER
To 12-bit AT TImer
8-bit AUTORELOAD
REGISTER
/2
1
0
8-bit TIMEBASE
COUNTER 1
Timebase
1 or 2 ms
(@ 8MHz
f
LTIMER
f
)
OSC
8
LTICR
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR1
ICIE
ICF
TB
TB1IE TB1F
LTTB1 INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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ST7LITE2
LITE TIMER (Cont’d)
11.3.3 Functional Description
11.3.3.1 Timebase Counter 1
LTARR reload value. Software can write a new
value at anytime in the LTARR register, this value
will be automatically loaded in the counter when
the next overflow occurs.
The 8-bit value of Counter 1 cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
When Counter 2 overflows, the TB2F bit in the
LTCSR2 register is set by hardware and an inter-
rupt request is generated if the TB2IE bit is set.
The TB2F bit is cleared by software reading the
LTCSR2 register.
/32. An
OSC
overflow event occurs when the counter rolls over
from F9h to 00h. If f = 8 MHz, then the time pe-
OSC
riod between two counter overflow events is 1 ms.
This period can be doubled by setting the TB bit in
the LTCSR1 register.
11.3.3.3 Input Capture
When Counter 1 overflows, the TB1F bit is set by
hardware and an interrupt request is generated if
the TB1IE bit is set. The TB1F bit is cleared by
software reading the LTCSR1 register.
The 8-bit input capture register is used to latch the
free-running upcounter (Counter 1) 1 after a rising
or falling edge is detected on the ICAP1 pin. When
an input capture occurs, the ICF bit is set and the
LTICR1 register contains the MSB of Counter 1.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
11.3.3.2 Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can
be read by accessing the LTCNTR register. After
an MCU reset, it increments at a frequency of
The LTICR is a read-only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
f
/32 starting from the value stored in the
OSC
LTARR register. A counter overflow event occurs
when the counter rolls over from FFh to the
Figure 41. Input Capture Timing Diagram.
4µs
(@ 8MHz f
)
OSC
fCPU
fOSC/32
CLEARED
BY S/W
READING
LTIC REGISTER
01h
02h
03h
04h
05h
06h
07h
8-bit COUNTER 1
LTIC PIN
ICF FLAG
07h
xxh
04h
LTICR REGISTER
t
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1
ST7LITE2
LITE TIMER (Cont’d)
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
Read / Write
Reset Value: 0x00 0000 (x0h)
7
0
0
0
0
0
0
0
TB2IE TB2F
Bits 7:2 = Reserved, must be kept cleared.
11.3.4 Low Power Modes
Mode
SLOW
WAIT
Description
Bit 1 = TB2IE Timebase 2 Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
No effect on Lite timer
(this peripheral is driven directly
by f
/32)
OSC
No effect on Lite timer
ACTIVE-HALT No effect on Lite timer
Bit 0 = TB2F Timebase 2 Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
HALT
Lite timer stops counting
11.3.5 Interrupts
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
Exit
Enable Exit
Control from
Exit
from
Halt
Interrupt Event
from
Active
Halt
Event
Flag
Bit
Wait
LITE
TIMER
AUTORELOAD
REGISTER
Timebase 1
Event
TB1F TB1IE
TB2F TB2IE
Yes
Yes
No
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
Timebase 2
Event
Yes
Yes
No
No
No
No
IC Event
ICF
ICIE
7
0
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
AR7
AR7
AR7
AR7
AR3
AR2
AR1
AR0
Bits 7:0 = AR[7:0] Counter 2 Reload Value.
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
67/131
1
ST7LITE2
LITE TIMER (Cont’d)
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
MHz)
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8
OSC
OSC
7
0
CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0
Bit 4 = TB1IE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bits 7:0 = CNT[7:0] Counter 2 Reload Value.
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
Bit 3 = TB1F Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
7
0
-
Bits 2:0 = Reserved
ICIE
ICF
TB
TB1IE TB1F
-
-
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
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1
ST7LITE2
LITE TIMER (Cont’d)
Table 15. Lite Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR2
Reset Value
TB2IE
0
TB2F
0
08
09
0A
0B
0C
0
0
0
0
0
0
LTARR
Reset Value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
LTCNTR
Reset Value
CNT7
0
CNT6
0
CNT5
0
CNT4
0
CNT3
0
CNT2
0
CNT1
0
CNT0
0
LTCSR1
Reset Value
ICIE
0
ICF
x
TB
0
TB1IE
0
TB1F
0
0
0
0
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
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ST7LITE2
11.4 SERIAL PERIPHERAL INTERFACE (SPI)
11.4.1 Introduction
11.4.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 42 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.4.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Figure 42. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
SOD SSM SSI
0
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
70/131
1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 43.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 46) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 43. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
71/131
1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 45)
There are two cases depending on the data/clock
timing relationship (see Figure 44):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.4.5.3).
– SS internal must be held high continuously
Figure 44. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 45. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
72/131
1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.3 Master Mode Operation
11.4.3.5 Slave Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 46).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
11.4.3.2 and Figure 44. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):
1. Write to the SPICSR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
46 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
11.4.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
2. Write to the SPICR register:
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
When data transfer is complete:
– The SPIF bit is set by hardware
11.4.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware
1. An access to the SPICSR register while the
SPIF bit is set.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.4.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
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ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.4 Clock Phase and Clock Polarity
Figure 46, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 46).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 46. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
74/131
1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5 Error Flags
11.4.5.2 Overrun Condition (OVR)
11.4.5.1 Master Mode Fault (MODF)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the Device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the Device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
11.4.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 11.4.3.2 Slave Select
Management.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the Device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application de-
fault state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 47).
Figure 47. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL=0
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ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured,
using a device as the master and four devices as
slaves (see Figure 48).
Multi-Master System
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 48. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
Slave
Device
SCK
Slave
SCK
Slave
SCK
Slave
Device
Device
Device
MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI
MOSI MISO
SCK
Master
Device
5V
SS
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1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.6 Low Power Modes
SS pin or the SSI bit in the SPICSR register) is low
when the Device enters Halt mode. So if Slave se-
lection is configured as external (see Section
11.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the Device to exit
from WAIT mode.
11.4.7 Interrupts
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the Device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Trans-
fer Event
HALT
SPIF
Yes
Yes
Master Mode
Fault Event
SPIE
MODF
OVR
Yes
Yes
No
No
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
11.4.6.1 Using the SPI to wake-up the Device
from Halt mode
In slave configuration, the SPI is able to wake-up
the Device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the Device from
Halt mode only if the Slave Select signal (external
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ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF=1, MODF=1 or OVR=1
in the SPICSR register)
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.4.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 16 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Table 16. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
f
f
f
/16
/32
/64
CPU
CPU
CPU
Note: This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.4.5.1 Master Mode Fault
(MODF)).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
78/131
1
ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 2 = SOD SPI Output Disable.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
7
0
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.4.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the Device and an exter-
nal device has been completed.
Bit 0 = SSI SS Internal Mode.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 47).
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
0: No write collision occurred
1: A write collision has been detected
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.4.5.2). An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
1: Overrun error detected
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.4.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF=1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 42).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
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ST7LITE2
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0031h
0032h
0033h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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ST7LITE2
11.5 10-BIT A/D CONVERTER (ADC)
11.5.1 Introduction
■ Data register (DR) which contains the results
■ Conversion complete status flag
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 7 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 7 different sources.
■ On/off bit (to reduce consumption)
The block diagram is shown in Figure 49.
11.5.3 Functional Description
11.5.3.1 Analog Power Supply
V
and V
are the high and low level refer-
SSA
DDA
The result of the conversion is stored in a 10-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V and V pins.
DD
SS
11.5.2 Main Features
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
■ 10-bit conversion
■ Up to 7 channels with multiplexed input
■ Linear successive approximation
Figure 49. ADC Block Diagram
DIV 4
1
f
f
ADC
CPU
DIV 2
0
0
1
SLOW
bit
0
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
x 1 or
ANALOG
MUX
x 8
AINx
C
ADC
AMPSEL
bit
ADCDRH
D9
D8
D7
D6
D5
D4
D3
D2
AMP
CAL
AMP
SEL
ADCDRL
0
0
0
SLOW
D1
D0
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ST7LITE2
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.3.2 Input Voltage Amplifier
ADC Conversion mode
The input voltage can be amplified by a factor of 8
by enabling the AMPSEL bit in the ADCDRL regis-
ter.
In the ADCCSR register:
Set the ADON bit to enable the A/D converter and
to start the conversion. From this time on, the
ADC performs a continuous conversion of the
selected channel.
When the amplifier is enabled, the input range is
0V to V /8.
DD
For example, if V
vert voltages in the range 0V to 430mV with an
= 5V, then the ADC can con-
DD
When a conversion is complete:
ideal resolution of 0.6mV (equivalent to 13-bit res-
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
olution with reference to a V to V range).
SS
DD
For more details, refer to the Electrical character-
istics section.
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPSEL bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
11.5.3.3 Digital A/D Conversion Result
3. Read ADCDRH. This clears EOC automati-
cally.
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
If the input voltage (V ) is greater than V
AIN
DDA
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
2. Read ADCDRH. This clears EOC automati-
cally.
If the input voltage (V ) is lower than V
(low-
SSA
AIN
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
11.5.4 Low Power Modes
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
R
is the maximum recommended impedance
AIN
Mode
Description
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
WAIT
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
11.5.3.4 A/D Conversion
HALT
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
t
(see Electrical Characteristics)
STAB
before accurate conversions can be
performed.
In the ADCCSR register:
11.5.5 Interrupts
– Select the CS[2:0] bits to assign the analog
channel to convert.
None.
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ST7LITE2
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
7
0
7
0
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
D9
D8
D7
D6
D5
D4
D3
D2
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
Bit 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
1: Conversion complete
Read/Write
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Reset Value: 0000 00xx (0xh)
7
0
0
AMP
CAL
AMP-
SEL
0
0
SLOW
D1
D0
Bit 5 = ADON A/D Converter on
Bit 7:5 = Reserved. Forced by hardware to 0.
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software.
0: Calibration off
Bit 4:3 = Reserved. Must be kept cleared.
1: Calibration on. The input voltage of the amp is
set to 0V.
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Channel Pin*
CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
SLOW SPEED
ADC
f
/2
0
0
1
0
1
x
CPU
f
CPU
f
/4
CPU
*The number of channels is device dependent. Refer to
the device pinout description.
Bit 2 = AMPSEL Amplifier Selection Bit
This bit is set and cleared by software.
0: Amplifier is not selected
1: Amplifier is selected
Note: When AMPSEL=1 it is mandatory that f
be less than or equal to 2 MHz.
ADC
Bit 1:0 = D[1:0] LSB of Analog Converted Value
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ST7LITE2
Table 18. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0034h
0035h
0036h
ADCDRH
Reset Value
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
ADCDRL
Reset Value
0
0
0
0
0
0
AMPCAL SLOW
AMPSEL
0
D1
x
D0
x
0
0
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ST7LITE2
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 19. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Relative btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
85/131
1
ST7LITE2
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
12.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
86/131
1
ST7LITE2
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
SWAP
Swap Nibbles
Call or Jump subroutine
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
CALL, JP
12.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Instructions
JRxx
Conditional Jump
Call Relative
Indirect Indexed (Short)
CALLR
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long)
Relative (Direct)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 20. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
87/131
1
ST7LITE2
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
88/131
1
ST7LITE2
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
89/131
1
ST7LITE2
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
90/131
1
ST7LITE2
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 51.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 51. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range) and V =3.3V (for the 3V≤V ≤4V
DD
DD
voltage range). They are given only as design
guidelines and are not tested.
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 50.
Figure 50. Pin loading conditions
ST7 PIN
C
L
91/131
1
ST7LITE2
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
ESD(HBM)
V
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
see section 13.7.3 on page 104
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
150
150
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
I
50
IO
- 25
± 5
± 5
± 5
± 5
± 20
mA
Injected current on RESET pin
2) & 4)
I
INJ(PIN)
Injected current on OSC1 and OSC2 pins
5)
Injected current on any other pin
2)
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
Maximum junction temperature (see Table 21, “THERMAL CHARACTERISTICS,” on
page 121)
T
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the device.
92/131
1
ST7LITE2
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions: Suffix 6 Devices
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
2.4
2.7
3.3
0
Max
Unit
f
f
f
= 8 MHz. max., T = 0 to 70°C
5.5
5.5
5.5
16
OSC
OSC
OSC
A
V
Supply voltage
= 8 MHz. max.
= 16 MHz. max.
≥3.3V
V
DD
V
V
V
DD
DD
DD
External clock frequency on
CLKIN pin
f
≥2.4V, T = 0 to +70°C
MHz
CLKIN
A
0
8
≥2.7V
Figure 52. f
Maximum Operating Frequency Versus VDD Supply Voltage
CLKIN
FUNCTIONALITY
GUARANTEED
IN THIS AREA
f
[MHz]
CLKIN
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
FUNCTIONALITY
GUARANTEED
IN THIS AREA
1
0
AT T 0 to 70°C
A
SUPPLY VOLTAGE [V]
5.5
2.7
2.0
2.4
3.3
3.5
4.0
4.5
5.0
93/131
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ST7LITE2
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
1)
4.00
3.40
2.65
4.25
3.60
2.90
4.50
3.80
3.15
Reset release threshold
1)
1)
V
IT+
(LVD)
(V rise)
DD
V
1)
High Threshold
Med. Threshold
Low Threshold
3.80
3.20
2.40
4.05
3.40
2.70
4.30
3.65
2.90
Reset generation threshold
1)
1)
V
V
IT-
(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT-
(LVD)
200
mV
µs/V
ns
hys
IT+
(LVD)
2)
Vt
V
rise time rate
20
20000
150
POR
DD
t
I
Filtered glitch delay on V
DD
Not detected by the LVD
g(VDD)
)
LVD/AVD current consumption
245
µA
DD(LVD
Note:
1. Not tested in production.
2. Not tested in production. The V rise time rate condition is needed to insure a correct device power-on and LVD reset.
DD
When the V slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
1)
4.40
3.90
3.20
4.70
4.10
3.40
5.00
4.30
3.60
1=>0 AVDF flag toggle threshold
1)
1)
V
IT+
(AVD)
(V rise)
DD
V
1)
High Threshold
Med. Threshold
Low Threshold
4.30
3.70
2.90
4.60
3.90
3.20
4.90
4.10
3.40
0=>1 AVDF flag toggle threshold
1)
1)
V
V
IT-
(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
-V
150
mV
V
hys
IT+
IT-
(AVD)
(AVD)
Voltage drop between AVD flag set
and LVD reset activation
∆V
V
fall
0.45
IT-
DD
Note:
1. Not tested in production.
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions
Min
2.4
2.4
3.3
Typ
Max
5.5
Unit
V
Internal RC Oscillator operating voltage
x4 PLL operating voltage
DD(RC)
V
V
3.3
V
DD(x4PLL)
DD(x8PLL)
x8 PLL operating voltage
5.5
PLL
input
clock
t
PLL Startup time
60
STARTUP
(f
)
PLL
cycles
94/131
1
ST7LITE2
OPERATING CONDITIONS (Cont’d)
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.
13.3.4.1 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 4.5 to 5.5V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C,V =5V
Min
Typ
760
Max
Unit
Internal RC oscillator fre-
quency
A
DD
f
kHz
RC
2 )
RCCR = RCCR0 ,T =25°C,V =5V
1000
A
DD
T =25°C,V =4.5 to 5.5V
-1
-5
+1
%
%
%
A
DD
Accuracy of Internal RC
oscillator with
RCCR=RCCR0
ACC
T =-40 to +85°C,V =5V
+2
RC
A
DD
2)
1)
1)
T =0 to +85°C,V =4.5 to 5.5V
-2
+2
A
DD
RC oscillator current con-
sumption
1)
I
T =25°C,V =5V
970
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =5V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
1)
x8 PLL input clock
1
PLL
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x8 PLL Accuracy
PLL jitter period
4)
f
f
f
= 1MHz@T =25°C,V =4.5 to 5.5V
0.1
RC
RC
RC
A
DD
ACC
PLL
4)
= 1MHz@T =-40 to +85°C,V =5V
0.1
%
A
DD
3)
t
= 1MHz
8
kHz
%
w(JIT)
3)
JIT
PLL jitter (∆f
/f )
1
PLL
CPU CPU
1)
I
PLL current consumption T =25°C
600
µA
DD(PLL)
A
Notes:
1. Data based on characterization results, not tested in production
2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ T =25°C, V =5V. See “INTERNAL RC OS-
A
DD
CILLATOR ADJUSTMENT” on page 23
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy.
STAB
PLL
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 12 on page 24.
PLL
STAB
95/131
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ST7LITE2
OPERATING CONDITIONS (Cont’d)
13.3.4.2 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 2.7 to 3.3V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C, V = 3.0V
Min
Typ
560
700
Max
Unit
Internal RC oscillator fre-
quency
A
DD
f
kHz
RC
2)
RCCR=RCCR1 ,T =25°C,V = 3V
A
DD
T =25°C,V =3V
-2
+2
+25
15
%
%
%
A
DD
Accuracy of Internal RC
ACC
oscillator when calibrated T =25°C,V =2.7 to 3.3V
-25
-15
RC
A
DD
1)2)
with RCCR=RCCR1
T =-40 to +85°C,V =3V
A
DD
RC oscillator current con-
sumption
1)
I
T =25°C,V =3V
700
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =3V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
1)
x4 PLL input clock
1
PLL
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x4 PLL Accuracy
PLL jitter period
4)
4)
f
f
f
= 1MHz@T =25°C,V =2.7 to 3.3V
0.1
0.1
RC
RC
RC
A
DD
ACC
PLL
= 1MHz@T =40 to +85°C,V = 3V
%
A
DD
3)
t
= 1MHz
8
1
kHz
%
w(JIT)
3)
JIT
PLL jitter (∆f
/f
)
PLL
CPU CPU
1)
I
PLL current consumption T =25°C
190
µA
DD(PLL)
A
Notes:
1. Data based on characterization results, not tested in production
2. RCCR1 is a factory-calibrated setting for 700MHz with ±0.2 accuracy @ T =25°C, V =3V. See “INTERNAL RC OS-
A
DD
CILLATOR ADJUSTMENT” on page 23.
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy
STAB
PLL
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 12 on page 24.
PLL
STAB
96/131
1
ST7LITE2
OPERATING CONDITIONS (Cont’d)
Figure 53. RC Osc Freq vs V
@ T =25°C
Figure 54. RC Osc Freq vs V
DD
DD
A
(Calibrated with RCCR1: 3V @ 25°C)
(Calibrated with RCCR0: 5V@ 25°C)
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°
0°
25°
90°
105°
130°
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (V)
VDD (V)
Figure 55. Typical RC oscillator Accuracy vs
temperature @ V =5V
DD
(Calibrated with RCCR0: 5V @ 25°C
Figure 56. RC Osc Freq vs V and RCCR Value
DD
1.80
1.60
1.40
1.20
2
(
)
*
1
0
(
)
*
-1
-2
-3
-4
1.00
0.80
0.60
0.40
0.20
0.00
rccr=00h
rccr=64h
rccr=80h
rccr=C0h
rccr=FFh
(
)
*
-5
-45
0
25
85
125
Temperature (°C)
(
) tested in production
*
2.4 2.7
3
3.3 3.75
4
4.5
5
5.5
6
Vdd (V)
97/131
1
ST7LITE2
OPERATING CONDITIONS (Cont’d)
Figure 57. PLL ∆f
/f
versus time
CPU CPU
/f
∆f
CPU CPU
Max
0
t
Min
t
t
w(JIT)
w(JIT)
Figure 58. PLLx4 Output vs CLKIN frequency
Figure 59. PLLx8 Output vs CLKIN frequency
7.00
6.00
5.00
11.00
9.00
7.00
5.00
3.00
1.00
3.3
5.5
5
4.00
3
2.7
4.5
4
3.00
2.00
1.00
0.85
0.9
1
1.5
2
2.5
1
1.5
2
2.5
3
External Input Clock Frequency (MHz)
External Input Clock Frequency (MHz)
Note: f
= f
/2*PLL4
OSC
CLKIN
Note: f
= f
/2*PLL8
CLKIN
OSC
13.3.4.3 32MHz PLL
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Min
Typ
Max
Unit
V
1)
V
Voltage
Frequency
4.5
5
32
8
5.5
DD
1)
f
f
MHz
MHz
PLL32
INPUT
7
Input Frequency
9
Note 1: 32 MHz is guaranteed within this voltage range.
98/131
1
ST7LITE2
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T = -40 to +125°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
7.5
Max
12
Unit
1)
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
f
f
f
f
=8MHz
CPU
CPU
CPU
CPU
2)
3.7
1.6
1.6
1
6
=8MHz
mA
3)
4)
2.5
2.5
10
50
30
=500kHz
=500kHz
I
DD
-40°C≤T ≤+85°C
A
Supply current in HALT mode
15
20
T = +125°C
µA
A
5)6)
Supply current in AWUFH mode
T = +25°C
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
OSC DD
CPU
V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
DD
based on f
divided by 32. All I/O pins in input mode with a static value at
OSC
CPU
V
or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
SS
5. All I/O pins in input mode with a static value at V or V (no load). Data tested in production at V max. and f
max.
6. This consumption refers to the Halt period only and not the associated run period which is software dependent.
DD
SS
DD
CPU
Figure 60. Typical I in RUN vs. f
Figure 61. Typical I in SLOW vs. f
DD
CPU
DD
CPU
9.0
1.6
8 MHz
4 MHz
1 MHz
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
250 KHz
125 KHz
62.5 Khz
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (V)
Vdd (V)
99/131
1
ST7LITE2
SUPPLY CURRENT CHARACTERISITCS (Cont’d)
Figure 62. Typical I in WAIT vs. f
Figure 64. Typical I in AWUFH mode
DD
DD
CPU
at T =25°C
A
1.4
0.035
0.030
0.025
0.020
0.015
0.010
0.005
250 KHz
1.2
fawu_rc ~125 KHz
125 KHz
1.0
62.5 Khz
0.8
0.6
0.4
0.2
0.0
0.000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
Vdd (V)
Figure 65. Typical I vs. Temperature
DD
at V = 5V and f
= 8MHz
Figure 63. Typical I in SLOW-WAIT vs. f
DD
CPU
DD
CPU
8.0
1.4
250 KHz
1.2
125 KHz
1.0
25°
-45°
90°
7.0
62.5 Khz
0.8
0.6
0.4
0.2
0.0
130°
6.0
5.0
4.0
3.0
2.0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (V)
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
Vdd (V)
13.4.2 On-chip peripherals
Symbol
Parameter
Conditions
Typ
Unit
f
f
f
f
=4MHz
=8MHz
=4MHz
=8MHz
V
V
V
V
V
V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
50
150
50
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
1)
I
12-bit Auto-Reload Timer supply current
DD(AT)
2)
I
SPI supply current
µA
DD(SPI)
300
TBD
TBD
3)
I
ADC supply current when converting
f
=4MHz
DD(ADC)
ADC
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f =8MHz.
cpu
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions with am-
DD
plifier off.
100/131
1
ST7LITE2
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1)
2)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
250
10
375
1500
22
3)
tCPU
µs
Interrupt reaction time
t
=8MHz
v(IT)
CPU
t
= ∆t
+ 10
1.25
2.75
v(IT)
c(INST)
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Dt
ish the current instruction execution.
is the number of t
cycles needed to fin-
c(INST)
CPU
13.5.2 Auto Wakeup from Halt Oscillator (AWU)
Symbol
Parameter
Conditions
Min
Typ
125
Max
250
50
Unit
kHz
µs
f
t
AWU Oscillator Frequency
AWU Oscillator startup time
50
AWU
RCSRT
101/131
1
ST7LITE2
13.6 MEMORY CHARACTERISTICS
T = -40°C to 125°C, unless otherwise specified
A
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2.4
5.5
10
V
Operating voltage for Flash write/erase
DD
prog
RET
2)
T =−40 to +85°C
5
Programming time for 1~32 bytes
ms
A
t
T =+25°C
0.24
0.48
Programming time for 1.5 kBytes
s
A
4)
3)
t
Data retention
T =+55°C
20
years
cycles
A
7)
N
Write erase cycles
T =+25°C
10K
RW
A
Read / Write / Erase
modes
= 8MHz, V = 5.5V
6)
2.6
mA
f
I
Supply current
CPU
DD
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
µA
µA
0
13.6.3 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
10
Unit
ms
T =−40 to +85°C
5
t
Programming time for 1~32 bytes
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
cycles
ret
A
7)
N
Write erase cycles
T =+25°C
300K
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.
102/131
ST7LITE2
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-1.2
-1
>1.5
1
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
FFTB
DD DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 66. EMC Recommended power supply connection
ST72XXX
10µF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
103/131
ST7LITE2
EMC CHARACTERISTICS (Cont’d)
13.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product
is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies
the board and the loading of each pin.
Note 1. Data based on characterization results, not tested in production.
13.7.3 7Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
13.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 67 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– A discharge from C through R (body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
4000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
TBD
A
ESD(MM)
104/131
ST7LITE2
Figure 67. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
105/131
ST7LITE2
EMC CHARACTERISTICS (Cont’d)
13.7.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 68. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
TBD
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 68. Simplified Diagram of the ESD Generator for DLU
R
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
2)
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
106/131
ST7LITE2
EMC CHARACTERISTICS (Cont’d)
13.7.4 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 69 and Figure 70 for standard
pins.
Figure 69. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 70. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
107/131
ST7LITE2
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
0.3xVDD
IL
V
V
0.7xVDD
IH
V
400
mV
1)
hys
hysteresis
I
Input leakage current
V
SS≤V ≤V
DD
±1
L
IN
µA
2)
I
Static current consumption
Floating input mode
200
250
S
V
V
=5V
=3V
50
120
160
5
Weak pull-up equivalent
DD
DD
R
V =V
SS
kΩ
3)
PU
IN
resistor
C
I/O pin capacitance
pF
IO
Output high to low level fall
time
t
t
25
25
1)
f(IO)out
C =50pF
Between 10% and 90%
L
ns
Output low to high level rise
1)
r(IO)out
time
4)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 71). Data based on design simulation and/or technology
characteristics, not tested in production.
3. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 72).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 71. Two typical Applications with unused I/O Pin
V
ST7XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
Note: only external pull-up allowed on ICCCLK pin
Figure 72. Typical I vs. V with V =V
SS
PU
DD
IN
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
108/131
ST7LITE2
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
I
I
I
I
I
I
=+5mA T ≤85°C
1.0
1.2
IO
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 76)
T ≥85°C
A
=+2mA T ≤85°C
0.4
0.5
IO
IO
IO
IO
IO
A
T ≥85°C
A
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 78)
T ≥85°C
A
=+8mA T ≤85°C
0.75
0.85
A
T ≥85°C
A
=-5mA, T ≤85°C
V
V
-1.5
-1.6
A
DD
DD
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 84)
T ≥85°C
A
2)
V
OH
=-2mA T ≤85°C
V
V
-0.8
-1.0
A
DD
DD
T ≥85°C
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 75)
I
=+2mA T ≤85°C
0.5
0.6
IO
A
V
T ≥85°C
A
1)3)
2)3)
1)3)
V
OL
I
I
=+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.5
0.6
IO
A
T ≥85°C
A
=-2mA T ≤85°C
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
V
V
-0.8
-1.0
IO
A
DD
DD
V
OH
T ≥85°C
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 74)
I
I
I
=+2mA T ≤85°C
0.6
0.7
IO
IO
IO
A
T ≥85°C
A
V
OL
=+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.6
0.7
A
T ≥85°C
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 81)
=-2mA T ≤85°C
V
V
-0.9
-1.0
2)3)
A
DD
DD
V
OH
T ≥85°C
A
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
.
IO
VDD
3. Not tested in production, based on characterization results.
Figure 73. Typical V at V =2.4V (standard)
Figure 74. Typical V at V =2.7V (standard)
OL DD
OL
DD
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45°C
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
0.01
1
2
0.01
1
2
lio (mA)
lio (mA)
109/131
ST7LITE2
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 75. Typical V at V =3.3V (standard)
Figure 76. Typical V at V =5V (standard)
OL DD
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
0.01
1
2
3
4
5
lio (mA)
0.01
1
2
3
lio (mA)
Figure 77. Typical V at V =2.4V (high-sink)
Figure 79. Typical V at V =3V (high-sink)
OL DD
OL
DD
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
6
7
8
9
10
15
6
7
8
9
10
lio (mA)
lio (mA)
Figure 78. Typical V at V =5V (high-sink)
OL
DD
2.50
2.00
1.50
1.00
0.50
0.00
-45
0°C
25°C
90°C
130°C
6
7
8
9
10
15
lio (mA)
20
25
30
35
40
110/131
ST7LITE2
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 80. Typical V -V at V =2.4V
Figure 82. Typical V -V
at V =3V
DD OH
DD
DD OH DD
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-0.01
-1
-2
lio (mA)
lio (mA)
Figure 83. Typical V -V
at V =4V
DD
Figure 81. Typical V -V at V =2.7V
DD OH
DD OH
DD
2.50
2.00
1.50
1.00
0.50
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-4
-5
-0.01
-1
-2
lio (mA)
lio(mA)
Figure 84. Typical V -V at V =5V
DD OH
DD
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-4
-5
lio (mA)
111/131
ST7LITE2
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 85. Typical V vs. V (standard I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3.3
5
2.4
2.7
3.3
5
VDD (V)
VDD (V)
Figure 86. Typical V vs. V (high-sink I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
3
5
2.4
3
5
VDD (V)
VDD (V)
Figure 87. Typical V -V vs. V
DD OH
DD
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3
4
5
4
5
VDD
VDD (V)
112/131
ST7LITE2
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40°C to 125°C, unless otherwise specified
A
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
0.3xVDD
IL
V
Input high level voltage
0.7xVDD
IH
1)
V
Schmitt trigger voltage hysteresis
2
V
hys
I =+5mA T ≤85°C
1.0
1.2
IO
A
0.5
T ≥85°C
A
2)
V
Output low level voltage
V
=5V
V
OL
DD
I
=+2mA T ≤85°C
0.4
0.5
IO
A
0.2
T ≥85°C
A
V
V
=5V
20
40
40
70
30
80
DD
3) 1)
R
Pull-up equivalent resistor
kΩ
ON
=3V.
120
DD
t
Generated reset pulse duration
Internal reset sources
µs
µs
ns
w(RSTL)out
4)
t
t
External reset pulse hold time
20
h(RSTL)in
g(RSTL)in
5)
Filtered glitch duration
200
6)7)8)
Figure 88. Typical Application with RESET pin
Recommended
V
DD
ST72XXX
if LVD is disabled
V
V
DD
DD
R
ON
INTERNAL
RESET
0.01µF
0.01µF
4.7kΩ
USER
EXTERNAL
RESET
Filter
5)
CIRCUIT
PULSE
GENERATOR
WATCHDOG
LVD RESET
Required if LVD is disabled
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in section 13.9.1 on page 113. Otherwise the reset will not be taken into account internally.
IL
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for I
in section 13.2.2 on page 92.
INJ(RESET)
113/131
ST7LITE2
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
f /128
CPU
0.0625
Max
Unit
Master
Slave
f
f
/42
CPU
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
c(SCK)
0
/24
f
CPU
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 89. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
r(SCK)
t
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
114/131
ST7LITE2
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 90. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
HZ
MSB OUT
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 91. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
r(SCK)
t
w(SCKL)
t
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
115/131
ST7LITE2
13.11 10-BIT ADC CHARACTERISTICS
Subject to general operating condition for V , f
, and T unless otherwise specified.
DD OSC
A
1)
Symbol
Parameter
ADC clock frequency
Conversion voltage range
External input resistor
Conditions
Min
Typ
Max
Unit
MHz
V
f
4
ADC
2)
V
R
V
V
AIN
AIN
SSA
DDA
3)
10
kΩ
C
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
6
pF
ADC
4)
t
0
STAB
µs
3.5
f
=8MHz, f
=4MHz
ADC
CPU
t
- Sample capacitor loading time
- Hold conversion time
4
10
ADC
1/f
ADC
Analog Part
Digital Part
1
I
mA
ADC
0.2
Figure 92. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN
AINx
10-Bit A/D
Conversion
V
AIN
V
0.6V
T
I
C
ADC
6pF
L
±1µA
ST72XXX
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V -V =5V. They are given only as design guide-
A
DD SS
lines and are not tested.
2. When V and V
pins are not available on the pinout, the ADC refers to V and V .
SS
DDA
SSA
DD
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
always valid.
. The first conversion after the enable is then
LOAD
116/131
ST7LITE2
ADC CHARACTERISTICS (Cont’d)
ADC Accuracy with V =5.0V
DD
Symbol
Parameter
Conditions
Typ
Max
4.5
2
Unit
2)
E
Total unadjusted error
TBD
TBD
TBD
TBD
TBD
T
O
G
D
2)
E
E
E
Offset error
2)
1)
Gain Error
f
=8MHz, f
=4MHz
3.5
3
LSB
CPU
ADC
2)
Differential linearity error
2)
E
Integral linearity error
4
L
Notes:
1) Data based on characterization results over the whole temperature range, monitored in production.
2) Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 13.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
Figure 93. ADC Accuracy Characteristics with amplifier disabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
1023
1022
1021
(2) The ideal transfer curve
(3) End point correlation line
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
1021 1022 1023 1024
V
V
DD
SS
117/131
ST7LITE2
ADC CHARACTERISTICS (Cont’d)
Figure 94. ADC Accuracy Characteristics with amplifier enabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
704
V
– V
DD
SS
1LSB
= -------------------------------
IDEAL
1024
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
E =Offset Error: deviation between the first actual
O
transition and the first ideal one.
(1)
E =Gain Error: deviation between the last ideal
G
transition and the last actual one.
E
O
E
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
7
108
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
701 702 703 704
430mV
V
SS
V
(OPAMP)
in
62.5mV
Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that f
be less than or equal
ADC
to 2 MHz. (if f
=8MHz. then SPEED=0, SLOW=1).
CPU
Vout (ADC input)
Vmax
Noise
Vmin
Vin
(OPAMP input)
0V
430mV
118/131
ST7LITE2
ADC CHARACTERISTICS (Cont’d)
Symbol
Parameter
Amplifier operating voltage
Amplifier input voltage
Amplifier offset voltage
Conditions
=5V
Min
4.5
Typ
175
8
Max
5.5
Unit
V
V
V
V
V
DD(AMP)
V
62.5
430
mV
mV
mV
IN
DD
OFFSET
STEP
3)
Step size for monotonicity
Output Voltage Response
Amplified Analog input Gain
5
Linearity
Gain factor
Vmax
Linear
2)
Output Linearity Max Voltage
Output Linearity Min Voltage
V
V
V
V
= 430mV,
INmax
=5V
Vmin
DD
Notes:
1) Data based on characterization results over the whole temperature range, not tested in production.
2) For precise conversion results it is recommended to calibrate the amplifier at the following two points:
– offset at V = 0V
INmin
– gain at full scale (for example V =250mV)
IN
3) Monotonicity guaranteed if V increases or decreases in steps of min. 5mV.
IN
119/131
ST7LITE2
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 95. 20-Pin Plastic Small Outline Package, 300-mil Width
mm
inches
D
h x 45×
Dim.
A
Min Typ Max Min Typ Max
L
2.35
2.65 0.093
0.30 0.004
0.51 0.013
0.32 0.009
13.00 0.496
7.60 0.291
0.104
0.012
0.020
0.013
0.512
0.299
A
c
A1
A1 0.10
a
B
C
D
E
e
0.33
0.23
e
B
12.60
7.40
1.27
0.050
H
h
α
10.00
0.25
0°
10.65 0.394
0.75 0.010
0.419
0.030
8°
E
H
8°
0°
L
0.40
1.27 0.016
0.050
Number of Pins
N
20
Figure 96. 20-Pin Plastic Dual In-Line Package, 300-mil Width
mm
Min Typ Max Min Typ Max
5.33 0.210
inches
Dim.
A2
A
A
A1
c
L
A1 0.38
0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
b
eB
b
D1
e
b2
c
0.20 0.25 0.36 0.008 0.010 0.014
24.89 26.16 26.92 0.980 1.030 1.060
D
D
D1 0.13
0.005
e
2.54
0.100
11
10
20
1
eB
10.92
0.430
E1
E1 6.10 6.35 7.11 0.240 0.250 0.280
L
2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
N
20
120/131
ST7LITE2
PACKAGE CHARACTERISTICS (Cont’d)
Table 21. THERMAL CHARACTERISTICS
Symbol
Ratings
Value
TBD
500
Unit
°C/W
mW
°C
R
Package thermal resistance (junction to ambient)
thJA
1)
P
Power dissipation
D
2)
T
Maximum junction temperature
150
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
121/131
ST7LITE2
14.2 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 97. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
60
40
80
100
140
120
160
Figure 98. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
122/131
ST7LITE2
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in a user
programmable version (FLASH). FLASH devices
are shipped to customers with a default content
(FFh). This implies that FLASH devices have to be
configured by the customer using the Option
Bytes.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
OPT3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
The option bytes can be accessed only in pro-
gramming mode (for example using a standard
ST7 programming tool).
Sector 0 Size
SEC1
SEC0
0.5k
1k
0
0
1
1
0
1
0
1
OPTION BYTE 0
2k
OPT7 = Reserved, must always be 1.
4k
OPT6:4 = OSCRANGE[2:0] Oscillator range
When the internal RC oscillator is not selected
(Option OSC=1), these option bits select the range
of the resonator oscillator current source or the ex-
ternal clock source.
OPT1 = FMP_R Read-out protection
This option indicates if the FLASH program mem-
ory and Data EEPROM is protected against pira-
cy. The read-out protection blocks access to the
program and data areas in any mode except user
mode and IAP mode. Erasing the option bytes
when the FMP_R option is selected will cause the
whole memory to be erased first and the device
can be reprogrammed. Refer to the ST7 Flash
Programming Reference Manual and section 4.5
on page 14 for more details
OSCRANGE
2
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
LP
1~2MHz
2~4MHz
4~8MHz
8~16MHz
MP
MS
HS
Typ.
frequency
range with
Resonator
0: Read-out protection off
1: Read-out protection on
VLP 32.768kHz
on OSC1
OPT0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
External
Clock source:
CLKIN
on PB4
1
1
1
1
1
0
Reserved
Note: When the internal RC oscillator is selected,
the OSCRANGE option bits must be kept at their
default value in order to select the 256 clock cycle
delay (see Section 7.5).
1: Write protection on
OPTION BYTE 0
OPTION BYTE 1
7
0
7
0
OSCRANGE
2:0
FMP FMP PLL PLL PLL32
WDG WDG
SW HALT
Res.
1
SEC1 SEC0
OSC LVD1 LVD0
R
W
x4x8 OFF
OFF
Default
Value
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
123/131
ST7LITE2
OPTION BYTES (Cont’d)
OPTION BYTE 1
Table 22. LVD Threshold Configuration
Configuration
LVD1 LVD0
OPT7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
1
1
0
0
1
0
1
0
LVD Off
Highest Voltage Threshold ( 4.1V)
Medium Voltage Threshold ( 3.5V)
Lowest Voltage Threshold ( 2.8V)
OPT6 = PLLOFF PLL disable.
0: PLL enabled
1: PLL disabled (by-passed)
Each device is available for production in a user
programmable version (FLASH). FLASH devices
are shipped to customers with a default content
(FFh). This implies that FLASH devices have to be
configured by the customer using the Option
Bytes.
OPT5 = PLL32OFF 32MHz PLL disable.
0: PLL32 enabled
1: PLL32 disabled (by-passed)
OPT4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Note: 1% RC oscillator available on ST7LITE25
and ST7LITE29 devices only
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
lected threshold as shown in Table 22.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Table 23. List of valid option combinations
Operating conditions
Option Bits
V
range
Clock Source
PLL
off
Typ f
OSC
PLLOFF
PLLx4x8
DD
CPU
0.7MHz @3V
0
0
-
1
0
-
x
0
-
1)
Internal RC 1%
x4
2.8MHz @3V
x8
-
2.4V - 3.3V
3.3V - 5.5V
off
0-4MHz
1
1
-
1
0
-
x
0
-
External clock or oscillator
(depending on OPT6:4 selec- x4
4MHz
tion)
x8
off
x4
x8
off
x4
x8
-
1MHz @5V
0
-
1
-
x
-
1)
Internal RC 1%
-
8MHz @5V
0-8MHz
-
0
1
-
0
1
-
1
x
-
External clock or oscillator
(depending on OPT6:4 selec-
tion)
8 MHz
1
0
1
Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only
Note: see Clock Management Block diagram in Figure 13
124/131
ST7LITE2
15.2 DEVICE ORDERING INFORMATION
Contact ST sales office for product availability
Table 24. Supported part numbers
Program
RAM
Data
EEPROM
(Bytes)
Temp.
Range
Part Number
Memory
(Bytes)
Package
(Bytes)
ST7FLITE20F2B6
ST7FLITE20F2M6
ST7FLITE25F2B6
ST7FLITE25F2M6
ST7FLITE29F2B6
ST7FLITE29F2M6
DIP20
SO20
DIP20
SO20
DIP20
SO20
-
-
8K FLASH
384
-40°C to 85°C
256
Contact ST sales office for product availability
125/131
ST7LITE2
15.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
ST Emulators
The emulator is delivered with everything (probes,
TEB, adapters etc.) needed to start emulating the
devices. To configure the emulator to emulate dif-
ferent ST7 subfamily devices, the active probe for
the ST7 EMU3 can be changed and the ST7EMU3
probe is designed for easy interchange of TEBs
(Target Emulation Board). See Table 26 for more
details.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Two types of development tool are offered by ST,
all of them connect to a PC via a parallel (LPT) or
USB port: see Table 25 and Table 26 for more de-
tails.
Table 25. STMicroelectronics Tools Features
1)
In-Circuit Emulation
Programming Capability
Software Included
ST7 CD-ROM with:
Yes, powerful emulation
ST7 EMU3 Emulator
features including trace/
logic analyzer
No
– ST7 Assembly toolchain
– STVD7 powerful Source Level
Debugger for Win 9x, Win 2000,
ME and NT4.0
– C compiler demo versions
– ST Realizer for Win 95.
ST7 Programming Board
No
Yes (All packages)
Windows Programming Tools for
Win 9x, NT4.0, 2000 and ME
Note:
1. In-Circuit Programming (ICP) interface for FLASH devices.
Table 26. Dedicated STMicroelectronics Development Tools
Active Probe
Supported Products ST7 Development Kit
ST7 Emulator
ST7 Programming Board
& TEB
ST7MDT10-EPB/EU
ST7MDT10-EPB/US
ST7MDT10-EPB/UK
ST7-STICK/EU
ST7FLITE20
ST7FLITE25
ST7FLITE29
N/A
ST7MDT10-EMU3
ST7MDT10-TEB
ST7-STICK/US
ST7-STICK/UK
126/131
ST7LITE2
15.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
127/131
ST7LITE2
IDENTIFICATION
AN 982
DESCRIPTION
USING ST7 WITH CERAMIC RESONATOR
AN1014
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1040
AN1070
AN1324
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1477
AN1502
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
128/131
ST7LITE2
16 IMPORTANT NOTES
16.1 EXECUTION OF BTJX INSTRUCTION
16.3 A/ D CONVERTER ACCURACY FOR FIRST
CONVERSION
When testing the address $FF with the
"BTJT" or "BTJF" instructions, the CPU may
perform an incorrect operation when the rel-
ative jump is negative and performs an ad-
dress page change.
When the ADC is enabled after being pow-
ered down (for example when waking up
from HALT, ACTIVE-HALT or setting the
ADON bit in the ADCCSR register), the first
conversion (8-bit or 10-bit) accuracy does
not meet the accuracy specified in the da-
tasheet.
To avoid this issue, including when using a C
compiler, it is recommended to never use ad-
dress $00FF as a variable (using the linker
parameter for example).
Workaround
16.2 ADC CONVERSION SPURIOUS RESULTS
In order to have the accuracy specified in the
datasheet, the first conversion after a ADC
switch-on has to be ignored.
Spurious conversions occur with a rate lower
than 50 per million. Such conversions
happen when the measured voltage is just
between 2 consecutive digital values.
Workaround
A software filter should be implemented to
remove erratic conversion results whenever
they may cause unwanted consequences.
129/131
ST7LITE2
17 SUMMARY OF CHANGES
Revision
Main changes
Date
Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) in Table 1, “Device Pin Description,”
on page 7
Modified note 5 in section 4.4 on page 13
Added “and the device can be reprogrammed” in section 4.5.1 on page 14
Added note on RC oscillator in section 7 on page 23 (main features) and changed section
7.1 on page 23: removed reference to ST7LITE20 in RCCR table
Changed Figure 13 on page 25 (CLKIN/2, OSC/2)
Added note in section 7.4 on page 26 (external clock source paragraph)
Added note in the description of AWUPR[7:0] bits in section 9.6.0.1 on page 45
Added text specifying that the watchdog counter is a free-running downcounter: Section
11.1.2 and section 11.1.3 on page 51
2.0
August-03
Added note in the description of OSC option bit and in Table 23, “List of valid option combi-
nations,” on page 124
Changed section 13.7 on page 103
Changed section 13.3.1 on page 93: f
instead of f
OSC
CLKIN
Changed description of WDG HALT option bit (section 15.1 on page 123)
Changed description of FMP_R option bit (section 15.1 on page 123)
Changed Table 26, “Dedicated STMicroelectronics Development Tools,” on page 126
130/131
ST7LITE2
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
131/131
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