ST7FOXA0M6TR [STMICROELECTRONICS]
8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8;
| 型号： | ST7FOXA0M6TR |
| 厂家： | 
ST |
| 描述： | 8-BIT, FLASH, 8MHz, MICROCONTROLLER, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总123页 (文件大小：1936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7FOXA0
8-bit MCU with single voltage Flash memory,
ADC, timers
Features
■ Memories
– 2 Kbytes single voltage extended Flash
(XFlash) Program memory with
Read-Out Protection
SO8
DIP8
In-Circuit Programming and In-Application
programming (ICP and IAP)
Endurance: 1K write/erase cycles
guaranteed
■ 2 timers
– One 8-bit Lite timer with prescaler
including: watchdog,
Data retention: 20 years at 55 °C
– 128 bytes RAM
1 real time base and 1 input capture
■ Clock, Reset and Supply Management
– Single 12-bit Auto-reload timer with 1 PWM
output, input capture, output compare,
dead-time generation and enhanced one
pulse mode functions
– Low voltage supervisor (LVD) for safe
power-on/off
– Clock sources: Internal trimmable 8 MHz
RC oscillator, auto wakeup internal low
power - low frequency oscillator or external
clock
■ A/D converter: 5 input channels
■ Interrupt management
– 11 interrupt vectors plus TRAP and RESET
– External reset source and watchdog reset
■ Instruction set
– Five power saving modes: Halt, Active-Halt,
Auto Wakeup from Halt, Wait and Slow
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
■ I/O Ports
– 5 multifunctional bidirectional I/Os
– 1 additional output line
– 5 high sink outputs
– 8 x 8 unsigned multiply instructions
■ Development tools
– Full HW/SW development package
– DM (Debug Module)
Table 1.
Device summary
Features
ST7FOXA0
Program memory - bytes
RAM (stack) - bytes
Timers
2K
128 (64)
1 x 8-bit timer, 1 x 12-bit AT (1 PWM)
1 x 10-bit
ADC
Packages
SO8 150”, DIP8 300”
February 2008
Rev 3
1/123
www.st.com
1
Contents
ST7FOXA0
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register and memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash programmable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1
4.3.2
In-Circuit Programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
4.5
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.1
4.5.2
Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
4.7
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Description of Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . 20
5
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1
6.1.2
6.1.3
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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ST7FOXA0
Contents
6.2
6.3
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1
6.2.2
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Internal Low Voltage Detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . 32
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . . 34
Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . . 34
6.4
6.5
System Integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1
Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
RC calibration control/status register (RCC_CSR) . . . . . . . . . . . . . . . . 37
Main Clock Control/Status Register (MCCSR) . . . . . . . . . . . . . . . . . . . 37
RC Control Register High (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RC Control Register Low (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Prescaler register (PSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 40
7
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1
7.2
7.3
7.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.4.1
7.4.2
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5
Auto wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.5.1
7.5.2
7.5.3
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AWUFH Control/Status Register (AWUCSR) . . . . . . . . . . . . . . . . . . . . 51
AWUFH Prescaler Register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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ST7FOXA0
8.2.1
8.2.2
8.2.3
8.2.4
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.3
8.4
8.5
8.6
8.7
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Device-specific I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1
Lite Timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.2
12-bit Autoreload Timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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Contents
10.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.2 Immediate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.3 Direct modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.4 Indexed modes (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . 80
10.1.5 Indirect modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.1.6 Indirect indexed modes (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11
12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3.1 External Interrupt Control Register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . 90
11.3.2 External Interrupt Control Register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . 91
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.3.2 Operating conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . 95
12.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5.1 Auto wakeup from Halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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12.7 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 100
12.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 100
12.7.2 EMI (Electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 102
12.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13
Device configuration and ordering information . . . . . . . . . . . . . . . . . 110
13.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1.1 ST7FOXA0 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.1.2 ST7FOXA0 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ST7FOX failure analysis service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 113
13.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14
15
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6/123
ST7FOXA0
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device pin description (8-pin package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ST7FOXA0 Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CPU clock delay during Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AWU register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DR Value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ST7FOXA0 I/O port configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Effect on Lite timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Lite timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Channel selection using CH[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Configuring the ADC clock speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 80
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 81
Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ST7FOXA0 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
AWU from Halt characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
7/123
List of tables
ST7FOXA0
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
RAM and hardware registers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flash program memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ST7FOXA0 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
General characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC accuracy with VDD = 4.5 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Configuration of sector size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8-pin plastic small outline package, 150-mil width, mechanical data . . . . . . . . . . . . . . . . 119
8-pin plastic dual in-line outline package - 300-mil width, mechanical data . . . . . . . . . . . 120
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
8/123
ST7FOXA0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ST7FOXA0 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ST7FOXA0 stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RCCRH_USER and RCCRL_USER programming flowchart. . . . . . . . . . . . . . . . . . . . . . . 26
RC user calibration programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. ST7FOXA0 clock management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. ST7FOXA0 reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 20. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 25. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 26. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 28. Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 29. Watchdog timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 30. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 31. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 33. PWM Signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 34. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35. Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 36. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 37. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 38. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 39. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 40. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 41. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 43. ST7FOXA0 ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 44. 8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 119
Figure 45. 8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 120
9/123
Description
ST7FOXA0
1
Description
The ST7FOXA0 is a member of the ST7 microcontroller family. All ST7 devices are based
on a common industry-standard 8-bit core, featuring an enhanced instruction set.
The device is positioned at the entry level of the 8-bit microcontroller range providing an
attractive cost while at the same time embedding the most advanced features.
The ST7FOXA0 features Flash memory with byte-by-byte In-Circuit Programming (ICP) and
In-Application Programming (IAP) capability.
Under software control, the ST7FOXA0 device can be placed in Wait, Slow, or Halt mode,
reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The ST7FOXA0 features an on-chip Debug Module (DM) to support In-Circuit Debugging
(ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference
Manual.
Figure 1.
General block diagram
Internal
Clock
AWU RC
Osc
8-MHz RC
Osc
External
Clock
Lite timer
with watchdog
Port A
LVD
12-bit auto-
reload timer
PA5:0
(6 bits)
VDD
VSS
Power
Supply
10-bit ADC
PA3 / RESET
Control
8-bit core
ALU
2 K Byte
Flash
Memory
RAM
(128 Bytes)
10/123
ST7FOXA0
Pin description
2
Pin description
Figure 2.
8-pin package pinout
V
1
8
7
6
5
V
SS
DD
PA5 (HS) / AIN4 / CLKIN
PA4 (HS) / AIN3 / MCO
PA3 / RESET
2 ei4
ei0
ei1
ei2
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA1 (HS) / AIN1 / ICCCLK
ei3
3
4
PA2 (HS) / LTIC / AIN2
(HS) : High sink capability
eix : associated external interrupt vector
11/123
Pin description
ST7FOXA0
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level:C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level: HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
●
●
Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
Output: OD = open drain, PP = push-pull
Note:
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Table 2.
Device pin description (8-pin package)
Level
Port / Control
Main
Function
(after
Pin
No.
Input Output
Pin Name
Alternate Function
reset)
(1)
1
2
VDD
S
Main power supply
PA5/AIN4/
CLKIN
I/
O
CT HS
CT HS
X
X
ei4
X
X
X
X
Port A5 Analog input 4 or External Clock Input
I/
O
3
4
5
PA4/AIN3/MCO
PA3/RESET (2)
PA2/AIN2/LTIC
ei3
X
X
X
X
X
X
X
Port A4 Analog input 3 or Main clock output
Port A3 RESET (2)
O
I/
O
Analog input 2 or Lite Timer Input
Capture
CT HS
X
ei2
X
X
Port A2
Analog input 1 or In Circuit
Communication Clock
Caution: During normal operation
this pin must be pulled-up, internally
or externally (external pull-up of 10k
mandatory in noisy environment).
This is to avoid entering ICC mode
unexpectedly during a reset. In the
application, even if the pin is
configured as output, any reset will
put it back in pull-up
PA1/AIN1/
ICCCLK
I/
O
6
CT HS
X
ei1
X
X
X
X
Port A1
PA0/AIN0/
ATPWM/
ICCDATA
Analog input 0 or Auto-Reload Timer
Port A0 PWM or In Circuit Communication
I/
O
7
8
CT HS
X
ei0
X
Data
(1)
VSS
S
Ground
1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
2. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
MUXCR0 and AAh to MUXCR1.
12/123
ST7FOXA0
Register and memory mapping
3
Register and memory mapping
As shown in Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM
and 2 Kbytes of Flash program memory. The RAM space includes up to 64 bytes for the
stack from C0h to FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 3) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option bytes (refer
to Section 13.1 on page 110).
Caution:
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Figure 3.
ST7FOXA0 memory map
0000h
0080h
HW Registers
Short Addressing
RAM (zero page)
(see Table 3)
007Fh
0080h
00C0h
00FFh
64-Byte Stack
RAM
(128 Bytes)
1000h
1001h
RCCRH_USER
RCCRL_USER
00FFh
0100h
DEE0h
DEE1h
RCCRH0
RCCRL0
Reserved
2K Flash
see Section 6.1.1
program memory
F7FFh
F800h
F800h
1 Kbyte
Flash Memory
(2K)
SECTOR 1
FBFFh
FC00h
1 Kbyte
SECTOR 0
FFFFh
FFDFh
FFE0h
Interrupt & Reset Vectors
(see )
FFFFh
(1)
Table 3.
Address
ST7FOXA0 Hardware register map
Block
Register label
Register name
Reset status
Remarks
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h (2)
08h
R/W
R/W
R/W
Port A
02h (3)
0003h to
000Ah
Reserved area (8 bytes)
13/123
Register and memory mapping
ST7FOXA0
Remarks
(1)
Table 3.
Address
ST7FOXA0 Hardware register map (continued)
Block
Register label
Register name
Reset status
000Bh
000Ch
LITE
TIMER
LTCSR
LTICR
Lite Timer Control/Status Register
Lite Timer Input Capture Register
0xh
00h
R/W
Read Only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
Timer Control/Status Register
Counter Register High
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
AUTO-
RELOAD
TIMER
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
R/W
R/W
R/W
0014h to
0016h
Reserved area (3 bytes)
AUTO-
RELOAD
TIMER
0017h
0018h
DCR0H
DCR0L
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
00h
00h
R/W
R/W
0019h to
002Eh
Reserved area (22 bytes)
Flash Control/Status Register
0002Fh
0030h
FLASH
FCSR
00h
00h
R/W
R/W
RC
Calibration
RCC_CSR
RC calibration Control/Status register
0031h to
0033h
Reserved area (3 bytes)
0034h
0035h
0036h
ADCCSR
ADCDRH
ADCDRL
A/D Control Status Register
A/D Data Register High
A/D Data Register Low
00h
xxh
00h
R/W
Read Only
R/W
ADC
0037h
0038h
ITC
EICR1
External Interrupt Control Register 1
Main Clock Control/Status Register
00h
00h
R/W
R/W
MCC
MCCSR
0039h
003Ah
Clock and
Reset
RCCRH
RCCRL
RC oscillator Control Register High
RC oscillator Control Register Low
FFh
0000 0x00b
R/W
R/W
003Bh to
003Ch
Reserved area (2 bytes)
003Dh
ITC
EICR2
PSCR
External Interrupt Control Register 2
Prescaler Register
00h
R/W
003Eh
003Fh
03h
09h
R/W
R/W
Clock
controller
CKCNTCSR Clock Controller Control/Status Register
0040h to
0046h
Reserved area (7 bytes)
0047h
0048h
MuxIO-
reset
MUXCR0
MUXCR1
Mux IO-Reset Control Register 0
Mux IO-Reset Control Register 1
00h
00h
R/W
R/W
0049h
004Ah
AWUPR
AWUCSR
AWU Prescaler Register
AWU Control/Status Register
FFh
00h
R/W
R/W
AWU
14/123
ST7FOXA0
Register and memory mapping
(1)
Table 3.
Address
ST7FOXA0 Hardware register map (continued)
Block
Register label
Register name
Reset status
Remarks
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control Register
DM Status Register
DM Breakpoint Register 1 High
DM Breakpoint Register 1 Low
DM Breakpoint Register 2 High
DM Breakpoint Register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
DM (4)
0051h to
007Fh
Reserved area (47 bytes)
1. Legend: x=undefined, R/W=read/write.
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
3. The bits associated with unavailable pins must always keep their reset value.
4. For a description of the Debug Module registers, see ICC protocol reference manual.
15/123
Flash programmable memory
ST7FOXA0
4
Flash programmable memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-
board using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
●
●
●
ICP (In-Circuit Programming)
IAP (In-Application Programming)
ICT (In-Circuit Testing) for downloading and executing user application test patterns in
RAM
●
●
Sector 0 size configurable by option byte
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
●
●
●
Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row
can be programmed or erased.
In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row can be
programmed or erased without removing the device from the application board.
In-Application Programming. In this mode, sector 1 can be programmed or erased
without removing the device from the application board and while the application is
running.
4.3.1
In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on
a printed circuit board (PCB) to communicate with an external programming device
connected via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
●
Download ICP Driver code in RAM from the ICCDATA pin
●
Execute ICP Driver code in RAM to program the Flash memory
16/123
ST7FOXA0
Flash programmable memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In Application Programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is Write/Erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
●
●
●
●
●
●
RESET: device reset
: device power supply ground
V
SS
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input serial data pin
OSC1: main clock input for external source
V
: application board power supply (optional, see Note 3)
DD
Note:
1
2
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used
to isolate the application RESET circuit in this case. When using a classical RC network with
R>1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3
4
The use of pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a
clock source, regardless of the selection in the option byte. In “disabled option byte” mode
(35-pulse ICC mode), pin 9 has to be connected to the CLKIN pin of the ST7 when the clock
is not available in the application or if the selected clock option is not programmed in the
option byte.
5
A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on
PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin
forces the opposite state in output mode. The resistor value is defined to limit the current
17/123
Flash programmable memory
ST7FOXA0
below 2mA at 5V. If PA3 is used as output push-pull, then the application must be switched
off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to
drive the RESET pin below V , special care must also be taken when a pull-up is placed on
IL
PA3 for application reasons.
Caution:
During normal operation the ICCCLK pin must be internally or externally pulled- up (external
pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly
during a reset. In the application, even if the pin is configured as output, any reset will put it
back in input pull-up.
Figure 4.
Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
APPLICATION BOARD
(See Note 4)
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
3.3kΩ
(See Note 5)
CL2
CL1
APPLICATION
See Note 1 and Caution
APPLICATION
I/O
POWER SUPPLY
See Note 1
ST7
18/123
ST7FOXA0
Flash programmable memory
4.5
Memory protection
There are two different types of memory protection: Read-Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Read-out protection
Read-Out Protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
●
In Flash devices, this protection is removed by reprogramming the option. In this case,
the program memory is automatically erased and the device can be reprogrammed.
The read-out protection is enabled and removed through the FMP_R bit in the option
byte.
4.5.2
Flash write/erase protection
Write/Erase Protection, when set, makes it impossible to both overwrite and erase program
memory. Its purpose is to provide advanced security to applications and prevent any change
being made to the memory content. Write/Erase Protection is enabled through the FMP_W
bit in the option byte.
Caution:
Once set, Write/Erase Protection can never be removed. A write-protected Flash
device is no longer reprogrammable.
4.6
Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
19/123
Flash programmable memory
ST7FOXA0
4.7
Description of Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
7
0
0
0
0
0
0
OPT
LAT
PGM
Read/write
Table 4.
Flash register mapping and reset values
Register
Address
(Hex.)
7
6
5
4
3
2
1
0
label
FCSR
-
0
-
0
-
0
-
0
-
0
OPT
0
LAT
0
PGM
0
002Fh
Reset Value
20/123
ST7FOXA0
Central processing unit
5
Central processing unit
5.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2
Main features
●
●
●
●
●
●
●
●
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
5.3
CPU registers
The six CPU registers shown in Figure 5. They are not present in the memory mapping and
are accessed by specific instructions.
Figure 5.
CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H
X
I
N
X
Z
X
C
X
RESET VALUE =
8
1
1
15
7
0
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
21/123
Central processing unit
ST7FOXA0
5.3.1
5.3.2
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The Cross-Assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
5.3.3
5.3.4
Program Counter (PC)
The Program Counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter low which is
the LSB) and PCH (Program Counter high which is the MSB).
Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
Reset value: 111x 1xxx
7
1
0
1
1
H
I
N
Z
C
Read/write
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry bit
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
22/123
ST7FOXA0
Central processing unit
Bit 3 = I Interrupt mask
bit
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note:
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
by software in the interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Bit 2 = N Negative bit
This bit is set and cleared by hardware. It is representative of the result sign of the last
th
arithmetic, logical or data manipulation. It is a copy of the 7 bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero bit
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
bit
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
5.3.5
Stack Pointer (SP)
Reset value: 00FFh
15
0
8
0
7
1
0
0
0
0
0
0
0
1
SP5 SP4 SP3 SP2 SP1 SP0
Read/write
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 6).
23/123
Central processing unit
ST7FOXA0
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note:
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 6.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 6. ST7FOXA0 stack manipulation example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 00C0h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 00FFh
Stack Higher Address = 00FFh
00C0h
Stack Lower Address =
24/123
ST7FOXA0
Supply, reset and clock management
6
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. The main features are the following:
●
Clock management
–
–
–
8 MHz internal RC oscillator (enabled by option byte)
Auto wakeup RC oscillator (enabled by option byte)
External clock input (enabled by option byte)
●
●
Reset Sequence Manager (RSM)
System Integrity management (SI)
–
Main supply Low voltage detection (LVD) with reset generation (enabled by option
byte)
6.1
RC oscillator adjustment
6.1.1
Internal RC oscillator
The device contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage range (4.5 V - 5.5 V). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCRH (RC Control register High) and in the bits 6:5 in the RCCRL (RC Control register
Low).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored for 5 V V supply voltage at 25 °C (see Table 5).
DD
Table 5.
RCCR
Predefined RC oscillator calibration values
Conditions
ST7FOX
Address
RCCRH
RCCRL
V
DD= 5V
DEE0h(1) (CR[9:2])
DEE1h(1) (CR[1:0])
TA= 25°C
fRC = 8 MHz
1. The DEE0h and DEE1h addresses are located in a reserved area in non-volatile memory. They are read-
only bytes for the application code. This area cannot be erased or programmed by any ICC operations.
For compatibility reasons with the RCCRL register, CR[1:0] bits are stored in the 5th and 6th position of
DEE1 address.
In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of
the selection in the option byte.
Section 12: Electrical characteristics on page 92 for more information on the frequency and
accuracy of the RC oscillator.
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the V and V pins and also between the V and
DD
SS
DDA
V
pins as close as possible to the ST7 device.
SSA
These bytes are systematically programmed by ST.
25/123
Supply, reset and clock management
ST7FOXA0
6.1.2
Customized RC calibration
If the application requires a higher frequency accuracy or if the voltage or temperature
conditions change in the application, the frequency may need to be recalibrated. Two non-
volatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new
values. These two-byte area is Electrically Erasable Programmable Read Only Memory.
Note:
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
How to program RCCRH_USER and RCCRL_USER
To access the write mode, the RCCLAT bit has to be set by software (the RCCPGM bit
remains cleared). When a write access to this two-byte area occurs, the values are latched.
When RCCPGM bit is set by the software, the latched data are programmed in the
EEPROM cells. To avoid wrong programming, the user must take care to only access these
two-byte addresses.
At the end of the programming cycle, the RCCPGM and RCCLAT bits are cleared
simultaneously.
Note:
During the programming cycle, it is forbidden to access the latched data (see Figure 7).
Figure 7.
RCCRH_USER and RCCRL_USER programming flowchart
READ MODE
RCCLAT=0
RCCPGM=0
WRITE MODE
RCCLAT=1
RCCPGM=0
WRITE THE 2 BYTES
AT THEIR ADDRESS
READ BYTES
START PROGRAMMING CYCLE
RCCLAT=1
RCCPGM=1 (set by software)
0
1
RCCLAT
CLEARED BY HARDWARE
Note:
If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
Access error handling
If a read access occurs while RCCLAT=1, then the data bus will not be driven.
If a write access occurs while RCCLAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the integrity of the data in
memory will not be guaranteed.
26/123
ST7FOXA0
Caution:
Supply, reset and clock management
When the Read-Out Protection is enabled through an option bit (see Section 13.1: Option
bytes), these two bytes are protected against Read-out (including a re-write protection). In
Flash devices, when this protection is removed by reprogramming the option byte, these two
bytes are automatically erased.
Figure 8.
RC user calibration programming cycle
READ OPERATION POSSIBLE
READ OPERATION NOT POSSIBLE
Internal
Programming
voltage
ERASE CYCLE
tPROG
WRITE CYCLE
WRITE OF
DATA LATCHES
Byte 1 Byte 2
RCCLAT
RCCPGM
tPROG is typically 5 ms and max 10 ms
6.1.3
Auto wakeup RC oscillator
The ST7FOX also contains an Auto wakeup RC oscillator. This RC oscillator should be
enabled to enter Auto wakeup from halt mode.
The Auto wakeup (AWU) RC oscillator can also be configured as the startup clock through
the CKSEL[1:0] option bits (see Section 13.1: Option bytes on page 110).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 9):
Case 1 Switching from internal RC to AWU
1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2. The RC_FLAG is cleared and the clock output is at 1.
3. Wait 3 AWU RC cycles till the AWU_FLAG is set
4. The switch to the AWU clock is made at the positive edge of the AWU clock signal
5. Once the switch is made, the internal RC is stopped
27/123
Supply, reset and clock management
ST7FOXA0
Case 2 Switching from AWU RC to internal RC
1. Reset the RC/AWU bit to enable the internal RC oscillator
2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4. The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5. Once the switch is made, the AWU RC is stopped
Note:
1
2
When the internal RC is not selected, it is stopped so as to save power consumption.
When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto wakeup from Halt mode.
3
When the external clock is selected, the AWU RC oscillator is always on.
Figure 9.
Clock switching
Set RC/AWU
Internal RC
AWU RC
Poll AWU_FLAG until set
Reset RC/AWU
AWU RC
Internal RC
Poll RC_FLAG until set
28/123
ST7FOXA0
Supply, reset and clock management
Figure 10. ST7FOXA0 clock management block diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3
CR1 CR0
CR2
RCCRH
RCCRL
Tunable
internal RC Oscillator
CKCNTCSR
RC/AWU
8MHz(f
)
RC
8 MHz
4 MHz
2 MHz
1 MHz
Clock
Controller
RC OSC
Prescaler
f
OSC
500 kHz
AWU CK
Ext Clock
CK2 CK1 CK0
PSCR
CKSEL[1:0]
Option bits
33kHz
AWU
RC
/2
DIVIDER
CLKIN
f
CLKIN
f
LTIMER
13-BIT
(1ms timebase @ 8 MHz f
)
LITE TIMER COUNTER
OSC
f
OSC
0
1
f
CPU
f
OSC
TO CPU AND
PERIPHERALS
f
/32
/32 DIVIDER
OSC
MCCSR
MCO SMS
MCO
6.2
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multi-oscillator block (1 to 16 MHz):
●
An external source
●
An internal high frequency RC oscillator
6.2.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive CLKIN.
29/123
Supply, reset and clock management
ST7FOXA0
6.2.2
Internal RC oscillator
In this mode, the tunable RC oscillator is used as main clock source. The two oscillator pins
have to be tied to ground.
The calibration is done through the RCCRH[7:0] and RCCRL[6:5] registers.
6.3
Reset sequence manager (RSM)
6.3.1
Introduction
The reset sequence manager includes three RESET sources as shown in Figure 12:
●
●
●
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 10.2.1 on page 84 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in Figure 11:
●
Active Phase depending on the RESET source
●
256 or 512 CPU clock cycle delay (see Table 6)
Caution:
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte.
The Reset vector fetch phase duration is 2 clock cycles.
Table 6.
CPU clock delay during Reset sequence
Clock source
CPU clock cycle delay
Internal RC 8 MHz Oscillator
Internal RC 32 kHz Oscillator
512
256
512
External clock connected to CLKIN pin
30/123
ST7FOXA0
Supply, reset and clock management
Figure 11. ST7FOXA0 reset sequence phases
RESET
Fetch
Internal reset
active phase
vector
256 or 512 clock cycles
31/123
Supply, reset and clock management
ST7FOXA0
6.3.2
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R weak pull-up
ON
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
t
in order to be recognized (see Figure 13: Reset sequences). This detection is
h(RSTL)in
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
Figure 12. Reset block diagram
VDD
RON
INTERNAL
RESET
Filter
RESET
___
WATCHDOG RESET
PULSE
GENERATOR
___
___
ILLEGAL OPCODE RESET 1)
LVD RESET
1. See Section 10.2.1: Illegal opcode reset on page 84 for more details on illegal opcode reset conditions.
6.3.3
6.3.4
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V is over
the minimum level specified for the selected f
DD
frequency.
OSC
A proper reset signal for a slow rising V supply can generally be provided by an external
RC network connected to the RESET pin.
DD
Internal Low Voltage Detector (LVD) reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-On reset
●
Voltage Drop reset
The device RESET pin acts as an output that is pulled low when V is lower than V
DD
IT+
(rising edge) or V lower than V (falling edge) as shown in Figure 13.
DD
IT-
The LVD filters spikes on V larger than t
to avoid parasitic resets.
g(VDD)
DD
32/123
ST7FOXA0
Supply, reset and clock management
6.3.5
Internal watchdog reset
The Reset sequence generated by an internal watchdog counter overflow is shown in
Figure 13: Reset sequences
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
.
w(RSTL)out
Figure 13. Reset sequences
VDD
VIT+(LVD)
VIT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
tw(RSTL)out
th(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
)
CPU
33/123
Supply, reset and clock management
ST7FOXA0
6.3.6
Multiplexed IO reset control register 1 (MUXCR1)
Reset value: 0000 0000 (00h)
7
0
MIR15
MIR14
MIR13
MIR12
MIR11
MIR10
MIR9
MIR8
Read/write once only
6.3.7
Multiplexed IO reset control register 0 (MUXCR0)
Reset value: 0000 0000 (00h)
7
0
MIR7
MIR6
MIR5
MIR4
MIR3
MIR2
MIR1
MIR0
Read/write once only
Bits 15:0 = MIR[15:0]
This 16-bit register is read/write by software but can be written only once between two
reset events. It is cleared by hardware after a reset; When both MUXCR0 and
MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To
configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
To configure PA3 as general purpose output:
After power-on / reset, the application program has to configure the I/O port by writing
to these registers as described above. Once the pin is configured as an I/O output, it
cannot be changed back to a reset pin by the application code.
To configure PA3 as RESET:
An internally generated reset (such as POR, WDG, illegal opcode) will clear the two
registers and the pin will act again as a reset function. Otherwise, a power-down is
required to put the pin back in reset configuration.
Table 7.
Multiplexed IO register map and reset values
Register
Address
(Hex.)
7
6
5
4
3
2
1
0
Label
MUXCR0
MIR7
0
MIR6
0
MIR5
0
MIR4
0
MIR3
0
MIR2
0
MIR1
0
MIR0
0
0047h
0048h
Reset Value
MUXCR1
MIR15 MIR14 MIR13 MIR12 MIR11 MIR10 MIR9
MIR8
0
0
0
0
0
0
0
0
Reset Value
34/123
ST7FOXA0
Supply, reset and clock management
6.4
System Integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD).
Note:
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 10.2.1 on page 84 for further details.
6.4.1
Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V supply
DD
voltage is below a V
reference value. This means that it secures the power-up as well
IT-(LVD)
as the power-down keeping the ST7 in reset.
The V reference value for a voltage drop is lower than the V
reference value
IT+(LVD)
IT-(LVD)
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when V is below:
DD
●
V
V
when V is rising
DD
IT+(LVD)
IT-(LVD)
●
when V is falling
DD
The LVD function is illustrated in Figure 14.
The voltage threshold can be enabled/disabled by option byte. See Section 13.1 on page
110.
Provided the minimum V value (guaranteed for the oscillator frequency) is above V
,
DD
IT-(LVD)
the MCU can only be in two modes:
●
Under full software control
In static safe reset
●
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Note:
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull V down to 0 V to ensure optimum restart
DD
conditions. Refer to circuit example in Figure 39 on page 106 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 13.1 on
page 110.
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the V supply voltage rises monotonously when the
DD
device is exiting from Reset, to ensure the application functions properly.
Caution:
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
35/123
Supply, reset and clock management
Figure 14. Low voltage detector vs reset
ST7FOXA0
VDD
Vhys
VIT+(LVD)
VIT-(LVD)
RESET
Figure 15. Reset and supply management block diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
RESET SEQUENCE
MANAGER
RCCRL
RESET
(RSM)
0
0
0
CR1 CR0 WDGF
0
LVDRF
LOW VOLTAGE
DETECTOR
(LVD)
VSS
VDD
36/123
ST7FOXA0
Supply, reset and clock management
6.5
Register description
6.5.1
RC calibration control/status register (RCC_CSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
RCCLAT RCCPGM
Read/write
Bits 7:2 = Reserved, forced by hardware to 0
0: Read mode
1: Write mode
Bit 1 = RCCLAT Latch Access Transfer bit: this bit is set by software.
It is cleared by hardware at the end of the programming cycle. It can only be cleared by
software if the RCCPGM bit is cleared
Bit 0 = RCCPGM Programming Control and Status bit
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note:
6.5.2
If the RCCPGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
Main Clock Control/Status Register (MCCSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
MCO
SMS
Read/write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
bit
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow mode selection
bit
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock f or f /32.
OSC
OSC
0: Normal mode (f
f
CPU = OSC
1: Slow mode (f
f
/32)
CPU = OSC
37/123
Supply, reset and clock management
ST7FOXA0
6.5.3
RC Control Register High (RCCRH)
Reset value: 1111 1111 (FFh)
7
0
CR9
CR8
CR7
CR6
Read/write
Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits
CR5
CR4
CR3
CR2
These bits must be written immediately after reset to adjust the RC oscillator
frequency. The application can store the correct value for each voltage range in Flash
memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the RCCRL register. Refer to
Chapter 6.5.4.
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
38/123
ST7FOXA0
Supply, reset and clock management
6.5.4
RC Control Register Low (RCCRL)
Reset value: 0000 0000 (00h)
7
0
0
CR1
CR0
0
0
LVDRF
0
0
Read/write
Bit 7 = Reserved, must be kept cleared
Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCRH register must be written immediately
after reset to adjust the RC oscillator frequency. Refer to Section 6.1.1: Internal RC
oscillator on page 25.
Bits 4:3 = Reserved, must be kept cleared
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled
by option byte, the LVDRF bit value is undefined.
The LVDRF flag is not cleared when another RESET type occurs (external or
watchdog), the LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can
not.
Bits 1:0 = Reserved, must be kept cleared
39/123
Supply, reset and clock management
ST7FOXA0
6.5.5
Prescaler register (PSCR)
Reset value: 0000 0011 (03h)
7
0
CK2
CK1
CK0
0
0
0
1
1
Read/write
Bits 7:5 = CK[2:0] internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits select
the prescaler of the internal RC oscillator. See Figure 10: ST7FOXA0 clock
management block diagram on page 29 and Table 8.
If the internal RC is used with a supply operating range below 3.3 V, a division ratio of
at least 2 must be enabled in the RC prescaler.
Table 8.
Internal RC prescaler selection bits
CK2
CK1
CK0
fOSC
0
0
0
1
0
1
0
1
0
fRC/2
fRC/4
fRC/8
fRC/16
fRC
1
1
0
others
Bits 4:0 = Reserved, must be kept at their reset value.
6.5.6
Clock controller control/status register (CKCNTCSR)
Reset value: 0000 1001 (09h)
7
0
0
0
0
0
AWU_FLAG
Read/write
RC_FLAG
0
RC/AWU
Bits 7:4 = Reserved, must be kept cleared.
Bit 3 = AWU_FLAG AWU Selection
bit
This bit is set and cleared by hardware.
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
Bit 2 = RC_FLAG RC Selection
bit
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
40/123
ST7FOXA0
Supply, reset and clock management
Bit 0 = RC/AWU RC/AWU Selection
0: RC enabled
bit
1: AWU enabled (default value)
Table 9.
Addre
Clock register mapping and reset values
Register
label
ss
7
6
5
4
3
2
1
0
(Hex.)
-
0
-
0
-
0
-
0
-
0
-
0
RCCLAT RCCPGM
0030h
003Ah
003Bh
003Ch
003Dh
RCC_CSR
0
0
MCCSR
-
0
-
0
-
0
-
0
-
0
-
0
MCO
0
SMS
0
Reset Value
RCCRH
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
Reset Value
RCCRL
-
0
CR1
1
CR0
1
-
0
-
0
LVDRF
x
-
-
0
0
Reset Value
PSCR
CK2
0
CK1
0
CK0
0
-
0
-
0
-
0
-
-
1
1
Reset Value
AWU_
FLAG
1
RC_FLA
CKCNTCSR
Reset Value
-
0
-
0
-
0
-
0
-
0
RC/AWU
1
0051h
G
0
41/123
Power saving modes
ST7FOXA0
7
Power saving modes
7.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 16):
●
●
●
●
●
Slow
Wait (and Slow-Wait)
Active Halt
Auto wakeup From Halt (AWUFH)
Halt
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency (f
).
OSC
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 16. Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
POWER CONSUMPTION
42/123
ST7FOXA0
Power saving modes
7.2
Slow mode
This mode has two targets:
●
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f ) to the available supply voltage.
●
CPU
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note:
Slow-Wait mode is activated when entering Wait mode while the device is already in Slow
mode.
Figure 17. Slow mode clock transition
fOSC/32
fOSC
fCPU
fOSC
SMS
NORMAL RUN MODE
REQUEST
7.3
Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches
to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to Figure 18 for a description of the Wait mode flowchart.
43/123
Power saving modes
Figure 18. Wait mode flowchart
ST7FOXA0
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
I BIT
N
RESET
Y
N
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
I BIT
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
X
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
7.4
Active-halt and halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 10. Enabling/disabling active-halt and halt modes
LTCSR TBIE ATCSR OVFIE
ATCSRCK1 bit ATCSRCK0 bit
Meaning
bit
bit
0
0
0
1
x
x
0
1
x
1
x
x
1
x
0
0
x
1
x
1
Active-Halt mode disabled
Active-Halt mode enabled
44/123
ST7FOXA0
Power saving modes
7.4.1
Active-halt mode
Active-Halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when active halt mode is enabled.
The MCU can exit Active-Halt mode on reception of a Lite timer/ AT timer interrupt or a
Reset.
●
●
When exiting Active-Halt mode by means of a Reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the Reset vector which
woke it up (see Figure 20).
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see Figure 20).
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution:
As soon as Active-Halt is enabled, executing a HALT instruction while the Watchdog is
active does not generate a Reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 19. Active-halt timing overview
ACTIVE
HALT
256 CPU
RUN
RUN
CYCLE DELAY 1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt Enabled]
FETCH
VECTOR
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
45/123
Power saving modes
Figure 20. Active-halt mode flowchart
ST7FOXA0
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
HALT INSTRUCTION
(Active Halt enabled)
I BIT
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
7.4.2
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the HALT instruction when active halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (seeTable : ) or a
Reset. When exiting Halt mode by means of a Reset or an interrupt, the main oscillator is
immediately turned on and the 256 CPU cycle delay is used to stabilize it. After the start up
delay, the CPU resumes operation by servicing the interrupt or by fetching the Reset vector
which woke it up (see Figure 22).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog Reset (see Section 13.1: Option bytes for
more details).
46/123
ST7FOXA0
Power saving modes
Figure 21. Halt timing overview
256 CPU CYCLE
DELAY
RUN
HALT
RUN
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
[Active Halt disabled]
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 22. Halt mode flowchart
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WATCHDOG
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
Y
N
INTERRUPT 3)
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
I BIT
X 4)
256 CPU CLOCK CYCLE
DELAY 5)
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
I BITS
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table : for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
47/123
Power saving modes
ST7FOXA0
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●
●
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a Program Counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
7.5
Auto wakeup from halt mode
Auto wakeup from halt (AWUFH) mode is similar to Halt mode with the addition of a specific
internal RC oscillator for wakeup (Auto wakeup from Halt oscillator) which replaces the main
clock which was active before entering Halt mode. Compared to Active-Halt mode, AWUFH
has lower power consumption (the main clock is not kept running), but there is no accurate
real-time clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.
Figure 23. AWUFH mode block diagram
AWU RC
oscillator
to 8-bit timer Input Capture
fAWU_RC
AWUFH
interrupt
AWUFH
prescaler/1 .. 255
/64
divider
(ei0 source)
48/123
ST7FOXA0
Power saving modes
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (f ). Its frequency is divided by
AWU_RC
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
●
●
●
the AWUF flag is set by hardware,
an interrupt wakes-up the MCU from Halt mode,
the main oscillator is immediately turned on and the 256 CPU cycle delay is used to
stabilize it.
After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency f
and then calculating the right prescaler value.
AWU_RC
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects f to the Input Capture of the 8-bit Lite timer, allowing the
AWU_RC
f
to be measured using the main oscillator clock as a reference timebase.
AWU_RC
Similarities with halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
●
●
●
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 7.4: Active-halt and halt modes).
When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
●
The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog Reset.
Figure 24. AWUF halt timing diagram
tAWU
RUN MODE
HALT MODE
256 tCPU
RUN MODE
Clear
fCPU
fAWU_RC
by software
AWUFH interrupt
49/123
Power saving modes
Figure 25. AWUFH mode flowchart
ST7FOXA0
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ENABLE
WATCHDOG
DISABLE
0
WDGHALT 1)
1
AWU RC OSC
MAIN OSC
PERIPHERALS 2)
CPU
ON
OFF
OFF
OFF
10
WATCHDOG
RESET
I[1:0] BITS
N
RESET
Y
N
INTERRUPT 3)
AWU RC OSC
MAIN OSC
OFF
ON
Y
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
XX 4)
256 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
OFF
ON
ON
ON
I[1:0] BITS
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table : for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
50/123
ST7FOXA0
Power saving modes
7.5.1
7.5.2
Register description
AWUFH Control/Status Register (AWUCSR)
Reset value: 0000 0000 (00h)
7
0
AWU
F
0
0
0
0
0
AWUM
AWUEN
Read/Write
Bits 7:3 = Reserved
Bit 2 = AWUF Auto wakeup flag
This bit is set by hardware when the AWU module generates an interrupt and cleared
by software on reading AWUCSR. Writing to this bit does not change its value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1 = AWUM Auto wakeup Measurement
bit
This bit enables the AWU RC oscillator and connects its output to the Input Capture of
the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator
dispersion and then compensate this dispersion by providing the right value in the
AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 = AWUEN Auto wakeup From Halt Enabled
bit
This bit enables the Auto wakeup from halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
prescaler value. It is set and cleared by software.
0: AWUFH (Auto wakeup from Halt) mode disabled
1: AWUFH (Auto wakeup from Halt) mode enabled
Note:
Whatever the clock source, this bit should be set to enable the AWUFH mode once the
HALT instruction has been executed.
51/123
Power saving modes
ST7FOXA0
7.5.3
AWUFH Prescaler Register (AWUPR)
Reset value: 1111 1111 (FFh)
7
0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Read/Write
Bits 7:0= AWUPR[7:0] Auto wakeup Prescaler
These 8 bits define the AWUPR Dividing factor (see Table 11).
Table 11. Configuring the dividing factor
AWUPR[7:0]
Dividing factor
00h
01h
...
Forbidden
1
...
FEh
FFh
254
255
In AWU mode, the time during which the MCU stays in Halt mode, t
, is given by the
AWU
equation below. See also Figure 24 on page 49.
1
--------------------
tAWU = 64 × AWUPR ×
+ tRCSTRT
fAWURC
The AWUPR prescaler register can be programmed to modify the time during which the
MCU stays in Halt mode before waking up automatically.
Note:
If 00h is written to AWUPR, the AWUPR remains unchanged.
Table 12. AWU register mapping and reset values
Address Register
7
6
5
4
3
2
1
0
(Hex.)
label
AWUCSR
Reset
0048h
0
0
0
0
0
AWUF
AWUM
AWUEN
Value
AWUPR
Reset
Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
0049h
1
1
1
1
1
1
1
1
52/123
ST7FOXA0
I/O ports
8
I/O ports
8.1
8.2
Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.
Functional description
A Data register (DR) and a Data Direction register (DDR) are always associated with each
port. The Option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer to the Port
Configuration table for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit
x corresponding to pin x of the port.
Figure 26 shows the generic I/O block diagram.
8.2.1
Input modes
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: floating or pull-
up. Refer to I/O Port Implementation section for configuration.
Note:
1
2
Writing to the DR modifies the latch value but does not change the state of the input pin.
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control register (EICR) or the Miscellaneous register controls this
sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several I/O interrupt pins on the same interrupt vector
are selected simultaneously, they are logically combined. For this reason if one of the
interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
53/123
I/O ports
ST7FOXA0
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution:
In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
a) Set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b) Select rising edge
c) Enable the external interrupt through the OR register
d) Select the desired sensitivity if different from rising edge
e) Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
2. To disable an external interrupt:
a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b) Select falling edge
c) Disable the external interrupt through the OR register
d) Select rising edge
e) Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
8.2.2
Output modes
Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the
I/O through the latch. Reading the DR bits returns the previously stored value.
If an OR bit is available, different output modes can be selected by software: push-pull or
open-drain. Refer to I/O Port Implementation section for configuration.
Table 13. DR Value and output pin status
DR
Push-Pull
Open-Drain
0
1
VOL
VOH
VOL
Floating
54/123
ST7FOXA0
I/O ports
8.2.3
Alternate functions
Many ST7s I/Os have one or more alternate functions. These may include output signals
from, or input signals to, on-chip peripherals.Table 2 describes which peripheral signals can
be input/output to which ports.
A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the
on-chip peripheral as an output (enable bit in the peripheral’s control register). The
peripheral configures the I/O as an output and takes priority over standard I/O programming.
The I/O’s state is readable by addressing the corresponding I/O data register.
Configuring an I/O as floating enables alternate function input. It is not recommended to
configure an I/O as pull-up as this will increase current consumption. Before using an I/O as
an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.
Configure an I/O as input floating for an on-chip peripheral signal which can be input and
output.
Caution:
I/Os which can be configured as both an analog and digital alternate function need special
attention. The user must control the peripherals so that the signals do not arrive at the same
time on the same pin. If an external clock is used, only the clock alternate function should be
employed on that I/O pin and not the other alternate function.
Figure 26. I/O port general block diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
DD
DDR
OR
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration
table for device specific information.
55/123
I/O ports
ST7FOXA0
(1)
Table 14. I/O port mode options
Configuration mode
Diodes
Pull-Up
P-Buffer
to VDD
to VSS
Floating with/without Interrupt
Pull-up with Interrupt
Push-pull
Off
On
Input
Off
On
On
On
Off
Output
Off
Open Drain (logic level)
1. Off means implemented not activated, On means implemented and activated.
Table 15. ST7FOXA0 I/O port configuration
Hardware configuration
DR REGISTER ACCESS
W
R
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
To on-chip peripheral
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
COMBINATIONAL
LOGIC
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
PAD
R/W
DR
REGISTER
DATA BUS
DR REGISTER ACCESS
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
From on-chip peripheral
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
56/123
ST7FOXA0
I/O ports
8.2.4
Analog alternate function
Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled
by the ADC registers) switches the analog voltage present on the selected pin to the
common analog rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any I/O while conversion is in progress. Do not
have clocking pins located close to a selected analog pin.
Caution:
The analog input voltage level must be within the limits stated in the absolute maximum
ratings.
8.3
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific I/O port features such as ADC input or open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27.
Other transitions are potentially risky and should be avoided, since they may present
unwanted side-effects such as spurious interrupt generation.
Figure 27. Interrupt I/O port state transitions
01
00
10
11
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
8.4
8.5
Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8: I/O port
pin characteristics.
Low power modes
s
Table 16. Effect of low power modes on I/O ports
Mode
Description
No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
Wait
No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
Halt
57/123
I/O ports
ST7FOXA0
8.6
Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM
instruction).
Table 17. Description of interrupt events
Enable
Control bit
Exit from
Wait
Exit from
Halt
Interrupt Event
Event flag
External interrupt on selected
external event
DDRx
ORx
-
Yes
Yes
See application notes AN1045 software implementation of I2C bus master, and AN1048 -
software LCD driver
8.7
Device-specific I/O port configuration
The I/O port register configurations are summarized in Table 18.
Table 18. Port configuration
Input (DDR=0)
Output (DDR=1)
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
PA0:2, PA4:5 (1)
PA3 (2)
floating
-
pull-up interrupt (1)
-
open drain
open drain
push-pull
push-pull
Port A
1. IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in HALT and AWUFH modes. Refer
to 11.3.2: External Interrupt Control Register 2 (EICR2) on page 91.
2. After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0
and MUXCR1 registers. See Section 6.3.6: Multiplexed IO reset control register 1 (MUXCR1) on page 34
and Section 6.3.7: Multiplexed IO reset control register 0 (MUXCR0) on page 34
Table 19. I/O port register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
Reset
Value
MSB
0
LSB
0
0000h
0001h
0002h
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
PADDR
Reset
Value
MSB
0
LSB
0
PAOR
Reset
Value
MSB
0
LSB
0
58/123
ST7FOXA0
On-chip peripherals
9
On-chip peripherals
9.1
Lite Timer (LT)
9.1.1
Introduction
The Lite Timer can be used for general-purpose timing functions. It is based on a free-
running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input
capture register and watchdog function.
9.1.2
Main features
●
Real-time Clock
–
–
–
13-bit upcounter
1 ms or 2 ms timebase period (@ 8 MHz f
Maskable timebase interrupt
)
OSC
●
●
Input Capture
–
–
8-bit input capture register (LTICR)
Maskable interrupt with wakeup from Halt Mode capability
Watchdog
–
–
–
–
–
Enabled by hardware or software (configurable by option byte)
Optional reset on HALT instruction (configurable by option byte)
Automatically resets the device unless disable bit is refreshed
Software reset (Forced Watchdog reset)
Watchdog reset status flag
59/123
On-chip peripherals
Figure 28. Lite timer block diagram
ST7FOXA0
f
LTIMER
To 12-bit AT TImer
f
WDG
WATCHDOG
WATCHDOG RESET
f
OSC
/2
1
0
Timebase
1 or 2 ms
(@ 8 MHz
13-bit UPCOUNTER
f
LTIMER
f
)
OSC
LTICR
8 MSB
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR
WDG
RF
ICIE
7
ICF
TB
TBIE
TBF
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
9.1.3
9.1.4
Functional description
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of f . A counter overflow event occurs when the
counter rolls over from 1F3Fh to 00h. If f
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR register.
OSC
= 8 MHz, then the time period between two
OSC
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
Watchdog
The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2 ms
(@ f
= 8 MHz), after which it then generates a reset.
osc
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after t . This means that software must write to the WDGD bit at
WDG
regular intervals to prevent a watchdog reset occurring. Refer to Figure 29.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2 ms, because this period is counted starting from reset. Moreover, if a 2 ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog
immediately after reset.
A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
60/123
ST7FOXA0
Caution:
On-chip peripherals
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
Once the WDGRF bit is set, if the watchdog is enabled, the microcontoller is immediatly
reset, even if the WDGD bit is set by software.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the Option Byte description in the "device configuration and ordering information"
section.
Using Halt Mode with the Watchdog (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
Timer stops counting and is no longer able to generate a Watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Figure 29. Watchdog timing diagram
HARDWARE CLEARS
WDGD BIT
t
WDG
(2 ms @ 8 MHz f
)
OSC
f
WDG
WDGD BIT
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
9.1.5
Input capture
The 8-bit input capture register is used to latch the free-running upcounter after a rising or
falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and
the LTICR register contains the MSB of the free-running upcounter. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
An overflow can be detected through the timebase event. This overflow occurs when the
counter rolls over from 1F3Fh to 00h, that is, from F9h to 00h if only the 8 MSB of the LTIC
counter are taken into account. In this case, the TB bit in the LTCSR register must be reset
to detect all overflows.
The LTICR is a read only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
61/123
On-chip peripherals
ST7FOXA0
9.1.6
Low power modes
Table 20. Effect on Lite timer
Mode
Description
Wait
Active-halt
Halt
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
9.1.7
Interrupts
Table 21. Interrupt events
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-Halt
Event
Interrupt Event
Flag
Timebase event
IC Event
TBF
ICF
TBIE
ICIE
Yes
Yes
No
No
Yes
No
Note:
The TBF and ICF interrupt events are connected to separate interrupt vectors (see
Interrupts chapter). They generate an interrupt if the enable bit is set in the LTCSR register
and the interrupt mask in the CC register is reset (RIM instruction).
Figure 30. Input capture timing diagram
125ns
(@ 8MHz f
)
OSC
f
CPU
f
OSC
CLEARED
BY S/W
READING
LTIC REGISTER
13-bit COUNTER
LTIC PIN
0001h
0002h
0003h
0004h
0005h
0006h
0007h
ICF FLAG
07h
LTICR REGISTER
xxh
04h
t
9.1.8
Register description
Lite Timer Control/Status Register (LTCSR)
Reset Value: 0000 0x00 (0xh)
7
0
ICIE
ICF
TB
TBIE
TBF
WDGRF
WDGE
WDGD
Read/Write
62/123
ST7FOXA0
On-chip peripherals
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software by reading the LTICR register. Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note:
After an MCU reset, software must initialize the ICF bit by reading the LTICR register
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
* 8000 (1 ms @ 8 MHz)
* 16000 (2 ms @ 8 MHz)
OSC
OSC
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 = TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to force a watchdog reset. It is set by
hardware when a watchdog reset occurs. It can be cleared by software after a read
access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hardware at the end of each t
0: Watchdog reset not delayed
period.
WDG
1: Watchdog reset delayed
63/123
On-chip peripherals
ST7FOXA0
Lite Timer Input Capture Register (LTICR)
Reset Value: 0000 0000 (00h)
7
0
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Read only
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in
the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or
falling edge occurs on the LTIC pin.
Table 22. Lite timer register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR
Reset Value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
WDGRF WDGE WDGD
0B
0C
x
0
0
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
64/123
ST7FOXA0
On-chip peripherals
9.2
12-bit Autoreload Timer (AT)
9.2.1
Introduction
The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based
on a free-running 12-bit upcounter with a PWM output channel.
9.2.2
Main Features
●
●
●
●
12-bit upcounter with 12-bit autoreload register (ATR)
Maskable overflow interrupt
PWM signal generator
Frequency range 2KHz-4MHz (@ 8 MHz f
)
CPU
–
–
–
Programmable duty-cycle
Polarity control
Maskable Compare interrupt
●
Output Compare Function
Figure 31. Block diagram
OVF INTERRUPT
REQUEST
ATCSR
7
0
0
0
0
CK1 CK0 OVF OVFIECMPIE
CMP INTERRUPT
REQUEST
CMPF0
f
LTIMER
(1 ms timebase
@ 8MHz)
f
COUNTER
12-BIT UPCOUNTER
CNTR
ATR
Update on OVF Event
f
CPU
12-BIT AUTORELOAD VALUE
OE0 bit
DCR0L
DCR0H
CMPF0 bit
OE0 bit
OP0 bit
Preload
Preload
0
1
POL-
ARITY
COMP-
PARE
f
PWM
PWM0
on OVF Event
IF OE0=1
12-BIT DUTY CYCLE VALUE (shadow)
9.2.3
Functional description
PWM Mode
This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
Note:
CMPF0 is available in PWM mode (see PWM0CSR description on page 71).
65/123
On-chip peripherals
ST7FOXA0
PWM Frequency and Duty Cycle
The PWM signal frequency (f
) is controlled by the counter period and the ATR register
PWM
value.
f
= f / (4096 - ATR)
COUNTER
PWM
Following the above formula, if f
is 8 MHz, the maximum value of f
is 4 Mhz (ATR
CPU
PWM
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
Note:
The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
must be greater than the contents of the ATR register.
The polarity bit can be used to invert the output signal.
The maximum available resolution for the PWM0 duty cycle is:
Resolution = 1 / (4096 - ATR)
Note:
To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by
changing the polarity.
Caution:
As soon as the DCR0H is written, the compare function is disabled and will start only when
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
DCRx register should be updated just before an OVF event, in order not to miss a compare
event and to have the right signal applied on the PWM output.
Figure 32. PWM function
4095
DUTY CYCLE
REGISTER
(DCR0)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
66/123
ST7FOXA0
On-chip peripherals
Figure 33. PWM Signal example
f
COUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
t
Output Compare Mode
To use this function, the OE bit must be 0, otherwise the compare is done with the shadow
register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded immediately (without waiting for an OVF
event).
The DCR0H must be written first, the output compare function starts only when the DCR0L
value is written.
When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L
registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is
generated if the CMPIE bit is set.
Note:
The output compare function is only available for DCRx values other than 0 (reset value).
Caution:
At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value
has not yet been written (in this case, the shadow register will contain the new DCR0H value
and the old DCR0L value), then:
- If OE=1 (PWM mode): the compare is done between the timer counter and the shadow
register (and not DCRx)
- if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There
is no PWM signal. The compare between DCRx or the shadow register and the timer
counter is locked until DCR0L is written.
67/123
On-chip peripherals
ST7FOXA0
9.2.4
Low power modes
Mode
Description
Slow
Wait
The input frequency is divided by 32
No effect on AT timer
Active-Halt
Halt
AT timer halted except if CK0=1, CK1=0 and OVFIE=1
AT timer halted
9.2.5
Interrupts
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-Halt
Event
Flag
Interrupt Event 1)
Overflow Event
CMP Event
OVF
OVFIE
CMPIE
Yes
Yes
No
No
Yes2)
No
CMPFx
Note:
1
2
The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt
mask in the CC register is reset (RIM instruction).
only if CK0=1 and CK1=0
9.2.6
Register description
TImer Control Status Register (ATCSR)
Reset Value: 0000 0000 (00h)
7
0
0
0
0
CK1
CK0
OVF
OVFIE
CMPIE
Read/Write
Bits 7:5 = Reserved, must be kept cleared.
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset. They
select the clock frequency of the counter.
Table 23. Counter clock selection
Counter Clock Selection
CK1
CK0
OFF
0
0
1
1
0
1
0
1
fLTIMER (1 ms timebase @ 8 MHz)
fCPU
Reserved
68/123
ST7FOXA0
On-chip peripherals
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
Caution:
When set, the OVF bit stays high for 1 f
cycle (up to 1ms depending on the clock
COUNTER
selection) after it has been cleared by software.
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by hardware after a reset. It allows to mask
the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
Counter register high (CNTRH)
Reset Value: 0000 0000 (00h)
15
0
8
0
0
0
CN11
Read only
CN10
CN9
CN8
Counter register low (CNTRL)
Reset value: 0000 0000 (00h)
7
0
CN7
CN6
CN5
CN4
CN3
CN2
CN1
CN0
Read only
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTRH can be incremented between the two read operations and to have an accurate
result when f
are read.
=f
, special care must be taken when CNTRL values close to FFh
timer CPU
When a counter overflow occurs, the counter restarts from the value specified in the
ATR register.
69/123
On-chip peripherals
ST7FOXA0
Auto reload register high (ATRH)
Reset value: 0000 0000 (00h)
15
8
0
0
0
0
ATR11
ATR10
ATR9
ATR8
Read/Write
Auto reload register low (ATRL)
Reset value: 0000 0000 (00h)
7
0
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Read/Write
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by software. The ATR register value is
automatically loaded into the upcounter when an overflow occurs. The register value is
used to set the PWM frequency.
PWM0 duty cycle register high (DCR0H)
Reset value: 0000 0000 (00h)
15
0
8
0
0
0
DCR11
DCR10
DCR9
DCR8
Read/Write
PWM0 duty cycle register low (DCR0L)
Reset value: 0000 0000 (00h)
7
0
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
Read/Write
70/123
ST7FOXA0
On-chip peripherals
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty
cycle of the PWM0 output signal (see Figure 32). In Output Compare mode, (OE0=0 in
the PWMCR register) they define the value to be compared with the 12-bit upcounter
value.
PWM0 control/status register (PWM0CSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
OP0
CMPF0
Read/Write
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = OP0 PWM0 Output Polarity.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software by reading the PWM0CSR register.
It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
0
OE0
Read/Write
Bits 7:1 = Reserved, must be kept cleared.
Bit 0 = OE0 PWM0 Output enable.
71/123
On-chip peripherals
This bit is set and cleared by software.
ST7FOXA0
0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)
1: PWM0 output enabled
Table 24. Register map and reset values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0D
0E
0F
10
11
12
13
17
18
0
0
0
0
0
0
CNTRH
Reset Value
CN11
0
CN10
0
CN9
0
CN8
0
0
CNTRL
Reset Value
CN7
0
CN6
0
CN5
0
CN4
0
CN3
0
CN2
0
CN1
0
CN0
0
ATRH
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP
0
CMPF0
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
72/123
ST7FOXA0
On-chip peripherals
9.3
10-bit A/D converter (ADC)
9.3.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 5
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 5 different sources.
The result of the conversion is stored in a 10-bit Data register. The A/D converter is
controlled through a Control/Status register.
9.3.2
Main features
●
●
●
●
●
●
10-bit conversion
Up to 5 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 34.
9.3.3
Functional description
Analog power supply
V
and V
are the high and low level reference voltage pins. In some devices (refer to
SSA
DDA
device pin out description) they are internally connected to the V and V pins.
DD
SS
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
73/123
On-chip peripherals
Figure 34. ADC block diagram
ST7FOXA0
DIV 4
1
0
f
f
ADC
CPU
DIV 2
0
1
SLOW
bit
EOC SPEEDADON
0
CH2 CH1 CH0
ADCCSR
4
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
ANALOG
MUX
AINx
C
ADC
ADCDRH
D9 D8
D7 D6 D5 D4 D3 D2
ADCDRL
0
0
0
0
0
SLOW
D1
D0
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (V ) is greater than V
(high-level voltage reference) then the
AIN
DDA
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (V ) is lower than V
(low-level voltage reference) then the
SSA
AIN
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
R
is the maximum recommended impedance for an analog input signal. If the impedance
AIN
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
74/123
ST7FOXA0
On-chip peripherals
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see Section 8:
I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on,
the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
The EOC bit is set by hardware.
●
The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRH. This clears EOC automatically.
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[2:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
9.3.4
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 25. Effect of low power modes on the A/D converter
Mode
Description
Wait
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
Halt
9.3.5
Interrupts
None.
75/123
On-chip peripherals
ST7FOXA0
9.3.6
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
0
EOC
SPEED
ADON
0
0
CH2
CH1
CH0
Read only
Read/write
Bit 7 = EOC End of Conversion bit
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection bit
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description
(ADCDRL register).
Bit 5 = ADON A/D Converter on bit
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 4:3 = Reserved, must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits select the analog input to convert. They are set and cleared by software.
Table 26. Channel selection using CH[2:0]
Channel Pin(1)
CH2
CH1
CH0
AIN0
AIN1
AIN2
AIN3
AIN4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1. The number of channels is device dependent. Refer to the device pinout description.
Data register High (ADCDRH)
Reset value: xxxx xxxx (xxh)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
Read only
76/123
ST7FOXA0
On-chip peripherals
Bits 7:0 = D[9:2] MSB of Analog Converted Value
ADC Control/data register Low (ADCDRL)
Reset value: 0000 00xx (0xh)
7
0
0
0
0
0
SLOW
Read/write
0
D1
D0
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode bit
This bit is set and cleared by software. It is used together with the SPEED bit in the
ADCCSR register to configure the ADC clock speed as shown on the table below.
Table 27. Configuring the ADC clock speed
(1)
fADC
SLOW
SPEED
fCPU/2
0
0
1
0
1
x
fCPU
fCPU/4
1. The maximum allowed value of fADC is 4 MHz (see Section 12.10 on page 108)
Bits 1:0 = D[1:0] LSB of Analog Converted value
Table 28. ADC register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC SPEED ADON
0
0
0
0
CH2
0
CH1
0
CH0
0
0036h
0037h
0038h
0
0
0
ADCDRH
Reset Value
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
ADCDRL
Reset Value
0
0
0
0
0
0
SLOW
0
D1
x
D0
x
0
0
77/123
Instruction set
ST7FOXA0
10
Instruction set
10.1
ST7 addressing modes
The ST7 core features 17 different addressing modes which can be classified in seven main
groups:
Table 29. Description of addressing modes
Addressing mode
Example
Inherent
Immediate
Direct
nop
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 30. ST7 addressing mode overview
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
ld A,$1000
Direct
Direct
00..FF
Long
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Direct
Direct
ld A,($10,X)
00..1FE
0000..FFFF
00..FF
+ 1
+ 2
+ 2
+ 2
+ 2
Indexed ld A,($1000,X)
ld A,[$10]
Indirect
Indirect
Indirect
00..FF
00..FF
00..FF
byte
word
byte
ld A,[$10.w]
0000..FFFF
00..1FE
Indexed
ld A,([$10],X)
78/123
ST7FOXA0
Instruction set
Table 30. ST7 addressing mode overview (continued)
Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Mode
Syntax
ld
Long
Indirect
Direct
Indexed
0000..FFFF
00..FF
word
+ 2
+ 1
+ 2
A,([$10.w],X)
PC-
Relative
Relative
jrne loop
jrne [$10]
128/PC+127(1)
PC-
Indirect
00..FF
00..FF
byte
byte
128/PC+127(1)
Bit
Bit
Direct
bset $10,#7
00..FF
00..FF
+ 1
+ 2
Indirect
bset [$10],#7
btjt
$10,#7,skip
Bit
Bit
Direct
Relative
Relative
00..FF
00..FF
+ 2
+ 3
btjt
Indirect
00..FF
byte
[$10],#7,skip
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
10.1.1
Inherent mode
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 31. Instructions supporting inherent addressing mode
Instruction
Function
NOP
TRAP
WFI
No operation
S/W interrupt
Wait for interrupt (low power mode)
Halt oscillator (lowest power mode)
Subroutine return
HALT
RET
IRET
Interrupt subroutine return
Set interrupt mask
Reset interrupt mask
Set carry flag
SIM
RIM
SCF
RCF
Reset carry flag
RSP
Reset stack pointer
Load
LD
CLR
Clear
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/decrement
Test negative or zero
1 or 2 complement
CPL, NEG
79/123
Instruction set
ST7FOXA0
Table 31. Instructions supporting inherent addressing mode (continued)
Instruction
Function
MUL
SLL, SRL, SRA, RLC, RRC
SWAP
Byte multiplication
Shift and rotate operations
Swap nibbles
10.1.2
Immediate mode
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
Imm
Table 32. Instructions supporting inherent immediate addressing mode
Immediate Instruction
Function
LD
CP
Load
Compare
BCP
Bit compare
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical operations
Arithmetic operations
10.1.3
Direct modes
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short) addressing mode
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
10.1.4
Indexed modes (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (No Offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
80/123
ST7FOXA0
Instruction set
Indexed mode (Long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
10.1.5
Indirect modes (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect mode (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect mode (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
10.1.6
Indirect indexed modes (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed mode (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed mode (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 33. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions
Function
Long and short instructions
LD
CP
Load
Compare
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Logical operations
Arithmetic addition/subtraction operations
Bit compare
81/123
Instruction set
ST7FOXA0
Table 33. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes (continued)
Instructions
Function
Short instructions only
CLR
INC, DEC
Clear
Increment/decrement
Test negative or zero
1 or 2 complement
Bit operations
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
SLL, SRL, SRA, RLC, RRC
SWAP
Bit test and jump operations
Shift and rotate operations
Swap nibbles
CALL, JP
Call or jump subroutine
10.1.7
Relative modes (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 34. Instructions supporting relative modes
Available Relative Direct/Indirect instructions
Function
JRxx
Conditional jump
Call relative
CALLR
The relative addressing mode consists of two submodes:
Relative mode (Direct)
The offset follows the opcode.
Relative mode (Indirect)
The offset is defined in memory, of which the address follows the opcode.
82/123
ST7FOXA0
Instruction set
10.2
Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 35. ST7 instruction set
Load and Transfer
Stack operation
LD
CLR
PUSH POP
RSP
Increment/decrement
Compare and tests
INC
CP
DEC
TNZ
OR
BCP
Logical operations
AND
XOR CPL NEG
Bit operation
BSET BRES
BTJT BTJF
Conditional bit test and branch
Arithmetic operations
Shift and rotate
ADC
SLL
ADD
SRL
JRT
SUB SBC MUL
SRA RLC RRC SWAP SLA
Unconditional jump or call
Conditional branch
JRA
JRF
JP
CALL CALLR NOP RET
JRxx
TRAP
SIM
Interruption management
Condition Code Flag modification
WFI
RIM
HALT IRET
SCF RCF
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes by:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
83/123
Instruction set
ST7FOXA0
10.2.1
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented: a reset is generated if the code to be
executed does not correspond to any opcode or prebyte value. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
I
Table 36. Illegal opcode detection
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
ADD
AND
BCP
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
CP
Add with Carry
Addition
A = A + M + C
A = A + M
A
A
M
M
M
M
H
H
N
N
N
N
Z
Z
Z
Z
C
C
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
JRH
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
H = 1 ?
H = 0 ?
I = 1 ?
I = 0 ?
N = 1 ?
JRNH
JRM
JRNM
JRMI
Jump if H = 0
Jump if I = 1
Jump if I = 0
Jump if N = 1 (minus)
84/123
ST7FOXA0
Instruction set
Table 36. Illegal opcode detection (continued)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
JRPL
JREQ
JRNE
JRC
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
JRUGE
JRUGT
JRULE
LD
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
Unsigned <=
dst <= src
X,A = X * A
neg $10
Jump if C = 0
Jump if (C + Z = 0)
Jump if (C + Z = 1)
Load
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
N
N
N
N
Z
Z
Z
Z
MUL
Multiply
0
0
NEG
Negate (2's compl)
No Operation
C
NOP
OR
OR operation
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
M
POP
Pop from the Stack
reg
CC
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4]<=>Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
85/123
Instruction set
ST7FOXA0
Table 36. Illegal opcode detection (continued)
Mnemo
Description
Function/Example
Dst
Src
H
I
N
Z
C
WFI
Wait for Interrupt
Exclusive OR
0
XOR
A = A XOR M
A
M
N
Z
86/123
ST7FOXA0
Interrupts
11
Interrupts
The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in Figure 35.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
external interrupts subsection).
Note:
After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●
●
●
●
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table
for vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note:
As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first (see the Interrupt Mapping table).
Interrupts and low power mode
All interrupts allow the processor to leave the WAIT low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the HALT low power mode
(refer to the “Exit from HALT” column in the Interrupt Mapping table).
11.1
11.2
Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in Figure 35.
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
HALT low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
87/123
Interrupts
Caution:
ST7FOXA0
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
11.3
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
The I bit of the CC register is cleared.
●
The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●
Writing “0” to the corresponding bit in the status register or
●
Access to the status register while the flag is set followed by a read or write of an
associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 35. Interrupt processing flowchart
FROM RESET
N
I BIT SET?
N
Y
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
88/123
ST7FOXA0
Interrupts
Table 37. ST7FOXA0 interrupt mapping
Source
Exit
from
HALT
Register
Label
Priority
Order
Address
Vector
N°
Description
Block
RESET
TRAP
AWU
ei0
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
N/A
Software Interrupt
Auto wakeup Interrupt
External Interrupt 0
External Interrupt 1
External Interrupt 2 (2)
Not used
0
1
AWUCSR
yes (1) FFFAh-FFFBh
FFF8h-FFF9h
Highest
Priority
2
ei1
yes
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
3 (2)
ei2 (2)
4
N/A
no
5
ei3
External Interrupt 3
External Interrupt 4 (3)
Not used
yes
6 (3)
ei4 (3)
no (3) FFEEh-FFEFh
7
no
no
FFECh-FFEDh
FFEAh-FFEBh
AT TIMER Output Compare PWMxCSR or
8
9
Interrupt
ATCSR
AT TIMER
AT TIMER Overflow Interrupt
ATCSR
yes (4) FFE8h-FFE9h
Lowest
Priority
LITE TIMER Input Capture
Interrupt
10
LTCSR
LTCSR
no
FFE6h-FFE7h
LITE
TIMER
11
12
13
LITE TIMER RTC1 Interrupt
Not used
yes (4) FFE4h-FFE5h
no
no
FFE2h-FFE3h
FFE0h-FFE1h
Not used
1. This interrupt exits the MCU from “Auto wakeup from HALT” mode only.
2. Whatever the sensitivity configuration, this interrupt cannot exit the MCU from HALT, ACTIVE-HALT and AWUFH modes
when a falling edge occurs.
3. This interrupt exits the MCU from “WAIT” and “ACTIVE-HALT” modes only. Moreover IS4[1:0] =01 is the only safe
configuration to avoid spurious interrupt in Halt and AWUFH modes.
4. These interrupts exit the MCU from “ACTIVE-HALT” mode only.
89/123
Interrupts
ST7FOXA0
11.3.1
External Interrupt Control Register 1 (EICR1)
Reset value: 0000 0000 (00h)
7
0
0
0
IS21
IS20
IS11
IS10
IS01
IS00
Read/write
Bits 7:6 = Reserved, must be kept cleared.
Bits 5:4 = IS2[1:0] ei2 sensitivity
bits
These bits define the interrupt sensitivity for ei2 according to Table ?.
Bits 3:2 = IS1[1:0] ei1 sensitivity
bits
These bits define the interrupt sensitivity for ei1 according to Table ?.
Bits 1:0 = IS0[1:0] ei0 sensitivity
bits
These bits define the interrupt sensitivity for ei0 according to Table ?.
Note:
1
2
These 8 bits can be written only when the I bit in the CC register is set.
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
3
Whatever the sensitivity configuration, ei2 cannot exit the MCU from HALT, ACTIVE-HALt
and AWUFH modes when a falling edge occurs.
ISx1
ISx0
External interrupt sensitivity
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
90/123
ST7FOXA0
Interrupts
11.3.2
External Interrupt Control Register 2 (EICR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
IS41
Read/write
IS40
IS31
IS30
Bits 7:4 = Reserved, must be kept cleared.
Bits 3:2 = IS4[1:0] ei4 sensitivity
bits
These bits define the interrupt sensitivity for ei1 according to Table ?.
Bits 1:0 = IS0[1:0] ei3 sensitivity
bits
These bits define the interrupt sensitivity for ei0 according to Table ?.
Note:
1
2
These 8 bits can be written only when the I bit in the CC register is set.
Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
3
IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH
modes.
Table 38. Interrupt register mapping and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
EICR1
-
0
-
0
IS21
0
IS20
0
IS11
0
IS10
0
IS01
0
IS00
0
0037h
003Dh
Reset Value
EICR2
-
0
-
0
-
0
-
0
IS41
0
IS40
0
IS31
0
IS30
0
Reset Value
91/123
Electrical characteristics
ST7FOXA0
12
Electrical characteristics
12.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
12.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
12.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the
A
DD
4.5 V≤ V ≤ 5.5 V voltage range). They are given only as design guidelines and are not
DD
tested.
12.1.3
12.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 36.
Figure 36. Pin loading conditions
ST7 PIN
C
L
12.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 37.
92/123
ST7FOXA0
Electrical characteristics
Figure 37. Pin input voltage
ST7 PIN
V
IN
12.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 39. Voltage characteristics
Symbol
DD - VSS
VIN
Ratings
Maximum value
Unit
V
Supply voltage
7.0
V
Input voltage on any pin(1)(2)
VSS-0.3 to VDD+0.3
Electrostatic discharge voltage (Human Body
model)
VESD(HBM)
VESD(CDM)
see Section 12.7.3 on page
102
Electrostatic discharge voltage (Charge Device
model)
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted Program Counter). To guarantee safe operation, this connection has to be done through a pull-
up or pull-down resistor (typical: 4.7 kΩ for RESET, 10 kΩ for I/Os). Unused I/O pins must be tied in the
same way to VDD or VSS according to their reset configuration.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
93/123
Electrical characteristics
ST7FOXA0
Unit
Table 40. Current characteristics
Symbol
Ratings
Maximum value
IVDD
IVSS
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
75
150
Output current sunk by any standard I/O and control
pin
20
IIO
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
40
- 25
5
mA
(2)(3)
IINJ(PIN)
Injected current on OSC1/CLKIN and OSC2 pins
Injected current on any other pin(4)
5
5
Total injected current (sum of all I/O and control
pins)(4)
(2)
ΣIINJ(PIN)
20
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 41. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-65 to +150
°C
Maximum junction temperature (see Table 66: Thermal characteristics on
page 121)
TJ
94/123
ST7FOXA0
Electrical characteristics
12.3
Operating conditions
12.3.1
General operating conditions
T = -40 to +85 °C unless otherwise specified.
A
Table 42. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
fCPU
Supply voltage
fCPU = 8 MHz max.
4.5
5.5
V
CPU clock frequency
4.5 V≤ VDD≤5.5 V
up to 8
MHz
12.3.2
Operating conditions with Low Voltage Detector (LVD)
T = -40 to 85 °C unless otherwise specified.
A
,
Table 43. Operating characteristics with LVD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
(VDD rise)
VIT+
3.9
4.2
4.5
(LVD)
V
Reset generation threshold
(VDD fall)
VIT-
3.7
2
4.0
4.3
(LVD)
Vhys
VtPOR
LVD voltage threshold hysteresis
VDD rise time rate(1)(2)
VIT+(LVD)-VIT-
150
mV
µs/V
µA
(LVD)
IDD(LVD)
LVD current consumption
VDD = 5 V
80
140
1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset release. When the VDD slope is outside these values, the LVD may not release properly the
reset of the MCU.
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to
circuit example in Figure 39 on page 106.
95/123
Electrical characteristics
ST7FOXA0
12.3.3
Internal RC oscillator
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the V and V pins as close as possible to the ST7
DD
SS
device
Internal RC oscillator calibrated at 5.0 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 44. Internal RC oscillator characteristics (5.0 V calibration)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
RCCR = FF (reset value),
TA = 25 °C, VDD = 5 V
4.4
Internal RC oscillator
frequency
fRC
MHz
RCCR=RCCR0(1)
,
8
6
7
TA = 25 °C, VDD = 5 V
RC trimming
granularity
fG(RC)
ACCRC
tsu(RC)
TA = 25 °C, VDD = 5 V
kHz
%
TA = 25 °C, VDD = 5 V (2)
without user calibration
TA = 25 °C, VDD = 4.5 to 5.5 V (2)
with user calibration
-2
2
4
%
%
Accuracy of Internal
RC oscillator with
RCCR=RCCR01)
TA= 0 to +85 °C,
VDD = 4.5 to 5.5 V(2)
with user calibration
-2.5
TA = -40 to 0 °C,
VDD = 4.5 to 5.5 V(2)
with user calibration
-4
2.5
%
RC oscillator setup
time
TA = 25 °C, VDD = 5 V
4 (3)
µs
1. See Section 6.1.1: Internal RC oscillator
2. Guaranteed by characterization
3. Not tested in production
96/123
ST7FOXA0
Electrical characteristics
12.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
12.4.1
Supply current
T = -40 to +85 °C unless otherwise specified.
A
Table 45. Supply current characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
fCPU = 4 MHz
2.5
5.0
1.1
2
4.5(2)
Supply current in Run mode(1)
fCPU = 8 MHz
9
mA
fCPU = 4 MHz
fCPU = 8 MHz
2(2)
3.5
Supply current in Wait mode(3)
IDD
Supply current in Slow mode(4)
Supply current in Slow-Wait mode(5)
Supply current in AWUFH mode(6)(7)
Supply current in Active Halt mode
Supply current in Halt mode(8)
fCPU/32 = 250 kHz
fCPU/32 = 250 kHz
550
450
50
950
750
100(2)
250
5
µA
120
0.5
TA = 85 °C
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. Data based on characterization, not tested in production.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
8. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
97/123
Electrical characteristics
ST7FOXA0
12.4.2
On-chip peripherals
Table 46. On-chip peripheral characteristics
Symbol
Parameter
Conditions
Typ
Unit
IDD(AT)
12-bit Auto-Reload timer supply current(1)
ADC supply current when converting(2)
fCPU=8 MHz
fADC=4 MHz
VDD=5.0 V
VDD=5.0 V
30
µA
µA
IDD(ADC)
750
1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer
running in PWM mode at fcpu= 8 MHz.
2. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
12.5
Clock and timing characteristics
Subject to general operating conditions for V , f
, and T .
A
DD OSC
Table 47. General timings
Symbol
Parameter(1)
Conditions
Min
Typ(2)
Max
Unit
2
3
12
1500
22
tCPU
ns
tc(INST)
Instruction cycle time
fCPU = 8 MHz
fCPU = 8 MHz
250
10
375
Interrupt reaction time(3)
tv(IT) = ∆tc(INST) + 10
tCPU
µs
tv(IT)
1.25
2.75
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
12.5.1
Auto wakeup from Halt oscillator (AWU)
Table 48. AWU from Halt characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
AWU Oscillator
Frequency
fAWU
16
32
64
kHz
AWU Oscillator startup
time
tRCSRT
50
µs
1. Guaranteed by Design. Not tested in production.
98/123
ST7FOXA0
Electrical characteristics
12.6
Memory characteristics
T = -40 °C to 85 °C, unless otherwise specified.
A
Table 49. RAM and hardware registers characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM
Data retention mode(1)
Halt mode (or Reset)
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
Table 50. Flash program memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Refer to operating
range of VDD with TA,
Section 12.3.1 on
page 95
Operating voltage for Flash
Write/Erase
VDD
4.5
5.5
V
Programming time for 1~32
bytes(1)
TA=−40 to +85 °C
5
10
ms
tprog
Programming time for 4 kbytes
Data retention(2)
TA=+25 °C
TA=+55 °C(3)
TA=+25 °C
0.64 1.28
s
tRET
NRW
20
years
cycles
Write erase cycles
1k
Read / Write / Erase
modes
2.6
mA
fCPU = 8 MHz,
VDD = 5.5 V
IDD
Supply current(4)
No Read/No Write
mode
100
µA
µA
Power down mode /
Halt
0
0.1
1. Up to 32 bytes can be programmed at a time.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the TA decreases.
4. Guaranteed by Design. Not tested in production.
99/123
Electrical characteristics
ST7FOXA0
12.7
EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test
SS
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
●
Software recommendations
The software flowchart must include the management of runaway conditions such as:
–
–
–
Corrupted Program Counter
Unexpected reset
Critical Data corruption (control registers...)
●
Prequalification trials
Most of the common failures (unexpected reset and Program Counter corruption) can
be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can
be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 51. EMS test results
Level/
Class
Symbol
Parameter
Conditions
Voltage limits to be applied on any I/O pin VDD=5 V, TA=+25 °C, fOSC=8 MHz
VFESD
2B
3B
to induce a functional disturbance
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be
applied through 100pF on VDD and VSS
pins to induce a functional disturbance
VDD=5 V, TA=+25 °C, fOSC=8 MHz
VFFTB
conforms to IEC 1000-4-4
100/123
ST7FOXA0
Electrical characteristics
12.7.2
EMI (Electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
(1)
Table 52. ST7FOXA0 EMI characteristics
Max vs.
[fOSC/fCPU
Monitored
]
Symbol Parameter
Conditions
Unit
Frequency Band
-/8MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
20
20
13
2.5
VDD=5 V, TA=+25 °C,
SO8 package,
conforming to SAE J
1752/3
dBµV
SEMI
Peak level
-
1. Data based on characterization results, not tested in production.
101/123
Electrical characteristics
ST7FOXA0
12.7.3
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: Human Body model and Machine model. This test conforms to the
JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Table 53. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value(1)
Electrostatic discharge voltage (Human Body
model)
VESD(HBM)
VESD(CDM)
TA=+25 °C
TA=+25 °C
4000
V
Electrostatic discharge voltage (Charge Device
model)
500
1. Data based on characterization results, not tested in production.
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance.
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 54. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +85 °C
A
102/123
ST7FOXA0
Electrical characteristics
12.8
I/O port pin characteristics
12.8.1
General characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Table 55. General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
VSS - 0.3
0.7VDD
0.3VDD
V
VDD+0.3
Schmitt trigger voltage
hysteresis(1)
Vhys
IL
400
400
mV
Input leakage current
VSS ≤ VIN ≤ VDD
1
Static current consumption
induced by each floating
input pin(2)
µA
IS
Floating input mode
Weak pull-up equivalent
resistor(3)
RPU
CIO
VIN=VSS
VDD=5 V
100
120
5
140
kΩ
I/O pin capacitance
pF
Output high to low level fall
time(1)
tf(IO)out
25
CL= 50 pF
Between 10% and 90%
ns
Output low to high level rise
time(1)
tr(IO)out
tw(IT)in
25
External interrupt pulse
time(4)
1
tCPU
1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 38). Static peak current value taken at a fixed VIN value,
based on design simulation and technology characteristics, not tested in production. This value depends on VDD and
temperature values.
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 38. Two typical applications with unused I/O pin
VDD
ST7XXX
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
1. During normal operation the ICCCLK pin must be pulled-up, internally or externally (external pull-up of 10k
mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset.
2. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
103/123
Electrical characteristics
ST7FOXA0
12.8.2
Output driving current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Table 56. Output driving current characteristics
Symbol
Parameter
Conditions
Min
Max
1.2
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
IIO=+5 mA, TA≤ 85°C
IIO=+2mA, TA≤ 85°C
IIO=+20mA,TA≤ 85°C
IIO=+8mATA≤ 85°C
0.4
(1)
VOL
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
1.3
V
0.75
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
IIO=-5mA,TA≤ 85°C VDD-1.5
IIO=-2mATA≤ 85°C VDD-0.8
(2)
VOH
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 40. and the sum of IIO
(I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 40. and the sum of IIO
(I/O ports and control pins) must not exceed IVDD
.
104/123
ST7FOXA0
Electrical characteristics
12.9
Control pin characteristics
12.9.1
Asynchronous RESET pin
T = -40 to 85 °C, unless otherwise specified.
A
Table 57. Asynchronous RESET pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
VSS - 0.3
0.7VDD
0.3VDD
V
VDD+0.3
Vhys
Schmitt trigger voltage hysteresis(1)
Output low level voltage (2)
Pull-up equivalent resistor(3)
Generated reset pulse duration
External reset pulse hold time(4)
Filtered glitch duration
2
V
mV
kΩ
µs
µs
ns
VOL
VDD= 5 V IIO = +2 mA
200
RON
VIN=VSS
VDD = 5 V
30
20
50
70
tw(RSTL)out
th(RSTL)in
tg(RSTL)in
Internal reset sources
90(1)
200
1. Data based on characterization results, not tested in production
2. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 40. on page 94 and the
sum of IIO (I/O ports and control pins) must not exceed IVSS
.
3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between VILmax
and VDD
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
105/123
Electrical characteristics
Figure 39. RESET pin protection when LVD is enabled
ST7FOXA0
ST7xxx
VDD
Optional
(note 3)
Required
R
ON
INTERNAL
RESET
EXTERNAL
RESET
Filter
0.01µF
1MΩ
WATCHDOG
ILLEGALOPCODE
LVD RESET
PULSE
GENERATOR
1. The reset network protects the device against parasitic resets. The output of the external reset circuit must
have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the
ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the
user must ensure that the level on the RESET pin can go below the VIL max. level specified in
Section 12.9.1 on page 105. Otherwise the reset will not be taken into account internally. Because the
reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in
Section Table 40. on page 94.
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
Tips when using the LVD
●
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in Table 2 on page 11 and notes above).
●
Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100nF + 1MΩ pull-down on the RESET pin.
●
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to
20µF capacitor.”
106/123
ST7FOXA0
Electrical characteristics
Figure 40. RESET pin protection when LVD is disabled
VDD
ST7XXX
R
ON
Filter
INTERNAL
RESET
USER
EXTERNAL
RESET
CIRCUIT
0.01µF
WATCHDOG
PULSE
GENERATOR
ILLEGALOPCODE
Required
1. The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the VIL max. level specified in Section 12.9.1 on page 105. Otherwise the reset will not be
taken into account internally.
Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
I
INJ(RESET) in Section Table 40. on page 94.
2. Please refer to Section 10.2.1 on page 84 for more details on illegal opcode reset conditions.
107/123
Electrical characteristics
ST7FOXA0
12.10
10-bit ADC characteristics
Subject to general operating condition for V , f
, and T unless otherwise specified.
A
DD OSC
Table 58. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ(1)
Max
Unit
fADC
VAIN
ADC clock frequency
4
MHz
V
Conversion voltage range
VSS
VDD
8k(2)
10k(2)
VDD = 5 V, fADC = 4 MHz
RAIN
External input resistor
Ω
4.5 V ≤ VDD ≤ 5.5 V, fADC = 2 MHz
Internal sample and hold
capacitor
CADC
tSTAB
3
pF
Stabilization time after ADC
enable
0(3)
3.5
µs
Conversion time (Sample+Hold)
fCPU = 8 MHz, fADC = 4 MHz
tADC
- Sample capacitor loading time
- Hold conversion time
4
10
1/fADC
1. Unless otherwise specified, typical data are based on TA = 25 °C and VDD-VSS = 5 V. They are given only as design
guidelines and are not tested.
2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum
value). Data guaranteed by Design, not tested in production.
3. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always
valid.
Figure 41. Typical application with ADC
VDD
VT
0.6 V
RAIN
AINx
10-Bit A/D
Conversion
VAIN
VT
0.6 V
IL
1 µA
CADC
ST7xxx
108/123
ST7FOXA0
Electrical characteristics
Table 59. ADC accuracy with V = 4.5 to 5.5 V
DD
Symbol
Parameter
Conditions
Typ
Max
Unit
(1)
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error
Offset error
2.0
0.9
1.0
1.2
1.1
5.0
2.5
1.5
3.5
4.5
fCPU=8 MHz,
Gain Error
LSB
fADC=4 MHz(1)
Differential linearity error
Integral linearity error
1. Data based on characterization results over the whole temperature range.
Figure 42. ADC accuracy characteristics
(1) Example of an actual transfer curve
(2) The ideal transfer curve
Digital Result
EG
1023
1022
1021
(3) End point correlation line
V
– V
DD
SS
1LSB
= -------------------------------
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer
curves.
IDEAL
1024
(2)
ET
EO=Offset Error: deviation between the first
actual transition and the first ideal one.
(3)
7
6
5
4
3
2
1
(1)
EG=Gain Error: deviation between the last
ideal transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum
deviation between actual steps and the ideal
one.
ED
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
0
1
2
3
4
5
6
7
Vin (LSBIDEAL)
1021 1022 1023 1024
VDD
VSS
109/123
Device configuration and ordering information
ST7FOXA0
13
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7FOXA0 XFlash devices are shipped to customers with a default program memory
content (FFh).
13.1
Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
13.1.1
ST7FOXA0 Option byte 1
Bits 7:6 = CKSEL[1:0] Start-up clock selection.
These bits are used to select the startup frequency. By default, the internal RC is
selected.
Table 60. Startup clock selection
Configuration
CKSEL1
CKSEL0
Internal RC as Startup Clock
AWU RC as a Startup Clock
Reserved
0
0
1
1
0
1
0
1
External Clock on pin PA5
Bit 5 = Reserved, must always be 1.
Bit 4 = Reserved, must always be 0.
Bit 3 = Reserved, must always be 1
Bit 2 = LVD Low Voltage Detection selection.
This option bit enables the low voltage detection block (LVD).
0: LVD on
1: LVD off (default value)
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated when entering HALT mode while
the Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
110/123
ST7FOXA0
Device configuration and ordering information
13.1.2
ST7FOXA0 Option byte 0
OPT 7:4 = Reserved, must always be set
OPT 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 according to Table 61.
Table 61. Configuration of sector size
Sector 0 Size
SEC1
SEC0
0.5k
1k
0
1
-
0
0
1
2k
Bit 1 = FMP_R Read-Out Protection
Read-Out Protection, when selected provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option bytes
when the FMP_R option is selected will cause the whole memory to be erased first,
and the device can be reprogrammed. Refer to Section 4.5 on page 19 and the ST7
Flash Programming Reference Manual for more details.
0: Read-Out Protection off
1: Read-Out Protection on
Bit 0 = FMP_W Flash write protection
This option indicates if the Flash program memory is write protected.
0: Write protection off
1: Write protection on
Warning: When the Flash write protection is selected, the program
memory (and the option bit itself) can never be erased or
programmed again.
Option byte 0
Option byte 1
7
0
7
0
SEC SEC FMP FMP CK
CK
WDG WDG
SW HALT
Res Res Res Res
Res Res Res LVD
1
0
R
W
SEL1 SEL0
Default value
1
1
1
1
0
0
0
0
0
0
1
0
1
1
1
1
111/123
Device configuration and ordering information
ST7FOXA0
13.2
Device ordering information
Figure 43. ST7FOXA0 ordering information scheme
Example:
ST7 FOX
A
0
B
6
TR
Family
ST7 Microcontroller Family
Sub-family
FOX
No. of pins
A = 8
Memory size
0 = 2K
Package
B = DIP
M = SO
Temperature range
6 = -40 °C to 85 °C
Shipping
TR = Tape and Reel (available on SO8 package only)
Blank = Tube (DIP and SO packages)
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please contact the ST Sales Office nearest to you.
ST7FOX failure analysis service
For ST7FOX family devices, STMicroelectronics agrees to accept return of defective parts
subject to the FAR (Failure Analysis Report ) procedure only if the customer reject rate
exceeds 0.35 % for each delivered batch.
A batch is identified with a single trace code located on the top side marking.
112/123
ST7FOXA0
Device configuration and ordering information
13.3
Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
13.3.1
13.3.2
Starter kits
ST offers complete, affordable starter kits. Starter kits are complete hardware/software tool
packages that include features and samples to help you quickly start developing your
application.
Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16Kbytes of code.
The range of hardware tools includes a full-featured STiceEmulator, the low-cost RLink and
the ST7-STICK in-circuit debugger/programmer. These tools are supported by the ST7
Toolset from STMicroelectronics, which includes the STVD7 integrated development
environment (IDE) with high-level language debugger, editor, project manager and
integrated programming interface.
13.3.3
Programming tools
During the development cycle, the STice emulator, the ST7-STICK and the RLink provide
in-circuit programming capability for programming the Flash microcontroller on your
application board.
ST also provides a low-cost dedicated in-circuit programmer and ST7 Socket Boards,
which provide all the sockets required for programming any of the devices in a specific ST7
sub-family with any tool with in-circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
13.3.4
Order codes for development and programming tools
Table 62 below lists the ordering codes for the ST7FOX development and programming
tools. For additional ordering codes for spare parts and accessories, refer to the online
product selector at www.st.com/mcu.
113/123
Device configuration and ordering information
Table 62. Development tool order codes
ST7FOXA0
Debugging and
programming tool
MCU
ST socket boards
STX-RLINK(1)(2)
ST7-STICK(3)(4)
EMU3 or STice emulator(5)
,
ST7FOXA0M6
ST7FOXA0B6
,
ST7SB10-SU0 socket board(3)
1. USB connection to PC.
2. Available from ST or from Raisonance, www.raisonance.com.
3. Add suffix /EU, /UK or /US for the power supply for your region.
4. Parallel port connection to PC.
5. Contact local ST sales office for sales types.
13.4
ST7 application notes
Table 63. ST7 application notes
Identification
Description
Application examples
Serial numbering implementation
managing the Read-Out Protection in Flash microcontrollers
AN1658
AN1720
AN1755
AN1756
AN1812
A high resolution/precision thermometer using ST7 and NE555
Choosing a DALI implementation strategy with ST7DALI
A high precision, low cost, single supply ADC for positive and negative input voltages
Example drivers
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
SCI communication between ST7 and PC
SPI communication between ST7 and EEPROM
I²C communication between ST7 and M24Cxx EEPROM
ST7 software SPI master communication
SCI software communication with a PC using ST72251 16-bit timer
Real time clock with ST7 timer Output Compare
Driving a buzzer through ST7 timer PWM function
Driving an analog keyboard with the ST7 ADC
ST7 keypad decoding techniques, implementing wakeup on keystroke
Using the ST7 Universal Serial Bus microcontroller
Using ST7 PWM signal to generate analog output (sinusoïd)
ST7 routine for I²C Slave mode Management
Multiple interrupt sources management for ST7 MCUs
ST7 S/W implementation of I²C bus master
114/123
ST7FOXA0
Device configuration and ordering information
Description
Table 63. ST7 application notes (continued)
Identification
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
UART emulation software
Managing reception errors with the ST7 SCI peripherals
ST7 software LCD Driver
PWM duty cycle switch implementing true 0% & 100% duty cycle
Description of the ST72141 motor control peripherals registers
ST72141 BLDC motor control software and flowchart example
ST7 pCAN peripheral driver
PWM management for BLDC motor drives using the ST72141
An introduction to sensorless brushless DC motor drive applications with the ST72141
Using the ST7263 for designing a USB mouse
Handling Suspend mode on a USB mouse
Using the ST7263 kit to implement a USB game pad
BLDC motor start routine for the ST72141 microcontroller
Using the ST72141 motor control MCU in Sensor mode
Using the ST7 USB low-speed firmware V4.x
Emulated 16-bit slave SPI
Developing an ST7265X mass storage application
Starting a PWM signal directly at high level using the ST7 16-bit timer
16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs
Device firmware upgrade (DFU) implementation in ST7 non-USB applications
Generating a high resolution sinewave using ST7 PWMART
SMBus slave driver for ST7 I2C peripherals
Software UART using 12-bit ART
ST7MC PMAC sine wave motor control software library
General purpose
AN1476
AN1526
AN1709
AN1752
Low cost power supply for home appliances
ST7FLITE0 quick reference note
EMC design for ST microcontrollers
ST72324 quick reference note
Product evaluation
AN 910
AN 990
AN1077
AN1086
Performance benchmarking
ST7 benefits vs industry standard
Overview of enhanced CAN controllers for ST7 and ST9 MCUs
U435 can-do solutions for car multiplexing
115/123
Device configuration and ordering information
ST7FOXA0
Table 63. ST7 application notes (continued)
Identification
Description
AN1103
AN1150
AN1151
AN1278
Improved B-EMF detection for low speed, low voltage with ST72141
Benchmark ST72 vs PC16
Performance comparison between ST72254 & PC16F876
LIN (Local Interconnect Network) solutions
Product migration
AN1131
AN1322
AN1365
AN1604
AN2200
Migrating applications from ST72511/311/214/124 to ST72521/321/324
Migrating an application from ST7263 Rev.B to ST7263B
Guidelines for migrating ST72C254 applications to ST72F264
How to use ST7MDT1-TRAIN with ST72F264
Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB
Product optimization
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
AN1530
AN1605
AN1636
AN1828
AN1946
AN1953
AN1971
Using ST7 with ceramic resonator
How to minimize the ST7 power consumption
Software techniques for improving microcontroller EMC performance
Monitoring the Vbus signal for USB self-powered devices
ST7 checksum self-checking capability
Electrostatic discharge sensitive measurement
Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains
Emulated data EEPROM with ST7 HD Flash memory
Extending the current & voltage capability on the ST7265 VDDF supply
Accurate timebase for low-cost ST7 applications with internal RC oscillator
Using an active RC to wake up the ST7LITE0 from power saving mode
Understanding and minimizing ADC conversion errors
PIR (passive infrared) detector using the ST7FLITE05/09/SUPERLITE
Sensorless BLDC motor control and BEMF sampling methods with ST7MC
PFC for ST7MC starter kit
ST7LITE0 microcontrolled ballast
Programming and tools
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
ST7 Visual DeVELOP software key debugging features
Key features of the Cosmic ST7 C-compiler package
Executing code In ST7 RAM
Using the indirect addressing mode with ST7
ST7 serial test controller programming
Starting with ST7 assembly tool chain
116/123
ST7FOXA0
Device configuration and ordering information
Description
Table 63. ST7 application notes (continued)
Identification
AN1039
AN1071
AN1106
AN1179
AN1446
AN1477
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
ST7 math utility routines
Half duplex USB-to-serial bridge using the ST72611 USB microcontroller
Translating assembly code from HC05 to ST7
Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)
Using the ST72521 emulator to debug an ST72324 target application
Emulated data EEPROM with XFlash memory
Developing a USB smartcard reader with ST7SCR
On-board programming methods for XFlash and HD Flash ST7 MCUs
In-application programming (IAP) drivers for ST7 HD Flash or XFlash MCUs
Device firmware upgrade (DFU) Implementation for ST7 USB applications
Software implementation for ST7DALI-EVAL
Using the ST7 USB device firmware upgrade development kit (DFU-DK)
ST7 customer ROM code release information
Data logging program for testing ST7 applications via ICC
Field updates for Flash memory based ST7 applications using a PC comm port
Hardware implementation for ST7DALI-EVAL
ST7MC three-phase AC induction motor control software library
ST7MC three-phase BLDC motor control software library
System optimization
AN1711
AN1827
AN2009
AN2030
Software techniques for compensating ST7 ADC errors
Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
PWM management for 3-phase BLDC motor drives using the ST7FMC
Back EMF detection during PWM on time by ST7MC
117/123
Package mechanical data
ST7FOXA0
14
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
118/123
ST7FOXA0
Package mechanical data
Figure 44. 8-pin plastic small outline package - 150-mil width, package outline
D
h x 45°
A2
A
A1
C
α
B
L
E
H
e
Table 64. 8-pin plastic small outline package, 150-mil width, mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
B
1.35
0.10
1.10
0.33
0.19
4.80
3.80
1.75
0.25
1.65
0.51
0.25
5.00
4.00
0.0531
0.0039
0.0433
0.0130
0.0075
0.1890
0.1496
0.0689
0.0098
0.0650
0.0201
0.0098
0.1969
0.1575
C
D
E
e
1.27
0.0500
H
h
5.80
0.25
0°
6.20
0.50
8°
0.2283
0.0098
0°
0.2441
0.0197
8°
α
L
0.40
1.27
0.0157
0.0500
Number of Pins
N
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
119/123
Package mechanical data
ST7FOXA0
Figure 45. 8-pin plastic dual in-line outline package - 300-mil width, package outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Table 65. 8-pin plastic dual in-line outline package - 300-mil width, mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
5.33
0.2098
0.38
2.92
0.36
1.14
0.2
9.02
7.62
6.1
-
0.0150
0.1150
0.0142
0.0449
0.0079
0.3551
0.3000
0.2402
3.3
4.95
0.56
1.78
0.36
10.16
8.26
7.11
-
0.1299
0.0181
0.0598
0.0098
0.3650
0.3098
0.2500
0.1000
0.3000
0.1949
0.0220
0.0701
0.0142
0.4000
0.3252
0.2799
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
b2
c
D
E
E1
e
eA
eB
L
-
-
10.92
3.81
0.4299
0.1500
3.3
2.92
0.1299
0.1150
1. Values in inches are converted from mm and rounded to 4 decimal digits.
120/123
ST7FOXA0
Package mechanical data
14.1
Thermal characteristics
Table 66. Thermal characteristics
Symbol
Ratings
Value
Unit
SO8
130
82
Package thermal resistance
(junction to ambient)
RthJA
°C/W
DIP8
Maximum junction
temperature(1)
TJmax
150
°C
SO8
180
300
PDmax
Power dissipation(2)
mW
DIP8
1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA
.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT
where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the
ports used in the application.
121/123
Revision history
ST7FOXA0
15
Revision history
Table 67. Document revision history
Date
Revision
Changes
18-Oct-2007
1
Initial release
Added LVD function
Modified Figure 3: ST7FOXA0 memory map on page 13
Modified note 4 in Section 4.4: ICC interface on page 17
Added RCC_CSR in Table 3: ST7FOXA0 Hardware register map on
page 13
Added Section 6.1.2: Customized RC calibration on page 26
Section 12.7: EMC (electromagnetic compatibility) characteristics on
page 100 modified
22-Nov-2007
04-Feb-2008
2
3
Modified Section 13.2: Device ordering information on page 112
ST7FOXU0 replaced by ST7FOXA0
Added LVD in Figure 1: General block diagram on page 10
Modified Figure 43: ST7FOXA0 ordering information scheme on
page 112
Modified Table 62: Development tool order codes on page 114
122/123
ST7FOXA0
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123/123
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