ST7PLITES5Y0M6 [STMICROELECTRONICS]
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI; 8位MCU单电压闪存存储器，数据EEPROM ， ADC ，定时器， SPI
| 型号： | ST7PLITES5Y0M6 |
| 厂家： | 
ST |
| 描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| 文件： | 总122页 (文件大小：1718K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7LITE0, ST7SUPERLITE
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
DATA EEPROM, ADC, TIMERS, SPI
■ Memories
– 1K or 1.5K bytes single voltage Flash Pro-
gram memory with read-out protection, In-Cir-
cuit and In-Application Programming (ICP and
IAP). 10K write/erase cycles guaranteed, data
retention: 20 years at 55°C.
DIP16
– 128 bytes RAM.
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management
SO16
150”
– 3-level low voltage supervisor (LVD) and aux-
iliary voltage detector (AVD) for safe power-
on/off procedures
– Clock sources: internal 1MHz RC 1% oscilla-
tor or external clock
– One 12-bit Auto-reload Timer (AT) with output
compare function and PWM
■ 1 Communication Interface
– PLL x4 or x8 for 4 or 8 MHz internal clock
– SPI synchronous serial interface
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
■ A/D Converter
– 8-bit resolution for 0 to V
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 4 external interrupt lines (on 4 vectors)
■ I/O Ports
DD
– Fixed gain Op-amp for 11-bit resolution in 0 to
250 mV range (@ 5V V
)
DD
– 5 input channels
■ Instruction Set
– 13 multifunctional bidirectional I/O lines
– 9 alternate function lines
– 6 high sink outputs
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
■ 2 Timers
– 8 x 8 unsigned multiply instruction
– One 8-bit Lite Timer (LT) with prescaler in-
cluding: watchdog, 1 realtime base and 1 in-
put capture.
■ Development Tools
– Full hardware/software development package
Device Summary
ST7SUPERLITE
Features
ST7LITE0
ST7LITES2
ST7LITES5
ST7LITE02
1.5K
128 (64)
ST7LITE05
ST7LITE09
1.5K
Program memory - bytes
RAM (stack) - bytes
1K
1K
1.5K
128 (64)
-
128 (64)
128 (64)
128 (64)
128
Data EEPROM - bytes
-
-
-
LT Timer w/ Wdg,
LT Timer w/ Wdg,
LT Timer w/ Wdg,
LT Timer w/ Wdg,
Peripherals
AT Timer w/ 1 PWM, AT Timer w/ 1 PWM, AT Timer w/ 1 PWM,
AT Timer w/ 1 PWM, SPI,
8-bit ADC w/ Op-Amp
SPI
SPI, 8-bit ADC
SPI
Operating Supply
CPU Frequency
Operating Temperature
Packages
2.4V to 5.5V
1MHz RC 1% + PLLx4/8MHz
-40°C to +85°C
SO16 150”, DIP16
Rev. 2.4
August 2003
1/122
1
Table of Contents
ST7LITE0, ST7SUPERLITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 33
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Table of Contents
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 100
13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 109
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 111
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD-
WARE WATCHDOG OPTION 116
16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 116
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Table of Contents
ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
18 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
20 SILICON limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
20.1 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 118
20.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
20.3 FUNCTIONAL ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
21 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
22 ERRATA SHEET REVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please note that an errata sheet can be found at the end of this document on page 118
and pay special attention to the Section “IMPORTANT NOTES” on page 116.
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ST7LITE0, ST7SUPERLITE
1 INTRODUCTION
The ST7LITE0 and ST7SUPERLITE are members
of the ST7 microcontroller family. All ST7 devices
are based on a common industry-standard 8-bit
core, featuring an enhanced instruction set.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The ST7LITE0 and ST7SUPERLITE feature
FLASH memory with byte-by-byte In-Circuit Pro-
gramming (ICP) and In-Application Programming
(IAP) capability.
For easy reference, all parametric data are located
in section 13 on page 78.
Under software control, the ST7LITE0 and
ST7SUPERLITE devices can be placed in WAIT,
SLOW, or HALT mode, reducing power consump-
tion when the application is in idle or standby state.
Figure 1. General Block Diagram
Internal
CLOCK
1 MHz. RC OSC
+
PLL x 4 or x 8
LITE TIMER
w/ WATCHDOG
LVD/AVD
V
DD
PA7:0
(8 bits)
POWER
SUPPLY
PORT A
V
SS
12-BIT AUTO-
RESET
RELOAD TIMER
CONTROL
8-BIT CORE
ALU
SPI
FLASH
MEMORY
PB4:0
(5 bits)
PORT B
(1 or 1.5K Bytes)
8-BIT ADC
RAM
(128 Bytes)
DATA EEPROM
(128 Bytes)
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1
ST7LITE0, ST7SUPERLITE
2 PIN DESCRIPTION
Figure 2. 16-Pin Package Pinout (150mil)
V
PA0 (HS)/LTIC
1
2
3
4
5
6
7
8
ei0
16
15
14
13
12
11
10
9
SS
V
PA1 (HS)
DD
RESET
SS/AIN0/PB0
PA2 (HS)/ATPWM0
PA3 (HS)
ei3
ei2
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
PA4 (HS)
PA5 (HS)/ICCDATA
PA6/MCO/ICCCLK
PA7
ei1
(HS) 20mA high sink capability
ei associated external interrupt vector
x
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ST7LITE0, ST7SUPERLITE
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type:
I = input, O = output, S = supply
In/Output level: C= CMOS 0.15V /0.85V with input trigger
DD
DD
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
1)
– Input:
float = floating, wpu = weak pull-up, int = interrupt , ana = analog
2)
– Output:
OD = open drain , PP = push-pull
Table 1. Device Pin Description
Level
Port / Control
Input Output
Main
Function
(after reset)
Pin
n°
Pin Name
Alternate Function
1
2
3
V
V
S
S
Ground
SS
DD
Main power supply
RESET
I/O
C
C
C
C
X
X
X
X
X
Top priority non maskable interrupt (active low)
T
T
T
T
ADC Analog Input 0 or SPI Slave
Select (active low)
4
5
6
PB0/AIN0/SS
PB1/AIN1/SCK
PB2/AIN2/MISO
I/O
I/O
I/O
X
X
X
ei3
X
X
X
Port B0
X
X
Port B1
Port B2
ADC Analog Input 1 or SPI Clock
ADC Analog Input 2 or SPI Master
In/ Slave Out Data
ADC Analog Input 3 or SPI Master
Out / Slave In Data
7
PB3/AIN3/MOSI
I/O
C
X
ei2
ei1
X
X
Port B3
T
ADC Analog Input 4 or External
clock input
8
9
PB4/AIN4/CLKIN
PA7
I/O
I/O
C
C
X
X
X
X
X
X
X
Port B4
Port A7
T
T
Main Clock Output/In Circuit Com-
munication Clock.
Caution: During reset, this pin
must be held at high level to avoid
entering ICC mode unexpectedly
(this is guaranteed by the internal
pull-up if the application leaves the
pin floating).
10 PA6 /MCO/ICCCLK
I/O
C
X
X
X
X
Port A6
T
PA5/
11
I/O C HS
X
X
X
X
Port A5
In Circuit Communication Data
T
ICCDATA
12 PA4
I/O C HS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port A4
Port A3
Port A2
Port A1
Port A0
T
13 PA3
I/O C HS
T
14 PA2/ATPWM0
15 PA1
I/O C HS
Auto-Reload Timer PWM0
Lite Timer Input Capture
T
I/O C HS
T
16 PA0/LTIC
I/O C HS
ei0
T
Note:
In the interrupt input column, “ei ” defines the associated external interrupt vector. If the weak pull-up col-
x
umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
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1
ST7LITE0, ST7SUPERLITE
3 REGISTER & MEMORY MAP
As shown in Figure 3 and Figure 4, the MCU is ca-
pable of addressing 64K bytes of memories and I/
O registers.
The highest address bytes contain the user reset
and interrupt vectors.
The size of Flash Sector 0 is configurable by Op-
tion byte.
The available memory locations consist of up to
128 bytes of register locations, 128 bytes of RAM,
128 bytes of data EEPROM and up to 1.5 Kbytes
of user program memory. The RAM space in-
cludes up to 64 bytes for the stack from 0C0h to
0FFh.
IMPORTANT: Memory locations marked as “Re-
served” must never be accessed. Accessing a re-
seved area can have unpredictable effects on the
device.
Figure 3. Memory Map (ST7LITE0)
0000h
0080h
HW Registers
(see Table 2)
Short Addressing
RAM (zero page)
007Fh
0080h
00BFh
00C0h
RAM
(128 Bytes)
64 Bytes Stack
00FFh
0100h
00FFh
Reserved
0FFFh
1000h
1000h
RCCR0
Data EEPROM
(128 Bytes)
RCCR1
1001h
107Fh
1080h
see section 7.1 on page 23
1.5K FLASH
Reserved
PROGRAM MEMORY
F9FFh
FA00h
FA00h
0.5 Kbytes
SECTOR 1
FBFFh
FC00h
Flash Memory
(1.5K)
1 Kbytes
SECTOR 0
FFFFh
FFDFh
FFE0h
FFDEh
RCCR0
Interrupt & Reset Vectors
(see Table 7)
RCCR1
FFDFh
FFFFh
see section 7.1 on page 23
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1
ST7LITE0, ST7SUPERLITE
REGISTER AND MEMORY MAP (Cont’d)
Figure 4. Memory Map (ST7SUPERLITE)
0000h
0080h
HW Registers
Short Addressing
RAM (zero page)
(see Table 2)
007Fh
00BFh
00C0h
0080h
RAM
(128 Bytes)
64 Bytes Stack
00FFh
0100h
00FFh
Reserved
1K FLASH
PROGRAM MEMORY
FBFFh
FC00h
FC00h
0.5 Kbytes
SECTOR 1
FDFFh
FE00h
Flash Memory
(1K)
0.5 Kbytes
SECTOR 0
FFFFh
FFDFh
FFE0h
Interrupt & Reset Vectors
FFDEh
FFDFh
RCCR0
RCCR1
(see Table 7)
FFFFh
see section 7.1 on page 23
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1
ST7LITE0, ST7SUPERLITE
REGISTER AND MEMORY MAP (Cont’d)
Legend: x=undefined, R/W=read/write
Table 2. Hardware Register Map
Register
Reset
Status
Address
Block
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Remarks
R/W
R/W
R/W
Label
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
00h
Port A
00h
40h
1)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
E0h
R/W
R/W
R/W
Port B
00h
00h
2)
0006h to
000Ah
Reserved area (5 bytes)
000Bh
000Ch
LITE
TIMER
LTCSR
LTICR
Lite Timer Control/Status Register
Lite Timer Input Capture Register
xxh
xxh
R/W
Read Only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
AUTO-RELOAD
TIMER
PWM0CSR PWM 0 Control/Status Register
R/W
0014h to
0016h
Reserved area (3 bytes)
0017h AUTO-RELOAD DCR0H
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
00h
00h
R/W
R/W
0018h
TIMER
DCR0L
0019h to
002Eh
Reserved area (22 bytes)
0002Fh
00030h
FLASH
FCSR
Flash Control/Status Register
00h
00h
R/W
R/W
EEPROM
EECSR
Data EEPROM Control/Status Register
0031h
0032h
0033h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
0034h
0035h
0036h
ADCCSR
ADCDAT
ADCAMP
A/D Control Status Register
A/D Data Register
A/D Amplifier Control Register
00h
00h
00h
R/W
Read Only
R/W
ADC
0037h
ITC
EICR
External Interrupt Control Register
00h
R/W
0038h
0039h
MCCSR
RCCR
Main Clock Control/Status Register
RC oscillator Control Register
00h
FFh
R/W
R/W
CLOCKS
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1
ST7LITE0, ST7SUPERLITE
Register
Label
Reset
Address
Block
Register Name
Remarks
Status
003Ah
SI
SICSR
System Integrity Control/Status Register
Reserved area (45 bytes)
0xh
R/W
003Bh to
007Fh
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
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ST7LITE0, ST7SUPERLITE
4 FLASH PROGRAM MEMORY
4.1 Introduction
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Commu-
nication) which allows an ST7 plugged on a print-
ed circuit board (PCB) to communicate with an ex-
ternal programming device connected via cable.
ICP is performed in three steps:
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Program-
ming.
Switch the ST7 to ICC mode (In-Circuit Communi-
cations). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory contain-
ing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
– Download ICP Driver code in RAM from the
ICCDATA pin
■ ICP (In-Circuit Programming)
– Execute ICP Driver code in RAM to program
the FLASH memory
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection against piracy
4.3 PROGRAMMING MODES
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM can be programmed or
erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM can be programmed or erased with-
out removing the device from the application
board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM can be pro-
grammed or erased without removing the de-
vice from the application board and while the
application is running.
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory ar-
eas except Sector 0, which is write/erase protect-
ed to allow recovery in case errors occur during
the programming operation.
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1
ST7LITE0, ST7SUPERLITE
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli-
cation RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up re-
sistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET: device reset
– V : device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN: main clock input for external source
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program-
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
– V : application board power supply (option-
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another de-
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val-
ues.
4. Pin 9 has to be connected to the CLKIN pin of
the ST7 when the clock is not available in the ap-
plication or if the selected clock option is not pro-
grammed in the option byte.
5. During reset, this pin must be held at high level
to avoid entering ICC mode unexpectedly (this is
guaranteed by the internal pull-up if the application
leaves the pin floating).
2. During the ICP session, the programming tool
must control the RESET pin. This can lead to con-
flicts between the programming tool and the appli-
Figure 5. Typical ICC Interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
OPTIONAL
(See Note 3)
OPTIONAL
(See Note 4)
APPLICATION BOARD
9
7
5
6
3
1
2
10
8
4
APPLICATION
RESET SOURCE
See Note 2
APPLICATION
POWER SUPPLY
See Notes 1 and 5
See Note 1
APPLICATION
I/O
ST7
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ST7LITE0, ST7SUPERLITE
FLASH PROGRAM MEMORY (Cont’d)
4.5 Memory Protection
4.6 Related Documentation
There are two different types of memory protec-
tion: Read Out Protection and Write/Erase Protec-
tion which can be applied individually.
For details on Flash programming and ICC proto-
col, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Refer-
ence Manual.
4.5.1 Read out Protection
Read out protection, when selected, makes it im-
possible to extract the memory content from the
microcontroller, thus preventing piracy. Both pro-
4.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
2
gram and data E memory are protected.
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
In flash devices, this protection is removed by re-
programming the option. In this case, both pro-
gram and data E memory are automatically
2
erased, and the device can be reprogrammed.
7
0
0
Read-out protection selection depends on the de-
vice type:
0
0
0
0
OPT
LAT
PGM
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing op-
erations.
– In ROM devices it is enabled by mask option
specified in the Option List.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impos-
sible to both overwrite and erase program memo-
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
2
ry. It does not apply to E data. Its purpose is to
provide advanced security to applications and pre-
vent any change being made to the memory con-
tent.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
Table 3. FLASH Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
FCSR
Reset Value
OPT
0
LAT
0
PGM
0
002Fh
0
0
0
0
0
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1
ST7LITE0, ST7SUPERLITE
5 DATA EEPROM
5.1 INTRODUCTION
5.2 MAIN FEATURES
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile back-
up for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection against piracy
Figure 6. EEPROM Block Diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
0
0
0
E2LAT E2PGM
EEPROM
ROW
ADDRESS
DECODER
4
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
DECODER
128
128
DATA
MULTIPLEXER
32 x 8 BITS
4
4
DATA LATCHES
ADDRESS BUS
DATA BUS
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ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
the value is latched inside the 32 data latches ac-
cording to its address.
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 7 describes these different memory
access modes.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
WRITE MODE
E2LAT=1
E2PGM=0
E2PGM=0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
READ BYTES
IN EEPROM AREA
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
1
E2LAT
CLEARED BY HARDWARE
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1
ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
2
Figure 8. Data E PROM Write Operation
Row / Byte
0
1
2
3
...
30 31
Physical Address
00h...1Fh
0
1
ROW
DEFINITION
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Read operation possible
Programming cycle
Byte 1 Byte 2
PHASE 1
Byte 32
PHASE 2
Writing data latches
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem-
ory is not guaranteed.
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ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
5.6 Data EEPROM Read-out Protection
Active-Halt mode
The read-out protection is enabled through an op-
tion bit (see section 15.1 on page 109).
Refer to Wait mode.
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out piracy (including a re-write pro-
tection). In Flash devices, when this protection is
removed by reprogramming the Option Byte, the
entire Program memeory and EEPROM is first au-
tomatically erased.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE CYCLE
WRITE OF
DATA LATCHES
tPROG
LAT
PGM
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1
ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EEC-
SR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the pro-
gramming cycle, the memory data is not guaran-
teed
Table 4. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
E2LAT
0
E2PGM
0
0030h
0
0
0
0
0
0
Reset Value
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1
ST7LITE0, ST7SUPERLITE
6 CENTRAL PROCESSING UNIT
6.1 INTRODUCTION
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
Index Registers (X and Y)
6.2 MAIN FEATURES
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
6.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
1
1
H I N Z
C
CONDITION CODE REGISTER
RESET VALUE =
8
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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1
ST7LITE0, ST7SUPERLITE
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.
Reset Value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Bit 2 = N Negative.
The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
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1
ST7LITE0, ST7SUPERLITE
CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 00 FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
0
0
0
7
1
0
1
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 64 bytes deep, the 10 most sig-
nificant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP5 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
event
@ 00C0h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 00FFh
Stack Higher Address = 00FFh
00C0h
Stack Lower Address =
22/122
1
ST7LITE0, ST7SUPERLITE
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ST7FLITE02/
ST7FLITE05/
ST7FLITES2/
ST7FLITES5
ST7FLITE09
RCCR
Conditions
Address
ducing the number of external components.
Address
Main features
V
=5V
DD
1000h and
FFDEh
■ Clock Management
RCCR0
T =25°C
FFDEh
A
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
f
=1MHz
RC
V
=3.0V
DD
1001h and-
FFDFh
RCCR1
T =25°C
FFDFh
– External Clock Input (enabled by option byte)
A
f
=700KHz
RC
– PLL for multiplying the frequency by 4 or 8
(enabled by option byte)
and V pins as close as possible to the ST7 de-
SS
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
vice.
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Conse-
quently, customers intending to use FASTROM
service must not use these two bytes.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an ex-
ternal reference signal.
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The ST7LITE0 and ST7SUPERLITE contain an in-
ternal RC oscillator with an accuracy of 1% for a
given device, temperature and voltage. It must be
calibrated to obtain the frequency required in the
application. This is done by software writing a cal-
ibration value in the RCCR (RC Control Register).
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequen-
cy from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be load-
ed in the RCCR. Predefined calibration values are
bled and the multiplication factor of 4 or 8 is select-
ed by 2 option bits.
– The x4 PLL is intended for operation with V in
DD
the 2.4V to 3.3V range
stored in EEPROM for 3.0 and 5V V supply volt-
DD
ages at 25°C, as shown in the following table.
– The x8 PLL is intended for operation with V in
DD
the 3.3V to 5.5V range
Notes:
Refer to Section 15.1 for the option byte descrip-
tion.
– See “ELECTRICAL CHARACTERISTICS” on
page 78. for more information on the frequency
and accuracy of the RC oscillator.
If the PLL is disabled and the RC oscillator is ena-
bled, then f
1MHz.
OSC =
– To improve clock stability, it is recommended to
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
place a decoupling capacitor between the V
f
DD
OSC
23/122
1
ST7LITE0, ST7SUPERLITE
Figure 12. PLL Output Frequency Timing
Diagram
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
LOCKED bit set
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
4/8 x
input
freq.
t
STAB
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
t
LOCK
clock f
0: Normal mode (f
1: Slow mode (f
or f
/32.
OSC
OSC
f
CPU = OSC
t
STARTUP
f
/32)
CPU = OSC
t
RC CONTROL REGISTER (RCCR)
Read / Write
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
Reset Value: 1111 1111 (FFh)
clock after a delay of t
.
STARTUP
7
0
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC ) is reached after
a stabilization time of t
13.3.4 Internal RC Oscillator and PLL)
CR0
CR70 CR60 CR50 CR40 CR30 CR20 CR10
PLL
(see Figure 12 and
STAB
Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-
justment Bits
These bits must be written immediately after reset
to adjust the RC oscillator frequency and to obtain
an accuracy of 1%. The application can store the
correct value for each voltage range in EEPROM
and write it to this register at start-up.
Refer to section 7.5.4 on page 32 for a description
of the LOCKED bit in the SICSR register.
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
00h = maximum available frequency
FFh = lowest available frequency
Reset Value: 0000 0000 (00h)
Note: To tune the oscillator, write a series of differ-
ent values in the register until the correct frequen-
cy is reached. The fastest method is to use a di-
chotomy starting with 80h.
7
0
MCO SMS
00
0
0
0
0
0
Bits 7:2 = Reserved, must be kept cleared.
Table 5. Clock Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
MCCSR
MCO
0
SMS
0
0038h
0039h
0
0
0
0
0
0
Reset Value
RCCR
CR70
1
CR60
1
CR50
1
CR40
1
CR30
1
CR20
1
CR10
1
CR0
1
Reset Value
24/122
1
ST7LITE0, ST7SUPERLITE
Figure 13. Clock Management Block Diagram
CR7 CR6 CR5 CR4 CR3 CR2 CR1
CR0
RCCR
1MHz
8MHz
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
f
Tunable
1% RC Oscillator
OSC
4MHz
Option byte
0 to 8 MHz
/2 DIVIDER
CLKIN
Option byte
f
LTIMER
8-BIT
(1ms timebase @ 8 MHz f
)
LITE TIMER COUNTER
OSC
f
f
/32
OSC
OSC
/32 DIVIDER
1
0
f
CPU
TO CPU AND
PERIPHERALS
f
OSC
(except LITE
TIMER)
MCCSR
MCO SMS
0
7
f
CPU
MCO
25/122
1
ST7LITE0, ST7SUPERLITE
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The RESET vector fetch phase duration is 2 clock
cycles.
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 12).
(see
STARTUP
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 14. RESET Sequence Phases
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
RESET
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
INTERNAL RESET
Active Phase
FETCH
256 CLOCK CYCLES
VECTOR
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
■ RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
Figure 15. Reset Block Diagram
V
DD
R
ON
INTERNAL
RESET
FILTER
RESET
PULSE
GENERATOR
WATCHDOG RESET
LVD RESET
26/122
1
ST7LITE0, ST7SUPERLITE
RESET SEQUENCE MANAGER (Cont’d)
7.4.2 Asynchronous External RESET pin
A proper reset signal for a slow rising V supply
can generally be provided by an external RC net-
work connected to the RESET pin.
DD
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
7.4.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
A RESET signal originating from an external
■ Power-On RESET
source must have a duration of at least t
in
h(RSTL)in
■ Voltage Drop RESET
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 16.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
DD
IT-
The LVD filters spikes on V larger than t
avoid parasitic resets.
to
g(VDD)
DD
7.4.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
7.4.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
.
signal is held low until V
level specified for the selected f
is over the minimum
w(RSTL)out
DD
frequency.
OSC
Figure 16. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 TCPU
)
VECTOR FETCH
27/122
1
ST7LITE0, ST7SUPERLITE
7.5 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low voltage Detector (LVD) and Auxiliary Volt-
age Detector (AVD) functions. It is managed by
the SICSR register.
Provided the minimum V
the oscillator frequency) is above V
MCU can only be in two modes:
value (guaranteed for
DD
, the
IT-(LVD)
– under full software control
– in static safe reset
7.5.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
ates a static reset when the V supply voltage is
DD
below a V
reference value. This means that
IT-(LVD)
it secures the power-up as well as the power-down
keeping the ST7 in reset.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
The V
lower than the V
reference value for a voltage drop is
IT-(LVD)
reference value for power-
IT+(LVD)
on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
Notes:
The LVD is an optional function which can be se-
lected by option byte. See section 15.1 on page
109.
The LVD Reset circuitry generates a reset when
V
is below:
DD
– V
when V is rising
DD
It allows the device to be used without any external
RESET circuitry.
IT+(LVD)
– V
when V is falling
DD
IT-(LVD)
If the LVD is disabled, an external circuitry must be
used to ensure a proper power-on reset.
The LVD function is illustrated in Figure 17.
The voltage threshold can be configured by option
byte to be low, medium or high. See section 15.1
on page 109.
Caution: If an LVD reset occurs after a watchdog
reset has occurred, the LVD will take priority and
will clear the watchdog flag.
Figure 17. Low Voltage Detector vs Reset
V
DD
V
hys
V
V
IT+
(LVD)
IT-
(LVD)
RESET
28/122
1
ST7LITE0, ST7SUPERLITE
Figure 18. Reset and Supply Management Block Diagram
WATCHDOG
TIMER (WDG)
STATUS FLAG
SYSTEM INTEGRITY MANAGEMENT
AVD Interrupt Request
RESET SEQUENCE
MANAGER
RESET
SICSR
(RSM)
LOC LVD AVD AVD
0
0
0
0
KED RF
F
IE
0
7
LOW VOLTAGE
DETECTOR
(LVD)
V
SS
V
DD
AUXILIARY VOLTAGE
DETECTOR
(AVD)
29/122
1
ST7LITE0, ST7SUPERLITE
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.5.2 Auxiliary Voltage Detector (AVD)
7.5.2.1 Monitoring the V Main Supply
DD
The Voltage Detector function (AVD) is based on
The AVD voltage threshold value is relative to the
selected LVD threshold configured by option byte
(see section 15.1 on page 109).
an analog comparison between a V
and
main sup-
IT-(AVD)
V
reference value and the V
IT+(AVD)
DD
ply voltage (V
for falling voltage is lower than the V
). The V
reference value
AVD
IT-(AVD)
If the AVD interrupt is enabled, an interrupt is gen-
refer-
IT+(AVD)
erated when the voltage crosses the V
or
IT+(LVD)
ence value for rising voltage in order to avoid par-
V
threshold (AVDF bit is set).
IT-(AVD)
asitic detection (hysteresis).
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See Figure 19.
The output of the AVD comparator is directly read-
able by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD functions only if the LVD is en-
abled through the option byte.
The interrupt on the rising edge is used to inform
the application that the V warning state is over
DD
Figure 19. Using the AVD to Monitor V
DD
V
DD
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
V
hyst
V
IT+(AVD)
V
IT-(AVD)
V
V
IT+(LVD)
IT-(LVD)
AVDF bit
0
1
RESET
1
0
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
INTERRUPT Cleared by
reset
INTERRUPT Cleared by
hardware
LVD RESET
30/122
1
ST7LITE0, ST7SUPERLITE
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.5.3 Low Power Modes
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
WAIT
Description
Enable Exit
Control from
Exit
from
Halt
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Event
Flag
Interrupt Event
Bit
Wait
The CRSR register is frozen.
AVD event
AVDF AVDIE
Yes
Yes
HALT
The AVD remains active but the AVD inter-
rupt cannot be used to exit from Halt mode.
7.5.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
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1
ST7LITE0, ST7SUPERLITE
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.5.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit changes value. Refer to
Figure 19 for additional details
Reset Value: 0000 0x00 (0xh)
0: V over AVD threshold
DD
7
0
1: V under AVD threshold
DD
LOCK
ED
0
0
0
0
LVDRF AVDF AVDIE
Bit 0 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa-
tion is automatically cleared when software enters
the AVD interrupt routine.
Bit 7:4 = Reserved, must be kept cleared.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: AVD interrupt disabled
1: AVD interrupt enabled
0: PLL not locked
1: PLL locked
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description in Section 11.1 for more
details. When the LVD is disabled by OPTION
BYTE, the LVDRF bit value is undefined.
Bit 1 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
Table 6. System Integrity Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SICSR
LOCKED LVDRF
AVDF
0
AVDIE
0
003Ah
0
0
0
0
0
x
Reset Value
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1
ST7LITE0, ST7SUPERLITE
8 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 20.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
It will be serviced according to the flowchart on
Figure 20.
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
– Normal processing is suspended at the end of
the current instruction execution.
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
– The PC, X, A and CC registers are saved onto
the stack.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically NANDed before entering the
edge/level detection block.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of a NANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
8.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
Priority Management
By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
Interrupts and Low Power Mode
– Writing “0” to the corresponding bit in the status
register or
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta-
ble).
– Access to the status register while the flag is set
followed by a read or write of an associated reg-
ister.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
8.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
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1
ST7LITE0, ST7SUPERLITE
INTERRUPTS (Cont’d)
Figure 20. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
N
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 7. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
Software Interrupt
Not used
0
1
ei0
ei1
ei2
ei3
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Not used
N/A
2
yes
3
4
5
6
Not used
7
SI
AVD interrupt
SICSR
PWM0CSR
ATCSR
yes
no
8
AT TIMER Output Compare Interrupt
AT TIMER Overflow Interrupt
LITE TIMER Input Capture Interrupt
LITE TIMER RTC Interrupt
SPI Peripheral Interrupts
Not used
AT TIMER
9
yes
no
10
11
12
13
LTCSR
LITE TIMER
SPI
LTCSR
yes
yes
SPICSR
Lowest
Priority
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1
ST7LITE0, ST7SUPERLITE
INTERRUPTS (Cont’d)
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
Bit 1:0 = IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0
(Port A0) according to Table 8.
Read/Write
Note: These 8 bits can be written only when the I
bit in the CC register is set.
Reset Value: 0000 0000 (00h)
7
0
Table 8. Interrupt Sensitivity Bits
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
ISx1 ISx0
External Interrupt Sensitivity
Bit 7:6 = IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei3
(Port B0) according to Table 8.
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
Bit 5:4 = IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2
.
(Port B3) according to Table 8.
Bit 3:2 = IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1
(Port A7) according to Table 8.
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1
ST7LITE0, ST7SUPERLITE
9 POWER SAVING MODES
9.1 INTRODUCTION
9.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 21): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
the available supply voltage.
) to
CPU
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
main oscillator frequency (f
).
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
OSC
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Notes:
SLOW-WAIT mode is activated when entering
WAIT mode while the device is already in SLOW
mode.
Figure 21. Power Saving Mode Transitions
SLOW mode has no effect on the Lite Timer which
is already clocked at F
.
OSC/32
High
RUN
Figure 22. SLOW Mode Clock Transition
f
/32
f
OSC
OSC
SLOW
WAIT
f
CPU
f
OSC
SLOW WAIT
ACTIVE HALT
HALT
SMS
NORMAL RUN MODE
REQUEST
Low
POWER CONSUMPTION
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ST7LITE0, ST7SUPERLITE
POWER SAVING MODES (Cont’d)
9.3 WAIT MODE
Figure 23. WAIT Mode Flow-chart
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
OSCILLATOR
PERIPHERALS
CPU
ON
ON
OFF
0
WFI INSTRUCTION
‘WFI’ instruction.
I BIT
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
N
RESET
Y
N
INTERRUPT
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.
Y
OSCILLATOR
PERIPHERALS
CPU
ON
OFF
ON
0
Refer to Figure 23.
I BIT
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
1)
I BIT
X
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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ST7LITE0, ST7SUPERLITE
POWER SAVING MODES (Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
Figure 24. ACTIVE-HALT Timing Overview
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
ACTIVE
HALT
256 CPU
CYCLE DELAY
RUN
RUN
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt Enabled]
FETCH
VECTOR
ATCSR
OVFIE
bit
LTCSR
TBIE bit
ATCSR ATCSR
CK1 bit CK0 bit
Meaning
Figure 25. ACTIVE-HALT Mode Flow-chart
0
0
0
1
x
x
0
1
x
1
x
x
1
x
0
0
x
1
x
1
OSCILLATOR
PERIPHERALS 2)
CPU
ON
OFF
OFF
0
ACTIVE-HALT
mode disabled
HALT INSTRUCTION
(Active Halt enabled)
I BIT
ACTIVE-HALT
mode enabled
N
9.4.1 ACTIVE-HALT MODE
RESET
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS 2)
CPU
Y
ON
OFF
ON
The MCU can exit ACTIVE-HALT mode on recep-
tion of a Lite Timer / AT Timer interrupt or a RE-
SET.
I BIT
X 4)
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure 25).
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 25).
I BITS
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
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ST7LITE0, ST7SUPERLITE
POWER SAVING MODES (Cont’d)
9.4.2 HALT MODE
Figure 27. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when active halt mode is disa-
bled.
HALT INSTRUCTION
(Active Halt disabled)
ENABLE
WATCHDOG
DISABLE
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 34) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
CPU cycle delay is used to stabilize the oscillator.
After the start up delay, the CPU resumes opera-
tion by servicing the interrupt or by fetching the re-
set vector which woke it up (see Figure 27).
0
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
OFF
OFF
0
PERIPHERALS 2)
CPU
I BIT
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
N
RESET
Y
N
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
I BIT
X 4)
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 109 for more details).
256 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
Figure 26. HALT Timing Overview
I BITS
256 CPU CYCLE
FETCH RESET VECTOR
OR SERVICE INTERRUPT
RUN
HALT
RUN
DELAY
Notes:
RESET
OR
INTERRUPT
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
HALT
INSTRUCTION
[Active Halt disabled]
FETCH
VECTOR
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 34 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of t
(see Figure 12).
STARTUP
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1
ST7LITE0, ST7SUPERLITE
POWER SAVING MODES (Cont’d)
9.4.2.1 HALT Mode Recommendations
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
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1
ST7LITE0, ST7SUPERLITE
10 I/O PORTS
10.1 INTRODUCTION
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
The I/O ports offer different functional modes:
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the EICR register
must be modified.
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
10.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
10.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
DR register value and output pin status:
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
DR
0
Push-pull
Open-drain
Vss
V
V
SS
DD
1
Floating
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 28
Note: When switching from input to output mode,
the DR register has to be written first to drive the
correct level on the pin as soon as the port is con-
figured as an output.
10.2.3 Alternate Functions
10.2.1 Input Modes
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming under the following
conditions:
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
– When the signal is coming from an on-chip pe-
ripheral, the I/O pin is automatically configured in
output mode (push-pull or open drain according
to the peripheral).
Different input modes can be selected by software
through the OR register.
Note: Writing the DR register modifies the latch
value but does not affect the pin status.
– When the signal is going to an on-chip peripher-
al, the I/O pin must be configured in floating input
mode. In this case, the pin state is also digitally
readable by addressing the DR register.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
Notes:
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the
EICR register.
– Input pull-up configuration can cause unexpect-
ed value at the input of the alternate peripheral
input.
– When an on-chip peripheral use a pin as input
and output, this pin has to be configured in input
floating mode.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
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ST7LITE0, ST7SUPERLITE
I/O PORTS (Cont’d)
Figure 28. I/O Port General Block Diagram
ALTERNATE
OUTPUT
1
0
REGISTER
ACCESS
P-BUFFER
(see table below)
V
DD
ALTERNATE
ENABLE
PULL-UP
(see table below)
DR
DDR
OR
V
DD
PULL-UP
CONDITION
PAD
If implemented
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
EXTERNAL
INTERRUPT
SOURCE (ei )
FROM
OTHER
BITS
x
POLARITY
SELECTION
Table 9. I/O Port Mode Options
Configuration Mode
Diodes
Pull-Up
P-Buffer
to V
to V
SS
DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
On
Off
Output
Off
Open Drain (logic level)
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
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ST7LITE0, ST7SUPERLITE
I/O PORTS (Cont’d)
Table 10. I/O Port Configurations
Hardware Configuration
DR REGISTER ACCESS
V
DD
R
PULL-UP
CONDITION
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
FROM
OTHER
PINS
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
DR REGISTER ACCESS
V
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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ST7LITE0, ST7SUPERLITE
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
Enable Exit
Control from
Exit
from
Halt
Event
Flag
Interrupt Event
Bit
Wait
External interrupt on
selected external
event
DDRx
ORx
-
Yes
Yes
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
10.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 29 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
10.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to Section 13.8.
10.4 LOW POWER MODES
Figure 29. Interrupt I/O Port State Transitions
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
01
00
10
11
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
INPUT
floating/pull-up
interrupt
INPUT
floating
(reset state)
OUTPUT
open-drain
OUTPUT
push-pull
= DDR, OR
XX
The I/O port register configurations are summa-
rised as follows.
Table 11. Port Configuration
Input (DDR=0)
Output (DDR=1)
OR = 0
Port
Pin name
PA7
OR = 0
floating
floating
floating
floating
floating
floating
floating
OR = 1
pull-up interrupt
pull-up
OR = 1
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
open drain
open drain
open drain
open drain
open drain
open drain
open drain
Port A
PA6:1
PA0
pull-up interrupt
pull-up
PB4
PB3
pull-up interrupt
pull-up
Port B
PB2:1
PB0
pull-up interrupt
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ST7LITE0, ST7SUPERLITE
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
Reset Value
MSB
0
LSB
0
0000h
0001h
0002h
0003h
0004h
0005h
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PADDR
Reset Value
MSB
0
LSB
0
PAOR
Reset Value
MSB
0
LSB
0
PBDR
Reset Value
MSB
1
LSB
0
PBDDR
Reset Value
MSB
0
LSB
0
PBOR
Reset Value
MSB
0
LSB
0
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ST7LITE0, ST7SUPERLITE
11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT)
11.1.1 Introduction
■ Watchdog
– Enabled by hardware or software (configura-
ble by option byte)
– Optional reset on HALT instruction (configura-
ble by option byte)
– Automatically resets the device unless disable
bit is refreshed
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 8-bit
upcounter with two software-selectable timebase
periods, an 8-bit input capture register and watch-
dog function.
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
11.1.2 Main Features
■ Realtime Clock
– 8-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz f
– Maskable timebase interrupt
■ Input Capture
)
OSC
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
Figure 30. Lite Timer Block Diagram
f
LTIMER
To 12-bit AT TImer
f
WDG
WATCHDOG
WATCHDOG RESET
f
/32
OSC
/2
1
0
Timebase
1 or 2 ms
(@ 8MHz
8-bit UPCOUNTER
f
LTIMER
f
)
OSC
LTICR
8
8-bit
LTIC
INPUT CAPTURE
REGISTER
LTCSR
WDG
RF
ICIE
7
ICF
TB
TBIE
TBF
WDGE WDGD
0
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
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ST7LITE0, ST7SUPERLITE
LITE TIMER (Cont’d)
11.1.3 Functional Description
A Watchdog reset can be forced at any time by
setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated
by setting the WDGE bit and then the WDGRF bit
has to be set.
The value of the 8-bit counter cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of f
/32. A
OSC
counter overflow event occurs when the counter
rolls over from F9h to 00h. If f = 8 MHz, then
The WDGRF bit also acts as a flag, indicating that
the Watchdog was the source of the reset. It is au-
tomatically cleared after it has been read.
OSC
the time period between two counter overflow
events is 1 ms. This period can be doubled by set-
ting the TB bit in the LTCSR register.
Caution: When the WDGRF bit is set, software
must clear it, otherwise the next time the watchdog
is enabled (by hardware or software), the micro-
controller will be immediately reset.
When the timer overflows, the TBF bit is set by
hardware and an interrupt request is generated if
the TBIE is set. The TBF bit is cleared by software
reading the LTCSR register.
Hardware Watchdog Option
11.1.3.1 Watchdog
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGE bit in
the LTCSR is not used.
The watchdog is enabled using the WDGE bit.
The normal Watchdog timeout is 2ms (@ = 8 MHz
f
), after which it then generates a reset.
Refer to the Option Byte description in the "device
configuration and ordering information" section.
OSC
To prevent this watchdog reset occuring, software
must set the WDGD bit. The WDGD bit is cleared
Using Halt Mode with the Watchdog (option)
by hardware after t
. This means that software
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
WDG
must write to the WDGD bit at regular intervals to
prevent a watchdog reset occurring. Refer to Fig-
ure 31.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the Lite Timer
stops counting and is no longer able to generate a
Watchdog reset until the microcontroller receives
an external interrupt or a reset.
If the watchdog is not enabled immediately after
reset, the first watchdog timeout will be shorter
than 2ms, because this period is counted starting
from reset. Moreover, if a 2ms period has already
elapsed after the last MCU reset, the watchdog re-
set will take place as soon as the WDGE bit is set.
For these reasons, it is recommended to enable
the Watchdog immediately after reset or else to
set the WDGD bit before the WGDE bit so a
watchdog reset will not occur for at least 2ms.
If an external interrupt is received, the WDG re-
starts counting after 256 CPU clocks. If a reset is
generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller.
Note: Software can use the timebase feature to
set the WDGD bit at 1 or 2 ms intervals.
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1
ST7LITE0, ST7SUPERLITE
Figure 31. Watchdog Timing Diagram
HARDWARE CLEARS
WDGD BIT
t
WDG
(2ms @ 8MHz f
)
OSC
f
WDG
WDGD BIT
INTERNAL
WATCHDOG
RESET
SOFTWARE SETS
WDGD BIT
WATCHDOG RESET
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ST7LITE0, ST7SUPERLITE
LITE TIMER (Cont’d)
Input Capture
ACTIVE-HALT No effect on Lite timer
HALT
Lite timer stops counting
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the ICAP1 pin. When an input cap-
ture occurs, the ICF bit is set and the LTICR regis-
ter contains the MSB of the free-running up-
counter. An interrupt is generated if the ICIE bit is
set. The ICF bit is cleared by reading the LTICR
register.
11.1.5 Interrupts
Exit
from
Active-
Halt
Enable Exit Exit
Control from from
Interrupt Event
Event
Flag
Bit
Wait Halt
Timebase
Event
TBF
ICF
TBIE
ICIE
Yes
Yes
No
No
Yes
No
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
IC Event
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
11.1.4 Low Power Modes
Mode
SLOW
WAIT
Description
No effect on Lite timer
(this peripheral is driven directly
They generate an interrupt if the enable bit is set in
the LTCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
by f
/32)
OSC
No effect on Lite timer
Figure 32. Input Capture Timing Diagram.
4µs
(@ 8MHz f
)
OSC
fCPU
fOSC/32
CLEARED
BY S/W
READING
LTIC REGISTER
8-bit COUNTER
LTIC PIN
01h
02h
03h
04h
05h
06h
07h
ICF FLAG
07h
LTICR REGISTER
xxh
04h
t
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1
ST7LITE0, ST7SUPERLITE
LITE TIMER (Cont’d)
11.1.6 Register Description
0: No counter overflow
1: A counter overflow has occurred
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 2 = WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to
force a watchdog reset. It is set by hardware when
a watchdog reset occurs and cleared by hardware
or by software. It is cleared by hardware only when
an LVD reset occurs. It can be cleared by software
after a read access to the LTCSR register.
0: No watchdog reset occurred.
7
0
ICIE
ICF
TB
TBIE
TBF WDGR WDGE WDGD
Bit 7 = ICIE Interrupt Enable.
1: Force a watchdog reset (write), or, a watchdog
reset occurred (read).
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 1 = WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
1: Watchdog enabled
Bit 0 = WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hard-
ware at the end of each t
0: Watchdog reset not delayed
period.
WDG
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
1: Watchdog reset delayed
LITE TIMER INPUT CAPTURE REGISTER
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = t
1: Timebase period = t
MHz)
* 8000 (1ms @ 8 MHz)
* 16000 (2ms @ 8
OSC
OSC
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bit 4 = TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
Bit 3 = TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
Table 13. Lite Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
LTCSR
Reset Value
ICIE
0
ICF
x
TB
0
TBIE
0
TBF
0
WDGRF
0
WDGE
0
WDGD
0
0B
0C
LTICR
Reset Value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
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ST7LITE0, ST7SUPERLITE
11.2 12-BIT AUTORELOAD TIMER (AT)
11.2.1 Introduction
■ PWM signal generator
■ Frequency range 2KHz-4MHz (@ 8 MHz f
)
CPU
The 12-bit Autoreload Timer can be used for gen-
eral-purpose timing functions. It is based on a free-
running 12-bit upcounter with a PWM output chan-
nel.
– Programmable duty-cycle
– Polarity control
– Maskable Compare interrupt
■ Output Compare Function
11.2.2 Main Features
■ 12-bit upcounter with 12-bit autoreload register
(ATR)
■ Maskable overflow interrupt
Figure 33. Block Diagram
OVF INTERRUPT
REQUEST
ATCSR
7
0
0
0
0
CK1 CK0 OVF OVFIECMPIE
CMP INTERRUPT
REQUEST
CMPF0
f
LTIMER
(1 ms timebase
@ 8MHz)
f
COUNTER
12-BIT UPCOUNTER
Update on OVF Event
CNTR
ATR
f
CPU
12-BIT AUTORELOAD VALUE
OE0 bit
DCR0L
DCR0H
CMPF0 bit
OE0 bit
OP0 bit
Preload
Preload
0
1
POL-
ARITY
COMP-
PARE
f
PWM
PWM0
on OVF Event
IF OE0=1
12-BIT DUTY CYCLE VALUE (shadow)
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ST7LITE0, ST7SUPERLITE
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.3 Functional Description
PWM Mode
When a upcounter overflow occurs (OVF event),
the ATR value is loaded in the upcounter, the
preloaded Duty cycle value is transferred to the
Duty Cycle register and the PWM0 signal is set to
a high level. When the upcounter matches the
DCRx value the PWM0 signals is set to a low level.
To obtain a signal on the PWM0 pin, the contents
of the DCR0 register must be greater than the con-
tents of the ATR register.
This mode allows a Pulse Width Modulated sig-
nals to be generated on the PWM0 output pin with
minimum core processing overhead. The PWM0
output signal can be enabled or disabled using the
OE0 bit in the PWMCR register. When this bit is
set the PWM I/O pin is configured as output push-
pull alternate function.
The polarity bit can be used to invert the output
signal.
Note: CMPF0 is available in PWM mode (see
PWM0CSR description on page 55).
The maximum available resolution for the PWM0
duty cycle is:
PWM Frequency and Duty Cycle
The PWM signal frequency (f
) is controlled by
PWM
Resolution = 1 / (4096 - ATR)
the counter period and the ATR register value.
Note: To get the maximum resolution (1/4096), the
ATR register must be 0. With this maximum reso-
lution and assuming that DCR=ATR, a 0% or
100% duty cycle can be obtained by changing the
polarity .
f
= f / (4096 - ATR)
PWM
COUNTER
Following the above formula, if f
maximum value of f
value = 4094), and the minimum value is 2 kHz
(ATR register value = 0).
is 8 MHz, the
CPU
is 4 Mhz (ATR register
PWM
Caution: As soon as the DCR0H is written, the
compare function is disabled and will start only
when the DCR0L value is written. If the DCR0H
write occurs just before the compare event, the
signal on the PWM output may not be set to a low
level. In this case, the DCRx register should be up-
dated just after an OVF event. If the DCR and ATR
values are close, then the DCRx register shouldbe
updated just before an OVF event, in order not to
miss a compare event and to have the right signal
applied on the PWM output.
Note: The maximum value of ATR is 4094 be-
cause it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the
DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution
below.
Figure 34. PWM Function
4095
DUTY CYCLE
REGISTER
(DCR0)
AUTO-RELOAD
REGISTER
(ATR)
000
t
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
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ST7LITE0, ST7SUPERLITE
12-BIT AUTORELOAD TIMER (Cont’d)
Figure 35. PWM Signal Example
fCOUNTER
ATR= FFDh
FFFh
COUNTER
FFDh
FFEh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
t
Output Compare Mode
The compare between DCRx or the shadow regis-
ter and the timer counter is locked until DCR0L is
written.
To use this function, the OE bit must be 0, other-
wise the compare is done with the shadow register
instead of the DCRx register. Software must then
write a 12-bit value in the DCR0H and DCR0L reg-
isters. This value will be loaded immediately (with-
out waiting for an OVF event).
11.2.4 Low Power Modes
Mode
Description
The input frequency is divided
by 32
SLOW
The DCR0H must be written first, the output com-
pare function starts only when the DCR0L value is
written.
WAIT
No effect on AT timer
AT timer halted except if CK0=1,
CK1=0 and OVFIE=1
AT timer halted
ACTIVE-HALT
HALT
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCR0H and DCR0L registers,
the CMPF0 bit in the PWM0CSR register is set
and an interrupt request is generated if the CMPIE
bit is set.
11.2.5 Interrupts
Note: The output compare function is only availa-
ble for DCRx values other than 0 (reset value).
Exit
Enable Exit Exit
Event from
Interrupt
Event
Control from from
1)
Flag
Active-
Halt
Bit
Wait Halt
Caution: At each OVF event, the DCRx value is
written in a shadow register, even if the DCR0L
value has not yet been written (in this case, the
shadow register will contain the new DCR0H value
and the old DCR0L value), then:
Overflow
Event
2)
OVF OVFIE Yes No
Yes
CMP Event CMPFx CMPIE Yes No
No
Note 1: The interrupt events are connected to sep-
arate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in
the ATCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
– If OE=1 (PWM mode): the compare is done be-
tween the timer counter and the shadow register
(and not DCRx)
– if OE=0 (OCMP mode): the compare is done be-
tween the timer counter and DCRx. There is no
PWM signal.
Note 2: only if CK0=1and CK1=0
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ST7LITE0, ST7SUPERLITE
12-BIT AUTORELOAD TIMER (Cont’d)
11.2.6 Register Description
0: OVF interrupt disabled
1: OVF interrupt enabled
TIMER CONTROL STATUS REGISTER (ATC-
SR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and clear by
hardware after a reset. It allows to mask the inter-
rupt generation when CMPF bit is set.
0: CMPF interrupt disabled
7
0
0
0
0
CK1
CK0
OVF OVFIE CMPIE
1: CMPF interrupt enabled
Bit 7:5 = Reserved, must be kept cleared.
COUNTER REGISTER HIGH (CNTRH)
Read only
Reset Value: 0000 0000 (00h)
Bit 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter. The change be-
comes effective after an overflow.
15
0
8
0
0
0
CN11 CN10 CN9
CN8
Counter Clock Selection
CK1 CK0
OFF
0
0
1
1
0
1
0
1
COUNTER REGISTER LOW (CNTRL)
Read only
f
(1 ms timebase @ 8 MHz)
LTIMER
f
CPU
Reset Value: 0000 0000 (00h)
Reserved
7
0
CN7
CN6
CN5
CN4
CN3
CN2
CN1
CN0
Bit 2 = OVF Overflow Flag.
This bit is set by hardware and cleared by software
by reading the ATCSR register. It indicates the
transition of the counter from FFh to ATR value.
0: No counter overflow occurred
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
1: Counter overflow occurred
This 12-bit register is read by software and cleared
by hardware after a reset. The counter is incre-
mented continuously as soon as a counter clock is
selected. To obtain the 12-bit value, software
should read the counter value in two consecutive
read operations, LSB first. When a counter over-
flow occurs, the counter restarts from the value
specified in the ATR register.
Caution:
When set, the OVF bit stays high for 1 f
COUNTER
cycle, (up to 1ms depending on the clock selec-
tion).
Bit 1 = OVFIE Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
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ST7LITE0, ST7SUPERLITE
12-BIT AUTORELOAD TIMER (Cont’d)
AUTO RELOAD REGISTER (ATRH)
Read / Write
Reset Value: 0000 0000 (00h)
PWM0 DUTY CYCLE REGISTER LOW (DCR0L)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
7
0
0
0
0
0
ATR11 ATR10 ATR9 ATR8
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
AUTO RELOAD REGISTER (ATRL)
Read / Write
Bits 15:12 = Reserved, must be kept cleared.
Reset Value: 0000 0000 (00h)
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. The high
register must be written first.
7
0
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
In PWM mode (OE0=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWM0 output signal (see Figure 34). In Output
Compare mode, (OE0=0 in the PWMCR register)
they define the value to be compared with the 12-
bit upcounter value.
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = ATR[11:0] Autoreload Register.
This is a 12-bit register which is written by soft-
ware. The ATR register value is automatically
loaded into the upcounter when an overflow oc-
curs. The register value is used to set the PWM
frequency.
PWM0
CONTROL/STATUS
REGISTER
(PWM0CSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
PWM0 DUTY CYCLE REGISTER HIGH (DCR0H)
Read / Write
Reset Value: 0000 0000 (00h)
0
0
0
0
0
0
OP0 CMPF0
15
0
8
Bit 7:2= Reserved, must be kept cleared.
0
0
0
DCR11 DCR10 DCR9 DCR8
Bit 1 = OP0 PWM0 Output Polarity.
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the polarity
of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 = CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software
by reading the PWM0CSR register. It indicates
that the upcounter value matches the DCR0 regis-
ter value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
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ST7LITE0, ST7SUPERLITE
12-BIT AUTORELOAD TIMER (Cont’d)
PWM OUTPUT CONTROL REGISTER (PWMCR)
Read/Write
Bits 7:1 = Reserved, must be kept cleared.
Reset Value: 0000 0000 (00h)
Bit 0 = OE0 PWM0 Output enable.
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O
pin free for general purpose I/O)
7
0
0
0
0
0
0
0
0
OE0
1: PWM0 output enabled
Table 14. Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ATCSR
Reset Value
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0D
0E
0F
10
11
12
13
17
18
0
0
0
0
0
0
CNTRH
Reset Value
CN11
0
CN10
0
CN9
0
CN8
0
0
CNTRL
Reset Value
CN7
0
CN8
0
CN7
0
CN6
0
CN3
0
CN2
0
CN1
0
CN0
0
ATRH
Reset Value
ATR11
0
ATR10
0
ATR9
0
ATR8
0
0
0
0
0
ATRL
Reset Value
ATR7
0
ATR6
0
ATR5
0
ATR4
0
ATR3
0
ATR2
0
ATR1
0
ATR0
0
PWMCR
Reset Value
OE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM0CSR
Reset Value
OP
0
CMPF0
0
DCR0H
Reset Value
DCR11
0
DCR10
0
DCR9
0
DCR8
0
DCR0L
Reset Value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
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ST7LITE0, ST7SUPERLITE
11.3 SERIAL PERIPHERAL INTERFACE (SPI)
11.3.1 Introduction
11.3.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
Figure 36 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
11.3.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
3 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
CPU
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
■ Write collision, Master Mode Fault and Overrun
flags
Figure 36. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
SOD SSM SSI
0
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 37.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 40) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 37. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 39)
There are two cases depending on the data/clock
timing relationship (see Figure 38):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.3.5.3).
– SS internal must be held high continuously
Figure 38. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 39. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.3 Master Mode Operation
11.3.3.5 Slave Mode Operation
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
In slave mode, the serial clock is received on the
SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 40).
Note: The slave must have the same CPOL
and CPHA settings as the master.
– Manage the SS pin as described in Section
11.3.3.2 and Figure 38. If CPHA=1 SS must
be held low continuously. If CPHA=0 SS must
be held low during byte transmission and
pulled up between each byte to let the slave
write in the shift register.
To operate the SPI in master mode, perform the
following two steps in order (if the SPICSR register
is not written first, the SPICR register setting may
be not taken into account):
1. Write to the SPICSR register:
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
40 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
11.3.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
2. Write to the SPICR register:
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when software
writes a byte in the SPIDR register.
When data transfer is complete:
– The SPIF bit is set by hardware
11.3.3.4 Master Mode Transmit Sequence
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
Clearing the SPIF bit is performed by the following
software sequence:
When data transfer is complete:
– The SPIF bit is set by hardware
1. An access to the SPICSR register while the
SPIF bit is set.
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
2. A write or a read to the SPIDR register.
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Clearing the SPIF bit is performed by the following
software sequence:
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 11.3.5.2).
1. An access to the SPICSR register while the
SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
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ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Clock Phase and Clock Polarity
Figure 40, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 40).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 40. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
61/122
1
ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5 Error Flags
not cleared the SPIF bit issued from the previously
transmitted byte.
11.3.5.1 Master Mode Fault (MODF)
When an Overrun occurs:
Master mode fault occurs when the master device
has its SS pin pulled low.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
When a Master mode fault occurs:
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the device and disables the SPI periph-
eral.
The OVR bit is cleared by reading the SPICSR
register.
– The MSTR bit is reset, thus forcing the device
into slave mode.
11.3.5.3 Write Collision Error (WCOL)
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
Clearing the MODF bit is done through a software
sequence:
1. A read access to the SPICSR register while the
MODF bit is set.
2. A write to the SPICR register.
Write collisions can occur both in master and slave
mode. See also Section 11.3.3.2 Slave Select
Management.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
11.3.5.2 Overrun Condition (OVR)
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
Clearing the WCOL bit is done through a software
sequence (see Figure 41).
Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
RESULT
ter instead of reading it does not
reset the WCOL bit
2nd Step
Read SPIDR
WCOL=0
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1
ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.5.4 Single Master Systems
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 42).
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 42. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
MCU
SCK
Slave
MCU
SCK
Slave
MCU
Slave
MCU
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
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1
ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.6 Low Power Modes
SPI exits from Slave mode, it returns to normal
state immediately.
Mode
Description
No effect on SPI.
Caution: The SPI can wake up the ST7 from Halt
mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low
when the ST7 enters Halt mode. So if Slave selec-
tion is configured as external (see Section
11.3.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
WAIT
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the MCU is woken up by
an interrupt with “exit from HALT mode” ca-
pability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the device.
11.3.7 Interrupts
HALT
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Transfer
Event
SPIF
Yes
Yes
Master Mode Fault
Event
SPIE
MODF
OVR
Yes
Yes
No
No
11.3.6.1 Using the SPI to wakeup the MCU from
Halt mode
Overrun Error
In slave configuration, the SPI is able to wakeup
the ST7 device from HALT mode through a SPIF
interrupt. The data received is subsequently read
from the SPIDR register when the software is run-
ning (interrupt vector fetch). If multiple data trans-
fers have been performed before software clears
the SPIF bit, then the OVR bit is set by hardware.
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
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1
ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.5.1 Master Mode Fault
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
Note: These 2 bits have no effect in slave mode.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 15 SPI Master
mode SCK Frequency.
Table 15. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
0: Divider by 2 enabled
1: Divider by 2 disabled
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 11.3.5.1 Master Mode Fault
(MODF)).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
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1
ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
11.3.3.2 Slave Select Management.
0: Hardware management (SS managed by exter-
nal pin)
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 41).
0: No write collision occurred
1: A write collision has been detected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 11.3.5.2). An interrupt is generated if
SPIE = 1 in SPICSR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 11.3.5.1
Master Mode Fault (MODF)). An SPI interrupt can
be generated if SPIE=1 in the SPICSR register.
This bit is cleared by a software sequence (An ac-
cess to the SPICSR register while MODF=1 fol-
lowed by a write to the SPICR register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
0: No master mode fault detected
1: A fault in master mode has been detected
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 36).
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ST7LITE0, ST7SUPERLITE
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 16. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
31
32
33
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
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1
ST7LITE0, ST7SUPERLITE
11.4 8-BIT A/D CONVERTER (ADC)
11.4.1 Introduction
11.4.3 Functional Description
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 5 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 5 different sources.
11.4.3.1 Analog Power Supply
The block diagram is shown in Figure 43.
V
and V are the high and low level reference
SS
DD
voltage pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
For more details, refer to the Electrical character-
istics section.
11.4.3.2 Input Voltage Amplifier
11.4.2 Main Features
The input voltage can be amplified by a factor of 8
by enabling the AMPSEL bit in the ADAMP regis-
ter.
■ 8-bit conversion
■ Up to 5 channels with multiplexed input
■ Linear successive approximation
■ Dual input range
When the amplifier is enabled, the input range is
0V to 250 mV.
– 0 to V or
DD
For example, if V = 5V, then the ADC can con-
DD
– 0V to 250mV
vert voltages in the range 0V to 250mV with an
ideal resolution of 2.4mV (equivalent to 11-bit res-
■ Data register (DR) which contains the results
■ Conversion complete status flag
■ On/off bit (to reduce consumption)
olution with reference to a V to V range).
SS
DD
For more details, refer to the Electrical character-
istics section.
■ Fixed gain operational amplifier (x8) (not
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPSEL bit.
available on ST7LITES5 devices)
Figure 43. ADC Block Diagram
f
f
DIV 4
ADC
CPU
1
0
DIV 2
0
1
(ADCAMP Register)
0
SLOW
bit
7
EOC SPEEDADON
0
0
CH2 CH1 CH0
ADCCSR
3
AIN0
AIN1
HOLD CONTROL
R
ADC
ANALOG TO DIGITAL
CONVERTER
x 1 or
x 8
ANALOG
MUX
C
ADC
D5
AINx
AMPSEL bit
(ADCAMP Register)
ADCDR
D7
D6
D4
D3
D2
D1
D0
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ST7LITE0, ST7SUPERLITE
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.3.3 Digital A/D Conversion Result
ADC Configuration
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
If the input voltage (V ) is greater than or equal
AIN
to V
(high-level voltage reference) then the
DDA
conversion result in the DR register is FFh (full
scale) without overflow indication.
In the CSR register:
– Select the CH[2:0] bits to assign the analog
channel to be converted.
If input voltage (V ) is lower than or equal to
AIN
V
(low-level voltage reference) then the con-
SSA
ADC Conversion
version result in the DR register is 00h.
In the CSR register:
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
– Set the ADON bit to enable the A/D converter
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
R
is the maximum recommended impedance
When a conversion is complete
AIN
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
– The EOC bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
11.4.3.4 A/D Conversion Phases
A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
The A/D conversion is based on two conversion
phases as shown in Figure 44:
■ Sample capacitor loading [duration: t
]
SAMPLE
Figure 44. ADC Conversion Timings
During this phase, the V
input voltage to be
AIN
measured is loaded into the C
capacitor.
sample
ADC
ADON
t
CONV
ADCCSR WRITE
OPERATION
■ A/D conversion [duration: t
]
HOLD
During this phase, the A/D conversion is
t
HOLD
computed (8 successive approximations cycles)
HOLD
CONTROL
and the C
sample capacitor is disconnected
ADC
from the analog input pin to get the optimum
analog to digital conversion accuracy.
t
SAMPLE
EOC BIT SET
■ The total conversion time:
t
t
+ t
CONV = SAMPLE HOLD
11.4.4 Low Power Modes
While the ADC is on, these two phases are contin-
uously repeated.
Mode
WAIT
Description
No effect on A/D Converter
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilization time before ac-
curate conversions can be performed.
HALT
11.4.3.5 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 11.4.6 for the bit defini-
tions and to Figure 44 for the timings.
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.4.5 Interrupts
None
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ST7LITE0, ST7SUPERLITE
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write
DATA REGISTER (ADCDAT)
Read Only
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
EOC SPEED ADON
0
0
CH2
CH1
CH0
D7
D6
D5
D4
D3
D2
D1
D0
Bit 7 = EOC Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bits 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the EOC flag.
AMPLIFIER CONTROL REGISTER (ADCAMP)
Read/Write
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Reset Value: 0000 0000 (00h)
7
0
0
0
Bit 5 = ADON A/D Converter and Amplifier On
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
AMP-
SEL
0
0
0
SLOW
0
Bit 7:4 = Reserved. Forced by hardware to 0.
Note: Amplifier not available on ST7LITES5
devices
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Bit 4:3 = Reserved. must always be cleared.
f
SLOW SPEED
ADC
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
f
/2
0
0
1
0
1
x
CPU
f
CPU
f
/4
CPU
1
Channel Pin
CH2
CH1
CH0
Bit 2 = AMPSEL Amplifier Selection Bit
AIN0
AIN1
AIN2
AIN3
AIN4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
This bit is set and cleared by software. For
ST7LITES5 devices, this bit must be kept at its re-
set value (0).
0: Amplifier is not selected
1: Amplifier is selected
Note: When AMPSEL=1 it is mandatory that f
be less than or equal to 2 MHz.
ADC
Notes:
1. The number of pins AND the channel selection
varies according to the device. Refer to the device
pinout.
Bit 1:0 = Reserved. Forced by hardware to 0.
2. A write to the ADCCSR register (with ADON set)
aborts the current conversion, resets the EOC bit
and starts a new conversion.
Note: If ADC settings are changed by writing the
ADCAMP register while the ADC is running, a
dummy conversion is needed before obtaining re-
sults with the new settings.
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ST7LITE0, ST7SUPERLITE
Table 17. ADC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ADCCSR
Reset Value
EOC
0
SPEED
0
ADON
0
CH2
0
CH1
0
CH0
0
34h
35h
0
0
ADCDAT
Reset Value
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
SLOW
0
AMPSEL
0
ADCAMP
Reset Value
36h
0
0
0
0
0
0
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ST7LITE0, ST7SUPERLITE
12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
Indexed
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 18. ST7 Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer
Size
(Hex.)
Destination/
Source
Length
(Bytes)
Mode
Syntax
Inherent
Immediate
Short
nop
+ 0
+ 1
+ 1
+ 2
ld A,#$55
ld A,$10
Direct
Direct
00..FF
Long
ld A,$1000
0000..FFFF
+ 0 (with X register)
+ 1 (with Y register)
No Offset
Direct
Indexed
ld A,(X)
00..FF
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Direct
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
0000..FFFF
00..FF
Indirect
Indirect
Indirect
Indirect
Direct
00..FF
00..FF
00..FF
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
0000..FFFF
00..1FE
Indexed
Indexed
ld A,([$10.w],X) 0000..FFFF
1)
1)
jrne loop
PC-128/PC+127
Indirect
Direct
jrne [$10]
PC-128/PC+127
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
bset $10,#7
bset [$10],#7
Bit
Indirect
Direct
00..FF
Bit
Relative btjt $10,#7,skip 00..FF
Relative btjt [$10],#7,skip 00..FF
Bit
Indirect
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.
72/122
1
ST7LITE0, ST7SUPERLITE
ST7 ADDRESSING MODES (Cont’d)
12.1.1 Inherent
12.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
IRET
SIM
12.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
RSP
LD
Indexed (No Offset)
CLR
Clear
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Indexed (Short)
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
CPL, NEG
MUL
Indexed (long)
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
SWAP
12.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
12.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
LD
Load
CP
Compare
Indirect (short)
BCP
Bit Compare
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
73/122
1
ST7LITE0, ST7SUPERLITE
ST7 ADDRESSING MODES (Cont’d)
12.1.6 Indirect Indexed (Short, Long)
SWAP
Swap Nibbles
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
CALL, JP
Call or Jump subroutine
12.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Function
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Instructions
JRxx
Conditional Jump
Call Relative
Indirect Indexed (Short)
CALLR
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Indirect Indexed (Long)
Relative (Direct)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the ad-
dress follows the opcode.
Table 19. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Addition/subtrac-
tion operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions Only
CLR
Function
Clear
INC, DEC
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
TNZ
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
74/122
1
ST7LITE0, ST7SUPERLITE
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
The instructions are described with one to four
bytes.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PIX 92 Replace an instruction using direct, di-
rect bit, or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PC
Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
75/122
1
ST7LITE0, ST7SUPERLITE
INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
M
M
M
Addition
A
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
0
I
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
H
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
JRH
H = 1 ?
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I = 1
I = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
Jump if I = 0
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
Jump if Z = 0 (not equal)
Jump if C = 1
N = 1 ?
N = 0 ?
Z = 1 ?
Z = 0 ?
C = 1 ?
JRNC
JRULT
Jump if C = 0
C = 0 ?
Jump if C = 1
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
76/122
1
ST7LITE0, ST7SUPERLITE
INSTRUCTION GROUPS (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
0
0
Negate (2’s compl)
No Operation
OR operation
Pop from the Stack
neg $10
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
POP
reg
CC
M
M
M
H
I
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
reg, CC
I = 0
0
RLC
RRC
RSP
SBC
SCF
SIM
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I = 1
1
SLA
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Subtraction
N
N
N
N
M
SWAP nibbles
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
Test for Neg & Zero
S/W trap
S/W interrupt
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
M
N
Z
77/122
1
ST7LITE0, ST7SUPERLITE
13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
13.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 46.
13.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 46. Pin input voltage
devices with an ambient temperature at T =25°C
A
ST7 PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
IN
13.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =5V (for the 4.5V≤V ≤5.5V
A
DD
DD
voltage range), V =3.75V (for the 3V≤V ≤4.5V
DD
DD
voltage range) and
V
=2.7V (for the
DD
2.4V≤V ≤3V voltage range). They are given only
as design guidelines and are not tested.
DD
13.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
13.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 45.
Figure 45. Pin loading conditions
ST7 PIN
C
L
78/122
1
ST7LITE0, ST7SUPERLITE
13.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
13.2.1 Voltage Characteristics
Symbol
- V
Ratings
Maximum value
7.0
Unit
V
Supply voltage
DD
SS
V
1) & 2)
V
Input voltage on any pin
VSS-0.3 to VDD+0.3
IN
ESD(HBM)
V
Electrostatic discharge voltage (Human Body Model)
Electrostatic discharge voltage (Machine Model)
see section 13.7.2 on page 91
V
ESD(MM)
13.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
100
100
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on RESET pin
I
50
IO
mA
- 25
± 5
± 5
± 20
2) & 4)
2)
I
INJ(PIN)
5) & 6)
Injected current on any other pin
5)
ΣI
Total injected current (sum of all I/O and control pins)
INJ(PIN)
13.2.3 Thermal Characteristics
Symbol
Ratings
Value
Unit
T
Storage temperature range
-65 to +150
°C
STG
T
Maximum junction temperature (see Section 14.2 THERMAL CHARACTERISTICS)
J
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the device if an unintentional internal reset
DD
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V or V according to their reset configuration.
DD
SS
2. When the current limitation is not possible, the V absolute maximum rating must be respected, otherwise refer to
IN
I
specification. A positive injection is induced by V >V while a negative injection is induced by V <V
.
INJ(PIN)
IN
DD
IN
SS
3. All power (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
mum current injection on four I/O port pins of the device.
maxi-
INJ(PIN)
6. True open drain I/O port pins do not accept positive injection.
79/122
1
ST7LITE0, ST7SUPERLITE
13.3 OPERATING CONDITIONS
13.3.1 General Operating Conditions: Suffix 6 Devices
T = -40 to +85°C unless otherwise specified.
A
Symbol
Parameter
Conditions
Min
2.4
2.7
3.3
0
Max
5.5
5.5
5.5
16
Unit
f
f
f
= 8 MHz. max., T = 0 to 70°C
OSC
OSC
OSC
A
V
Supply voltage
= 8 MHz. max.
= 16 MHz. max.
≥3.3V
V
DD
V
V
V
DD
DD
DD
External clock frequency on
CLKIN pin
f
≥2.4V, T = 0 to +70°C
MHz
CLKIN
A
0
8
≥2.7V
Figure 47. f
Maximum Operating Frequency Versus VDD Supply Voltage
CLKIN
FUNCTIONALITY
GUARANTEED
IN THIS AREA
f
[MHz]
CLKIN
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
4
FUNCTIONALITY
GUARANTEED
IN THIS AREA
1
0
AT T 0 to 70°C
A
SUPPLY VOLTAGE [V]
5.5
2.7
2.0
2.4
3.3
3.5
4.0
4.5
5.0
80/122
1
ST7LITE0, ST7SUPERLITE
13.3.2 Operating Conditions with Low Voltage Detector (LVD)
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
4.00
3.40
2.65
4.25
3.60
2.90
4.50
3.80
3.15
Reset release threshold
V
IT+
(LVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
3.80
3.20
2.40
4.05
3.40
2.70
4.30
3.65
2.90
Reset generation threshold
V
V
IT-
(LVD)
(V fall)
DD
LVD voltage threshold hysteresis
V
-V
IT-
(LVD)
200
mV
µs/V
ns
hys
IT+
(LVD)
1)
Vt
V
rise time rate
20
20000
150
POR
DD
t
I
Filtered glitch delay on V
DD
Not detected by the LVD
g(VDD)
)
LVD/AVD current consumption
200
µA
DD(LVD
Notes:
1. Not tested in production. The V rise time rate condition is needed to ensure a correct device power-on and LVD reset.
DD
When the V slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T = -40 to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
High Threshold
Med. Threshold
Low Threshold
Min
Typ
Max
Unit
4.40
3.90
3.20
4.70
4.10
3.40
5.00
4.30
3.60
1=>0 AVDF flag toggle threshold
V
IT+
(AVD)
(V rise)
DD
V
High Threshold
Med. Threshold
Low Threshold
4.30
3.70
2.90
4.60
3.90
3.20
4.90
4.10
3.40
0=>1 AVDF flag toggle threshold
V
V
IT-
(AVD)
(V fall)
DD
AVD voltage threshold hysteresis
V
-V
150
mV
V
hys
IT+
IT-
(AVD)
(AVD)
Voltage drop between AVD flag set
and LVD reset activation
∆V
V
fall
TBD
0.45
IT-
DD
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
Symbol
Parameter
Conditions
Min
2.4
2.4
3.3
Typ
Max
5.5
Unit
V
Internal RC Oscillator operating voltage
x4 PLL operating voltage
DD(RC)
V
V
3.3
V
DD(x4PLL)
DD(x8PLL)
x8 PLL operating voltage
5.5
PLL
input
clock
t
PLL Startup time
60
STARTUP
(f
)
PLL
cycles
81/122
1
ST7LITE0, ST7SUPERLITE
OPERATING CONDITIONS (Cont’d)
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.
13.3.4.1 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 4.5 to 5.5V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C,V =5V
Min
Typ
760
Max
Unit
Internal RC oscillator fre-
quency
A
DD
f
kHz
RC
2 )
RCCR = RCCR0 ,T =25°C,V =5V
1000
A
DD
T =25°C,V =4.5 to 5.5V
-1
-5
+1
%
%
%
A
DD
Accuracy of Internal RC
oscillator with
RCCR=RCCR0
ACC
T =-40 to +85°C,V =5V
+2
RC
A
DD
2)
1)
1)
T =0 to +85°C,V =4.5 to 5.5V
-2
+2
A
DD
RC oscillator current con-
sumption
1)
I
T =25°C,V =5V
970
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =5V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
1)
x8 PLL input clock
1
PLL
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x8 PLL Accuracy
PLL jitter period
4)
f
f
f
= 1MHz@T =25°C,V =4.5 to 5.5V
0.1
RC
RC
RC
A
DD
ACC
PLL
4)
= 1MHz@T =-40 to +85°C,V =5V
0.1
%
A
DD
3)
t
= 1MHz
8
kHz
%
w(JIT)
3)
JIT
PLL jitter (∆f
/f )
1
PLL
CPU CPU
1)
I
PLL current consumption T =25°C
600
µA
DD(PLL)
A
Notes:
1. Data based on characterization results, not tested in production
2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ T =25°C, V =5V. See “INTERNAL RC OS-
A
DD
CILLATOR ADJUSTMENT” on page 23
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy.
STAB
PLL
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 12 on page 24.
PLL
STAB
82/122
1
ST7LITE0, ST7SUPERLITE
OPERATING CONDITIONS (Cont’d)
13.3.4.2 Devices with ‘”6” order code suffix (tested for T = -40 to +85°C) @ V = 2.7 to 3.3V
A
DD
Symbol
Parameter
Conditions
RCCR = FF (reset value), T =25°C, V = 3.0V
Min
Typ
560
700
Max
Unit
Internal RC oscillator fre-
quency
A
DD
f
kHz
RC
2)
RCCR=RCCR1 ,T =25°C,V = 3V
A
DD
T =25°C,V =3V
-2
+2
+25
15
%
%
%
A
DD
Accuracy of Internal RC
ACC
oscillator when calibrated T =25°C,V =2.7 to 3.3V
-25
-15
RC
A
DD
1)2)
with RCCR=RCCR1
T =-40 to +85°C,V =3V
A
DD
RC oscillator current con-
sumption
1)
I
T =25°C,V =3V
700
µA
DD(RC)
A
DD
2)
t
f
t
t
RC oscillator setup time T =25°C,V =3V
10
µs
MHz
ms
ms
%
su(RC)
A
DD
1)
x4 PLL input clock
1
PLL
5)
PLL Lock time
2
4
LOCK
STAB
5)
PLL Stabilization time
x4 PLL Accuracy
PLL jitter period
4)
4)
f
f
f
= 1MHz@T =25°C,V =2.7 to 3.3V
0.1
0.1
RC
RC
RC
A
DD
ACC
PLL
= 1MHz@T =40 to +85°C,V = 3V
%
A
DD
3)
t
= 1MHz
8
1
kHz
%
w(JIT)
3)
JIT
PLL jitter (∆f
/f
)
PLL
CPU CPU
1)
I
PLL current consumption T =25°C
190
µA
DD(PLL)
A
Notes:
1. Data based on characterization results, not tested in production
2. RCCR1 is a factory-calibrated setting for 700kHz with ±2% accuracy @ T =25°C, V =3V. See “INTERNAL RC OS-
A
DD
CILLATOR ADJUSTMENT” on page 23.
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
is required to reach ACC
accuracy
STAB
PLL
5. After the LOCKED bit is set ACC
is max. 10% until t
has elapsed. See Figure 12 on page 24.
PLL
STAB
83/122
1
ST7LITE0, ST7SUPERLITE
OPERATING CONDITIONS (Cont’d)
Figure 48. RC Osc Freq vs V
@ T =25°C
Figure 49. RC Osc Freq vs V
DD
DD
A
(Calibrated with RCCR1: 3V @ 25°C)
(Calibrated with RCCR0: 5V@ 25°C)
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°
0°
25°
90°
105°
130°
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
2.5
3
3.5
4
4.5
5
5.5
6
Vdd (V)
VDD (V)
Figure 50. Typical RC oscillator Accuracy vs
temperature @ V =5V
DD
(Calibrated with RCCR0: 5V @ 25°C
Figure 51. RC Osc Freq vs V and RCCR Value
DD
1.80
1.60
1.40
1.20
2
(
)
*
1
0
(
)
*
-1
-2
-3
-4
1.00
0.80
0.60
0.40
0.20
0.00
rccr=00h
rccr=64h
rccr=80h
rccr=C0h
rccr=FFh
(
)
*
-5
-45
0
25
85
125
Temperature (°C)
(
) tested in production
*
2.4 2.7
3
3.3 3.75
4
4.5
5
5.5
6
Vdd (V)
84/122
1
ST7LITE0, ST7SUPERLITE
OPERATING CONDITIONS (Cont’d)
Figure 52. PLL ∆f /f versus time
CPU CPU
/f
∆f
CPU CPU
Max
0
t
Min
t
t
w(JIT)
w(JIT)
Figure 53. PLLx4 Output vs CLKIN frequency
Figure 54. PLLx8 Output vs CLKIN frequency
7.00
6.00
5.00
11.00
9.00
7.00
5.00
3.00
1.00
3.3
5.5
5
4.00
3
2.7
4.5
4
3.00
2.00
1.00
0.85
0.9
1
1.5
2
2.5
1
1.5
2
2.5
3
External Input Clock Frequency (MHz)
External Input Clock Frequency (MHz)
Note: f
= f
/2*PLL4
OSC
CLKIN
Note: f
= f
/2*PLL8
CLKIN
OSC
85/122
1
ST7LITE0, ST7SUPERLITE
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
T = -40 to +125°C unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
4.50
Max
7.00
Unit
1)
Supply current in RUN mode
Supply current in WAIT mode
Supply current in SLOW mode
Supply current in SLOW WAIT mode
f
f
f
f
=8MHz
CPU
CPU
CPU
CPU
2)
1.75
0.75
0.65
0.50
5
2.70
1.13
1
=8MHz
mA
3)
4)
=500kHz
=500kHz
I
DD
10
-40°C≤T ≤+85°C
A
Supply current in HALT mode
µA
100
T = +125°C
A
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
DD
SS
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (CLKIN)
DD
SS
driven by external square wave, LVD disabled.
3. SLOW mode selected with f
SS
based on f
divided by 32. All I/O pins in input mode with a static value at V or
OSC DD
CPU
V
(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f
based on f
divided by 32. All I/O pins in input mode with a static value at
CPU
OSC
V
or V (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
DD
SS
Figure 55. Typical I in RUN vs. f
Figure 56. Typical I in SLOW vs. f
CPU
DD
CPU
DD
8MHz
5.0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
4MHz
4.0
1MHz
3.0
500kHz
250kHz
125kHz
2.0
1.0
0.0
2.4
2.7
3.7
4.5
5
5.5
2.4
2.7
3.7
4.5
5
5.5
Vdd (V)
VDD (V)
Figure 57. Typical I in WAIT vs. f
Figure 58. Typical I in SLOW-WAIT vs. f
DD
CPU
DD
CPU
8MHz
2.0
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
4MHz
1.5
1MHz
500kHz
250kHz
125kHz
1.0
0.5
0.0
2.4
2.7
3.7
Vdd (V)
4.5
5
5.5
2.4
2.7
3.7
4.5
5
5.5
Vdd (V)
86/122
1
ST7LITE0, ST7SUPERLITE
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 59. Typical I vs. Temperature
DD
at V = 5V and f
= 8MHz
DD
CPU
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
RUN
WAIT
SLOW
SLOW WAIT
-45
25
90
130
Temperature (°C)
13.4.2 On-chip peripherals
Symbol
Parameter
Conditions
Typ
50
Unit
f
f
f
f
=4MHz
=8MHz
=4MHz
=8MHz
V
V
V
V
V
V
=3.0V
=5.0V
=3.0V
=5.0V
=3.0V
=5.0V
CPU
CPU
CPU
CPU
DD
DD
DD
DD
DD
DD
1)
I
12-bit Auto-Reload Timer supply current
DD(AT)
150
50
2)
I
SPI supply current
µA
DD(SPI)
300
780
1100
3)
I
ADC supply current when converting
f
=4MHz
DD(ADC)
ADC
1. Data based on a differential I measurement between reset configuration (timer stopped) and a timer running in PWM
DD
mode at f =8MHz.
cpu
2. Data based on a differential I measurement between reset configuration and a permanent SPI master communica-
DD
tion (data sent equal to 55h).
3. Data based on a differential I measurement between reset configuration and continuous A/D conversions with am-
DD
plifier off.
87/122
1
ST7LITE0, ST7SUPERLITE
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
13.5.1 General Timings
1
2)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
f
f
=8MHz
c(INST)
CPU
250
10
375
1500
22
3)
tCPU
µs
Interrupt reaction time
t
=8MHz
v(IT)
CPU
t
= ∆t
+ 10
1.25
2.75
v(IT)
c(INST)
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Dt
ish the current instruction execution.
is the number of t
cycles needed to fin-
c(INST)
CPU
88/122
1
ST7LITE0, ST7SUPERLITE
13.6 MEMORY CHARACTERISTICS
T = -40°C to 125°C, unless otherwise specified
A
13.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
1.6
V
RM
13.6.2 FLASH Program Memory
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2.4
5.5
10
V
Operating voltage for Flash write/erase
DD
prog
RET
2)
T =−40 to +85°C
5
Programming time for 1~32 bytes
ms
A
t
T =+25°C
0.24
0.48
Programming time for 1.5 kBytes
s
A
4)
3)
t
Data retention
T =+55°C
20
years
cycles
A
7)
N
Write erase cycles
T =+25°C
10K
RW
A
Read / Write / Erase
modes
= 8MHz, V = 5.5V
6)
2.6
mA
f
I
Supply current
CPU
DD
DD
No Read/No Write Mode
Power down mode / HALT
100
0.1
µA
µA
0
13.6.3 EEPROM Data Memory
Symbol
Parameter
Conditions
Min
Typ
Max
10
Unit
ms
T =−40 to +85°C
5
t
Programming time for 1~32 bytes
A
prog
4)
3)
t
Data retention
T =+55°C
20
years
cycles
ret
A
7)
N
Write erase cycles
T =+25°C
300K
RW
A
Notes:
1. Minimum V supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-
DD
isters (only in HALT mode). Guaranteed by construction, not tested in production.
2. Up to 32 bytes can be programmed at a time.
3. The data retention time increases when the T decreases.
A
4. Data based on reliability test results and monitored in production.
5. Data based on characterization results, not tested in production.
6. Guaranteed by Design. Not tested in production.
7. Design target value pending full product characterization.
89/122
1
ST7LITE0, ST7SUPERLITE
13.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
13.7.1 Functional EMS
(Electro Magnetic Susceptibility)
■ FTB: A Burst of Fast Transient voltage (positive
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
1)
1)
Symbol
Parameter
Conditions
=5V, T =+25°C, f
conforms to IEC 1000-4-2
Neg
Pos
Unit
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
V
=8MHz
OSC
DD
A
V
-0.7
-1.2
>1.5
1.2
FESD
kV
Fast transient voltage burst limits to be ap-
V
=5V, T =+25°C, f
=8MHz
OSC
DD
A
V
plied through 100pF on V and V pins
FFTB
DD DD
conforms to IEC 1000-4-4
to induce a functional disturbance
2)
Figure 60. EMC Recommended power supply connection
ST72XXX
10µF 0.1µF
V
V
DD
SS
ST7
DIGITAL NOISE
FILTERING
V
DD
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC
performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).
90/122
1
ST7LITE0, ST7SUPERLITE
EMC CHARACTERISTICS (Cont’d)
13.7.2 Absolute Electrical Sensitivity
Machine Model Test Sequence
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.
– C is loaded through S1 by the HV pulse gener-
ator.
L
– S1 switches position from generator to ST7.
– A discharge from C to the ST7 occurs.
L
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
13.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 61 and the following test sequences.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST7.
Human Body Model Test Sequence
– C is loaded through S1 by the HV pulse gener-
L
ator.
– S1 switches position from generator to R.
– A discharge from C through R (body resistance)
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
4000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
TBD
A
ESD(MM)
Figure 61. Typical Equivalent ESD Circuits
S1
R=1500Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
HIGH VOLTAGE
PULSE
GENERATOR
ST7
ST7
C =100pF
S2
L
S2
C =200pF
L
HUMAN BODY MODEL
MACHINE MODEL
Notes:
1. Data based on characterization results, not tested in production.
91/122
1
ST7LITE0, ST7SUPERLITE
EMC CHARACTERISTICS (Cont’d)
13.7.2.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 62. For
more details, refer to the AN1181 ST7
application note.
■ LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+85°C
A
V
=5.5V, f
=4MHz, T =+25°C
DLU
A
DD
OSC
A
Figure 62. Simplified Diagram of the ESD Generator for DLU
R
=50MΩ
R =330Ω
D
CH
DISCHARGE TIP
V
V
DD
SS
HV RELAY
C =150pF
S
ST7
ESD
2)
DISCHARGE
RETURN CONNECTION
GENERATOR
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
92/122
1
ST7LITE0, ST7SUPERLITE
EMC CHARACTERISTICS (Cont’d)
13.7.3 ESD Pin Protection Strategy
Standard Pin Protection
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.
To protect the output structure the following ele-
ments are added:
– A diode to V (3a) and a diode from V (3b)
DD
SS
– A protection device between V and V (4)
DD
SS
To protect the input structure the following ele-
ments are added:
– A resistor in series with the pad (1)
– A diode to V (2a) and a diode from V (2b)
DD
SS
– A protection device between V and V (4)
DD
SS
An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 63 and Figure 64 for standard
pins.
Figure 63. Positive Stress on a Standard Pad vs. V
SS
V
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
Path to avoid
V
V
V
SS
SS
Figure 64. Negative Stress on a Standard Pad vs. V
DD
V
DD
DD
(3a)
(3b)
(2a)
(1)
(4)
OUT
IN
Main path
(2b)
V
V
SS
SS
93/122
1
ST7LITE0, ST7SUPERLITE
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
Symbol
Parameter
Input low level voltage
Input high level voltage
Schmitt trigger voltage
Conditions
Min
Typ
Max
Unit
V
0.3xVDD
IL
V
V
0.7xVDD
IH
V
400
mV
1)
hys
hysteresis
I
Input leakage current
V
SS≤V ≤V
DD
±1
L
IN
µA
2)
I
Static current consumption
Floating input mode
200
250
S
V
V
=5V
=3V
50
120
160
5
Weak pull-up equivalent
DD
DD
R
V =V
SS
kΩ
3)
PU
IN
resistor
C
I/O pin capacitance
pF
IO
Output high to low level fall
time
t
t
25
25
1)
f(IO)out
C =50pF
Between 10% and 90%
L
ns
Output low to high level rise
1)
r(IO)out
time
4)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 65). Data based on design simulation and/or technology
characteristics, not tested in production.
3. The R
pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics de-
PU
PU
scribed in Figure 66).
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 65. Two typical Applications with unused I/O Pin
V
ST7XXX
DD
UNUSED I/O PORT
10kΩ
10kΩ
UNUSED I/O PORT
ST7XXX
Note: only external pull-up allowed on ICCCLK pin
Figure 66. Typical I vs. V with V =V
PU
DD
IN
SS
l
90
80
70
60
50
40
30
20
10
0
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
6
Vdd(V)
94/122
1
ST7LITE0, ST7SUPERLITE
I/O PORT PIN CHARACTERISTICS (Cont’d)
13.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD CPU
Symbol
Parameter
Conditions
Min
Max
Unit
I
I
I
I
I
I
=+5mA T ≤85°C
1.0
1.2
IO
IO
IO
IO
IO
IO
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 70)
T ≥85°C
A
=+2mA T ≤85°C
0.4
0.5
A
T ≥85°C
A
1)
V
OL
=+20mA,T ≤85°C
1.3
1.5
A
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 72)
T ≥85°C
A
=+8mA T ≤85°C
0.75
0.85
A
T ≥85°C
A
=-5mA, T ≤85°C
V
V
-1.5
-1.6
A
DD
DD
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 78)
T ≥85°C
A
2)
V
OH
=-2mA T ≤85°C
V
V
-0.8
-1.0
A
DD
DD
T ≥85°C
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 69)
I
=+2mA T ≤85°C
0.5
0.6
IO
A
V
T ≥85°C
A
1)3)
2)3)
1)3)
V
OL
I
I
=+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.5
0.6
IO
A
T ≥85°C
A
=-2mA T ≤85°C
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
V
V
-0.8
-1.0
IO
A
DD
DD
V
OH
T ≥85°C
A
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 68)
I
I
I
=+2mA T ≤85°C
0.6
0.7
IO
IO
IO
A
T ≥85°C
A
V
OL
=+8mA T ≤85°C
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
0.6
0.7
A
T ≥85°C
A
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 75)
=-2mA T ≤85°C
V
V
-0.9
-1.0
2)3)
A
DD
DD
V
OH
T ≥85°C
A
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I
. True open drain I/O pins does not have V
.
IO
VDD
OH
3. Not tested in production, based on characterization results.
Figure 67. Typical V at V =2.4V (standard)
Figure 68. Typical V at V =2.7V (standard)
OL DD
OL
DD
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45°C
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
0.01
1
2
0.01
1
2
lio (mA)
lio (mA)
95/122
1
ST7LITE0, ST7SUPERLITE
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 69. Typical V at V =3.3V (standard)
Figure 70. Typical V at V =5V (standard)
OL DD
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
0.01
1
2
3
4
5
lio (mA)
0.01
1
2
3
lio (mA)
Figure 71. Typical V at V =2.4V (high-sink)
Figure 73. Typical V at V =3V (high-sink)
OL DD
OL
DD
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
6
7
8
9
10
15
6
7
8
9
10
lio (mA)
lio (mA)
Figure 72. Typical V at V =5V (high-sink)
OL
DD
2.50
2.00
1.50
1.00
0.50
0.00
-45
0°C
25°C
90°C
130°C
6
7
8
9
10
15
lio (mA)
20
25
30
35
40
96/122
1
ST7LITE0, ST7SUPERLITE
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 74. Typical V -V at V =2.4V
Figure 76. Typical V -V
at V =3V
DD OH
DD
DD OH
DD
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-0.01
-1
-2
lio (mA)
lio (mA)
Figure 77. Typical V -V
at V =4V
DD
Figure 75. Typical V -V at V =2.7V
DD OH
DD OH
DD
2.50
2.00
1.50
1.00
0.50
0.00
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-4
-5
-0.01
-1
-2
lio (mA)
lio(mA)
Figure 78. Typical V -V at V =5V
DD OH
DD
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-45°C
0°C
25°C
90°C
130°C
-0.01
-1
-2
-3
-4
-5
lio (mA)
97/122
1
ST7LITE0, ST7SUPERLITE
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 79. Typical V vs. V (standard I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.06
0.05
0.04
0.03
0.02
0.01
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3.3
5
2.4
2.7
3.3
5
VDD (V)
VDD (V)
Figure 80. Typical V vs. V (high-sink I/Os)
OL
DD
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-45
-45
0°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
3
5
2.4
3
5
VDD (V)
VDD (V)
Figure 81. Typical V -V vs. V
DD OH
DD
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
-45°C
0°C
-45°C
0°C
25°C
90°C
130°C
25°C
90°C
130°C
2.4
2.7
3
4
5
4
5
VDD
VDD (V)
98/122
1
ST7LITE0, ST7SUPERLITE
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
T = -40°C to 125°C, unless otherwise specified
A
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
V
V
0.3xVDD
IL
V
Input high level voltage
0.7xVDD
IH
1)
V
Schmitt trigger voltage hysteresis
1
V
hys
I =+5mA T ≤85°C
1.0
1.2
IO
A
0.5
T ≥85°C
A
2)
V
Output low level voltage
V
=5V
V
OL
DD
I
=+2mA T ≤85°C
0.4
0.5
IO
A
0.2
T ≥85°C
A
V
V
=5V
=3V
20
20
40
TBD
30
80
DD
3) 1)
R
Pull-up equivalent resistor
kΩ
ON
DD
t
Generated reset pulse duration
Internal reset sources
µs
µs
ns
w(RSTL)out
4)
t
t
External reset pulse hold time
h(RSTL)in
g(RSTL)in
5)
Filtered glitch duration
200
6)7)8)
Figure 82. Typical Application with RESET pin
Recommended
V
DD
ST72XXX
if LVD is disabled
V
V
DD
DD
R
ON
INTERNAL
RESET
0.01µF
0.01µF
4.7kΩ
USER
EXTERNAL
RESET
Filter
5)
CIRCUIT
PULSE
GENERATOR
WATCHDOG
LVD RESET
Required if LVD is disabled
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. The R
ILmax
pull-up equivalent resistor is based on a resistive transistor. Specfied for voltages on RESET pin between
DD
ON
V
and V
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network protects the device against parasitic resets.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in section 13.9.1 on page 99. Otherwise the reset will not be taken into account internally.
IL
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
ified for I
in section 13.2.2 on page 79.
INJ(RESET)
99/122
1
ST7LITE0, ST7SUPERLITE
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating conditions for V
,
DD
f
, and T unless otherwise specified.
OSC
A
Symbol
Parameter
Conditions
Min
f /128
CPU
0.0625
Max
Unit
Master
Slave
f
f
/42
CPU
CPU
f
=8MHz
=8MHz
f
CPU
SCK
SPI clock frequency
MHz
1/t
c(SCK)
0
/24
f
CPU
t
t
r(SCK)
f(SCK)
SPI clock rise and fall time
see I/O port pin description
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 83. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
r(SCK)
t
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
100/122
1
ST7LITE0, ST7SUPERLITE
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 84. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
HZ
MSB OUT
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 85. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
w(SCKH)
t
r(SCK)
t
w(SCKL)
t
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
DD
DD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
101/122
1
ST7LITE0, ST7SUPERLITE
13.11 8-BIT ADC CHARACTERISTICS
T = -40°C to 125°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MHz
V
f
ADC clock frequency
4
ADC
V
R
Conversion voltage range
External input resistor
V
V
AIN
AIN
SS
DD
1)
10
kΩ
C
Internal sample and hold capacitor
Stabilization time after ADC enable
V
=5V
3
pF
ADC
DD
2)
t
0
STAB
µs
t
Conversion time (t
+t )
SAMPLE HOLD
3
CONV
f
=8MHz, f
=4MHz
ADC
CPU
t
Sample capacitor loading time
Hold conversion time
4
8
SAMPLE
1/f
ADC
t
HOLD
3)
4)
Figure 86. R
max. vs f
with C =0pF
Figure 87. Recommended C /R
values
AIN
ADC
AIN
AIN AIN
45
40
35
30
25
20
15
10
5
1000
100
10
Cain 10 nF
Cain 22 nF
Cain 47 nF
4 MHz
2 MHz
1 MHz
1
0
0.1
0
10
30
70
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Figure 88. Typical Application with ADC
V
DD
V
T
0.6V
2kΩ(max)
R
AIN
AINx
8-Bit A/D
Conversion
V
AIN
C
V
T
0.6V
AIN
I
C
ADC
3pF
L
±1µA
ST72XXX
Notes:
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
3.C
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
PARASITIC
pacitance (3pF). A high C
value will downgrade conversion accuracy. To remedy this, f
should be reduced.
PARASITIC
ADC
4. This graph shows that depending on the input signal variation (f ), C
can be increased for stabilization and to allow
AIN
AIN
the use of a larger serial resistor (R
. It is valid for all f
frequencies ≤ 4MHz.
AIN)
ADC
102/122
1
ST7LITE0, ST7SUPERLITE
ADC CHARACTERISTICS (Cont’d)
13.11.0.1 General PCB Design Guidelines
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
ADC Accuracy
T = -40°C to 85°C, unless otherwise specified
A
Symbol
Parameter
Conditions
Typ
Max
Unit
2)
E
Total unadjusted error
±1
T
O
G
D
2)
E
E
E
Offset error
-0.5 / +1
±1
2)
Gain Error
f
=4MHz, f
=2MHz ,V =5.0V
LSB
CPU
ADC
DD
2)
1)
Differential linearity error
±1
2)
1)
E
E
Integral linearity error
±1
L
2)
Total unadjusted error
±2
T
2)
E
E
E
Offset error
-0.5 / 3.5
-2 / 0
O
G
D
2)
Gain Error
f
=8MHz, f
=4MHz ,V =5.0V
LSB
CPU
ADC
DD
2)
1)
Differential linearity error
±1
2)
1)
E
Integral linearity error
±1
L
Notes:
1) Data based on characterization results over the whole temperature range, monitored in production.
2) Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being
performed on any analog input.
Analog pins can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative
current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.
Any positive injection current within the limits specified for I
accuracy.
and ΣI
in Section 13.8 does not affect the ADC
INJ(PIN)
INJ(PIN)
103/122
ST7LITE0, ST7SUPERLITE
ADC CHARACTERISTICS (Cont’d)
Figure 89. ADC Accuracy Characteristics with Amplifier disabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
255
254
253
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
256
E =Total Unadjusted Error: maximum deviation
T
(2)
between the actual and the ideal transfer curves.
E
E =Offset Error: deviation between the first actual
T
O
(3)
transition and the first ideal one.
7
6
5
4
3
2
1
E =Gain Error: deviation between the last ideal
(1)
G
transition and the last actual one.
E =Differential Linearity Error: maximum deviation
D
E
O
between actual steps and the ideal one.
E
L
E =Integral Linearity Error: maximum deviation
L
between any actual transition and the end point
correlation line.
E
D
1 LSB
IDEAL
7
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
253 254 255 256
V
V
DDA
SSA
104/122
ST7LITE0, ST7SUPERLITE
ADC CHARACTERISTICS (Cont’d)
Figure 90. ADC Accuracy Characteristics with Amplifier enabled
Digital Result ADCDR
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
V
– V
DDA
SSA
= -------------------------------------
1LSB
IDEAL
103 × 8
E =Total Unadjusted Error: maximum deviation
T
(2)
between the actual and the ideal transfer curves.
E
E =Offset Error: deviation between the first actual
T
O
(3)
transition and the first ideal one.
n+7
n+6
n+5
n+4
n+3
n+2
n+1
E =Gain Error: deviation between the last ideal
(1)
G
transition and the last actual one.
E =Differential Linearity Error: maximum deviation
D
E
O
between actual steps and the ideal one.
E
L
E =Integral Linearity Error: maximum deviation
L
between any actual transition and the end point
correlation line.
E
D
n=Amplifier Offset
1 LSB
IDEAL
7
V
(LSB
)
in
IDEAL
0
1
2
3
4
5
6
100 101 102 103
250 mV
V
SS
Note: When the AMPSEL bit in the ADCDRL register is set, it is mandatory that f
be less than or equal
ADC
to 2 MHz. (if f
=8MHz. then SPEED=0, SLOW=1).
CPU
Symbol
Parameter
Conditions
=5V
Min
4.5
0
Typ
Max
5.5
Unit
V
V
V
V
V
Amplifier operating voltage
Amplifier input voltage
Amplifier offset voltage
DD(AMP)
V
250
mV
mV
mV
IN
DD
200
OFFSET
STEP
3)
Step size for monotonicity
Output Voltage Response
Amplified Analog input Gain
5
Linearity
Gain factor
Vmax
Linear
2)
1)
1)
7
8
9
Output Linearity Max Voltage
Output Linearity Min Voltage
2.05
2.2
0.22
2.4
V
V
V
V
= 250mV,
INmax
1)
=5V
Vmin
0
0.25
DD
Notes:
1) Data based on characterization results over the whole temperature range, not tested in production.
2) For precise conversion results it is recommended to calibrate the amplifier at the following two points:
– offset at V = 0V
INmin
– gain at full scale (for example V =250mV)
IN
3) Monotonicity guaranteed if V increases or decreases in steps of min. 5mV.
IN
105/122
ST7LITE0, ST7SUPERLITE
14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA
Figure 91. 16-Pin Plastic Dual In-Line Package, 300-mil Width
mm
Min Typ Max Min Typ Max
5.33 0.210
inches
Dim.
E
A
A1 0.38
0.015
A2
A
A1
A2 2.92 3.30 4.95 0.115 0.130 0.195
0.36 0.46 0.56 0.014 0.018 0.022
b
L
c
E1
b2 1.14 1.52 1.78 0.045 0.060 0.070
b3 0.76 0.99 1.14 0.030 0.039 0.045
b2
b
eB
e
D1
b3
c
0.20 0.25 0.36 0.008 0.010 0.014
18.67 19.18 19.69 0.735 0.755 0.775
D
D
D1 0.13
0.005
e
2.54
7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280
0.100
E
L
2.92 3.30 3.81 0.115 0.130 0.150
eB
10.92
0.430
Number of Pins
N
16
Figure 92. 16-Pin Plastic Small Outline Package, 150-mil Width
mm
inches
L
Dim.
A
Min Typ Max Min Typ Max
45×
1.35
1.75 0.053
0.25 0.004
0.51 0.013
0.25 0.007
10.00 0.386
4.00 0.150
0.069
0.010
0.020
0.010
0.394
0.157
A
A1
A1 0.10
B
C
D
E
e
0.33
0.19
9.80
3.80
e
a
B
C
A1
H
D
1.27
0.050
H
α
5.80
0°
6.20 0.228
0.244
8°
9
8
16
1
8°
0°
E
L
0.40
1.27 0.016
0.050
Number of Pins
N
16
0016020
106/122
ST7LITE0, ST7SUPERLITE
14.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
TBD
500
Unit
°C/W
mW
°C
R
Package thermal resistance (junction to ambient)
thJA
1)
P
Power dissipation
D
2)
T
Maximum junction temperature
150
Jmax
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the chip internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
2. The average chip-junction temperature can be obtained from the formula T = T + P x RthJA.
J
A
D
107/122
ST7LITE0, ST7SUPERLITE
14.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines.
Figure 93. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250
COOLING PHASE
(ROOM TEMPERATURE)
5 sec
200
150
100
50
SOLDERING
PHASE
80°C
Temp. [°C]
PREHEATING
PHASE
Time [sec]
0
20
60
40
80
100
140
120
160
Figure 94. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C
for 25 sec
200
150
100
50
150 sec above 183°C
90 sec at 125°C
Temp. [°C]
ramp down natural
2°C/sec max
ramp up
2°C/sec for 50sec
Time [sec]
0
100
200
300
400
Recommended glue for SMD plastic packages:
■ Heraeus: PD945, PD955
■ Loctite: 3615, 3298
108/122
ST7LITE0, ST7SUPERLITE
15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (FASTROM).
OPTION BYTE 0
Bit 7:4 = Reserved, must always be 1.
ST7PLITE0x and ST7PLITES2/S5 devices are
Factory Advanced Service Technique ROM (FAS-
TROM) versions: they are factory-programmed
XFlash devices.
Bit 3:2 = SEC[1:0] Sector 0 size definition
These option bits indicate the size of sector 0 ac-
cording to the following table.
Sector 0 Size
SEC1
SEC0
ST7FLITE0x and ST7FLITES2/S5 XFlash devices
are shipped to customers with a default program
memory content (FFh). The OSC option bit is pro-
grammed to 0 by default.
0.5k
1k
0
0
1
0
1
x
1)
The FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes while the FASTROM
devices are factory-configured.
1.5k
Note 1: Configuration available for ST7LITE0 de-
vices only.
Bit 1 = FMP_R Read-out protection
This option indicates if the FLASH program mem-
ory and Data EEPROM is protected against pira-
cy. The read-out protection blocks access to the
program and data areas in any mode except user
mode and IAP mode. Erasing the option bytes
when the FMP_R option is selected will cause the
whole memory to be erased first, , and the device
can be reprogrammed. Refer to Section 4.5 and
the ST7 Flash Programming Reference Manual for
more details.
15.1 OPTION BYTES
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes can be accessed only in pro-
gramming mode (for example using a standard
ST7 programming tool).
0: Read-out protection off
1: Read-out protection on
Bit 0 = FMP_W FLASH write protection
This option indicates if the FLASH program mem-
ory is write protected.
Warning: When this option is selected, the pro-
gram memory (and the option bit itself) can never
be erased or programmed again.
0: Write protection off
1: Write protection on
109/122
ST7LITE0, ST7SUPERLITE
OPTION BYTES (Cont’d)
OPTION BYTE 1
Bit 7 = PLLx4x8 PLL Factor selection.
Bit 5 = Reserved, must always be 1.
0: PLLx4
1: PLLx8
Bit 4 = OSC RC Oscillator selection
0: RC oscillator on
Bit 6 = PLLOFF PLL disable.
0: PLL enabled
1: RC oscillator off
1: PLL disabled (by-passed)
Table 20. List of valid option combinations
Operating conditions
Option Bits
V
range
Clock Source
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Typ f
OSC
PLLOFF
PLLx4x8
DD
CPU
0.7MHz @3V
0
0
-
1
0
-
x
0
-
Internal RC 1%
2.8MHz @3V
-
2.4V - 3.3V
3.3V - 5.5V
0-4MHz
1
1
-
1
0
-
x
0
-
External clock
Internal RC 1%
External clock
4MHz
-
1MHz @5V
0
-
1
-
x
-
-
8MHz @5V
0-8MHz
-
0
1
-
0
1
-
1
x
-
8 MHz
1
0
1
Note 1: see Clock Management Block diagram in Figure 13
Bit 1 = WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
Bit 3:2 = LVD[1:0] Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 21.
1: Software (watchdog to be enabled by software)
Bit 0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Table 21. LVD Threshold Configuration
Configuration
LVD1 LVD0
1
1
0
0
1
0
1
0
LVD Off
Highest Voltage Threshold ( 4.1V)
Medium Voltage Threshold ( 3.5V)
Lowest Voltage Threshold ( 2.8V)
OPTION BYTE 0
OPTION BYTE 1
7
0
7
0
FMP FMP PLL PLL
WDG WDG
SW HALT
Reserved
SEC1 SEC0
OSC LVD1 LVD0
R
W
x4x8 OFF
Default
Value
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
110/122
ST7LITE0, ST7SUPERLITE
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the FASTROM con-
tents and the list of the selected options (if any).
The FASTROM contents are to be sent on dis-
kette, or by electronic means, with the S19 hexa-
decimal file generated by the development tool. All
unused bytes must be set to FFh. The selected op-
tions are communicated to STMicroelectronics us-
ing the correctly completed OPTION LIST append-
ed.
Refer to application note AN1635 for information
on the counter listing returned by ST after code
has been transferred.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Table 22. Supported part numbers
Program
Memory
(Bytes)
Data
EEPROM
(Bytes)
RAM
(Bytes)
Temp.
Range
Part Number
ADC
Package
ST7FLITES2Y0B6
ST7FLITES2Y0M6
ST7FLITES5Y0B6
ST7FLITES5Y0M6
ST7PLITES2Y0B6
ST7PLITES2Y0M6
ST7PLITES5Y0B6
ST7PLITES5Y0M6
ST7FLITE02Y0B6
ST7FLITE02Y0M6
ST7FLITE05Y0B6
ST7FLITE05Y0M6
ST7FLITE09Y0B6
ST7FLITE09Y0M6
ST7PLITE02Y0B6
ST7PLITE02Y0M6
ST7PLITE05Y0B6
ST7PLITE05Y0M6
ST7PLITE09Y0B6
ST7PLITE09Y0M6
-
-
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
DIP16
SO16
-
-
1K FLASH
128
-40°C +85°C
-40°C +85°C
1)
-
yes
yes
-
1)
-
-
-
-
1K FASTROM
128
128
1)
1)
-
yes
yes
-
-
-
-
-
2)
2)
2)
2)
-
yes
yes
yes
yes
-
1.5K FLASH
-40°C +85°C
-
128
128
-
-
-
2)
2)
2)
2)
-
yes
yes
yes
yes
1.5K FASTROM
128
-40°C +85°C
-
128
128
Contact ST sales office for product availability
Note 1: available without Operational Amplifier
Note 2: available with Operational Amplifier
111/122
ST7LITE0, ST7SUPERLITE
ST7LITE0 AND ST7SUPERLITE FASTROM MICROCONTROLLER OPTION LIST
Customer
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No
Reference/FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
--------------------------------- ----------------------------------------- -----------------------------------------
|
|
|
|
FASTROM DEVICE:
1.5K
1K
--------------------------------- ----------------------------------------- -----------------------------------------
PDIP16:
SO16:
|
|
|
|
|
|
[ ] ST7PLITE02Y0B6
[ ] ST7PLITE05Y0B6
[ ] ST7PLITE09Y0B6
[ ] ST7PLITE02Y0M6
[ ] ST7PLITE05Y0M6
[ ] ST7PLITE09Y0M6
|
|
|
|
|
|
[ ] ST7PLITES2Y0B6
[ ] ST7PLITES5Y0B6
[ ] ST7PLITES2Y0M6
[ ] ST7PLITES5Y0M6
Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and
RCCR1 (see section 7.1 on page 23).
Conditioning (check only one option):
--------------------------------------------------------------------------
--------------------------------------------------------------------------
|
|
Packaged Product (do not specify for DIP package)
[ ] Tape & Reel
[ ] Tube
|
|
|
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _" (DIP16 only)
Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Maximum character count:
PDIP16 (9 char. max) : _ _ _ _ _ _ _ _ _
SO16 (6 char. max) : _ _ _ _ _ _
Sector 0 size:
[ ] 0.5K
[ ] 1K
[ ] 1.5K (ST7LITE0 devices only)
Readout Protection:
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled
FLASH write Protection:
Clock Source Selection:
[ ] Internal RC
[ ] External Clock
[ ] PLLx4 [ ] PLLx8
PLL
[ ] Disabled
[ ] Disabled
LVD Reset
[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Watchdog Selection:
[ ] Software Activation
[ ] Disabled
[ ] Hardware Activation
[ ] Enabled
Watchdog Reset on Halt:
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date:
Signature:
Important note: Not all configurations are available. See Table 20 on page 110 for authorized option byte
combinations.
112/122
ST7LITE0, ST7SUPERLITE
15.3 DEVELOPMENT TOOLS
STmicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compli-
ers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
or USB port: see Table 23 and Table 24 for more
details.
Table 23. STMicroelectronics Tools Features
In-Circuit Emulation
1)
Programming Capability
Software Included
ST7 In Circuit
Yes
ST7 CD ROM with:
Yes (all packages)
Debugging Kit
– ST7 Assembly toolchain
Yes, powerful emulation
features including trace/
logic analyzer
– STVD7 powerful Source Level
Debugger for Win 9x and NT
– C compiler demo versions
ST7 Emulator
No
– ST Realizer for Win 3.1 and Win
95.
– Windows Programming Tools
for Win 9x and NT
ST7 Programming Board
No
Yes (All packages)
Table 24. Dedicated STMicroelectronics Development Tools
ST7 In Circuit Debugging
Supported Products
ST7 Emulator
ST7 Programming Board
Kit
ST7FLITE0-INDART
(parallel port)
ST7FLITE02, ST7FLITE05,
ST7FLITE09, ST7FLITES2,
ST7FLITES5
ST7MDT10-EMU3
ST7MDT10-EPB
ST7FLIT0-IND/USB
(USB port)
Note:
1. In-Circuit Programming (ICP) interface for FLASH devices.
113/122
ST7LITE0, ST7SUPERLITE
15.4 ST7 APPLICATION NOTES
IDENTIFICATION
DESCRIPTION
EXAMPLE DRIVERS
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
114/122
ST7LITE0, ST7SUPERLITE
IDENTIFICATION
AN 982
DESCRIPTION
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1014
AN1015
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1040
AN1070
AN1324
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1477
AN1502
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
AN1530
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1478
AN1527
AN1575
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
115/122
ST7LITE0, ST7SUPERLITE
16 IMPORTANT NOTES
16.1 Execution of BTJX Instruction
Description
Workaround
Executing a BTJx instruction jumps to a random
address in the following conditions: the jump goes
to a lower address (jump backward) and the test is
performed on a data located at the address
00FFh.
Devices configured with Hardware Watchdog
must be programmed using a specific program-
ming mode that ignores the option byte settings. In
this mode, an external clock, normally provided by
the programming tool, has to be used. In ST tools,
this mode is called "ICP OPTIONS DISABLED".
16.2 In-Circuit Programming of devices
previously programmed
Watchdog option
with
Hardware
Sockets on ST programming tools (such as
ST7MDT10-EPB) are controlled using "ICP OP-
TIONS DISABLED" mode. Devices can therefore
be reprogrammed by plugging them in the ST Pro-
gramming Board socket, whatever the watchdog
configuration.
Description
In-Circuit Programming of devices configured with
Hardware Watchdog (WDGSW bit in option byte 1
programmed to 0) requires certain precautions
(see below).
When using third-party tools, please refer the
manufacturer’s documentation to check how to ac-
cess specific programming modes. If a tool does
not have a mode that ignores the option byte set-
tings, devices programmed with the Hardware
watchdog option cannot be reprogrammed using
this tool.
In-Circuit Programming uses ICC mode. In this
mode, the Hardware Watchdog is not automati-
cally deactivated as one might expect. As a conse-
quence, internal resets are generated every 2 ms
by the watchdog, thus preventing programming.
The device factory configuration is Software
Watchdog so this issue is not seen with devices
that are programmed for the first time. For the
same reason, devices programmed by the user
with the Software Watchdog option are not im-
pacted.
16.3 In-Circuit Debugging with Hardware
Watchdog
In Circuit Debugging is impacted in the same way
as In Circuit Programming by the activation of the
hardware watchdog in ICC mode. Please refer to
Section 16.2.
The only devices impacted are those that have
previously been programmed with the Hardware
Watchdog option.
116/122
ST7LITE0, ST7SUPERLITE
17 SUMMARY OF CHANGES
Revision
Main changes
Date
Added ST7LITE02x devices and ST7SUPERLITE devices
Changed Caution to pin n°10 in Table 1, “Device Pin Description,” on page 7
Changed note 5 in section 4.4 on page 13
Changed section 4.5.1 on page 14
Changed section 11.4.6 on page 70: added note in the description of ADON Bit (ADCCSR
register) and modified description of AMPSEL bit in the ADCAMP register
Changed section 13.3.1 on page 80: f
Changed note 2 in section 13.3.4.2 on page 83
Changed section 13.7.1 on page 90
instead of f
CLKIN
OSC
2.4
August-03
Updated section 13.7.2.2 on page 92 (“Electrical Sensitivities” table)
Changed section 15 on page 109
Changed section 15.2 on page 111
Changed Table 24, “Dedicated STMicroelectronics Development Tools,” on page 113
Changed option list on page 112
117/122
ERRATA SHEET
ST7LITE0, ST7SUPERLITE
LIMITATIONS AND CORRECTIONS
18 SILICON IDENTIFICATION
This section of the document refers to rev Y ST7FLITE0 and ST7FLITES2/S5 devices.
They are identifiable:
■
On the device package, by the last letter of the Trace code marked on the device package
On the box, by the last 3 digits of the Internal Sales Type printed on the box label.
■
Table 25. Device Identification
Trace Code marked on device
Internal Sales Type on box label
7FLITE09Y0M6$U5
7FLITE09Y0B6$U5
7FLITE05Y0M6$U5
7FLITE05Y0B6$U5
7FLITE02Y0M6$U5
7FLITE02Y0B6$U5
7FLITES5Y0M6$U5
7FLITES5Y0B6$U5
7FLITES2Y0M6$U5
7FLITES2Y0B6$U5
Flash Devices: “xxxxxxxxxY”
See also Figure 95
19 REFERENCE SPECIFICATION
Limitations in this document are with reference to the ST7LITE0, ST7SUPERLITE
Datasheet Revision 2.4 (August 2003).
20 SILICON LIMITATIONS
20.1 NEGATIVE INJECTION IMPACT ON ADC ACCURACY
Injecting a negative current on an analog input pins significantly reduces the accuracy of the
AD Converter. Whenever necessary, the negative injection should be prevented by the addi-
tion of a Schottky diode between the concerned I/Os and ground.
Injecting a negative current on digital input pins degrades ADC accuracy especially if per-
formed on a pin close to ADC channel in use.
Rev. 2.5
August 2003
118/122
ERRATA SHEET
20.2 ADC CONVERSION SPURIOUS RESULTS
Spurious conversions occur with a rate lower than 50 per million. Such conversions happen
when the measured voltage is just between 2 consecutive digital values.
Workaround
A software filter should be implemented to remove erratic conversion results whenever they
may cause unwanted consequences.
20.3 FUNCTIONAL ESD SENSITIVITY
The ST7LITE0 and ST7SUPERLITE, when configured with High or Medium LVD threshold,
are below the STMicroelectronics functional sensitivity standard. When positive stress is in-
jected on I/Os, the LVD reset is activated, but normal operation resumes after reset.
As a consequence, the application should be well protected against ESD. The firmware may
also be designed to allow warm reset, as described in EMC application note AN1015, allowing
the application to resume normal operation after a reset.
This does not affect ESD absolute maximum ratings: the ST7LITE0 and ST7SUPERLITE
meet STMicroelectronics standards concerning ESD levels that may cause damage to the sil-
icon. Devices configured without LVD and with the Low LVD threshold level are not impacted.
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ERRATA SHEET
21 DEVICE MARKING
Figure 95. Revision Marking on Box Label and Device Marking
TYPE xxxx
Internalxxx$xx
Trace Code
LAST 2 DIGITS AFTER $
IN INTERNAL SALES TYPE
ON BOX LABEL
INDICATE SILICON REV.
LAST LETTER OF TRACE CODE
ON DEVICE INDICATES
SILICON REV.
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ERRATA SHEET
22 ERRATA SHEET REVISION HISTORY
Revision
Main Changes
Date
2.5
This revision refers to the ST7LITE0, ST7SUPERLITE datasheet revision 2.4. August 2003
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ERRATA SHEET
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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122/122
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