ST7WIND21 [STMICROELECTRONICS]
8-BIT, MROM, 12MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, TQFP-48;
| 型号： | ST7WIND21 |
| 厂家： | 
ST |
| 描述： | 8-BIT, MROM, 12MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, TQFP-48 时钟 微控制器 外围集成电路 |
| 文件： | 总181页 (文件大小：3109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST7WIND21
8-BIT LOW-SPEED USB MCU WITH 3 EPs, ROM, TIMERS,
DUAL 27MHz RF RECEIVER, DUAL PS/2
PRELIMINARY DATA
■ Memories
– 24K ROM program memory with read/write
protection
– 2.5K RAM
■ Clock, Reset and Supply Management
– Dual Clock Source Management:
12 MHz monocrystal oscillator
6 MHz internal RC oscillator
TQFP48
7 x 7
– Enhanced Reset System
– 4 power saving modes: Slow, Wait, Halt and
Auto Wake-Up From Halt
■ Interrupt Management
– Nested Interrupt Controller
– 14 interrupt vectors plus TRAP and RESET
■ I/O ports
■ USB (Universal Serial Bus) Interface
– DMA for low-speed applications compliant
with USB 1.5 Mbs specification (v 2.0) and
USB HID specification (v 1.1):
– Integrated transceivers
– Suspend and Resume operations
– 3 Endpoints
– 15 multifunctional bidirectional I/O lines
– 7 with high sink capability
■ 3 Timers
– PS/2-compatible I/Os
■ Other Communication Interfaces
– Configurable Watchdog Timer
– 8-bit Time Base Unit (TBU)
– Dual PS/2 interface
– SPI synchronous serial interface
■ Instruction Set
– 16-bit Timer with: 2 input captures, 2 output
compares, external clock input, PWM and
pulse generator modes
■ Dual RF Receiver Interface
– 8-bit data manipulation
– 27 MHz radio frequency band
– Demodulator
– Delta Sigma A/D with digital filtering
– DSP protocol management
– Compatible with NRZ data
– 63 basic instructions with illegal opcode de-
tection
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development Tools
– Full hardware/software development package
– DM (Debug module)
Table 1. Device Summary
Features
ST7WIND21
Program memory - bytes
24K ROM
RAM (stack) - bytes
2560 (256)
RF Interface
27 MHz frequency band, Dual receiver, NRZ data compatible
Peripherals
USB (3 Endpoints), Watchdog, TBU, 16-bit Timer, SPI, 2 x PS/2
Operating Supply
CPU Frequency
Operating temperature
Package
4.0V to 5.5V
6MHz or 12MHz
0°C to +55°C
TQFP48/TQFP100 (EMUCHIP)
Rev. 1.0
1/181
January 2005
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 CLOCK, RESET AND SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2.1 Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 CLOCK-OUT CAPABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4.3 Power-on reset (POR) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.6 INTERRUPT VECTOR TABLE MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.7 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7.1 Software and Hardware Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7.2 Enable and Sensitivity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7.3 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
181
7.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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7.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.1 HALT MODE RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.7 PORTS WITH SPECIAL PULL-UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.1.4 Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.5 Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.6 Generating a Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.7 Hardware Watchdog Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.1.10Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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9.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.4 RF COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.4.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.5 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.5.4 Low Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.6 PS/2 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.6.3 Protocol Description and Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.6.5 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.6.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.6.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.7 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.7.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.7.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.7.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1.1Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.2Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.3Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.4Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.5Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.6Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.7Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.2.1Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
181
4/181
Table of Contents
11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1.1Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1.4Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.4.1RUN and WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.4.2HALT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.4.3Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.4.4On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.4.5RF Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.5.3Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.5.46-MHz RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.5.5Auto Wake-up RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.7.1Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.7.2Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.7.3Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 157
11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.10.2Time Base Unit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.10.316-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.10.4Auto Wake-up from Halt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.11 RF COMMUNICATION ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . 164
11.11.1Radio Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.12 OTHER COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . 167
11.12.1USB - Universal Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5/181
Table of Contents
11.12.2SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.13 POWER-ON-RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.14 VOLTAGE REGULATORS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13 DEVICE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 174
13.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
14 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 180
14.2 STAB BIT DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14.3 RECEIVER TEST SIGNAL OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
14.4 RECEIVER SLICER LEVEL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6/181
ST7WIND21
1 INTRODUCTION
The ST7WInD21 device, subsequently referred to
as “the Device” throughout this datasheet, is a
member of the ST7 microcontroller family. It is
based on a common industry-standard 8-bit core,
featuring an enhanced instruction set.
cost external components, including a crystal, ca-
pacitors and resistors.
Figure 56 on page 94 shows the RF Analog block
diagram as well as the recommended external
component circuitry. This power supply decou-
pling structure ensures optimum radio characteris-
tics.
It operates with either 12MHz external oscillator or
a 6MHz internal RC. The main clock can be
switched dynamically to use either source.
The Device includes an ST7 CPU, I/O lines and
various peripherals as listed below:
Under software control, the Device can be placed
in Slow, Wait, Auto Wake-up from Halt or Halt
mode, reducing power consumption when the ap-
plication is in idle or stand-by state.
– Embedded 3.3V voltage regulator for generating
the 3.3V power supply (V )
33
– Enhanced Reset System ensuring proper pow-
er-on or power-off of the Device
The enhanced instruction set and addressing
modes of the CPU offer both power and flexibility
to software developers, enabling the design of
highly efficient and compact application code. In
addition to standard 8-bit data management, the
ST7 CPU features 8x8 unsigned multiplication and
indirect addressing modes.
– Configurable Watchdog Timer
– Time Base Unit Timer
– 16-bit Timer
– Dual RF Receiver
– USB low-speed interface with 3 endpoints, pro-
grammable in/out configuration and embedded
transceivers (no external components are need-
ed).
The Device features a fully integrated RF commu-
nication block composed of a dual receiver (2RX).
Each receiver can operate simultaneously in the
27MHz band covering worldwide usage. The RF
communication block is designed to support NRZ
coded data and to operate with a minimum of low-
– Dual PS/2 interface
– Serial Peripheral Interface
7/181
1
ST7WIND21
INTRODUCTION (Cont’d)
Figure 1. Device Block Diagram
PROGRAM
PA[7:0]
Px[7:0]
PORT A
PORT x
MEMORY
24K Bytes
RAM
(2.5K Bytes)
USB DATA
BUFFER (48 B)
WATCHDOG
TBU
USBDP
USBDM
USB
16-Bit Timer
/2
SPI
CLOCK MGR
OSC1
OSC2
12MHz
OSCILLATOR
PS/2 0
PS/2 1
6MHz RC
OSCILLATOR
RESET MGR
CONTROL
RESET
8-BIT CORE
ALU
DUAL RF RECEIVER
&
Rx RF ANTENNA
DEMODULATOR
1.8V
REGULATOR
V
V
18
33
3.3V
V
REGULATOR
DD
8/181
1
ST7WIND21
2 PIN DESCRIPTION
Figure 2. 48-Pin TQFP Package Pinout
48 47 46 45 44 43 42 41 40 39 38 37
OSC2
OSC1
V
36
1
18_LOOP_PLL1
ei1
V
2
35
34
33
32
31
30
29
28
27
26
25
18_OUT_ADC1
V
BIAS1
3
SS_OSC
V
V
4
SS_SUB_DIG
SS_SUB_RF
V
NC
NC
33_DIG1
5
V
V
V
18_OUT_DIG
DD
6
NC
7
RXNIN
RXPIN
8
33_OUT
PG1 / USBDM / PS2_0DATA
PG0 / USBDP / PS2_0CLK
9
ei3
ei0
V
10
18_OUT_LNA
BIAS0
PA7 / USBPUP
PA6 (HS) / OCMP2 / PS2_1DATA
11
12
ei0
V
18_OUT_ADC0
24
13 14 15 16 17 18 19 20 21 22 23
(HS) 10mA high sink capability
eix associated external interrupt vector
9/181
1
ST7WIND21
Figure 3. 100-Pin TQFP Package Pinout (EMUCHIP package)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
NC
NC
18_OUT_PLL1
NC
NC
NC
NC
NC
OSC2
OSC1
ei1
V
V
18_LOOP_PLL1
NC
V
18_OUT_ADC1
NC
BIAS1
SS_SUB_RF
V
SS_OSC
V
9
EMU9
EMU10
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
V
V
SS_DIG2
SS_SUB_DIG
33_DIG1
SS_DIG1
RXNIN
RXPIN
NC
NC
V
V
18_OUT_LNA
18_OUT_DIG
NC
BIAS0
NC
NC
V
DD
V
33_OUT
V
PG1 / USBDM / PS2_0DATA
PG0 / USBDP / PS2_0CLK
NC
NC
PA7 / USBPUP
EMU11
18_OUT_ADC0
ei3
ei0
NC
NC
NC
V
V
18_LOOP_PLL0
ei0
ei0
18_OUT_PLL0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(HS) 10mA high sink capability
eix associated external interrupt vector
Note: For further information on the emulator, please refer to the ST7WInD probe user guide.
10/181
1
ST7WIND21
PIN DESCRIPTION (Cont’d)
For supply pin connection guidelines, refer to the
SUPPLY MANAGEMENT Section.
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int =
interrupt, ana = analog
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
– Output: OD = open drain, PP = push-pull
In/Output level: C = CMOS 0.3V /0.7V with in-
Refer to the I/O PORTS Section for more details
on the software configuration of the I/O ports.
T
33
33
put trigger
Output level: HS = 10mA high sink (on N-buffer
only)
The reset configuration of each pin is shown in
bold. This configuration is valid as long as the de-
vice is in reset state.
Table 2. Device Pin Description
Pin n°
Level
Port / Control
Input Output
Main
Function
(after
Pin Name
Alternate Functions
reset)
1
2
NC
NC
Not Connected
Not Connected
3
4
48 V
S
S
PLL1 1.8V Voltage Regulator Output
PLL1 Filter Supply
18_OUT_PLL1
1
V
18_LOOP_PLL1
5
NC
Not Connected
6
2
V
S
ADC1 1.8V Voltage Regulator Output
Not Connected
18_OUT_ADC1
7
NC
8
3
4
5
6
7
8
9
BIAS1
I
RX1 Bias Resistor
9
V
S
O
O
O
I
RF Substrate Ground
Not Connected
SS_SUB_RF
10
11
12
13
14
15
NC
NC
Not Connected
NC
Not Connected
RXNIN
RXPIN
NC
RX Antenna Negative Input
RX Antenna Positive Input
Not Connected
I
Low Noise Amplifier 1.8V Voltage Regulator
Output
16 10 V
S
18_OUT_LNA
17
18 11 BIAS0
19 NC
20 12 V
NC
Not Connected
I
RX0 Bias Resistor
Not Connected
S
ADC0 1.8V Voltage Regulator Output
Not Connected
18_OUT_ADC0
21
22
23
NC
NC
NC
Not Connected
Not Connected
24 13 V
S
PLL0 Filter Supply
18_LOOP_PLL0
11/181
1
ST7WIND21
Pin n°
Level
Port / Control
Input Output
Main
Function
(after
Pin Name
Alternate Functions
reset)
25 14 V
S
I
PLL0 1.8V Voltage Regulator Output
PLL0 Filter
18_OUT_PLL0
26 15 CPOUT0
27 16 V
28 17 V
S
S
Common (PLL, ADC and LNA) RF0 Ground
RF0 3.3V Power Supply
Not Connected
SS_RF0
33_RF0
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
Not Connected
V
S
Digital 3.3V Power Supply
Emulator interface 22
33_DIG0
EMU22
EMU21
EMU20
EMU19
EMU18
EMU17
EMU16
EMU15
EMU14
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
T
T
T
T
T
T
T
T
T
Emulator interface 21
Emulator interface 20
Emulator interface 19
Emulator interface 18
Emulator interface 17
Emulator interface 16
Emulator interface 15
Emulator interface 14
41 18 PA0/ICCDATA
I/O C HS
X
X
ei0
ei0
X
X
X
X
Port A0 ICC Data
T
3)
42 19 PA1/ICCCLK
43 20 V
I/O C HS
X
X
Port A1 ICC Clock
T
S
Digital Ground
SS_DIG0
44 21 PA2/ICAP1
45 22 PA3/ICAP2
46 23 PA4/EXTCLK
I/O C HS
X
X
X
X
X
X
ei0
ei0
ei0
X
X
X
X
X
X
Port A2 Timer Input Capture 1
Port A3 Timer Input Capture 2
Port A4 Timer External Clock Source
T
I/O C HS
T
I/O C HS
T
PA5/PS2_1CLK/
47 24
Timer Output Com-
Port A5 PS2 1 Clock
pare 1
4)
I/O C HS
X
X
X
X
ei0
ei0
X
X
X
X
T
OCMP1
PA6/
48 25 PS2_1DATA/
OCMP2
Timer Output Com-
4)
I/O C HS
Port A6 PS2 1 Data
pare 2
T
49
50
51
EMU13
EMU12
EMU11
I/O C
I/O C
I/O C
I/O C
Emulator interface 13
Emulator interface 12
Emulator interface 11
Port A7 USB Pull-up
Not Connected
T
T
T
T
5)
4)
52 26 PA7/USBPUP
X
X
X
X
ei0
ei3
X
X
X
53
54
NC
NC
Not Connected
PG0/USBDP/
PS2_0CLK
USB bidirectional
Port G0 PS2 0 Clock
55 27
12/181
I/O C
T
data (data +)
ST7WIND21
Pin n°
Level
Port / Control
Input Output
Main
Function
(after
Pin Name
Alternate Functions
reset)
PG1/USBDM/
PS2_0DATA
USB bidirectional
data (data -)
4)
56 28
I/O C
X
X
ei3
X
Port G1 PS2 0 Data
T
57 29 V
58 30 V
S
S
3.3V Voltage Regulator Output
+5V Power Supply
33_OUT
DD
59
NC
Not Connected
60 31 V
S
Digital 1.8V Voltage Regulator Output
Not Connected
18_OUT_DIG
61
62
NC
V
S
Digital Ground
SS_DIG1
63 32 V
64 33 V
S
Digital 3.3V Power Supply
Digital Substrate Ground
Digital Ground
33_DIG1
S
SS_SUB_DIG
SS_DIG2
65
66
67
V
S
EMU10
EMU9
I/O C
Emulator interface 10
Emulator interface 9
Oscillator Ground
T
T
I/O C
68 34 V
S
I
SS_OSC
69 35 OSC1
70 36 OSC2
External clock input or oscillator inverter input
Oscillator inverter output
Not Connected
O
71
72
73
74
75
NC
NC
NC
NC
NC
Not Connected
Not Connected
Not Connected
Not Connected
76 37 V
S
Oscillator 3.3V Power Supply
33_OSC
PP
77
V
I
I
C
C
X
V
Mode Selection Pin. Must be pulled-low.
PP
T
T
T
78 38 TEST
X
X
Test Mode Selection Pin. Must be tied low.
79 39 RESET
I/O C
I/O C
X
X
Top Priority non maskable Interrupt (active low)
SPI Master Out
PB0/MOSI/
RX0DATA
80 40
81 41
X
X
X
X
ei1
ei1
X
X
Port B0
RX0DATA output
T
T
/ Slave In Data
PB1/MISO/
RX1DATA
SPI Master In /
Slave Out Data
I/O C
X
Port B1
RX1DATA output
82 42 PB2/SCK
83 43 PB3/SS
84 44 PB4/MCO
I/O C
I/O C
I/O C
S
X
X
X
X
X
X
ei1
ei1
ei1
X
X
X
X
X
X
Port B2 SPI Serial Clock
T
T
T
Port B3 SPI Slave Select (active low)
Port B4 Master Clock Output
Digital Ground
85
86
87
V
SS_DIG3
EMU8
EMU7
I/O C
I/O C
Emulator interface 8
T
T
Emulator interface 7
13/181
1
ST7WIND21
Pin n°
Level
Port / Control
Input Output
Main
Function
(after
Pin Name
Alternate Functions
reset)
88
89
90
91
92
93
94
95
96
97
EMU6
I/O C
Emulator interface 6
Emulator interface 5
Emulator interface 4
Emulator interface 3
Emulator interface 2
Emulator interface 1
Emulator interface 0
Digital 3.3V Power Supply
Not Connected
T
T
T
T
T
T
T
EMU5
EMU4
EMU3
EMU2
EMU1
EMU0
I/O C
I/O C
I/O C
I/O C
I/O C
I/O C
S
V
33_DIG2
NC
NC
Not Connected
98 45 V
99 46 V
S
S
I
RF1 3.3V Power Supply
Common (PLL and ADC) RF1 Ground
PLL1 Filter
33_RF1
SS_RF1
100 47 CPOUT1
Notes:
1. I/O ports with less than 8 bits may have unbonded pads present internally. Pads that are not bonded to
external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at
reset state to avoid added current consumption.
2. In the interrupt input column, “eiX” defines the associated external interrupt vector.
3. During normal operation, this pin must be pulled-up, internally or externally, to avoid entering ICC mode
unexpectedly during a reset.
4. These I/Os feature a dedicated 4.7KΩ pull-up resistor in addition to the standard weak pull-up.
5. This I/O features a dedicated switch allowing control of 1.5KΩ external USB pull-up resistor.
6. Port A and Port G I/Os are 5V tolerant.
14/181
1
ST7WIND21
3 REGISTER & MEMORY MAP
As shown in Figure 4, the ST7 CPU embedded in
the Device is capable of addressing 64 KBytes of
memories and hardware registers.
space includes 256 bytes of stack and 48 bytes of
USB data buffer. The reset vector address is
FFFFh.
The available memory locations consist of 128
bytes of register locations, 24Kbytes of ROM and
2.5 Kbytes of RAM. Additional hardware registers
are accessible through register paging. The RAM
Important: Memory locations noted “Reserved”
must never be accessed. Accessing a reserved
area can have unpredictable effects on the De-
vice.
Figure 4. Memory Map
0000h
0080h
Short Addressing RAM
HW Registers
(see Table 3)
(zero page)
(128 Bytes)
00FFh
0100h
Stack or
007Fh
0080h
16-bit Addressing RAM
(256 Bytes)
RAM
2.5K Bytes
01FFh
0200h
USB Data Buffer
0A7Fh
0A80h
(48 Bytes)
022Fh
0230h
02E0h
Interrupt Vectors
Reserved
02FFh
(2128 Bytes)
9FFFh
A000h
16-bit Addressing RAM
0A7Fh
Program Memory
24K Bytes
FFDFh
FFE0h
Interrupt & Reset Vectors
FFFFh
15/181
1
ST7WIND21
Table 3. Hardware Register Memory Map
Register
Register
name
Reset
Status
Address
Block
Remarks
R/W
R/W
R/W
2)
Label
1)
0000h
0001h
0002h
PADR
PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
Port A
00h
02h
1)
2)
2)
2)
0003h
0004h
0005h
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h
R/W
R/W
R/W
Port B
00h
00h
0006h
to
Reserved Area (12 Bytes)
0011h
0012h
0013h
WATCH-
DOG
WDGCR
WDGCSR
Watchdog Control Register
Watchdog Control/Status Register
7Fh
00Fh
R/W
R/W
0014h
to
Reserved Area (3 Bytes)
0016h
0017h
0018h
0019h
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
SPI
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
T16CR2
T16CR1
T16CSR
T16IC1HR
T16IC1LR
T16OC1HR
T16OC1LR
T16CHR
Timer Control Register 2
Timer Control Register 1
Timer Control/Status Register
Timer Input Capture 1 High Register
Timer Input Capture 1 Low Register
Timer Output Compare 1 High Register
Timer Output Compare 1 Low Register
Timer Counter High Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
16-BIT
TIMER
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
T16CLR
Timer Counter Low Register
T16ACHR
T16ACLR
T16IC2HR
T16IC2LR
T16OC2HR
T16OC2LR
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture 2 High Register
Timer Input Capture 2 Low Register
Timer Output Compare 2 High Register
Timer Output Compare 2 Low Register
R/W
0029h
002Ah
TBUCVR
TBUCSR
TBU Counter Value Register
TBU Control/Status Register
00h
00h
R/W
R/W
TBU
002Bh
Reserved Area (1 Byte)
002Ch
002Dh
002Eh
CMCR0
CMCR1
CMR
Clock Management Control Register 0
Clock Management Control Register 1
Clock Mode Register
00h
00h
14h
R/W
R/W
R/W
Clocks
002Fh
Reserved Area (1 Byte)
0030h
0031h
0032h
0033h
0034h
0035h
0036h
ISPR0
ISPR1
ISPR2
ISPR3
EICR
PAEIENR
PBEIENR
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Port A External Interrupt Enable Register
Port B External Interrupt Enable Register
FFh
FFh
FFh
FFh
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ITC
0037h
Reserved Area (1 Byte)
16/181
1
ST7WIND21
Register
Label
Register
name
Reset
Status
Address
Block
Remarks
2)
0038h
0039h
PAEISR
PBEISR
Port A External Interrupt Status Register
Port B External Interrupt Status Register
00h
00h
R/W
R/W
ITC
003Ah
Reserved Area (1 Byte)
003Bh
003Ch
AWUCSR
AWUPR
Auto Wake Up From Halt Control/Status Reg.
Auto Wake Up From Halt Prescaler
00h
FFh
R/W
R/W
AWU
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
USBISTR
USBIMR
USBCTLR
USBDADDR
USBSR0
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Status Register
USB Error Status Register
00h
00h
16h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USBSR1
USBEP0R
USB Endpoint 0 Register
USBCNT0RXR
USBCNT0TXR
USBEP1RXR
USBCNT1RXR
USBEP1TXR
USBCNT1TXR
USBEP2RXR
USBCNT2RXR
USBEP2TXR
USBCNT2TXR
USB EP0 Reception Counter Register
USB EP0 Transmission Counter Register
USB EP1 Reception Register
USB EP1 Reception Counter Register
USB EP1 Transmission Register
USB EP1 Transmission Counter Register
USB EP2 Reception Register
USB EP2 Reception Counter Register
USB EP2 Transmission Register
USB EP2 Transmission Counter Register
USB
004Eh
004Fh
0050h
PS2C0R
PS2CS0R
PS2D0R
PS/2 Driver Control 0 Register
PS/2 Control Status 0 Register
PS/2 Data 0 Register
00h
00h
00h
R/W
R/W
R/W
PS/2 0
PS/2 1
0051h
0052h
0053h
PS2C1R
PS2CS1R
PS2D1R
PS/2 Control 1 Register
PS/2 Control Status 1 Register
PS/2 Data 1 Register
00h
00h
00h
R/W
R/W
R/W
0054h
0055h
0056h
0057h
PAGPUCR
PGDR
PGDDR
PGOR
Port A and G Pull-Up Control Register
Port G Data Register
Port G Data Direction Register
Port G Option Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Port G
ITC
0058h
0059h
005Ah
PGEICR
PGEIENR
PGEISR
Port G External Interrupt Control Register
Port G External Interrupt Enable Register
Port G External Interrupt StatusRegister
00h
00h
00h
R/W
R/W
R/W
005Bh
to
Reserved Area (5 Bytes)
005Fh
0060h
RF Pages RFPAGER
RF Page Selection Register
00h
R/W
0061h
0062h
0063h
0064h
0065h
0066h
0067h
RFCSR
RF Control/Status Register
RX0 Control/Status Register
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
RX0CSR
RX0RSSHR
RX0RSSLR
RX1CSR
RX1RSSHR
RX1RSSLR
RX0 Receive Strength High Register
RX0 Receive Strength Low Register
RX1 Control/Status Register
RX1 Receive Strength High Register
RX1 Receive Strength Low Register
Read Only
Read Only
R/W
Read Only
Read Only
RF Page 0
0068h
to
Reserved Area (3 Bytes)
006Ah
17/181
1
ST7WIND21
Register
Label
Register
name
Reset
Status
Address
Block
Remarks
2)
0061h
0062h
0063h
RFREGCR0
RFREGCR1
RFSYNR
RF Regulator Control Register 0
RF Regulator Control Register 1
RF Synthesizer Register
00h
00h
00h
R/W
R/W
R/W
0064h
to
0066h
Reserved Area (3 Bytes)
RF Page 1
Common
0067h
RFTSWR
RF Track Slicer Weighting Register
Reserved Area (3 Bytes)
00h
R/W
0068h
to
006Ah
0061h
0062h
0063h
0064h
RX0CFHR
RX0CFLR
RX0OFFHR
RX0OFFLR
RX0 Carrier Frequency High Register
RX0 Carrier Frequency Low Register
RX0 Offset High Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
RX0 Offset Low Register
0065h
0066h
RF Page 2
RX0
Reserved Area (2 Bytes)
0067h
0068h
0069h
RX0DRR
RX0SLHR
RX0SLLR
RX0 Data Rate Register
RX0 Slicer level High Register
RX0 Slicer level Low Register
00h
00h
00h
R/W
R/W
R/W
006Ah
Reserved Area (1 Byte)
0061h
0062h
0063h
0064h
RX1CFHR
RX1CFLR
RX1OFFHR
RX1OFFLR
RX1 Carrier Frequency High Register
RX1 Carrier Frequency Low Register
RX1 Offset High Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
RX1 Offset Low Register
0065h
0066h
RF Page 3
RX1
Reserved Area (2 Bytes)
0067h
0068h
0069h
RX1DRR
RX1SLHR
RX1SLLR
RX1 Data Rate Register
RX1 Slicer level High Register
RX1 Slicer level Low Register
00h
00h
00h
R/W
R/W
R/W
006Ah
Reserved Area (1 Byte)
006Bh
to
Reserved Area (13 Bytes)
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
DMCR1
DMCSR
Debug Module Control Register 1
00h
10h
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Debug Module Control Status Register
Debug Module Breakpoint 1 High Register
Debug Module Breakpoint 1 Low Register
Debug Module Breakpoint 2 High Register
Debug Module Breakpoint 2 Low Register
Debug Module Control Register 2
DMBK1HR
DMBK1LR
DMBK2HR
DMBK2LR
DMCR2
Debug
Module
3)
007Fh
Reserved Area (1 Byte)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. For a description of the Debug Module registers, see ICC reference manual.
18/181
1
ST7WIND21
4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
4.3 CPU REGISTERS
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
The 6 CPU registers shown in Figure 5 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
4.2 MAIN FEATURES
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
Index Registers (X and Y)
addressing mode)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to the Y register.)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
The Y register is not affected by the interrupt auto-
matic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 5. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
0
X INDEX REGISTER
Y INDEX REGISTER
RESET VALUE = XXh
7
RESET VALUE = XXh
PCL
PCH
7
8
15
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
0
1
1
I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE =
8
1
1
X 1 X X X
0
15
7
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
19/181
1
ST7WIND21
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Reset Value: 111x1xxx
7
0
This bit is accessed by the JREQ and JRNE test
instructions.
1
1
I1
H
I0
N
Z
C
The 8-bit Condition Code register contains the in-
terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
These bits can be individually tested and/or con-
trolled by specific instructions.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
0: No half carry has occurred.
1: A half carry has occurred.
Interrupt Software Priority
Level 0 (main)
I1
1
0
0
1
I0
0
1
0
1
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.
Level 1
Level 2
Bit 2 = N Negative.
Level 3 (= interrupt disable)
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
th
sult 7 bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
See the interrupt management chapter for more
details.
This bit is accessed by the JRMI and JRPL instruc-
tions.
Bit 1 = Z Zero.
20/181
1
ST7WIND21
CENTRAL PROCESSING UNIT (Cont’d)
STACK POINTER (SP)
Read/Write
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Reset Value: 01FFh
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.
15
8
1
0
0
7
0
0
0
0
0
0
The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 6.
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 6).
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
Since the stack is 256 bytes deep, the 8 most sig-
nificant bits are forced by hardware. Following a
CPU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), the Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which is the stack
higher address.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.
Figure 6. Stack Manipulation Example
CALL
Subroutine
RET
or RSP
PUSH Y
POP Y
IRET
Interrupt
Event
@ 0100h
SP
SP
SP
Y
CC
A
CC
A
CC
A
X
X
X
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
PCH
PCL
SP
SP
PCH
PCL
PCH
PCL
SP
@ 01FFh
Stack Higher Address = 01FFh
0100h
Stack Lower Address =
21/181
1
ST7WIND21
5 CLOCK, RESET AND SUPPLY MANAGEMENT
5.1 CLOCK SYSTEM
Internal RC Oscillators
The Device contains an internal RC oscillator for
low power operation at a frequency of 6 MHz. A
characteristic of RC oscillators is that their fre-
quency varies from one Device to another and with
temperature and voltage. For this reason, a fea-
ture allows the RC to be calibrated using the main
oscillator. Calibration can be performed at any
time by setting the CALRC bit in the CMR register.
This also calibrates the AWU oscillator used in
Auto-wakeup from Halt mode (see Section 7.5).
The main clock of the Device can be generated by
three different source types:
■ an external source
■ a 12MHz crystal oscillator (main oscillator)
■ a 6MHz internal RC oscillator
The associated hardware configurations are
shown in Table 4. Refer to the electrical character-
istics section for more details. On reset, the select-
ed Device clock source is the crystal oscillator.
Table 4. Device Clock Sources
Hardware Configuration
External Clock Source
An external clock source can be used to drive the
Device. The clock signal (square, sinus or triangle)
with ~50% duty cycle has to be input on the OSC1
pin while OSC2 pin is unconnected.
Device
OSC1
OSC2
NC
Crystal Oscillator
The internal oscillator is designed to operate with a
12MHz AT-cut parallel resonant quartz.
The crystal and associated components should be
installed as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
EXTERNAL
SOURCE
Device
OSC1
This oscillator is not stopped during the reset
phase to avoid losing time in the oscillator start-up
phase.
OSC2
C
C
L2
L1
LOAD
CAPACITORS
Figure 7.
Clock Control Block Diagram
MCO
MCO
fCPU
OSC/RC bit
fOSCMAIN
SMS[1:0] bits
DIV 1/2/4/8
Clock
to CPU
OSCEN bit
12MHz Crystal
fOSC
1
(or external Clock)
fOSCRC
CMCR0/CMCR1
CONTROL REG.
0
Clock to
Peripherals and
RF Digital Block
RCEN bit
6MHz internal RC
Clock to USB
Peripheral
DIV 2
22/181
1
ST7WIND21
5.2 CLOCK MANAGEMENT
5.3.1 Register Description
To save power, the application can switch back
and forth dynamically between the 12 MHz crystal
oscillator or the 6 MHz RC oscillator while still
staying in Run mode. This feature provides two
types of run mode:
CLOCK MANAGEMENT CONTROL 0 REGIS-
TER (CMCR0)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
■ Main Run mode ( with 12 MHz clock source) for
full operation with USB and RF communication
RF-
DSP
RX1 RX0
0
TBU SPI
T16 USB
■ Secondary Run mode (with 6 MHz clock source)
for fast wakeup from Halt mode, but without
USB or RF communication.
Bit 7 = RX1 RX1 clock enable
This bit enables the clock of the RX1. It is set and
cleared by software.
0: RX1 clock disabled
1: RX1 clock enabled
Control bits are also provided to enable or disable
the clock to individual on-chip peripherals.
In addition the application software can put the De-
vice in SLOW, SLOW/WAIT, Wait, HALT or Auto
Wakeup from Halt mode as described in Section 7
"POWER SAVING MODES" on page 43.
Bit 6 = RX0 RX0 clock enable
This bit enables the clock of the RX0. It is set and
cleared by software.
0: RX0 clock disabled
1: RX0 clock enabled
5.2.1 Software Examples
Switching from Secondary to Main Run Mode
; SWITCH to 12 MHz
LD
it
A,#$1C ; enable OSC 12 and select
LD
LD
LD
LD
CMR, A
Bit 5 = RF-DSP RF DSP clock enable
This bit enables the clocks driving the RF and
DSP. It is set and cleared by software.
0: RF DSP clocks disabled
A,#$14 ; disable RC 6MHz
CMR, A
A, CMR
1: RF DSP clocks enabled
Switching from Main to Secondary Run Mode
; SWITCH to 6 MHz
LD
it
A,#$0C
; enable RC 6 and select
Bit 4 = Reserved, must be kept cleared.
LD
LD
LD
LD
CMR, A
A,#$08
CMR, A
A, CMR
; disable OSC 12MHz
Bit 3 = TBU TBU clock enable
This bit enables the clock of the TBU. It is set and
cleared by software.
0: TBU clock disabled
1: TBU clock enabled
5.3 CLOCK-OUT CAPABILITY
The clock-out capability is an alternate function of
Bit 2 = SPI SPI clock enable
This bit enables the clock of the SPI. It is set and
cleared by software.
an I/O port pin that outputs the f
clock to drive
CPU
external devices. It is controlled by the MCO bit in
the CMCR1 register.
0: SPI clock disabled
1: SPI clock enabled
23/181
1
ST7WIND21
CLOCK MANAGEMENT (Cont’d)
Bit 1 = 16TIM 16TIM clock enable
This bit enables the clock of the 16TIM. It is set
and cleared by software.
0: DM clock disabled
1: DM clock enabled
0: 16TIM clock disabled
Bits 3:2 = Reserved. Must be kept cleared.
Bits 1:0 = Reserved. Must be kept cleared.
1: 16TIM clock enabled
Bit 0 = USB USB clock enable
This bit enables the clock of the USB. It is set and
cleared by software.
0: USB clock disabled
1: USB clock enabled
CLOCK MODE REGISTER
(CMR)
Read/Write
Reset Value: 0001 0100 (14h)
CLOCK MANAGEMENT CONTROL 1 REGIS-
TER (CMCR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
EN-
CAL
OSC/ RC- OSC-
RC
CALF
STAB
SMS1 SMS0
EN
EN
7
0
0
Bit 7 = CALF Calibration flag
This bit indicates the end of the 6 MHz and auto
wake-up RC calibration. It is set by hardware and
cleared when setting the ENCAL bit.
0: Calibration on-going
MCO PS2-1 PS2-0 DM
0
0
0
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function. It is
set and cleared by software.
1: Calibration finished
0: MCO alternate function disabled (I/O pin free for
general-purpose I/O)
Bit 6 = ENCAL Enable Calibration
This bit enables the calibration of the 6 MHz and
auto wake-up RC oscillator. It is set by software
and cleared by hardware. The RCEN bit does not
need to be set to perform a calibration.
0: Stop the calibration
1: MCO alternate function enabled (f
port)
on I/O
CPU
Bit 6 = PS2-1 PS2-1 clock enable
This bit enables the clock of the PS2-1. It is set
and cleared by software.
0: PS2-1 clock disabled
1: PS2-1 clock enabled
1: Start the calibration
Bit 5 = STAB Stabilization flag
This bit indicates the end of the oscillator stabiliza-
tion. It is cleared when either RCEN or OSCEN bit
is set and it is set after a fixed delay.
Bit 5 = PS2-0 PS2-0 clock enable
This bit enables the clock of the PS2-0. It is set
and cleared by software.
0: PS2-0 clock disabled
1: PS2-0 clock enabled
0: Oscillator stabilization on-going
1: Oscillator stabilization complete
When the 6MHz RC oscillator is enabled, the
STAB delay is of 11.2µs wheras it is of 1.36ms
when the 12MHz oscillator is enabled. This bit
does not guarantee that the oscillator is stable
when STAB bit is set. It can depend on oscillator
characteristics.
Bit 4 = DM Debug Module Clock enable
This bit enables the clock of the DM. It is set by
software. Once this bit is set, it cannot be cleared
except by a reset.
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1
ST7WIND21
CLOCK MANAGEMENT (Cont’d)
Bit 4 = OSC/RC Oscillator / RC selection
This bit selects the oscillator type: main oscillator
or RC. It is set and cleared by software and set by
hardware when entering Halt mode. It can be used
to switch from Main Run Mode to Secondary Run
Mode if the corresponding oscillator is enabled
(OSCEN or RCEN bits)
select the slow mode division factor (as explained
below:
SMS1
SMS0
division factor
0
0
1
1
0
1
0
1
1
2
4
8
0: 6 MHz RC selected (if RCEN=1)
1: 12 MHz oscillator selected (if OSCEN=1)
Note: Software modification of the OSC/RC,
RCEN and OSCEN bits is subject to the following
conditions imposed by hardware logic:
Bit 3 = RCEN 6MHz RC enable
This bit enables the RC 6MHz oscillator. It can be
set by software anytime and cleared by software
while OSC/RC=1. It is set by hardware after a
wake up from Halt mode by external interrupt.
0: 6 MHz RC oscillator disabled
1. It is not possible to modify OSCEN and RCEN
at the same time (previous values are kept
unchanged).
1: 6 MHz RC oscillator enabled
2. It is not possible to select a clock if the corre-
sponding clock is disabled (previous value is
kept unchanged).
Bit 2 = OSCEN 12 MHz oscillator enable
This bit enables the 12 MHz oscillator (or external
clock). It can be set by software anytime and
cleared by software while OSC/RC=0. It is cleared
by hardware when entering Halt mode and set by
hardware after a reset.
3. It is not possible to disable RCEN if 6 MHz RC
oscillator is selected.
4. It is not possible to disable OSCEN if 12MHz
oscillator is selected.
5. Whatever the clock selected by the RC/OSC
bit, when entering HALT mode, RC oscillator is
selected, RC oscillator is disabled and 12MHz
oscillator is disabled
0: 12 MHz Oscillator disabled
1: 12 MHz Oscillator enabled
Bits 1:0 = SMS[1:0] Slow mode select
These two bits are set and cleared by software to
6. The 6 MHz RC oscillator is automatically
selected when waking up from HALT mode.
Caution: When OSC/RC is switched, several f
CPU
pulses are lost because of switching from one
clock source to another. This must be taken into
account when using MCO or timer functions.
Table 5. Clock, Reset and Supply Control/Status Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CMCR0
RX1
0
RX0
0
RF-DSP
0
0
0
TBU
0
SPI
0
T16
0
USB
0
002Ch
002Dh
002Eh
Reset Value
CMCR1
MCO
0
PS2-1
0
PS2-0
0
DM
0
0
0
0
0
0
0
0
0
Reset Value
CMR
CALF
0
ENCAL
0
STAB
0
OSC/RC
1
RCEN
0
OSCEN
1
SMS1
0
SMS0
0
Reset Value
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ST7WIND21
5.4 RESET SEQUENCE MANAGER (RSM)
5.4.1 Introduction
The reset sequence manager includes four RE-
SET sources as shown in Figure 9:
The RESET vector fetch phase duration is 2 clock
cycles.
■ External RESET source pulse
Figure 8. RESET Sequence Phases
■ Internal LVD RESET (for supervising the 5V
supply)
■ Internal POR RESET (for supervising the
RESET
power-on of the 1.8V digital parts)
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
■ Internal WATCHDOG RESET
Active Phase
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
5.4.2 Asynchronous External RESET pin
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the Device memory
map.
The RESET pin is both an input and an open-drain
output with integrated R
weak pull-up resistor.
ON
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the Device. See
Electrical Characteristic section for more details.
The basic RESET sequence consists of 3 phases
as shown in Figure 8:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
A RESET signal originating from an external
■ RESET vector fetch
source must have a duration of at least t
in
h(RSTL)in
order to be recognized (see Figure 10). This de-
tection is asynchronous and therefore the Device
can enter reset state even in HALT mode.
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
Figure 9. Reset Block Diagram
V
33
R
ON
INTERNAL
RESET
Filter
RESET
POR RESET
LVD RESET
PULSE
GENERATOR
WATCHDOG RESET
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ST7WIND21
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
The Device RESET pin acts as an output that is
pulled low when V <V
(rising edge) or
DD
IT+
V
<V (falling edge) as shown in Figure 10.
DD
IT-
The LVD filters spikes on V larger than t
to
DD
g(VDD)
avoid parasitic resets.
5.4.3 Power-on reset (POR) RESET
Note: it is recommended to make sure that the
V supply voltage rises monotonously when the
DD
device is exiting from RESET, to ensure the appli-
cation functions properly.
The POR ensures a safe power-on sequence for
the 1.8V volt digital parts of the Device.
5.4.4 Internal Low Voltage Detector (LVD)
RESET
5.4.5 Internal Watchdog RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 10.
Starting from the Watchdog counter underflow, the
Device RESET pin acts as an output that is pulled
■ Voltage Drop RESET
low during at least t
.
w(RSTL)out
Figure 10. RESET Sequences
V
DD
V
V
IT+(LVD)
IT-(LVD)
LVD
RESET
EXTERNAL
RESET
WATCHDOG
RESET
RUN
RUN
RUN
RUN
ACTIVE
PHASE
ACTIVE
PHASE
ACTIVE PHASE
t
w(RSTL)out
t
h(RSTL)in
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
WATCHDOG UNDERFLOW
INTERNAL RESET (256 TCPU
)
VECTOR FETCH
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Section 10.2.1 on page 142 for further de-
tails.
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ST7WIND21
5.5 SUPPLY MANAGEMENT
The Device operates with a single external 5V
– REG18_DIG
power source (V ). This 5V supply is converted
DD
To reduce the Device power consumption, each of
the RF regulators can be powered off individually
through the RFREGCRn register.
to 3.3V by one internal voltage regulator (REG33).
This 3.3V supply is then converted to 1.8V by sev-
eral voltage regulators:
The regulators REG33 and REG18_DIG cannot
be powered off.
– REG18_PLL0
– REG18_ADC0
– REG18_LNA
– REG18_PLL1
– REG18_ADC1
The V connections (not shown in Figure 11) can
SS
be connected to a common ground plane.
V
and V
are the shielding
SS_SUB_RF
SS_SUB_DIG
ground connections for the RF analog and digital
parts respectively.
Figure 11. RF Voltage Regulator Interconnections
5V
V
DD
REG33
V
V
V
V
V
33_DIG0
33_DIG1
100nF
33_DIG2
100nF
33_OSC
33_OUT
100nF
100nF
100nF
4.7µF
3.3V
V
V
33_RF0
33_RF1
100nF
100nF
REG18_PLL1
REG18_PLL0
V18REF0
REG18_ADC1
V
REG18_ADC0
REG18_LNA
V
REG18_DIG
V18REF1
V
V
V
V
18
_OUT_ADC1
18
18
18
_OUT_PLL1
_OUT_PLL0
_OUT_ADC0
18
18
_OUT_LNA
_OUT_DIG
1.8V
100nF
100nF
100nF
100nF
100nF
100nF
Note: Refer to Figure 56 on page 94 for more information on RF power supply decoupling and
external components.
28/181
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ST7WIND21
6 INTERRUPTS
6.1 INTRODUCTION
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The CPU enhanced interrupt management pro-
vides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI
This interrupt management is based on:
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) CPU interrupt controller.
Table 6. Interrupt Software Priority Levels
Interrupt software priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
6.2 MASKING AND PROCESSING FLOW
0
1
Level 2
0
0
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process-
ing flow is shown in Figure 12.
Level 3 (= interrupt disable)
High
1
1
Figure 12. Interrupt Processing Flowchart
PENDING
INTERRUPT
Y
Y
RESET
TLI
N
Interrupt has the same or a
lower software priority
than current one
N
I1:0
FETCH NEXT
INSTRUCTION
THE INTERRUPT
STAYS PENDING
Y
“IRET”
N
RESTORE PC, X, A, CC
FROM STACK
EXECUTE
INSTRUCTION
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
29/181
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ST7WIND21
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
■ TLI (Top Level Hardware Interrupt)
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
This hardware interrupt is generated when the
Watchdog Time-out Flag is set.
Caution: A TRAP instruction must not be used in a
TLI service routine.
– the highest software priority interrupt is serviced,
■ TRAP (Non Maskable Software Interrupt)
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in Figure 12 as a TLI.
Figure 13 describes this decision process.
Caution: TRAP cannot be interrupted by a TLI.
■ RESET
Figure 13. Priority Decision Process
The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
PENDING
INTERRUPTS
See the RESET chapter for more details.
Different
Same
SOFTWARE
PRIORITY
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
HIGHEST SOFTWARE
PRIORITY SERVICED
HIGHEST HARDWARE
PRIORITY SERVICED
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci-
sion process.
■ Peripheral Interrupts
Different Interrupt Vector Sources
Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 12). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
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ST7WIND21
INTERRUPTS (Cont’d)
6.3 INTERRUPTS AND LOW POWER MODES
6.4 CONCURRENT & NESTED MANAGEMENT
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 13.
The following Figure 14 and Figure 15 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 15. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 14. Concurrent Interrupt Management
SOFTWARE
PRIORITY
I1
I0
LEVEL
TLI
3
1 1
1 1
1 1
1 1
1 1
1 1
IT0
3
IT1
IT1
3
IT2
3
IT3
3
RIM
IT4
3
MAIN
MAIN
3/0
11 / 10
10
Figure 15. Nested Interrupt Management
SOFTWARE
PRIORITY
LEVEL
I1
I0
TLI
3
1 1
1 1
0 0
0 1
1 1
1 1
IT0
3
IT1
IT1
IT2
2
IT2
1
IT3
3
RIM
IT4
IT4
3
MAIN
MAIN
3/0
11 / 10
10
31/181
1
ST7WIND21
INTERRUPTS (Cont’d)
6.5 INTERRUPT REGISTER DESCRIPTION
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
CPU CC REGISTER INTERRUPT BITS
Read/Write
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
Reset Value: 111x 1010 (xAh)
7
0
7
0
ISPR0
ISPR1
I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
1
1
I1
H
I0
N
Z
C
Bit 5, 3 = I1, I0 Software Interrupt Priority
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
These two bits indicate the current interrupt soft-
ware priority.
ISPR3
1
1
1
1
I1_13 I0_13 I1_12 I0_12
Interrupt Software Priority Level
I1
1
I0
0
Level 0 (main)
Level 1
Low
These four registers contain the interrupt software
priority of each interrupt vector.
0
1
Level 2
0
0
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in these registers where
its own software priority is stored. This corre-
spondance is shown in the following table.
Level 3 (= interrupt disable*)
High
1
1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri-
ority registers (ISPRx).
Vector address
ISPRx bits
FFFBh-FFFAh
FFF9h-FFF8h
...
I1_0 and I0_0 bits*
I1_1 and I0_1 bits
...
They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
FFE1h-FFE0h
I1_13 and I0_13 bits
*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.
– Each I1_x and I0_x bit value in the ISPRx regis-
ters has the same meaning as the I1 and I0 bits
in the CC register.
– Level 0 can not be written (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: previous=CFh, write=64h, result=44h)
The RESET, TRAP and TLI vectors have no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the TLI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter-
rupt x).
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ST7WIND21
INTERRUPTS (Cont’d)
Table 7. Dedicated Interrupt Instruction Set
Instruction
HALT
IRET
New Description
Entering Halt mode
Function/Example
I1
1
H
I0
0
N
Z
C
Interrupt routine return
Jump if I1:0=11
Pop CC, A, X, PC
I1:0=11 ?
I1
H
I0
N
Z
C
JRM
JRNM
POP CC
RIM
Jump if I1:0<>11
I1:0<>11 ?
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Mem => CC
I1
1
H
I0
0
1
1
0
N
Z
C
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
SIM
1
TRAP
WFI
1
Wait for interrupt
1
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions
change the current software priority up to the next IRET instruction or one of the previously mentioned
instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions
should never be used in an interrupt routine.
DM CONTROL REGISTER (DMCR1)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 5:0 = Reserved, must be kept cleared.
7
0
0
DM CONTROL REGISTER 2 (DMCR2)
Read/Write
0
MTR
0
0
0
0
0
Reset Value: 0000 0000 (00h)
7
0
Bit 7 = Reserved, must be kept cleared.
0
0
0
0
0
0
0
SVR
Bit 6 = MTR Monitor Control.
Bit 7:1= Reserved, must be kept cleared
This bit must be set to access all DM registers, if
this bit is cleared all DM registers except MTR bit
are write protected. This bit is set by software or by
hardware at the beginning of ICC Monitor execu-
tion. It is cleared by hardware at the end of the ICC
Monitor.
Bit 0 = SVR Switch Interrupt Vectors to RAM
This bit is set and cleared by software. It switches
the interrupt vector table location to RAM
0: Interrupt vector table located in ROM
1: Interrupt vector table located in RAM
0: ICC Monitor program is not running
1: ICC Monitor program is running
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ST7WIND21
6.6 Interrupt Vector Table Management
For added flexibility, the ST7WInD21 features two
interrupt vector table modes. After reset, the inter-
rupt vectors are located in ROM. The application
can switch the vectors to RAM by executing the
sequence in the procedure given below. Prior to
switching the vectors to RAM, the RAM area must
be initialised.
Procedure:
To switch the vectors from ROM to RAM:
1. Initialise the RAM area with the correct interrupt
vectors
2. Set the MTR bit in the DMCR1 register
3. Set the SVR bit in the DMCR2 register to ena-
ble the interrupt vector table in RAM
Table 8. Interrupt Mapping
Source
Exit
from
HALT
Vector
Address
(ROM)
Vector
Address
(RAM)
Register Priority
N°
Description
Block
Label
Order
RESET
TRAP
WDG
USB
Reset
yes
no
FFFEh-FFFFh
N/A
Software interrupt
FFFCh-FFFDh 02FCh-02FDh
FFFAh-FFFBh 02FAh-02FBh
FFF8h-FFF9h 02F8h-02F9h
0
1
Watchdog TLI interrupt
USB end of suspend
Port A external interrupts/
WDGCSR
USBISTR
PAEISR /
no
Highest
Priority
yes
2
ei0 / AWU
yes
FFF6h-FFF7h 02F6h-02F7h
Auto Wake up From HALT AWUCSR
3
4
5
6
7
ei1
Port B external interrupts
reserved
PBEISR
reserved
reserved
reserved
reserved
yes
no
no
no
no
FFF4h-FFF5h 02F4h-02F5h
FFF2h-FFF3h 02F2h-02F3h
FFF0h-FFF1h 02F0h-02F1h
FFEEh-FFEFh 02EEh-02EFh
FFECh-FFEDh 02ECh-02EDh
reserved
reserved
reserved
reserved
reserved
reserved
reserved
PS/2 0
ei3
PS/2 0 interrupt
Port G external interrupt
PS2CS0R
PGEISR
no
yes
8
FFEAh-FFEBh 02EAh-02EBh
9
PS/2 1
USB
PS/2 1 interrupt
PS2CS1R
USBISTR
T16CSR
TBUCSR
SPISR
no
no
FFE8h-FFE9h 02E8h-02E9h
FFE6h-FFE7h 02E6h-02E7h
FFE4h-FFE5h 02E4h-02E5h
FFE2h-FFE3h 02E2h-02E3h
FFE0h-FFE1h 02E0h-02E1h
10
11
12
13
USB interrupt
16-bit Timer
TBU
16-bits Timer interrupt
Time Base Unit interrupt
SPI interrupt
no
no
Lowest
Priority
SPI
yes
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ST7WIND21
INTERRUPTS (Cont’d)
6.7 EXTERNAL INTERRUPTS
found in the External Interrupt Enable Port x regis-
ter (EINENxR).
When an event occurs on an I/O port, this incom-
ing signal is interpreted as an external interrupt.
This signal can also be used to wake up the De-
vice from HALT. There are several controlling fac-
tors for external interrupts:
The external interrupt sensitivity is controlled by
the ISxx bits in the EICR (Figure 16). This control
allows to have up to 4 fully independent external
interrupt source sensitivities. Port B is divided on
two different controls, to allow more programming
flexibility.
– Priority (Hardware and Software)
– Enable/Disable control bits
– Sensitivity Control
Each external interrupt source can be generated
on four different events on the pin:
■ Falling edge
– Status Flag
■ Rising edge
■ Falling and rising edge
■ Falling edge and low level
Up to 8 signals on 8 ports can share one external
interrupt. For example, ei0 is shared on all 8 ports
of Port A.
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3).
6.7.1 Software and Hardware Priorities
External interrupts have default priorities associat-
ed with them. They are as listed in the Interrupt
Mapping table. These are the hardware priorities
and are unchangeable.
6.7.3 Status Flag
When an event occurs signalling that an external
interrupt is requested, a flag is set by hardware.
This flag informs the user which external interrupt
has occurred. Each external interrupt has its own
specific flag. They are found in the External Inter-
rupt Port x register (EIxSR). If the corresponding
external interrupt is enabled when this flag is set,
the external interrupt is serviced.
Software priorities are user assigned by program-
ming the appropriate bits in the Interrupt Software
Priority register (ISPRx) for a given external inter-
rupt. The whole external interrupt group will have
the same priority. For example, ISPR0 bits[4:5]
control the software priority for Port A’s external in-
terrupt, ei0.
If several interrupts are pending, the interrupts are
serviced according to their priority (software and or
hardware, according to which interrupt mode is be-
ing employed).
These two types of priorities are important to man-
age because they function in the same manner as
other interrupts for concurrent and nested modes.
6.7.2 Enable and Sensitivity Controls
If there is an unwanted pending interrupt, it can be
cleared by writing a different value in the ISx[1:0]
in the EICR.
At an external interrupt event, for the interrupt to
be acknowledged, it must be enabled. There is a
control bit for each external interrupt. They are
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ST7WIND21
INTERRUPTS (Cont’d)
Figure 16. Port A External Interrupt Control bits
PORT A 7:0 INTERRUPTS [7-0]
EICR
PAOR.x
PADDR.x
ISA1
ISA0
SENSITIVITY
CONTROL
PAx
EIASR
ITxF
FLAG
STATUS
EIENAR
ITxE
IT 7
IT 0
ei0 INTERRUPT SOURCE
ENABLE
CONTROL
EXTERNAL INTERRUPT CONTROL BLOCK
AWUFH
Oscillator
AWUEN
To Timer Input Capture
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ST7WIND21
INTERRUPTS (Cont’d)
Figure 17. Port B External Interrupt Control bits
PORT B4 INTERRUPT [12]
EICR
PBOR.4
ISB11 ISB10
PBDDR.4
SENSITIVITY
PB4
CONTROL
EIBSR
IT12F
FLAG
STATUS
EIENBR
IT12E
ENABLE
CONTROL
IT 12
EXTERNAL INTERRUPT CONTROL BLOCK
ei1 INTERRUPT SOURCE
IT 11
IT 8
PORT B 3:0 INTERRUPTS [11-8]
EICR
PBOR.x
PBDDR.x
ISB01 ISB00
SENSITIVITY
CONTROL
PBx
EIBSR
ITxF
FLAG
STATUS
EIENBR
ITxE
ENABLE
CONTROL
EXTERNAL INTERRUPT CONTROL BLOCK
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ST7WIND21
INTERRUPTS (Cont’d)
Figure 18. Port G External Interrupt Control bits
PORT G 1:0 INTERRUPTS [25-24]
PGEICR
PGOR.x
PGDDR.x
ISG1
ISG0
SENSITIVITY
CONTROL
PGx
PGEISR
ITxF
FLAG
STATUS
PGEIENR
ITxE
IT 25
IT 24
ei3 INTERRUPT SOURCE
ENABLE
CONTROL
EXTERNAL INTERRUPT CONTROL BLOCK
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INTERRUPTS (Cont’d)
6.7.4 Register Description
Bits 1:0 = ISA[1:0] Port A ei0 sensitivity IT[7-0}
The interrupt sensitivity, defined using the ISA[1:0]
bits, is applied to the ei0 external interrupts:
EXTERNAL INTERRUPT CONTROL REGISTER
(EICR)
Read/Write
ISA1 ISA0
External Interrupt Sensitivity
Reset Value: 0000 0000 (00h)
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
7
0
0
Falling edge only
0
ISB11 ISB10 ISB01 ISB00 ISA1 ISA0
Rising and falling edge
Bits 7:6 = Reserved, must be kept cleared.
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 5:4 = ISB1[1:0] Port B4 ei1 sensitivity IT12
The interrupt sensitivity, defined using the
ISB1[1:0] bits, is applied to the ei1 external inter-
rupts:
PORT A EXTERNAL INTERRUPT ENABLE
REGISTER (PAEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
ISB1 ISB1
External Interrupt Sensitivity
1
0
7
0
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
IT7E IT6E IT5E IT4E IT3E IT2E IT1E IT0E
Falling edge only
Rising and falling edge
Bits 7:0 = ITxE Port A interrupt enable
These bits are set and cleared by software.
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 3:2 = ISB0[1:0] Port B(3:0) ei1 sensitivity-
IT[11-8]
The interrupt sensitivity, defined using the
ISB0[1:0] bits, is applied to the ei1 external inter-
rupts:
PORT B EXTERNAL INTERRUPT ENABLE
REGISTER (PBEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
ISB0 ISB0
External Interrupt Sensitivity
1
0
0
0
IT12E IT11E IT10E IT9E IT8E
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Bits 7:5 = Reserved, must be kept cleared.
Falling edge only
Rising and falling edge
Bits 4:0 = ITxE Port B interrupt enable
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
These bits are set and cleared by software.
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
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ST7WIND21
INTERRUPTS (Cont’d)
PORT A EXTERNAL INTERRUPT STATUS
REGISTER (PAEISR)
PORT B EXTERNAL INTERRUPT STATUS
REGISTER (PBEISR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
IT7F IT6F IT5F IT4F IT3F IT2F IT1F IT0F
0
0
IT12F IT11F IT10F IT9F IT8F
Bits 7:0 = ITxF Port A interrupt flag
Bits 7:5 = Reserved, must be kept cleared.
These bits are set by hardware and cleared by
software (by writing 0).
0: ITx external interrupt not requested.
1: ITx external interrupt requested.
Bits 4:0 = ITxF Port B interrupt flag
These bits are set by hardware and cleared by
software (by writing 0).
0: ITx external interrupt not requested.
1: ITx external interrupt requested.
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ST7WIND21
INTERRUPTS (Cont’d)
PORT G EXTERNAL INTERRUPT CONTROL
REGISTER (PGEICR)
PORT G EXTERNAL INTERRUPT ENABLE REG-
ISTER (PGEIENR)
Read/Write
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
0
7
0
0
0
0
0
0
0
ISG1
ISG0
0
0
0
0
0
IT25E
IT24E
Bits 7:2 = Reserved.
Bits 7:2 = Reserved, must be kept cleared.
Bit 1:0 = ISG[1:0] Interrupt sensitivity Port G1:0
The interrupt sensitivity, defined using the ISG[1:0]
bits, is applied to the ei3 external interrupts:
Bit 1 = IT25E ei3 external interrupt enable
0: ei3 external interrupt disabled on port G1.
1: ei3 external interrupt enabled on port G1.
ISG1 ISG0
External Interrupt Sensitivity
Bit 0 = IT24 ei3 external interrupt enable
0: ei3 external interrupt disabled on port G0.
1: ei3 external interrupt enabled on port G0.
0
0
1
1
0
1
0
1
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
PORT G EXTERNAL INTERRUPT STATUS REGIS-
TER (PGEISR)
Read/Write
Reset Value: 0000 0000 (00h)
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
7
0
0
0
0
0
0
0
IT25F
IT24F
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = IT25F ei3 external interrupt flag
0: ei3 external interrupt not requested on port G1.
1: ei3 external interrupt requested on port G1.
Bit 0 = IT24F ei3 external interrupt flag
0: ei3 external interrupt not requested on port G0.
1: ei3 external interrupt requested on port G0.
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ST7WIND21
INTERRUPTS (Cont’d)
Table 9. Nested Interrupts Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
ei1
ei0/AWUFH
USB EOSuspend
WDG
0030h
0031h
0032h
0033h
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
1
ISPR0
Reset Value
1
1
reserved
reserved
reserved
reserved
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
ISPR1
Reset Value
T16
USB
PS2_1
SPI
PS2_1/ei3
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
ISPR2
Reset Value
TBU
I1_13
1
I0_13
1
I1_12
1
I0_12
1
ISPR3
Reset Value
1
1
1
1
EICR
Reset Value
0
0
0
0
ISB11
0
ISB10
0
ISB01
0
ISB00
0
ISA1
0
ISA0
0
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
0058h
0059h
005Ah
0078h
007Eh
PAEIENR
Reset Value
IT7E
0
IT6E
0
IT5E
0
IT4E
0
IT3E
0
IT2E
0
IT1E
0
IT0E
0
PBEIENR
Reset Value
0
0
0
0
0
0
IT12E
0
IT11E
0
IT10E
0
IT9E
0
IT8E
0
reserved
Reset Value
0
0
0
0
0
0
0
0
PAEISR
Reset Value
IT7F
0
IT6F
0
IT5F
0
IT4F
0
IT3F
0
IT2F
0
IT1F
0
IT0F
0
PBEISR
Reset Value
0
0
0
0
0
0
IT12F
0
IT11F
0
IT10F
0
IT9F
0
IT8F
0
reserved
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PGEICR
Reset Value
ISG1
0
ISG0
0
PGEIENR
Reset Value
IT25E
0
IT24E
0
PGEISR
Reset Value
IT25F
0
IT24F
0
0
0
0
0
0
0
0
0
0
0
DMCR1
Reset Value
MTR
0
0
0
0
DMCR2
Reset Value
SVR
0
0
0
0
0
0
0
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ST7WIND21
7 POWER SAVING MODES
7.1 INTRODUCTION
7.2 SLOW MODE
To give a large measure of flexibility to the applica-
tion in terms of power consumption, five main pow-
er saving modes are implemented in the Device
(see Figure 19):
■ Secondary Run Mode (See Section 5.1 on page
22
■ Slow
■ Wait (and Slow-Wait)
■ Auto Wake up From Halt (AWUFH)
■ Halt
This mode has two targets:
– to reduce power consumption by decreasing the
internal clock in the Device,
– to adapt the internal clock frequency (f
available supply voltage.
) to the
CPU
SLOW mode is controlled by two bits in the CMR
register which select the internal slow frequency
(f
).
CPU
In this mode, the master clock frequency (f
)
OSC
can be divided by 1, 2, 4, or 8. The CPU and pe-
ripherals are clocked at this lower frequency
After a RESET the main operating mode is select-
ed by default . This mode drives the Device (CPU
and embedded peripherals) by means of a master
clock which is based on the main oscillator fre-
(f
).
CPU
Note: SLOW-WAIT mode is activated by entering
WAIT mode while the Device is in SLOW mode.
quency (f
).
OSCMAIN
Figure 20. SLOW Mode Clock Transitions
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific CPU instruc-
tion whose action depends on the oscillator status.
f
f
/2
f
OSC2
OSC
OSC
f
CPU
Figure 19. Power Saving Mode Transitions
f
OSC
High
00
01
00
SMS1:0
MAIN RUN
SECONDARY RUN
RUN MODE
REQUEST
NEW SLOW
FREQUENCY
REQUEST
SLOW
WAIT
7.3 WAIT MODE
WAIT mode places the Device in a low power con-
sumption mode by stopping the CPU.
SLOW WAIT
This power saving mode is selected by executing
the “WFI” CPU instruction.
AUTO WAKE UP FROM HALT
HALT
All peripherals remain active. During WAIT mode,
the I bits in the CC register are forced to 0, ena-
bling all interrupts. All other registers and memory
remain unchanged. The Device remains in WAIT
mode until an interrupt or reset occurs. If the event
is an interrupt, the program counter immediately
branches to the starting address of the interrupt or
reset service routine. If the wake up event is a re-
set, before fetching the reset vector, there is a 256
CPU clock cycle delay to allow for stabilization.
Refer to Figure 21.
Low
POWER CONSUMPTION
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ST7WIND21
Figure 21. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I1, I0 BITS
ON
ON
OFF
CLEARED
N
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
ON
ON
ON
PERIPH. CLOCK
CPU CLOCK
1)
I1, I0 BITS
IF RESET
256 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: 1) Before servicing an interrupt, the CC
register is pushed on the stack. The I0 and I1
bit values for each interrupt are predefined by
the user in the ISPRx register. During the inter-
rupt routine these values are loaded into I0 and
I1 bits and cleared when the CC register is
popped.
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ST7WIND21
POWER SAVING MODES (Cont’d)
7.4 HALT MODE
7.4.1 HALT MODE RECOMMENDATIONS
HALT mode is the lowest power consumption
mode. HALT mode is entered by executing the
HALT instruction. The all the internal oscillators
are stopped, causing all internal processing to be
stopped, including the operation of the on-chip pe-
ripherals. Only peripherals with an external oscilla-
tor continue running.
– Make sure that an external event is available to
wake up the Device from Halt mode.
– When using an external interrupt to wake up the
Device, reinitialize the corresponding I/O as “In-
put Pull-up with Interrupt” before executing the
HALT instruction. The main reason for this is that
the I/O may be wrongly configured due to exter-
nal interference or by an unforeseen logical con-
dition.
Entering HALT mode clears the I bits in the CC
register, enabling interrupts. If an interrupt is pend-
ing, the Device wakes up immediately. Not all in-
terrupts will wake up the Device from HALT, only
those listed in the Interrupt Mapping Table in the
Interrupt section allow wake-up.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
These specific interrupts (as described in Table 8)
or a reset wakes up the Device from HALT mode.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– If a reset is the wake-up event, the main oscilla-
tor is immediately turned on and a 256 CPU cy-
cle delay is used to stabilize the oscillator. After
the start up delay, the CPU resumes operation
by fetching the reset vector.
– As the HALT instruction clears the I bits in the
CC register to allow interrupts, the user may
choose to clear all pending interrupt bits before
executing the HALT instruction. This avoids en-
tering other peripheral interrupt routines after ex-
ecuting the external interrupt routine
– If an interrupt is the wakeup event, the RC oscil-
lator is immediately turned on and the CPU im-
mediately resumes operation by servicing the
interrupt which woke it up. The user can choose
to switch to the main oscillator by programming
the CMR register.
corresponding to the wake-up event (reset or ex-
ternal interrupt).
Refer to Figure 22 for more details.
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ST7WIND21
Figure 22. HALT Mode Flow Chart
HALT INSTRUCTION
(AWUCSR.AWUEN=0)
HALT MODE:
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
OFF
OFF
OFF
OFF
N
RESET
Y
N
INTERRUPT
Y
RESET WAKEUP MODE:
MAIN OSCILLATOR
6MHz RC OSC
ON
INT. WAKEUP MODE:
OFF
PERIPH. CLOCK
OFF
OFF
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
OFF
ON
CPU CLOCK
Note: No software
execution while main
oscillator stabilizes.
ON
ON
USER INTERRUPT ROUTINE
256 CLOCK
CYCLES DELAY
Y
RETURN TO
CLK SWITCHING MODE:
HALT?
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
ON
ON
MAIN RUN MODE:
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
ON
N
ON
ON
OFF
CPU
Y
ON
ON
Note: Software can execute
while main oscillator
stabilizes.
POWER
NEEDED?
FETCH RESET VECTOR
N
MAIN RUN MODE:
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
ON
SECONDARY RUN MODE:
OFF
MAIN OSCILLATOR
6MHz RC OSC
PERIPH. CLOCK
CPU CLOCK
OFF
ON
ON
ON
1)
ON
ON
1)
USB and RF peripherals not functional at this frequency.
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ST7WIND21
POWER SAVING MODES (Cont’d)
7.5 AUTO WAKE UP FROM HALT MODE
If the Auto Wake Up From Halt feature is enabled,
a dedicated internal RC time base wakes up the
Device from HALT mode after a programmable
delay (generating an ei0 interrupt).
the AWU flag is set by hardware and an interrupt
wakes-up the Device from Halt mode. At the same
time the main oscillator is immediately turned on.
After this start-up delay, the CPU resumes opera-
tion by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
For more information, see Auto Wake Up From
Halt Interrupt section in the Interrupts chapter.
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to HALT mode with the addition of an internal
RC oscillator for wake-up.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency f
and then
AWU_RC
This mode is entered by executing the HALT in-
struction when the AWUEN bit in the AWUCSR
register has been set.
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
f
to the ICAP1 input of the 16-bit timer, al-
AWU_RC
AWU_RC
Figure 23. AWUFH Mode Block Diagram
lowing the f
to be measured using the main
oscillator clock as a reference timebase.
AWU RC
oscillator
Similarities with Halt mode
The following AWUFH mode behaviour is the
same as normal Halt mode:
to Timer input capture
f
AWU_RC
– The Device can exit AWUFH mode by means of
any interrupt with exit from Halt capability or a re-
set (see Section 7.4 "HALT MODE" on page 45).
AWUFH
interrupt
– When entering AWUFH mode, the I[1:0] bits in
the CC register are forced to 10b to enable inter-
rupts. Therefore, if an interrupt is pending, the
Device wakes up immediately.
AWUFH
prescaler/1 .. 255
(ei0 source)
– In AWUFH mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
None of the peripherals are clocked except those
which get their clock supply from another clock
generator (such as an external or auxiliary oscil-
lator like the AWU oscillator).
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(f
). Its frequency is divided by a fixed divid-
AWU_RC
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
Figure 24. AWUF Halt Timing Diagram
t
AWU
RUN MODE
(6MHz)
RUN MODE
(12MHz)
HALT MODE
f
CPU
f
AWU_RC
Cleared
by software
AWUFH interrupt
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ST7WIND21
POWER SAVING MODES (Cont’d)
Figure 25. AWUFH Mode Flow-chart
HALT INSTRUCTION
(AWUCSR.AWUEN=1)
AWU Mode
AWU RC OSC
ON
6MHz RC OSC OFF
MAIN OSC
PERIPHERALS 1)
CPU
OFF
OFF
OFF
10
I[1:0] BITS
N
RESET
N
INTERRUPT 2)
Y
Y
See Figure 22.HALT
Mode Flow Chart
Notes:
1. Peripheral clocked with an external clock source
can still be active.
2. Only an AWUFH interrupt and some specific in-
terrupts can exit the Device from HALT mode. Re-
fer to Table 8, “Interrupt Mapping,” on page 34 for
more details.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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ST7WIND21
POWER SAVING MODES (Cont’d)
7.5.0.1 Register Description
0: AWUFH (Auto Wake Up From Halt) mode disa-
bled
AWUFH CONTROL/STATUS REGISTER
(AWUCSR)
Read/Write (except bit 2 read only)
Reset Value: 0000 0000 (00h)
1: AWUFH (Auto Wake Up From Halt) mode ena-
bled
AWUFH PRESCALER REGISTER (AWUPR)
Read/Write
Reset Value: 1111 1111 (FFh)
7
0
AWU AWU AWU
EN
7
0
0
0
0
0
0
F
M
AWU AWU AWU AWU AWU AWU AWU AWU
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
Bits 7:3 = Reserved.
Bits 7:0 = AWUPR[7:0] Auto Wake Up Prescaler
These 8 bits define the AWUPR Dividing factor (as
explained below:
Bit 2 = AWUF Auto Wake Up Flag
This bit is set by hardware when the AWU module
generates an interrupt and cleared by software on
reading AWUCSR.
AWUPR[7:0]
Dividing factor
0: No AWU interrupt occurred
1: AWU interrupt occurred
00h
01h
...
Forbidden (See note)
1
...
Bit 1 = AWUM Auto Wake Up Measurement
This bit enables the AWU RC oscillator and con-
nects its output to the ICAP1 input of the 16-bit tim-
er. This allows the timer to be used to measure the
AWU RC oscillator dispersion and then compen-
sate this dispersion by providing the right value in
the AWUPR register.
FEh
FFh
254
255
In AWU mode, the period that the MCU stays in
Halt Mode (t
fined by
in Figure 24 on page 47) is de-
AWU
0: Measurement disabled
1
t
= AWUPR × ------------------------- + t
SU(AWURC)
AWU
1: Measurement enabled
f
AWURC
This prescaler register can be programmed to
modify the time that the MCU stays in Halt mode
before waking up automatically.
Bit 0 = AWUEN Auto Wake Up From Halt Enabled
This bit enables the Auto Wake Up From Halt fea-
ture: once HALT mode is entered, the AWUFH
wakes up the Device after a time delay defined by
the AWU prescaler value. It is set and cleared by
software.
Note: If 00h is written to AWUPR, either an inter-
rupt is generated immediately after a HALT in-
struction, or the AWUPR remains unchanged.
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ST7WIND21
Table 10. AWU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
AWUCSR
Reset Value
003Bh
003Ch
0
0
0
0
0
AWUF
AWUM
AWUEN
AWUPR
Reset Value
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
1
1
1
1
1
1
1
1
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ST7WIND21
8 I/O PORTS
8.1 INTRODUCTION
8.2.2 Output Modes
Setting the DDRx bit selects output mode. Writing
to the DR bits applies a digital value to the I/O
through the latch. Reading the DR bits returns the
previously stored value.
The I/O ports allow data transfer. An I/O port can
contain up to 8 pins. Each pin can be programmed
independently either as a digital input or digital
output. In addition, specific pins may have several
other functions. These functions can include exter-
nal interrupt, alternate signal input/output for on-
chip peripherals or analog input.
If an OR bit is available, different output modes
can be selected by software: push-pull or open-
drain. Refer to I/O Port Implementation section for
configuration.
8.2 FUNCTIONAL DESCRIPTION
Table 11. DR value and output pin status
A Data Register (DR) and a Data Direction Regis-
ter (DDR) are always associated with each port.
The Option Register (OR), which allows input/out-
put options, may or may not be implemented. The
following description takes into account the OR
register. Refer to the Port Configuration table for
Device specific information.
DR
Push-Pull
Open-Drain
0
1
V
V
OL
OL
V
Floating
OH
Note: When switching from input to output mode,
first set the DR bit to set the correct level to be ap-
plied on the pin, then write the DDR to configure
the pin as an output.
An I/O pin is programmed using the corresponding
bits in the DDR, DR and OR registers: bit x corre-
sponding to pin x of the port.
8.2.3 Alternate Functions
Many I/Os of the Device have one or more alter-
nate functions to output. This may include output
signals from, or input signals to, on-chip peripher-
als. The Device Pin Description table describes
which peripheral signals can be input/output to
which ports.
Figure 26 shows the generic I/O block diagram.
8.2.1 Input Modes
Clearing the DDRx bit selects input mode. In this
mode, reading its DR bit returns the digital value
from that I/O pin.
A signal coming from an on-chip peripheral can be
output on an I/O. To do this, enable the on-chip
peripheral as an output (enable bit in the peripher-
al’s control register). The peripheral configures the
I/O as an output and takes priority over standard I/
O programming. The I/O’s state is readable by ad-
dressing the corresponding I/O data register.
If an OR bit is available, different input modes can
be configured by software: floating or pull-up. Re-
fer to I/O Port Implementation section for configu-
ration.
Note: Writing to the DR modifies the latch value
but does not change the state of the input pin.
External Interrupt Function
In input mode, external interrupts can be enabled
by setting the corresponding bit in the PxEIENR
register.
Configuring an I/O as floating enables alternate
function input. It is not recommended to configure
an I/O as pull-up as this will increase current con-
sumption. Before using an I/O as an alternate in-
put, configure it without interrupt. Otherwise spuri-
ous interrupts can occur.
Falling or rising edge sensitivity is programmed in-
dependently for each interrupt vector. The Exter-
nal Interrupt Control Register (EICR) controls this
sensitivity.
Configure an I/O as input floating for an on-chip
peripheral signal which can be input and output.
Several pins may be tied to one external interrupt
vector. Refer to Pin Description to see which ports
have external interrupts.
Caution:
I/Os which can be configured as both an analog
and digital alternate function need special atten-
tion. The user must control the peripherals so that
the signals do not arrive at the same time on the
same pin. If an external clock is used, only the
clock alternate function should be employed on
that I/O pin and not the other alternate function.
External interrupts are hardware interrupts. Fetch-
ing the corresponding interrupt vector automatical-
ly clears the request latch. Modifying the sensitivity
bits will clear any pending interrupts.
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ST7WIND21
I/O PORTS (Cont’d)
Figure 26. I/O Port General Block Diagram
ALTERNATE
OUTPUT
From on-chip peripheral
1
0
REGISTER
ACCESS
V
33
P-BUFFER
(see table below)
ALTERNATE
ENABLE
BIT
PULL-UP
(see table below)
DR
V
V
33 OR DD
DDR
OR
PULL-UP
CONDITION
PAD
OR SEL
DDR SEL
DR SEL
N-BUFFER
DIODES
(see table below)
PxEIENR
ANALOG
INPUT
CMOS
SCHMITT
TRIGGER
1
0
ALTERNATE
INPUT
To on-chip peripheral
EXTERNAL
INTERRUPT
REQUEST (ei )
Combinational
Logic
FROM
OTHER
BITS
x
SENSITIVITY
SELECTION
Note: Refer to the Port Configuration table for Device specific information.
Table 12. I/O Port Mode Options
Diodes
Configuration Mode
Pull-Up
P-Buffer
to V
V
to V
SS
33 OR DD
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Off
On
Input
Off
On
On
Off
NI
On
Off
NI
Output
Open Drain (logic level)
True Open Drain
NI (see note)
Legend:
NI - not implemented
Off - implemented not activated
On - implemented and activated
Note: The diode to V
V
DD V
is not imple-
33 OR
DD
mented in the true open drain pads. A local protec-
tion between the pad and V is implemented to
protect the device against possible stress.
OL
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ST7WIND21
I/O PORTS (Cont’d)
Figure 27. Standard I/O Port Configurations
Hardware Configuration
V
V
DR REGISTER ACCESS
33
33
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
to on-chip peripherals
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
V
V
V
33
33
33
DR REGISTER ACCESS
R
PU
PAD
R/W
DR
DATA BUS
REGISTER
DR REGISTER ACCESS
V
V
V
33
33
33
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
from on-chip peripherals
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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ST7WIND21
Figure 28. I/O Port G Configurations
Hardware Configuration
PAGPUCR
REGISTER
V
DR REGISTER ACCESS
DD
V
DD
R
PU_PS2
W
R
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT to
ON-CHIP PS2 0 PERIPHERAL
INTERRUPT
CONDITION
EXTERNAL INTERRUPT
SOURCE (ei3)
PAGPUCR
REGISTER
V
V
DD
DD
DR REGISTER ACCESS
R
PU_PS2
PAD
R/W
DR
DATA BUS
REGISTER
V
DD
PG0
DP
+
-
USBRX
DM
V
DD
PG1
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, read-
ing the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the
alternate function reads the pin status given by the DR register content.
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ST7WIND21
Figure 29. I/O Port PA4:0 Configurations
Hardware Configuration
V
V
DR REGISTER ACCESS
33
DD
PULL-UP
CONDITION
R
W
R
PU
DR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
to on-chip peripherals
EXTERNAL INTERRUPT
SOURCE (ei )
x
INTERRUPT
CONDITION
V
V
33
V
33
DD
DR REGISTER ACCESS
R
PU
PAD
R/W
DR
DATA BUS
REGISTER
DR REGISTER ACCESS
V
V
33
V
33
DD
R
PU
R/W
DR
REGISTER
DATA BUS
PAD
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT
from on-chip peripherals
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
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ST7WIND21
Figure 30. I/O Port PA6:5 Configurations with Special Pull-ups
Hardware Configuration
PAGPUCR
REGISTER
PAOR
REGISTER
DR REGISTER ACCESS
V
V
V
DD
33
DD
R
PU_PS2
R
W
R
PU
PADR
REGISTER
DATA BUS
PAD
ALTERNATE INPUT
to on-chip peripherals
PAGPUCR
REGISTER
PAOR
REGISTER
V
V
V
33
V
DD
DD
33
DR REGISTER ACCESS
R
PU
R
PU_PS2
PAD
R/W
DR
REGISTER
DATA BUS
PAGPUCR
REGISTER
PAOR
REGISTER
V
V
V
V
33
DD
33
DD
DR REGISTER ACCESS
R
PU
R
PU_PS2
PAD
R/W
DR
REGISTER
DATA BUS
ALTERNATE
ENABLE
BIT
ALTERNATE
OUTPUT FROM
ON-CHIP PERIPHERALS
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, read-
ing the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the
alternate function reads the pin status given by the DR register content.
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ST7WIND21
Figure 31. I/O Port PA7 Configurations with Special Pull-ups
Hardware Configuration
PAGPUCR
REGISTER
PAOR
REGISTER
DR REGISTER ACCESS
V
V
V
DD
33
33
R
PU_USB
R
W
R
PU
PADR
REGISTER
DATA BUS
PAD
PAGPUCR
REGISTER
PAOR
REGISTER
V
V
V
33
V
33
DD
33
DR REGISTER ACCESS
R
PU
R
PU_USB
PAD
R/W
DR
REGISTER
DATA BUS
PAGPUCR
REGISTER
PAOR
REGISTER
V
V
V
V
33
33
33
DD
DR REGISTER ACCESS
R
PU
R
PU_USB
PAD
R/W
DR
REGISTER
DATA BUS
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ST7WIND21
I/O PORTS (Cont’d)
8.3 I/O PORT IMPLEMENTATION
DDR and PxEIENR registers and if the I bit in the
CC register is cleared (RIM instruction).
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as open drain.
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Event
Flag
Interrupt Event
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects.
External inter-
rupt on selected
external event
DDRx
PxEIENRx
-
Yes
Yes
8.4 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to the Electrical Characteristics
Section.
8.5 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the Device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the Device to exit from HALT mode.
8.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
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I/O PORTS (Cont’d)
8.7 Ports with Special Pull-ups
I/O Ports G0, G1, A5 and A6 have special pull-ups
for PS/2 compatibility. Port PA7 has a special pull-
up for USB compatibility. These are enabled
through the PAGPUCR register.
PORT A and G PULL UP CONTROL REGISTER
(PAGPUCR)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
USB-
PUP
PUPA6 PUPA5 PUPG1 PUPG0
0
0
Bits 7:5 = Reserved, must be kept cleared.
Bit 4 = USBPUP PA7 USB Pull-Up resistor enable
0: USB pull-up disabled on PA7.
1: USB pull-up enabled on PA7. This replaces the
PA7 OR pull-up function, if enabled.
Bit 3 = PUPA6 PA6 Pull-Up resistor enable
0: Special pull-up disabled on PA6.
1: Special pull-up enabled on PA6. This replaces
the PA6 OR pull-up function, if enabled.
Bit 2 = PUPA5 PA5 Pull-Up resistor enable
0: Special pull-up disabled on PA5.
1: Special pull-up enabled on PA5. This replaces
the PA5 OR pull-up function, if enabled.
Bit 1 = PUPG1 PG1 Pull-Up resistor enable
0: Special pull-up disabled on PG1.
1: Special pull-up enabled on PG1.
Bit 0 = PUPG0 PG0 Pull-Up resistor enable
0: Special pull-up disabled on PG0.
1: Special pull-up enabled on PG0.
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ST7WIND21
I/O PORTS (Cont’d)
Table 13. Port Configuration
Input
Output
Port
Pin name
OR = 0
OR = 1
OR = 0
OR = 1
pull-up (or special pullup if
enabled in PAGPUCR register)
PA7:5
floating
open drain
push-pull
Port A
PA4:0
PB4:0
floating
floating
pull-up
pull-up
open drain
open drain
push-pull
push-pull
Port B
Port G
pull-up (or special pullup if
enabled in PAGPUCR)
PG1:0
floating
open drain
Table 14. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
except where noted
0
0
0
0
0
0
0
0
0000h
0001h
0002h
0003h
0004h
0005h
0054h
0055h
0056h
0057h
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
MSB
LSB
0
0
0
0
0
0
1
0
MSB
LSB
PAGPUCR
PGDR
PUPG1
USBPUP PUPA6
PUPA5
PUPG0
LSB
MSB
PGDDR
PGOR
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ST7WIND21
9 ON-CHIP PERIPHERALS
9.1 WATCHDOG TIMER (WDG)
9.1.1 Introduction
■ Watchdog event (if the WDGA or IE bit is set)
when the T6 bit reaches zero
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates a Device reset or a Top Level Inter-
rupt (TLI) on expiry of a programmed time period,
unless the program refreshes the counter’s con-
tents before the T6 bit becomes cleared.
■ Hardware Watchdog event selectable by option
byte
9.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 65536 machine
cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
9.1.2 Main Features
If the watchdog is activated (the WDGA or IE bit is
set) and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it gener-
ates a Watchdog event.
■ Programmable free-running downcounter (64
increments of 65536 CPU cycles)
■ Watchdog event configurable as Reset or TLI
Figure 32. Watchdog Block Diagram
TLI
RESET
WATCHDOG CONTROL/STATUS REGISTER (WDGCSR)
IE
WDGTF
-
-
-
-
-
-
WATCHDOG CONTROL REGISTER (WDGCR)
T5
WDGA T6
T1
T0
T4
T2
T3
7-BIT DOWNCOUNTER
CLOCK DIVIDER
f
CPU
÷65536
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WATCHDOG TIMER (Cont’d)
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent a Watchdog event. This
downcounter is free-running: it counts down even
if the watchdog is disabled.
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
9.1.6 Generating a Software reset
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
9.1.4 Reset Mode
The value to be stored in the WDGCR register
must be between FFh and C0h (see Table 15):
9.1.7 Hardware Watchdog Options
Two options in the option byte can be used to en-
able hardware watchdog with Reset or TLI. If both
are enabled the Reset event has priority.
– The WDGA bit is set (watchdog reset enabled)
– The T6 bit is set to prevent generating an imme-
diate Watchdog reset
Refer to the Option Byte description.
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
WDGHWR WDGHWI
Behaviour when a Watchdog
timeout occurs
option
option
If WDGA=1, a reset is generated.
If WDGA=0 and IE=1, a TLI is
generated.
9.1.5 Interrupt Mode
0
0
The value to be stored in the WDGCR register
must be between 7Fh and 40h (see Table 15):
If WDGA=1 a reset is generated.
If WDGA=0, a TLI is generated.
0
1
1
x
– The IE bit in the WDGCSR register is set (watch-
dog interrupt enabled)
A reset is generated.
– The WDGA bit is cleared (watchdog reset disa-
bled)
Note: 0= option disabled, 1= option enabled
9.1.8 Low Power Modes
– The T6 bit is set to prevent generating an imme-
diate TLI
Mode
WAIT
HALT
Description
No effect on Watchdog
Watchdog counter frozen
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a TLI.
Table 15.Watchdog Timing (f
= 12 MHz)
CPU
CR Register CR Register
initial value initial value WDG timeout
9.1.9 Interrupts
Enable Exit
Control from from
Exit
Event
Flag
Interrupt Event
with
with
period (ms)
Bit
Wait
Halt
WDGA=1
WDGA=0
TLI
WDGTF
IE
Yes
No
Max
Min
FFh
C0h
7Fh
40h
349.525
5.461
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ST7WIND21
WATCHDOG TIMER (Cont’d)
9.1.10 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
CONTROL/STATUS REGISTER (WDGCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Reset Value: 0111 1111 (7Fh)
7
0
WDG
TF
7
0
0
0
0
0
0
0
IE
WDGA T6
T5
T4
T3
T2
T1
T0
Bit 7:2 = must be kept cleared.
Bit 7 = WDGA Watchdog Reset Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog generates a reset when T6 reaches 0.
0: Watchdog Reset disabled
Bit 1 = WDGTF Watchdog Timeout Flag (read/
clear).
This bit is set when T6 reaches 0. A TLI is gener-
ated when IE is set. This bit is reset by hardware
when the WDGCSR register is read by software.
0: No Watchdog Timeout has occured
1: A Watchdog Timeout has occured
1: Watchdog Reset enabled
Note: This bit is not used if the hardware watch-
dog reset option is enabled by option byte.
Note: This bit is not used if the watchdog is config-
ured to generate a reset (WDGA=1 or hardware
watchdog reset is selected by option byte).
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A
watchdog event is produced when it rolls over from
40h to 3Fh (T6 becomes cleared).
Bit 0 = IE Watchdog Interrupt Enable (read/set).
This bit enables the generation of a Top Level in-
terrupt when WDGTF is set. This bit is set by soft-
ware and only cleared by hardware after a reset.
This bit has no effect if the WDGA bit is set.
0: Watchdog Interrupt disabled
1: Watchdog Interrupt enabled
Note: This bit is forced to 1 if the Hardware Watch-
dog Interrupt option is chosen (by option byte).
Table 16. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
0012h
0013h
Reset Value
WDGCSR
-
-
-
-
-
-
WDGTF
0
IE
0
Reset Value
0
0
0
0
0
0
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ST7WIND21
9.2 TIMEBASE UNIT (TBU)
9.2.1 Introduction
When the counter rolls over from FFh to 00h, the
OVF bit is set and an interrupt request is generat-
ed if ITE is set.
The Timebase unit (TBU) can be used to generate
periodic interrupts.
The user can write a value at any time in the
TBUCVR register.
9.2.2 Main Features
■ 8-bit upcounter
■ Programmable prescaler
■ Period between interrupts: max. 5.46ms (at
9.2.4 Programming Example
In this example, timer is required to generate an in-
terrupt after a delay of 1 ms.
12MHz f
)
CPU
■ Maskable interrupt
Assuming that f
is 12 MHz and a prescaler di-
CPU
9.2.3 Functional Description
The TBU operates as a free-running upcounter.
vision factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 47
TBU timer ticks.
When the TCEN bit in the TBUCSR register is set
by software, counting starts at the current value of
the TBUCVR register. The TBUCVR register is in-
cremented at the clock rate output from the pres-
caler selected by programming the PR[2:0] bits in
the TBUCSR register.
In this case, the initial value to be loaded in the
TBUCVR must be (256-47) = 209 (D1h).
ld A, D1h
ld TBUCVR, A ; Initialize counter value
ld A 1Fh
;
ld TBUCSR, A ; Prescaler factor = 256,
; interrupt enable,
; TBU enable
Figure 33. TBU Block Diagram
MSB
LSB
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
TBU PRESCALER
f
CPU
0
0
OVF ITE TCEN PR2 PR1 PR0
TBUCSR REGISTER
INTERRUPT REQUEST
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ST7WIND21
TIMEBASE UNIT (Cont’d)
9.2.5 Low Power Modes
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Mode
WAIT
HALT
Description
No effect on TBU
TBU halted.
Reset Value: 0000 0000 (00h)
7
0
0
0
OVF ITE TCEN PR2
PR1 PR0
9.2.6 Interrupts
Bits 7:6 = Reserved. Forced by hardware to 0.
Bit 5 = OVF Overflow Flag
Enable
Control from
Bit
Exit
Exit
from
Halt
Interrupt
Event
Event
Flag
Wait
Counter Over-
flow Event
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
OVF
ITE
Yes
No
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
1: Counter overflow
Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
is generated when OVF=1.
9.2.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCVR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 3 = TCEN TBU Enable.
7
0
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
Bits 2:0 = PR[2:0] Prescaler Selection
Bits 7:0 = CV[7:0] Counter Value
These bits are set and cleared by software to se-
lect the prescaling factor.
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is continuously incremented by hardware if
TCEN=1.
PR2 PR1 PR0
Prescaler Division Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
65/181
ST7WIND21
TIMEBASE UNIT (Cont’d)
Table 17. TBU Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
TBUCVR
Reset Value
CV7
0
CV6
0
CV5
0
CV4
0
CV3
0
CV2
0
CV1
0
CV0
0
0029h
002Ah
TBUCSR
Reset Value
0
0
0
0
OVF
0
ITE
0
TCEN
0
PR2
0
PR1
0
PR0
0
66/181
ST7WIND21
9.3 16-BIT TIMER
9.3.1 Introduction
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
9.3.3 Functional Description
9.3.3.1 Counter
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Counter Register (CR):
– Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
Some devices of the ST7 family have two on-chip
16-bit timers. They are completely independent,
and do not share any resources. They are syn-
chronized after a Device reset as long as the timer
clock frequencies are not modified.
– Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
This description covers one or two 16-bit timers. In
the devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
9.3.2 Main Features
■ Programmableprescaler:fCPU dividedby2,4or8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slowerthantheCPUclockspeed)withthechoice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 18. The
value in the counter register repeats every
131 072, 262 144 or 524 288 CPU clock cycles de-
pending on the CC[1:0] bits.
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
The timer frequency can be f
or an external frequency.
/2, f
/4, f
/8
CPU
CPU
CPU
■ Reduced Power Mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 34.
*Note: Some timer pins may not available (not
bonded) in some devices. Refer to the device pin
out description.
67/181
ST7WIND21
16-BIT TIMER (Cont’d)
Figure 34. Timer Block Diagram
INTERNAL BUS
f
CPU
16-BIT TIMER PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
1/2
1/4
1/8
COUNTER
REGISTER
1
1
2
2
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
pin
CIRCUIT
6
EDGE DETECT
CIRCUIT2
ICAP2
pin
OCMP1
pin
LATCH1
LATCH2
0
ICF1 OCF1 TOF ICF2 OCF2
0
TIMD
(Control/Status Register)
OCMP2
pin
CSR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
(Control Register 1) CR1
(Control Register 2) CR2
(See note)
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See Device Interrupt Vector Table)
TIMER INTERRUPT
68/181
ST7WIND21
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Beginning of the sequence
Read
LS Byte
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.
MS Byte
At t0
is buffered
Other
instructions
Returns the buffered
LS Byte value at t0
Read
LS Byte
At t0 +∆t
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (Device awakened by an interrupt)
or from the reset count (Device awakened by a
Reset).
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
9.3.3.2 External Clock
After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.
Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
The counter is synchronised with the falling edge
of the internal CPU clock.
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.
If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.
69/181
ST7WIND21
16-BIT TIMER (Cont’d)
Figure 35. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 36. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFC
FFFD
0000
0001
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Figure 37. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
0000
FFFC
FFFD
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is run-
ning.
70/181
ST7WIND21
16-BIT TIMER (Cont’d)
9.3.3.3 Input Capture
When an input capture occurs:
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 39).
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
MS Byte
LS Byte
ICiR
ICiHR
ICiLR
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
ICiR register is a read-only register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
Notes:
counter: (f
/CC[1:0]).
CPU
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
– Select the timer clock (CC[1:0]) (see Table 18).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
And select the following in the CR1 register:
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
71/181
ST7WIND21
16-BIT TIMER (Cont’d)
Figure 38. Input Capture Block Diagram
ICAP1
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
ICAP2
pin
(Status Register) SR
ICF1
ICF2
0
0
0
IC2R Register
IC1R Register
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
COUNTER
IEDG2
CC0
CC1
Figure 39. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
Note: The active edge is the rising edge.
Note: The time between an event on the ICAPi pin
and the appearance of the corresponding flag is
from 2 to 3 CPU clock cycles. This depends on the
moment when the ICAP event happens relative to
the timer clock.
72/181
ST7WIND21
16-BIT TIMER (Cont’d)
9.3.3.4 Output Compare
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
∆t f
* CPU
PRESC
∆ OCiR =
– Sets a flag in the status register
– Generates an interrupt if enabled
Where:
∆t
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
f
CPU
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see Table 18)
PRESC
MS Byte
LS Byte
OCiR
OCiHR
OCiLR
If the timer clock is an external clock, the formula
is:
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
∆ OCiR = ∆t f
* EXT
Where:
Timing resolution is one count of the free running
counter: (f
∆t
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
).
CC[1:0]
CPU/
f
EXT
Procedure:
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
To use the output compare function, select the fol-
lowing in the CR2 register:
1. Reading the SR register while the OCFi bit is
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
set.
2. An access (read or write) to the OCiLR register.
– Select the timer clock (CC[1:0]) (see Table 18).
And select the following in the CR1 register:
The following procedure is recommended to pre-
vent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Select the OLVLi bit to applied to the OCMPi pins
after the match occurs.
– Write to the OCiHR register (further compares
are inhibited).
– Set the OCIE bit to generate an interrupt if it is
needed.
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
When a match is found between OCRi register
and CR register:
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
– OCFi bit is set.
73/181
ST7WIND21
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
/2, OCFi and
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
CPU
OCMPi are set while the counter value equals
the OCiR register value (see Figure 41 on page
75). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
/4, f
/8 or in
CPU
CPU
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR regis-
ter value plus 1 (see Figure 42 on page 75).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 40. Output Compare Block Diagram
16 BIT FREE RUNNING
OC1E
CC1 CC0
OC2E
COUNTER
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
Latch
1
OCIE
FOLV2 FOLV1OLVL2
OLVL1
OCMP1
Pin
16-bit
16-bit
Latch
2
OCMP2
Pin
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
74/181
ST7WIND21
16-BIT TIMER (Cont’d)
Figure 41. Output Compare Timing Diagram, f
=f
/2
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 42. Output Compare Timing Diagram, f
=f
/4
TIMER
CPU
INTERNAL CPU CLOCK
TIMER CLOCK
2ECF 2ED0 2ED1 2ED2
2ED3
2ED4
2ED3
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
75/181
ST7WIND21
16-BIT TIMER (Cont’d)
9.3.3.5 One Pulse Mode
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Procedure:
t * f
To use one pulse mode:
CPU
- 5
OCiR Value =
1. Load the OC1R register with the value corre-
sponding to the length of the pulse (see the for-
mula in the opposite column).
PRESC
Where:
t
= Pulse period (in seconds)
2. Select the following in the CR1 register:
f
= CPU clock frequency (in hertz)
CPU
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
= Timer prescaler factor (2, 4 or 8 depend-
ing on the CC[1:0] bits, see Table 18)
PRESC
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
If the timer clock is an external clock the formula is:
OCiR = t f
-5
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
* EXT
Where:
t
= Pulse period (in seconds)
3. Select the following in the CR2 register:
f
= External timer clock frequency (in hertz)
– Set the OC1E bit, the OCMP1 pin is then ded-
icated to the Output Compare 1 function.
EXT
– Set the OPM bit.
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 43).
– Select the timer clock CC[1:0] (see Table 18).
One pulse mode cycle
Notes:
ICR1 = Counter
When
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
OCMP1 = OLVL2
event occurs
on ICAP1
Counter is reset
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
to FFFCh
ICF1 bit is set
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
When
Counter
OCMP1 = OLVL1
= OC1R
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
When a valid event occurs on the ICAP1 pin, the
counter value is loaded in the ICR1 register. The
counter is then initialized to FFFCh, the OLVL2 bit
is output on the OCMP1 pin and the ICF1 bit is set.
5. When one pulse mode is used OC1R is dedi-
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
76/181
ST7WIND21
16-BIT TIMER (Cont’d)
Figure 43. One Pulse Mode Timing Example
2ED3
01F8
IC1R
FFFC FFFD FFFE
2ED0 2ED1 2ED2
2ED3
FFFC FFFD
01F8
COUNTER
ICAP1
OLVL2
OLVL1
OLVL2
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 44. Pulse Width Modulation Mode Timing Example
2ED0 2ED1 2ED2
34E2 FFFC
FFFC FFFD FFFE
34E2
COUNTER
OCMP1
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
77/181
ST7WIND21
16-BIT TIMER (Cont’d)
9.3.3.6 Pulse Width Modulation Mode
18).
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
OCMP1 = OLVL2
When
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are loaded in
their respective shadow registers (double buffer)
only at the end of the PWM period (OC2) to avoid
spikes on the PWM output pin (OCMP1). The
shadow registers contain the reference values for
comparison in PWM “double buffering” mode.
Counter
= OC2R
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Note: There is a locking mechanism for transfer-
ring the OCiR value to the buffer. After a write to
the OCiHR register, transfer of the new compare
value to the buffer is inhibited until OCiLR is also
written.
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
t * f
Unlike in Output Compare mode, the compare
function is always enabled in PWM mode.
CPU
- 5
OCiR Value =
PRESC
Where:
t
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
Procedure
f
To use pulse width modulation mode:
CPU
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see Table 18)
PRESC
If the timer clock is an external clock the formula is:
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
OCiR = t f
-5
* EXT
Where:
t
= Signal or pulse period (in seconds)
3. Select the following in the CR1 register:
f
= External timer clock frequency (in hertz)
EXT
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC1R register.
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 44)
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with OC2R register.
Notes:
1. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
2. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table
78/181
ST7WIND21
16-BIT TIMER (Cont’d)
3. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
4. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
9.3.4 Low Power Modes
Mode
Description
No effect on 16-bit Timer.
WAIT
Timer interrupts cause the Device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the Device is woken up by a RESET.
HALT
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
9.3.5 Interrupts
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
Yes
Yes
Yes
Yes
Yes
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
ICF1
ICF2
No
No
No
No
No
ICIE
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
OCF1
OCF2
TOF
OCIE
TOIE
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
9.3.6 Summary of Timer modes
AVAILABLE RESOURCES
MODES
Input Capture 1
Input Capture 2
Yes
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
1)
3)
2)
Not Recommended
Not Recommended
Partially
No
PWM Mode
No
No
1)
2)
3)
See note 4 in Section 9.3.3.5 "One Pulse Mode" on page 76
See note 5 in Section 9.3.3.5 "One Pulse Mode" on page 76
See note 4 in Section 9.3.3.6 "Pulse Width Modulation Mode" on page 78
79/181
ST7WIND21
16-BIT TIMER (Cont’d)
9.3.7 Register Description
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1:Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
CONTROL REGISTER 1 (CR1)
Read/Write
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no suc-
cessful comparison.
Reset Value: 0000 0000 (00h)
7
0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
80/181
ST7WIND21
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 3, 2 = CC[1:0] Clock Control.
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer re-
mains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
The timer clock mode depends on these bits:
Table 18. Clock Control Bits
Timer Clock
fCPU / 4
CC1
CC0
0
0
1
0
1
0
fCPU / 2
fCPU / 8
External Clock (where
available)
1
1
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer re-
mains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
81/181
ST7WIND21
16-BIT TIMER (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read Only
Note: Reading or writing the ACLR register does
not clear TOF.
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
0
0
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
Bit 7 = ICF1 Input Capture Flag 1.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it
freezes the timer prescaler and counter and disa-
bled the output functions (OCMP1 and OCMP2
pins) to reduce power consumption. Access to the
timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: Timer prescaler, counter and outputs disabled
1:The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.
Bits 1:0 = Reserved, must be kept cleared.
82/181
ST7WIND21
16-BIT TIMER (Cont’d)
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
OUTPUT COMPARE
(OC1HR)
1
HIGH REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
7
0
MSB
LSB
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
OUTPUT COMPARE
(OC1LR)
1
LOW REGISTER
Read Only
Reset Value: Undefined
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
7
0
MSB
LSB
MSB
LSB
83/181
ST7WIND21
16-BIT TIMER (Cont’d)
OUTPUT COMPARE
(OC2HR)
2
HIGH REGISTER
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read/Write
Reset Value: 1000 0000 (80h)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE
(OC2LR)
2
LOW REGISTER
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read/Write
Reset Value: 0000 0000 (00h)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to CSR register does not clear the TOF bit in the
CSR register.
7
0
MSB
LSB
7
0
COUNTER HIGH REGISTER (CHR)
MSB
LSB
Read Only
Reset Value: 1111 1111 (FFh)
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
This is an 8-bit register that contains the high part
of the counter value.
Read Only
Reset Value: Undefined
7
0
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
MSB
LSB
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the CSR register clears the TOF bit.
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).
7
0
MSB
LSB
7
0
MSB
LSB
84/181
ST7WIND21
16-BIT TIMER (Cont’d)
Table 19. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CR2
Reset Value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
CR1
Reset Value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
CSR
Reset Value
ICF1
-
OCF1
-
TOF
-
ICF2
-
OCF2
-
TIMD
0
-
-
-
-
IC1HR
Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
-
-
IC1LR
Reset Value
MSB
-
LSB
-
-
-
-
-
OC1HR
Reset Value
MSB
1
LSB
0
0
0
1
1
1
1
-
0
0
1
1
1
1
-
0
0
1
1
1
1
-
0
0
1
1
1
1
-
0
0
1
1
1
1
-
0
0
1
0
1
0
-
OC1LR
Reset Value
MSB
0
LSB
0
CHR
Reset Value
MSB
1
LSB
1
CLR
Reset Value
MSB
1
LSB
0
ACHR
Reset Value
MSB
1
LSB
1
ACLR
Reset Value
MSB
1
LSB
0
IC2HR
Reset Value
MSB
-
LSB
-
IC2LR
Reset Value
MSB
-
LSB
-
-
-
-
-
-
-
OC2HR
Reset Value
MSB
1
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0C2LR
Reset Value
MSB
0
LSB
0
85/181
ST7WIND21
9.4 RF COMMUNICATION
9.4.1 Introduction
■ 27 MHz Band PLL Synthesizer
– Channel frequency: 26.905 to 27.305 MHz in
The RF Communication block is a fully integrated
dual receiver. It operates in the 27 MHz band cov-
ering worldwide usage. It supports NRZ data and
offers a cost-saving solution requiring a minimum
of external components: crystal, PLL loop filter or
biasing resistors.
10KHz steps
■ FSK demodulation
■ Compatible with NRZ data (1.5K to 5Kbits/s
data rate supported)
■ Flexible data decoding using the 16-bit timer
It contains two receivers which can operate simul-
taneously (Refer to Figure 45).
input capture function
■ Receiver Modulation Index capability:1.9 to 3.2
at 2.5 Kbits/s; 1.2 to 2.1 at 5 Kbits/s
9.4.2 Main Features
■ Single 12 MHz crystal oscillator system
-4
■ 5 µV input sensitivity with BER=10
■ 36 dB of adjacent channel rejection (at 50 KHz)
Figure 45. RF General Block Diagram
DIGITAL BLOCK
RECEIVER
CONTROLLER 0
RXDATA0
ANALOG FRONT
DSP
END BLOCK
RECEIVER
CONTROLLER 1
RXDATA1
COMMON
To 16-Bit Timer
CONTROLLER
86/181
ST7WIND21
RF COMMUNICATION(Cont’d)
9.4.3 Functional Description
The demodulator principle is I/Q low IF (intermedi-
ate frequency) with a 15kHz offset.
Figure 46 shows the block diagram of the RF ana-
log front end section.
Figure 46. RF Analog Front End Block Diagram
LO1
PLL
BIAS / VREF
Lock
SYNTH
I
∆Σ ADC
RXPIN
LNA
RXNIN
Q
∆Σ ADC
I
∆Σ ADC
LNA
Q
∆Σ ADC
Lock
LO0
PLL
SYNTH
BIAS / VREF
87/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.3.1 Receiver Overview
RF Analog Front End
– Intermediate Frequency Local Oscillator (IFLO)
Mixer
– Channel Filter & Decimation
– FM Discriminator
– Baseband Filter
– Slicer
The RF analog front end of the receiver is an LNA
(Low Noise Amplifier), including an attenuator,
which first amplifies the signal. The signal is then
down-mixed into the low Intermediate Frequency
range (15kHz). The low-pass filter keeps this sig-
nal in the bandwidth from DC up to 100kHz. The
delta-sigma ADC and the decimator filter convert
the analog signal into digital words.
The mixer function mixes the I and Q signals com-
ing from the analog front end with the output of a
baseband complex oscillator (IFLO) to mix from
the IF down to DC. The IFLO has a programmable
frequency allowing small frequency offsets.
Once the signal is mixed, the DSP works at base-
band frequency range.
The signal is digitally down-mixed to DC frequen-
cy, and the digital demodulator provides the data
stream to the digital block (refer to Figure 47.Digit-
al Receiver Block Diagram).
The channel filter isolates the wanted channel and
the result is decimated.
The channel filter & decimation output is converted
in the FM discriminator from cartesian to polar.
The resulting magnitude is used as the signal
strength indicator (RSS) and the angle derivative
is used to calculate instantaneous frequency.
The slicer produces an oversampled version of bi-
nary data.
The RXDATA output is connected internally to the
input capture of the 16-bit timer.
The PLL synthesizer must be programmed to se-
lect the channel to be demodulated (with a 15kHz
frequency offset).
The Electrical Characteristics section provides the
data rate and frequency deviation allowed for the
receiver.
RF Digital block
The digital block is based on a DSP with embed-
ded firmware which generates the data stream.
The DSP functions for the receiver are shown in
Figure 47:
Figure 47. Digital Receiver Block Diagram
2
10
I
IFLO
Channel Filter &
Decimation
FM
Baseband
Filter
Slicer
8
RXDATA
To 16-bit
timer
Q
Discriminator
Mixer
input
capture
16
16
RXRSSR
Register
88/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.3.2 PLL Synthesizer
Figure 49. Receiver Frequency Plan
The Device includes an integrated PLL synthesiz-
er which allows to demodulate any channel fre-
quency from 26.905MHz up to 27.305MHz in
steps of 10kHz.
f
f
f
LO2
LO0
LO1
The reference clock is provided by the 12MHz
crystal oscillator, and then multiplied by the rele-
vant factor defined using RXnCFR registers.
The PLL synthesizer requires only few external
components for loop stabilization: two capacitors
and one resistor, as shown in Figure 48 on page
89.
Freq
f
f
f
f
f
RF0
RF1
RF2’
RF2
RF1’
50kHz
50kHz
15kHz
Figure 48. PLL Synthesizer Application
Device
The receiver is designed to work on channels
spaced 50kHz apart, with 15kHz of Intermediate
Frequency.
V18_OUT_PLLn
100nF
VSS_RF
Two-channel environment
The best way to configure a 2-channel environ-
V18_LOOP_PLLn
560
ment is: f
and f
are the channels of a two
RF0
RF1
RF0
220nF
channel system, f
is lower than f
. The f
Ω
RF1 RF0
CPOUTn
signal is demodulated with local oscillator 0 (f
with local oscillator 1 (f
set at 15kHz lower than f
)
LO0
and f
). f
LO1
must be
RF1
LO1
LO0
and f
at 15kHz
RF0
22nF
higher than f
ister.
by programming the RXnCF reg-
RF1
The frequency error is about 7kHz when the bit
status LOCKn rises. This error decreases down to
less than 1kHz (37ppm), after a further delay of
about 100µs.
For example, in order to select f
at 27.055MHz
RF0
and f
at 27.105MHz, f
may be set to
RF1
LO0
27.04MHz and f
may be set to 27.12MHz with
LO1
the RXnCF register. Then, the user must select
the wanted channel, by programming the RXnOFF
9.4.3.3 Receiver Frequency plan
Figure 49 shows the frequency plan of a typical re-
ceiver application involving the Device.
register (for example, RXnOFFR may be set to
0
+15kHz, RXnOFFR may be set to -15kHz).
1
89/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.3.4 Receiver characteristics Sensitivity
Adjacent channel rejection (ACR)
The “sensitivity” level is associated with a single
signal to be received. In order to reach a targeted
BER (Bit Error Rate) for the demodulator, the input
signal needs to be at or above a minimum level.
This minimum level is the “sensitivity” level. Figure
50 shows the RF receiver sensitivity level.
A signal in the adjacent channel (unwanted signal
at +/-50kHz of frequency offset) may affect the
BER if the level of this unwanted signal is above
the adjacent channel rejection specification limit
(see Figure 51).
The receiver is able to receive the wanted channel
(W Channel) until the power level of the unwanted
adjacent channel (UW Chan.) is less than 36dB
above the wanted channel. This is assuming that
the wanted signal is 3dB over the reference sensi-
tivity level, as defined above.
Figure 50. Reference Sensitivity Level
The RF demodulator template of adjacent channel
rejection is shown in Figure 51.
Notes:
-93dBm
1. One of the limiting factors is the phase noise of
the receiver and the phase noise of the interfering
signal.
2. It is assumed that the interfering signal (single
tone generator) has phase noise characteristics
better than 100dBc/Hz @ 50kHz.
-4
With BER=10 (under 50Ω)
90/181
ST7WIND21
RF COMMUNICATION (Cont’d)
Figure 51. Reference In-Band Interferer Level
suming that the wanted signal is 3dB above the
reference sensitivity level, as defined in Figure 50.
-42dBm
-45dBm
-48dBm
The RF demodulator template of image suppres-
sion channel rejection is shown in Figure 52.
For example, if RXnOFFR is set to -15kHz, then
the image frequency is set to +15kHz. An unwant-
ed signal in the image frequency is attenuated of
30dB with respect to the wanted signal.
-54dBm
36dB
Figure 52. Image Suppression Level
-90dBm
-60dBm
-90dBm
-4
With BER=10 (under 50Ω)
Image suppression (IMR)
As a consequence, setting the frequency offset will
automatically define where the image frequency
will be: -(RXnOFFR). The receiver is sensitive to
that frequency, with (at least) 30dB of attenuation.
Out-of-Band Interferer Reference Level
The receiver is able to receive the wanted channel
(W Channel) until the power level of the unwanted
adjacent channel (in the Image frequency) is less
than 30dB above the wanted channel. This is as-
A dual single tone signal at frequencies F +∆F and
C
F +2∆F can affect the bit error rate on the wanted
C
rd
signal at frequency F (due to 3 order inter-mod-
C
ulation distortion). The limit of these two interferer
signals are specified as shown in Figure 53.
91/181
ST7WIND21
RF COMMUNICATION (Cont’d)
Figure 53. Out-of-Band Interferer Reference
Level
Receiver Compression / Saturation
Figure 54 shows the maximum input signal level
allowed before saturation of the analog chain at
10mV (-27dBm) with attenuator disabled and
50mV (-13dBm) with attenuator enabled.
-45dBm
Figure 54. System Dynamic
RSS Register value
100000
10000
1000
100
10
-90dBm
∆F>200kHz
-4
With BER=10 (under 50Ω)
1
or
Att OFF
This dual channel emission can be either on upper
frequencies (as shown in Figure 53), or on lower
or
Att ON
frequencies (F ; F -∆F; F -2∆F)
C
C
C
Input Attenuator
RSS Register Overflow
The analog RF chain includes an input attenuator.
It can be set or reset using the RXATN bit.
Attenuator disabled
Non functional area
Desensitization area
Sensitive area
Attenuator enabled
When the received signal is high (close to the sat-
uration of the chain), the attenuator can be used to
reduce the gain of the whole analog chain (both re-
ceivers are then attenuated). The user can choose
to enable or disable this attenuator depending on
the value of the RXnRSS register, which provides
the strength of the demodulated signal in the de-
modulation channel.
Insensitive area
Receiver Desensitization
This phenomenon is directly linked to compression
(see above).
When the received signals become large enough
at the input of the LNA, the receiver chain (LNA,
mixers, low pass filter and ADC) saturates as
shown in Figure 54. The total gain of this chain is
then reduced.
If the chain receives an (unwanted) strong signal
and a wanted signal with a lower amplitude, then
the level of the wanted signal is decreased.
This is due to the loss of gain due to the strong sig-
nal which saturates the chain.
92/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.3.5 Device Power Supply Decoupling
Figure 55. RF Voltage Regulator Enable
Sequence
The RF Analog Front End is divided into 5 different
blocks in order to guarantee optimum radio char-
acteristics (power supply decoupling). Figure 56
shows how to decouple these power supplies.
Enable
V18REFn
The noise level on these power supplies must be
checked properly, in order to guarantee the overall
RF performance.
No
See also Electrical Characteristics section: Sec-
tion 11.11.1.1 "Characterization Conditions" on
page 164.
Is 35µs delay
elapsed?
Important note: each of the RF regulators can be
Yes
powered
on/off
individually
through
the
Enable
REG18_xxx
RFREGCRn register. The sequence used to ena-
ble RF regulators is shown in Figure 55.
93/181
ST7WIND21
RF COMMUNICATION (Cont’d)
Figure 56. Device Power Supply Decoupling and External Components
V
V
are power supplies generated through internal 1.8V regulators. They must not be shorted together.
must be star routed as cleanly as possible.
18_XXX
SS_XXX
Note: This does not represent the Device pin-out.
100nF
100nF
100nF
220nF
560
22nF
Ω
56KΩ/1%
LNA
REF
PLL SYNTH
RXPIN
3K
LNA
RXNIN
PLL
PLL
ADC
ADC
0
1
0
1
VSS_SUB_RF
LNA
PLL SYNTH
REF
56KΩ/1%
560
Ω
22nF
220nF
100nF
100nF
94/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.3.6 Application Examples
Note: the antenna frequency response should be
stable within the operating band. The antenna
should attenuate outband signals to improve over-
all system performance.
Figure 57 shows a typical application schematic,
with a characteristic impedance of 3KΩ for the an-
tenna and the input (off-chip resistor).
9.4.4 Low Power Modes
Figure 57. Typical Receiver Application
Mode
WAIT
Description
Device
No effect on RF Communication peripheral.
RF Communication peripheral registers are
frozen.
5pF
10nF
In halt mode, the RF Communication periph-
eral is inactive. Before entering halt mode,
the receivers must be disabled. Before re-
suming operations, the 12MHz oscillator
must be selected.
RXPIN
RXNIN
HALT
LNA
3KΩ*
100pF
10nF
5pF
9.4.5 Interrupts
3KΩ antenna
The RF Communication peripheral does not man-
age any interrupt sources as data decoding is per-
formed using the 16-bit timer.
95/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.6 Register Description
Bit 6 = RXT RX Test
This bit is set and cleared by software. It enables
the output of RXnDATA on PB0 and PB1 pins.
0: No effect on PB0 and PB1 pins (used as stand-
ard I/O pins)
The register map of the RF peripheral is divided
into pages. Each page allows access to a dedicat-
ed controller which is selected through the RF-
PAGER register. Each controller provides the user
with control registers for setting RF parameters.
1: RXn DATA output available on PB0 and
PB1pins
These parameters must be static during opera-
tions, but may be changed while the receiver is
disabled. All RF parameters are taken into account
by the DSP when the receiver is enabled.
Bit 5:2 = Reserved, must be kept cleared.
9.4.6.1 RF Page Selector
Bits 1:0 = RFP[1:0] RF Page Selection
These bits are set and cleared by software. They
select the RF page as shown in the table below.
RF PAGE SELECTION REGISTER
(RFPAGER)
Read/Write
RFP1 RFP0 Selected
Peripheral
Reset Value: 0000 0000 (00h)
bit
bit
RF Page
RFCSR, RXnCSR and
RXnRSSR
0
0
0
7
0
0
0
1
1
1
0
1
1
2
3
RF Common Controller
RF Receiver Controller 0
RF Receiver Controller 1
RXT
0
0
0
0
RFP1 RFP0
Bit 7 = Reserved, must be kept cleared.
Table 20. RF Page Selector Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
RFPAGER
0
0
RXT
0
0
0
0
0
0
0
0
0
RFP1
0
RFP0
0
60h
Reset Value
96/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.6.2 RF Common Controller
SYNTHESIZER REGISTER (RFSYNR)
Read/Write
The RF Common Controller provides the user with
control registers for setting the RF parameters that
are common to the two channel receivers.
Reset value: 0000 0000 (00h)
7
0
CONTROL/STATUS REGISTER (RFCSR)
Read/Write (except bits 2 and 3)
Reset value: 0000 0000 (00h)
D7
D6
D5
D4
D3
D2
D1
D0
Bits 7:0 = D[7:0] Synthesizer Reference Divider
This register configures the reference frequency to
be used by both synthesizers.
7
0
0
LOCK LOCK RX
RX
INV ATN
Software must write 96h in this register to set the
reference frequency to 80 kHz.
0
0
0
1
0
RF REGULATOR CONTROL REGISTER 0
(RFREGCR0)
Bits 7:4 = Reserved, must be kept cleared.
Read/Write
Reset value: 0000 0000 (00h)
Bit 3 = LOCK1 In-lock Indicator for RX1 Synthesiz-
er (Read only)
This bit is set and cleared by hardware.
0: RX1 synthesizer not locked
1: RX1 synthesizer locked
7
0
0
0
REG REG REG REG
04 03 02 01
0
0
Bit 2 = LOCK0 In-lock Indicator for RX0 Synthe-
sizer (Read only)
This bit is set and cleared by hardware.
Bits 7:5 = Reserved, must be kept cleared.
0: RX0 synthesizer not locked
1: RX0 synthesizer locked
Bits 4:1 = REG0[4:1] Regulator control bits
These bits are set and cleared by software. They
can be used to individually power on and power off
the various regulators. Refer to the Supply Man-
agement Chapter for a description of the regula-
tors.
Bit 1 = RXINV Inverter enable
This bit is set and cleared by software. It is used to
invert the receiver I and Q signals.
0: Inverter disabled
0: Regulator off
1: Regulator on
1: Inverter enabled
Bit 0 = RXATN Attenuator enable
This bit is set and cleared by software. It is used to
control the 14 dB receiver attenuator.
0: Attenuator disabled
Bit 0 = Reserved, must be kept cleared.
REG0 bits
REG01
REG02
REG03
REG04
Meaning
V18REF0
1: Attenuator enabled
REG18_LNA
REG18_ADC0
REG18_PLL0
97/181
ST7WIND21
RF COMMUNICATION (Cont’d)
RF REGULATOR CONTROL REGISTER 1
(RFREGCR1)
TRACK SLICER WEIGHTING REGISTER
(RFTSWR)
Read/Write
Read/Write
Reset value: 0000 0000 (00h)
Reset value: 0000 0000 (00h)
7
0
0
0
7
0
REG REG
14 13
REG
11
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Bits 7:0= D[7:0] Slicer Weighting
Bits 7:5 = Reserved, must be kept cleared.
This register defines the slicer time constant. Au-
thorized values are listed in the following table:
Bits 4:3 = REG1[4:3] Regulator control bits
D[7:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
Slicer time constant (ms)
Infinite
These bits are set and cleared by software. They
can be used to individually power on and power off
the regulators. Refer to the Supply Management
Chapter for a description of the regulators.
0: Regulator off
699.051
349.525
233.017
174.763
139.810
116.508
99.864
1: Regulator on
REG1 bits
REG11
Meaning
V18REF1
REG13
REG18_ADC1
REG18_PLL1
87.381
REG14
77.672
69.905
63.550
Bit 2 = Reserved, must be kept cleared.
58.254
53.773
Bit 1 = REG11 Regulator control bit
Refer to the above table.
49.932
46.603
43.691
Bit 0 = Reserved, must be kept cleared.
41.121
38.836
36.792
34.953
33.288
31.775
30.394
29.127
27.962
26.887
25.891
24.966
24.105
23.302
22.550
21.845
21.183
20.560
98/181
ST7WIND21
D[7:0]
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
Slicer time constant (ms)
19.973
19.418
18.893
18.396
17.924
17.476
17.050
16.644
16.257
15.888
15.535
15.197
14.873
14.564
14.266
13.981
13.707
13.443
13.190
12.945
12.710
12.483
12.264
12.053
11.848
11.651
11.460
11.275
11.096
10.923
10.280
9.709
D[7:0]
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
Slicer time constant (ms)
4.993
4.855
4.723
4.599
4.481
4.369
4.262
4.161
4.064
3.972
3.884
3.799
3.718
3.641
3.567
3.495
3.427
3.361
3.297
3.236
3.178
3.121
3.066
3.013
2.962
2.913
2.865
2.819
2.774
2.731
2.570
2.427
2.300
2.185
2.080
1.986
1.900
1.820
1.748
1.680
1.618
1.560
1.507
1.456
1.409
1.365
1.324
1.285
9.198
8.738
8.322
7.944
7.598
7.282
6.991
6.722
6.473
6.241
6.026
5.825
5.638
5.461
5.296
5.140
99/181
ST7WIND21
D[7:0]
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
Slicer time constant (ms)
1.248
1.214
1.181
1.150
1.120
1.092
1.066
1.040
1.016
0.993
0.971
0.950
0.929
0.910
0.892
0.874
0.857
0.840
0.824
0.809
0.794
0.780
0.767
0.753
0.740
0.728
0.716
0.705
0.694
0.683
0.643
0.607
0.575
0.546
0.520
0.496
0.475
0.455
0.437
0.420
0.404
0.390
0.377
0.364
0.352
0.341
0.331
0.321
D[7:0]
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Slicer time constant (ms)
0.312
0.303
0.295
0.287
0.280
0.273
0.266
0.260
0.254
0.248
0.243
0.237
0.232
0.228
0.223
0.218
0.214
0.210
0.206
0.202
0.199
0.195
0.192
0.188
0.185
0.182
0.179
0.176
0.173
100/181
ST7WIND21
RF COMMUNICATION (Cont’d)
Table 21. RF Common Controller Register Map and Reset Values (Page 0)
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
RFCSR
0
0
0
0
LOCK1
0
LOCK0
0
RXINV
0
RXATN
0
61h
Reset Value
0
0
0
0
Table 22. RF Common Controller Register Map and Reset Values (Page 1)
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
RFREGCR0
Reset Value
0
0
0
REG04
0
REG03
0
REG02
0
REG01
0
0
0
61h
62h
63h
0
0
0
0
0
RFREGCR1
Reset Value
0
0
0
0
0
0
REG14
0
REG13
0
REG11
0
0
0
RFSYNR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
64h
to
Reserved area (3 Bytes)
66h
RFTSWR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
67h
Reset Value
68h
to
Reserved area (3 Bytes)
6Ah
101/181
ST7WIND21
RF COMMUNICATION (Cont’d)
9.4.6.3 RF Receiver Controller
Bits 1:0 = BBF[1:0] Baseband filter bandwidth
The RF Receiver Controller provides the user with
control registers for setting parameters of the re-
ceiver block.
These bits are used to select one of the eight pos-
sible low pass filters depending on the protocol
and data rate used.
BBF1 BBF0
Baseband Filter Bandwidth (kHz)
DRR < 4.8 Kbits/s RX DRR 4.8 Kbits/s
CONTROL STATUS REGISTER (RXnCSR)
Read /Write
RX
n
n
≥
0
0
1
1
0
1
0
1
1.2 kHz
1.7 kHz
2.4 kHz
3.2 kHz
3.2 kHz
4.8 KHz
6.4 KHz
9.6 KHz
Reset value: 0000 0000 (00h)
7
0
RXD
OEN
RX
SEL
RX
EN
BB
F1
BB
F0
0
0
CF
CARRIER FREQUENCY REGISTER LOW
(RXnCFLR)
Bits 7 = RXDOEN Receiver Data Output Enable
Read/Write
Reset Value: 0000 0000 (00h)
This bit is used to enable or disable the receiver
data stream output to the timer.
0: Disabled
7
0
1: Enabled
CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
Bit 6:5 = Reserved, must be kept cleared
Bits 7:0 = CF[7:0] Carrier Frequency LSB
This register, used with the RXnCFHR register,
programs the receiver synthesizer. It contains the
LSB.
Bit 4 = RXSEL Capture Mode selection
This bit is used to select the capture mode .
0: Connect I/O Port PAx to 16-bit timer ICx func-
tion
1: Connect RXDATA internally to 16-bit timer ICx
function
CARRIER FREQUENCY REGISTER HIGH
(RXnCFHR)
Read/Write
Bit 3 = RXEN Receiver enable
This bit is used to enable and disable the receiver.
0: Disabled
Reset value: 0000 0000 (00h)
7
0
0
1: Enabled
0
0
0
CF11 CF10 CF9 CF8
Bit 2 = CF Channel filter bandwidth
This bit is used to select the channel filter band-
width.
0: Standard bandwidth (16 kHz)
1: High bandwidth (22 kHz)
Bits 7:4= Reserved, must be kept cleared
Bits 3:0= CF[11:8] Carrier Frequency MSB
This register, used with the RXnCFLR register,
programs the receiver synthesizer with a resolu-
tion of 10 kHz. It contains the MSB.
Note: The standard bandwidth channel filter
should be used for data rates lower than 4 kbits/s.
CF[11:0]
0A82h
0AA6h
..
Carrier Frequency (MHz)
26.90 MHz
27.26 MHz
..
102/181
ST7WIND21
RF COMMUNICATION (Cont’d)
FREQUENCY OFFSET LOW REGISTER
(RXnOFFLR)
RXnOFFxR registers act as a 16-bit signed regis-
ter and use 2’s complement encoding:
Read/Write
RXOFFSET
Reset value: 0000 0000 (00h)
Frequency Offset (kHz)
[9:0]
00 96h
03 6Ah
+15 kHz
-15 kHz
7
0
D7
D6
D5
D4
D3
D2
D1
D0
DATA RATE REGISTER (RXnDRR)
Read/Write
Reset value: 0000 0000 (00h)
Bits 7:0= RXOFFSET[7:0] Frequency Offset
This register, used with the RXnOFFHR register,
programs the receiver frequency offset with a res-
olution of 100 Hz. It contains the LSB.
7
0
0
0
DR
0
0
0
0
0
FREQUENCY OFFSET HIGH REGISTER
(RXnOFFHR)
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = Reserved, must be kept cleared.
7
0
0
Bit 6 = DR Data rate
This bit is used to select the receiver NRZ data
rate.
0
0
0
0
0
D9
D8
0: NRZ data rate < 4.8 kbits/s
1: NRZ data rate ≥ 4.8 kbits/s
Bits 7:2 = Reserved, must be kept cleared.
Bits 5:0 = Reserved, must be kept cleared.
Bits 1:0= RXOFFSET[9:8] Frequency Offset
This register, used with the RXnOFFLR register,
programs the receiver frequency offset with a res-
olution of 100 Hz. It contains the MSB.
Note: NRZ data rate value must be within the
1.5 K to 5 Kbits/s range.
103/181
ST7WIND21
RF COMMUNICATION (Cont’d)
RECEIVER STRENGTH LOW REGISTER
(RXnRSSLR)
RECEIVER STRENGTH HIGH REGISTER
(RXnRSSHR)
Read only
Read only
Reset value: 0000 0000 (00h)
Reset value: 0000 0000 (00h)
7
0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13 D12 D11 D10
D9
D8
Bits 7:0= RXRSS[7:0] Receiver Signal Strength
This 8-bit register is used with the RXnRSSHR
register. It contains the LSB of the receiver signal
magnitude.
Bits 7:0= RXRSS[15:8] Receiver Signal Strength
This 8-bit register is used with the RXnRSSHR
register. It contains the MSB of the receiver signal
magnitude. It provides a value indicating the input
level in the selected channel. This register is use-
ful for determining if the system is saturated during
demodulation.
Table 23. RSS register value versus input level
with attenuator disabled
Min.
(µV
3.58
4.48
5.38
Typ.
) (µV
Max.
) (µV )
RMS
Table 24. RSS register value versus input level
with attenuator enabled
RXRSS[15:0]
RMS
RMS
4.48
5.60
6.72
5.38
0005h
0006h
0007h
...
Min.
(µV
Typ.
) (µV
Max.
) (µV )
RMS
6.72
8.06
RXRSS[15:0]
RMS
RMS
4.48
8.96
5.6
6.72
0001h
0002h
0003h
...
11.2
16.8
13.44
20.16
8
10
12
000Bh
...
13.44
80
100
120
0070h
...
80
100
120
0016h
...
800
1000
1200
0460h
...
800
1000
1200
00E0h
...
6670
8000
8330
10000
12500
10000
12000
15000
2475h
2BC0h
36B0h
...
40000
48000
60000
50000
60000
75000
60000
72000
90000
2BC0h
3480h
41A0h
...
10000
42856
53952
74922
47618
59947
75469
52380
65942
83016
3CEFh
3D39h
3D4Ch
...
214789 238655 262520
270403 300448 330492
340417 378242 416066
3D35h
3D50h
3D50h
...
76210
85509
84678
93146
3D54h
3D50h
3D57h
381955 424395 466834
480852 534281 587709
539526 599474 659421
3D55h
3D4Dh
3D4Eh
95010 104511
107650 119611 131572
Caution: Due to the attenuation of the channel fil-
ter (50dB out of channel bandwidth), the RSS val-
ue gives the signal level of an unwanted signal at-
tenuated by 50dB.
104/181
ST7WIND21
RF COMMUNICATION (Cont’d)
RECEIVER SLICER LEVEL LOW REGISTER
(RXnSLLR)
Read only
Reset value: 0000 0000 (00h)
7
0
D7
D6
D5
D4
D3
D2
D1
D0
Bits 7:0= RXSL[7:0] Slicer Level LSB
This 8-bit register is used with the RXnSLHR reg-
ister. It contains the LSB of the slicer level.
RECEIVER SLICER LEVEL HIGH REGISTER
(RXnSLHR)
Read only
Reset value: 0000 0000 (00h)
7
0
D15 D14 D13 D12 D11 D10
D9
D8
Bits 7:0= RXSL[15:8] Slicer Level MSB
This 8-bit register is used with the RXnSLLR regis-
ter. It contains the MSB of the slicer level using a
resolution of 0.715Hz.
RXnSLxR registers act as a 16-bit signed register
and use 2’s complement encoding.
This register is useful to indicate the frequency er-
ror between the receiver and the transmitter, as-
suming that the transmitted signal is DC balanced.
The value read can be used to adjust RXnOFFR
register to compensate frequency errors.
105/181
ST7WIND21
RF COMMUNICATION (Cont’d)
Table 25. RF Receiver Controller Register Map and Reset Values (Page 0)
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
RX0CSR
RXDOEN
0
0
0
RXSEL
0
RXEN
0
CF
0
BBF1
0
BBF0
0
62h
63h
64h
65h
66h
67h
Reset Value
0
0
RX0RSSHR
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
Reset Value
RX0RSSLR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
RX1CSR
RXDOEN
0
0
0
0
0
RXSEL
0
RXEN
0
CF
0
BBF1
0
BBF0
0
Reset Value
RX1RSSHR
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
Reset Value
RX1RSSLR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
Table 26. RF Receiver Controller Register Map and Reset Values (RX0=Page 2, RX1=Page 3)
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
RXnCFHR
0
0
0
0
CF11
0
CF10
0
CF9
0
CF8
0
61h
62h
63h
64h
Reset Value
0
0
0
0
RXnCFLR
CF7
0
CF6
0
CF5
0
CF4
0
CF3
0
CF2
0
CF1
0
CF0
0
Reset Value
RXnOFFHR
0
0
0
0
0
0
0
0
0
0
0
0
D9
0
D8
0
Reset Value
RXnOFFLR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Reset Value
65h
to
Reserved area (2 Bytes)
66h
RXnDRR
0
0
DR
0
0
0
0
0
0
0
0
0
0
0
0
0
67h
68h
Reset Value
RXnSLHR
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
Reset Value
RXnSLLR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
69h
6Ah
Reset Value
Reserved area (1 Byte)
106/181
ST7WIND21
9.5 USB INTERFACE (USB)
9.5.1 Introduction
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http://www.usb.org.
The USB Interface implemented allows to connect
the Device to a USB host in low-speed mode. It is
a highly integrated block which includes a USB
transceiver, the Serial Interface Engine (SIE) and
the USB data buffer interface. No external compo-
nents are needed apart from the external pull-up
on USBDM for low-speed recognition by the USB
host.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens, handles data transmis-
sion/reception, and handshaking as required by
the USB standard. It also performs frame format-
ting, including CRC generation and checking.
9.5.2 Main Features
■ USB Specification Version 2.0 Compliant
■ Supports Low-Speed USB Protocol
■ Three Endpoints (including default endpoint)
Endpoints
The Endpoint registers indicate if the Device is
ready to transmit/receive, and how many bytes
need to be transmitted.
■ CRC generation/checking, NRZI encoding/
decoding and bit-stuffing
Data Transfer to/from USB Data Buffer Memory
■ USB Suspend/Resume operations
■ On-Chip USB Transceiver
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place to/from the USB data buffer. At the end of
the transaction, an interrupt is generated.
9.5.3 Functional Description
The block diagram in Figure 58, gives an overview
of the USB interface hardware.
Interrupts
By reading the Interrupt Status register, applica-
tion software can know which USB event has oc-
curred.
Figure 58. USB Block Diagram
ENDPOINT
CPU
REGISTERS
USBDM
BUFFER
Address,
Transceiver
SIE
INTERFACE
USBDP
data busses
and interrupts
USB
MEMORY
REGISTERS
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ST7WIND21
USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
All endpoints are 8 bytes in size.
There are three Endpoints including one bidirec-
tional control Endpoint (Endpoint 0), two IN or
OUT Endpoints (Endpoint 1 and 2).
Figure 59. Endpoint Buffer Size
Endpoint 0 Buffer OUT
Endpoint 0 Buffer IN
8 Bytes
8 Bytes
Endpoint 1Buffer OUT
Endpoint 1 Buffer IN
Endpoint 2 Buffer OUT
Endpoint 2 Buffer IN
8 Bytes
8 Bytes
8 Bytes
8 Bytes
108/181
ST7WIND21
USB INTERFACE (Cont’d)
9.5.4 Low Power modes
Mode
Description
No effect on USB.
WAIT
USB interrupt events cause the Device to exit from WAIT mode.
USB registers are frozen.
In halt mode, the USB is inactive. USB operations resume when the Device is woken up by an interrupt
with “exit from halt capability” or by an event on the USB line in case of suspend. This event will generate
an ESUSP interrupt which will wake-up from halt mode.
HALT
9.5.5 Interrupts
Exit
From
Halt
Enable Con- ExitFrom
Interrupt Event
Event Flag
trol Bit
Wait
Correct TRansfer
Setup OVeRrun
ERROR
CTR
SOVR
ERR
CTRM
SOVRM
ERRM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
No
No
Suspend Mode Request
End of SUSPend mode.
USB RESET
SUSP
ESUSP
RESET
SOF
SUSPM
ESUSPM
RESETM
SOFM
Start Of Frame
Note: The USB end of suspend interrupt event is
connected to a single interrupt vector (USB ES-
USP) with the exit from halt capability (wake-up).
All the other interrupt events are connected to an-
other interrupt vector: USB interrupt (USB). They
generate an interrupt if the corresponding enable
control bit is set and the interrupt mask bits (I0, I1)
in CC register are reset (RIM instruction).
109/181
ST7WIND21
USB INTERFACE (Cont’d)
9.5.6 Register Description
INTERRUPT STATUS REGISTER (USBISTR)
Read/Write
event is the SETUP token reception on the Control
Endpoint (EP0).
Bit 4 = ERR Error.
Reset Value: 0000 0000 (00h)
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
7
0
1: Timeout, CRC, bit stuffing, nonstandard
framing or buffer overrun error detected
CTR
0
SOVR ERROR SUSP ESUSP RESET SOF
These bits cannot be set by software. When an in-
terrupt occurs these bits are set by hardware. Soft-
ware must read them to determine the interrupt
type and clear them after servicing.
Note: The CTR bit (which is an OR of all the end-
point CTR flags) cannot be cleared directly, only
by clearing the CTR flags in the Endpoint regis-
ters.
Note: Refer to the ERR[2:0] bits in the USBSR
register to determine the error type.
Bit 3 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB.
The suspend request check is active immediately
after each USB reset event and is disabled by
hardware when suspend mode is forced (FSUSP
bit in the USBCTLR register) until the end of
resume sequence.
Bit 7 = CTR Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed. This bit is an OR of all
CTR flags (CTR0 in the USBEP0R register and
CTR_RX and CTR_TX in the USBEPnRXR and
USBEPnTXR registers). By looking in the USBSR
register, the type of transfer can be determined
from the PID[1:0] bits for Endpoint 0. For the other
Endpoints, the Endpoint number on which the
transfer was made is identified by the EP[2:0] bits
and the type of transfer by the IN/OUT bit.
0: No Correct Transfer detected
Bit 2 = ESUSP End Suspend mode.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
This interrupt is serviced by a specific vector, in or-
der to wake up the Device from HALT mode.
0: No End Suspend detected
1: Correct Transfer detected
1: End Suspend detected
Note: A transfer where the Device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overrun, bit
stuffing or framing errors.
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note:
The
USBDADDR,
USBEP0R,
USBEP1RXR, USBEP1TXR, USBEP2RXR and
USBEP2TXR registers are reset by a USB reset.
Bit 6 = Reserved, forced by hardware to 0.
Bit 5 = SOVR Setup Overrun.
Bit 0 = SOF Start of frame.
This bit is set by hardware when a SOF token is re-
ceived on the USB.
This bit is set by hardware when a correct Setup
transfer operation is performed while the software
is servicing an interrupt which occurred on the
same Endpoint (CTR0 bit in the USBEP0R regis-
ter is still set when SETUP correct transfer oc-
curs).
0: No SOF received
1: SOF received
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND, XOR...
0: No SETUP overrun detected
1: SETUP overrun detected
When this event occurs, the USBSR register is not
updated because the only source of the SOVR
110/181
ST7WIND21
USB INTERFACE (Cont’d)
INTERRUPT MASK REGISTER (USBIMR)
Read/Write
Bits [5:4] = Reserved.
Reset Value: 0000 0000 (00h)
Bit 3 = RESUME Resume.
7
0
This bit is set by software to wake-up the Host
when the Device is in suspend mode.
0: Resume signal not forced
SOVR
M
SUSP ESUSP RESET
CTRM
0
ERRM
SOFM
M
M
M
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
These bits are mask bits for all the interrupt condi-
tion bits included in the USBISTR register. When-
ever one of the USBIMR bits is set, if the corre-
sponding USBISTR bit is set, and the I- bit in the
CC register is cleared, an interrupt request is gen-
erated. For an explanation of each bit, please refer
to the description of the USBISTR register.
Bit 2 = PDWN Power down.
This bit is set by software to turn off the transceiv-
er.
0: Transceiver on
1: Transceiver off
Note: Do not forget to turn off the pull-up on DM
before to set the PDWN bit.
CONTROL REGISTER (USBCTLR)
Read/Write
Reset value: 0001 0110 (16h)
Bit 1 = FSUSP Force suspend mode.
This bit is set by software to enter Suspend mode.
The Device should also be put in Halt mode to re-
duce power consumption.
7
0
FSTAT FSTAT
RESU
ME
0
1
PDWN FSUSP FRES
0: Suspend mode inactive
1
0
1: Suspend mode active
Bit 7:6 = FSTAT[1:0] Forced state.
When the hardware detects USB activity, it resets
this bit (it can also be reset by software).
This bits gives the state forced on USB ports when
RESUME bit is set. Of course, the default value is
K to force a RESUME event.
Bit 0 = FRES Force reset.
Note: This is a test feature because the only legal
state which can be forced on USB port is the K
state when the Device has the wake-up capability.
This bit is set by software to force a reset of the
USB interface, just as if a RESET sequence came
from the USB.
0: Reset not forced
1: USB interface reset forced.
Table 27. Forced state encoding
FSTAT1
FSTAT0
Meaning
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
K: K state is forced on USB
ports.
0
0
J: J state is forced on USB
ports.
0
1
1
1
0
1
SE0: SE0 state forced on USB
ports.
SE1: SE1 state forced on USB
ports (not a valid USB state).
111/181
ST7WIND21
USB INTERFACE (Cont’d)
DEVICE ADDRESS REGISTER (USBDADDR)
Read/Write
correspond to the most significant bits of the PID
field of the last token PID received by Endpoint 0.
Note: The least significant PID bits have a fixed
value of 01.
Reset Value: 0000 0000 (00h)
When a CTR interrupt occurs on Endpoint 0 (see
register USBISTR) the software should read the
PID[1:0] bits to retrieve the PID name of the token
received.
7
0
0
ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
The USB specification defines PID bits as:
Bit 7 = Reserved, forced by hardware to 0.
PID1
PID0
PID Name
OUT
0
1
1
0
0
1
Bits 6:0 = ADD[6:0] Device address, 7 bits.
IN
SETUP
Software must write into this register the address
sent by the host during enumeration.
Note: This register is also reset when a USB reset
is received or forced through bit FRES in the US-
BCTLR register.
Bit 5 = IN/OUT Last transaction direction for End-
point 1or 2.
This bit is set by hardware when a CTR interrupt
occurs on Endpoint 1 or 2.
0: OUT transaction
USB STATUS REGISTER 0 (USBSR0)
Read only
1: IN transaction
Reset Value: 0000 0000 (00h)
Bits 4:3 = Reserved, forced by hardware to 0.
7
0
IN/
OUT
Bits 2:0 = EP[2:0] Endpoint number.
These bits identify the endpoint which required at-
tention.
PID1 PID0
0
0
EP2
EP1
EP0
Bits 7:6 = PID[1:0] Token PID bits 1 & 0 for End-
point 0 Control.
USB token PIDs are encoded in four bits. PID[1:0]
000 = Endpoint 0
001 = Endpoint 1
010 = Endpoint 2
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ST7WIND21
USB INTERFACE (Cont’d)
USB STATUS REGISTER 1 (USBSR1)
Read only
1: Reset sequence detected on USB
Reset Value: 0000 0000 (00h)
Bits 2:0 = ERR[2:0] Error type.
These bits identify the type of error which oc-
curred.
7
0
ERR2 ERR1 ERR0
Meaning
USB_R
ST
0
0
0
RSM
ERR2 ERR1 ERR0
0
0
0
0
0
1
0
1
0
No error
Bitstuffing error
CRC error
Bits 7:5 = Reserved, forced by hardware to 0.
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
0
1
1
0
1
0
Bit 4= RSM Resume Detected
PID error (PID encoding error,
unexpected or unknown PID)
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP event.
0: No resume sequence detected on USB
1: Resume sequence detected on USB
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
1
1
0
1
1
1
Other error (wrong packet,
timeout error)
Bit 3= USB_RST USB Reset detected.
This bit shows that a reset sequence has started
on the USB. It can be used to determine the cause
of an ESUSP event (Reset sequence).
Note: these bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (USBISTR bit 4) is cleared by
software.
0: No reset sequence detected on USB
113/181
ST7WIND21
USB INTERFACE (Cont’d)
ENDPOINT 0 REGISTER (USBEP0R)
Read/Write
These bits contain the information about the end-
point status, which are listed below
Reset value: 0000 0000(00h)
Table 28. Transmission Status Encoding
STAT_TX1 STAT_TX0
Meaning
7
0
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
STAT_ STAT_
STAT_ STAT_
DTOG
_TX
DTOG
_RX
0
0
CTR0
0
TX1
TX0
RX1
RX0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
This register is used for controlling Endpoint 0.
DTOG_xX and STAT_xX bits are also reset by a
USB reset, either received from the USB or forced
through the FRES bit in USBCTLR.
0
1
1
0
NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
Bit 7 = CTR0 Correct Transfer.
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
This bit is set by hardware when a correct transfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
1
1
These bits are written by software. Hardware sets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint; this allows software to prepare the
next set of data to be transmitted.
0: No CTR on Endpoint 0
1: Correct transfer on Endpoint 0
Bit 6 = DTOG_TX Data Toggle, for transmission
transfers.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX are normally updated by hardware, on
receipt of a relevant PID. They can be also written
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
Bit 3 = Reserved, forced by hardware to 0.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a control transfer (SETUP trans-
actions start always with DATA0 PID). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
Bits 5:4 = STAT_TX [1:0] Status bits, for transmis-
sion transfers.
114/181
ST7WIND21
USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0] Status bits, for reception
transfers.
These bits contain the information about the end-
point status, which are listed below:
This register is used for controlling Endpoint 1 or 2,
transmission. DTOG_TX and STAT_TX bits are
also reset by a USB reset, either received from the
USB or forced through the FRES bit in the US-
BCTLR register.
Table 29. Reception Status Encoding
Bits [7:4] = Reserved, forced by hardware to 0.
STAT_RX1 STAT_RX0
Meaning
DISABLED:no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
Bit 3 = CTR_TX Correct Transmission Transfer.
This bit is set by hardware when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1 or 2
1: Correct transfer in transmission on Endpoint 1
or 2
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
0
1
1
0
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
Bit 2 = DTOG_TX Data Toggle, for transmission
transfers.
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by hardware, at the receipt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
1
1
handles the transaction).
These bits are written by software. Hardware sets
the STAT_RX and STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) addressed
to this endpoint, so the software has the time to ex-
amine the received data before acknowledging a
new transaction.
Note 1:
Bits [1:0] = STAT_TX [1:0] Status bits, for trans-
mission transfers.
These bits contain the information about the end-
point status, which is listed below
If a SETUP transaction is received while the status
is different from DISABLED, it is acknowledged
and the two directional status bits are set to NAK
by hardware.
Table 30. Transmission Status Encoding
Note 2:
STAT_TX1 STAT_TX0
Meaning
When a STALL is answered by the USB device,
the two directional status bits are set to STALL by
hardware.
DISABLED: transmission
transfers cannot be executed.
0
0
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
0
1
ENDPOINT
TRANSMISSION
REGISTER
(USBEP1TXR, USBEP2TXR)
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
Read/Write
1
1
0
1
Reset value: 0000 0000 (00h)
VALID: this endpoint is ena-
bled for transmission.
7
0
STAT_ STAT_
CTR_T DTOG
_TX
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
0
0
0
0
X
TX1
TX0
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ST7WIND21
USB INTERFACE (Cont’d)
ENDPOINT
RECEPTION
REGISTER
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint, so the software has the time to examine
the received data before acknowledging a new
transaction.
(USBEP1RXR, USBEP2RXR)
Read/Write
Reset value: 0000 0000 (00h)
7
0
STAT_ STAT_
CTR_R DTOG
_RX
0
0
0
0
X
RX1
RX0
RECEPTION COUNTER REGISTER (USBCNTn-
RXR)
This register is used for controlling Endpoint 1 and
2 reception. DTOG_RX and STAT_RX bits are
also reset by a USB reset, either received from the
USB or forced through the FRES bit in the US-
BCTLR register.
Read/Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
CNT3 CNT2 CNT1 CNT0
Bits [7:4] = Reserved, forced by hardware to 0.
This register contains the allocated buffer size for
endpoint n reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT (or SETUP for Endpoint 0)
transaction. At the end of a reception, the value of
this register is the max size decremented by the
number of bytes received (to determine the
number of bytes received, the software must sub-
tract the content of this register from the allocated
buffer size).
Bit 3 = CTR_RX Reception Correct Transfer.
This bit is set by hardware when a correct transfer
operation is performed in reception. This bit must
be cleared after that the corresponding interrupt
has been serviced.
Bit 2 = DTOG_RX Data Toggle, for reception
transfers.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
TRANSMISSION COUNTER REGISTER
(USBCNTnTXR)
The receiver toggles DTOG_RX only if it receives
a correct data packet and the packet’s data PID
matches the receiver sequence bit.
Read/Write
Reset Value 0000 0000 (00h)
Bits [1:0] = STAT_RX [1:0] Status bits, for recep-
tion transfers.
7
0
These bits contain the information about the end-
point status, which is listed below:
0
0
0
0
CNT3 CNT2 CNT1 CNT0
Table 31. Reception Status Encoding
This register contains the number of bytes to be
transmitted by Endpoint n at the next IN token ad-
dressed to it.
STAT_RX1 STAT_RX0
Meaning
DISABLED: reception trans-
fers cannot be executed.
0
0
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
0
1
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
1
1
0
1
VALID: this endpoint is ena-
bled for reception.
116/181
ST7WIND21
Table 32. USB Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
USBISTR
Reset Value
CTR
0
0
0
SOVR
0
ERR
0
SUSP
0
ESUSP
0
RESET
0
SOF
0
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
USBIMR
Reset Value
CTRM
0
0
0
SOVRM
0
ERRM
0
SUSPM
0
ESUSPM
0
RESETM
0
SOFM
0
USBCTLR
Reset Value
FSTAT1
0
FSTAT0
0
RESUME
0
PDWN
1
FSUSP
1
FRES
0
0
1
USBDADDR
Reset Value
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
0
USBSR0
Reset Value
PID1
0
PID0
0
IN /OUT
0
EP2
0
EP1
0
EP0
0
0
0
USBSR1
Reset Value
RSM
0
USB_RST
0
ERR2
0
ERR1
0
ERR0
0
0
0
0
USBEP0R
Reset Value
CTR0
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USBCNT0RXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
0
0
0
0
0
0
0
0
0
0
USBCNT0TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
USBEP1RXR
Reset Value
CTR_RX
0
DTOG_RX STAT_RX1
STATRX0
0
0
0
USBCNT1RXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
USBEP1TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
USBCNT1TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
USBEP2RXR
Reset Value
CTR_RX
0
DTOG_RX STAT_RX1 STAT_RX0
0
0
0
USBCNT2RXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
USBP2TXR
Reset Value
CTR_TX
0
DTOG_TX STAT_TX1 STAT_TX0
0
0
0
USBCNT2TXR
Reset Value
CNT3
0
CNT2
0
CNT1
0
CNT0
0
117/181
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9.6 PS/2 INTERFACE
9.6.1 Introduction
9.6.2 Main Features
■ Based on the IBM PS/2 specification
■ Inter-Frame timing management
■ Interrupt capability (4 interrupt sources)
The PS/2 Interface allows communication be-
tween the Device and a PC using the PS/2 proto-
col.
The protocol used is based on the IBM specifica-
tion.
– Communication complete
– Communication aborted
– Host request to send
– Reception error
■ 3 Registers
– Control register
– Status register
– Data register (for transmission and reception)
Figure 60. PS/2 Interface Block Diagram
INTERNAL BUS
PS2DATA
SHR
PS2CSR
Registers
PS2CR
FSM
S
S
RTX
PS2CLOCK
Sampling
TIMER
Engine
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PS/2 INTERFACE (Cont’d)
9.6.3 Protocol Description and Timings
Timings
The PS/2 Interface is designed to handle the basic
PS/2 protocol.
The clock period is fixed at 80µs. Before its activa-
tion, the PS/2 Interface must be configured
through the PS/2 Config/Status register (PS2CSR)
to select the right ratio between the CPU frequen-
cy and the PS/2 Interface.
Protocol
The communication is performed using two lines:
- PS2CLOCK
- PS2DATA
Host to Device
At the beginning of a Host to Device communica-
tion, the PS/2 Interface generates a fixed 100µs
timeout duration between the release of the clock
by the host and the generation of the first negative
edge on the clock by the PS/2 Interface.
The clock is always generated by the PS/2 Inter-
face (Device). The PC (Host) can only force it to
zero in order to cancel the communication and/or
inhibit the bus.
The data line is bidirectional, depending on the
communication direction. A data frame is always
composed of a start bit, 8 bits of data, a parity bit
(odd parity) and a stop bit.
During the communication, the PS/2 Interface
samples both clock and data lines three times at
2.5µs intervals. The acquired value is determined
by these three samples.
In host to Device communication, the host controls
the data line. The Device can force the data line
to zero to send an acknowledge after reception of
a stop bit.
A minimum delay is generated between an event
(clock or data transition) and the first sampling.
This is done in order to avoid corrupted sampling
due to the line set-up time. This delay lasts from
12.5 to 17.5µs.
In Device to host communication, the PS/2 Inter-
face controls the data line. If the host forces it to
zero, it generates a Host Request To Send
(HRTS).
All the timings related to Host to Device communi-
cation are detailed in the Figure 61.
Figure 61. PS/2 Interface Timing: Host to Device communication
HOST TO DEVICE START SEQUENCE
17.5µs
17.5µs
DATA
CLOCK
DATA
SAMPLING
START BIT
BIT 1
BIT 0
80µs
80µs
100µs
INHIBIT
TIMEOUT_RX
RX
PS/2
HOST TO DEVICE STOP SEQUENCE
17.5
17.5
µs
µs
12.5µs
15µs
CLOCK
DATA
BIT 7
PARITY
STOP
ACK
80
ACK
µ
s
PS/2
RX
STOP
IDLE
sampling
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ST7WIND21
PS/2 INTERFACE (Cont’d)
Device to Host
due to the line set-up time. This delay lasts from
15µs to 17.5µs.
During a Device to Host communication, the PS/2
Interface samples both clock and data lines three
times at 2.5µs intervals. This is shown in Figure
62.
A minimum delay is generated between an event
(clock or data transition) and the first sampling.
This is done in order to avoid corrupted sampling
Parity Calculation
The parity is calculated with an odd algorithm,
meaning that the sum of the 8 data bits and the
parity bit is odd.
Figure 62. PS/2 Interface Timing: Device to Host communication
DEVICE TO HOST START SEQUENCE
17.5µ
s
17.5µ
s
17.5µs
CLOCK
DATA
START BIT
80
BIT 0
BIT 1
BIT 2
80µ
s
80µs
µ
s
PS/2
IDLE
TX
DEVICE TO HOST STOP SEQUENCE
17.5
17.5µ
s
µs
17.5µ
s
17.5µs
CLOCK
DATA
BIT 7
PARITY
BIT 6
STOP
80
µs
80µ
s
80µs
PS/2
TX
IDLE
DEVICE TO HOST ABORT SEQUENCE
15
15µs
µ
s
CLOCK
DATA
PS/2
IDLE_RX
TX
Host forces CK to 0
TX
INHIBIT
Host forces DATA to 0
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PS/2 INTERFACE (Cont’d)
9.6.4 Functional Description
– a transmission start command from the Device
– an inhibit
– an HRTS.
The basic PS/2 protocol is handled by the Device
PS/2 Interface. Figure 63 illustrates the logic that
is described below, following the Device from state
to state.
After timeout, the PS/2 Interface will go into idle
mode also.
Configuration
The Device can not force the PS/2 Interface into
receive mode when no HRTS has been transmit-
ted.
Before it is turned on, the PS/2 Interface must be
configured through bits in the PS2CSR register
and the PAGPUCR register (see Section 8). This
step defines the pull-up activation, the operating
Transmission mode
frequency (linked to f
ment.
) and the timing manage-
CPU
When the Device wants to send a byte to the host,
it puts the PS/2 Interface into transmit mode by
clearing the CD bit in the PS2CR register and writ-
ing the data in the PS2DR register.
This configuration can not be modified once the
PS/2 Interface is turned on, i.e once the PS2ON bit
in the PS/2 Control Register (PS2CR) is set.
As soon as the data is written and Timeout TX has
expired (if timing management is enabled), the
transmission starts and the RTXS bit in the
PS2CR register is set by hardware. If timing man-
agement is not enabled, timing must be handled
by software.
Note: the PS/2 pull-ups must not be disabled while
the PS/2 peripheral is on.
Timing management
If Timing Management is enabled i.e if the TOFF
bit in the PS2CSR register is cleared, the PS/2 In-
terface can handle 3 different timeouts.
At the end of the transmission, the RTXS bit in the
PS2CR register is cleared, and the RTXC flag in
the PS2CSR register is set, both by hardware. A
Transmission Complete interrupt will be generated
if the RTXCIE bit in the PS2CR register is set.
– Timeout TX which represents a 100µs inter-
frame timing: no transmission will start before the
end of this timeout.
– Timeout TX Inhibit which represents a 100µsec
time between an inhibit and the start of a trans-
mission.
A transmission can be aborted either by the user
or by the host. To abort a transmission, the user
can clear the RTXS bit in the PS2CR register. The
host can also abort it by generating either an inhib-
it (ck at 0) or an HRTS (data at 0).
– Timeout RX which represents the 100µs Device
response time to a Host Request To Send
(HRTS): no reception will start before the end of
this timeout.
In each case, the RTXS bit in the PS2CR register
is cleared and an abort flag is set by hardware
(RTXA bit in the PS2CSR register). An Abort inter-
rupt will be generated if the RTXAIE bit in the
PS2CR register is set.
It is recommended to always use the timing man-
agement function provided. This saves the user
from the necessity of using software to manage
the timing.
When the abort comes from an HRTS, the HRTS
flag is set and an interrupt will be generated if the
HRTS Interrupt Enable in the PS2CR is set.
Idle mode
After the PS/2 Interface is configured, it can be en-
abled by setting the PS2ON bit in the PS2CR reg-
ister. Once on, its state goes from init to idle. In
Idle the cell is waiting either for:
No error can occur in transmission mode. A line er-
ror on the clock line will be interpreted as an inhib-
it. A line error on the data line will be interpreted as
an HRTS.
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PS/2 INTERFACE (Cont’d)
Reception mode
generated. An acknowledge is automatically sent
to the host.
As soon as the PS/2 Interface receives an HRTS,
which may or may not be preceded by an inhibit,
the state goes into idle_rx mode after the Timeout
RX delay, if timing management is enabled. The
state change is immediate if timing management is
not enabled, unless otherwise managed by soft-
ware.
The reception can be aborted only by the host by
generating either an inhibit or a Host Request To
Send (HRTS).
If reception is aborted, the RTXS bit in the PS2CR
register is cleared by hardware and the abort flag
is set (the RTXA bit in the PS2CSR register). If the
Abort Interrupt is enabled, an interrupt is generat-
ed (the RTXAIE bit in the PS2CR register).
To start reception, the user must first switch the
PS/2 Interface to reception mode by setting the
CD bit in the PS2CR register. Then, the RTXS bit
in the PS2CR register must be set.
When reception is aborted due to an HRTS flag, in
order to receive data from the host, the HRTS In-
terrupt in the PS2CR register must be set. After
the interrupt, and Timeout RX delay, if timing man-
agement is enabled, reception from the host oc-
curs. If timing management is not used, reception
configuration and start up must be managed by
software.
At the end of reception, the RTXS bit in the PS2CR
register is cleared by hardware, signalling that re-
ception is over. RTXC flag in the PS2CSR register
is also set meaning that reception is complete. If
the Reception Complete Interrupt is enabled (the
RTXCIE bit in the PS2CR register), an interrupt is
Figure 63. PS/2 Interface State Diagram
timeout_tx
data=0
ck=1
timeout
timeout_tx_inhibit
cell on
init
ck=0
ck=1
data=1
ck=0
complete_rtx
inhibit
idle
ck=1
data=0
data=0
tx
data=0
hrts
or ck=0
ck=0 or data=1
abort_rtx
timeout_rx
ck=0
timeout
ck=0
rx
or data=1
idle_rx
stop error
stop_rx
ck=0
stop_error
ack_tx
parity error
parity_error
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PS/2 INTERFACE (Cont’d)
9.6.5 Error Management
– A data line stuck at 0 is interpreted as a Host Re-
quest To Send (HRTS) thus, it will abort the cur-
rent transmission and activate both Bit 1 and Bit
2 in the PS2CSR.
The PS/2 Interface can generate 2 types of error
during reception: parity error and stop bit error.
9.6.5.1 Parity Error
Lines stuck at 1 are ignored.
Parity error occurs when the parity of the host
frame is wrong.
In case of error or abort, the data in the PS2DR
register is lost, and the register returns to its reset
state (00h).
In case of parity error, the RXE bit in the PS2CSR
register is set. At the same time the RTXS is
cleared and RTXC is set, indicating the end of re-
ception.
9.6.6 Low Power Modes
Mode
Description
No effect on PS/2.
If the error interrupt is enabled, the RXEIE in the
PS2CR register, an interrupt is generated.
WAIT
PS/2 interrupt events cause the Device to
exit from WAIT mode.
An acknowledge is sent to the host after reception
of the stop bit.
PS/2 registers are frozen.
In HALT mode, the PS/2 is inactive. PS/2 op-
eration resumes when the Device is woken
up by an interrupt with “exit from HALT
mode” capability.
HALT
9.6.5.2 Stop bit Error
Stop bit error occurs if the stop bit Is missing in the
host frame. The PS/2 Interface continues to output
the clock until a stop bit is received.
9.6.7 Interrupts
At the first missing stop bit, the RXE flag in the
PS2CSR register is set, even if an end of reception
has not been received. Then, the RTXC flag in the
PS2CSR register is set.
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Interrupt
Event
Event
Flag
RTXC
RTXA
HRTS
RXE
An interrupt is generated if the RXEIE in the
PS2CR register is set.
RTX
RTXCIE
RTXAIE
HRTSIE
RXEIE
Complete
The end of the reception is still managed as previ-
ously described. The RTXS will be cleared by
hardware.
RTX
Aborted
Yes
No
Host Request
To Send
An acknowledge is sent to the host after the recep-
tion of the stop bit.
RX
Error
Note:
During transmission, no error can occur as:
– A clock line stuck at 0 is interpreted as an abort.
Note: All the interrupts are connected to the same
interrupt line.
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PS/2 INTERFACE (Cont’d)
9.6.8 Register Description
Bit 3 = RTXCIE RX/TX Complete Interrupt Enable.
This bit is set and cleared by software.
0: RX/TX Complete interrupt disabled
1: RX/TX Complete interrupt enabled
PS/2 CONTROL REGISTER (PS2CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 2 = RTXS RX/TX Start.
This bit is set by hardware by writing a value in the
PS2DR register in transmit mode, and set by soft-
ware after a Host Request To Send in receive
mode.
7
0
HRT- RTXAI RTX-
PS2O
N
-
RXEIE
RTXS
CD
SIE
E
CIE
This bit is cleared by software to abort a transmis-
sion. It is cleared by hardware when communica-
tion is over.
It is not possible to abort a reception.
0: RX/TX over / Abort TX
1: Start RX/TX
Bit 7 = Reserved, must be kept cleared.
Bit 6 = RXEIE RX Error Interrupt Enable.
This bit is set and cleared by software.
0: RX Error interrupt disabled
1: RX Error interrupt enabled
Bit 1 = CD Communication Direction.
Bit 5 = HRTSIE HRTS Interrupt Enable.
This bit is set and cleared by software.
0: HRTS interrupt disabled
This bit is set and cleared by software. It can only
be set when no communication is active (RTXS bit
is cleared).
0: TX
1: RX.
1: HRTS interrupt enabled
Bit 4 = RTXAIE RX/TX Abort Interrupt Enable.
This bit is set and cleared by software.
0: RX/TX Abort interrupt disabled
Bit 0 = PS2ON PS/2 ON
This bit is set and cleared by software.
0: PS/2 Interface is OFF
1: RX/TX Abort interrupt enabled
1: PS/2 Interface is ON
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PS/2 INTERFACE (Cont’d)
PS/2 CONFIG/STATUS REGISTER (PS2CSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 1 = RTXA RX/TX Abort.
This bit is set by hardware and cleared by software
(by writing 1).
If the RTXAIE bit in the PS2CR Register is set, an
interrupt is generated.
7
0
0
0: No abort
1: RX or TX aborted
FSEL1 FSEL0 TOFF RXE HRTS RTXA RTXC
Bit 0 = RTXC RX/TX Complete.
This bit is set by hardware and cleared by software
(by writing 1).
If the RTXCIE bit in the PS2CR Register is set, an
interrupt is generated.
0: No communication / Communication ongoing
1: RX or TX complete
Bit 7 = Reserved, must be kept cleared.
Bit 6:5 = FSEL[1:0] Frequency Selection
This bit is set and cleared by software when the
PS/2 Interface is OFF.
It selects the division ratio according to the internal
frequency f
.
CPU
Note: In case of abort, the RTXC bit is not set.
00: 12 MHz
01: 8 MHz
10: 6 MHz
11: 4 MHz
PS/2 DATA REGISTER (PS2DR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 4 = TOFF Timing OFF
This bit is set and cleared by software when the
PS/2 Interface is OFF.
7
0
0: Timing management enabled
1: Timing management disabled
D7
D6
D5
D4
D3
D2
D1
D0
Bit 3 = RXE RX Error.
Bit 7:0 = PS2D[7:0] PS/2 Data.
This bit is set by hardware and cleared by software
(by writing 1).
These bits are written by software when no com-
munication is in progress i.e the RTXS bit in the
PS2CR register is cleared and the interface is con-
figured in transmit mode, i.e the CD bit is set.
Writing a value in this register will automatically set
the RTXS bit and start transmission.
If the RXEIE bit in the PS2CR register is set, an in-
terrupt is generated.
0: No Error
1: Reception Error
These bits are written by hardware during recep-
tion.
They can be read only when no communication is
in progress i.e the RTXS bit in the PS2CR register
is cleared.
Bit 2 = HRTS Host Request To Send.
This bit is set by hardware and cleared by software
(by writing 1).
If the HRTSIE bit in the PS2CR register is set, an
interrupt is generated.
0: No request
1: Host request to send
Note: During communication, these bits return the
value 00h when read.
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PS/2 INTERFACE (Cont’d)
Table 33. PS/2 Register Map and Reset Values
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
PS2CnR
Reset Value
PS/2 0: 4Eh
PS/2 1: 51h
0
0
RXEIE
0
HRTSIE
0
RTXAIE RTXCIE
RTXS
0
CD
0
PS2ON
0
0
PS2CSnR
Reset Value
PS/2 0: 4Fh
PS/2 1: 52h
0
0
FSEL1
0
FSEL0
0
TOFF
0
RXE
0
HRTS
0
RTXA
0
RTXC
0
PS2DnR
Reset Value
PS/2 0: 50h
PS/2 1: 53h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
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9.7 SERIAL PERIPHERAL INTERFACE (SPI)
9.7.1 Introduction
9.7.3 General Description
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
Figure 64 shows the serial peripheral interface
(SPI) block diagram. There are 3 registers:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
9.7.2 Main Features
■ Full duplex synchronous transfers (on 3 lines)
■ Simplex synchronous transfers (on 2 lines)
■ Master or slave operation
The SPI is connected to external devices through
4 pins:
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
■ Six master mode frequencies (f
/4 max.)
CPU
■ f
/2 max. slave mode frequency (see note)
CPU
– SCK: Serial Clock out by SPI masters and in-
put by SPI slaves
■ SS Management by software or hardware
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
– SS: Slave select:
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
■ Write collision, Master Mode Fault and Overrun
flags
Note: In slave mode, continuous transmission is
not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 64. Serial Peripheral Interface Block Diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
7
0
SPICSR
MISO
8-Bit Shift Register
SPIF WCOL OVR MODF
0
SOD SSM SSI
Write
SOD
bit
1
SS
SPI
STATE
0
SCK
CONTROL
7
0
SPICR
MSTR
SPR0
SPIE SPE SPR2
CPOL CPHA SPR1
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.3.1 Functional Description
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 65.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 68) but master and slave
must be programmed with the same timing mode.
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 65. Single Master/ Single Slave Application
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
Not used if SS is managed
by software
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SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.3.2 Slave Select Management
In Slave Mode:
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 67)
There are two cases depending on the data/clock
timing relationship (see Figure 66):
If CPHA=1 (data latched on 2nd clock edge):
– SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
V
, or made free for standard I/O by manag-
SS
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
In Master mode:
– SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 9.7.5.3).
– SS internal must be held high continuously
Figure 66. Generic SS Timing Diagram
Byte 3
Byte 2
MOSI/MISO
Master SS
Byte 1
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Figure 67. Hardware/Software Slave Select Management
SSM bit
SSI bit
1
0
SS internal
SS external pin
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SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.3.3 Master Mode Operation
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
In master mode, the serial clock is output on the
SCK pin. The clock frequency, polarity and phase
are configured by software (refer to the description
of the SPICSR register).
9.7.3.5 Slave Mode Operation
In slave mode, the serial clock is received on the
SCK pin from the master device.
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the fol-
lowing actions:
To operate the SPI in master mode, perform the
following steps in order (if the SPICSR register is
not written first, the SPICR register setting (MSTR
bit ) may be not taken into account):
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits (see
Figure 68).
Note: The slave must have the same CPOL
and CPHA settings as the master.
1. Write to the SPICR register:
– Manage the SS pin as described in Section
9.7.3.2 and Figure 66. If CPHA=1 SS must be
held low continuously. If CPHA=0 SS must be
held low during byte transmission and pulled
up between each byte to let the slave write in
the shift register.
– Select the clock frequency by configuring the
SPR[2:0] bits.
– Select the clock polarity and clock phase by
configuring the CPOL and CPHA bits. Figure
68 shows the four possible configurations.
Note: The slave must have the same CPOL
and CPHA settings as the master.
2. Write to the SPICR register to clear the MSTR
bit and set the SPE bit to enable the SPI I/O
functions.
2. Write to the SPICSR register:
– Either set the SSM bit and set the SSI bit or
clear the SSM bit and tie the SS pin high for
the complete byte transmit sequence.
9.7.3.6 Slave Mode Transmit Sequence
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MISO pin most sig-
nificant bit first.
3. Write to the SPICR register:
– Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if
SS is high).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
The transmit sequence begins when software
writes a byte in the SPIDR register.
9.7.3.4 Master Mode Transmit Sequence
When data transfer is complete:
– The SPIF bit is set by hardware
When software writes to the SPIDR register, the
data byte is loaded into the 8-bit shift register and
then shifted out serially to the MOSI pin most sig-
nificant bit first.
– An interrupt request is generated if SPIE bit is
set and interrupt mask in the CCR register is
cleared.
When data transfer is complete:
– The SPIF bit is set by hardware
Clearing the SPIF bit is performed by the following
software sequence:
– An interrupt request is generated if the SPIE
bit is set and the interrupt mask in the CCR
register is cleared.
1. An access to the SPICSR register while the
SPIF bit is set.
2. A write or a read to the SPIDR register.
Clearing the SPIF bit is performed by the following
software sequence:
Notes: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
1. An access to the SPICSR register while the
SPIF bit is set
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an Overrun
condition (see Section 9.7.5.2).
2. A read to the SPIDR register.
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ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.4 Clock Phase and Clock Polarity
Figure 68, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 68).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 68. Data Clock Timing Diagram
CPHA =1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
CPHA =0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
Bit 4
Bit 4
Bit3
Bit 2
Bit 2
Bit 1
Bit 1
LSBit
LSBit
MISO
(from master)
MSBit Bit 6
MSBit Bit 6
Bit 5
Bit 5
Bit3
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
132/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.5 Error Flags
9.7.5.2 Overrun Condition (OVR)
9.7.5.1 Master Mode Fault (MODF)
An overrun condition occurs, when the master de-
vice has sent a data byte and the slave device has
not cleared the SPIF bit issued from the previously
transmitted byte.
Master mode fault occurs when the master device
has its SS pin pulled low.
When a Master mode fault occurs:
When an Overrun occurs:
– The MODF bit is set and an SPI interrupt re-
quest is generated if the SPIE bit is set.
– The OVR bit is set and an interrupt request is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output
from the Device and disables the SPI periph-
eral.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the SPIDR register returns this byte. All other
bytes are lost.
– The MSTR bit is reset, thus forcing the Device
into slave mode.
The OVR bit is cleared by reading the SPICSR
register.
Clearing the MODF bit is done through a software
sequence:
9.7.5.3 Write Collision Error (WCOL)
1. A read access to the SPICSR register while the
MODF bit is set.
A write collision occurs when the software tries to
write to the SPIDR register while a data transfer is
taking place with an external device. When this
happens, the transfer continues uninterrupted;
and the software write will be unsuccessful.
2. A write to the SPICR register.
Notes: To avoid any conflicts in an application
with multiple slaves, the SS pin must be pulled
high during the MODF bit clearing sequence. The
SPE and MSTR bits may be restored to their orig-
inal state during or after this clearing sequence.
Write collisions can occur both in master and slave
mode. See also Section 9.7.3.2 "Slave Select
Management" on page 130.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the CPU oper-
ation.
In a slave device, the MODF bit can not be set, but
in a multi master configuration the Device can be in
slave mode with the MODF bit set.
The WCOL bit in the SPICSR register is set if a
write collision occurs.
The MODF bit indicates that there might have
been a multi-master conflict and allows software to
handle this using an interrupt routine and either
perform to a reset or return to an application de-
fault state.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 69).
Figure 69. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Read SPICSR
1st Step
RESULT
SPIF =0
WCOL=0
2nd Step
Read SPIDR
Clearing sequence before SPIF = 1 (during a data byte transfer)
Read SPICSR
1st Step
Note: Writing to the SPIDR regis-
ter instead of reading it does not
reset the WCOL bit
RESULT
2nd Step
Read SPIDR
WCOL=0
133/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.5.4 Single Master and Multimaster
Configurations
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
There are two types of SPI systems:
– Single Master System
– Multimaster System
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Single Master System
A typical single master system may be configured,
using a device as the master and four devices as
slaves (see Figure 70).
Multi-Master System
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
Figure 70. Single Master / Multiple Slave Configuration
SS
SS
SS
SS
SCK
SCK
Slave
SCK
Slave
SCK
Slave
Slave
Device
Device
Device
Device
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
134/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.6 Low Power Modes
SS pin or the SSI bit in the SPICSR register) is low
when the Device enters Halt mode. So if Slave se-
lection is configured as external (see Section
9.7.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
Mode
Description
No effect on SPI.
WAIT
SPI interrupt events cause the Device to exit
from WAIT mode.
9.7.7 Interrupts
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the Device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Enable
Control from
Bit
Exit
Exit
from
Halt
Event
Flag
Interrupt Event
Wait
SPI End of Trans-
fer Event
HALT
SPIF
Yes
Yes
Master Mode
Fault Event
SPIE
MODF
OVR
Yes
Yes
No
No
Overrun Error
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
9.7.6.1 Using the SPI to wake-up the Device
from Halt mode
In slave configuration, the SPI is able to wake-up
the Device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake-up the Device from
Halt mode only if the Slave Select signal (external
135/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
9.7.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Bit 3 = CPOL Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
Reset Value: 0000 xxxx (0xh)
7
0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF=1, MODF=1 or OVR=1
in the SPICSR register)
Bit 2 = CPHA Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 9.7.5.1 "Master Mode Fault (MODF)"
on page 133). The SPE bit is cleared by reset, so
the SPI peripheral is not initially connected to the
external pins.
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Note: These 2 bits have no effect in slave mode.
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 34.
0: Divider by 2 enabled
Table 34. SPI Master mode SCK Frequency
Serial Clock
SPR2 SPR1 SPR0
f
f
/4
/8
1
0
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
CPU
CPU
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
f
f
f
/16
/32
/64
CPU
CPU
CPU
Bit 4 = MSTR Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 9.7.5.1 "Master Mode Fault (MODF)"
on page 133).
f
/128
CPU
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
136/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
7
0
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
SPIF
WCOL OVR MODF
-
SOD SSM SSI
1: SPI output disabled
Bit 7 = SPIF Serial Peripheral Data Transfer Flag
(Read only).
Bit 1 = SSM SS Management.
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the SPICR register. It is cleared by a
software sequence (an access to the SPICSR
register followed by a write or a read to the
SPIDR register).
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI SS pin
and uses the SSI bit value instead. See Section
9.7.3.2 "Slave Select Management" on page 130.
0: Hardware management (SS managed by exter-
nal pin)
0: Data transfer is in progress or the flag has been
cleared.
1: Data transfer between the Device and an exter-
nal device has been completed.
1: Software management (internal SS signal con-
trolled by SSI bit. External SS pin free for gener-
al-purpose I/O)
Note: While the SPIF bit is set, all writes to the
SPIDR register are inhibited until the SPICSR reg-
ister is read.
Bit 0 = SSI SS Internal Mode.
This bit is set and cleared by software. It acts as a
‘chip select’ by controlling the level of the SS slave
select signal when the SSM bit is set.
0 : Slave selected
Bit 6 = WCOL Write Collision status (Read only).
This bit is set by hardware when a write to the
SPIDR register is done during a transmit se-
quence. It is cleared by a software sequence (see
Figure 69).
0: No write collision occurred
1: A write collision has been detected
1 : Slave deselected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
7
0
Bit 5 = OVR SPI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 9.7.5.2). An interrupt is generated if
SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
D7
D6
D5
D4
D3
D2
D1
D0
The SPIDR register is used to transmit and receive
data on the serial bus. In a master device, a write
to this register will initiate transmission/reception
of another byte.
1: Overrun error detected
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Bit 4 = MODF Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 9.7.5.1
"Master Mode Fault (MODF)" on page 133). An
SPI interrupt can be generated if SPIE=1 in the
SPICR register. This bit is cleared by a software
sequence (An access to the SPICSR register
while MODF=1 followed by a write to the SPICR
register).
While the SPIF bit is set, all writes to the SPIDR
register are inhibited until the SPICSR register is
read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 64).
0: No master mode fault detected
1: A fault in master mode has been detected
137/181
ST7WIND21
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 35. SPI Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
SPIDR
Reset Value
MSB
x
LSB
x
0017h
0018h
0019h
x
x
x
x
x
x
SPICR
Reset Value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
SPICSR
Reset Value
SPIF
0
WCOL
0
OVR
0
MODF
0
SOD
0
SSM
0
SSI
0
0
138/181
ST7WIND21
10 INSTRUCTION SET
10.1 CPU ADDRESSING MODES
so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:
The CPU features 17 different addressing modes
which can be classified in 7 main groups:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.
Addressing Mode
Inherent
Example
nop
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Immediate
Direct
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
Indexed
Indirect
Relative
Bit operation
bset byte,#5
The ST7 Assembler optimizes the use of long and
short addressing modes.
The CPU Instruction set is designed to minimize
the number of bytes required per instruction: To do
Table 36. CPU Addressing Mode Overview
Pointer
Address
(Hex.)
Pointer Size
(Hex.)
Length
(Bytes)
Mode
Syntax
Destination
Inherent
Immediate
Short
Long
nop
+ 0
ld A,#$55
+ 1
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 2
+ 1
+ 2
+ 2
+ 3
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
ld A,$10
00..FF
ld A,$1000
ld A,(X)
0000..FFFF
00..FF
No Offset
Short
Long
Indexed
Indexed
Indexed
ld A,($10,X)
ld A,($1000,X)
ld A,[$10]
00..1FE
0000..FFFF
00..FF
Short
Long
00..FF
byte
word
byte
word
ld A,[$10.w]
ld A,([$10],X)
ld A,([$10.w],X)
jrne loop
0000..FFFF 00..FF
00..1FE 00..FF
Short
Long
Indirect Indexed
Indirect Indexed
Direct
0000..FFFF 00..FF
PC+/-127
Relative
Relative
Bit
Indirect
jrne [$10]
PC+/-127
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
byte
byte
byte
Direct
bset $10,#7
bset [$10],#7
Bit
Indirect
Bit
Direct
Relative btjt $10,#7,skip
Bit
Indirect Relative btjt [$10],#7,skip
139/181
ST7WIND21
INSTRUCTION SET OVERVIEW (Cont’d)
10.1.1 Inherent
10.1.3 Direct
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.
In Direct instructions, the operands are referenced
by their memory address.
The direct addressing mode consists of two sub-
modes:
Inherent Instruction
Function
No operation
Direct (short)
NOP
The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.
TRAP
S/W Interrupt
Wait For Interrupt (Low Pow-
er Mode)
WFI
Direct (long)
Halt Oscillator (Lowest Power
Mode)
HALT
The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
RET
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask (level 3)
Reset Interrupt Mask (level 0)
Set Carry Flag
IRET
SIM
10.1.4 Indexed (No Offset, Short, Long)
RIM
In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.
SCF
RCF
Reset Carry Flag
RSP
Reset Stack Pointer
Load
The indirect addressing mode consists of three
sub-modes:
LD
CLR
Clear
Indexed (No Offset)
PUSH/POP
INC/DEC
TNZ
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (Short)
CPL, NEG
MUL
The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
Swap Nibbles
Indexed (long)
SWAP
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.
10.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
10.1.5 Indirect (Short, Long)
The required data byte to do the operation is found
by its memory address, located in memory (point-
er).
Immediate Instruction
Function
LD
Load
The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:
CP
Compare
BCP
Bit Compare
Indirect (short)
AND, OR, XOR
ADC, ADD, SUB, SBC
Logical Operations
Arithmetic Operations
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
140/181
ST7WIND21
INSTRUCTION SET OVERVIEW (Cont’d)
10.1.6 Indirect Indexed (Short, Long)
10.1.7 Relative mode (Direct, Indirect)
This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
Available Relative
Direct/Indirect
Instructions
Function
The indirect indexed addressing mode consists of
two sub-modes:
JRxx
CALLR
Conditional Jump
Call Relative
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.
The relative addressing mode consists of two sub-
modes:
Relative (Direct)
Indirect Indexed (Long)
The offset is following the opcode.
Relative (Indirect)
The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
The offset is defined in memory, which address
follows the opcode.
Table 37. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Function
Instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
Arithmetic Additions/Sub-
stractions operations
ADC, ADD, SUB, SBC
BCP
Bit Compare
Short Instructions
Only
Function
CLR
Clear
INC, DEC
TNZ
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
CPL, NEG
BSET, BRES
Bit Test and Jump Opera-
tions
BTJT, BTJF
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Opera-
tions
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
141/181
ST7WIND21
INSTRUCTION SET OVERVIEW (Cont’d)
10.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Load and Transfer
LD
CLR
POP
DEC
TNZ
OR
Stack operation
PUSH
INC
RSP
BCP
Increment/Decrement
Compare and Tests
Logical operations
CP
AND
BSET
BTJT
ADC
SLL
XOR
CPL
NEG
Bit Operation
BRES
BTJF
ADD
SRL
JRT
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
SUB
SRA
JRF
SBC
RLC
JP
MUL
RRC
CALL
SWAP
CALLR
SLA
Unconditional Jump or Call
Conditional Branch
JRA
JRxx
TRAP
SIM
NOP
RET
Interruption management
Condition Code Flag modification
WFI
RIM
HALT
SCF
IRET
RCF
Using a pre-byte
PDY 90
Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
The instructions are described with one to four op-
codes.
PIX 92
Replace an instruction using di-
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
The whole instruction becomes:
PC-2
PC-1
PC
End of previous instruction
Prebyte
PIY 91
Replace an instruction using X in-
direct indexed addressing mode by a Y one.
opcode
10.2.1 Illegal Opcode Reset
PC+1
Additional word (0 to 2) according
to the number of bytes required to compute the ef-
fective address
In order to provide enhanced robustness to the de-
vice against unexpected behaviour, a system of il-
legal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
142/181
ST7WIND21
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
ADC
ADD
AND
BCP
Description
Add with Carry
Function/Example
A = A + M + C
A = A + M
Dst
Src
I1
H
H
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
A
M
Addition
A
M
M
M
Logical And
A = A . M
A
Bit compare A, Memory
Bit Reset
tst (A . M)
A
BRES
BSET
BTJF
BTJT
CALL
CALLR
CLR
bres Byte, #3
bset Byte, #3
btjf Byte, #3, Jmp1
btjt Byte, #3, Jmp1
M
M
M
M
Bit Set
Jump if bit is false (0)
Jump if bit is true (1)
Call subroutine
Call subroutine relative
Clear
C
C
reg, M
reg
0
N
N
N
1
Z
Z
Z
CP
Arithmetic Compare
One Complement
Decrement
tst(Reg - M)
A = FFH-A
dec Y
M
C
1
CPL
reg, M
reg, M
DEC
HALT
IRET
INC
Halt
1
0
Interrupt routine return
Increment
Pop CC, A, X, PC
inc X
I1
H
I0
N
N
Z
Z
C
reg, M
JP
Absolute Jump
Jump relative always
Jump relative
jp [TBL.w]
JRA
JRT
JRF
Never jump
jrf *
JRIH
JRIL
Jump if ext. INT pin = 1
Jump if ext. INT pin = 0
Jump if H = 1
(ext. INT pin high)
(ext. INT pin low)
H = 1 ?
JRH
JRNH
JRM
Jump if H = 0
H = 0 ?
Jump if I1:0 = 11
Jump if I1:0 <> 11
Jump if N = 1 (minus)
Jump if N = 0 (plus)
Jump if Z = 1 (equal)
I1:0 = 11 ?
I1:0 <> 11 ?
N = 1 ?
JRNM
JRMI
JRPL
JREQ
JRNE
JRC
N = 0 ?
Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
Jump if C = 1
Jump if C = 0
Jump if C = 1
C = 1 ?
JRNC
JRULT
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
143/181
ST7WIND21
INSTRUCTION SET OVERVIEW (Cont’d)
Mnemo
JRULE
LD
Description
Jump if (C + Z = 1)
Load
Function/Example
Unsigned <=
dst <= src
Dst
Src
I1
H
I0
N
N
N
N
N
Z
Z
Z
Z
Z
C
reg, M
A, X, Y
reg, M
M, reg
X, Y, A
MUL
NEG
NOP
OR
Multiply
X,A = X * A
neg $10
0
0
Negate (2's compl)
No Operation
OR operation
C
A = A + M
pop reg
pop CC
push Y
C = 0
A
M
reg
CC
M
M
POP
Pop from the Stack
M
I1
1
H
I0
0
C
0
PUSH
RCF
RET
RIM
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Substract with Carry
Set carry flag
reg, CC
I1:0 = 10 (level 0)
C <= A <= C
C => A => C
S = Max allowed
A = A - M - C
C = 1
RLC
RRC
RSP
SBC
SCF
SIM
reg, M
reg, M
N
N
Z
Z
C
C
A
M
N
Z
C
1
Disable Interrupts
Shift left Arithmetic
Shift left Logic
I1:0 = 11 (level 3)
C <= A <= 0
C <= A <= 0
0 => A => C
A7 => A => C
A = A - M
1
1
SLA
reg, M
reg, M
reg, M
reg, M
A
N
N
0
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
Shift right Logic
Shift right Arithmetic
Substraction
N
N
N
N
M
M
SWAP nibbles
A7-A4 <=> A3-A0
tnz lbl1
reg, M
Test for Neg & Zero
S/W trap
S/W interrupt
1
1
1
0
Wait for Interrupt
Exclusive OR
XOR
A = A XOR M
A
N
Z
144/181
ST7WIND21
11 ELECTRICAL CHARACTERISTICS
11.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are re-
11.1.5 Pin input voltage
ferred to V
.
SS
The input voltage measurement on a pin of the de-
vice is described in Figure 72.
11.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
Figure 72. Pin input voltage
Devices with an ambient temperature at T =25°C
A
DEVICE PIN
and T =T max (given by the selected temperature
A
A
range).
V
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean 3Σ).
IN
11.1.2 Typical values
Unless otherwise specified, typical data are based
on T =25°C, V =3.3V. They are given only as de-
A
33
sign guidelines and are not tested.
11.1.3 Typical curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
11.1.4 Loading capacitor
The loading conditions used for pin parameter
measurement are shown in Figure 71.
Figure 71. Pin loading conditions
DEVICE PIN
C
L
145/181
ST7WIND21
11.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the Device. This is a stress rating only and func-
tional operation of the Device under these condi-
tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.
11.2.1 Voltage Characteristics
Symbol
Ratings
Supply voltage
Maximum value
Unit
V
- V
5.6
VSS-0.3 to 5.6
VSS-0.3 to V18+0.3
VSS-0.3 to V33+0.3
50
V
DD
SS
Input Voltage on open drain pin
V
1) & 2)
V
Pins n°1 to 16 and 46 to 48
Pins n°17 to 45
IN
Input Voltage on other pins
|∆V
| and |∆V | Variations between different digital power pins
SSx
DDx
mV
|V
- V
|
Variations between digital and analog ground pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
50
SSA
SSx
V
ESD(HBM)
see Section 11.7 on page 155
V
ESD(MM)
11.2.2 Current Characteristics
Symbol
Ratings
Maximum value
Unit
3)
3)
I
Total current into V power lines (source)
100
100
25
VDD
DD
I
Total current out of V ground lines (sink)
SS
VSS
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
mA
I
50
IO
Output current source by any I/Os and control pin
Total injected current (sum of all I/O and control pins ex-
cept Port A and G pins)
- 25
2)
2)
ΣI
0
5)
INJ(PIN)
2)
I
Injected current on 5V tolerant pins (Port A and G)
5
INJ(PIN)
mA
5)
ΣI
Total injected current (Port A and G pins)
15
INJ(PIN)
11.2.3 Thermal Characteristics
Symbol
Ratings
Value
-65 to +150
150
Unit
°C
T
Storage temperature range
Maximum junction temperature
STG
4)
T
°C
JMAX
Notes:
1. Directly connecting the RESET and I/O pins to V or V could damage the Device if an unintentional internal reset
33
SS
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for
RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to V or V
.
33
SS
2. I
must never be exceeded. This is implicitly insured if V maximum is respected. If V maximum cannot be
INJ(PIN)
IN
INJ(PIN)
IN
respected, the injection current must be limited externally to the I
value. A positive injection is induced by V >V
IN 33
while a negative injection is induced by V <V . For true open-drain pads, there is no positive injection current, and the
corresponding V maximum must always be respected.
IN
SS
IN
3. All power supply (V ) and ground (V ) lines must always be connected to the external supply.
DD
SS
4.The average chip-junction temperature can be obtained from the formula T = T + P x RthJA (see Section 12.2 on
J
A
D
page 173).
5. When several inputs are submitted to a current injection, the maximum ΣI
is the absolute sum of the positive
INJ(PIN)
and negative injected currents (instantaneous values). These results are based on characterisation with ΣI
maxi-
INJ(PIN)
mum current injection on four I/O port pins of the Device.
146/181
ST7WIND21
11.3 OPERATING CONDITIONS
11.3.1 General Operating Conditions
Symbol
Parameter
Internal clock frequency
Power Supply
Conditions
Min
0
Max
12
Unit
MHz
V
f
CPU
V
4.0
0
5.6
55
DD
T
Ambient temperature range
°C
A
11.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the Device functional operating modes over temperature
range does not take into account the clock source current consumption. To get the total Device consump-
tion, the two current values must be added (except for HALT mode for which the clock is stopped).
Symbol
∆I
Parameter
Conditions
Max
Unit
Supply current variation vs. temperature
Constant V and f
10
%
DD(∆Ta)
DD
CPU
11.4.1 RUN and WAIT Modes
1)
2)
Symbol
Parameter
Conditions
Typ
1
Max
Unit
f
f
f
f
=12MHz, f
=12MHz
CPU
3.5
2
OSC
3)5)
4)5)
Supply current in RUN mode
=6MHz, f
=6MHz
CPU
1.5
1
RC_6MHz
I
mA
DD
=12MHz, f
=12MHz
1.5
1.5
OSC
CPU
Supply current in WAIT mode
=6MHz, f
=6MHz
CPU
1
RC_6MHz
Notes:
1. Typical data are based on T =25°C, V =5.
A
DD
2. Data based on characterization results, tested in production at V max.
DD
3. CPU running with memory access, all I/O pins in input mode with a static value at V or V (no load), all peripherals
33
SS
in reset state; clock input (OSC1) driven by external square wave.
4. All I/O pins in input mode with a static value at V or V (no load), all peripherals in reset state; clock input (OSC1)
33
SS
driven by external square wave.
5. The given consumption takes into account the I
the digital and USB peripherals.
of the 5V/3.3V and 3.3V/1.8V regulators required to operate both
ON
147/181
ST7WIND21
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
11.4.2 HALT Modes
1)
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current in HALT mode (suspend
mode for USB)
POR + 5V/3.3V REG.
+ 3.3V/1.8 REG.
I
100
190
µA
2)
DD
11.4.3 Supply and Clock Managers
The previous current consumption specified for
the Device functional operating modes over tem-
perature range does not take into account the
clock source current consumption. To get the total
device consumption, the two current values must
be added (except for HALT mode).
1)
3)
Symbol
Parameter
Conditions
Typ
Max
Unit
Supply current of internal RC 6MHz oscilla-
tor
180
500
250
I
µA
DD(CK)
4) & 5)
1000
Supply current of crystal oscillator
11.4.4 On-Chip Peripherals
Symbol
Parameter
Conditions
Typ
TBD
135
10
Unit
µA
2)
I
Auto Wake Up From Halt Timer
DD(AWU)
6)
I
Timer supply current
DD(T16)
6)
I
TBU supply current
DD(TBU)
7)
I
SPI supply current
TBD
TBD
DD(SPI)
8)
I
PS/2 supply current
µA
DD(PS/2)
Notes:
1. Typical data are based on T =25°C and f
=12MHz.
A
CPU
2. All I/O pins in input mode with a static value at V or V (no load). Data based on characterization results, tested in
33
SS
production at V max (pull-up consumption not included).
DD
3. Data based on characterization results, not tested in production.
4. Data based on characterization results done with the external components specified in Section 11.5.4, not tested in
production.
5. As the oscillator is based on a current source, the consumption does not depend on the voltage.
6. Data based on a differential I measurement between reset configuration (timer stopped) and timer counter enabled
DD
(only TCE bit set).
7. Data based on a differential I measurement between reset configuration (SPI disabled) and a permanent SPI master
DD
communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.
8. Data based on a differential I measurement between reset configuration (PS/2 disabled) and a permanent PS/2 com-
DD
munication (data sent equal to 55h).This measurement includes the pad toggling consumption.
148/181
ST7WIND21
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
11.4.5 RF Peripheral
Table 38. Consumption in Reception mode
Symbol
1 Receiver running
Current consumption for
Parameter
Conditions
Min
Typ
Max
Unit
I
RX0 or RX1 voltage regulators only
RX0 or RX1 RF block only
1
1.1
7
1.3
9
mA
mA
mA
DD-PM
Power Management
RX0 or RX1 current con-
sumption
I
DD-RF
Total Current
consumption
I
Reception with RX0 or RX1
13
15
1)
DD
2 Receivers running
Current consumption for
I
RX0 & RX1 voltage regulators only
RX0 & RX1 RF blocks only
Reception
1.6
1.8
14
21
2
mA
mA
mA
DD-PM01
Power Management
Current consumption on
RX0 & RX1
I
15
23
DD-RF01
Total Current
consumption
I
1)
DD-01
Note 1. CPU running with memory access, all I/O pins in input mode with static value at V or V (no load), all periph-
33
SS
erals in reset state (except RX block), oscillator driven by a crystal, associated power supply management.
149/181
ST7WIND21
11.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V , f
, and T .
DD OSC
A
11.5.1 General Timings
1)
Symbol
Parameter
Conditions
Min
2
Typ
Max
12
Unit
tCPU
ns
3
t
Instruction cycle time
c(INST)
f
f
=12MHz
167
10
250
1000
22
CPU
CPU
2)
tCPU
µs
Interrupt reaction time
t
v(IT)
t
= ∆t
+ 10
c(INST)
=12MHz
0.833
1.833
v(IT)
11.5.2 External Clock Source
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
OSC1 input pin high level voltage
OSC1 input pin low level voltage
0.7xV
V
33
OSC1H
33
V
V
V
0.3xV
33
OSC1L
SS
t
t
3)
w(OSC1H)
see Figure 73
OSC1 high or low time
15
w(OSC1L)
ns
t
t
3)
r(OSC1)
OSC1 rise or fall time
15
1
f(OSC1)
I
OSCx Input leakage current
V
≤V ≤V
33
µA
L
SS
IN
Figure 73. Typical Application with an External Clock Source
90%
V
V
OSC1H
OSC1L
10%
t
t
w(OSC1H)
t
t
w(OSC1L)
f(OSC1)
r(OSC1)
OSC2
Not connected internally
f
OSC
EXTERNAL
CLOCK SOURCE
I
L
OSC1
Device
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
150/181
ST7WIND21
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
11.5.3 Crystal Oscillator
The Device internal clock is supplied from a crystal
oscillator. All the information given in this para-
graph are based on characterization results with
specified typical external components. In the appli-
cation the load capacitors have to be placed as
close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal manufacturer for
more details (frequency, package, accuracy...).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1) 2)
f
Oscillator frequency
12
MHz
OSC
V
V
=3.3V
5.6
3.8
33
33
Oscillator start-up G
G
t
mA/V
m
m_OSC
=2V
3)
Start-up time
1
ms
ppm
%
without serial resistor
0.6
50
SU(OSC)
CK
Total quartz accuracy
abs. value + temp + aging
60
55
ACC
4)
α
Crystal oscillator duty cycle
45
OSC
Figure 74. Typical Application with a Crystal
i
2
f
OSC
C
L
OSC1
OSC2
CRYSTAL
5)
R
F
C
L
R
S
Device
Notes:
1. Refer to crystal manufacturer characteristics.
2. The oscillator selection can be optimized in terms of supply current using an high quality crystal with small R value.
S
Refer to crystal manufacturer characteristics for more details.
3. t
is the typical oscillator start-up time measured between V = 4.0V and the fetch of the first instruction (with
SU(OSC)
DD
a quick V ramp-up from 0 to V (<50µs)).
DD
DD
4. The crystal oscillator duty cycle and frequency have to be adjusted trough the C capacitances. Refer to crystal man-
L
ufacturer for more details.
5. Depending on the crystal power dissipation, a serial resistor R may be added. Refer to crystal manufacturer for more
s
details
151/181
ST7WIND21
CLOCK CHARACTERISTICS (Cont’d)
Figure 75. Determining load capacitance value
C
C
0
CRYSTAL
L
R
m
m
C
C
m
L
L
C
C
L
L
2
2
G
G
= R x (2 x Π x f
) x (2 x C + C )
m_critic
m_critic
m
OSC 0 L
< (4 x G
)
m_OSC
With :
R : crystal motional resistance
m
C : crystal motional capacitance
m
L : crystal motional inductance
m
C : load capacitance
L
C : shunt capacitance
0
11.5.4 6-MHz RC Oscillator
The Device internal clock can be supplied with a 6-MHz RC oscillator.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator frequency before
calibration
3.6
6
8.4
MHz
1)
At a specific temperature and V
er supply voltage.
pow-
18_DIG
5.4
6
6.6
11
2
MHz
Including 10% V
age variation only
power supply volt-
18_DIG
1)
f
t
OSC
Oscillator frequency after
calibration
Including 20°C temperature variation
1)
only
%
Including V
power supply voltage and
18_DIG
temperature variation over the product
23
10
1)
range
2)
Start-up time
µs
4
SU(OSC)
Notes:
1. Data based on characterization results.
2. t is the typical oscillator start-up time measured
between V = 4.0V and the fetch of the first instruction
DD
(with a quick V ramp-up from 0 to V (<50µs)).
DD
DD
SU(OSC)
152/181
ST7WIND21
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 76. Typical 6-MHz RC Oscillator
11.5.5 Auto Wake-up RC Oscillator
The Device internal clock can be supplied with an auto wake-up RC oscillator.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator frequency be-
fore calibration
60
100
140
Hz
1)
At a specific temperature and V
er supply voltage.
pow-
18_DIG
90
100
110
1
Hz
Including 10% V
age variation only
power supply volt-
18_DIG
1)
f
t
AWURC
Oscillator frequency af-
ter calibration
Including 20°C temperature variation
only
8
1)
%
Including V
power supply voltage and
18_DIG
temperature variation over the product
19
10
1)
range
2)
Start-up time
µs
4
SU(AWURC)
Notes:
1. Data based on characterization results.
2. t is the typical oscillator start-up time measured between V = 4.0V and the fetch of the first instruction (with
SU(AWURC)
DD
a quick V ramp-up from 0 to V (<50µs)).
DD
DD
Figure 77. Typical Internal RC Oscillator
153/181
ST7WIND21
11.6 MEMORY CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
DD OSC
11.6.1 RAM and Hardware Registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1)
V
Data retention mode
HALT mode (or RESET)
0.8
V
RM
Note:
1. Minimum V
supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware
18_DIG
registers (only in HALT mode). Guaranteed by construction, not tested in production.
154/181
ST7WIND21
11.7 EMC CHARACTERISTICS
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Susceptibility tests are performed on a sample ba-
sis during Device characterization.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
11.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the De-
vice (toggling 2 LEDs through I/O ports), the prod-
uct is stressed by two electro magnetic events until
a failure occurs (indicated by the LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the Device
until a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V and V through
DD
SS
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
A Device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
To complete these trials, ESD stress can be ap-
plied directly on the Device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015)
11.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at Device level with a typical application
environment and simplified MCU software. It
.
Level/
Symbol
Parameter
Conditions
Class
Voltage limits to be applied on any I/O pin to induce a
functional disturbance
V
=5V, T =+25°C, f
=12MHz,
OSC
DD
A
V
3B
FESD
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
V
=5V, T =+25°C, f =12 MHz, con-
DD
A
OSC
V
through 100pF on V and V pins to induce a func-
3B
FFTB
DD SS
forms to IEC 1000-4-4
tional disturbance
155/181
ST7WIND21
EMC CHARACTERISTICS (Cont’d)
11.7.2 Electro Magnetic Interference (EMI)
Based on a simple application running on the De-
vice (toggling 2 LEDs through the I/O ports), the
Device is monitored in terms of emission. This
emission test is in line with the norm SAE J 1752/
3 which specifies the board and the loading of
each pin.
Max vs. [f
/f
]
Unit
Monitored
Frequency Band
OSC CPU
Symbol
Parameter
Conditions
12/12MHz
0.1MHz to 30MHz
30MHz to 130MHz
130MHz to 1GHz
SAE EMI Level
18
21
17
4
V
=5V, T =+25°C,
A
DD
dBµV
S
Peak level
TQFP48 7x7 package
conforming to SAE J 1752/3
EMI
-
Notes:
1. Data based on characterization results, not tested in production.
2. Refer to Application Note AN1709 for data on other package types.
156/181
ST7WIND21
EMC CHARACTERISTICS (Cont’d)
11.7.3 Absolute Maximum Ratings (Electrical
Sensitivity)
11.7.3.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (a positive then a nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends on the
number of supply pins in the device (3 parts*(n+1)
supply pin). Two models can be simulated: Human
Body Model and Machine Model. This test con-
forms to the JESD22-A114A/A115A standard.
Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the Device
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the application note AN1181.
Absolute Maximum Ratings
1)
Symbol
Ratings
Conditions
Maximum value
Unit
Electro-static discharge voltage
(Human Body Model)
T =+25°C
V
2000
A
ESD(HBM)
V
Electro-static discharge voltage
(Machine Model)
T =+25°C
V
200
A
ESD(MM)
Notes:
1. Data based on characterization results, not tested in production.
11.7.3.2 Static and Dynamic Latch-Up
■ DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the Device and the
Device is put in reset mode. This test conforms
to the IEC1000-4-2 and SAEJ1752/3 standards.
For more details, refer to the application note
AN1181.
■ LU: 3 complementary static tests are required
on 10 Devices to assess the latch-up
performance. A supply overvoltage (applied to
each power supply pin) and a current injection
(applied to each input, output and configurable I/
O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC latch-up
standard. For more details, refer to the
application note AN1181.
Electrical Sensitivities
1)
Symbol
LU
Parameter
Static latch-up class
Dynamic latch-up class
Conditions
Class
T =+25°C
A
A
A
T =+50°C
A
V
=5V, f
=12MHz, T =+25°C
OSC A
DLU
A
DD
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
157/181
ST7WIND21
11.8 I/O PORT PIN CHARACTERISTICS
11.8.1 General Characteristics
Subject to general operating conditions for V , f
, and T unless otherwise specified.
33 OSC
A
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
2)
0.3xV33
V
Input low level voltage
Input high level voltage
IL
2)
V
CMOS ports
0.7xV33
IH
3)
V
Schmitt trigger voltage hysteresis
Input leakage current
250
mV
µA
hys
I
V
SS≤V ≤V33
15
L
IN
4)
I
Static current consumption
Floating input mode
200
S
3.3V Weak pull-up equivalent resis-
R
V =V
V33=3.3V
33
110
kΩ
5)
PU
IN
SS
tor (see Figure 80)
8)
R
R
5V pull-up equivalent resistor
V =V
VDD=5V
3.5
40
6.3
83
kΩ
Ω
PU_PS2
IN
SS
SS
Equivalent serial resistor
I/O pin capacitance
V =V
V33=3.3V
PU_USB
IN
C
5
pF
IO
6)
t
Output high to low level fall time
10
10
16
16
C =50pF
Between 10% and 90%
f(IO)out
r(IO)out
L
ns
6)
t
Output low to high level rise time
7)
t
External interrupt pulse time
1
t
CPU
w(IT)in
Notes:
1. Unless otherwise specified, typical data are based on T =25°C and V =5V.
A
DD
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 78). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I current characteristics). This
PU
PU
data is based on characterization results, tested in production at V max.
33
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
8. Rpu_PS2 pull-up are only available on PA5, PA6, PG0 and PG1.
158/181
ST7WIND21
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 78. Two typical Applications with
unused I/O Pin
Figure 79. Typical I vs. V with V =V
PU 33 IN SS
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
2
2.25
2.5
2.75
3
3.25
3.5
3.6
V
33DD
Device
0°C
10kΩ
25°C
55°C
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
Device
V33 (V)
Figure 80. Typical R vs. V with V =V
PU
33
IN
SS
120.0
100.0
80.0
60.0
40.0
20.0
0.0
0°C
25°C
55°C
2
2.25
2.5
2.75
3
3.25
3.5
3.6
V33 (V)
159/181
ST7WIND21
I/O PORT PIN CHARACTERISTICS (Cont’d)
11.8.2 Output Driving Current
Subject to general operating conditions for V , f
, and T unless otherwise specified.
A
33 OSC
Symbol
Parameter
Conditions
I =+5mA
Min
Max
Unit
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 82 and Figure 83)
0.6
IO
I =+2mA
0.35
1.2
IO
1)
V
OL
I =+20mA
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 81)
IO
V
I =+8mA
TBD
IO
I =-5mA
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 83)
2.6
IO
2)
V
OH
I =-2mA
TBD
IO
Figure 81. Typical V vs. V (high-sink I/Os)
OL
33
600.0
500.0
400.0
300.0
200.0
100.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
0°C
25°C
55°C
0.0
2
2
2.25
2.5
2.75
3
3.25
3.5
3.6
2.5
2.5
2.75
3
3.25
3.5
3.6
V33 (V)
V33 (V)
Figure 82. Typical V vs. V (standard I/Os)
OL
33
80.0
250.0
200.0
150.0
100.0
50.0
0°C
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
25°C
55°C
0°C
25°C
55°C
0.0
2
2.25
2.5
2.75
3
3.25
3.5
3.6
2
2.25
2.5
2.75
3
3.25
3.5
3.6
V33 (V)
V33 (V)
Notes:
1. The I current sunk must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
2. The I current sourced must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of
IO
I
(I/O ports and control pins) must not exceed I . True open drain I/O pins does not have V
.
OH
IO
V33
160/181
ST7WIND21
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 83. Typical V -V vs. V (standard I/Os)
33 OH
33
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0°C
25°C
55°C
2
2.25
2.5
2.75
3
3.25
3.5
3.6
V33 (V)
161/181
ST7WIND21
11.9 CONTROL PIN CHARACTERISTICS
11.9.1 Asynchronous RESET Pin
T = 0 to +55°C unless otherwise specified
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
7)
V
Input low level voltage
0.16xV
IL
33
V
Input high level voltage
0.85xV
IH
33
1)
V
Schmitt trigger voltage hysteresis
250
V
hys
I
I
=+5mA
=+2mA
0.6
0.35
110
IO
2) 6)
V
Output low level voltage
V
V
=3.3V
=3.3V
V
OL
33
33
IO
1)3)8)
R
Pull-up equivalent resistor
33
kΩ
µs
ON
30 +
t
Generated reset pulse duration
Internal reset sources
w(RSTL)out
256*f
OSC
4)
t
External reset pulse hold time
2.5
µs
h(RSTL)in
5)
t
Filtered glitch duration
200
ns
g(RSTL)in
Notes:
1. Data based on characterization results, not tested in production.
2. The I current sunk must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of I
IO
IO
(I/O ports and control pins) must not exceed I
.
VSS
3. The R pull-up resistor is based on a true resistor.
ON
4. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short pulses applied
on RESET pin with a duration below t can be ignored.
h(RSTL)in
5. The reset network protects the device against parasitic resets.
6. The output of the external reset circuit must have an open-drain output to drive the Device reset pad. Otherwise the
Device can be damaged when the CPU generates an internal reset.
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V max. level specified in Section 11.9.1. Otherwise the reset will not be taken into account internally.
IL
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified in Section 11.2.2 on page 146.
Figure 84. Typical I on RESET pin
Figure 85. Typical R on RESET pin
PU
PU
0.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
2
2.25
2.5
2.75
3
3.25
3.5
3.6
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
0°C
0°C
25°C
55°C
25°C
55°C
2
2.25
2.5
2.75
3
3.25
3.5
3.6
V33 (V)
V33 (V)
162/181
ST7WIND21
11.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V , f
, and T unless otherwise specified.
33 OSC
A
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out-
put compare, input capture, external clock, PWM output...).
11.10.1 Watchdog Timer
Symbol
Parameter
Conditions
Min
Typ
Typ
Max
Unit
65 536
5.461
4 194 304
349.525
t
CPU
t
Watchdog time-out duration
w(WDG)
fCPU = 12MHz
ms
11.10.2 Time Base Unit Timer
Symbol
Parameter
Conditions
Standalone mode
Standalone mode
Min
Max
Unit
2
65536
t
CPU
t
TBU time-out duration
w(TBU)
0.166
5.461
ms
f
= 12MHz
CPU
11.10.3 16-Bit Timer
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
Input capture pulse time
1
2
t
t
w(ICAP)in
CPU
CPU
t
PWM resolution time
f
f
= 12MHz
= 6MHz
166.7
333.3
0
res(PWM)
CPU
ns
CPU
f
Timer external clock frequency
PWM repetition rate
f
f
/4
/4
MHz
MHz
bit
EXT
CPU
f
0
PWM
CPU
Res
PWM resolution
16
PWM
11.10.4 Auto Wake-up from Halt Timer
Symbol
Parameter
Conditions
Min
1
Typ
Max
255
Unit
t
AWU
t
AWUFH time-out duration
w(AWU)
f
= 100Hz
10
2 550
ms
AWU
163/181
ST7WIND21
11.11 RF COMMUNICATION Electrical Characteristics
11.11.1 Radio Electrical Characteristics
11.11.1.1 Characterization Conditions
must comply with the conditions mentioned in the
Table 39.
In order to reach all the electrical characteristics
mentioned in Table 40 , the Device environment
Table 39. Receiver Characterization Conditions
Parameter
Name
Conditions
Min
Typ
Max
Unit
In frequency range “A”
Maximum Power Supply
Noise Level
PSN
at 50kHz in +/-30kHz bandwidth
referred to VSS_OUT_PLLn
In frequency range “A”
50
µV
A
RMS
Maximum CPOUT Noise
Level
CPOUTN
at 50kHz in +/-30kHz bandwidth
referred to V18_OUT_PLLn
In frequency range “C”
50
30
µV
A
RMS
Maximum Power Supply
Noise Level
PSN
PSN
at 27MHz in +/-100kHz bandwidth
referred to VSS_LNA
mV
C
D
RMS
In frequency range “D”
Maximum Power Supply
Noise Level
at 216MHz in +/-100kHz bandwidth
referred to V18_OUT_PLLn
600
µV
RMS
The power supplies has to be decoupled in order
to decrease noise amplitude on power supplies
below the values provide by Table 39 and also in
Figure 86.
These noise sources are the Device itself and also
external noise conducted through USB / PS/2 plug
or power supplies.
Figure 86 describes the frequency range defini-
tion, and shows the expected noise level on these
frequency ranges during receiving.
Figure 86. Frequency Range Definition
A
C D
0dBV
-20dBV
-40dBV
-60dBV
-80dBV
-100dBV
-120dBV
Note: High impedance measurements
164/181
ST7WIND21
RF COMMUNICATION Electrical Characteristics (Cont’d)
11.11.1.2 Characterization Information
Figure 88 shows the test board schematic used
with balun matched at 3.3KΩ.
Figure 87 shows the test board schematic used to
measure the sensitivity. This uses a single ended
to differential balun matched at 200Ω.
Figure 87. 200Ω Input circuit for Sensitivity Measurements (wide band balun)
10nF
10nF
RF_IN
RXPIN
RXNIN
50Ω
V
IN
200Ω
1:4
10nF
V
= 5µV = -99dBm on 200Ω load.
IN
Figure 88. 3.3KΩ Input circuit for Sensitivity Measurements
10nF
10nF
10nF
1.5µH
RF_IN
RXPIN
50Ω
V
3pF
IN
3.3KΩ
RXNIN
1.5µH
1:4
V
= 5µV = -111dBm on 3.3KΩ load.
IN
165/181
ST7WIND21
RF COMMUNICATION Electrical Characteristics (Cont’d)
Table 40. Receiver Radio Characteristics
Unless otherwise specified, typical data are based on T =25°C and V =1.8V
A
18
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
DEMODULATOR
Channel frequency
26,905
27,305
kHz
kHz
26,890 + (10×N)
(0 ≤ N ≤ 43)
Channel Frequency Range
FR
F
RANG
Local oscillator frequency
Data Rate at 2.5Kbit/s
Data Rate at 5.0Kbit/s
2.4
3.2
4.1
4.0
kHz peak
kHz peak
Admissible Frequency De-
viation
DEV25
DEV50
F
2.9
5.4
Admissible Crystal toler-
ance
Receiver and Transmitter contribu-
tion
XTAL
-120
120
ppm
pF
TOL
Input Capacitance
CIN
RIN
5
Attenuator off. RXPIN/RXNIN res.
(process and temp variation)
Attenuator on. RXPIN/RXNIN res.
(process and temp variation)
40
50
60
KΩ
ATTOFF
Input Resistance
RIN
180
210
230
Ω
ATTON
Attenuator Enable (with 3.3KΩ an-
tenna impedance)
VMX
500
500
160
mV
mV
mV
mV
ATTON
ATTOFF
ATTON
Maximum Input Signal
Compression Level
VMX
CP1
Attenuator Disable
Attenuator Enable (with 3.3KΩ an-
tenna impedance)
CP1
Attenuator Disable
100
5
ATTOFF
SENS25
SENS50
IN
IN
2.5 Kbit/s; F =2.5kHz
7
9
µV
µV
dev
RMS
1)
Sensitivity
5.0 Kbit/s; F =5kHz
6
dev
RMS
ACR
50kHz freq. offset (see Figure 51)
100kHz freq. offset (see Figure 51)
More than 200kHz frequency offset
(see Figure 53)
33
39
36
42
dB
Adjacent Channel Rejec-
tion
50
ACR
dB
100
Dual Interferers Level
Image Suppression
Co-Channel Rejection
DUAL
-45
dBm
INT
RX_IM
At +/-30kHz frequency offset
Data Rate at 2.5Kbit/s
27
-11
-11
8
30
-8
-8
10
1
dBc
dBc
dBc
dB
SUP
CO
REJ
Data Rate at 5.0Kbit/s
Analog Attenuator
Set-up Time
ATT
With 3.3KΩ antenna impedance
from RF Power Down mode
12
3
ANARF
WUdel
ms
RX
Note:
-4
1. Sensitivity is characterized for BER=10 , using NRZ coding with 3.3KΩ input circuit.
166/181
ST7WIND21
11.12 OTHER COMMUNICATION INTERFACE CHARACTERISTICS
11.12.1 USB - Universal Bus Interface
(Operating conditions TA = 0 to +70°C, V = 4.0 to 5.25V unless otherwise specified)
DD
USB DC Electrical Characteristics
Parameter
Symbol
VDI
Conditions
I(D+, D-)
Min.
0.2
Max.
Unit
V
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
Static Output Low
VCM
VSE
Includes VDI range
0.8
2.5
2.0
V
0.8
V
1)
VOL
RL of 1.5K ohms to 3.6v
0.3
V
1)
Static Output High
VOH
USBV
RL of 15K ohms to V
2.8
3.6
V
SS
3
USBVCC: voltage level
V
=5v
3.00
3.60
V
DD
Figure 89. USB: Data Signal Rise and Fall Time
Differential
Data Lines
Crossover
points
VCRS
VSS
tr
tf
Table 41. USB: Low-speed Driver Electrical Characteristics
Parameter
Symbol
Conditions
CL=50 pF
CL=600 pF
CL=50 pF
CL=600 pF
tr/tf
Min
Max
Unit
75
4)
Rise time
tr
300
ns
75
4)
Fall Time
tf
300
120
Rise/ Fall Time matching
trfm
80
%
V
Output signal Crossover
Voltage
VCRS
1.3
2.0
Notes:
1. RL is the load connected on the USB drivers.
2. All the voltages are measured from the local ground potential.
3. To improve EMC performance (noise immunity), it is recommended to connect a 100nF capacitor to the
USBVCC pin.
4. Measured from 10% to 90% of the data signal. For more detailed information, please refer to Chapter
7 (Electrical) of the USB specification (version 1.1).
167/181
ST7WIND21
11.12.2 SPI - Serial Peripheral Interface
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Subject to general operating condition for V
,
DD
f
, and T unless otherwise specified.
CPU
A
Symbol
Parameter
Conditions
Min
/128
0.0625
Max
Unit
Master
Slave
f
f
f
/4
CPU
2
CPU
f
=12MHz
=12MHz
f
CPU
SCK
MHz
SPI clock frequency
1/t
/2
c(SCK)
CPU
0
f
4
CPU
t
t
r(SCK)
SPI clock rise and fall time
see I/O port pin description
f(SCK)
t
SS setup time
SS hold time
Slave
Slave
120
120
su(SS)
t
h(SS)
t
t
Master
Slave
100
90
w(SCKH)
SCK high and low time
Data input setup time
Data input hold time
w(SCKL)
t
Master
Slave
100
100
su(MI)
t
su(SI)
ns
t
Master
Slave
100
100
h(MI)
t
h(SI)
t
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
0
120
240
120
a(SO)
t
dis(SO)
t
v(SO)
h(SO)
v(MO)
h(MO)
Slave (after enable edge)
t
0
t
0.25
0.25
Master (before capture edge)
t
CPU
t
Figure 90. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
t
t
dis(SO)
a(SO)
v(SO)
h(SO)
t
t
r(SCK)
f(SCK)
see
note 2
MISO
OUTPUT
INPUT
MSB OUT
see note 2
BIT6 OUT
LSB OUT
t
t
h(SI)
su(SI)
LSB IN
MSB IN
BIT1 IN
MOSI
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
33
33
168/181
ST7WIND21
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 91. SPI Slave Timing Diagram with CPHA=11)
SS
INPUT
t
t
su(SS)
c(SCK)
t
h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
dis(SO)
a(SO)
t
t
h(SO)
v(SO)
t
t
r(SCK)
f(SCK)
see
note 2
see
note 2
MISO
OUTPUT
MSB OUT
BIT6 OUT
HZ
LSB OUT
t
t
h(SI)
su(SI)
MSB IN
LSB IN
BIT1 IN
MOSI
INPUT
Figure 92. SPI Master Timing Diagram 1)
SS
INPUT
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
w(SCKH)
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
h(MI)
su(MI)
MISO
MOSI
INPUT
MSB IN
h(MO)
BIT6 IN
LSB IN
t
t
v(MO)
MSB OUT
LSB OUT
see note 2
BIT6 OUT
see note 2
OUTPUT
Notes:
1. Measurement points are done at CMOS levels: 0.3xV and 0.7xV
.
33
33
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
169/181
ST7WIND21
11.13 POWER-ON-RESET CHARACTERISTICS
Table 42. Power-on-reset characteristics
1)
Symbol
Parameter
Threshold voltage
Conditions
Min
Typ
Max
Unit
V
V
H
1.10
1.4
100
8
1.60
POR
POR
Hysteresis
mV
µA
nS
I
Current consumption
POR pulse duration
10
80
DD_POR
t
200
POR
Triangular glitch-
with 300mV height
t
Glitch duration filtered
nS
glitch
Table 43. Low Voltage Detector characteristics
1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset release threshold
V
3.5
4
V
IT+
IT-
(V rising)
DD
Reset generation threshold
V
3.4
3.9
V
(V falling)
DD
V
V
Hysteresis V - V
IT-
100
mV
hys
IT+
V
rise time rate
DD
0.02
500
V/ms
tPOR
Note:
1. Unless otherwise specified, typical data are based on T = 25°C and V -V = 3.3V. They are given only as design
A
33 SS
guidelines and are not tested.
170/181
ST7WIND21
11.14 VOLTAGE REGULATORS CHARACTERISTICS
Table 44. 5V-3.3V Voltage Regulator characteristics
1)
Symbol
Parameter
Input voltage range
Conditions
Min
4.00
3.10
Typ
5.00
Max Unit
V
5.60
3.60
V
V
IN
V
Output voltage range
3.30
OUT33
Output current drive (including exter-
nal current consumption)
I
30
mA
OUT33
C
Decoupling capacitance
Equivalent series resistor
Multi layer / ceramic capacitor
4.7
0
10
µF
33
ESR
0.5
1
Ω
at I
command
=0mA & Power-down
LOAD
400
µs
µs
t
I
Start-up delay
ON
at I =30mA & Power-down
command
LOAD
600
Current consumption
30
1
µA
µA
ON
I
I
current
DD
OFF
2)
Table 45. 3.3V-1.8V Voltage Regulator characteristics
1)
Symbol
Parameter
Input voltage range
Output voltage range
Conditions
Min
2.00
1.65
Typ
3.30
1.80
Max
Unit
V
3.60
1.95
250
V
V
IN
V
OUT18
Suspend mode
Normal mode
µA
mA
nF
Ω
I
Output current drive
OUT18
15
100
0
C
Decoupling capacitance Multi layer / ceramic capacitor
Equivalent series resistor
18
ESR
4
75
75
300
1
t
Start-up delay
without output consumption
Suspend mode
µs
ON
I
Current consumption
µA
µA
ON
Normal mode
I
I
current
DD
OFF
Table 46. 1.8V BandGap characteristics
1)
Symbol
Parameter
Current consumption
Start-up delay
Conditions
Min
30
Typ
Max
50
40
1
Unit
µA
I
t
35
25
ON
ON
10
µs
I
I
current
DD
µA
OFF
Note:
1. Unless otherwise specified, typical data are based on T = 25°C and V -V = 3.3V. They are given only as design
A
33 SS
guidelines and are not tested.
2. This voltage regulator is for internal supply only. It cannot be used to power external components.
171/181
ST7WIND21
12 PACKAGE CHARACTERISTICS
12.1 PACKAGE MECHANICAL DATA
Figure 93. 48-Pin Thin Quad Flat Package
mm
inches
Dim.
Min Typ Max Min Typ Max
D
A
A
1.60
0.063
0.006
D1
A2
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
A1
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.354
0.276
0.354
0.276
0.020
3.5°
D1
E
e
E1
E
E1
e
θ
0°
7°
0°
7°
c
L1
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
48
L
θ
L1
N
Figure 94. 100-Pin Thin Quad Flat Package
mm
inches
A
D
Dim.
Min Typ Max Min Typ Max
D1
A2
A
1.60
0.063
0.006
A1
A1 0.05
0.15 0.002
A2 1.35 1.40 1.45 0.053 0.055 0.057
b
C
0.17 0.22 0.27 0.007 0.009 0.011
0.09 0.20 0.004 0.008
b
e
D
16.00
14.00
16.00
14.00
0.50
0.630
0.551
0.630
0.551
0.020
3.5°
D1
E
E1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45 0.60 0.75 0.018 0.024 0.030
1.00 0.039
Number of Pins
100
c
L1
L
1
L
h
N
172/181
ST7WIND21
12.2 THERMAL CHARACTERISTICS
Symbol
Ratings
Value
Unit
°C/W
mW
Package thermal resistance (junction to ambient)
TQFP100
44
R
thJA
Package thermal resistance (junction to ambient)
TQFP48
55
1)
P
Power dissipation
500
D
Notes:
1. The power dissipation is obtained from the formula P =P +P
where P
is the Device internal power (I xV
)
D
INT
PORT
INT
DD DD
and P
is the port power dissipation determined by the user.
PORT
173/181
ST7WIND21
13 DEVICE CONFIGURATION
13.1 OPTION BYTE
The option byte allows the hardware configuration
of the microcontroller to be selected. In masked
ROM devices, the option bytes are fixed in hard-
ware by the ROM code (see option list).
FMP_R Full Memory Readout Protection
This option protects the ROM program memory
against readout. This protects the application-
firmware against software piracy.
– Readout enabled
– Readout disabled
WDGHWR Hardware Watchdog Reset
This option permanently enables the watchdog re-
set.
WDGHWI Hardware Watchdog Interrupt
This option permanently enables the watchdog
Top Level Interrupt (TLI) interrupt. Refer to Section
9.1 for more information in the WDGA and IE con-
trol bits in the WDGCSR register.
Behaviour when a Watchdog timeout
occurs
If WDGA=1, a reset is generated.
If WDGA=0 and IE=1, a TLI is generated.
0
0
If WDGA=1 a reset is generated.
If WDGA=0, a TLI is generated.
0
1
1
x
A reset is generated.
Note: 0= option disabled, 1= option enabled
If both are enabled the Reset event has priority.
13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the S19 hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.
The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
174/181
ST7WIND21
ST7WInD21 MICROCONTROLLER OPTION LIST
Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact
Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conditioning:
[ ] Tray
[ ] Tape & Reel
Hardware Watchdog Reset:
Hardware Watchdog Interrupt:
[ ] Enabled
[ ] Enabled
[ ] Disabled
[ ] Disabled
[ ] Disabled
Full Memory Readout Protection: [ ] Enabled
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175/181
ST7WIND21
13.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tained from the STMicroelectronics Internet site:
http//www.st.com.
Evaluation board
One evaluation tool is available from ST:
■ ST7WInD-EVAL
Emulator
One type of emulator is available from ST for the
ST7WInD21 family:
■ ST7 EMU3 high-end emulator is delivered with
everything (probes, TEB, etc.) needed to start
emulating the ST7WInD21. See Table 47.
Table 47. STMicroelectronics Development Tools
Emulation
Supported
Products
ST7 EMU3 series
ST7WInD-EMU3
ST7WInD21
176/181
ST7WIND21
13.4 ST7 APPLICATION NOTES
Table 48. ST7 Application Notes
IDENTIFICATION DESCRIPTION
APPLICATION EXAMPLES
AN1658
AN1720
AN1755
AN1756
SERIAL NUMBERING IMPLEMENTATION
MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS
A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555
CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI
EXAMPLE DRIVERS
SCI COMMUNICATION BETWEEN ST7 AND PC
AN 969
AN 970
AN 971
AN 972
AN 973
AN 974
AN 976
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN1475
AN1504
AN1602
AN1633
AN1712
AN1713
AN1753
AN1947
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
EMULATED 16 BIT SLAVE SPI
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS
GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART
SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS
SOFTWARE UART USING 12-BIT ART
ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY
177/181
ST7WIND21
Table 48. ST7 Application Notes
IDENTIFICATION DESCRIPTION
GENERAL PURPOSE
AN1476
AN1526
AN1709
AN1752
LOW COST POWER SUPPLY FOR HOME APPLIANCES
ST7FLITE0 QUICK REFERENCE NOTE
EMC DESIGN FOR ST MICROCONTROLLERS
ST72324 QUICK REFERENCE NOTE
PRODUCT EVALUATION
AN 910
AN 990
AN1077
AN1086
AN1103
AN1150
AN1151
AN1278
PERFORMANCE BENCHMARKING
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131
AN1322
AN1365
AN1604
MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264
HOW TO USE ST7MDT1-TRAIN WITH ST72F264
PRODUCT OPTIMIZATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1181
AN1324
AN1502
AN1529
USING ST7 WITH CERAMIC RENATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-
TOR
AN1530
AN1605
AN1636
AN1828
AN1971
USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE
UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS
PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE
ST7LITE0 MICROCONTROLLED BALLAST
PROGRAMMING AND TOOLS
AN 978
AN 983
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
AN1064
AN1071
AN1106
ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES
KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
178/181
ST7WIND21
Table 48. ST7 Application Notes
IDENTIFICATION DESCRIPTION
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1179
AN1446
AN1477
AN1478
AN1527
AN1575
AN1576
AN1577
AN1601
AN1603
AN1635
AN1754
AN1796
AN1900
AN1904
AN1905
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
EMULATED DATA EEPROM WITH XFLASH MEMORY
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS
DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS
SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL
USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK)
ST7 CUSTOMER ROM CODE RELEASE INFORMATION
DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC
FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT
HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL
ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY
ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY
SYSTEM OPTIMIZATION
AN1711
AN1827
AN2009
AN2030
SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS
IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC
BACK EMF DETECTION DURING PWM ON TIME BY ST7MC
179/181
ST7WIND21
14 KNOWN LIMITATIONS
14.1
CLEARING
ACTIVE
INTERRUPTS
14.2 STAB BIT DELAY
OUTSIDE INTERRUPT ROUTINE
The STAB bit is used to indicate to the firmware
that either the 12MHz main oscillator or the 6MHZ
RC oscillator is stabilized. Normally the STAB de-
lay depends on the oscillator type which has been
enabled. In current silicon revision, this delay is
fixed at 85µs whatever the oscillator. As a conse-
quence, to ensure that the oscillator is stabilized, a
software delay must be used.
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e. when:
- The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
14.3 RECEIVER TEST SIGNAL OUTPUT
- The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
The current silicon revision does not support the
capability to output receiver demodulated data on
PB0 and PB1. The RXT bit in the RFPAGER reg-
ister has no effect.
- The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
14.4 RECEIVER SLICER LEVEL REGISTER
The receiver slicer level low register is not availa-
ble on the current silicon revision (always read as
0). As a consequence, the resolution of the receiv-
er slicer level is 183Hz.
Perform SIM and RIM operation before and after
resetting an active interrupt request
Ex:
SIM
reset flag or interrupt mask
RIM
180/181
ST7WIND21
15 REVISION HISTORY
Date
Revision
Main changes
13-January-2005
1.0
First release
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia – Belgium - Brazil - Canada - China – Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
181/181
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