STA50513TR [STMICROELECTRONICS]
40V 3.5A QUAD POWER HALF BRIDGE; 40V 3.5A四路电源半桥
| 型号： | STA50513TR |
| 厂家： | 
ST |
| 描述： | 40V 3.5A QUAD POWER HALF BRIDGE |
| 文件： | 总10页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA505
40V 3.5A QUAD POWER HALF BRIDGE
1 FEATURES
Figure 1. Package
■ MULTIPOWER BCD TECHNOLOGY
■ MINIMUM INPUT OUTPUT PULSE WIDTH
DISTORTION
PowerSO36
■ 200mΩ RdsON COMPLEMENTARY DMOS
OUTPUT STAGE
Table 1. Order Codes
■ CMOS COMPATIBLE LOGIC INPUTS
■ THERMAL PROTECTION
Part Number
STA505
Package
PowerSO36
in Tape & Reel
■ THERMAL WARNING OUTPUT
■ UNDER VOLTAGE PROTECTION
STA50513TR
current capability.
The device is particularly designed to make the out-
put stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver 50 + 50W @
2 DESCRIPTION
STA505 is a monolithic quad half bridge stage in Mul-
tipower BCD Technology. The device can be used as
dual bridge or reconfigured, by connecting CONFIG
pin to Vdd pin, as single bridge with double current
capability, and as half bridge (Binary mode) with half
THD = 10% at V 30V output power on 8
Ω
load and
load in single
BTL configuration. The input pins have threshold pro-
portional to V pin voltage.
cc
80W @ THD = 10% at V 36V on 8
Ω
cc
L
Figure 2. Audio Application Circuit (Dual BTL)Pin Description
+VCC
VCC1A
15
C30
C55
1000µF
IN1A
29
M3
M2
M5
M4
1µF
IN1A
L18 22µH
C20
17
16
VL
23
24
+3.3V
OUT1A
CONFIG
PWRDN
FAULT
100nF
OUT1A
GND1A
C52
330pF
PWRDN
25
C99
100nF
14
12
R98
6
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
8Ω
LOGIC
VCC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
VCC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
V
CCSIGN
IN2A
36
31
20
19
OUT2A
GND2A
C109
330pF
C107
100nF
6
4
R103
6
IN2A
IN2B
C108
470nF
8Ω
GND-Reg
VCC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
Rev. 11
1/10
February 2006
STA505
Table 2. Pin Function
N°
1
Pin
GND-SUB
OUT2B
Vcc2B
Description
Substrate ground
Output half bridge 2B
Positive Supply
2 ; 3
4
5
GND2B
GND2A
Vcc2A
Negative Supply
Negative Supply
Positive Supply
6
7
8 ; 9
10 ; 11
12
OUT2A
OUT1B
Vcc1B
Output half bridge 2A
Output half bridge 1B
Positive Supply
13
GND1B
GND1A
Vcc1A
Negative Supply
Negative Supply
Positive Supply
14
15
16 ; 17
18
OUT1A
NC
Output half bridge 1A
Not connected
19
GND-clean Logical ground
20
GND-Reg
Vdd
Ground for regulator Vdd
21 ; 22
23
5V Regulator referred to ground
High logical state setting voltage
Configuration pin
VL
24
CONFIG
IN1A
29
Input of half bridge 1A
Stand-by pin
25
PWRDN
26
TRI-STATE Hi-Z pin
27
FAULT
TH-WAR
IN1A
Fault pin advisor
28
Thermal warning advisor
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to +Vcc
Signal Positive Supply
29
30
IN1B
31
IN2A
32
IN2B
33 ; 34
35 ; 36
Vss
Vcc Sign
2/10
STA505
Table 3. Functional Pin Status
PIN NAME
Logical value
IC -STATUS
FAULT
0
1
Fault detected (Short circuit, or Thermal ..)
Normal Operation
FAULT (*)
TRI-STATE
TRI-STATE
PWRDN
0
1
0
1
0
1
All powers in Hi-Z state
Normal operation
Low absorpion
PWRDN
Normal operation
THWAR
Temperature of the IC =130C
Normal operation
THWAR(*)
CONFIG
0
1
Normal Operation
CONFIG(**)
OUT1A=OUT1B ; OUT2A=OUT2B
(IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
(**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 3. Pin Connection
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
VSS
3
4
VSS
5
IN2B
GND2B
GND2A
6
IN2A
7
IN1B
VCC2A
8
IN1A
OUT2A
OUT2A
OUT1B
OUT1B
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
10
11
12
13
14
15
16
17
18
VCC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.
V
L
V
V
DD
DD
GND-Reg
GND-Clean
D01AU1273
3/10
STA505
Table 4. Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
40
Unit
V
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32
Operating Temperature Range
Storage and Junction Temperature
Vmax
Top
5.5
V
-40 to 90
-40 to 150
°C
°C
Tstg, Tj
Table 5. Thermal Data
Symbol
Parameter
Min.
Typ.
Max.
Unit
°C/W
°C
Tj-case Thermal Resistance Junction to Case (thermal pad)
2.5
TjSD
Twarn
thSD
Thermal shut-down junction temperature
Thermal warning temperature
150
130
25
°C
Thermal shut-down hysteresis
°C
Table 6. Electrical Characteristcs (VL = 3.3V; Vcc = 30V; Tamb = 25°C; fsw = 384Khz; unless otherwise
specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
RdsON Power Pchannel/Nchannel
MOSFET RdsON
Id=1A;
200
270
mΩ
Idss
Power Pchannel/Nchannel
leakage Idss
Vcc=35V
50
µA
gN
gP
Power Pchannel RdsON Matching Id=1A
95
95
%
%
Power Nchannel RdsON
Matching
Id=1A
Dt_s
Dt_d
Low current Dead Time (static)
see test circuit no.1; see fig. 1
10
20
50
ns
ns
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω
Id=3.5A; see fig. 3
td ON
td OFF
tr
Turn-on delay time
Turn-off delay time
Rise time
Resistive load
100
100
25
ns
ns
ns
ns
V
Resistive load
Resistive load; as fig.1;
Resistive load; as fig. 1;
tf
Fall time
25
VCC
Supply voltage operating voltage
10
36
VIN-High High level input voltage
VL/2
V
+300mV
VIN-Low Low level input voltage
VL/2
-
V
300mV
IIN-H
IIN-L
High level Input current
Low level input current
Pin voltage = VL
1
1
µA
µA
Pin voltage = 0.3V
4/10
STA505
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
I
High level PWRDN pin input
current
35
µA
PWRDN-H
VLow
Low logical state voltage VLow
(pin PWRDN, TRISTATE) (note 1)
VL = 3.3V
0.8
V
V
VHigh
High logical state voltage VHigh
(pin PWRDN, TRISTATE) (note 1)
VL = 3.3V
1.7
3
IVCC-
PWRDN
Supply current from Vcc in Power PWRDN = 0
Down
mA
IFAULT
Output Current pins
FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V
Tri-state=0
1
mA
mA
mA
IVCC-hiz Supply current from Vcc in Tri-
state
22
50
IVCC
Supply current from Vcc in
operation
both channel switching)
Input pulse width = 50% Duty;
Switching Frequency = 384KHz;
No LC filters;
IVCC-q
Isc (short circuit current limit)
(note 2)
3.5
70
6
7
8
A
VUV
Undervoltage protection threshold
V
tpw-min Output minimum pulse width
No Load
150
ns
Table 7.
Notes: 1. The following table explains the VLow, VHigh variation with V
L
VL
2.7
3.3
5
VLow min VHigh max
Unit
V
0.7
0.8
1.5
1.7
V
0.85
1.85
V
Note 2: See relevant Application Note AN1994
Table 8. Logic Truth Table (see fig. 5)
OUTPUT
MODE
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
5/10
STA505
Figure 4. Test Circuit.
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
INxY
M58
M57
OUTxY
R 8Ω
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 5.
+VCC
Q1
Q2
OUTxA
OUTxB
INxA
INxB
Q3
Q4
GND
D00AU1134
Figure 6.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTxA
Iout=4.5A
Q2
Q4
DTin(A)
DTout(B)
DTin(B)
INxB
Rload=8Ω
OUTxB
INxA
L67 22µ
L68 22µ
Iout=4.5A
Q3
C69
470nF
C70
470nF
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D00AU1162A
6/10
STA505
Figure 7. Typical Single BTL Configuration to Obtain 80W @ THD 10%, RL = 8Ω, VCC = 36V (note 1)
VL
+3.3V
23
18
N.C.
22µH
100nF
GND-Clean
GND-Reg
17
16
OUT1A
OUT1A
19
20
100nF
FILM
11
10
100nF
X7R
10K
100nF
X7R
470nF
FILM
100nF
OUT1B
OUT1B
OUT2A
OUT2A
22Ω
6.2
1/2W
VDD
VDD
1/2W
21
22
24
8Ω
6.2
1/2W
CONFIG
9
8
330pF
X7R
TH_WAR
PWRDN
FAULT
TH_WAR
OUT2B
OUT2B
28
25
100nF
FILM
3
2
nPWRDN
22µH
10K
VCC1A
27
26
+36V
15
TRI-STATE
IN1A
1µF
2200µF
63V
100nF
X7R
VCC1B
VCC2A
29
30
31
32
12
7
IN1B
IN1A
IN1B
IN2A
+36V
IN2B
1µF
X7R
VSS
VSS
VCC2B
33
34
4
14
13
GND1A
GND1B
100nF
X7R
VCCSIGN
35
100nF
X7R
V
CCSIGN
GND2A
GND2B
36
1
6
5
Add.
GNDSUB
D01AU1274
Note: 1. "A PWM modulator as driver is needed . In particular, this result is performed using the STA30X+STA50X demo board".
Figure 8. Typical Quad Half Bridge Configuration
+VCC
VCC1P
15
17
16
C21
2200µF
IN1A
29
M3
M2
M5
M4
R61
5K
IN1A
C31 820µF
L11 22µH
V
L
23
24
+3.3V
OUTPL
C71
100nF
CONFIG
PWRDN
FAULT
R41
20
C91
1µF
4Ω
OUTPL
PWRDN
25
C81
100nF
14
12
PGND1P
R51
6
R62
5K
C41
330pF
PROTECTIONS
R57
10K
R59
10K
27
26
&
LOGIC
VCC1N
TRI-STATE
C58
100nF
C51
1µF
C61
100nF
11
10
R63
5K
TH_WAR
IN1B
28
30
OUTNL
OUTNL
PGND1N
C32 820µF
L12 22µH
TH_WAR
C72
100nF
R42
20
IN1B
C92
1µF
4Ω
VDD
VDD
VSS
VSS
21
22
33
34
13
7
C82
100nF
R52
6
R64
5K
C42
330pF
REGULATORS
VCC2P
M17
M15
M16
M14
R65
5K
C58
100nF
C53
100nF
C33 820µF
L13 22µH
VCCSIGN
VCCSIGN
8
9
35
OUTPR
C60
100nF
C73
100nF
R43
20
C93
1µF
4Ω
36
31
20
19
OUTPR
C83
100nF
6
4
PGND2P
R53
6
R66
5K
IN2A
IN2B
C43
330pF
IN2A
GND-Reg
VCC2N
GND-Clean
C52
1µF
C62
100nF
3
2
R67
5K
OUTNR
OUTNR
PGND2N
C34 820µF
L14 22µH
IN2B
32
1
C74
100nF
R44
20
GNDSUB
C94
1µF
4Ω
5
C84
100nF
R54
6
R68
5K
C44
330pF
D03AU1474
For more information refer to the application notes AN1456 and AN1661
7/10
STA505
Figure 9. Power SO36 (Slug up) Mechanical Data & Package Dimensions
mm
inch
TYP. MAX.
0.135
0.126
0.039
0.008
-0.0015
0.015
0.012
0.630
0.38
DIM.
MIN.
3.25
3.1
TYP. MAX. MIN.
3.43 0.128
OUTLINE AND
MECHANICAL DATA
A
A2
A4
A5
a1
b
3.2
1
0.122
0.031
0.8
0.2
0.030
0.22
0.23
15.8
9.4
-0.040 0.0011
0.38 0.008
0.32 0.009
c
D
16
0.622
0.37
D1
D2
E
9.8
1
0.039
0.57
13.9
10.9
14.5 0.547
11.1 0.429
2.9
E1
E2
E3
E4
e
0.437
0.114
0.244
1.259
0.026
0.435
0.003
0.625
0.043
0.043
10˚
5.8
2.9
6.2
3.2
0.228
0.114
0.65
e3
G
11.05
0
0.075
15.9
1.1
0
H
15.5
0.61
h
L
0.8
1.1
0.031
N
10˚
s
8 ˚
8˚
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
7183931 D
8/10
STA505
Table 9. Revision History
Date
Revision
Description of Changes
First Issue in EDOCS DMS
December 2003
June 2004
8
9
Note 2: See relevant Application Note AN1994
November 2004
February 2006
10
11
Changed Vcc in Electrical Characteristics from 9 min to 10 min
Changed Top value on Table 4.
9/10
STA505
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