STA518 [STMICROELECTRONICS]
40V 3.5A quad power half bridge; 40V 3.5A四路电源半桥
| 型号： | STA518 |
| 厂家： | 
ST |
| 描述： | 40V 3.5A quad power half bridge |
| 文件： | 总19页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STA518
40V 3.5A quad power half bridge
Feature
■ Multipower BCD technology
■ Minimum input output pulse width distortion
■ 200mΩ R
complementary dmos output
dsON
stage
■ CMOS compatible logic inputs
■ Thermal protection
PSSO36 (slug up)
■ Thermal warning output
■ Under voltage protection
■ Short circuit protection
The device is particularly designed to make the
output stage of a stereo All-Digital High Efficiency
(DDX™) amplifier capable to deliver an output
power of 24W x 4 channels @ THD = 10% at Vcc
30V on 4W load in single ended configuration.
It can also deliver 50 + 50W @ THD = 10% at Vcc
29V as output power on 8W load in BTL
Description
STA518 is a monolithic quad half bridge stage in
Multipower BCD Technology. The device can be
used also as dual bridge or reconfigured, by
connecting CONFIG pin to Vdd pin, as single
bridge with double current capability.
configuration and 70W @ THD = 10% at Vcc 34V
on 8W in single paralleled BTL configuration.
The input pins have threshold proportional to VL
pin voltage
.
Order codes
Part number
Temp range, °C
Package
Packing
STA518
-40 to 90
-40 to 90
PowerSSO36 (slug up)
PowerSSO36 (slug up)
Tube
STA51813TR
Tape & reel
May 2006
Rev 3
1/19
www.st.com
1
Contents
STA518
Contents
1
2
3
Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
3.4
3.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
Logic interface and decode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power outputs: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Parallel output / high current operation: . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional informations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
7
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
STA518
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VLOW, VHIGH variation with I
bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Logic Truth Table (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/19
List of figures
STA518
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Audio application circuit ( Quad single ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Connection (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low current dead time for Single End application: test circuit. . . . . . . . . . . . . . . . . . . . . . . 11
High current dead time for Bridge application: block diagram . . . . . . . . . . . . . . . . . . . . . . 11
High current dead time for Bridge application: test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 11
STA518 Block Diagram Full-Bridge DDX® or Binary Modes . . . . . . . . . . . . . . . . . . . . . . . 12
STA518 Block Diagram Binary Half-Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Stereo Full Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Single BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Power Derating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. THD vs Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. PSSO36 (Slug Up) Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . 17
4/19
STA518
1
Audio application circuit
Audio application circuit
Figure 1.
Audio application circuit ( Quad single ended)
5/19
Pins description
STA518
2
Pins description
Figure 2.
Pin Connection (top view)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
V
CCSign
GND-SUB
OUT2B
OUT2B
VCC2B
VCCSign
VSS
3
4
VSS
5
IN2B
GND2B
GND2A
VCC2A
6
IN2A
7
IN1B
8
IN1A
OUT2A
OUT2A
OUT1B
OUT1B
9
TH_WAR
FAULT
TRI-STATE
PWRDN
CONFIG
VL
10
11
12
13
14
15
16
17
18
V
CC1B
GND1B
GND1A
VCC1A
OUT1A
OUT1A
N.C.
V
V
DD
DD
GND-Reg
GND-Clean
D01AU1273
Table 1.
N°
Pin Function
Pin
Description
1
2 ; 3
4
GND-SUB
OUT2B
Vcc2B
Substrate ground
Output half bridge 2B
Positive supply
5
GND2B
GND2A
Vcc2A
Negative Supply
Negative Supply
Positive supply
6
7
8 ; 9
10 ; 11
12
OUT2A
OUT1B
Vcc1B
Output half bridge 2A
Output half bridge 1B
Positive supply
13
GND1B
GND1A
Vcc1A
Negative Supply
Negative Supply
Positive supply
14
15
16 ; 17
35 ; 36
OUT1A
Vcc Sign
Output half bridge 1A
Signal Positive supply
6/19
STA518
Pins description
Table 1.
N°
Pin Function (continued)
Pin
Description
18
19
NC
GND-clean
GND-Reg
Vdd
Not connected
Logical ground
20
Ground for regulator Vdd
21 ; 22
23
5V Regulator referred to ground
Logic Reference Voltage
Configuration pin
VL
24
CONFIG
PWRDN
TRI-STATE
FAULT
TH-WAR
IN1A
25
Stand-by pin
26
Hi-Z pin
27
Fault pin advisor
28
Thermal warning advisor
Input of half bridge 1A
Input of half bridge 1B
Input of half bridge 2A
Input of half bridge 2B
5V Regulator referred to +Vcc
Signal Positive supply
29
30
IN1B
31
IN2A
32
IN2B
33 ; 34
35 ; 36
Vss
Vcc Sign
Table 2.
Functional Pin Status
Pin Name
Pin N.
Logical value
IC - STATUS
Fault detected (Short circuit,
or Thermal.)
FAULT
27
0
FAULT *
TRI-STATE
TRI-STATE
PWRDN
27
26
26
25
25
28
28
24
1
0
1
0
1
0
1
0
Normal Operation
All powers in Hi-Z state
Normal operation
Low consumption
PWRDN
Normal operation
THWAR
Temperature of the IC =130C
Normal operation
THWAR(1)
CONFIG
Normal Operation
OUT1A=OUT1B ;
OUT2A=OUT2B
CONFIG(2)
24
1
(IF IN1A = IN1B; IN2A = IN2B)
1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implemented single BTL
(MONO MODE) operation for high current.
7/19
Electrical specifications
STA518
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
Vmax
Top
DC Supply Voltage (Pin 4,7,12,15)
Maximum Voltage on pins 23 to 32
Operating Temperature Range
Power Dissipation (Tcase = 70°C)
40
5.5
V
V
-40 to 90
21
°C
W
°C
Ptot
Tstg, Tj Storage and Junction Temperature
-40 to 150
3.2
Recommended operating conditions
Table 4.
Symbol
Recommended operating conditions (*)
Parameter
Min. Typ. Max.
Unit
VCC
VL
DC Supply Voltage
10
2.7
0
36.0
5.0
70
V
V
Input Logic Reference
Ambient Temperature
3.3
Tamb
°C
(*) performances not guaranteed beyond recommended operating conditions
3.3
Thermal data
Table 5.
Symbol
Thermal data (*)
Parameter
Min.
Typ. Max. Unit
Tj-case
TjSD
Twarn
thSD
Thermal Resistance Junction to Case (thermal pad)
Thermal shut-down junction temperature
Thermal warning temperature
1.5
°C/W
°C
150
130
25
°C
Thermal shut-down hysteresis
°C
(*) see Thermal information
3.4
Thermal information
The power dissipated within the device depends primarly on the supply voltage, load
impedance and output modulation level. The PSSO36 Package of the STA518 includes an
exposed thermal slug on the top of the device to provide a direct thermal path from the IC to
the heatsink. For the Quad single ended application the Dissipated Power vs Ouptut Power
is shown in Figure 10.
8/19
STA518
Electrical specifications
Considering that for the STA518 the Thermal resistance Junction to slug is 1.5°C/W and the
extimated Thermal resistance due to the grease placed between slug and heat sink is
2.3°C/W ( the use of thermal pads for this package is not recommended), the suitable Heat
Sink Rth to be used can be drawn from the following graph Figure 11, where is shown the
Derating Power vs.Tambient for different heatsinkers.
3.5
Electrical characteristcs
Table 6.
Electrical Characteristcs
Refer to circuit in Figure 3 (V = 3.3V; V = 30V; R = 8Ω; f = 384KHz;
L
CC
L
sw
T
= 25°C unless otherwise specified)
amb
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Power Pchannel/Nchannel
MOSFET RdsON
RdsON
Id = 1A
200
270
mΩ
Power Pchannel/Nchannel
leakage Idss
Idss
gN
VCC = 35V
Id = 1A
50
µA
%
Power Pchannel RdsON
Matching
95
95
Power Nchannel RdsON
Matching
gP
Id = 1A
%
ns
ns
Dt_s
Dt_d
td ON
Low current Dead Time (static)
see test circuit Figure 3
10
20
50
L = 22µH; C = 470nF; RL = 8 Ω
Id = 3A; seeFigure 5
High current Dead Time
(dinamic)
Turn-on delay time
Resistive load; VCC = 30V
Resistive load; VCC = 30V
100
100
25
ns
ns
ns
ns
V
td OFF Turn-off delay time
tr
tf
Rise time
Resistive load; as Figure 3
Fall time
25
VCC
Supply voltage operating voltage
10
36
VL/2
+300mV
VIN-H
VIN-L
High level input voltage
Low level input voltage
V
V
VL/2
300mV
-
IIN-H
IIN-L
Hi level Input current
Low level input current
Pin voltage = VL
1
1
µA
µA
Pin voltage = 0.3V
IPWRDN-
Hi level PWRDN pin input current VL = 3.3V
35
µA
V
H
Low logical state voltage VLow
VL = 3.3V
VLOW
VHIGH
0.8
(pin PWRDN, TRISTATE) (1)
High logical state voltage VHigh
VL = 3.3V
1.7
3
V
(pin PWRDN, TRISTATE) (1)
IVCC-
Supply current from Vcc in Power
PWRDN = 0
Down
mA
PWRDN
9/19
Electrical specifications
STA518
Table 6.
Symbol
Electrical Characteristcs (continued)
Refer to circuit in Figure 3 (V = 3.3V; V = 30V; R = 8Ω; f = 384KHz;
L
CC
L
sw
T
= 25°C unless otherwise specified)
amb
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Output Current pins
IFAULT FAULT -TH-WARN when
FAULT CONDITIONS
Vpin = 3.3V
1
mA
Supply current from Vcc in Tri-
IVCC-hiz
state
V
CC = 30V; Tri-state = 0
22
50
mA
mA
VCC = 30V;
Supply current from VCC in
operation
Input pulse width = 50% Duty;
Switching Frequency = 384kHz;
No LC filters;
IVCC
(both channel switching)
IVCC-q Isc (short circuit current limit) (2) VCC = 30V
3.5
70
6
7
A
V
Undervoltage protection
threshold
VUV
tpw_min Output minimum pulse width
No Load
150
ns
1. The Table 7 explains the VLOW, VHIGH variation with Ibias.
2. See relevant Application Note AN1994
Table 7.
V
, V
variation with I
LOW HIGH bias
VL
VLow min
VHigh max
Unit
2.7
3.3
5
0.7
0.8
1.5
1.7
V
V
V
0.85
1.85
Table 8.
Logic Truth Table (see Figure 4)
OUTPUT
MODE
TRI-STATE
INxA
INxB
Q1
Q2
Q3
Q4
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
Hi-Z
DUMP
ON
OFF
ON
NEGATIVE
POSITIVE
Not used
OFF
ON
OFF
OFF
ON
OFF
10/19
STA518
Electrical specifications
Low current dead time for Single End application: test circuit.
Figure 3.
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
DTr
DTf
Duty cycle = 50%
M58
M57
OUTxY
R 8Ω
INxY
+
-
V67 =
vdc = Vcc/2
gnd
D03AU1458
Figure 4.
High current dead time for Bridge application: block diagram
+VCC
Q1
Q2
OUTxA
OUTxB
INxA
INxB
Q3
Q4
GND
D00AU1134
Figure 5.
High current dead time for Bridge application: test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+VCC
Duty cycle=A
Duty cycle=B
DTout(A)
M58
M57
M64
M63
Q1
OUTA
Iout=4A
Q2
OUTB
DTin(A)
INA
DTout(B)
L68 22µ
DTin(B)
INB
Rload=8Ω
L67 22µ
Iout=4A
Q3
C69
470nF
C70
470nF
Q4
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D03AU1517
11/19
Technical information
STA518
4
Technical information
The STA518 is a dual channel H-Bridge that is able to deliver 50W per channel (@
THD=10% R = 8Ω,
L
V
= 29V) of audio output power in high efficiency.
CC
The STA518 converts both DDX and binary-controlled PWM signals into audio power at the
load. It includes a logic interface , integrated bridge drivers, high efficiency MOSFET outputs
and thermal and short circuit protection circuitry.
In DDX mode, two logic level signals per channel are used to control high-speed MOSFET
switches to connect the speaker load to the input supply or to ground in a Bridge
configuration, according to the damped ternary Modulation operation.
In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The
STA518 includes over-current and thermal protection as well as an under-voltage
Lockout with automatic recovery. A thermal warning status is also provided.
®
Figure 6.
STA518 Block Diagram Full-Bridge DDX or Binary Modes
INL[1:2]
INR[1:2]
VL
OUTPL
Left
H-Bridge
Logic I/F
and Decode
PWRDN
OUTNL
TRI-STATE
Protection
Circuitry
FAULT
OUTPR
OUTNR
TWARN
Right
H-Bridge
Regulators
Figure 7.
STA518 Block Diagram Binary Half-Bridge Mode
INL[1:2]
LeftA
OUTPL
‰-Bridge
INR[1:2]
Logic I/F
and Decode
VL
LeftB
PWRDN
OUTNL
‰-Bridge
TRI-STATE
Protection
Circuitry
FAULT
RightA
‰-Bridge
OUTPR
TWARN
RightB
‰-Bridge
Regulators
OUTNR
4.1
Logic interface and decode:
The STA518 power outputs are controlled using one or two logic level timing signals. In
order to provide a proper logic interface, the Vbias input must operate at the dame voltage
as the DDX control logic supply.
Protection circuitry:
12/19
STA518
Technical information
The STA518 includes protection circuitry for over-current and thermal overload conditions. A
thermal warning pin (pin.28) is activated low (open drain MOSFET) when the IC
temperature exceeds 130°C, in advance of the thermal shutdown protection. When a fault
condition is detected , an internal fault signal acts to immediately disable the output power
MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain
MOSFET connected to the fault pin (pin.27) is switched on.
There are two possible modes subsequent to activating a fault:
1. SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent,
an activated fault will disable the device, signaling low at the FAULT output.
The device may subsequently be reset to normal operation by toggling the TRI-STATE
pin from High to Low to High using an external logic signal.
2. AUTOMATIC recovery mode: This is shown in the Audio Application Circuit of Quad
single Ended). The FAULT and TRI-STATE pins are shorted together and connected to
a time constant circuit comprising R59 and C58.
An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to
resume following a delay determined by the time constant of the circuit.
If the fault condition is still present , the circuit operation will continue repeating until the
fault condition is removed .
An increase in the time constant of the circuit will produce a longer recovery interval.
Care must be taken in the overall system design as not to exceed the protection
thesholds under normal operation.
4.2
4.3
Power outputs:
The STA518 power and output pins are duplicated to provide a low impedance path for the
device's bridged outputs. All duplicate power, ground and output pins must be connected for
proper operation.
The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state
during power-up until the logic power supply, V , is settled.
L
Parallel output / high current operation:
When using DDX Mode output , the STA518 outputs can be connected in parallel in order to
increase the output current capability to a load. In this configuration the STA518 can provide
70W into 8 ohm.
This mode of operation is enabled with the CONFIG pin (pin.24) connected to VREG1 and
the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB,
OUTRA=OUTRB.
4.4
Additional informations:
Output Filter: A passive 2nd-order passive filter is used on the STA518 power outputs to
reconstruct an analog Audio Signal . System performance can be significantly affected by
the output filter design and choice of passive components. A filter design for 6ohm/8ohm
loads is shown in the Typical Application circuit of Figure 9.
Quad Single ended circuit (Figure 1) shows a filter for ½ bridge mode, 4 ohm loads.
13/19
Technical information
Figure 8.
STA518
Typical Stereo Full Bridge Configuration to Obtain 50+50W @ THD = 10%,
RL = 8Ω, VCC =29V
+VCC
VCC1A
15
17
16
C30
1µF
C55
1000µF
IN1A
29
M3
M2
M5
M4
IN1A
L18 22µH
C20
V
23
24
L
+3.3V
OUT1A
CONFIG
PWRDN
FAULT
100nF
OUT1A
GND1A
C52
330pF
PWRDN
25
C99
100nF
14
12
R98
6
PROTECTIONS
R57
10K
R59
10K
27
26
&
C23
470nF
8Ω
LOGIC
VCC1B
R63 R100
C101
100nF
TRI-STATE
20
6
C58
100nF
C31
1µF
11
10
C21
100nF
TH_WAR
IN1B
28
30
OUT1B
OUT1B
GND1B
TH_WAR
L19 22µH
IN1B
VDD
VDD
VSS
VSS
21
22
33
34
13
7
REGULATORS
V
CC2A
C32
1µF
M17
M15
M16
M14
C58
100nF
C53
100nF
L113 22µH
VCCSIGN
VCCSIGN
8
9
35
OUT2A
C60
100nF
C110
100nF
36
31
20
19
OUT2A
GND2A
C109
330pF
C107
100nF
6
4
R103
6
IN2A
IN2B
IN2A
C108
470nF
GND-Reg
8Ω
V
CC2B
R104
20
R102
6
C106
100nF
GND-Clean
C33
1µF
3
2
C111
100nF
OUT2B
OUT2B
GND2B
IN2B
32
1
L112 22µH
GNDSUB
5
D00AU1148B
Figure 9.
Typical Single BTL Configuration to Obtain 70W @ THD 10%, R = 8Ω,
L
V
= 34V (note 1))
CC
V
L
+3.3V
23
18
N.C.
22µH
100nF
GND-Clean
GND-Reg
17
16
OUT1A
OUT1A
19
20
100nF
FILM
11
10
100nF
X7R
10K
100nF
X7R
470nF
FILM
100nF
OUT1B
OUT1B
OUT2A
OUT2A
22Ω
6.2
1/2W
VDD
VDD
1/2W
21
22
24
8Ω
6.2
1/2W
CONFIG
9
8
330pF
X7R
32V
32V
TH_WAR
PWRDN
FAULT
TH_WAR
OUT2B
OUT2B
28
25
100nF
FILM
3
2
nPWRDN
22µH
10K
VCC1A
27
26
15
TRI-STATE
IN1A
1µF
2200µF
63V
100nF
X7R
VCC1B
VCC2A
29
30
31
32
12
7
IN1B
IN1A
IN1B
IN2A
IN2B
1µF
X7R
VSS
VSS
VCC2B
33
34
4
14
13
GND1A
GND1B
100nF
X7R
VCCSIGN
35
100nF
X7R
V
CCSIGN
GND2A
GND2B
36
1
6
5
Add.
GNDSUB
D04AU1549
Note:
1
"A PWM modulator as driver is needed . In particular, this result is performed using the
STA308+STA518+STA50X demo board". Peak Power for t ≤1sec
14/19
STA518
Characterization curves
5
Characterization curves
The following characterization are obtained using the quad single ended configuration (Figure 1) with
STA308A controller
Figure 10. Power Dissipation vs Output Power Figure 11. Power Derating Curve
Pd(W)
Pd (W)
16
14
12
10
8
25
20
15
10
5
1
1)Infinite
2) 1.5 C/W
3) 3 C/W
4) 4.5 C/W
5) 6 C/W
Vcc=30V
Rl=4ohm
F =1Kz
3
2
4
6
5
4
2
0
0
4
8
12
16
20
24
20 40 60 80 100 120 140 160
Tambient(C)
0
4 x Pout (W)
Figure 12. THD+N vs Output Power
Figure 13. Output Power vs Supply Voltage
Pout(W)
30
THD(%)
10
27.5
Vcc = 26V
Rl = 4 ohm
F = 1KHz
5
Rl=4 ohm
25
F=1KHz
22.5
Single Ended
20
2
1
Single Ended
17.5
15
THD=10%
12.5
0.5
10
THD=1%
7.5
5
0.2
0.1
2.5
100m
200m
500m
1
2
5
10
20 30
Pout(W)
+10
+12
+14
+16
+18
+20
Vdc
+22
+24
+26
+28 +30
Figure 14. THD vs Frequency
THD(%)
1
0.5
0.2
Rl=4 ohm
0.1
Pout=1W
Single Ended
0.05
0.02
0.01
20
50
100
200
500
1k
2k
5k
10k 20k
Freq(Hz)
15/19
Characterization curves
STA518
The following characterizations are obtained using the stereo full bridge configuration (Figure 8) with
STA308A controller.
Figure 15. Output Power vs Supply Voltage
Figure 16. THD+N vs Output Power
THD(%)
10
90
80
o(W)
5
Rl=8ohm
F=1KHz
Vcc=29V
2
70
60
50
40
30
20
10
Rl=8ohm
1
F=1KHz
THD=10%
0.5
Double BTL
Stereo Full
BTL
0.2
0.1
Single
Parallel BTL
THD=1%
0.05
0.02
0.01
0
+10
100m
200m
500m
1
2
5
10
20
60
+12
+14
+16
+18
+20
+22
+24
+26
+28
+30
+32
+34 +36
Pout(W)
Vsupply(V)
Figure 17. Power Dissipation vs Output Power
Pd (W)
12
Vcc=29V
10
Rl=8ohm
8
6
4
2
0
F=1KHz
0
10
20
30
40
50
2 X Pout (W)
The following characterizations are obtained using the single BTL configuration (Figure 9) with STA308A
controller.
Figure 18. THD+N vs Output Power
THD(%)
10
5
Vcc=34V
2
Rl=8ohm
1
F=1KHz
0.5
Single BTL
0.2
0.1
0.05
0.02
0.01
100m 200m
500m
1
2
5
10
20
50 80
Pout(W)
16/19
STA518
Package information
6
Package information
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 19. PSSO36 (Slug Up) Mechanical Data & Package Dimensions
mm
inch
TYP. MAX.
0.097
DIM.
MIN.
2.15
2.15
0
0.18
0.23
10.10
TYP. MAX. MIN.
2.47 0.084
2.40 0.084
OUTLINE AND
MECHANICAL DATA
A
A2
a1
b
0.094
0.003
0.014
0.012
0.075
0
0.36 0.007
0.32 0.009
10.50 0.398
c
(1)
0.413
D
(1)
E
7.4
7.6
0.291
0.299
e
e3
F
G
G1
H
h
0.50
8.50
2.3
0.020
0.035
0.090
0.004
0.002
0.413
0.016
0.033
0.169
0.10
0.06
10.50 0.398
0.40
10.10
0.55
L
0.85 0.022
M
N
O
Q
S
T
U
X
4.3
10˚ (max)
1.2
0.8
2.9
3.65
1.0
0.047
0.031
0.114
0.144
0.039
0.185
0.279
4.10
6.50
4.70 0.161
7.10 0.256
Y
PowerSSO-36
(slug-up)
(1) “D and E” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
7618147 A
17/19
Revision history
STA518
7
Revision history
Table 9.
Date
Document revision history
Revision
Changes
19-Aug-2004
11-Nov-2004
1
2
Initial release.
Changed symbol in “Electrical Characteristics”.
Changed operating temperature range value to -40 to 90°C
(seeTable 3).
18-May-2006
3
18/19
STA518
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19/19
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