STD2NB80 [STMICROELECTRONICS]
N - CHANNEL 800V - 4.6 ohm - 1.9A - IPAK/DPAK PowerMESH MOSFET; N - CHANNEL 800V - 4.6欧姆 - 1.9A - IPAK / DPAK的PowerMESH MOSFET
| 型号： | STD2NB80 |
| 厂家： | 
ST |
| 描述： | N - CHANNEL 800V - 4.6 ohm - 1.9A - IPAK/DPAK PowerMESH MOSFET |
| 文件： | 总9页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STD2NB80
N - CHANNEL 800V - 4.6
Ω
- 1.9A - IPAK/DPAK
PowerMESH MOSFET
TYPE
VDSS
RDS(on)
ID
STD2NB80
800 V
< 6.5 Ω
1.9 A
■
■
■
■
■
■
TYPICAL RDS(on) = 4.6 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
3
ADD SUFFIX ”T4” FOR ORDERING IN TAPE
& REEL (2500 UNITS)
3
2
1
1
DESCRIPTION
IPAK
TO-251
(Suffix ”-1”)
DPAK
TO-252
(Suffix ”T4”)
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■
SWITCH MODE POWER SUPPLIES(SMPS)
DC-AC CONVERTERS FOR WELDING
EQUIPMENTAND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
■
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDGR
VGS
ID
Parameter
Value
800
Unit
V
Drain-source Voltage (VGS = 0)
Drain- gate Voltage (RGS = 20 k
Gate-source Voltage
800
V
)
Ω
± 30
1.9
V
Drain Current (continuous) at Tc = 25 oC
A
o
ID
Drain Current (continuous) at Tc = 100 C
1.2
A
I
DM(• )
Drain Current (pulsed)
7.6
A
o
Ptot
Total Dissipation at Tc = 25 C
55
W
Derating Factor
0.44
4.5
W/oC
V/ns
oC
oC
dv/dt(1) Peak Diode Recovery voltage slope
Tstg
Storage Temperature
-65 to 150
Tj
Max. Operating Junction Temperature
150
(•) Pulse width limited by safe operating area
( 1) ISD ≤ 2A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/9
January 1999
STD2NB80
THERMAL DATA
Rthj-case Thermal Resistance Junction-case
Max
Max
Typ
2.27
100
1
oC/W
oC/W
oC/W
oC
Thermal Resistance Junction-ambient
Rthj-amb
Rthc-sink Thermal Resistance Case-sink
Tl
Maximum Lead Temperature For Soldering Purpose
275
AVALANCHE CHARACTERISTICS
Symbol
Parameter
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
1.9
A
EAS
Single Pulse Avalanche Energy
176
mJ
(starting Tj = 25 oC, ID = IAR, VDD = 50 V)
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwisespecified)
OFF
Symbol
V(BR)DSS Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (VGS = 0) VDS = Max Rating
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
800
V
ID = 250 µA VGS = 0
IDSS
IGSS
VDS = Max Rating
1
50
µA
Tc = 125 oC
A
µ
Gate-body Leakage
Current (VDS = 0)
± 100
nA
VGS = ± 30 V
ON ( )
Symbol
Parameter
Test Conditions
VDS = VGS ID = 250 µA
Min.
Typ.
Max.
Unit
VGS(th)
Gate Threshold
Voltage
3
4
5
V
RDS(on)
ID(on)
Static Drain-source On VGS = 10V ID =1.3 A
Resistance
4.6
6.5
Ω
On State Drain Current VDS > ID(on) x RDS(on)max
VGS = 10 V
1.9
A
DYNAMIC
Symbol
Parameter
Forward
Test Conditions
VDS > ID(on) x RDS(on)max ID = 1.3 A
Min.
Typ.
Max.
Unit
gfs ( )
1
2
S
Transconductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25 V f = 1 MHz VGS = 0
440
60
7
pF
pF
pF
2/9
STD2NB80
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on delay Time
Rise Time
VDD = 400 V ID = 1.5 A
12
10
ns
ns
RG = 4.7 Ω
VGS = 10 V
(see test circuit, figure 3)
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 640 V ID =3 A VGS = 10 V
17
6.5
7.5
24
nC
nC
nC
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
VDD = 640 V ID = 3 A
RG = 4.7 Ω VGS = 10 V
(see test circuit, figure 5)
15
17
22
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
ISD
ISDM (• )
Source-drain Current
Source-drain Current
(pulsed)
1.9
7.6
A
A
VSD ( ) Forward On Voltage
ISD = 1.9 A VGS = 0
1.6
V
trr
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
650
2.8
8.5
ns
ISD = 2.6 A di/dt = 100 A/ s
VDD = 100 V
(see test circuit, figure 5)
µ
Tj = 150 oC
Qrr
C
µ
IRRM
A
( ) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/9
STD2NB80
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-sourceVoltage
CapacitanceVariations
4/9
STD2NB80
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drainDiode Forward Characteristics
5/9
STD2NB80
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Fig. 4: Gate Charge test Circuit
Resistive Load
Fig. 5: Test Circuit For InductiveLoad Switching
And Diode Recovery Times
6/9
STD2NB80
TO-251 (IPAK) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
2.2
TYP.
MAX.
2.4
MIN.
0.086
0.035
0.027
0.025
0.204
MAX.
0.094
0.043
0.051
0.031
0.212
0.033
A
A1
A3
B
0.9
1.1
0.7
1.3
0.64
5.2
0.9
B2
B3
B5
B6
C
5.4
0.85
0.3
0.012
0.95
0.6
0.6
6.2
6.6
4.6
16.3
9.4
1.2
1
0.037
0.023
0.023
0.244
0.260
0.181
0.641
0.370
0.047
0.039
0.45
0.48
6
0.017
0.019
0.236
0.252
0.173
0.626
0.354
0.031
C2
D
E
6.4
4.4
15.9
9
G
H
L
L1
L2
0.8
0.8
0.031
H
L
D
L2
L1
0068771-E
7/9
STD2NB80
TO-252 (DPAK) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
2.2
TYP.
MAX.
2.4
MIN.
0.086
0.035
0.001
0.025
0.204
0.017
0.019
0.236
0.252
0.173
0.368
MAX.
0.094
0.043
0.009
0.035
0.212
0.023
0.023
0.244
0.260
0.181
0.397
A
A1
A2
B
0.9
1.1
0.03
0.64
5.2
0.23
0.9
B2
C
5.4
0.45
0.48
6
0.6
C2
D
0.6
6.2
E
6.4
6.6
G
4.4
4.6
H
9.35
10.1
L2
L4
0.8
0.031
0.6
1
0.023
0.039
H
DETAIL ”A”
D
L2
DETAIL ”A”
L4
0068772-B
8/9
STD2NB80
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1998 STMicroelectronics – Printed in Italy – All Rights Reserved
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9/9
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