STE2007_06 [STMICROELECTRONICS]
96 x 68 Single-chip LCD controller/driver; 96× 68单芯片LCD控制器/驱动器
| 型号： | STE2007_06 |
| 厂家： | 
ST |
| 描述： | 96 x 68 Single-chip LCD controller/driver |
| 文件： | 总62页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STE2007
96 x 68 Single-chip LCD controller/driver
■ Low power consumption, suitable for battery
Features
operated systems
■ 68 x 96 bits Display Data RAM
■ 33,49, 65 and 68 Lines mode
■ Row by row scrolling
■ Interfaces supply voltage range from 1.6 to
3.6V
■ High voltage generator supply voltage range
from 2.4 to 3.6V
■ Interfaces
■ Display supply voltage range from 3 to 13.2V
– 3-lines Serial Interface (read and write)
– I2C (read and write)
Description
– 4-Line serial (read and write)
■ Partial display mode (33,25,17,9 lines mode)
The STE2007 is a low power LCD driver, capable
to drive 96 columns and up to 68 lines, designed
for monochrome displays.
■ Fully integrated oscillator that requires no
external components
■ CMOS compatible inputs
The STE2007 includes fully integrated bias
voltage generator (up to 5x multiplication factor),
and internal oscillator, thus reducing to minimum
the number of external components required and
the current consumption.
■ Programmable ID-Number
■ Programmable Bias Ratio
■ Programmable columns organization
■ Fully integrated configurable LCD bias voltage
The STE2007 features the three standard serial
interfaces (3 and 4 lines serial, I2C interface).
generator with:
– Selectable multiplication factor
(3x, 4X and 5X)
– Effective sensing for high precision output
– Eight selectable temperature compensation
coefficients
■ Designed for chip-on-glass (COG) applications
December 2006
Rev 3
1/62
www.st.com
62
Content
STE2007
Content
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Driver pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
CPU interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Display driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MCU Tx Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Driver TxData Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1
4.1.2
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.2
2
I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1
4.3.2
4.3.3
4.3.4
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Starting the communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4
Reading mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1 IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Display Data RAM (DDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
DDRAM and Page/column address circuit . . . . . . . . . . . . . . . . . . . . . . . . 27
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STE2007
Content
5.2
5.3
Line address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Partial Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.1
5.3.2
5.3.3
5.3.4
33 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
25 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4
Command parameters default configuration . . . . . . . . . . . . . . . . . . . . . . 38
6
Instruction setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1
6.2
6.3
Initialization (power on sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Display data writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
8
Power on/power off timing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Display on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Display all points on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.10 Data reading from driver (Driver TxData–mode) . . . . . . . . . . . . . . . . . . . 46
8.11 Power Control Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.12 VLCD set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.1 V0R - Voltage Range Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.2 VOP set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.12.3 Electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.13 Power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.15 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.16 Image Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Content
STE2007
8.17 Bias Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.18 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.19 Charge Pump Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.20 Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.21 Icon mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.22 N- Line inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.23 Number of lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9
Chip mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10
4/62
STE2007
Introduction
1
Introduction
In this document is specified LCD driver for Black&White full graphic displays with a
resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows).
Abbreviations
LCD
COG
MCU
Liquid Crystal Display
Chip On Glass –technology
Micro Controller Unit
DDRAM Display Data Random Access Memory
MSB
LSB
Most Significant Bit
Least Significant Bit
To Be Defined
T.B.D.
Table 1.
General driver parameters
Driver assembly technology
Chip On Glass (COG)
Memory Size
(Columns x Rows)
96x68
DDRAM capacity:
6528 bits
Mux
1:68
1:65
1:49
1:33
Frame frequency (Hz)
65
70
75
80
5/62
Introduction
STE2007
Figure 1.
Chip mechanical drawing
R66
STE2007
BUMP SIDE
(0,0)
Y
X
!
/
!
!
45µm
VSS_AUX
VSS_AUX
VSS_AUX
VSS_AUX
72µm
R67
R65
6/62
STE2007
Driver pin description
2
Driver pin description
2.1
CPU interface pins
Table 2.
Signal
CPU interface logic
Type
Description
Note
!RES
I
Reset Input
When Low the
communication port is
enabled
!CS
I
Chip Select Input
Must be connected to
SDAIN at Module Level
SDOUT
0
Serial Data Output
SDAIN
SCLK
I
I
Serial Data Input /I2C Interface Data Input
Serial Clock Input/I2C Interface Clock
Must be left floating
when I2C Interface is not
is use
SDA_OUT
0
I2C Bus Data Out
SA1
SA0
I
I
I2C Slave Address
I2C Slave Address
Cannot be left floating
Cannot be left floating
Must be connected to
VSSAUX at Module
Level when 4-Line SPI is
not in USE
!D/C
I
4 Line SPI Data/Command Selector
2.2
Power supply pins
Table 3.
Signal
Power supply pins
Type
Description
Analog & Digital Grounds
Note
VSS
VSS_LCD
VSS_CP
VDDI
Power
Power
Power
Power
Power
Power
Power
Drivers Analog Ground
Booster Ground
Digital Power
VDD
Analog Supply
VDD_CP
VSSAUX
Booster Power Supply
Auxiliar Vss Output
7/62
Driver pin description
STE2007
Table 4.
Signal
High voltage pins
Type
Description
Booster Output
Booster Sense Input
Note
High
Cext = 0.1-1µF
Connected to Vss
VLCD
Voltage
High
Voltage
Must be connected to
Vlcd at module level
VLCD_SENSE
COM0 to
COM67
High
Voltage
Unused lines must be left
floating
LCD Row Driver Output
LCD Row Driver Output
LCD Column Driver Output
High
Voltage
Unused lines must be left
floating
COMS
High
Voltage
Unused lines must be left
floating
SEG0 to SEG95
2.3
Configuration pins
Table 5.
Signal
Configuration pin description
Type
Config
Description
Note
VSS/VSSAUX
VDDI
Internal Oscillator Stopped
Internal Oscillator Active
OSCIN
I
SEL1
SEL0
Interfa
I2C
VSS/VSSAUX
VSS/VSSAUX
VDD1
VSS//VSSAUX
SEL0 -SEL1
I
VDD1
VSS/VSSAUX
VDD1
SPI 4-Line
Serial 3-Lin
Not Us
VDD1
VSS/VSSAUX
IDA=”0”
IDA=”1”
IDB=”0”
IDB=”1”
IDA
IDB
I
I
VDDI
VSS/VSSAUX
VDDI
8/62
STE2007
Driver pin description
2.4
Test pins
Table 6.
Signal
Test pin description
Type
Description
Note
Must Be connected to VSS
in Normal Working Mode
T2
T1
T0
T3
T4
T5
I
Test Input. Enable Test Mode.
Must Be connected to VSS
in Normal Working Mode
I
Test Input. Enable Test Mode.
Test Input.
Must Be connected to VSS
in Normal Working Mode
I
Must Be OPEN in Normal
Working Mode
O
O
O
Test Output.
Must Be OPEN in Normal
Working Mode
Test Output.
Must Be OPEN in Normal
Working Mode
Test Output.
Must Be OPEN in Normal
Working Mode
T6
O
O
Test Output.
VREF_BUFF
Analog Test Output
Must be left floating
9/62
Electrical characteristics
STE2007
3
Electrical characteristics
3.1
Absolute maximum ratings
Table 7.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDDI
VDD
VLCD
ISS
Vi
Supply Voltage Range
Supply Voltage Range
LCD Supply Voltage Range
Supply Current
- 0.5 to + 5
- 0.5 to + 5
- 0.5 to + 14.0
- 50 to +50
-0.5 to VDDI + 0.5
- 10 to + 10
- 10 to + 10
300
V
V
V
mA
V
Digital Inputs Voltage
Iin
DC Input Current
mA
mA
mW
mW
°C
°C
Iout
Ptot
Po
DC Output Current
Total Power Dissipation (Tj = 85°C)
Power Dissipation per Output
Operating Junction Temperature(1)
Storage Temperature
30
Tj
-25 to + 85
- 65 to 150
Tstg
VDD pin vs
VDDI (*)
±1500
±1750
V
V
All Pins(2) vs ESD maximum Withstanding Voltage range Test
VDDI
Condition : CDF-AEC-Q100-002-"Human body Model"
Acceptance criteria: "Normal performance
All Pins vs
Power
±2000
V
supplies(3)
1. Device behavior and characterization are measured over this temperature range during internal
qualification of the product. During production testing, however, device performance is measured at a fixed
ambient temperature, typically 25°C.
2. Except VDD pin
3. Except VDDI supply
Note:
(*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together
10/62
STE2007
Electrical characteristics
3.2
DC characteristics
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V;
Tamb = 25°C; unless otherwise specified.
Table 8.
Symbol
DC characteristics
Parameter
Test Condition
Min.
Typ.
Max.
Unit
VDD,VDDCP Power Supply Voltage
Operating Voltage
2.4
3.6
V
Power Supply
VDDI
I/O supply Voltage
1.6
3.6
V
Voltage(Logic)
VLCD
Booster Output
13.5
13.5
V
V
VLCD_SENSE Booster Sense Input
V
LCD=10V; VDD=2.6V;
No display Load;
SCLK=0Hz
LCD Supply Voltage
VLCD
-2.2
2.2
5
%
Accuracy
f
Power Saver Mode ON
(Interfaces quiescent)
1
µA
I(VDDI
)
Logic Supply Current
Analog Supply Current
Power Saver Mode OFF
(Interfaces quiescent)
6
20
µA
µA
Write Mode
120
250
VLCD=10V;Booster= 5X;
f
SCLK=0Hz; VDD=2.4V
I(V
DD
90
180
µA
+V
)
Refresh Rate=75Hz;
no display load
DDCP
Logic inputs
Logic High level input
voltage
VIH
0.7VDDI
Vss
VDDI
0.3VDDI
1
V
V
Logic Low level input
voltage
VIL
IIH
Logic High level input
current
µA
µA
Logic Low level input
current
IlL
-1
Logic outputs
VOH
Logic High level output
voltage
lOUT = -500µA;
0.8VDDI
Vss
VDDI
V
V
VDDI=1.6V
Logic Low level output
voltage
lOUT = 500µA;
VDDI=1.6V
VOL
0.2VDDl
11/62
Electrical characteristics
STE2007
3.3
AC characteristics
Tamb = 25°C; unless otherwise specified.
Table 9.
AC Operation - Internal oscillator
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VDDI= 1.6; VDD= 2.9V
Rafresh Rate = 75Hz
FFRAME
Frame Frequency Default
65
75
84
Hz
3.4
MCU Tx data mode
Table 10. AC Characteristics for serial interface
Symbol
Signal
Description
Notes
Min.
Typ.
Max.
Unit
tcss
tcsh
tchw
tsds
tsdh
tac
60
100
50
ns
ns
ns
ns
ns
ns
!CS
Chip select
Data setup time
Data hold time
Access Time
100
100
0
Input Serial Data
Interface
SDAIN
125
100
Output Serial Data
interface
SDAOUT
Output Disable
Time
tod
25
100
ns
ns
ns
tscyc
tshw
Serial clock cycle
250
100
Serial clock H
pulse width
SCLK
Serial clock input
Serial clock L
pulse width
tslw
100
ns
Note:
1
2
The input signal rise and fall times must be within 10ns.
Every timing is specified on the basis of 30% and 70% of VDDI.
Figure 2.
MCU TxData timing
tchw
tcss
tcsh
tchw
!CS
tscyc
tslw
SCLK
tshw
tf
tr
tsds
tsdh
SDA/MCU TxData
12/62
STE2007
Electrical characteristics
Table 11. Input signals change time
Signal
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
Inputs
tr,tf
10
ns
1. To 30% & 70% levels
3.5
Driver TxData mode
Table 12. Timings based on 4 MHz SCLK speed
Symbol
Item
Condition
Min.
Typ.
Max.
Units
T1
T2
T3
T4
T5
Data hold time
Note 1
100
10
125
100
100
–
ns
ns
ns
ns
ns
Access time
–
–
–
–
Output disable time
Data setup time
!CS pulse width high
25
100
250
Note:
1
Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns
before SCLK pulse falling edge
2
3
The input signal rise and fall times must be within 10ns.
Every timing is specified on the basis of 30% and 70% of VDDI.
Table 13. Timings based on 1 MHz SCLK speed
Symbol
Item
Condition
Min.
Typ.
Max.
Units
T1
T2
T3
T4
T5
Data hold time
–
–
–
–
–
100
10
125
450
450
–
ns
ns
ns
ns
ns
Access time
Output disable time
Data setup time
1CS pulse width high
25
100
250
Note:
1
2
The input signal rise and fall times must be within 10ns.
Every timing is specified on the basis of 30% and 70% of VDDI.
13/62
Electrical characteristics
Figure 3.
STE2007
Driver TxData Mode AC timing characteristics
Timing A
Timing B
SCLK
MCU TxData
Command
Tx
Hi±±
Rx
Command
MCU Data direction
Driver TxData
Tx
Hi±±
Status
Hi±±
T1
T2
Timing A
SCLK
MCU TxData
Driver TxData
Driver SDA direction
in
out
!CS
T3
T4
Timing B
SCLK
MCU TxData
D/C
Driver TxData
Driver SDA direction
out
in
T5
!CS
1/2 SCLK
1/2 SCLK
3.5.1
Reset timing
Table 14. Reset timing
Symbol
Signal
Description
Min.
Max.
Unit
trs
trw
trj
!RES
!RES
!RES
Reset time
2500
Reset low pulse width (for valid reset)
Reset rejection (for noise spike)
2500
ns
1000
Note:
14/62
1
2
The input signal rise and fall times must be within 10ns.
Every timing is specified on the basis of 30% and 70% of VDDI.
STE2007
Figure 4.
Electrical characteristics
Reset timing
trj
trw
!RES
trs
Normal operation
During reset
Internal circuit status
15/62
Interface
STE2007
4
Interface
4.1
3-lines 9-bit serial interface
STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and
the host processor.
It consists of three lines:
–
–
–
SDAIN/SDAOUT Serial Data
SCLK Serial Clock
!CS Peripheral enable: - Active Low- Enables and Disables the serial interface
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of
!RES, the serial interface is ready to receive data after the internal reset time. Serial data
must be input to SDA in the sequence D/!C, D7 to D0. STE2007 read data on SCLK rising
edge. The first bit of serial data D/!C is data/command flag. When D/!C =”1” D7 to D0 bits
are display RAM data or Command Parameters. When D/!C=”0” D7 to D0 bits identify a
command
4.1.1
MCU TxData mode (write mode)
STE2007 is always a slave device on the communication bus and receive the
communication clock on the SCLK pin from the master. Information are exchanged word-
wide. Every word is composed by 9 bit. The first bit is named D/!C and indicates whether the
following byte is a command (D/!C =0) or a Display Data Byte (D/!C =1).
During data transfer, the data line is sampled by the receiver unit on the SCLK rising edge.
The data/command received is transferred to DDRAM or Executed on the first falling edge
after the latching rising edge or on the !CS rising edge.
If !CS stays low after the last bit of a command/data byte, the serial interface expects the
D/!C bit of the next data byte on the next SCLK positive edge.
A reset pulse on !RES pin interrupts any transmission.
Figure 5.
MCU TxData mode
!CS
D/C D7 D6 D5 D4 D3 D2 D1 D0 D/C D7 D6 D5 D4
SDA
SCLK
10 11 12 13 14
1
2
3
4
5
6
7
8
9
4.1.1.1 Data/command transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received
Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a
command parameter, the not complete received byte is discarded, the communication is
interrupted and the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready
to receive the same byte interrupted re-transmitted or a new command identifier.
16/62
STE2007
Figure 6.
Interface
3-lines SPI Data transfer break condition
Break
!CS
SCL
SDA
D7
D6
D5
D4
D3
D/!C
D7
D6
D5
D4
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0204
4.1.1.2 Data/command transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters
to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS
is forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
If a new command identifier is transferred after a pause condition the previous
communication session is definitively closed.
Four are the possible conditions:
–
–
–
–
Command-Pause-Command
Command-Pause-Parameter
Parameter-Pause-Command
Parameter-Pause-Parameter
Figure 7.
3-lines SPI data transfer pause
Pause
!CS
SCL
SDA
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0203
17/62
Interface
STE2007
4.1.2
Driver TxData Mode (read mode)
The Driver TxData–mode is a method to check the electrical interconnection between LCD
driver and baseband, to identify the driver and for VDD Intercfonnection electrical self
testing.
Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper
electrical contact on VDD can be noted from a too low level of VLCD.
The serial interface Driver TxData–mode is controlled by three input signals.
The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled
when !CS is low after having received one Reading Command.
To access Driver TxData–mode a Reading command must be sent to STE2007 driver. The
first bit (D/C) is low to indicates next 8–bits are for command. The data is read to the driver
on the rising edge of SCLK (see section ”MCU TxData–mode”). After last command bit (bit
0) is read SDAOUT becomes active (Low impedance) and MCU is able to read data from
driver.
SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK
rising edges from the last SCLK rising edge of teh reading command transfer (Figure 8).
After sending out all 8 bits the driver release automatically the bus and go back to the MCU
TxData–mode. MCU Txdata line changes from high–z to active low or high in the falling
edge of 8th SCLK pulse. !CS must be set high and low again before !D/C writing can
continue.
If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted
and SDAOUT is forced in high impedance Mode.
SDAOUT and SDAIN line can be short circuited in normal working conditions.
18/62
STE2007
Interface
Figure 8.
AC timing characteristics
Timing A
Timing B
SCLK
MCU TxData
Command
Hi±±
Command
MCU Data direction
Tx
Rx
Tx
Driver TxData
Hi±±
Status
Hi±±
T1
T2
Timing A
SCLK
MCU TxData
Driver TxData
Driver SDA direction
in
out
!CS
T3
T4
Timing B
SCLK
MCU TxData
D/C
Driver TxData
Driver SDA direction
out
in
T5
!CS
1/2 SCLK
1/2 SCLK
Figure 9.
Timing chart for start and stop of data reading from driver
Self Test command writing
Reading of status
D/C writing
...
SCLK
...
1
1
2
8
9
2
8
2
1
7
High ±
...
MCU TxData
0
1
0
D/C
D/C='0'
7
...
...
7
High ±
...
Driver TxData
7
1
0
6
...
!CS
Driver TxData begins
MCU TxData begins
MCU TxData begins
19/62
Interface
STE2007
4.2
4-Line SPI
STE2007 4-lines serial interface is a bidirectional link between the display driver and the
host processor.
It consists of four lines:
–
–
–
–
SDA Serial Data
SCL Serial Clock
!CS Peripheral enable: - Active Low- Enables and Disables the serial interface
Mode selection (D/!C).
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of
!RES, the serial interface is ready to receive data after the internal reset time.
4.2.1
MCU TxData mode (write mode)
STE2007 is always a slave device on the communication bus and receive the
communication clock on the SCL pin from the master. Information are exchanged byte-wide.
During data transfer, the data line is sampled by the receiver unit on the SCL rising edge.
D/!C line status set whether the byte is a command (D/!C =0) or a data (D/!C =1); D/!C line is
read on the eighth SCL clock pulse during every byte transfer.
If !CS stays low after the last bit of a command/data byte, the serial interface expects the
MSB of the next data byte on the next SCL positive edge.
If !CS line is forced high in the middle of a data transfer, not complete Data bytes and
Commands bytes are discarded.
A reset pulse on !RES pin interrupts any transmission.
Figure 10. 4-lines SPI commands transfe
!CS
D/!C
SCL
SDA
D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
(input)
SDA
(output)
Hi-Z
COMMAND
COMMAND
COMMAND
COMMAND
LR0189
Figure 11. 4-lines SPI Video data write cycle
!CS
D/!C
SCL
SDA
D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
(input)
SDA
(output)
Hi-Z
DATA to VIDEO RAM
DATA to VIDEO RAM
DATA to VIDEO RAM
COMMAND
LR0190
20/62
STE2007
Interface
4.2.1.1 Data/command transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received
Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a
command parameter, the not complete received byte is discarded, the communication is
interrupted and the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready
to receive the same byte interrupted re-transmitted or a new command identifier.
Figure 12. 4-lines SPI Data Transfer break condition
Break
!CS
D/!C
SCL
SDA
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0192
4.2.1.2 Data/command transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters
to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS
is forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
If a new command identifier is transferred after a pause condition the previous
communication session is definitively closed.
Four are the possible conditions:
–
–
–
–
Command-Pause-Command
Command-Pause-Parameter
Parameter-Pause-Command
Parameter-Pause-Parameter
21/62
Interface
STE2007
Figure 13. 4-lines SPI Data transfer pause
Pause
!CS
D/!C
SCL
SDA
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0191
4.2.2
Driver TxData Mode (read mode)
Throughout SDA line is possible to read some registers value (ID Numbers, Status byte,
temperature).
SDA (output Driver) is in High impedance in steady state and during data write.
Figure 14. 4-lines SPI 8-Bit read cycle
DATA
Read Command
Next Command
!CS
D!C
SCL
High ±
SDA
(Input)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
High ±
SDA
(Output)
D0
D7
D6
D5
D4
D3
D2
D1
LR0255
MCU Data Tx Start
LCD Driver Data Tx Start
MCU Data Tx Start
2
4.3
I C Bus
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
–
–
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high will be interpreted as a
Start or Stop Data Transfer condition (see below).
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
22/62
STE2007
Interface
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer starts with a start condition and terminated with a stop condition. The
number of data bytes transferred between the start and the stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2007 will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
23/62
Interface
STE2007
Figure 15. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
D00IN1151
Figure 16. Acknowledgment on the I2C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
4.3.1
4.3.2
Communication protocol
The STE2007 is an I2C slave. The access to the device is bi-directional since data write and
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
Starting the communication
To start the communication between the bus master and the slave LCD driver, the master
must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA
bus line (Most significant bit first). This consists of the 7-bit Device Address Code, and the 1-
bit Read/Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to
the type of communication (read or write).
All slaves with the corresponding address acknowledge in parallel, all the others ignore the
I2C-bus transfer.
Figure 17. Addree byte
STE2007
SLAVE ADDRESS
S S R
ADDRESS BYTE
0
1
1
1
1 A A
/
1
0 W
READ or WRITE
DESIGNATOR
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STE2007
Interface
4.3.3
MCU TxData Mode (Write Mode)
If the R/W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send
commands or data.
After the communication has started and slaves have acknowledged, the master sends a
control byte defined as follows and waits for its acknowledgement:
Co
DC
0
0
0
0
0
0
CONTROL BYTE
The Co bit is the control byte MSB and defines if after this control byte will follow a single
byte sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether
the following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C =
0) or DDRAM data (D/C = 1).
Depending on state of flags Co and D/C, four writing sequences are possible:
SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a
command will follow the control byte;
SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to
be written in DDRAM will follow the control byte;
MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow
the control byte, with each single byte interpreted as a command;
MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the
control byte, with each byte interpreted as a data byte to be written in DDRAM.
Every single byte of a sequence must be acknowledged by all addressed units.
A multiple data sequence is terminated only by sending a STOP condition on the I2C bus.
When a sequence is terminated, another sequence of any type can follow or a I2C STOP
condition can be sent to close the communication.
In a single or multiple data bytes sequence, every data byte received is stored in the
DDRAM at the location specified by the current values of data pointers. Data pointers are
automatically updated after each single data byte written.
25/62
Interface
STE2007
4.3.4
Driver TxData mode (Read mode)
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If
the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 18. Communication protocol
WRITE MODE
STE2007 ACK
COMMUNICATION
I2C START
COND
SA1
1
SA2
0
A
0
1
1
1
START
R/W
SLAVE ADDRESS
STE2007 ACK
STE2007 ACK
Co D/C
SINGLE COMMAND
SEQUENCE
1
0 0 0 0 A
0 0 0 A COMMAND Byte
Control Byte
Command Byte
STE2007 ACK
STE2007 ACK
STE2007 ACK
Co D/C
MULTIPLE COMMAND
SEQUENCE
0
0 0
A
0
0
0
0
0
COMMAND Byte
A
COMMAND Byte
A
Control Byte
First Command Byte
Last Command Byte
STE2007 ACK
STE2007 ACK
Co D/C
SINGLE DATA
SEQUENCE
1
1
0
0
0
0
0
0 A
DATA Byte
A
Control Byte
Data Byte
STE2007 ACK
STE2007 ACK
STE2007 ACK
DATA Byte A
Co D/C
MULTIPLE DATA
SEQUENCE
0
1
0
0
0
0
0
0 A
DATA Byte
A
Control Byte
First Data Byte
Last Data Byte
COMMUNICATION
STOP
I2C STOP
COND
READ MODE
STE2007 ACK
MASTER ACK
I2C START
COND
I2C START
COND
STATUS BYTE READ
SEQUENCE
SA1 SA2
0
1
1
1
1
0
A
STATUS Byte
A
R/W
SLAVE ADDRESS
LR0008d
26/62
STE2007
Interface
4.4
Reading mode
STE2007 features a reading Command to transmitt data from the LCD driver to Host
Processor. After the reading command STE2007 transfers 8 bits to the Host controller:
–
Identification Byte (Command Code DBhex)
4.4.1
IIdentification byte
Identification byte is an 8 Bit code that identify the module revision Number.
Table 15. ID byte format
Bit nr
D7(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
0
0
IDB PAD IDA PAD
0
0
0
0
Figure 19. Identification byte in reading mode
STE2007
Power IC
VDDCP
VDD
VDD
VDDI
VDDI
VSS
GND
Command decoder
VSSCP
ASIC(MCU)
MCU TxData
RESET
SDA
Multi
ID
plexer
XCS
test
SCLK
Driver TxData
Auto
return
VLCD
Voltage booster
Driver side
LCD Power
Supply circuit
BaseBand side
Figure 20. Identification information
Identification Information
Send rading command (DBh)
Read status(ID data)
Send reset command
Command:E2H
27/62
Display Data RAM (DDRAM)
STE2007
5
Display Data RAM (DDRAM)
5.1
DDRAM and Page/column address circuit
The DDRAM stores pixel data for LCD. It is a 68–row (8 page by 8 bits +4) by 96–column
addressable array. D7 to D0 display data from MCU corresponds to the LCD common
direction. ”0” bit in DDRAM is a OFF–dot on display and ”1” bit in DDRAM is displayed as
ON–dot on display.
Figure 21. DDRAM vs. display on LCD
COM0
COM1
COM2
COM3
COM4
±±
D0
D1
D2
D3
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
D4
±±
DDRAM
Display on LCD
Each pixel can be selected when page address and column address are specified. The
MCU issues Page address set command to change the page and access to another page.
In DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are
valid.
The DDRAM column address is specified by Column address set command.
The specified column address is automatically incremented by +1 when a Display data write
command is entered. After the last column address (5Fh), column address returns to 00h
and page address incremented by +1. After the very last address (column=5Fh, page=8h),
both column address and page address return to 00h (column address=00h, page
address=0h).
Figure 22. Column address in normal mode
Data
Data for page address 0H to 07H
LSBit
D0
D1
D2
D3
D4
D5
D6
D7
0H
1H
0
1
2
94 95
190 191
286 287
382 383
478 479
574 575
670 671
96 97 98
2H 192 193 194
3H 288 289 290
4H 384 385 386
5H 480 481 482
6H 576 577 578
7H 672 673 674
8H 768 769 770
MSBit
Page address
766 767
862 863
5EH 5FH
02H
00H 01H
Column address
D0
D1
D2
D3
Data for page address 8H
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STE2007
Display Data RAM (DDRAM)
Figure 23. Column address in reversed mode
Data for page address 0H to 07H
Data
D0
D1
D2
D3
D4
D5
D6
D7
LSBit
95
94
190
286
382
478
574
670
766
862
0H
1H
96
191
287
383
479
575
671
767
863
98 97
194 193 192 2H
290 289 288 3H
386 385 384 4H
482 481 480 5H
578 577 576 6H
674 673 672 7H
770 769 768 8H
MSBit
Page address
5FH
02H
5EH
01H 00H
Column address
D0
D1
D2
D3
Data for page address 8H
Data can be written to the DDRAM at the same time as data is being displayed, without
causing the LCD to flicker.
Segment driver direction command can be used to reverse the relationship between the
DDRAM column address and segment output. This function is achieved writing data into
DDRAM in reverse order (from Right to left).
Table 16. Column address direction
Column
00H
01H
02H
5DH
5EH
5FH
5DH
address
Normal
Direction
SEG0
SEG1
SEG94
SEG2
_ _ _ _ _ _
_ _ _ _ _ _
SEG93
SEG2
SEG94
SEG1
SEG95
SEG0
Reverse
Direction
SEG95
SEG93
5.2
Line address circuit
The line address circuit specifies the line address relating to the COM output when the
contents of the DDRAM are displayed. The display start line that is normally the top line of
the display, can be specified by Display start line address set command.
STE2007 features Four different Multiplexing Mode to fine tune the duty ratio on the display
size:
–
–
–
–
68 Lines Display
65 Lines Display
49 Lines Display
33 Lines Display
29/62
Display Data RAM (DDRAM)
Figure 24. M68–line mode
STE2007
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
COM Output
Normal Reverse
direction direction
Line
Line
t
Normal Reverse
D3 D2 D1 D0
Address
Address
direction direction
COM66
COM65
COM64
COM0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COMS
COM66
COM65
COM64
COM63
COM62
COM61
COM60
COM59
COM58
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COMS
COM10 COM57
COM11
COM56
COM12 COM55
COM13 COM54
COM14 COM53
COM15 COM52
COM16 COM51
COM17 COM50
COM18 COM49
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
COM19
COM48
COM20 COM47
COM21 COM46
COM22 COM45
COM23 COM44
COM24 COM43
COM25 COM42
COM26 COM41
COM27
COM40
COM28 COM39
COM29 COM38
COM30 COM37
COM31 COM36
Start
Start
COM32
COM33
COM34
COM35
COM35
COM34
COM33
COM32
COM36 COM31
COM37 COM30
COM38 COM29
COM39 COM28
COM40 COM27
COM41 COM26
COM42 COM25
COM43 COM24
COM44 COM23
COM45 COM22
COM46 COM21
COM47 COM20
COM48 COM19
COM49 COM18
COM50 COM17
COM51 COM16
COM52 COM15
COM53 COM14
COM54 COM13
COM55 COM12
COM56 COM11
COM57 COM10
COM58 COM9
COM59 COM8
COM60 COM7
COM61 COM6
COM62 COM5
COM63 COM4
1
COM14
COM13
COM12
COM1
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
Page 7
Page 8
0
1
1
0
1
0
1
0
D7
D0
D1
D2
D3
COM64
COM65 COM2
COM66
COMS
COM3
40H
41H
42H
40H
41H
42H
COM1
COM0
43H
43H
Column address
00H
02H 03H 04H 05H 06H
5AH
5BH 5CH 5DH 5EH5FH
01H
59H
Display start line does not access 65th, 66th, 67th, 68th line
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
30/62
STE2007
Display Data RAM (DDRAM)
Figure 25. 65–line mode
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Normal Reverse
Line
Line
t
D3 D2 D1 D0
Address
Address
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
Start
Start
COM8
COM7
COM6
Page 7
Page 8
COM5
0
1
1
0
1
0
1
0
COM4
COM61 COM3
COM1
COM62
COM63 COM0
COM64 COM64
COM62
COM63
COM64
COM2
COM1
COM0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
31/62
Display Data RAM (DDRAM)
Figure 26. 49–line mode
STE2007
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Normal Reverse
direction direction
Line
Line
t
D3 D2 D1 D0
Address
Address
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM0
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
COM19 COM28
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
Start
Start
COM33 COM15
COM34 COM14
COM35 COM13
COM36 COM12
COM37 COM11
COM38 COM10
COM39 COM9
COM40 COM8
COM41 COM7
COM42 COM6
COM43 COM5
COM44 COM4
COM45 COM3
COM46 COM2
COM47 COM1
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COM0
COM48
Page 7
Page 8
0
1
1
0
1
0
1
0
D7
D0
D1
D2
D3
COM64 COM64
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
32/62
STE2007
Display Data RAM (DDRAM)
Figure 27. 33–line mode
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Line
Line
t
Normal Reverse
Address
D3 D2 D1 D0
Address
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10 COM21
COM11 COM20
COM12 COM19
COM13 COM18
COM14 COM17
COM15 COM16
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
Page 0
Page 1
0
0
0
0
0
0
0
1
COM10 COM22
COM11 COM21
COM12 COM20
COM13 COM19
COM14 COM18
COM15 COM17
COM16 COM16
COM17 COM15
COM18 COM14
COM19 COM13
COM20 COM12
COM21 COM11
COM22 COM10
COM23 COM9
COM24 COM8
COM25 COM7
COM26 COM6
COM27 COM5
COM28 COM4
COM29 COM3
COM16
COM17
COM18
COM15
COM14
COM13
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
COM19 COM12
0
0
0
0
1
1
0
1
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Start
Start
COM30
COM31 COM1
COM0
COM2
COM32
0
0
0
1
1
1
0
0
1
0
1
0
Page 7
Page 8
0
1
1
0
1
0
1
0
D7
D0
D1
D2
D3
COM64 COM64
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
5.3
Partial display
STE2007 feature four configuration for Partial Display function:
–
–
–
–
33 Line Partial Display
25 Line Partial display
16 Line Partial Display
9 Line Partial Display
Partial display Area location on the screen is defined by Image Location Parameter.
Image Location + Partial display area > Multiplexing rate.
33/62
Display Data RAM (DDRAM)
STE2007
Figure 28. Illustration of partial display
Display
Display
Image Location + Partial display area width <= MultiplIemxaignegLroactaetion + Partial display area width
>
When Partial Display Mode is enabled the user has to Update the Operative Voltage, Bias
Ratio and Charge Pump Setting to match the new working conditions.
5.3.1
33 Line partial display mode
Partial Display Area is composed of 33 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
–
Multiplexing Value
IL[2:0]
Figure 29. Example: Partial display 33 lines & MUX65
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Line
Line
t
D3 D2 D1 D0
Address
Normal Reverse
Address
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM0
COMS0
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
IL[2:0]
IL[2:0]
COM8
COM9
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COMS0 COMS0
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
Start
Start
COM8
COM7
COM6
Page 7
Page 8
COM5
0
1
1
0
1
0
1
0
COM4
COM61 COM3
COM62
COM63
COM2
COM1
COMS0 COM0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
43H
43H
Column address
00H
02H 03H 04H 05H 06H
5AH
5BH 5CH 5DH 5EH5FH
01H
59H
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
34/62
STE2007
Display Data RAM (DDRAM)
Figure 30. Example: Partial Display 33 lines & MUX68
ICONMODE="1"
ICONMODE="0"
D
a
a
Page address
COM Output
COM Output
Normal Reverse
direction direction
Line
Line
t
Normal Reverse
D3 D2 D1 D0
Address
Address
direction direction
COM66
COM65
COM64
COM0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COMS
COM66
COM65
COM64
COM63
COM62
COM61
COM60
COM59
COM58
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
IL[2:0]
IL[2:0]
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COMS
COM10 COM57
COM11 COM56
COM12 COM55
COM13 COM54
COM14 COM53
COM15 COM52
COM16 COM51
COM17 COM50
COM18 COM49
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
COM19
COM48
COM20 COM47
COM21 COM46
COM22 COM45
COM23 COM44
COM24 COM43
COM25 COM42
COM26 COM41
COM27 COM40
COM28 COM39
COM29 COM38
COM30 COM37
COM31 COM36
Start
Start
COM32
COM33
COM34
COM35
COM35
COM34
COM33
COM32
COM36 COM31
COM37 COM30
COM38 COM29
COM39 COM28
COM40 COM27
COM41 COM26
COM42 COM25
COM43 COM24
COM44 COM23
COM45 COM22
COM46 COM21
COM47 COM20
COM48 COM19
COM49 COM18
COM50 COM17
COM51 COM16
COM52 COM15
COM53 COM14
COM54 COM13
COM55 COM12
COM56 COM11
COM57 COM10
COM58 COM9
COM59 COM8
COM60 COM7
COM61 COM6
COM62 COM5
COM63 COM4
COM64 COM3
COM65 COM2
1
COM14
COM13
COM12
COM1
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
Page 7
Page 8
0
1
1
0
1
0
1
0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
COM1
COM0
COM66
COMS
43H
43H
Column address
00H
02H 03H 04H 05H 06H
5AH
5BH 5CH 5DH 5EH5FH
01H
59H
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
35/62
Display Data RAM (DDRAM)
STE2007
5.3.2
25 Line partial display mode
Partial Display Area is composed of 25 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
–
Multiplexing Value
IL[2:0]
Figure 31. Example: Partial display 25 lines & MUX65
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Line
Line
t
D3 D2 D1 D0
Address
Address
Normal Reverse
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
IL[2:0]
IL[2:0]
COM8
COM9
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
Start
Start
COM8
COM7
COM6
Page 7
Page 8
COM5
0
1
1
0
1
0
1
0
COM4
COM61 COM3
COM1
COM62
COM63 COM0
COM64 COM64
COM62
COM63
COM64
COM2
COM1
COM0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
IMAGE lOCATION (IL[2:0]) + Partial display Area Width (19
) <= Multiplexing Rate (40 )
hex
hex
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
36/62
STE2007
Display Data RAM (DDRAM)
5.3.3
17 Line partial display mode
Partial display area is composed of 17 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
–
Multiplexing Value
IL[2:0]
Figure 32. Partial display 17 lines
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Line
Line
t
D3 D2 D1 D0
Address
Address
Normal Reverse
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
IL[2:0]
IL[2:0]
COM8
COM9
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
Start
Start
COM8
COM7
COM6
Page 7
Page 8
COM5
0
1
1
0
1
0
1
0
COM4
COM61 COM3
COM1
COM62
COM63 COM0
COM64 COM64
COM62
COM63
COM64
COM2
COM1
COM0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11
) <= Multiplexing Rate (40
)
hex
hex
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
37/62
Display Data RAM (DDRAM)
STE2007
5.3.4
9 Line partial display mode
Partial display area is composed of 9 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
–
Multiplexing Value
IL[2:0]
Figure 33. Partial display 9 lines
ICONMODE="0"
ICONMODE="1"
D
a
a
Page address
COM Output
Normal Reverse
direction direction
COM Output
Line
Line
t
D3 D2 D1 D0
Address
Address
Normal Reverse
direction direction
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
COM1
COM2
COM3
Page 0
Page 1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
COM4
COM5
COM6
COM7
IL[2:0]
IL[2:0]
COM8
COM9
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 2
Page 3
Page 4
Page 5
Page 6
Start
Start
COM8
COM7
COM6
Page 7
Page 8
COM5
0
1
1
0
1
0
1
0
COM4
COM61 COM3
COM1
COM62
COM63 COM0
COM64 COM64
COM62
COM63
COM64
COM2
COM1
COM0
D7
D0
D1
D2
D3
40H
41H
42H
40H
41H
42H
43H
43H
Column address
5AH
5BH 5CH 5DH 5EH5FH
00H 01H 02H 03H 04H 05H 06H
59H
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11
) <= Multiplexing Rate (40 )
hex
hex
S
E
G
0
S
E
G
S
E
G
1
S
E
G
S
E
G
2
S
E
G
S
E
G
3
S
E
G
S
E
G
4
S
E
G
S
E
G
5
S
E
G
S
E
G
6
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
S
E
G
Normal
Direction
SEG
Output
89 90 91 92 93 94 95
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Reverse
Direction
95 94 93 92 91 90 89
38/62
STE2007
Display Data RAM (DDRAM)
5.4
Command parameters default configuration
Table 17. Command parameters default configuration
Status
Driver status
After Power On
After HW Reset
After SW Reset
Description
MCU TxData–mode
Power Saver Mode
All Pixel On
OFF
MCU TxData–mode
Power Saver Mode
All Pixel On
OFF
MCU TxData–mode
Power Saver Mode
All Pixel On
OFF
Power saver mode
Display mode
Inversion
Display
OFF
OFF
OFF
Frame memory
Page address
Random
0hex
No change
0hex
No change
0hex
Columns address
Display start line
Segment drivers direction
Common drivers direction
VOR - Voltage range
Electronic volume
Power control register
ID byte
0hex
0hex
0hex
0hex
0hex
0hex
Normal
Normal
4hex
Normal
Normal
4hex
Normal
Normal
4hex
90hex
90hex
90hex
Booster OFF
0hex
Booster OFF
0hex
Booster OFF
0hex
IDA/IDB Pads
Charge pump
5x
5x
5x
Bias Ratio
1/10
1/10
1/10
VLCD Temperature Comp.
N-Line inversion
Multiplexing rate
Refresh rate
0ppm
0ppm
0ppm
Frame Inv.
1/68
Frame Inv.
1/68
Frame Inv.
1/68
80Hz
80Hz
80Hz
Image location
Icon mode
0hex
0hex
0hex
Disabled
Disabled
Disabled
39/62
Instruction setups
STE2007
6
Instruction setups
6.1
Initialization (power on sequence)
Power ON
Reset status
V0-Voltage Range (**H)
Electronic volume (**H)
Power saver OFF (Display all points OFF (A4H))
Power control set (2FH)
6.2
Display data writing sequence
Page address set (B*H)
Column address set Upper 3-bit address (1*H)
Column address set Lower 4-bit address (0*H)
Display data write
This command is need-
ed only at 1st time after
initialization.
Display ON (AFH)
6.3
Power off
Optional Status
!RES Pin="Low Level"
min.20ms
VDD - GND Power OFF
VDDI - GND Power OFF
Power Saver Status or Booster OFF Status
min. 0ms
!RES Pin="Low Level"
VDD - GND Power OFF
VDDI - GND Power OFF
40/62
STE2007
Power on/power off timing sequence
7
Power on/power off timing sequence
Figure 34 shows the timing diagram for power on/power down sequences.
Figure 34. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI
tp1 > 0
tp1 > 0
VDDI
VDD
tpi >0µs
tpi >0µs
Inputs
High-±
High-±
Outputs
tcs >0µs
tcs >0µs
tp2 >0µs
!CS
t
t
PWROFF1 >0 ms
PWROFF2 >20ms
!RES
trs = max. 5µs
INTERNAL
RESET
Trs = max. 5µs
Reset State
Reset State
XCS,SDAIN,XRES can become ”High” simultaneously with VDDI (tcs>0,tpi>0;tp2>0).
trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph)
tPWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status
tPWROFF2>20ms must be considered when driver is in Normal Working Condition
VDDI, VDD and VDD_CP can come up/go down in any sequence
VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the
driver is forced in reset state.
If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24)
Figure 35. Timing for phone’s power on sequence when VDDI Up before VDD
tp1 < 0
tp1 < 0
VDDI
VDD
tpi >0µs
tpi >0µs
SDAIN
High-±
High-±
SDAOUT
tcs >0µs
tcs >0µs
tp2 >0µs
!CS
t
t
PWROFF1 >0 ms
PWROFF2 >20ms
!RES
trs = max. 5µs
INTERNAL
RESET
Trs = max. 5µs
Reset State
Reset State
41/62
Power on/power off timing sequence
STE2007
Table 18. Instruction Set
Command
Code
Function
(D/C) D7 D6 D5 D4 D3 D2 D1 D0 Hex
0
1
AE LCD display
AF 0: OFF, 1: ON
Display ON/OFF
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
A6 LCD display
Display
normal/reverse
A7 0: normal, 1: reverse
0
1
A4 LCD display
Display all points
ON/OFF
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
A5 0: normal display, 1: all points ON
Page address set
address
address
Sets the DDRAM page address
Column address set
upper 3–bit address
*
Sets the DDRAM column address
Column address set
lower 4–bit address
0
0
0
0
0
1
0
0
address
Sets the DDRAM display start line
address
Display start line
address set
address
Sets the correspondence between
0
1
A0 the DDRAM column address and
Segment driver
direction
0
0
1
1
0
1
1
0
0
0
0
0
*
0
*
the SEG driver output.
A1
0:Normal, 1: reverse
Sets the correspondence between
the DDRAM line address and the
COM driver output.
0
1
Common driver
direction select
*
0: normal, 1: reverse
Display data write
1
0
Write data
Writes to the DDRAM
Self Test/Identification
data reading
1
0
1
0
0
1
1
1
0
1
1
DB Identification byte
Operating
mode
Sets the on–chip power supply
circuit operating mode
Power control set
0
0
0
1
0
VO-Range
0
0
0
1
0
0
1
0
VO-Range
Sets the electronic volume value
Sets the electronic volume value
Electronic volume
Electronic volume value
Compound command of Display
OFF and Display-all-points-ON
Power saver
–
–
–
–
–
–
–
–
–
Reset
NOP
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
E2 Internal reset
E3 Non–operation
E1
VOP
Sets the VLCD
VOP[7:0]
0
*
0
*
1
*
1
*
1
*
0
0
0
38
SET VLCD Slope in temperature
Termal Compensation
Thermal
Comp
0
42/62
STE2007
Power on/power off timing sequence
Table 18. Instruction Set (continued)
Command
Code
Function
(D/C) D7 D6 D5 D4 D3 D2 D1 D0 Hex
0
0
0
0
0
*
0
*
1
*
1
*
1
*
1
*
0
1
3D
Sets the Charge Pump Mux Factor
Charge Pump
Refresh Rate
Charge
Pump
1
*
1
*
1
*
0
*
1
*
1
*
1
1
EF
Sets the Display Refresh
Frequency
Refersh
Rate
Bias ratio
0
0
0
0
0
0
0
1
*
0
0
*
1
1
1
0
0
1
Bias Ratio
Sets the VLCD
1
0
1
AD
AC
N-line Inversion
Number of Lines
Image Location
F1
0
N-Line Inversion
1
1
*
1
0
*
1
0
*
0
1
*
Mux Rate
1
1
0
0
SET Initial Row on Display
*
IL[2:0]
Ico
n
Icon Mode
0
1
1
1
1
1
0
0
0
0
1
*
0
*
1
*
0
*
1
*
0
*
0
*
1
*
A9
Reserved for STM (STM Test
Mode)
STM TEST MODE1
Reserved for STM (STM Test
Mode)
STM TEST MODE2
STM TEST MODE3
STM TEST MODE4
STM TEST MODE5
STM TEST MODE6
STM TEST MODE7
STM TEST MODE8
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
AA
AB
A8
FF
FC
FE
FD
Reserved for STM (STM Test
Mode)
Reserved for STM (STM Test
Mode)
Reserved for STM (STM Test
Mode)
Reserved for STM (STM Test
Mode)
Reserved for STM (STM Test
Mode)
Reserved for STM (STM Test
Mode)
* = Disabled bits.
43/62
Commands
STE2007
8
Commands
8.1
Display on/off
This command turns the display ON and OFF
Table 19. Display on/ofF
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
1
0
1
0
1
1
1
0
1
AE
AF
Display OFF
Display ON
When the Display OFF command is executed in the Display all points ON mode, Power
saver mode is entered. See the section on the Power saver for details.
8.2
Display normal/reverse
This command can reverse the lit and unlit without overwriting the contents of the DDRAM.
Table 20. Display normal/reverse
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
Normal:DDRAM Data ”H”=LCD ON
voltage
0
1
0
1
0
0
1
1
0
A6
Reverse:DDRAM Data ”L”=LCD ON
voltage
0
1
A7
8.3
Display all points on/off
This command makes it possible to force all display points ON regardless of the content of
the DDRAM. Even when this is done, the DDRAM contents are maintained. This command
takes priority over the Display normal/reverse command.
Table 21. Display all points ON/OFF
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
1
0
1
0
0
1
0
0
1
A4
A5
Normal Display Mode
Display All Points ON
When the Display all points ON command is executed when in the Display OFF mode,
Power saver mode is entered. See the section on the Power Saver for details.
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STE2007
Commands
8.4
Page address set
This command specifies the page address of the DDRAM.
Specifying the page address and column address enables to access a desired bit of the
DDRAM. After the last column address (5FH), page address is incremented by +1. After the
very last address (column = 5FH, page = 8H), page address return to 0H.
Table 22. Page address set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
B0
B1
B2
:
0H
1H
2H
:
:
1
0
0
0
B8
8H
8.5
Column address set
This command specifies the column address of the DDRAM. The column address is split
into two sections (the upper 3–bits and lower 4–bits) when it is set.
Each time the DDRAM is accessed, the column address automatically increments by +1,
imaging it possible for the MCU to continuously access to the display data. After the last
column address (5FH), column address returns to 00H.
Table 23. Column address set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
0
0
0
1
0
*
A6
A2
A5
A1
A4
A0
Upper bit address
Lower bit address
A3
* Disabled bit
(D/C)
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
.
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
1
0
1
0
00H
01H
02H
.
.
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
5EH
5FH
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Commands
STE2007
8.6
Display start line address set
This command is used to specify the display start line address of the DDRAM.
If the display start line address is changed dynamically using this command, then screen
scrolling, page swapping can be performed.
Table 24. Display start line address set
(D/C) D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
0
:
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
1
0
1
0
40
41
42
0H
1H
2H
:
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
7E
7F
3EH
3FH
Display start line assress con be used in partial dispaly mode to relocate the partial display
window on the screen.
Display start line + Partial Display area with must be smaller or equal to the number of line
selected.
8.7
Segment driver direction select
This command can reverse the correspondence between the DDRAM column address and
the segment driver output.
Table 25. Segment driver direction select
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
1
0
1
0
0
0
0
0
1
A0
A1
Normal
Reverse
8.8
Common driver direction select
This command can reverse the correspondence between the DDRAM line address and the
common driver output.
Table 26. Common driver direction select
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
1
0
0
0
1
*
*
*
*
*
*
Normal
Reverse
* Disabled bit
46/62
STE2007
Commands
8.9
Display data write
This command writes 8–bit data to the specified DDRAM address. Since the column
address is automatically incremented by +1 after each write, the MCU can continuously
write multiple–word data.
Table 27. Display data write
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
1
Write Data
8.10
Data reading from driver (Driver TxData–mode)
These commands set SDAOUT to Driver TxData–mode and enable to read the identification
byte.
Table 28. ID Byte
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
1
0
1
0
0
1
1
0
0
0
1
0
1
0
DB
Reads ID byte
Pad Default
IDB
IDA
8.11
Power Control Set
This command sets the on–chip power supply function ON/OFF.
Table 29. Power Control Set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
28
29
2A
2B
2C
2D
2E
Booster : OFF
Voltage Regulator:OFF
Voltage Follower : OFF
Booster : ON
0
1
1
1
2F
Voltage regulator : ON
Voltage follower : ON
47/62
Commands
STE2007
8.12
VLCD set
The LCD Voltage VLCD at reference temperature (TA = 25°C) can be set using the Voltage
Range V0R, Electronic Volume EV and VOP registers content according to the following
formula:
VLCD (T=TA) = ( V0P[7:0] + EV[4:0] - 16 + 32 · V0R[2:0]) · B + VLCDMIN
with the following values:
Symbol
Value
Unit
Note
B
VLCDMIN
TA
0.04
3
V
V
Single Voltage Step
25
°C
Room Temperature
For information on VLCD thermal compensation see PAR. 8.18 .
Figure 36.
Vout
13.20V
EV[3:0]
1Fh
12h
11h
10h
B
00h
VOP[7:0]*B+V-OR
3V
00h
FFh
Figure 37.
V0R[2:0]
EV[4:0]
Thermal
Compensation
VOUT
DAC
Step: 40mV
Range 3V-13.20V
8.12.1
V0R - Voltage Range Set
This command sets a value of the Voltage Range.
Table 30. V0R – Voltage Range
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
0
0
1
0
0
V0R - Voltage Range
Command Identifier + Data Field
48/62
STE2007
Commands
Table 31. V0R
V0R
Value
(D/C) D7
D6
D5
D4
D3
D2
D1
D0
HEX
32 · V0R · B + VLCDMIN
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20
21
22
23
24
25
26
27
0
1
2
3
4
5
6
7
3.00 V
4.28 V
5.56 V
6.84 V
8.12 V (Default)
9.40 V
10.68 V
11.96 V
8.12.2
VOP set
Contrast Setting Adjustment .
Table 32. VOP Set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
0
1
1
1
0
0
0
0
1
E1
Command Identifier
Data Field
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0
Table 33. VOP
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 HEX
VOP Adjustment
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
1
:
0
1
0
:
00
01
02
:
0 Step (Default)
+1 Step
+2 Step
:
0
1
1
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
0
:
1
0
1
:
7F
80
81
:
+127 Step
0 Step
-1 Step
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
FD
FE
FF
-125 Step
-126 Step
-127 Step
49/62
Commands
STE2007
8.12.3
Electronic volume
This command sets a value of electronic volume EV for the VLCD voltage regulator, to
adjust the contrast of LCD panel display (End User).
Table 34. Electronic volume
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
0
0
Electronic Volume Value
Command Identifier + Data Field
Table 35. EV
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Hex
EV Value
VLCD voltage
0
0
0
:
1
0
0
0
0
0
0
0
0
0
0
0
:
0
0
1
0
1
0
80
81
82
:
0 Step
low
1 Step
2 Step
:
16 Step (Default)
:
:
:
0
:
1
0
0
:
0
0
90
:
0
0
1
1
1
1
1
1
1
1
0
1
9E
9F
30 Step
31 Step
high
8.13
Power saver mode
If the display all points ON command is executed when the display is in display OFF mode,
power saver mode is entered. This mode stops every operation of the LCD display system.
Figure 38. Power saver mode
Command
Effect
Power saver (Display OFF & Display all points ON
Power saver mode
Powersaver OFF (Display all points OFF)
Power saver mode canceled
The internal states in power saver mode are as follows:
–
–
–
The oscillation circuit is stopped
The LCD power supply circuit is stopped
The LCD driver circuit is stopped and segment/common driver outputs to the Vss
level
–
The display data and operation mode before execution of the Power saver are
held, and the MCU can access to the DDRAM and internal registers.
50/62
STE2007
Commands
8.14
Reset
When this command is issued, the driver is initialized.This command doesn’t change
DDRAM content.
Table 36. Reset
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
E2
Function
0
1
1
1
0
0
0
1
0
Command Identifier
8.15
NOP
Non–operation command.
Table 37. NOP
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
E3
Function
0
1
1
1
0
0
0
1
1
Command Identifier
8.16
Image Location
Image Location Command
Table 38. Image Location
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
Function
0
0
1
*
0
*
1
*
0
*
1
*
1
0
0
AC
Command Identifier
Data Field
IL2
IL1
IL0
Table 39. Image Location
IL2
IL1
IL0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 Lines
8 Lines
16 Lines
24 Lines
32 Lines
48 Lines
56 Lines
64 Lines
51/62
Commands
STE2007
8.17
Bias Ratio
It is possible to select different Bias Ratio.
Table 40. Bias Ratio
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command Identifier + Data Field
0
0
0
1
1
0
BR2 BR1 BR0
Table 41. BIAS Ratio
BR2
BR1
BR0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bias Ratio =1/10 - 81 Lines
Bias Ratio = 1/9 - 65 Lines
Bias Ratio =1/8 - 49 Lines
Bias Ratio = 1/7 - 33 Lines
Bias Ratio =1/6 - 25 Lines
Bias Ratio = 1/5 - 17 Lines
Bias Ratio =1/4 - 9 Lines
Not Used
Figure 39. Bias levels Generator
BR=001
BR=011
BR=000
BR=010
VLCD
VLCD
VLCD
VLCD
R
R
R
R
R
R
9
8
9
7
8
6
7
·VLCD
10
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
R
R
3 R
R
8
7
9
6
8
5
7
·VLCD
10
6 R
5 R
R
4 R
R
2
2
9
2
8
2
7
·VLCD
10
R
1
1
9
1
8
1
7
·VLCD
10
R
R
R
R
VSS
VSS
VSS
VSS
BR=101
BR=100
BR=110
VLCD
VLCD
VLCD
R
R
R
R
5
4
5
3
4
·VLCD
6
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
·VLCD
R
R
1 R
R
4
3
5
2
4
·VLCD
6
2 R
4 R
R
2
2
5
2
4
·VLCD
6
R
1
1
5
1
4
·VLCD
6
R
R
R
VSS
VSS
VSS
52/62
STE2007
Commands
8.18
Temperature Compensation
Its is possible to select different VLCD temperature compensation Coefficients.
Table 42. VLCD Temperature Compensation
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
0
0
1
1
1
0
0
0
38
Command Identifier
Thermal
Compensation
0
*
*
*
*
*
Data Field
TC
Temperature Compensation Formula:
VLCD(T) = VLCD(TA) · [1 + (T(°C) - TA) · TC]
TC = Temperature Compensation Coefficients
T(°C) = Temperature
VLCD(TA) = LCD Voltage at TA Temperature (Room Temperature)
Table 43. TC
TC2
TC1
TC0
TC Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TC= 0 PPM
TC= -300 PPM
TC= -600 PPM
TC= -900 PPM
TC= -1070 PPM
TC= -1200 PPM
TC= -1500 PPM
TC= -1800 PPM
8.19
Charge Pump Multiplication Factor
It is possible to select different Charge Pump Multiplication Factors.
Table 44. Charge Pump Setting
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
3D
Function
0
0
0
*
0
*
1
*
1
*
1
*
1
*
0
1
Command Identifier
Data Field
CP1 CP0
53/62
Commands
STE2007
Table 45. Charge Pump Multiplication Factor
CP1
CP0
Function
0
0
1
1
0
1
0
1
5 x
4 x
3 x
Not Used
8.20
Refresh Rate
It is possible to select different Refresh Rate.
Table 46. Refresh rate setting
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
Function
0
0
1
*
1
*
1
*
0
*
1
*
1
*
1
1
EF
Command Identifier
Data Field
RR1 RR0
Table 47. Refresh Rate
RR1
RR0
Function
0
0
1
1
0
1
0
1
80 Hz
75 Hz
70 Hz
65 hz
8.21
Icon mode
Icon Mode
–
–
0: Icon Mode Disabled
1: Icon Mode Enabled
Table 48. Icon Mode
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
1
1
1
1
0
0
ICON
Command Identifier
8.22
N- Line inversion
N-line Inversion Function.
Table 49. N-Line Inversion
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0 HEX
AD
Function
0
0
1
*
0
*
1
0
1
1
0
1
Command Identifier
Data Field
F1
NL4 NL3 NL2 NL1 NL0
54/62
STE2007
Pad coordinates
Table 50. N-Line
F1
NL4 NL3 NL2 NL1 NL0
Function
N row
*
0
1
*
0
*
0
*
0
*
0
*
0
*
N-line inversion disabled (default)
XOR function disabled
XOR function enabled
N-line inversion enabled
N-line inversion enabled
:
*
*
*
*
*
0
0
:
0
0
:
0
0
:
0
1
:
1
0
:
2
3
*
:
:
*
1
1
1
1
1
N-line inversion enabled
32
The XOR function defines the polarity as the result of the logical XOR between the N-Line
and the frame polarity.
8.23
Number of lines
Multiplexing Rate setting command.
Table 51. Number of lines
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
1
0
1
0
M2
M1
M0
Command Identifier + Data Field
Table 52. Multiplexing rate
M2
M1
M0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
68 Lines (Default)
65 Lines
49 Lines
33 Lines
33 Lines Partial Display
25 Lines Partial Display
17 Lines Partial Display
9 Lines Partial Display
9
Pad coordinates
See Table 53: Pad coordinates and Table 55: Alignment marks coordinates.
55/62
Pad coordinates
STE2007
Table 53. Pad coordinates
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
R16
R14
R12
R10
R8
1
-2632.5
-2587.5
-2542.5
-2497.5
-2452.5
-2407.5
-2362.5
-2317.5
-2272.5
-2227.5
-2182.5
-2137.5
-2092.5
-2047.5
-2002.5
-1957.5
-1912.5
-1867.5
-1822.5
-1777.5
-1732.5
-1687.5
-1642.5
-1597.5
-1552.5
-1507.5
-1462.5
-1417.5
-1372.5
-1327.5
-1282.5
-1237.5
-1192.5
-1147.5
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-1102.5
-1057.5
-1012.5
-967.5
-922.5
-877.5
-832.5
-787.5
-742.5
-697.5
-652.5
-607.5
-562.5
-517.5
-472.5
-427.5
-382.5
-337.5
-292.5
-247.5
-202.5
-157.5
-112.5
112.5
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
2
3
4
5
R6
6
R4
7
R2
8
R0
9
C0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
157.5
202.5
247.5
292.5
337.5
382.5
427.5
472.5
517.5
562.5
56/62
STE2007
Pad coordinates
Table 53. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
607.5
652.5
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
C94
C95
R1
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
2182.5
2227.5
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-514.35
-450.0
-405.0
-360.0
-315.0
-270.0
-225.0
-180.0
-135.0
-90.0
697.5
2272.5
742.5
R3
2317.5
787.5
R5
2362.5
832.5
R7
2407.5
877.5
R9
2452.4
922.5
R11
R13
R15
R17
R19
R21
R23
R25
R27
R29
R31
R33
R35
R37
R39
R41
R43
R45
R47
R49
R51
R53
R55
R57
R59
R61
R63
R65
2497.5
967.5
2542.5
1012.5
1057.5
1102.5
1147.5
1192.5
1237.5
1282.5
1327.5
1372.5
1417.5
1462.5
1507.5
1552.5
1597.5
1642.5
1687.5
1732.5
1777.5
1822.5
1867.5
1912.5
1957.5
2002.5
2047.5
2092.5
2137.5
2587.5
2632.5
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2831.85
2632.5
-45.0
0.0
45.0
90.0
135.0
180.0
225.0
270.0
315.0
360.0
405.0
450.0
514.35
514.35
514.35
2587.5
2542.0
57/62
Pad coordinates
STE2007
Table 53. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
R67
TEST3
TEST4
VSS_AUX
VSS_AUX
VSS_AUX
VSS_AUX
N_RES
N_CS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
2497.5
2376.0
2304.0
1944.0
1872.0
1800.0
1728.0
1584.0
1512.0
1368.0
1296.0
1224.0
1152.0
1080.0
1008.0
936.0
514.35
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDD
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
-720.0
-792.0
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
517.5
514.35
514.35
514.35
514.35
450.0
405.0
360.0
315.0
270.0
225.0
180.0
135.0
90.0
-864.0
-936.0
-1008.0
-1080.0
-1224.0
-1296.0
-1368.0
-1440.0
-1512.0
-1584.0
-1656.0
-1728.0
-1872.0
-1944.0
-2016.0
-2088.0
-2160.0
-2304.0
-2376.0
-2497.5
-2542.5
-2587.5
-2632.5
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
VDD
VDD
T2
VDD
T1
VDD
T0
VDD
VSS
VDD_CP
VDD_CP
VLCD_SNS
VLCD
VLCD
VLCD
VLCD
TEST4
TEST5
R66
VSS
VSS
VSS_LCD
VSS_LCD
VSS_LCD
VSS_CP
VSS_CP
VSS_CP
DC
864.0
792.0
720.0
648.0
576.0
432.0
SDAOUT
SDIN
360.0
R64
288.0
R62
SDOUT
SCLK
216.0
R60
144.0
R58
VREF_BUFF
VSS_AUX
SEL1
72.0
R56
-72.0
R54
-144.0
-216.0
-288.0
-360.0
-432.0
-504.0
-576.0
R52
SEL0
R50
SA1
R48
SA0
R46
IDB
R44
IDA
R42
OSC_IN
R40
45.0
58/62
STE2007
Pad coordinates
Table 53. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
R38
R36
R34
R32
R30
R28
209
210
211
212
213
214
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
0.0
R26
R24
R22
R20
R18
215
216
217
218
219
-2831.85
-2831.85
-2831.85
-2831.85
-2831.85
-270.0
-315.0
-360.0
-405.0
-450.0
-45.0
-90.0
-135.0
-180.0
-225.0
59/62
Chip mechanical drawing
STE2007
10
Chip mechanical drawing
Table 54. Mechanical dimensions
Parameter
Dimensions
Wafer Thickness
500µm
5.92 mm x 1.29 mm
28µm X 89 µm X 15
35µm X 96µm
45µm
Die Size (X x Y)
Bumps Size on Columns and Segments Side
Pad Size on Columns and Segments Side
Bumps Pitch on Columns and Segments Side
Bumps Size on Interfaces Side
Pad Size on Interfaces Side
55µm X 73µm X 15
64 µm X 82 µm
72µm
Bumps Pitch on Interfaces Side
Spacing between Bumps
17µm
Table 55. Alignment marks coordinates
MARKS
X
Y
Mark1
Mark2
Mark3
Mark4
Mark5
-2834.55
2834.55
-2834.55
2834.55
2205.0
517.05
517.05
-517.05
-517.05
517.05
Figure 40. Alignment marks dimensions
35 µm
85 µm
60/62
STE2007
Ordering information
11
Ordering information
Table 56. Order codes
Part number
Type
Bumped Dice on Waffle Pack
STE2007DIE2
12
Revision history
Table 57. Document revision history
Date
Revision
Changes
09-Nov-2005
1
Initial release.
Adjustments in Abs Max ratings regarding ESD in Table 7.
13-Mar-2006
12-Dec-2006
2
3
Adjustments on DC & AC charactersitics (VLCD, I(VDDI) in Table 8 &
FFRAME in Table 9)
Reviewed operating temperature range in Chapter 3: Electrical
characteristics.
61/62
STE2007
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