STEVAL-ISA051V1 [STMICROELECTRONICS]
Complete DDR2/3 memory power supply controller evaluation board based on the PM6670S; 完整的DDR2 / 3内存供电的基础上PM6670S控制器评估板型号: | STEVAL-ISA051V1 |
厂家: | ST |
描述: | Complete DDR2/3 memory power supply controller evaluation board based on the PM6670S |
文件: | 总4页 (文件大小:152K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STEVAL-ISA051V1
Complete DDR2/3 memory power supply controller
evaluation board based on the PM6670S
Data Brief
Features
■ 4.5 V to 28 V input voltage range
■ 0.9 V, 1ꢀ voltage reference
■ 1.8 V (DDR2) or 1.5 V (DDR3) fixed output
voltages
■ 0.9 V to 2.6 V adjustable output voltage
■ 1.237 V 1ꢀ reference voltage available
■ Very fast load transient response
■ Constant on-time loop control
■ No R
current sensing using the R
DS(on)
SENSE
of the low-side MOSFETs
STEVAL-ISA051V1
■ Negative current limit
■ Latched OVP, UVP and thermal shutdown
■ Fixed 3 ms soft-start
The device is fully compliant with system sleep
states S3 and S4/S5, providing LDO output high
impedance in suspend-to-RAM and tracking
discharge of all outputs in suspend-to-disk.
■ Selectable pulse-skipping at light load
■ Selectable no-audible (33 kHz) pulse-skip
mode
■ All ceramic output capacitors application
supported
■ Output voltage ripple compensation
Description
This evaluation board is based on the PM6670S
and represents a complete DDR2/3 power supply
regulator for portable applications designed to
meet JEDEC specifications. It integrates a
constant on-time (COT) buck controller, a 2 Apk
sink/source low drop-out regulator and a 15 mA
low noise buffered reference. The COT
architecture assures fast transient response
supporting both polymeric and ceramic output
capacitors. An embedded integrator control loop
compensates the DC voltage error due to the
output ripple. The 2 Apk sink/source linear
regulator provides the memory termination
voltage with fast load transient response.
February 2008
Rev 1
1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4
Circuit schematic
STEVAL-ISA051V1
1
Circuit schematic
Figure 1.
Schematic
1
1
1
1
1
3
1
1
2
1
+
3
1
1
2
1
1
1
8 S 1 _ N E
3 _ D N G D A
1 H P _ T E S E
2 _ D N G D A
C C V A
D N G _ T T V
T T V
N I _ O D L
F E R T T V
G C S D
8 S 1 _ 1 G P
5 0 S 1 _ 1 G P
2
7 3
8 3
9 3
0 4
1 4
2 4
3 4
4 4
5 4
6 4
7 4
8 4
4 2
3 2
2 2
1 2
0 2
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 _ 5 0 S 1 _ _ 1 N I
1 _ 5 0 S 1 _ _ 1 N I
V
V
2 _ 5 0 _ S 1 _ W S V
1 _ 5 0 _ S 1 _ W S V
2 _ 5 0 S 1 _ 1 D N G D S
1 _ 5 0 S 1 _ 1 D N G D S
5 0 S 1 _ 1 B F V
5 0 S 1 _ P M O C
5 0 S 1 _ S S
8 S 1 _ S S
2
1
B F _ T T V
C C V
3
1
3
1
C C V A V
1
C C V A V
1
1
1
2
1
1
3
1
2/4
STEVAL-ISA051V1
Revision history
2
Revision history
Table 1.
Date
11-Feb-2008
Document revision history
Revision
Changes
1
Initial release.
3/4
STEVAL-ISA051V1
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