STL15DN4F5 [STMICROELECTRONICS]
Dual N-channel 40 V, 8 mΩ, 15 A PowerFLAT?(5x6) double island, STripFET? V Power MOSFET; 双N沟道40 V， 8毫欧， 15 A PowerFLAT ？ （ 5×6 ）双岛的STripFET ？ V功率MOSFET
| 型号： | STL15DN4F5 |
| 厂家： | 
ST |
| 描述： | Dual N-channel 40 V, 8 mΩ, 15 A PowerFLAT?(5x6) double island, STripFET? V Power MOSFET |
| 文件： | 总12页 (文件大小：778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STL15DN4F5
Dual N-channel 40 V, 8 mΩ, 15 A
PowerFLAT™(5x6) double island, STripFET™ V Power MOSFET
Features
RDS(on)
max.
Type
VDSS
ID
STL15DN4F5
40 V
9 mΩ
15 A (1)
1. The value is rated according Rthj-pcb
■ R
* Q industry benchmark
DS(on)
g
■ Extremely low on-resistance R
DS(on)
■ Very low switching gate charge
■ Low gate drive power losses
PowerFLAT™ (5x6)
Double island
Application
■ Switching applications
– Automotive
Figure 1.
Internal schematic diagram
Description
The device is a dual N-channel STripFET™ V.
This Power MOSFET technology is among the
latest improvements, which have been especially
tailored to achieve very low on-state resistance
providing also one of the best-in-class figure of
merit (FOM).
Table 1.
Device summary
Order code
Marking
Package
Packaging
PowerFLAT™(5x6)
Double island
STL15DN4F5
15DN4F5
Tape and reel
September 2010
Doc ID 17739 Rev 1
1/12
www.st.com
12
Contents
STL15DN4F5
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
Doc ID 17739 Rev 1
STL15DN4F5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
40
20
Unit
VDS
VGS
Drain-source voltage (VGS = 0)
Gate-source voltage
V
V
Drain current (continuous) at TC = 25 °C
(silicon limited)
(1)
ID
60
A
(2)
ID
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100°C
Drain current (pulsed)
15
10
A
A
(2)
ID
(3)
IDM
60
A
(1)
PTOT
Total dissipation at TC = 25°C
Total dissipation at TC = 25°C, t < 10 sec
Derating factor
60
W
(2)
PTOT
4.3
0.03
W
W/°C
TJ
Operating junction temperature
Storage temperature
-55 to 175
°C
Tstg
1. The value is rated according Rthj-c
2. The value is rated according Rthj-pcb
3. Pulse width limited by safe operating area
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) (steady state)
Thermal resistance junction-ambient
2.5
35
°C/W
°C/W
(1)
Rthj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec (see Figure 3)
Table 4.
Symbol
Avalanche data
Parameter
Value
Unit
Not-repetitive avalanche current,
(pulse width limited by Tj max.)
IAV
7.5
A
Single pulse avalanche energy
(1)
EAS
150
mJ
(starting TJ = 25 °C, ID = IAV , VDD = 24 V)
1. Tested at wafer level only.
Doc ID 17739 Rev 1
3/12
Electrical characteristics
STL15DN4F5
2
Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5.
Symbol
On/off states
Parameter
Test conditions
Min. Typ.
Max. Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 250 µA, VGS= 0
40
V
V
DS = Max rating,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = Max rating @125 °C
10
Gate body leakage current
(VDS = 0)
IGSS
VGS = 20 V
±100
nA
VGS(th)
RDS(on)
VDS= VGS, ID = 250 µA
VGS= 10 V, ID= 7.5 A
Gate threshold voltage
2
4
9
V
Static drain-source on
resistance
8
mΩ
Table 6.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
1550
230
25
pF
pF
pF
VDS = 25 V, f = 1 MHz
VGS = 0
Output capacitance
-
-
-
-
Reverse transfer
capacitance
Qg
Qgs
Qgd
VDD= 20 V, ID = 15 A
VGS = 10 V
Total gate charge
Gate-source charge
Gate-drain charge
25
6
nC
nC
nC
5.5
(see Figure 14)
4/12
Doc ID 17739 Rev 1
STL15DN4F5
Electrical characteristics
Min. Typ. Max. Unit
Table 7.
Switching times
Parameter
Symbol
Test conditions
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
18
45
32
5
ns
ns
ns
ns
V
DD = 20 V, ID = 7.5 A,
RG = 4.7 Ω, VGS = 10 V
-
-
Turn-off delay time
Fall time
(see Figure 13)
Table 8.
Symbol
Source drain diode
Parameter
Test conditions
Min Typ. Max Unit
ISD
Source-drain current
-
-
-
15
60
A
A
V
(1)
Source-drain current (pulsed)
Forward on voltage
ISDM
(2)
ISD = 15 A, VGS = 0
1.1
VSD
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 15 A,
30
35
ns
nC
A
Qrr
di/dt = 100 A/µs,
VDD = 32 V, Tj = 150 °C
-
2.2
IRRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %
Doc ID 17739 Rev 1
5/12
Electrical characteristics
STL15DN4F5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM07129v1
I
D
(A)
Tj=175°C
Tc=25°C
Single pulse
100
10ms
10
1
100ms
1s
0.1
0.01
10
VDS(V)
0.1
1
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
AM07130v1
AM07131v1
I
D
(A)
I
D
(A)
V
GS=10V
VDS=0.4V
35
35
6V
5V
30
30
25
20
15
25
20
15
10
10
5
0
5
0
4V
DS(V)
0.2
2
0.8
V
8
VGS(V)
0
0.4
0.6
0
4
6
Figure 6.
Normalized B
vs temperature Figure 7.
Static drain-source on resistance
VDSS
AM07132v1
AM07133v1
BVDSS
R
DS(on)
(norm)
(mOhm)
VGS=10V
1.15
1.10
1.05
1.00
0.95
8.6
8.2
7.8
0.90
7.4
7.0
0.85
0.80
2
4
6
8
10 12 14
-75 -50
-25
25 50 75
TJ(°C)
150
ID(A)
0
0
100 125
6/12
Doc ID 17739 Rev 1
STL15DN4F5
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
AM07135v1
AM07134v1
V
GS
C
(V)
(pF)
V
DD=20V
=15A
I
D
10
Ciss
Coss
Crss
8
6
4
1000
100
10
2
0
10
20
0.1
25
Qg(nC)
VDS(V)
0
5
15
1
10
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature temperature
AM07136v1
AM07137v1
V
GS(th)
RDS(on)
(norm)
(norm)
2.0
1.00
1.5
1.0
0.8
0.6
0.4
0.5
0
-75 -50
-75 -50
-25
-25
0
25 50 75
T
J(°C)
0
25 50 75
TJ(°C)
100
125
150
100
125 150
Figure 12. Source-drain diode forward
characteristics
AM07138v1
VSD
(V)
TJ=-55°C
0.9
0.8
0.7
0.6
TJ=25°C
TJ=175°C
0.5
0.4
0
2
4
6
8
10 12 14
ISD(A)
Doc ID 17739 Rev 1
7/12
Test circuits
STL15DN4F5
3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
2200
3.3
µF
RL
µF
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
D.U.T.
VG
VD
RG
VGS
2200
µF
D.U.T.
2.7kΩ
47kΩ
PW
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped inductive load test
circuit
L
A
A
A
B
D
FAST
DIODE
L=100µH
VD
G
2200
µF
D.U.T.
B
3.3
µF
VDD
S
3.3
µF
1000
µF
B
VDD
25
Ω
ID
D
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
ton
toff
tdoff
V(BR)DSS
tr
tf
tdon
VD
90%
10%
90%
IDM
10%
VDS
ID
0
0
VDD
VDD
90%
VGS
10%
AM01472v1
AM01473v1
8/12
Doc ID 17739 Rev 1
STL15DN4F5
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and products status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 17739 Rev 1
9/12
Package mechanical data
STL15DN4F5
PowerFLAT™ (5x6) double island mechanical data
mm
Dim
Min
Typ
Max
A
A1
A3
b
0.80
0.83
0.02
0.20
0.40
5.00
4.75
4.21
6.00
5.75
3.61
2.42
1.27
0.80
0.58
0.90
0.05
0.35
0.47
D
D1
D2
E
4.11
4.31
E1
E2
E3
e
3.51
2.32
3.71
2.52
L
0.70
0.90
0.68
L1
0.48
8066312_A
10/12
Doc ID 17739 Rev 1
STL15DN4F5
Revision history
5
Revision history
Table 9.
Date
02-Sep-2010
Document revision history
Revision
Changes
1
First release
Doc ID 17739 Rev 1
11/12
STL15DN4F5
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Doc ID 17739 Rev 1
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