STLC60134 [STMICROELECTRONICS]
TOSCA INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT; TOSCA集成的ADSL CMOS模拟前端电路![STLC60134](http://pdffile.icpdf.com/pdf1/p00064/img/icpdf/STLC60134_338641_icpdf.jpg)
型号: | STLC60134 |
厂家: | ![]() |
描述: | TOSCA INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT |
文件: | 总22页 (文件大小:168K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STLC60134S
TOSCA INTEGRATED ADSL CMOS
ANALOG FRONT-END CIRCUIT
FULLY INTEGRATED AFE FOR ADSL
OVERALL 12 BIT RESOLUTION, 1.1MHz
SIGNAL BANDWIDTH
8.8MS/s ADC
8.8MS/s DAC
THD: -60dB @FULL SCALE
TQFP64
ORDERING NUMBER: STLC60134S
4-BIT DIGITAL INTERFACE TO/FROM THE
DMT MODEM
1V FULL SCALE INPUT
lows to get a T1.413Issue 2 compliant solution.
DIFFERENTIAL ANALOG I/O
ACCURATE CONTINUOUS-TIME CHANNEL
FILTERING
3rd & 4th ORDER TUNABLE CONTINUOUS
TIME LP FILTERS
The STLC60134S analog front end handles 2
transmission channels on a balanced 2 wire inter-
connection; a 16 to 640Kbit/s upstream channel
and a 1.536 to 8.192Mbit/s downstreamchannel.
A 256 carrier DMT coding (frequency spacing
4.3125kHz) transforms the downstream channel
to a 1MHz bandwidth analog signal (tones 32-
255) and the upstream channel (tones 8-31) to a
100kHz bandwidth signal on the line.
This asymmetrical data transmission system uses
high resolution, high speed analog to digital and
digital to analog conversion and high order ana-
log filtering to reduce the echo and noise in both
0.5 WATT AT 3.3V
0.5µm HCMOS5 LA TECHNOLOGY
64 PIN TQFP PACKAGE
DESCRIPTION
STLC60134S is the Analog Front End of the
STMicroelectronics Tosca
ADSL chipset and
when coupled with STLC60135 (DTM modem) al-
Figure 1. Block Diagram
XTAL-DRIVER
VCXO
R-MOS-C
I/V-REF
TUNING
DAC
ERROR
ADC
CORRECTION
G=-15...0dB
step=1dB
13 bits
TXP
TXN
+
-
-
ANALOG
LOOP
+
4 bits
MUX
AGCtx
DIGITAL
IF
1.1MHz
HC2
1.1MHz
HC1
138KHz
SC2
DIGITAL
LOOP
DAC
MUX
G=0..31dB
step=1dB
12 bits
4 bits
RXP(0:1)
RXN(0:1)
+
-
+
-
AGCrx
D99TL453
August 1999
1/22
STLC60134S
the ATU-C/ATU-R receivers and transmitters. Ex-
ternal low noise driver and input stage used with
STLC60134Sguarantee low noise performances.
pendent frequencypulling.
The DAC which is driven by the CTRLIN pin pro-
vides a current output with 8-bit resolution and
can be used to tune the XTAL frequency with the
help of external components. A time constant be-
tween DAC input and VCXO output can be intro-
duced (via the CTLIN interface) and programmed
with the help of an external capacitor (on VCOC
pin).
The STLC60134S chip can be used at ATU-C
and ATU-R ends (behaviour set by LTNT pin).
The selection consists mainly of a filter inter-
change between the RX and TX path. The filters
(with a programmable cutoff frequency) use auto-
matic Continuous Time Tuning to avoid time vary-
ing phase characteristic which can be of dramatic
consequencefor DMT modem. It requires few ex-
ternal components, uses a 3.3V supply (a sepa-
rate 3.0V supply of the digital part is possible)
and is packaged in a 64-pin TQFP in order to re-
duce PCB area.
See chapter ’VCXO’ for the external circuit re-
.
lated to the VCXO
The Digital Interface part
The digital part of the STLC60134S can be di-
vided in 3 sections:
The data interface converts the multiplexed
data from/to the DMT signal processor into
valid representation for the TX DAC and RX
ADC. It performs also the error correction
mechanism needed at the (redundant) ADC
output.
The control interface allows the board proces-
sor to configure the STLC60134S paths
(RX/TX gains, filter band, ...) or settings (OSR,
vcodac enable, digital / analog loopback,...).
The test interface to enable digital (Full Scan,
nandtree, loop backs, functional,...) or analog
(TIN, TOUT assignation) tests to be per-
formed.
The Receiver (RX) part
The DMT signal coming from the line to the
STLC60134S is first filtered by the two following
external filters:
POTS HP filter: Attenuation of speech and POTS
signalling
Channel filter:
Attenuation of echo signal to
improve RX dynamic
An analog multiplexer allows the selection be-
tween two input ports which can be used to select
an attenuated(0, 10dB for ex.) version of the sig-
nal in case of short loop or large echo. The sig-
nal is amplified by a low noise gain stage (0-
31dB) then low-pass filtered to avoid anti-aliasing
and to ease further digital processing by remov-
ing unwanted high frequencyout-of-band noise.
A 12-bit A/D converter samples the data at
8.832MS/s (or 4.416MS/s in alternative mode),
transforms the signal into a digital representation
and sends it to the DMT signal processor via the
digital interface.
DMT Signal
A DMT signal is basically the sum of N inde-
pendently QAM modulated signals, each carried
over a distinct carrier. The frequency separation
of each carrier is 4.3125kHz with a total number
of 256 carriers (ANSI). For N large, the signal can
be modelled by a gaussian process with a certain
amplitude probability density function. Since the
maximum amplitude is expected to arise very
rarely, we decide to clip the signal and to trade-
off the resulting SNR loss against AD/DA dy-
namic. A clipping factor (Vpeak/Vrms = ”crest fac-
tor”) of 5 will be used resulting in a maximum
SNR of 75dB.
The Transmitter (TX) part
The 12-bit data words at 8.832MS/s (or
4.416MS/s) coming from the DMT signal proces-
sor through the digital interface are transformed
by D/A converterinto a analog signal.
This signal is then filtered to decrease DMT side-
lobes level and meet the ANSI transmitter spec-
tral response but also to reduce the out-of-band
noise (which can be echoed to the RX path) to an
acceptable level. The pre-driver buffers the signal
for the external line driver and in case of short
loop provide attenuation(-15...0dB).
ADSLDMT signalsarenominallysentat -40dBm/Hz
±3dB (-3.65dBm/carrier) with a maximal power of
100mW for down link transmitter and 15.7mW for
uplink transmitter.
DMT symbols are transmitted without ’window-
ing’ causing sin (x)/x like sidelobes. For spectral
response shaping, the 1st sidelobe level is as-
sumed to be 13dB under the carrier level with
an attenuation of -20dB/dec.
The minimum SNR + D needed for DMT carrier
demodulation is about (3 N + 20) dB with a
minimum of 38dB were N is the constellation size
of a carrier (in bits).
The VCXO part
The VCXO is divided in a XTAL driver and a aux-
iliary 8 bits DAC for timing recovery.
The XTAL driver is able to operate at 35.328MHz
and provides an amplitude regulation mechanism
to avoid temperature / supply / technology de-
2/22
STLC60134S
mit power and line impedance signal amplitudes
can differ from these values.
The reference line impedance for all power calcu-
lations is 100Ω.
Maximum / minimum signal levels
The following table gives the transmitted and re-
ceived signal levels for both ATU-R and ATU-C
sides. All the levels are referred to the line volt-
ages (i.e. after hybrid and transformers in TX di-
rection, before hybrid and transformer in RX di-
rection).
PACKAGE
The STLC60134S is packaged in a 64-pin TQFP
package (body size 10x10mm, pitch 0.5mm).
Note that signal amplitudes shown below are for
illustration purpose and depending on the trans-
Table 1. Target Signal Levels
(on the line).
Parameter
ATU - C
ATU - R
RX
839 mVpdif
TX
15.8 Vpdif
RX
3.95 Vpdif
TX
Max level
3.4 Vpdif
Max RMS level
Min level
168 mVrms
54 mVpdif
11 mVrms
3.16 Vrms
3.95 Vpdif
791 mVrms
791 mVrms
42 mVpdif
8 mVrms
671 mVrms
839 mVpdif
168 mVrms
Min RMS level
Table 2. Total Signal Level
(on the line).
Parameter
ATU - C
ATU - R
RX
TX
RX
TX
Max level for receiver 4 Vpdif (Long line)
4.2 Vpdif (Short line)
Figure 2. Pin Connection
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
TX1
TX0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RXIP0
RXIN0
GC1
NU3
NU2
GC0
NU1
VCOC
GP2
NU0
CTRLIN
DVSS1
CLKM
CLNIB
CLWD
RX3
AVDD6
AVDD5
RES
RES
10
11
12
AGND
RES
13
14
RX2
RES
RX1
AVSS5
AVSS4
GP1
RX0
15
16
DVDD1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D98TL355mod
3/22
STLC60134S
Table 3. Pin Functions.
N.
Name
Function
PCB connection Supply
ANALOG INTERFACE
24
25
26
31
32
38
44
45
46
47
48
49
50
53
55
56
59
60
VRAP
VREF
VRAN
TXP
positive voltage reference ADC
ground reference ADC
Decoupling network AVDD3
Decoupling network AVDD3
Decoupling network AVDD3
negative voltage reference ADC
pre driver output
Line driver input
Line driver input
AVDD4
AVDD4
TXN
pre driver output
AGND
VCOC
GC0
virtual analog ground (AVDD/2 = 1.65V)
VCODAC time constant capacitor
External gain control output LSB
External gain control output MSB
analog receive negative input Gain 0
analog receive positive input Gain 0
analog receive negative input Gain 1 (most sensitive input)
analog receive positive input Gain 1 (most sensitive input)
current reference TX DAC/DACE
current reference VCO DAC
Decoupling network AVDD5
VCODAC cap.
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
AVDD5
GC1
RXN0
RXP0
RXN1
RXP1
IREF
IVCO
VCXO
XTALI
XTALO
Echo filter output
Echo filter output
Echo filter output
Echo filter output
Decoupling network AVDD2
VCO bias network AVDD1
VXCO control current
VCXO filter
AVDD1
AVDD1
AVDD1
XTAL oscillator input pin
XTAL oscillator output pin
Crystal + varicap
Crystal + varicap
DIGITAL INTERFACE
1
TX1
digital transmit input, parallel data
digital transmit input, parallel data
serial data input (settings)
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
DVDD2
2
7
TX0
CTRLIN
CLKM
CLNIB
CLWD
RX3
Async Interface
Load = CL<30pF
9
master clock output, f = 35.328MHz
10
11
12
13
14
15
18
19
nibble clock output, f = 17.664MHz (OSR= 2) or ground (OSR= 4) Load = CL<30pF
word clock output, f = 8.832/4.416MHz
digital receive output, parallel data
digital receive output, parallel data
digital receive output, parallel data
digital receive output, parallel data
power down select, ”1” = power down
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
Load = CL<30pF
RX2
RX1
RX0
PDOWN
LTNT
Power down input DVDD2
VDD in ATU-C mode DVDD2
ATU-R / ATU-C select pin 1, ATU-R = 0 /ATU-C = 1 / test
mode MSB
20
22
33
43
63
64
21
RESETN
GP0
reset pin (active low)
RC- reset
DVDD2
AVDD
General purpose output 0 (on AVDD 1)
General purpose output 1 (on AVDD 1)
General purpose output 2 (on AVDD 1)
digital transmit input, parallel data
digital transmit input, parallel data
RESERVED
Echo filter output
Echo filter output
Echo filter output
Load = CL<30pF
Load = CL<30pF
GP1
AVDD
GP2
TX3
AVDD
DVDD2
DVDD2
TX2
RES
Must be connected
to DVSS (input)
36,
37, 39,
RES
Must be connected
to AVSS (input)
RESERVED
40, 57
SUPPLY VOLTAGES
8
DVSS1
DVDD1
DVDD2
AVSS3
AVDD3
DVSS
DVDD
DVDD
AVSS
AVDD
16
17
23
27
Digital I/O supply voltage
digital internal supply voltage
ADC supply voltage
4/22
STLC60134S
Table 3. Pin Functions
(continued)
28
34
35
41
42
51
52
54
58
61
62
SPARES
3
AVDD4
AVSS4
AVSS5
AVDD5
AVDD6
AVSS6
AVSS2
AVDD2
AVDD1
AVSS1
DVSS2
TX pre - drivers supply
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
AVSS
AVDD
AVDD
AVSS
DVSS
CT filter supply
LNA supply
DAC and support circuit
XTAL oscillator supply voltage
NU3
NU2
NU1
NU0
NC0
NC1
Not used inputs
Not used inputs
Not used inputs
Not used inputs
DVSS
DVSS
DVSS
DVSS
4
5
6
29
30
1
LT ↔ AUT-C; NT ↔ ATU-R
Figure 3. Grounding and Decoupling Networks.
10µF
VRAP pin
VRAN pin
4.7µH
L1
ANALOG
VDD
AVDD (each pin must
have its own capacitor)
100nF
10µF
100nF
100nF
10µF
100nF
10µF
100nF
VREF pin
IREF pin
100nF
VCOC pin
10µF
AGND pin
10µF
100nF
10µF
D98TL356
duce DMT sidelobes and out of band noise influ-
ence on the receiver. On the RX path, a LP filter
must be used in order to reduce the echo signal
level and to avoid saturation of the input stage of
the receiver.
The POTS filter is used in both directions to re-
duce crosstalk between STLC60134S signals
and POTS speech and signalling.
ATU-C END: BLOCK DIAGRAM
The transformer at ATU-C side has 1:2 ratio. The
termination resistors are 12.5Ω in case of 100Ω
lines.
The hybrid bridge resistors should be < 2.5kΩ for
low-noise.
An HP filter must be used on the TX path to re-
5/22
STLC60134S
Figure 4. ATU-C END Block Diagram.
POTS
35.328MHz
LINE
LP
Zo=100
POTS FILTER
MASTER CLOCK
35.328MHz
2:1
XTRAL
DRIVER
NIBBLES 17.664MHz
HP POTS FILTER
RXT1
RXT2
WORD 8.832/4.416MHz
R
R
RXP(0:1)
RXN(0:1)
0..31dB
LNA
RXn
8.832MS/s
4.416MS/s
4
12-bit A/D
CONVERTER
12.5
12.5
LPF
LP138KHz
SC2
GRX
CTRLIN
LTNT=1
RESETN
TO
STLC60135
2R
2R
GTX
LINE
DRIVER
-15..0dB
TXP
TXN
4
12-bit D/A
PD
HPF
LP 1.1MHz
HC2
CONVERTER
TXn
8.832MS/s
4.416MS/s
D98TL357mod
duce DMT sidelobes and out of band noise influ-
ence on the receiver. On the RX path, a HP filter
must be used in order to reduce the echo signal
level and to avoid saturation of the input stage of
the receiver.
The POTS filter is used in both directions to re-
duce crosstalk between ADSL signals and POTS
speech and signalling. Low pass POTS filter can
be very simple for Lite - ADSL application
ATU-R END: BLOCK DIAGRAM
The ATU-R side block diagram is equal to the
ATU-C side block diagram with the following dif-
ferences:
- The transformer ratio is 1:1
- Termination resistors are 50Ω for 100Ω lines.
An LP filter may be used on the TX path to re-
Figure 5. ATU-R END Block Diagram.
POTS
35.328
MHz
LINE
LP
VCXOUT
Zo=100
POTSFILTER
MASTER CLOCK
35.328MHz
1:1
HP POTSFILTER
XTAL
DRIVER
VCODAC
NIBBLES17.664MHz
WORD 8.832/4.416MHz
RXT1
RXT2
R
R
RXP(0:1)
RXN(0:1)
0..31dB
LNA
RXn
8.832MS/s
4.416MS/s
4
12- bit A/D
CONVERTER
50
50
HPF
LP 1.1MHz
HC2
GRX
CTRLIN
LTNT=0
TO
STLC60135
2R
2R
RESETN
GTX
LINE
DRIVER
-15..0dB
TXP
TXN
4
12-bit D/A
PD
LPF
LP 138KHz
SC2
CONVERTER
TXn
8.832MS/s
4.416MS/s
D98TL358mod
6/22
STLC60134S
the frequency band of interest. The maximum
noise density within the pass band can exceed
the average value as follows:
ATU-R RX path (max AGC setting):
<100nVHz-1/2 @ 138kHz
<31nVHz-1/2 for 250kHz < f
RX PATH
Speech filter
An external bi-directional LC filter for up and
downstream POTS service splits the speech sig-
nal from the ADSL signal to the POTS circuits on
ATU-C.
The ADSL analog front end integrated circuit
does not contain any circuitry for the POTS serv-
ice but it guarantees that bandwidth is not dis-
turbed by spurious signals from the ADSL-spec-
trum.
ATU-C RX path (max AGC setting):
<100nVHz-1/2 for 34.5kHz< f <138kHz
RX-PATH NOISE AT MINIMUM GAIN
At the minimum AGC the total average thermal
noise of the analog RX-path at the ADC input
should be lower than the ADC quantisationnoise.
The maximum noise density within the pass band
can exceed the average value as follows:
Channel Filters
The external analog circuits provide partial echo
cancellation by an analog filtering of the receive
signal for both ATU-R (Reception of downstream
channel) and ATU-C (Reception of upstream
channel). This is feasible because the upstream
and the downstream data can be modulated on
separate carriers (FDM).
ATU-R RX path (min AGC setting):
-1/2
<500nVHz
@ 138kHz< f
ATU-C RX path (min AGC setting):
<1.5µVHz-1/2 @ 34.5kHz < f < 138kHz
These noise specifications correspond with 10bit
resolution of the complete RX-path.
Table 4. RX Common-mode Voltage
Line Noise Model
The power spectral density of the crosstalk noise
sources as described in ANSI document is given
in the figure below (no HDB3 interferer signals).
Also given in dotted line, is the noise model used
in this document to specify the sensivity require-
ments which are stronger than the original ones.
Description
Value/Unit
Common mode signal VCM
at RXIN1 and RXIN2:
1.6V < VCM <1.7V
Figure 6. Crosstalk PSD.
AGC of RX path
The AGC gain in the RX-path is controlled
through a 5-bits digital code.
dBm/Hz
-100
Four inputs are provided for RX input and the se-
lection is made with the RXMUX bits of the
CTRLIN interface. This can be used to make
lower gain paths in case of high input signal.
-110
-120
-130
-140
D98TL359
79.5 138 250
795
kHz
Table 5. AGC Characteristics.
Description
Value/Unit
20nVHz-1/2
Input referred noise
(max. gain)
Signal to Noise Performance
Max. input level
Max. output level
Gain range
1Vpd
1Vpd
RX- PATH SENSITIVITY AT MAXIMUM GAIN
The RX path sensitivity at the maximal RX-AGC
of the ATU-R receiver is defined at -140dBm/Hz
(for 100Ω ref) on the line. This figure corresponds
to the equivalent input noise of 31nVHz
on the line.
The sensitivity at the maximal RX - gain of the
ATU-C receiver is defined at -130dBm/Hz (for
100Ω ref) on the line. The figure corresponds to
the equivalent input noise of 100nVHz
on the line.
0to 31dB with step = 1dB
Gain and step accuracy
0.3dB
±
-1/2
seen
RX Filters
The combination of the external filter (an LC lad-
der filter typically) with the integrated lowpass fil-
ter must provide:
- echo reduction to improve dynamic range
- DMT sidelobe and out of band (anti-aliasing)
attenuation.
-1/2
seen
Both noise figures include the noise of the hybrid.
It is the equivalent average thermal noise over
- Anti alias filter (60dB rejection @ image freq.)
7/22
STLC60134S
ATU-R RX Filters
The integratedfilter have the following characteristics:
Table 6. Integrated HC Filter Characteristics
Description
Input referred noise
Max. input level
Value/Unit
100nVHz-1/2
1Vpd
Max. output level
Type
1Vpd
3rd order butterworth
Frequency band
1.104MHz (0%setting, see below)
Frequency tuning
Max. in-band ripple
-43.75% ->+0%
1dB
Matlab Model
[B, A] = butter (3, w0, ’s’)
F0 = 1560KHz
w0 = 2 * pi * F0/((20 + n)/16)
n = -4,..,3
Default cut off frequency @ -3dB
Actual cut off @ -3dB
HC Freq. selection register
see (AFE settings ,Table 22)
Table 7. Phase Characteristic
Description
Total RX filter group delay
Value/Unit
< 50µs @ 138kHz < f < 1.104MHz
< 15µs @ 138kHz < f < 1.104MHz
Total RX filter group delay distortion
Figure 7. HC Filter Mask for ATU-R RX and ATU-C TX
AMPLITUTDE
+/-1dB
5dB
36dB
50dB
0dB
30
D98TL360
1104 2208
7728
16560
kHz
Note: The total ATU_R RX path (including ADC) group delay distortion is 16µs (i.e. = 15µs + 1µs of ADC)
ATU-C RX filter
This filter is the same as the one used for ATU-R TX.
Linearity of RX
Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies
f1 and f2 and each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the RX - AGC amplifier (i.e: be-
fore the ADC) for the case of minimal AGC setting.
The following tables 8 and 9 list the RX path intermodulation distortion (as S/IM3 ratio) in downstream
and upstreambandwidth.
Table 8. Linearity of ATU-R RX
f1 (0.5Vpd)
f2 (0.5Vpd)
300kHz
200kHz
500kHz
400kHz
700kHz
600kHz
S/IM3 (AGC = 0dB)
59.5dB @ 100kHz
53.5dB @ 400kHz
43.5dB @ 700kHz
42.5dB @ 800kHz
59.5dB @ 300kHz
48.0dB @ 600kHz
48.0dB @ 500kHz
42.5dB @ 800kHz
8/22
STLC60134S
Table 9. Linearity of ATU-C RX
f1 (0.5Vpd)
f2 (0.5Vpd)
80kHz
70kHz
S/IM3 (AGC = 20 dB)
2f2 - f1
2f1 - f2
56.5dB @ 60kHz
56.5dB @ 90kHz
Table 10. RX Filter to A/D Interface
RX filter to A/D maximal level:
1Vpd = full scale of A/D
Table 11. A/D Convertors (A pipeline architecture is used for A/D convertors).
Numbers of bits:
12bits
Minimum resolution of the A/D convertor
Linearity error of the A/D convertor
Full scale input range:
11bits
<1LSB (out of 12bits)
1 Vpdif ±5%
Sampling rate:
8.832MHz (or 4.416MHz in OSR = 2 mode)
<0.5dB without in-band ripple
Maximum attenuation at 1.1MHz:
Maximum group delay:
<3 s
µ
Maximum group delay distortion:
<1 s
µ
Power Supply Rejection
The noise on the power supplies for the RX path must be lower than the following:
<50mVrms in band white noise for any AVDD.
In this case, PSR (power supply rejection) of STLC60134SRX path is lower than -43dB.
TX PATH
Transmitter Spectral Response
The two figures below show the ANSI spectral response mask for ATU-C and ATU-R transmitters
Figure 8. ATU-C TX spectral response mask
+/-3dB
dBm/Hz
24dB
50dB
-40
-64
-90
30
D98TL361
1104 2208
11040
KHz
Figure 9. ATU-R TX spectral response mask
+/-3dB
dBm/Hz
24dB
48dB
-40
-64
-88
30
D98TL362
138 181
224
KHz
9/22
STLC60134S
Table 12. AGC of TX Path (from filter output to TXP and TXN).
Output noise
25mVHz-1/2
1Vpd
Input level (nominal)
Output level nominal, full-scale
Maximum Output Load
AGC range:
1.5Vpd
> 500 ; <10pF
Ω
-15dB...dB
1dB
AGC step:
Gain and step accuracy
0.3dB
±
Minimum code (0000) stands for AGC = -15dB and maximum (1111 - MSB left) for AGC = 0dB (See Tx
setting, Table22).
TX Pre-driver Capability
The pre-driver drives an external line power amplifier which transmits the required power to the line.
Table 13. TX Pre-driver
TX drive level to the external line driver for max. AGC setting
External line driver input impedance:
1.5 Vpdif
> 500
< 30pF
resistive
capacitive
Ω
Pre-driver characteristics:
closed loop gain:
-15dB...0dB with step = 1dB
< 10mV
ooutput impedance:
output offset voltage (0dB)
input noise voltage (0dB)
< 20nVHz-1/2 @ f > 250k
Ω
< 50nVHz-1/2 @ 34.5K < f
<138kΩ
output common mode voltage:
1.6V < Vcm < 1.7V
TX Filter
The TX filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A con-
vertor’s output to suppress the image spectrum. For this reason they must be realized in a continuous
time approach.
ATU-R TX Filter
The purpose of this filter is to remove out-of-band noise of the ATU-R TX path echoed to the ATU-R RX
path. In order to meet the transmitter spectral response, an additional filtering must be (digitally) per-
formed. The integrated filter has the following characteristics:
Table 14. Integrated SC Filter Characteristics
Description
Value/Unit
Input referred noise
Max. input level
Max. output level
Type
100nVHz-1/2
1Vpd
1Vpd
4th order chebytchef
Frequency band
Frequency tuning
Max. in-band ripple
Matlab Model
138kHz (0% settingseebelow)
-25%-> +25%
1dB
[B,A] = cheby1 (4,0.5,W0,’s’) {ripple = 0.5}
F0 = 151.8kHz
W0 = 2*pi*F0/((17+n)/16)
Default cut-off frequency @ -3dB
Actual cut-off @ -3dB
SC Freq. selection register
n = -4,..,3
see (AFE settings, Table 22)
10/22
STLC60134S
Table 15. Phase characteristics
Description
Value/Unit
<50 s @ 34.5kHz < f < 138kHz
Total TX filter group delay
µ
Total TX filter group delay distortion
<20 s @ 34.5kHz < f < 138kHz
µ
Note: The total ATU-R TX path (including DAC) group delay distortion is 16µs (i.e. = 15µs + 1µs of DAC)
Figure 10. SC Filter Mask for ATU-CRX and ATU-R TX
AMPLITUTDE
0dB
+/-1dB
20dB
30
D98TL363
138 250
KHz
Table 16. D/A Convertor (A current steering architecture is used).
Description
Value/Unit
Numbers of bits:
12bits
11bits
Minimum resolution of the D/A convertors
Linearity error of the A/D convertor
Full scale input range:
<1LSB (out of 12bits)
1 Vpdif 5%
±
Sampling rate:
8.832MHz (or 4.416MHz in compatible mode)
<3 s
Maximum group delay:
µ
Maximum group delay distortion:
<1 s
µ
Linearity of ATU-C TX
Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and
each with 0.5Vpdamplitude (total ≤ 1Vpd)at the outputof the pre-driverforthe case of a total AGC = 0dB.
Table 17. Linearity of ATU-C TX
f1 (0.5Vpd)
f2 (0.5Vpd)
300kHz
200kHz
500kHz
400kHz
700kHz
600kHz
S/IM3 (AGC = 0dB)
59.5dB @ 100kHz
53.5dB @ 400kHz
43.5dB @ 700kHz
42.5dB @ 800kHz
59.5dB @ 300kHz
48.0dB @ 600kHz
48.0dB @ 500kHz
42.5dB @ 800kHz
11/22
STLC60134S
Linearity of ATU-R TX
Table 18. Linearity of ATU-R TX
f1 (0.5Vpd)
80kHz
f2 (0.5Vpd)
70kHz
S/IM3 (AGC = 0 dB)
59.5dB (@ 60KHz, 90KHz)
TX IDLE CHANNEL NOISE
ATU-C TX idle channel noise
The idle channel noise specifications correspond with 11bit resolution of the complete TX-path. ATU-C
TX idle channel output noise on TX.
Table 19. ATU-C TX idle channel noise
For max AGC setting (0dB)
In-band noise
Out-of-band noise
500nVHz-1/2
500nVHz-1/2
@ 138kHz -1.104MHz
@ 34.5kHz -138kHz
For min AGC setting (=-15dB)
In-band noise
80nVHz-1/2
@ 138kHz -1.104MHz
ATU-R TX idle channel noise
ATU-R TX idle channel output noise on TXP, TXN
Table 20. ATU-R TX idle channel noise
For max AGC setting (0dB)
In-band noise
Out-of-band noise
1.6 VHz-1/2
@ 34.5kHz -138kHz
@ 138kHz
@ 250kHz -1.104MHz
µ
1.6µVHz-1/2
150nVHz-1/2
For min AGC setting (=-15dB)
In-band noise
500nVHz-1/2
@ 34kHz -138kHz
Power Supply Rejection
The noise on the power supplies for the TX-path must be lower than the following:
< 50mVrms in-band white noise for AVDD.
< 15mVrmsin-bandwhite noise forPre-driverAVDD.
VCXO
A voltage controlled crystal oscillator driver is integrated in STLC60134S. The nominal frequency is
35.328MHz. The quartz crystal is connectedbetween the pins XTALI and XTALO.
The principle of the VCXOcontrol is shown in figure 11.
The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC
which generates a control current. This current is externally converted and filtered to generate the re-
quired control voltage (range:-15V to 0.5V) for the varicap. The VCXO circuit characteristics are given in
Table 21.
12/22
STLC60134S
Table 21. VCXO circuit Characteristics
Symbol
fabs
Parameter
Min.
Nominal
Max.
Note
Absolute frequency accuracy
Frequency Tuning Range
VCXO Output Current
-15ppm
35.328MHz
+15ppm
frange
IO
50ppm
±
100 A
Rref = 16.5k
Ω
µ
AVDD = 3.3V
Ii
Reference Input Current
100 A
1mA
AVDD = 3.3V
µ
m
N.B: frequency tuning range is proportional to the crystal dynamic capacitance C .
Figure 11. Principle of VCXO control
AVDD
CS
AVDD/22÷AVDD/2
IVCO
VCOCX
RREF
1MΩ
AVDD
Ii
8 bits
±30%
CTRLIN
DAC
IO=Ii
Filtered VCXO
(see CTRLIN table)
VCXOUT
XTALO
AGND
Clk35
CP
Ct
Rt
-15V
XTALI
D98TL364mod
The tuning must be monotonicwith 8-bit resolution with the worst-case tuning step of <2ppm/LSB (8-bit).
s
The time constant of the tuning must be variable from 5s to 10s through an external capacitor C (R =
1MΩ ±30%). This determines the speed of the VCXO in normal operation (slow speed in ”show time”)
with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt.
13/22
STLC60134S
DIGITAL INTERFACE
Control Interface
The digital setting codes for the STLC60134S configuration are sent over a serial line (CTRLIN) using
the word clock (CLWD).
The data burst is composed of 16 bits from which the first bit is used as start bit (’0’), the three LSBs be-
ing used to identify the data contained in the 12 remaining bits. Test related data are overruled by the
normal settingsif the TEST pin is low.
Table 22. Control Interface Bit Mapping
M
S
B
L
S
B
RX SETTINGS
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External Gain Control GC1
(init = 0)
(init = 0)
(init)
x
External Gain Control GC0
Rx input selected = RXIN0, RXIP0
Rx input selected = RXIN1, RXIP1
AGC RX Gain setting 0dB
0
1
0
0
x
1
0
0
x
1
0
0
x
1
0
0
x
1
0
1
x
1
(init)
AGC RX Gain setting 1dB
AGC RX Gain setting XdB
AGC RX Gain setting 31dB
0
0
1
1
0
1
0
1
Normal mode Filter selection see LTNT pin (init)
In ATU-C conf, force HC2 for RX path, TX grounded
In ATU-C conf, force HC1 for RX path
Normal mode Filter selection see LTNT pin
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
TX SETTINGS
0
0
0
0
0
0
0
0
0
0
0
x
1
0
0
x
1
0
0
x
1
0
1
x
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Transmit TX - AGC setting -15dB
Transmit TX - AGC setting -14dB
Transmit TX - AGC setting (X - 15) dB
Transmit TX - AGC setting 0dB
Not used
(init)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(init)
(init)
Not used
Not used
(init)
Not used
(init)
x
x
x
General Purpose Output (GPO) setting
(init = 000)
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
AFE SETTINGS
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Normal Mode (Digital path)
(init)
Digital Loopback (digital TX to digital RX - DACnot used)
Normal Mode (Analog path)
Analog loopback (RXi to TXi - ADC not used) 1)
0
1
(init)
0
1
VCO DAC disabled
VCO DAC enabled
HC filter enabled
HC filter enabled
(init)
(init)
0
1
1) After initialization, this bit has to be cleared (0) to make the device properly operate.
14/22
STLC60134S
Table 22. Control Interface Bit Mapping (continued)
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
AFE SETTINGS
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
OSR set to 4
OSR set to 2
(init)
1
0
1
1
1
0
1
1
1
SC freq. selection: Fc = 138kHz
SC freq. selection: Fc ~ 110kHz
SC freq. selection: Fc ~ 170kHz
HC freq. selection: Fc = 1.104MHz
HC freq. selection: Fc ~ 768kHz
(init) (*)
(*)
(*)
1
0
0
1
0
1
(init) (*)
(*)
0
1
VCXO output NOT filtered (”show-time”)
VCXO output filtered
(init)
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
VCO DAC VALUE SETTINGS
0
0
0
0
x
1
0
x
1
0
x
1
0
x
1
0
x
1
0
x
1
0
x
1
0
x
1
0
0
0
1
1
1
1
1
1
VCO DAC CURRENT value @ MINIMUM
VCO DAC CURRENT value @ X
VCO DAC CURRENT value @ MAXIMUM
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
POWER DOWN ANALOG BLOCK SETTINGS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TXD Active
(init)
(init)
(init)
(init)
(init)
(init)
(init)
(init)
(init)
(init)
(init)
(init)
TXD in powerdown
N.U.
0
1
N.U.
0
1
ADC Active
ADC in powerdown
HFC2 Active
0
1
HFC2 in powerdown
HFC1 Active
0
1
HFC1 in powerdown
SCF2 Active
0
1
SCF2 in powerdown
SCF1 Active
0
1
SCF1 in powerdown
LNA Active
0
1
LNA in powerdown
DAC Active
0
1
DAC in powerdown
DACE Active
0
1
DACE in powerdown
VCODAC Active
VCODAC in powerdown
XTAL Active
0
1
0
1
XTAL in powerdown
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
RESERVED
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
RESERVED
(*) For each filter, 8 possible frequency values (see table 6 and table 14). Notation is 2’s complement range from -4 = 100b +3 = 011b.
Fc is the frequency band (-1dB)
15/22
STLC60134S
Control Interface Timing
The word clock (CLWD) is used to sample at negativegoing edge the control information. The start bit b15
is transmittedfirst followedby bits b[14:0]andat least16 stop bits need to be providedto validatethe data.
Figure 12. Control Interface.
CLWD
CTRLIN
START
BIT
DATA
ID.
>=16 STOP BITS=HIGH
D98TL365
Data set-up and hold time versus falling edge CLWD must be greater than 10nsec.
Receive / Transmit Interface
RECEIVE / TRANSMIT PROTOCOL
The digital interface is based on 4 x 8.832MHz(35.328MHz) data lines in the following manner:
If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal
mode), and all the RXi, TXi, CLKWDperiods are twice as long as in normal mode. This ensures a compati-
bility with lower speedproducts.
TX Signal Dynamic
The dynamic of data signal for both TX DACs is 12 bits extracted from the available signed 16 bit repre-
sentationcoming from the digital processor.
The maximal positive number is 214-1, the most negative number is -214, the 3 LSBs are filled with ’0’.
Any signal exceedingthese limits is clamped to the maximum value.
Table 23.
BIT MAP/NIBBLE
TXD0
N0
not used
N1
N2
N3
data bit 1
data bit 2
data bit 3
data bit 4
data bit 5
data bit 6
data bit 7
data bit 8
data bit 9
data bit 10
data SIGN
data SIGN
TXD1
not used
TXD2
not used
TXD3
d0 = data bit 0 (LSB)
Table 24. TX bit map
N3
N2
N1
N0
sign
sign
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
n.u.
n.u.
n.u.
The two sign bits must be identical.
16/22
STLC60134S
RX Signal Dynamic
The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2’s
complement) representation with a maximal positive number of 214 -1 and a most negative number -214.
The 2 LSBs are filled with ’0’.
Table 25.
BIT MAP/NIBBLE
RXD0
N0
N1
N2
N3
0
data bit 2
data bit 3
data bit 4
data bit 5
data bit 6
data bit 7
data bit 8
data bit 9
data bit 10
data bit 11
data SIGN
data SIGN
RXD1
0
RXD2
d0 = data bit 0 (LSB)
data bit 1
RXD3
Table 26. RX bit map
N3
N2
N1
N0
0
sign
sign
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
0
The two sign bits must be identical.
Figure 13. TX/ RX Digital Interface Timing
CLKM
35.328MHz
CLWD
8.832MHz
TXDx/RXDx
N0
N1
N2
N3
OSR=4
CLKNIB
17.664MHz
CLWD
4.416MHz
TXDx/RXDx
N0
N1
N2
N3
D98TL366
OSR=2
Receive / Transmit interface timing
The interface is a triple (RX, TX) nibble - serial interface running at 8.8MHz sampling (normal mode).
The data are represented in 16bits format, and transferred in groups of 4 bits (nibbles). The LSBs are
transferred first. The STLC60134S generates a nibble clock (CLKM master clock in normal mode,
CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the falling
edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital proces-
sor.
Data, CLWD setup and hold times are 5ns with referenceto the falling edge of CLKM/CLKNIB.
(not floating).
17/22
STLC60134S
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going
edge of CLKM/CLKNIB.This holdsfor the data streamfrom STLC60134Sand from thedigital processor.
Data,CLWD setupandholdtimes are5nswithreferenceto thefalling edgeof CLKM/CLKNIB.(notfloating).
POWER DOWN
When pin Pdown = ”1”, the chip is set in power down mode. As the Pdown signal is synchronously sam-
pled, minimum duration is 2 periods of the 35MHz clock. In this mode all analog functional blocks are
deactivated except: preamplifiers (TX), clock circuits for output clock CLKM. Pdown will not affect the digi-
tal part of the chip. Anyway, after a Pdown transition, the digital part status, is updated after 3 clock peri-
ods (worst case)
down
The chip is activated when P
= ”0”.
In power down mode the following conditions hold:
- Outputvoltages at TXP/TXN = AGND
- Preamplifier is on with maximum gain setting (0dB), (digitalgainsettingcoefficientsareoverruled)
- TheXTAL outputclockonpin CLKMkeepsrunning.
- All digital setting are retained.
- Digital output on pins RXDx don’t care (not floating).
In power-down mode the power consumption is 100mW.
Following external conditions are added:
- Clock pin CLW is running.
- CTRLIN signals can still be allowed.
- AGND remainsat AVDD/2 (circuit is powered up)
- Input signal at TXDx inputs are not strobed.
The Pdown signal controls asynchronouslythe power-down of each analog module:
- After a few µs the analog channel is functional
- After about 100ms the analog channel delivers full performance
RESET FUNCTION
The reset function is implied when the RESETN pin is at a low voltage input level. In this condition, the
reset function can be easily used for power up reset conditions.
Detailed Description
During reset: (reset is asynchronous,tenths of ns are enough to put the IC in reset)
All clock outputsare deactivatedand put to logical”1” (exceptfor the XTAL andmaster clock CLKM)
After reset: (4 clock periods after reset transition, as worst case)
- OSR = 4
- Allanaloggains(RX, TX)are setto minimumvalue
- Nominalfilter frequencybands(138kHz,1.104Hz)
- LNA input = ”11” (max. attenuation)
- VCO dac disabled
- Dependingof the LTNT pin value the following configurationis chosen:
’0’ (ATU-R)
RX:
TX:
LNA -> HC2 -> ADC
DAC -> SC2 -> TX
’1’ (ATU-C)
RX:
TX:
LNA -> SC2 -> ADC
DAC -> HC2 -> TX
18/22
STLC60134S
Digital outputs are placed in don’t care condition (non-floating).
N.B.
If a Xtal oscillator is used, the RESET must be released at last 10µs after power-on, to ensure a
correct duty cycle for the clk35 clock signal.
ELECTRICAL RATINGS AND CHARACTERISTICS
Table 27. Absolute Maximum Ratings
Symbol
VDD
Parameter
Any VDD Supply Voltage, related to substrate
Voltage at any input pin
Min
- 0.5
-0.5
-40
Max
5
Unit
V
Vin
VDD +0.5
125
V
Tstg
Storage Temperature
°C
TL
Lead Temperature (10 second soldering)
Latch - up current @80°C
300
°C
ILU
100
mA
mA
mA
mA
mA
IAVDD
IAVDD
IDVDD
IDVDD
Analog Supply Current @ 3.6V - normal operation
Analog Supply Current @ 3.6V - power down
Analog Supply Current @ 3.6V - normal operation
Analog Supply Current @ 3.6V - power down
165
30
56
50
Table 28. Thermal Data
Symbol
Parameter
Thermal and Junction ambient
Value
50
Unit
Rth j-amb
°C/W
Table 29. OperatingConditions
(Unless specified, the characteristic limits of ’Static Characteristics’ in this document apply over an Top =
-40 to 80 °C; VDD within the range 3 to 3.6V ref. to substrate.
Symbol
AVDD
DVDD
Vin /Vout
Pd
Parameter
AVDD Supply Voltage, related to substrate
DVDD Supply Voltage, related to substrate
Voltage at any input and output pin
Power Dissipation
Min
3.0
2.7
0
Max
3.6
3.6
VDD
0.6
80
Unit
V
V
V
0.4
-40
-40
W
°C
°C
Tamb
Ambient Temperature
Tj
Junction Temperature
110
19/22
STLC60134S
STATIC CHARACTERISTICS
Table 30. Digital Inputs
Schmitt-triggerinputs: TXi, CTRLIN, PDOWN, LTNT, RESETN, TEST
Symbol
VIL
Parameter
Low Level Input Voltage
High Level Input Voltage
Hysteresis
Test Condition
Min.
Typ.
Max.
Unit
V
0.3 DVDD
VIH
0.7 DVDD
1.0
V
VH
1.3
3
V
Cimp
Input Capacitance
pF
Table 31. Digital Outputs
Hard Driven Outputs: RXi
Symbol
VOL
Parameter
Test Condition
Iout = -4mA
Iout = 4mA
Min.
Typ.
Max.
Unit
V
Low Level Output Voltage
High Level Output Voltage
Load Capacitance
0.15 DVDD
VOH
0.85 DVDD
V
Cload
30
pF
Clock Driver Output: CLKM, CLNIB, CLKWD
Symbol
VOL
Parameter
Low Level Output Voltage
High Level Output Voltage
Load Capacitance
Test Condition
Iout = -4mA
Iout = 4mA
Min.
0.85 DVDD
45
Typ.
Max.
Unit
V
0.15 DVDD
VOH
V
Cload
DC
30
55
pF
%
Duty Cycle
20/22
STLC60134S
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
A2
B
1.60
0.063
0.006
0.05
1.35
0.18
0.12
0.15 0.002
1.40
0.23
1.45 0.053 0.055 0.057
0.28 0.007 0.009 0.011
C
0.16
0.20 0.0047 0.0063 0.0079
D
12.00
10.00
7.50
0.472
D1
D3
e
0.394
0.295
0.50
0.0197
E
12.00
10.00
7.50
0.472
0.394
E1
E3
L
0.295
0.40
0.60
0.75 0.0157 0.0236 0.0295
0.0393
L1
K
1.00
TQFP64
0°(min.), 7°(max.)
D
D1
D3
A
A2
A1
48
33
32
49
0.10mm
Seating Plane
17
16
64
1
C
e
K
TQFP64
21/22
STLC60134S
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22/22
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