STLS2E02 [STMICROELECTRONICS]
Loongson 2E: 700MHz 64-bit superscalar MIPS㈢ based microprocessor; 龙芯2E ： 700MHz的64位超标量MIPS㈢基于微处理器
| 型号： | STLS2E02 |
| 厂家： | 
ST |
| 描述： | Loongson 2E: 700MHz 64-bit superscalar MIPS㈢ based microprocessor |
| 文件： | 总5页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLS2E02
Loongson 2E:
700MHz 64-bit superscalar MIPS® based microprocessor
Data Brief
Features
■ 64 bit superscalar architecture
■ 700MHz clock frequency (typical conditions)
■ Single/double precision floating-point units
■ New Streaming Multimedia instruction set
support (SIMD)
■ 64KB instruction cache, 64KB data cache, on-
chip 512KB unified L2 cache
■ On-chip DDR-333 controller
PBGA452
■ Thermal Design Power (TDP)
– 4W @ 700MHz
■ Leading edge 90nm process technology
■ 35x35 BGA package
The memory hierarchy is composed by the first
level of 64KB 4-way set associative cache for
instructions and data, the second level of 512KB
unified 4-ways set associative cache and the
Memory Management Unit with Table Lookside
Buffer.
■ MIPS based
■ MIPS bus interface (Sysad)
Description
The STLS2E02, is a MIPS based 64-bit
superscalar microprocessor, able to issue four
instructions per clock cycle among six functional
units: two integer, two single/double-precision
floating-point, one 64bit SIMD and one load/store
unit.
The Loongson microprocessor family is the
outcome of a successful collaboration started in
2004 between STMicroelectronics and the
Institute of Computing Technology, part of the
Chinese Academy of Science. Loongson
microprocessors were co-developed by
STMicroelectronics and the Institute of
Computing Technology to address all the
applications requiring high level of performance
and low power dissipation.
The microarchitecture is organized with nine
stages of pipeline and support of dynamic branch
prediction.
Table 1.
Device summary
Part numbers
Package
PBGA452 (35x35x2.33mm)
Packing
STLS2E02
Tray
April 2007
Rev 2
1/5
For further information contact your local STMicroelectronics sales office.
www.st.com
5
Architectural features and block diagram
STLS2E02
1
Architectural features and block diagram
●
CPU
–
–
–
Out-of-order superscalar 64bit architecture
MIPS based
9 stage pipeline organized in fetch, pre-decode, decode, reg-map, dispatch, issue,
reg-read,execution and commit
–
–
–
–
–
Up to 64 instructions executed out-of-order with four issue mechanism
64bit register file (32 fix+32 float)
Register renaming unit composed by 64-entry physical register files
Branch prediction unit
Six functional units: two integer, two float, one SIMD unit, one load/store unit
●
Memory Hierarchy
–
–
–
–
–
–
64KB + 64KB four-ways set-associative first level instruction and data cache
512KB four-ways set associative unified second level cache
Up to 24 non-blocking accesses with on-the-fly Memory Disambiguation
Load speculation through value return from previous pending stores
Miss word first access for cache miss access
Instruction 16-entry TLB (Table Lookside Buffer) and unified 64-entry TLB with
page size from 4KB to 4MB
Figure 1.
Block diagram
Branch Bus
Commit Bus
Reorder Queue
Writeback Bus
BRQ
ROQ
BTB
Map Bus
D-Cache
64KB
ALU1
ALU2
AGU
Integer
Register
File
Fix
RS
BHT
ITLB
CP0
Queue
Floating
Point
FPU1
FPU2
Float
RS
TLB
Register
File
I-Cache
64KB
Refill Bus
Miss
Queue
Writeback
Queue
Cache Interface
L2 cache
DDR Controller
DDR
Arbitrator
SysAD Controller
AC00116
SysAD64
2/5
STLS2E02
Package information
2
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 2.
PBGA452 mechanical data & package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
TYP. MAX.
0.0969
A
A1
A2
b
2.460
0.0142
0.360
1.730
0.0681
0.600 0.750 0.900 0.0236 0.0295 0.0354
D
35.000
31.750
30.000
35.000
31.750
30.000
1.270
1.3780
1.2500
1.1811
1.3780
1.2500
1.1811
0.0500
0.0642
D1
D2
E
E1
E2
e
F
1.630
H
22.500
23.500 0.8858
0.200
0.9252
0.0079
0.0118
0.0059
ddd
eee
fff
HS/PBGA452 (35x35x2.33mm)
Slug Plastic Ball Grid Array
0.300
0.150
7656604 A
3/5
Revision history
STLS2E02
3
Revision history
Table 2.
Date
Document revision history
Revision
Changes
23-Mar-2007
26-Apr-2007
1
2
Initial release.
Text modifications.
4/5
STLS2E02
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5/5
相关型号：
STLS2F02-LP
MICROPROCESSOR, PBGA452, 27 X 27 MM, 2.90 MM HEIGHT, ROHS COMPLIANT, HFCBGA-452
STMICROELECTR
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