STM1403BSM-Q1F [STMICROELECTRONICS]
STM1403BSM-Q1F;
| 型号： | STM1403BSM-Q1F |
| 厂家： | 
ST |
| 描述： | STM1403BSM-Q1F |
| 文件： | 总8页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM1403, STM1404
3V FIPS-140
Security Supervisors with Battery Switchover
DATA BRIEFING
FEATURES
■
STM1403 SUPPORTS FIPS-140 SECURITY
Figure 1. Package
LEVEL 3+
–
4 High-Impedance Physical Tamper
Inputs
–
–
Over/Under Operating Voltage Detector
Security Alarm (SAL) on Tamper
Detection
■
STM1404 SUPPORTS FIPS-140 SECURITY
LEVEL 4
QFN16, 3x3mm (Q)
–
STM1403+ Over/Under Operating
Temperature Detector
–
Over/Under Temperature Thresholds are
Customer-Selectable and Factory-
Programmed
■
■
STM1403 AND STM1404 ARE 100% PIN-
COMPATIBLE
SUPERVISORY FUNCTIONS
■
■
BATTERY LOW VOLTAGE DETECTOR
(POWER-UP)
OPTIONAL V
(Available for STM1403A/1404A only)
LOW BATTERY SUPPLY CURRENT
(TYPICAL)
(1.237V)
REF
–
–
–
–
Automatic Battery Switchover
RST Output (Open Drain)
Manual (Push-button) Reset Input (MR)
Power-fail Comparator (PFI/PFO)
■
–
–
STM1403: 2.8µA (V
STM1404: 5.3µA (V
= 3.3V, 25°C)
= 3.3V, 25°C)
BAT
BAT
■
Vccsw (V SWITCH OUTPUT)
CC
–
–
Low When Switched to V
CC
■
SECURE LOW PROFILE 16-PIN, 3x3mm,
QFN PACKAGE
High When Switched to V
Indicator)
(BATT ON
BAT
Table 1. Device Options
STM704
V
V
Status,
During
Alarm
Physical
Tamper
Inputs
Over/Under Over/Under
REF
OUT
Vccsw Status,
During Alarm
Voltage
Temperature
(1.237V)
Option
(1)
Functions
Alarms
Alarms
(2)
STM1403A
STM1403B
STM1403C
STM1404A
STM1404B
STM1404C
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
ON
Normal Mode
Note 3
Note 3
■
High-Z
Ground
ON
High
High
(2)
■
■
■
Normal Mode
Note 3
Note 3
High-Z
Ground
High
High
Note: 1. SAL, RST, PFO, and BLD are Open Drain.
2. Normal Mode: Low when V is internally switched to V and High when V is internally switched to battery.
OUT
OUT
CC
3. Pin 9 is the V
pin for STM1403A, STM1404A. It is the V
pin for STM1403B/C and STM1404B/C.
REF
TPU
Rev 2.0
1/8
June 2005
For further information contact your local ST sales office.
STM1403, STM1404
SUMMARY DESCRIPTION
The STM1403/4 family of security supervisors are
a low power family of intrusion (tamper) detection
chips targeted at manufacturers of POS terminals
and other systems, to enable them to meet phys-
ical and/or environmental intrusion monitoring
requirements as mandated by various standards,
such as Federal Information Processing Stan-
dards (FIPS) Pub 140 entitled “Security Require-
ments for Cryptographic Modules,” published by
the National Institute of Standards and Technolo-
gy, U.S. Department of Commerce), EMVCo, ISO,
ZKA, and VISA PED.
STM1404 will target the highest security level 4
and include both physical and environmental (volt-
age and temperature) monitoring, while STM1403
will be a 100% pin-compatible, functional subset of
the STM1404, to target levels 3 and lower, and in-
cludes all of the functionality of the STM1404, ex-
cept for the over/under temperature monitoring.
The STM1404A and the STM1403A also offer a
(1.237V) as an option on pin 9. On
V
REF
STM1403B/C and STM1404B/C this pin is V
TPU
(internally switched V or V
).
BAT
CC
V
Pin Modes
OUT
Either part type can be made available in three
versions, corresponding to three modes of the
V
pin (Supply Voltage Out), when the SAL (Se-
OUT
curity Alarm) is asserted (active-low) upon tamper
detection:
STM1403A, STM1404A. V
stays ON (at V
CC
OUT
or V
) when SAL is driven low (activated).
BAT
STM1403B and STM1404B. V
is set to High-
OUT
Z when SAL is driven low (activated).
STM1403C and STM1404C. V is driven to
OUT
Ground when SAL is activated (may be used when
is connected directly to the V pin of the ex-
V
OUT
CC
ternal SRAM that holds the cryptographic codes).
The STM1403 and STM1404 include Automatic
Battery Switchover, RST Output (Open Drain),
Manual (Push-button) Reset Input (MR), Power-
fail Comparator (PFI/PFO), Physical and/or Envi-
ronmental Tamper Detect/Security Alarm, and
Battery Low Voltage Detect features.
All variants (see Table 1., Device Options) are pin-
compatible and available in a security-friendly, low
profile, 16-pin QFN package.
Figure 2. Logic Diagram
Table 2. Signal Names
(1)
V
CC
Switch Output
Vccsw
Manual (Push-button) Reset Input
Power-fail Input
MR
PFI
V
REF
(3)
or
V
Independent Physical Tamper
Detect Pins 1 through 4
BLD
V
CC
BAT
TP - TP
(1)
1
4
V
TPU
V
Supply Voltage Output
Active-low Reset Output
Power-fail Output
OUT
(2)
V
V
OUT
CCSW
(2)
RST
(3)
MR
PFI
RST
(2)
PFO
STM1403/4
(3)
PFO
SAL
(2)
Security Alarm Output
Battery Low Voltage Detect
1.237V Reference Voltage
Tamper Pull-up
SAL
(3)
(2)
TP (NH)
BLD
1
(3)
V
V
REF
TPU
V
TP
TP
TP
4
(3)
SS
2
3
(V or V
)
CC
BAT
(NL) (NH) (NL)
AI09682
V
V
V
Back-up Supply Voltage
Supply Voltage
Ground
BAT
CC
SS
Note: See PIN DESCRIPTIONS, page 9 of the full datasheet for
details.
Note: 1. V
only for STM1403/4A; V
for STM1403B/C and
TPU
REF
STM1404B/C.
2. Normal Mode: Low when V
V
1. Normal Mode: Low when V
is internally switched to
OUT
is internally switched to
OUT
V
and High when V
is internally switched to battery.
CC
OUT
and High when V
is internally switched to battery.
CC
OUT
2. SAL, RST, PFO, and BLD are Open Drain.
3. V only for STM1403/4A; V for STM1403B/C and
3. SAL, RST, PFO, and BLD are Open Drain.
REF
TPU
STM1404B/C.
2/8
STM1403, STM1404
Figure 3. QFN16 Connections
(1)
(2)
V
V
CC
BLD PFI
CCSW
15
16
14
13
12
(2)
1
2
RST
V
OUT
V
MR
11
10
9
BAT
(2)
(2)
3
4
SAL
PFO
V
(3)
TPU
V
or V
SS
REF
5
6
8
7
TP
(NH)
TP
(NL)
TP
(NH)
TP
3
4
1
2
(NL)
AI09683
Note: See PIN DESCRIPTIONS, page 9 of the full datasheet for details.
1. Normal Mode: Low when V is internally switched to V and High when V is internally switched to battery.
OUT
OUT
CC
2. SAL, RST, PFO, and BLD are Open Drain.
3. V only for STM1403/4A; V for STM1403B/C and STM1404B/C.
REF
TPU
3/8
STM1403, STM1404
Figure 4. Block Diagram
V
V
CC
OUT
(1,2)
BAT54J
COMPARE
COMPARE
V
V
SO
(1)
V
V
CCSW
(3)
BAT
V
INT
RST
t
rec
Generator
RST
MR
PFI
(3)
V
V
COMPARE
PFO
PFI
COMPARE @
POWER-UP
(3)
BLD
DET
(4)
V
TPU
(4)
1.237V V
REF
Generator
V
REF
V
COMPARE
HV
V
COMPARE
LV
TP (NH)
1
TP (NL)
2
(3)
SAL
TP (NH)
3
TP (NL)
4
(5)
High Temp.
Sense
T
> T
A
H
(5)
Low Temp.
Sense
T
< T
A
L
AI09684
Note: 1. BAT54J (from STMicroelectronics) recommended.
2. Required for battery-reverse charging protection.
3. Open Drain
4. V
only for STM1403/4A; V
for STM1403B/C and STM1404B/C.
REF
TPU
5. Available only on STM1404.
4/8
STM1403, STM1404
TAMPER DETECTION
Physical
Supply Voltage
The internally switched supply voltage, V
There are four (4) high-impedance physical
tamper detect input pins, 2 normally set to High
(NH) and 2 normally set to Low (NL). Each input is
designed with a glitch immunity. These inputs can
be connected externally to several types of actua-
tor devices (e.g., switches, wire mesh). A tamper
on any one of the four inputs that causes its state
to change will trigger the security alarm (SAL) and
drive it to active-low. Once the tamper condition no
longer exists, the SAL will return to its normal High
state.
(ei-
INT
ther V input or V
input) is continuously mon-
CC
BAT
itored. If V
should exceed the over voltage trip
INT
point, V (set at 4.2V, typical), or should go below
HV
the under voltage trip point, V (set at 2.0v, typi-
LV
cal). SAL will be driven active-low. Once the
tamper condition no longer exists, the SAL pin will
return to its normal High state.
Temperature (STM1404 Only)
The STM1404 has a built-in, bandgap-based sen-
sor to monitor the temperature. If a preset (cus-
tomer-selectable, factory-programmed) over-
TP and TP are set Normally to High (NH). They
1
3
are connected externally through a closed switch
or a high-impedance resistor to V (in the case
of STM1403/4A or STM1404A) or V
case of STM1403B/C, or STM1404B/C), A tamper
condition will be detected when the input pin is
temperature trip point (T ) or under-temperature
H
OUT
trip point (T ) is exceeded, the SAL is asserted
L
(in the
TPU
low.
When no tamper condition exists, SAL is normally
High (see PIN DESCRIPTIONS, page 9 of the full
datasheet for details).
When a tamper is detected, the SAL is activated
(driven low), independent of the part type. V
can be driven to one of three states, depending on
which variant of STM1403 or STM1404 is being
used (see Device Options, page 1):
pulled low. If not used, tie the pin to V
or V
.
TPU
OUT
TP and TP are set Normally to Low (NL). They
2
4
are connected externally through a high-imped-
ance resistor or a closed switch to V . A tamper
condition will be detected when the input pin is
pulled high. If not used, tie the pin to V
OUT
SS
.
SS
■
■
■
ON;
High-Z; or
Ground (V ).
SS
Note: The STM1403 or STM1404 must be initially
powered above V to enable the tamper detec-
RST
tion alarms. For example, if the battery is on while
V
V
= 0V, no alarm condition can be detected until
CC
CC
rises above V
(and t expires). From this
RST
rec
point on, alarms can be detected either on battery
or V . This is done to avoid false alarms when
CC
the device goes from no power to its operational
state.
5/8
STM1403, STM1404
PART NUMBERING
Table 3. Ordering Information Scheme
Example:
STM1403
A
T
M
–
Q
6
F
Device Type
STM1403: Physical, Voltage Tamper Detect
STM1404: Over/Under Temperature Detect
V
OUT
Status (SAL = Active-Low)
A: V
B: V
C: V
= ON; Vccsw = Normal Mode
= High-Z; Vccsw = High
= Ground; Vccsw = High
OUT
OUT
OUT
Reset Threshold Voltage
T: V
S: V
= 3.00V to 3.15V
= 2.85V to 3.00V
= 2.55V to 2.70V
RST
RST
R: V
RST
Battery Low Voltage Detect Threshold (V
)
DET
M: V
= 2.3V (Typ)
= 2.5V (Typ)
= 3.2V (Typ)
DET
DET
DET
N: V
O: V
Under (TL)/Over (TH) Temperature Alarm Thresholds (STM1404 only)
STM1403: Use dash (“–”).
STM1404: Use designators (below).
B: –25/+80°C
C: –25/+85°C
D: –25/+95°C
H: –35/+80°C
I: –35/+85°C
J: –35/+95°C
Package
Q = QFN16
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
F = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
6/8
STM1403, STM1404
REVISION HISTORY
Table 4. Document Revision History
Date
Revision
Description
11-October-04
1.0
First Edition
Corrected footprint dimensions; update characteristics (Figure 2, 3, 4, 5, 6, 7, 8, 9, 27,
28, 31; Table 1, 2, 3, 6, 7)
26-Nov-04
1.1
22-Dec-04
03-Feb-05
25-Feb-05
06-May-05
1.2
1.3
1.4
2.0
Update characteristics (Figure 5; Table 6, 7, 3)
Update characteristics (Figure 5; Table 6, 7)
Update temperature trip limits (Table 3)
v2.0 of DB corresponds to v1.5 of DS
7/8
STM1403, STM1404
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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