STM32479VI_技术文档

STM32F479xx

®

ARM Cortex -M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,

Ethernet, FMC, dual Quad-SPI, Crypto, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

Datasheet - production data

Features

&"'!

®

• Core: ARM 32-bit Cortex -M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 180 MHz,

MPU, 225 DMIPS/1.25 DMIPS/MHz

(Dhrystone 2.1), and DSP instructions

• Memories

UFBGA169 (7 × 7 mm)

UFBGA176 (10 x 10 mm)

TFBGA216 (13 x 13 mm)

LQFP176 (24 × 24 mm)

LQFP208 (28 x 28 mm)

WLCSP168

• Debug mode

–

SWD & JTAG interfaces

Cortex -M4 Trace Macrocell™

®

–

Up to 2 MB of Flash memory organized into two

banks allowing read-while-write

• Up to 161 I/O ports with interrupt capability

–

Up to 157 fast I/Os up to 90 MHz

Up to 159 5 V-tolerant I/Os

Up to 384+4 KB of SRAM including 64-KB of

CCM (core coupled memory) data RAM

Flexible external memory controller with up to

32-bit data bus: SRAM, PSRAM,

• Up to 21 communication interfaces

–

Up to 3 × I²C interfaces (SMBus/PMBus)

Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,

ISO7816 interface, LIN, IrDA, modem control)

Up to 6 SPIs (45 Mbits/s), 2 with muxed full-

duplex I²S for audio class accuracy via internal

audio PLL or external clock

SDRAM/LPSDR, SDRAM, Flash NOR/NAND

memories

–

Dual-flash mode Quad-SPI interface

–

• Graphics:

–

Chrom-ART Accelerator™ (DMA2D), graphical

hardware accelerator enabling enhanced

graphical user interface with minimum CPU load

LCD parallel interface, 8080/6800 modes

LCD TFT controller supporting up to XGA

resolution

–

1 x SAI (serial audio interface)

2 × CAN (2.0B Active)

SDIO interface

–

• Advanced connectivity

–

USB 2.0 full-speed device/host/OTG controller

with on-chip PHY

USB 2.0 high-speed/full-speed device/host/OTG

controller with dedicated DMA, on-chip full-

speed PHY and ULPI

Dedicated USB power rail enabling on-chip

PHYs operation throughout the entire MCU

power supply range

10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

®

–

MIPI DSI host controller supporting up to 720p

30Hz resolution

–

• Clock, reset and supply management

–

1.7 V to 3.6 V application supply and I/Os

POR, PDR, PVD and BOR

–

4-to-26 MHz crystal oscillator

Internal 16 MHz factory-trimmed RC (1%

accuracy)

32 kHz oscillator for RTC with calibration

Internal 32 kHz RC with calibration

• 8- to 14-bit parallel camera interface up to

–

54 Mbytes/s

• Cryptographic accelerator

•

Low power

Sleep, Stop and Standby modes

V_BATsupply for RTC, 20×32 bit backup registers

+ optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

and 7.2 MSPS in triple interleaved mode

• 2×12-bit D/A converters

–

Hardware accelerator for AES 128, 192 256,

Triple DES, HASH (MD5, SHA-1, SHA-2) and

HMAC

–

• True random number generator

• CRC calculation unit

• RTC: subsecond accuracy, hardware calendar

• 96-bit unique ID

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 180 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input. 2x watchdogs and

SysTick timer

Table 1. Device summary

Reference

Part numbers

STM32F479AI, STM32F479AG, STM32F479BI,

STM32F479xx STM32F479BG, STM32F479II, STM32F479IG

STM32F479NI, STM32F479NG

October 2015

DocID028010 Rev 2

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This is information on a product in full production.

www.st.com

Contents

STM32F479xx

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1

Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.1.1

1.1.2

1.1.3

1.1.4

LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

ARM^®Cortex^®-M4 with FPU and embedded Flash and SRAM . . . . . . . 19

Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Flexible Memory Controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.10 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.11 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.12 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.13 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25

2.15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.17 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.18 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.19 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.19.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.19.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.20 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Contents

2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32

2.21 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 33

2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.23

V_BAToperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.24.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.24.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.24.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.24.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.25 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.26 Universal synchronous/asynchronous receiver transmitters (USART) . . 37

2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.28 Inter-integrated sound (I²S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40

2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41

2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41

2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.38 Cryptographic accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.42 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.43 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.44 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.45 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Contents

STM32F479xx

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4

5

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Operating conditions at power-up / power-down (regulator ON) . . . . . . 92

Operating conditions at power-up / power-down (regulator OFF) . . . . . 92

Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 92

Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 110

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 119

5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 128

5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

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5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.3.26

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

BAT

5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 182

5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 183

5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 185

5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

6.1

6.2

6.3

6.4

6.5

6.6

6.7

WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

7

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 206

A.1

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

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List of tables

STM32F479xx

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F479xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 30

Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32

Voltage regulator modes in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

STM32F479xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

STM32F479xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 91

VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 92

Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 92

Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled except prefetch) or RAM,

regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . . 97

Typical and maximum current consumption in Run mode, code with data

Table 25.

Table 26.

processing running from Flash memory (ART accelerator enabled except prefetch),

regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . . 99

Typical and maximum current consumption in Sleep mode, regulator OFF. . . . . . . . . . . 100

Typical and maximum current consumption in Stop mode. . . . . . . . . . . . . . . . . . . . . . . . 101

Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 102

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Typical and maximum current consumption in V

mode. . . . . . . . . . . . . . . . . . . . . . . . 103

BAT

Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

LSE

HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6/208

DocID028010 Rev 2

STM32F479xx

List of tables

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 82.

Table 83.

Table 84.

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

Table 91.

Table 92.

Table 93.

Table 94.

Table 95.

SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 122

DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Flash memory programming with V

PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

2

I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 150

Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 151

Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 151

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

ADC static accuracy at f

= 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

= 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

= 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

ADC

ADC dynamic accuracy at f

= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 155

= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 155

ADC

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

BAT

internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 163

Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 163

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 164

Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 165

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 167

DocID028010 Rev 2

7/208

8

List of tables

STM32F479xx

Table 96.

Table 97.

Table 98.

Table 99.

Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 168

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 100. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 101. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 102. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 103. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 104. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 105. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 106. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 107. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 108. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 109. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 110. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 186

Table 112. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 187

Table 113. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 114. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 115. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 117. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,

ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 118. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 197

Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 120. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 121. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 122. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 123. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 206

Table 124. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

8/208

DocID028010 Rev 2

STM32F479xx

Description

1

Description

®

The STM32F479xx devices are based on the high-performance ARM Cortex -M4 32-bit

®

RISC core operating at a frequency of up to 180 MHz. The Cortex -M4 core features a

®

Floating point unit (FPU) single precision which supports all ARM single-precision data-

processing instructions and data types. It also implements a full set of DSP instructions and

a memory protection unit (MPU) which enhances application security.

The STM32F479xx devices incorporate high-speed embedded memories (Flash memory

up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an

extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB

buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose

16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,

a true random number generator (RNG), and a cryptographic acceleration cell. They also

feature standard and advanced communication interfaces:

2

•

Up to three I Cs

2

Six SPIs, two I Ss full duplex. To achieve audio class accuracy, the I S peripherals can

be clocked via a dedicated internal audio PLL or via an external clock to allow

synchronization.

•

Four USARTs plus four UARTs

An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the

ULPI),

•

Two CANs

One SAI serial audio interface

An SDMMC host interface

Ethernet and camera interface

LCD-TFT display controller

Chrom-ART Accelerator™

DSI Host.

Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)

interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a

cryptographic acceleration cell. Refer to Table 2 for the list of peripherals available on each

part number.

The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to

3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full

speed mode, is available on all packages.

The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of

power-saving mode allows the design of low-power applications.

The STM32F479xx devices are offered in 5 packages, ranging from 168 pins to 216 pins.

The set of included peripherals changes with the device chosen, according to Table 2.

DocID028010 Rev 2

11/208

44

Description

STM32F479xx

These features make the STM32F479xx microcontrollers suitable for a wide range of

applications:

•

Motor drive and application control

Medical equipment

Industrial applications: PLC, inverters, circuit breakers

Printers, and scanners

Alarm systems, video intercom, and HVAC

Home audio appliances

Figure 5 shows the general block diagram of the device family.

Table 2. STM32F479xx features and peripheral counts

Peripherals

STM32F479Ax STM32F479Ix STM32F479Bx STM32F479Nx

1024 2048 1024 2048 1024 2048 1024 2048

Flash memory in Kbytes

System

384(160+32+128+64)

SRAM in

Kbytes

Backup

4

FMC memory controller

Quad-SPI

Yes

Ethernet

No

General-

purpose

10

2

Timers

Advanced-

control

Basic

2

Random number generator

Yes

SPI / I²S

I²C

6/2(full duplex)⁽¹⁾

3

USART/UART

4/4

Yes

2

USB OTG FS

USB OTG HS

CAN

Communication

interfaces

SAI

1

SDIO

Yes

Camera interface

MIPI-DSI Host

LCD-TFT

Chrom-ART Accelerator™

(DMA2D)

Yes

Cryptography

GPIOs

114

131

161

12/208

DocID028010 Rev 2

STM32F479xx

Description

Table 2. STM32F479xx features and peripheral counts (continued)

Peripherals

STM32F479Ax STM32F479Ix STM32F479Bx STM32F479Nx

3

12-bit ADC

Number of channels

24

12-bit DAC

Number of channels

Yes

2

Maximum CPU frequency

Operating voltage

180 MHz

1.7 to 3.6V⁽²⁾

Ambient operating temperature: −40 to 85 °C / −40 to 105 °C

Junction temperature: −40 to 105 °C / −40 to 125 °C

Operating temperatures

Package

UFBGA169

WLCSP168

LQFP176

UFBGA176

LQFP208

TFBGA216

1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the

I2S audio mode.

2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).

DocID028010 Rev 2

13/208

44

Description

STM32F479xx

1.1

Compatibility throughout the family

STM32F479xx devices are not compatible with other STM32F4xx devices. Figure 1 and

Figure 2 show incompatible board designs, respectively, for LQFP176 and LQFP208

packages (highlighted pins). The UFBGA176 and TFBGA216 ballouts are compatible with

other STM32F4xx devices, only few IO port pins are substituted, as shown in Figure 3 and

Figure 4. The UFBGA169 package is incompatible with other STM32F4xx devices.

1.1.1

LQFP176 package

Figure 1. Incompatible board design for LQFP176 package

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06ꢀꢁꢂꢃꢄ9ꢅ

1. Pins from 86 to 133 are not compatible.

14/208

DocID028010 Rev 2

STM32F479xx

Description

1.1.2

LQFP208 package

Figure 2. Incompatible board design for LQFP208 package

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06ꢀꢁꢂꢃꢆ9ꢅ

1. Pins from 118 to 128 and pin 137 are not compatible

DocID028010 Rev 2

15/208

44

Description

STM32F479xx

1.1.3

UFBGA176 package

Figure 3. UFBGA176 port-to-terminal assignment differences

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06ꢀꢃꢄꢇꢀ9ꢅ

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

16/208

DocID028010 Rev 2

STM32F479xx

Description

1.1.4

TFBGA216 package

Figure 4. TFBGA216 port-to-terminal assignment differences

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06Yꢀꢃꢄꢇꢄ9ꢅ

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

DocID028010 Rev 2

17/208

44

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Description

STM32F479xx

Figure 5. STM32F479xx block diagram

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1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to

APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration

in the RCC_DCKCFGR register.

18/208

DocID028010 Rev 2

STM32F479xx

Functional overview

2

Functional overview

2.1

ARM^®Cortex^®-M4 with FPU and embedded Flash and SRAM

®

The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

®

The ARM Cortex -M4 with FPU core is a 32-bit RISC processor that features exceptional

code-efficiency, delivering the high-performance expected from an ARM core in the memory

size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

The STM32F47x line is compatible with all ARM tools and software.

Figure 5 shows the general block diagram of the STM32F47x line.

®

Note:

Cortex -M4 with FPU core is binary compatible with the Cortex -M3 core.

2.2

Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard

®

ARM Cortex -M4 with FPU processors. It balances the inherent performance advantage

®

of the ARM Cortex -M4 with FPU over Flash memory technologies, which normally require

the processor to wait for the Flash memory at higher frequencies.

To release the processor full 225 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

®

execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 180 MHz.

2.3

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

2.4

Embedded Flash memory

The devices embed a Flash memory of up to 2 Mbytes available for storing programs and

data.

2.5

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

2.6

Embedded SRAM

All devices embed:

•

Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)

data RAM

RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.

4 Kbytes of backup SRAM

•

This area is accessible only from the CPU. Its content is protected against possible

unwanted write accesses, and is retained in Standby or VBAT mode.

2.7

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB

HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB

and APB peripherals) and ensures a seamless and efficient operation even when several

high-speed peripherals work simultaneously.

20/208

DocID028010 Rev 2

STM32F479xx

Functional overview

Figure 6. STM32F479xx Multi-AHB matrix

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2.8

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

The DMA can be used with the main peripherals:

2

•

SPI and I S

2

I C

USART

General-purpose, basic and advanced-control timers TIMx

DAC

SDIO

Camera interface (DCMI)

ADC

SAI1

QUADSPI.

2.9

Flexible Memory Controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:

•

The NOR/PSRAM memory controller

The NAND/memory controller

The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

NOR Flash memory/OneNAND Flash memory

PSRAM

NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

•

Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

8-,16-,32-bit data bus width

Independent Chip Select control for each memory bank

Independent configuration for each memory bank

Write FIFO

Read FIFO for SDRAM controller

The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is

HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost

effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

22/208

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Functional overview

2.10

Quad-SPI memory interface (QUADSPI)

All STM32F479xx devices embeds a Quad-SPI memory interface, which is a specialized

communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can

work in direct mode through registers, external flash status register polling mode and

memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting

8, 16 and 32-bit access. Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in

Single Data Rate or Dual Data Rate.

2.11

LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)

and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

XGA (1024x768) resolution with the following features:

•

2 displays layers with dedicated FIFO (64x32-bit)

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

Up to 8 Input color formats selectable per layer

Flexible blending between two layers using alpha value (per pixel or constant)

Flexible programmable parameters for each layer

Color keying (transparency color)

Up to 4 programmable interrupt events.

2.12

DSI Host (DSIHOST)

®

The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It

includes a dedicated video interface internally connected to the LTDC and a generic APB

interface that can be used to transmit information to the display.

These interfaces are as follows:

•

LTDC interface:

–

Used to transmit information in Video Mode, in which the transfers from the host

processor to the peripheral take the form of a real-time pixel stream (DPI).

–

Through a customized for mode, this interface can be used to transmit information

in full bandwidth in the Adapted Command Mode (DBI).

APB slave interface:

–

Allows the transmission of generic information in Command mode, and follows a

proprietary register interface.

–

Can operate concurrently with either LTDC interface in either Video Mode or

Adapted Command Mode.

Video mode pattern generator:

–

Allows the transmission of horizontal/vertical color bar and D-PHY BER testing

pattern without any kind of stimuli.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

The DSI Host main features:

®

•

Compliant with MIPI Alliance standards

®

Interface with MIPI D-PHY

®

Supports all commands defined in the MIPI Alliance specification for DCS:

–

Transmission of all Command mode packets through the APB interface

Transmission of commands in low-power and high-speed during Video Mode

•

Supports up to two D-PHY data lanes

Bidirectional communication and escape mode support through data lane 0

Supports non-continuous clock in D-PHY clock lane for additional power saving

Supports Ultra Low-Power mode with PLL disabled

ECC and Checksum capabilities

Support for End of Transmission Packet (EoTp)

Fault recovery schemes

3D transmission support

Configurable selection of system interfaces:

–

AMBA APB for control and optional support for Generic and DCS commands

Video Mode interface through LTDC

Adapted Command Mode interface through LTDC

•

Independently programmable Virtual Channel ID in

–

Video Mode

Adapted Command Mode

APB Slave

Video Mode interfaces features:

•

LTDC interface color coding mappings into 24-bit interface:

–

16-bit RGB, configurations 1, 2, and 3

18-bit RGB, configurations 1 and 2

24-bit RGB

•

Programmable polarity of all LTDC interface signals

Extended resolutions beyond the DPI standard maximum resolution of 800x480 pixels:

maximum resolution is limited by available DSI physical link bandwidth:

–

Number of lanes: 2

Maximum speed per lane: 500Mbps

Adapted interface features:

•

Support for sending large amounts of data through the memory_write_start (WMS) and

memory_write_continue (WMC) DCS commands

•

LTDC interface color coding mappings into 24-bit interface:

–

16-bit RGB, configurations 1, 2, and 3

18-bit RGB, configurations 1 and 2

24-bit RGB

24/208

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STM32F479xx

Functional overview

Video mode pattern generator:

•

Vertical and horizontal color bar generation without LTDC stimuli

BER pattern without LTDC stimuli

2.13

Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

Rectangle copy

Rectangle copy with pixel format conversion

Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

2.14

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

®

and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex -

M4 with FPU core.

•

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support tail chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

2.15

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected

to the 16 external interrupt lines.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

2.16

Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator

or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is

detected, the system automatically switches back to the internal RC oscillator and a

software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing

to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL

clock entry is available when necessary (for example if an indirectly used external oscillator

fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio

2

class performance. In this case, the I S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

2.17

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory

through a serial interface. Refer to application note AN2606 for details.

2.18

Power supply schemes

•

V

= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

DD

enabled), provided externally through V pins.

DD

•

V

, V

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

DDA

SSA

blocks, RCs and PLL. V

and V

must be connected to V and V , respectively.

DDA

SSA DD SS

Note:

V

/V

minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

DD DDA

Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.

•

V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V is not present.

DD

•

V

can be connected either to VDD or an external independent power supply (3.0

DDUSB

to 3.6V) for USB transceivers.

For example, when device is powered at 1.8V, an independent power supply 3.3V can

be connected to V

. When the V

is connected to a separated power supply,

DDUSB

it is independent from V or V

but it must be the last supply to be provided and the

DD

DDA

first to disappear.

26/208

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STM32F479xx

Functional overview

The following conditions must be respected:

–

During power-on phase (V < V

), V should be always lower than

DDUSB

DD

DD_MIN

V

DD

–

During power-down phase (V < V

), V

should be always lower than

DD

DD_MIN

DDUSB

V

DD

–

V

rising and falling time rate specifications must be respected.

DDUSB

In operating mode phase, V

could be lower or higher than VDD:

DDUSB

– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

are operating between V and V .The V

V

DDUSB

DDUSB_MIN

DDUSB_MAX

DDUSB

supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

– If only one USB transceiver is used in the application, the GPIOs associated to

the other USB transceiver are still supplied by V

.

DDUSB

– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered

by V are operating between V and V

.

DD_MAX

DDUSB

DD_MIN

Figure 7. V

connected to an external independent power supply

DDUSB

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The DSI (Display Serial Interface) sub-system uses several power supply pins which are

independent from the other supply pins:

•

VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-

PHY. This supply must be connected to global VDD.

VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally

to VDD12DSI.

VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes

pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.

•

VSSDSI pin is an isolated supply ground used for DSI sub-system.

If DSI functionality is not used at all, then:

–

VDDDSI pin must be connected to global VDD.

VCAPDSI pin must be connected externally to VDD12DSI but the external

capacitor is no more needed.

–

VSSDSI pin must be grounded.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

2.19

Power supply supervisor

2.19.1

Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On the other package, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default BOR

thresholds, or to disable BOR permanently. Three BOR thresholds are available through

option bytes. The device remains in reset mode when V is below a specified threshold,

DD

V

or V

, without the need for an external reset circuit.

POR/PDR

BOR

The device also features an embedded programmable voltage detector (PVD) that monitors

the V /V power supply and compares it to the V threshold. An interrupt can be

DD DDA

PVD

generated when V /V

drops below the V

threshold and/or when V /V

is

DD DDA

PVD

DD DDA

higher than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

2.19.2

Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on

reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V and NRST and should maintain

DD

the device in reset mode as long as V is below a specified threshold. PDR_ON must be

DD

connected to VSS, as shown in Figure 8.

Figure 8. Power supply supervisor interconnection with internal reset OFF

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The V specified threshold, below which the device must be maintained under reset, is

DD

1.7 V (see Figure 9).

A comprehensive set of power-saving mode allows to design low-power applications.

28/208

DocID028010 Rev 2

STM32F479xx

Functional overview

When the internal reset is OFF, the following integrated features are no more supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

The brownout reset (BOR) circuitry must be disabled

The embedded programmable voltage detector (PVD) is disabled

V

functionality is no more available and V

pin should be connected to V

.

DD

BAT

All packages allow to disable the internal reset through the PDR_ON signal when connected

to VSS.

Figure 9. PDR_ON control with internal reset OFF

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1. PDR_ON signal to be kept always low.

2.20

Voltage regulator

The regulator has four operating modes:

•

Regulator ON

–

Main regulator mode (MR)

Low power regulator (LPR)

Power-down

•

Regulator OFF

2.20.1

Regulator ON

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

DocID028010 Rev 2

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44

Functional overview

STM32F479xx

There are three power modes configured by software when the regulator is ON:

•

MR mode used in Run/sleep modes or in Stop modes

–

In Run/Sleep mode

The MR mode is used either in the normal mode (default mode) or the over-drive

mode (enabled by software). Different voltages scaling are provided to reach the

best compromise between maximum frequency and dynamic power consumption.

The over-drive mode allows operating at a higher frequency than the normal mode

for a given voltage scaling.

–

In Stop modes

The MR can be configured in two ways during stop mode:

MR operates in normal mode (default mode of MR in stop mode)

MR operates in under-drive mode (reduced leakage mode).

•

LPR is used in the Stop modes:

The LP regulator mode is configured by software when entering Stop mode.

Like the MR mode, the LPR can be configured in two ways during stop mode:

–

LPR operates in normal mode (default mode when LPR is ON)

LPR operates in under-drive mode (reduced leakage mode).

Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator

output is in high impedance and the kernel circuitry is powered down, inducing zero

consumption. The contents of the registers and SRAM are lost.

Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.

Two external ceramic capacitors should be connected on V

and V

pin. Refer to

CAP_1

CAP_2

Section 2.18 and Table 123.

All packages have the regulator ON feature.

(1)

Table 3. Voltage regulator configuration mode versus device operating mode

Voltage regulator

Run mode

Sleep mode

Stop mode

Standby mode

configuration

Normal mode

MR

-

MR

-

MR or LPR

-

Over-drive

mode⁽²⁾

-

Under-drive mode

MR or LPR

-

Power-down

mode

-

Yes

1. ‘-’ means that the corresponding configuration is not available.

2. The over-drive mode is not available when V_DD= 1.7 to 2.1 V.

2.20.2

Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is

disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply

externally a V voltage source through V

and V

pins.

12

CAP_1

CAP_2

30/208

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STM32F479xx

Functional overview

Since the internal voltage scaling is not managed internally, the external voltage value must

be aligned with the targeted maximum frequency. Refer to Operating conditions.The two

2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer

to Section 2.18.

When the regulator is OFF, there is no more internal monitoring on V . An external power

12

supply supervisor should be used to monitor the V of the logic power domain. PA0 pin

12

should be used for this purpose, and act as power-on reset on V power domain.

12

In regulator OFF mode, the following features are no more supported:

•

PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power

domain which is not reset by the NRST pin.

12

•

As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As

a consequence, PA0 and NRST pins must be managed separately if the debug

connection under reset or pre-reset is required.

•

The over-drive and under-drive modes are not available.

The Standby mode is not available.

Figure 10. Regulator OFF

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The following conditions must be respected:

•

V

should always be higher than V

and V

to avoid current injection

CAP_2

DD

CAP_1

between power domains.

•

If the time for V and V

to reach V minimum value is faster than the time for

CAP_1

CAP_2

12

V

to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V

DD

CAP_1

and V

reach V minimum value and until V reaches 1.7 V (see Figure 11).

12 DD

CAP_2

•

Otherwise, if the time for V

and V

to reach V minimum value is slower

CAP_2 12

CAP_1

than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see

DD

Figure 12).

If V

and V

go below V minimum value and V is higher than 1.7 V, then a

CAP_2 12 DD

CAP_1

reset must be asserted on PA0 pin.

Note:

The minimum value of V depends on the maximum frequency targeted in the application

12

(see Operating conditions).

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44

Functional overview

STM32F479xx

Figure 11. Startup in regulator OFF: slow V slope

DD

- power-down reset risen after V

, V

stabilization

CAP_1

CAP_2

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1. This figure is valid whatever the internal reset mode (ON or OFF).

Figure 12. Startup in regulator OFF mode: fast V slope

DD

- power-down reset risen before V

, V

stabilization

CAP_1

CAP_2

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1. This figure is valid whatever the internal reset mode (ON or OFF).

2.20.3

Regulator ON/OFF and internal reset ON/OFF availability

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package

Regulator ON

Regulator OFF

Internal reset ON Internal reset OFF

WLCSP168

UFBGA169

LQFP208

Yes

No

Yes

PDR_ON set to V_DDPDR_ON set to V_SS

Yes

LQFP176

UFBGA176

TFBGA216

BYPASS_REG set BYPASS_REG set

to V_SS

to V_DD

32/208

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Functional overview

2.21

Real-time clock (RTC), backup SRAM and backup registers

The backup domain includes:

•

The real-time clock (RTC)

4 Kbytes of backup SRAM

20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain

the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-

coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are

performed automatically. The RTC provides a programmable alarm and programmable

periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is

also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC

has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz

output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can

be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit

programmable binary auto-reload downcounter with programmable resolution is available

and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a

time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data

which need to be retained in VBAT and standby mode. This memory area is disabled by

default to minimize power consumption (see Section 2.22). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data

when V power is not present. Backup registers are not reset by a system, a power reset,

DD

or when the device wakes up from the Standby mode (see Section 2.22).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,

hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is

powered either from the V supply when present or from the V

pin.

DD

BAT

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Functional overview

STM32F479xx

2.22

Low-power modes

The devices support three low-power modes to achieve the best compromise between low

power consumption, short startup time and available wakeup sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled.

The voltage regulator can be put either in main regulator mode (MR) or in low-power

mode (LPR). Both modes can be configured as follows (see Table 5):

–

Normal mode (default mode when MR or LPR is enabled)

Under-drive mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /

tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

Table 5. Voltage regulator modes in stop mode

Voltage regulator

Main regulator (MR)

Low-power regulator (LPR)

configuration

Normal mode

MR ON

LPR ON

Under-drive mode

MR in under-drive mode

LPR in under-drive mode

•

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the

backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,

a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event

occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed

and the 1.2 V domain is controlled by an external power.

2.23

V_BAToperation

The V

pin allows to power the device V

domain from an external battery, an external

BAT

supercapacitor, or from V when no external battery and an external supercapacitor are

DD

present.

V

operation is activated when V is not present.

DD

BAT

The V

pin supplies the RTC, the backup registers and the backup SRAM.

BAT

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Functional overview

Note:

When the microcontroller is supplied from V , external interrupts and RTC alarm/events

BAT

do not exit it from V

operation.

BAT

When PDR_ON pin is connected to V (Internal Reset OFF), the V

functionality is no

BAT

SS

more available and V

pin should be connected to VDD.

BAT

2.24

Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic

timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 6 compares the features of the advanced-control, general-purpose and basic timers.

Table 6. Timer feature comparison

Max

DMA

request

generation channels

Capture/

compare

Timer

type

Counter Counter Prescaler

Complementary interface timer

Timer

resolution

type

factor

output

clock

(MHz) (MHz)

clock

(1)

Up,

Down,

Up/down and 65536

Anyinteger

between 1

Advanced TIM1,

16-bit

32-bit

16-bit

Yes

No

4

2

1

2

1

0

Yes

No

90

45

90

45

180

control

TIM8

Up,

Down,

Up/down and 65536

Anyinteger

between 1

TIM2,

TIM5

90/180

180

Up,

Down,

Up/down and 65536

Anyinteger

between 1

TIM3,

TIM4

Anyinteger

between 1

and 65536

TIM9

Up

General

purpose

TIM10

,

Anyinteger

between 1

and 65536

No

180

TIM11

Anyinteger

between 1

and 65536

TIM12

No

90/180

TIM13

,

TIM14

Anyinteger

between 1

and 65536

No

Anyinteger

between 1

and 65536

TIM6,

TIM7

Basic

Yes

1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the

RCC_DCKCFGR register.

2.24.1

Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators

multiplexed on 6 channels. They have complementary PWM outputs with programmable

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Functional overview

STM32F479xx

inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

•

Input capture

Output compare

PWM generation (edge- or center-aligned modes)

One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link

feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

2.24.2

General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F47x devices

(see Table 6 for differences).

•

TIM2, TIM3, TIM4, TIM5

The STM32F47x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,

and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down

counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-

reload up/down counter and a 16-bit prescaler. They all feature 4 independent

channels for input capture/output compare, PWM or one-pulse mode output. This gives

up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the

other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the

Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are

capable of handling quadrature (incremental) encoder signals and the digital outputs

from 1 to 4 hall-effect sensors.

•

TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9

and TIM12 have two independent channels for input capture/output compare, PWM or

one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5

full-featured general-purpose timers. They can also be used as simple time bases.

2.24.3

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be

used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

2.24.4

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC and as it operates independently from the

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Functional overview

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes.

2.24.5

2.24.6

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

downcounter. It features:

•

A 24-bit downcounter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source.

2.25

Inter-integrated circuit interface (I²C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can

support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the

7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC

generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

The devices also include programmable analog and digital noise filters (see Table 7).

Table 7. Comparison of I2C analog and digital filters

Analog filter

Digital filter

Pulse width of

suppressed spikes

Programmable length from 1 to 15

I2C peripheral clocks

≥ 50 ns

2.26

Universal synchronous/asynchronous receiver transmitters

(USART)

The devices embed four universal synchronous/asynchronous receiver transmitters

(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver

transmitters (UART4, UART5, UART7, and UART8).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to

communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate

at up to 5.62 bit/s.

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USART1, USART2, USART3 and USART6 also provide hardware management of the CTS

and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication

capability. All interfaces can be served by the DMA controller.

(1)

Table 8. USART feature comparison

Max. baud

USART Standard

Modem

SPI

master

Smartcard rate in Mbit/s rate in Mbit/s APB

(ISO 7816) (oversampling (oversampling mapping

LIN

irDA

name

features (RTS/CTS)

by 16)

by 8)

APB2

(max.

90 MHz)

USART1

USART2

USART3

UART4

X

-

X

-

X

-

5.62

11.25

APB1

(max.

45 MHz)

2.81

5.62

2.81

5.62

11.25

5.62

APB1

(max.

45 MHz)

APB1

(max.

45 MHz)

APB1

(max.

45 MHz)

UART5

-

APB2

(max.

90 MHz)

USART6

UART7

X

-

X

-

X

-

APB1

(max.

45 MHz)

APB1

(max.

UART8

-

45 MHz)

1. X = feature supported.

2.27

Serial peripheral interface (SPI)

The devices feature up to six SPIs in slave and master modes in full-duplex and simplex

communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,

SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master

mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master

mode and slave mode.

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2.28

Inter-integrated sound (I²S)

2

Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available. They can be

operated in master or slave mode, in full duplex and simplex communication modes, and

can be configured to operate with a 16-/32-bit resolution as an input or output channel.

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of

2

the I S interfaces is/are configured in master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

Note:

For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port

B and GPIO Port D.

2.29

Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can

operate as transmitter or receiver with their FIFO. Many audio protocols are supported by

each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks

can be configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is

required.

SAI1 can be served by the DMA controller.

2.30

Audio PLL (PLLI2S)

2

The devices feature an additional dedicated PLL for audio I S and SAI applications. It allows

2

to achieve error-free I S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

2

The PLLI2S configuration can be modified to manage an I S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

2

I S/SAI flow with an external PLL (or Codec output).

2.31

Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the

PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the LCD-TFT clock.

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2.32

Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital

protocol Rev1.1.

2.33

Ethernet MAC interface with dedicated DMA and IEEE 1588

support

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for

ethernet LAN communications through an industry-standard medium-independent interface

(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an

external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,

fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals

for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

The devices include the following features:

•

Supports 10 and 100 Mbit/s rates

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors (see the STM32F4xx reference manual for details)

•

Tagged MAC frame support (VLAN support)

Half-duplex (CSMA/CD) and full-duplex operation

MAC control sublayer (control frames) support

32-bit CRC generation and removal

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes.

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

Triggers interrupt when system time becomes greater than target time

2.34

Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

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Functional overview

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

2.35

Universal serial bus on-the-go full-speed (OTG_FS)

The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

The major features are:

•

Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

12 host channels with periodic OUT support

Software configurable to OTG1.3 and OTG2.0 modes of operation

USB 2.0 LPM (Link Power Management) support

Internal FS OTG PHY support

HNP/SNP/IP inside (no need for any external resistor)

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

2.36

Universal serial bus on-the-go high-speed (OTG_HS)

The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.

The USB OTG HS supports both full-speed and high-speed operations. It integrates the

transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)

for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an

external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

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44

Functional overview

STM32F479xx

The major features are:

•

Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

8 bidirectional endpoints

16 host channels with periodic OUT support

Software configurable to OTG1.3 and OTG2.0 modes of operation

USB 2.0 LPM (Link Power Management) support

Internal FS OTG PHY support

External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

HNP/SNP/IP inside (no need for any external resistor)

for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

2.37

Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS

sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera

interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

•

Programmable polarity for the input pixel clock and synchronization signals

Parallel data communication can be 8-, 10-, 12- or 14-bit

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

Capability to automatically crop the image black & white.

2.38

Cryptographic accelerator

The devices embed a cryptographic accelerator. This cryptographic accelerator provides a

set of hardware acceleration for the advanced cryptographic algorithms usually needed to

provide confidentiality, authentication, data integrity and non repudiation when exchanging

messages with a peer.

•

These algorithms consists of:

Encryption/Decryption

–

DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-

,128- or 192-bit key

AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter

mode) chaining algorithms, 128, 192 or 256-bit key

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Functional overview

Universal hash

–

SHA-1 and SHA-2 (secure hash algorithms)

MD5

HMAC

The cryptographic accelerator supports DMA request generation.

2.39

2.40

Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 90 MHz.

2.41

Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16

external channels, performing conversions in the single-shot or scan mode. In scan mode,

automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very

precise monitoring of the converted voltage of one, some or all selected channels. An

interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

2.42

Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The

conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally

connected to the same input channel as V , ADC1_IN18, which is used to convert the

BAT

sensor output voltage into a digital value. When the temperature sensor and V

BAT

conversion are enabled at the same time, only V

conversion is performed.

BAT

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44

Functional overview

STM32F479xx

As the offset of the temperature sensor varies from chip to chip due to process variation, the

internal temperature sensor is mainly suitable for applications that detect temperature

changes instead of absolute temperatures. If an accurate temperature reading is needed,

then an external temperature sensor part should be used.

2.43

Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two

analog voltage signal outputs.

This dual digital Interface supports the following features:

•

two DAC converters: one for each output channel

8-bit or 10-bit monotonic output

left or right data alignment in 12-bit mode

synchronized update capability

noise-wave generation

triangular-wave generation

dual DAC channel independent or simultaneous conversions

DMA capability for each channel

external triggers for conversion

input voltage reference V

REF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through

the timer update outputs that are also connected to different DMA streams.

2.44

2.45

Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could

be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to

switch between JTAG-DP and SW-DP.

Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data

flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F47x through a small number of ETM pins to an external hardware trace port

analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or

any other high-speed channel. Real-time instruction and data flow activity can be recorded

and then formatted for display on the host computer that runs the debugger software. TPA

hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

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Pinouts and pin description

3

Pinouts and pin description

Figure 13. STM32F47x WLCSP168 pinout

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DocID028010 Rev 2

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79

Pinouts and pin description

STM32F479xx

Figure 14. STM32F47x UFBGA169 ballout

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46/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Figure 15. STM32F47x UFBGA176 ballout

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1. The above figure shows the package top view.

DocID028010 Rev 2

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79

Pinouts and pin description

STM32F479xx

Figure 16. STM32F47x LQFP176 pinout

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3,ꢅꢇ

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9''86%

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3)ꢀ

3*ꢉ

3)ꢄ

3*ꢆ

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3*ꢄ

966

9''

3)ꢉ

3*ꢀ

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3*ꢂ

966'6,

'6,+267B'ꢅ1

'6,+267B'ꢅ3

9''ꢅꢂ'6,

'6,+267B&.1

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'6,+267B'ꢇ1

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966$

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9''$

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ꢃꢈ

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ꢃꢉ

966

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3'ꢅꢂ

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06ꢀꢀꢁꢈꢇ9ꢀ

1. The above figure shows the package top view.

48/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Figure 17. STM32F47x LQFP208 pinout

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3(ꢀ

3(ꢄ

3(ꢆ

3(ꢉ

9%$7

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3+ꢅꢆ

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3+ꢅꢄ

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ꢁ

966

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ꢆꢇ

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966

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966$

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966

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9''

3%ꢅꢄ

3%ꢅꢀ

06Yꢀꢀꢁꢈꢉ9ꢆ

1. The above figure shows the package top view.

DocID028010 Rev 2

49/208

79

Pinouts and pin description

STM32F479xx

Figure 18. STM32F47x TFBGA216 ballout

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3.ꢀ

3-ꢅꢄ

3*ꢃ

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3'ꢀ

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3,ꢃ

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966

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3$ꢁ

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9''ꢅꢂ

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86%

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3&ꢈ

3&ꢉ

3*ꢉ

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966

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966

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3&ꢇ

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3$ꢂ

3$ꢀ

3&ꢅ

3$ꢇ

3$ꢉ

3&ꢂ

3$ꢄ

3$ꢆ

3%ꢂ

3&ꢄ

3&ꢆ

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3)ꢅꢀ

3)ꢅꢄ

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3*ꢇ

3-ꢂ

3)ꢅꢆ

3-ꢀ

3-ꢄ

3(ꢁ

3(ꢃ

3'ꢅꢂ

3'ꢅꢅ

3(ꢅꢅ

3(ꢅꢂ

3'ꢅꢀ

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3*ꢀ

3*ꢄ

3*ꢂ

3+ꢈ

3+ꢉ

3-ꢆ

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3+ꢅꢅ

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1

3

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3)ꢅꢅ

3%ꢅꢇ

3+ꢁ

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3$ꢈ

3%ꢅ

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3-ꢅ

3(ꢈ

3(ꢅꢇ

3(ꢅꢆ

3(ꢅꢀ

3%ꢅꢅ

3%ꢅꢄꢍꢍ

3%ꢅꢆꢍꢍ

5

06Yꢀꢀꢁꢈꢅ9ꢄ

1. The above figure shows the package top view.

50/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 9. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function during and after

reset is the same as the actual pin name

Pin name

S

I

Supply pin

Input only pin

Pin type

I/O

FT

TTa

B

Input / output pin

5 V tolerant I/O

3.3 V tolerant I/O directly connected to analog parts

Dedicated BOOT0 pin

I/O structure

Notes

RST

Bidirectional reset pin with weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Functions selected through GPIOx_AFR registers

Alternate

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

DocID028010 Rev 2

51/208

79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TRACECLK, SPI4_SCK,

SAI1_MCLK_A,

B2

F9

A2

1

A3

PE2

I/O FT

-

QUADSPI_BK1_IO2,

ETH_MII_TXD3,

-

FMC_A23, EVENTOUT

TRACED0, SAI1_SD_B,

FMC_A19, EVENTOUT

C1 E10 A1

C2 C11 B1

2

3

2

3

A2

A1

PE3

PE4

I/O FT

-

TRACED1, SPI4_NSS,

SAI1_FS_A, FMC_A20,

DCMI_D4, LCD_B0,

EVENTOUT

TRACED2, TIM9_CH1,

SPI4_MISO,

D1 B12 B2

4

5

4

5

B1

B2

PE5

PE6

I/O FT

-

SAI1_SCK_A, FMC_A21,

DCMI_D6, LCD_G0,

EVENTOUT

-

TRACED3, TIM9_CH2,

SPI4_MOSI, SAI1_SD_A,

FMC_A22, DCMI_D7,

LCD_G1, EVENTOUT

D2 D11 B3

-

G6

F5

C1

VSS

VDD

VBAT

S

-

E5 C12 C1

6

RTC_TAMP1/

RTC_TAMP2/

RTC_TS

(2)

(3)

-

D2

7

8

9

7

8

9

C2

D1

E1

PI8

I/O FT

EVENTOUT

RTC_TAMP1/

RTC_TS/

RTC_OUT

(2)

(3)

G4 D12 D1

E1 E11 E1

F1 E12 F1

PC13

PC14-

OSC32_IN

(PC14)

(2)

(3)

OSC32_IN

PC15-

OSC32_OUT I/O FT

(PC15)

(2)

(3)

10

-

10

-

F1

G5

E4

EVENTOUT

-

OSC32_OUT

-

VDD

S

-

CAN1_RX, FMC_D30,

LCD_VSYNC,

E2

G9

D3

11

PI9

I/O FT

EVENTOUT

52/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

ETH_MII_RX_ER,

FMC_D31, LCD_HSYNC,

EVENTOUT

E4 F10 E3

F2 F11 E4

12

13

12

13

D5

F3

PI10

PI11

I/O FT

-

LCD_G6,

OTG_HS_ULPI_DIR,

EVENTOUT

F5 F12 F2

F4 G11 F3

14

15

14

15

F2

F4

VSS

VDD

S

-

I2C2_SDA, FMC_A0,

EVENTOUT

F3 G10 E2

G3 H10 H3

G5 G12 H2

16

17

18

-

16

17

18

19

20

D2

E2

G2

E3

G3

PF0

PF1

PF2

PI12

PI13

I/O FT

-

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

LCD_HSYNC,

EVENTOUT

-

LCD_VSYNC,

EVENTOUT

-

21

22

23

24

25

26

H3

H2

J2

PI14

PF3

PF4

PF5

VSS

VDD

I/O FT

LCD_CLK, EVENTOUT

-

(4)

H4 H11 J2

L4 J10 J3

H3 H12 K3

19

20

21

FMC_A3, EVENTOUT

ADC3_IN9

FMC_A4, EVENTOUT

ADC3_IN14

K3

H6

H5

FMC_A5, EVENTOUT

ADC3_IN15

G7 J11 G2 22

G8 J12 G3 23

S

-

TIM10_CH1, SPI5_NSS,

SAI1_SD_B, UART7_Rx,

QUADSPI_BK1_IO3,

EVENTOUT

(4)

-

K2

K1

24

25

27

28

K2

K1

PF6

PF7

I/O FT

ADC3_IN4

ADC3_IN5

TIM11_CH1, SPI5_SCK,

SAI1_MCLK_B,

UART7_Tx,

(4)

QUADSPI_BK1_IO2,

EVENTOUT

SPI5_MISO,

SAI1_SCK_B,

TIM13_CH1,

(4)

-

L3

26

29

L3

PF8

I/O FT

ADC3_IN6

QUADSPI_BK1_IO0,

EVENTOUT

DocID028010 Rev 2

53/208

79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

SPI5_MOSI, SAI1_FS_B,

TIM14_CH1,

QUADSPI_BK1_IO1,

EVENTOUT

(4)

-

L2

27

28

30

L2

PF9

I/O FT

ADC3_IN7

ADC3_IN8

QUADSPI_CLK,

DCMI_D11, LCD_DE,

EVENTOUT

(4)

H1 K10 L1

31

32

L1

PF10

I/O FT

PH0-OSC_IN

(PH0)

G2 K11 G1 29

G1

-

EVENTOUT

OSC_IN

PH1-OSC_OUT

(PH1)

G1 K12 H1

30

31

33

34

H1

J1

I/O FT

-

OSC_OUT

H2

M1

H9

J9

J1

NRST

I/O RST

OTG_HS_ULPI_STP,

FMC_SDNWE, LCD_R5, ADC123_IN10

EVENTOUT

(4)

M2 32

35

36

M2

M3

PC0

I/O FT

TRACED0,

SPI2_MOSI/I2S2_SD,

SAI1_SD_A, ETH_MDC,

(4)

N1 L12 M3 33

PC1

PC2

ADC123_IN11

EVENTOUT

SPI2_MISO, I2S2ext_SD,

OTG_HS_ULPI_DIR,

(4)

-

M4 34

37

38

M4

L4

I/O FT

ETH_MII_TXD2,

FMC_SDNE0,

EVENTOUT

ADC123_IN12

ADC123_IN13

SPI2_MOSI/I2S2_SD,

OTG_HS_ULPI_NXT,

ETH_MII_TX_CLK,

FMC_SDCKE0,

M5 35

PC3

I/O FT

EVENTOUT

-

36

-

39

-

J5

J6

VDD

VSS

S

-

J2

-

L11 M1 37

40

-

M1

N1

P1

R1

VSSA

VREF-

VREF+

VDDA

-

N1

P1

-

38

39

41

42

J3 M12 R1

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

USART2_CTS,

PA0-

WKUP(PA0)

ADC123_IN0,

WKUP

(5)

J5

L10 N3

40

43

N3

I/O FT

UART4_TX,

ETH_MII_CRS,

EVENTOUT

54/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM2_CH2, TIM5_CH2,

USART2_RTS,

UART4_RX,

(4)

K1

K2

K9

L9

N2

P2

41

44

N2

PA1

I/O FT

QUADSPI_BK1_IO3,

ETH_MII_RX_CLK/ETH_

RMII_REF_CLK, LCD_R2,

EVENTOUT

ADC123_IN1

TIM2_CH3, TIM5_CH3,

TIM9_CH1, USART2_TX,

ETH_MDIO, LCD_R1,

EVENTOUT

42

43

45

46

47

P2

K4

J4

PA2

PH2

PH3

I/O FT

ADC123_IN2

QUADSPI_BK2_IO0,

ETH_MII_CRS,

FMC_SDCKE0, LCD_R0,

EVENTOUT

L2 M11 F4

-

QUADSPI_BK2_IO1,

ETH_MII_COL,

FMC_SDNE0, LCD_R1,

EVENTOUT

L1 N12 G4 44

I2C2_SCL, LCD_G5,

OTG_HS_ULPI_NXT,

LCD_G4, EVENTOUT

M2 M10 H4

45

46

48

49

H4

J3

PH4

PH5

I/O FT

-

I2C2_SDA, SPI5_NSS,

FMC_SDNWE,

L3

K8

J4

EVENTOUT

TIM2_CH4, TIM5_CH4,

TIM9_CH2, USART2_RX,

LCD_B2,

OTG_HS_ULPI_D0,

ETH_MII_COL, LCD_B5,

EVENTOUT

(4)

K3 N10 R2

47

50

R2

PA3

I/O FT

ADC123_IN3

J1 N11

-

51

-

K6

L5

K5

VSS

BYPASS_REG

VDD

S

I

-

FT

-

L4

48

49

J4 P12 K4

52

S

SPI1_NSS,

SPI3_NSS/I2S3_WS,

USART2_CK,

ADC12_IN4,

DAC_OUT1

N2

M9

N4

50

53

N4

PA4

I/O TTa

-

OTG_HS_SOF,

DCMI_HSYNC,

LCD_VSYNC,

EVENTOUT

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79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM2_CH1/TIM2_ETR,

TIM8_CH1N, SPI1_SCK,

OTG_HS_ULPI_CK,

ADC12_IN5,

DAC_OUT2

M3

L8

P4

51

52

54

55

P4

P3

PA5

PA6

I/O TTa

I/O FT

-

LCD_R4, EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO,

TIM13_CH1,

DCMI_PIXCLK, LCD_G2,

EVENTOUT

(4)

N3 P11 P3

ADC12_IN6

ADC12_IN7

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N, SPI1_MOSI,

TIM14_CH1,

QUADSPI_CLK,

ETH_MII_RX_DV/ETH_R

MII_CRS_DV,

(4)

K4

J8

R3

53

56

R3

PA7

I/O FT

FMC_SDNWE,

EVENTOUT

ETH_MII_RXD0/ETH_RMI

I_RXD0, FMC_SDNE0,

EVENTOUT

(4)

-

N5

P5

54

55

57

58

N5

P5

PC4

PC5

I/O FT

ADC12_IN14

ADC12_IN15

ETH_MII_RXD1/ETH_RMI

I_RXD1, FMC_SDCKE0,

EVENTOUT

-

59

60

L7

L6

VDD

VSS

S

-

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N, LCD_R3,

OTG_HS_ULPI_D1,

ETH_MII_RXD2,LCD_G1,

EVENTOUT

(4)

N4 P10 R5

56

57

61

62

R5

R4

PB0

PB1

I/O FT

ADC12_IN8

ADC12_IN9

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N, LCD_R6,

OTG_HS_ULPI_D2,

ETH_MII_RXD3,LCD_G0,

EVENTOUT

(4)

K5

N9

R4

I/O FT

PB2-

BOOT1(PB2)

L5

-

P9

-

M6 58

63

64

M5

G4

I/O FT

-

EVENTOUT

-

LCD_G2, LCD_R0,

EVENTOUT

-

PI15

LCD_R7, LCD_R1,

EVENTOUT

-

65

66

R6

R7

PJ0

PJ1

I/O FT

-

LCD_R2, EVENTOUT

56/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

DSIHOST_TE, LCD_R3,

EVENTOUT

-

67

P7

PJ2

I/O FT

-

68

69

N8

M9

PJ3

PJ4

I/O FT

-

LCD_R4, EVENTOUT

LCD_R5, EVENTOUT

-

SPI5_MOSI,

FMC_SDNRAS,

M5

K7

R6

59

70

P8

PF11

I/O FT

-

DCMI_D12, EVENTOUT

N5

J6

M8

N8

P8

J7

P6

60

71

72

73

74

75

76

77

78

M6

K7

L8

PF12

VSS

I/O FT

-

FMC_A6, EVENTOUT

-

M8 61

S

-

K6

M4

H5

M6

N6

M7

N8

N6

R7

P7

N7

62

63

64

65

66

VDD

PF13

PF14

PF15

PG0

-

N6

P6

M8

N7

M7

I/O FT

FMC_A7, EVENTOUT

FMC_A8, EVENTOUT

FMC_A9, EVENTOUT

FMC_A10, EVENTOUT

FMC_A11, EVENTOUT

L7

H8

J6

P7

M7 67

PG1

TIM1_ETR, UART7_Rx,

QUADSPI_BK2_IO0,

FMC_D4, EVENTOUT

N7

G6

H6

N7

M7

K6

R8

P8

P9

68

69

70

79

80

81

R8

N9

P9

PE7

PE8

PE9

I/O FT

-

TIM1_CH1N, UART7_Tx,

QUADSPI_BK2_IO1,

FMC_D5, EVENTOUT

TIM1_CH1,

QUADSPI_BK2_IO2,

FMC_D6, EVENTOUT

J7

L6

-

M9 71

82

83

K8

L9

VSS

VDD

S

-

N9

72

TIM1_CH2N,

H7

K7

L7

J8

P6

R9

73

84

R9

PE10

PE11

PE12

PE13

I/O FT

-

QUADSPI_BK2_IO3,

FMC_D7, EVENTOUT

-

TIM1_CH2, SPI4_NSS,

FMC_D8, LCD_G3,

EVENTOUT

N6 P10 74

M6 R10 75

L6 N11 76

85 P10

86 R10

87 R12

TIM1_CH3N, SPI4_SCK,

FMC_D9, LCD_B4,

EVENTOUT

TIM1_CH3, SPI4_MISO,

FMC_D10, LCD_DE,

EVENTOUT

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79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM1_CH4, SPI4_MOSI,

FMC_D11, LCD_CLK,

EVENTOUT

K8

L8

J5 P11 77

P5 R11 78

88 P11

89 R11

PE14

PE15

I/O FT

-

TIM1_BKIN, FMC_D12,

LCD_R7, EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

USART3_TX,

M8

N8

N5 R12 79

90 P12

PB10

PB11

I/O FT

-

QUADSPI_BK1_NCS,

OTG_HS_ULPI_D3,

ETH_MII_RX_ER,

-

LCD_G4, EVENTOUT

TIM2_CH4, I2C2_SDA,

USART3_RX,

OTG_HS_ULPI_D4,

ETH_MII_TX_EN/ETH_R

MII_TX_EN,

K5 R13 80

N4 M10 81

91 R13

92 L11

I/O FT

DSIHOST_TE, LCD_G5,

EVENTOUT

N9

M9

L9

-

VCAP1

VSS

S

-

P4

-

93

K9

-

P3 N10 82

94 L10

95 M14

VDD

PJ5

-

I/O FT

LCD_R6, EVENTOUT

I2C2_SMBA, SPI5_SCK,

TIM12_CH1,

ETH_MII_RXD2,

FMC_SDNE1, DCMI_D8,

EVENTOUT

-

M11 83

N12 84

96 P13

97 N13

PH6

PH7

I/O FT

-

I2C3_SCL, SPI5_MISO,

ETH_MII_RXD3,

-

I/O FT

FMC_SDCKE1,

DCMI_D9, EVENTOUT

I2C3_SDA, FMC_D16,

DCMI_HSYNC, LCD_R2,

EVENTOUT

H8

H9

J9

M5

L5

-

98 P14

99 N14

100 P15

PH8

PH9

I/O FT

-

I2C3_SMBA, TIM12_CH2,

FMC_D17, DCMI_D0,

LCD_R3, EVENTOUT

TIM5_CH1, FMC_D18,

DCMI_D1, LCD_R4,

EVENTOUT

M4

PH10

58/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM5_CH2, FMC_D19,

DCMI_D2, LCD_R5,

EVENTOUT

K9

N3

-

101 N15

102 M15

PH11

PH12

I/O FT

-

TIM5_CH3, FMC_D20,

DCMI_D3, LCD_R6,

EVENTOUT

H10 P2

-

H7

-

K10

VSS

VDD

S

-

103 K11

TIM1_BKIN, I2C2_SMBA,

SPI2_NSS/I2S2_WS,

USART3_CK, CAN2_RX,

OTG_HS_ULPI_D5,

ETH_MII_TXD0/ETH_RMI

I_TXD0, OTG_HS_ID,

EVENTOUT

N10 H5 P12 85 104 L13

N11 K4 P13 86 105 K14

N12 P1 R14 87 106 R14

N13 N2 R15 88 107 R15

PB12

PB13

PB14

PB15

I/O FT

-

TIM1_CH1N,

SPI2_SCK/I2S2_CK,

USART3_CTS, CAN2_TX, OTG_HS_VBU

OTG_HS_ULPI_D6,

ETH_MII_TXD1/ETH_RMI

I_TXD1, EVENTOUT

S

TIM1_CH2N,

TIM8_CH2N, SPI2_MISO,

I2S2ext_SD,

USART3_RTS,

TIM12_CH1,

OTG_HS_DM,

-

EVENTOUT

RTC_REFIN,

TIM1_CH3N,

TIM8_CH3N,

-

SPI2_MOSI/I2S2_SD,

TIM12_CH2,

OTG_HS_DP, EVENTOUT

USART3_TX, FMC_D13,

EVENTOUT

L10 L4 P15 89 108 L15

M10 N1 P14 90 109 L14

L11 M3 N15 91 110 K15

PD8

PD9

I/O FT

-

USART3_RX, FMC_D14,

EVENTOUT

USART3_CK, FMC_D15,

LCD_B3, EVENTOUT

PD10

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79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

USART3_CTS,

QUADSPI_BK1_IO0,

FMC_A16/FMC_CLE,

EVENTOUT

M11 J4 N14 92 111 N10

PD11

I/O FT

-

TIM4_CH1,

USART3_RTS,

M13 M2 N13 93 112 M10

M12 H4 M15 94 113 M11

PD12

PD13

I/O FT

-

QUADSPI_BK1_IO1,

FMC_A17/FMC_ALE,

EVENTOUT

-

TIM4_CH2,

QUADSPI_BK1_IO3,

FMC_A18, EVENTOUT

J10 M1

K10

-

95 114 J10

VSS

VDD

S

-

J13 96 115 J11

TIM4_CH3, FMC_D0,

EVENTOUT

L12 L3 M14 97 116 L12

PD14

PD15

I/O FT

-

TIM4_CH4, FMC_D1,

EVENTOUT

L13 L2 L14 98 117 K13

K13 L1 J12 99 118 H11

VDDDSI

VSS

S

-

H10

K12 K1 K12 100 119 K12

K2 D13 G13

-

VCAPDSI

VDD12DSI

-

J12 K3 M12 101 120 J12 DSIHOST_D0P I/O

J13 J3 M13 102 121 J13 DSIHOST_D0N I/O

K11 H1 H12 103 122 G12 VSSDSI

-

S

-

H12 J1 L12 104 123 H12 DSIHOST_CKP I/O

H13 J2 L13 105 124 H13 DSIHOST_CKN I/O

-

J11

-

D13 106 125

-

VDD12DSI

S

-

G12 H3 E12 107 126 F12 DSIHOST_D1P I/O

G13 H2 E13 108 127 F13 DSIHOST_D1N I/O

-

H11

-

H12 109 128

-

VSSDSI

PG2

S

-

F13 G5 L15 110 129 M13

F12 G4 K15 111 130 M12

I/O FT

FMC_A12, EVENTOUT

FMC_A13, EVENTOUT

PG3

FMC_A14/FMC_BA0,

EVENTOUT

E13 G2 K14 112 131 N12

PG4

I/O FT

-

60/208

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STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

FMC_A15/FMC_BA1,

EVENTOUT

E12 G1 K13 113 132 N11

F11 G3 J15 114 133 J15

PG5

PG6

I/O FT

-

DCMI_D12, LCD_R7,

EVENTOUT

SAI1_MCLK_A,

USART6_CK, FMC_INT,

DCMI_D13, LCD_CLK,

EVENTOUT

E11 H6 J14 115 134 J14

PG7

PG8

I/O FT

-

SPI6_NSS,

USART6_RTS,

ETH_PPS_OUT,

FMC_SDCLK, LCD_G7,

EVENTOUT

D13 G6 H14 116 135 H14

G9

F2 G12 117 136 G10

VSS

S

-

G11 F1 H13 118 137 G11

VDDUSB

TIM3_CH1, TIM8_CH1,

I2S2_MCK, USART6_TX,

SDIO_D6, DCMI_D0,

LCD_HSYNC,

F9

F3 H15 119 138 H15

PC6

I/O FT

-

EVENTOUT

TIM3_CH2, TIM8_CH2,

I2S3_MCK, USART6_RX,

SDIO_D7, DCMI_D1,

F10 G7 G15 120 139 G15

E10 F4 G14 121 140 G14

PC7

PC8

I/O FT

-

LCD_G6, EVENTOUT

TRACED1, TIM3_CH3,

TIM8_CH3, USART6_CK,

SDIO_D0, DCMI_D2,

EVENTOUT

MCO2, TIM3_CH4,

TIM8_CH4, I2C3_SDA,

I2S_CKIN,

QUADSPI_BK1_IO0,

SDIO_D1, DCMI_D3,

EVENTOUT

G10 F5 F14 122 141 F14

PC9

I/O FT

-

MCO1, TIM1_CH1,

I2C3_SCL, USART1_CK,

OTG_FS_SOF, LCD_R6,

EVENTOUT

D8

E8

E1 F15 123 142 F15

E2 E15 124 143 E15

PA8

PA9

I/O FT

-

TIM1_CH2, I2C3_SMBA,

SPI2_SCK/I2S2_CK,

USART1_TX, DCMI_D0,

EVENTOUT

OTG_FS_VBU

S

DocID028010 Rev 2

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79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM1_CH3, USART1_RX,

OTG_FS_ID, DCMI_D1,

EVENTOUT

E9

E3 D15 125 144 D15

PA10

PA11

I/O FT

-

TIM1_CH4,

USART1_CTS,

CAN1_RX, OTG_FS_DM,

LCD_R4, EVENTOUT

A13 F7 C15 126 145 C15

TIM1_ETR,

USART1_RTS, CAN1_TX,

OTG_FS_DP, LCD_R5,

EVENTOUT

A12 F6 B15 127 146 B15

A11 D1 A15 128 147 A15

PA12

I/O FT

-

PA13(JTMS-

SWDIO)

JTMS-SWDIO,

EVENTOUT

D12 D2 F13 129 148 E11

D11 C1 F12 130 149 F10

D10 C2 G13 131 150 F11

VCAP2

VSS

S

-

VDD

TIM8_CH1N, CAN1_TX,

FMC_D21, LCD_G2,

EVENTOUT

D9

B1

-

151 E12

152 E13

153 D13

PH13

PH14

PH15

I/O FT

-

TIM8_CH2N, FMC_D22,

DCMI_D4, LCD_G3,

EVENTOUT

C13 D3

C12 E4

TIM8_CH3N, FMC_D23,

DCMI_D11, LCD_G4,

EVENTOUT

TIM5_CH4,

SPI2_NSS/I2S2_WS⁽⁶⁾

FMC_D24, DCMI_D13,

LCD_G5, EVENTOUT

,

B13 E5 E14 132 154 E14

PI0

PI1

PI2

I/O FT

-

SPI2_SCK/I2S2_CK⁽⁶⁾

FMC_D25, DCMI_D8,

LCD_G6, EVENTOUT

,

C11 C3 D14 133 155 D14

TIM8_CH4, SPI2_MISO,

I2S2ext_SD, FMC_D26,

DCMI_D9, LCD_G7,

EVENTOUT

NC

B12 A1

-

156 C14

(7)

TIM8_ETR,

SPI2_MOSI/I2S2_SD,

FMC_D27, DCMI_D10,

EVENTOUT

B10 B2 C13 134 157 C13

PI3

I/O FT

-

D9 135

-

F9

VSS

S

-

62/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

-

B5

C9 136 158 E10

VDD

S

-

PA14(JTCK-

SWCLK)

JTCK-SWCLK,

EVENTOUT

A10 D4 A14 137 159 A14

I/O FT

JTDI,

TIM2_CH1/TIM2_ETR,

SPI1_NSS,

SPI3_NSS/I2S3_WS,

EVENTOUT

B11 A2 A13 138 160 A13

PA15(JTDI)

PC10

I/O FT

-

SPI3_SCK/I2S3_CK,

USART3_TX, UART4_TX,

QUADSPI_BK1_IO1,

SDIO_D2, DCMI_D8,

LCD_R2, EVENTOUT

C10 D5 B14 139 161 B14

I/O FT

I2S3ext_SD, SPI3_MISO,

USART3_RX,UART4_RX,

QUADSPI_BK2_NCS,

SDIO_D3, DCMI_D4,

EVENTOUT

B9

A9

B3 B13 140 162 B13

PC11

TRACED3,

SPI3_MOSI/I2S3_SD,

USART3_CK, UART5_TX,

SDIO_CK, DCMI_D9,

EVENTOUT

C4 A12 141 163 A12

PC12

CAN1_RX, FMC_D2,

EVENTOUT

C9

C7

E6 B12 142 164 B12

A3 C12 143 165 C12

PD0

PD1

I/O FT

-

CAN1_TX, FMC_D3,

EVENTOUT

TRACED2, TIM3_ETR,

UART5_RX, SDIO_CMD,

DCMI_D11, EVENTOUT

B8

C8

C5 D12 144 166 D12

D6 D11 145 167 C11

PD2

PD3

I/O FT

-

SPI2_SCK/I2S2_CK,

USART2_CTS,

FMC_CLK, DCMI_D5,

LCD_G7, EVENTOUT

USART2_RTS,

FMC_NOE, EVENTOUT

C6

B7

B4 D10 146 168 D11

C6 C11 147 169 C10

PD4

PD5

I/O FT

-

USART2_TX, FMC_NWE,

EVENTOUT

F8

F7

A4

-

D8 148 170 F8

C8 149 171 E9

VSS

VDD

S

-

DocID028010 Rev 2

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79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

SPI3_MOSI/I2S3_SD,

SAI1_SD_A,

D7

E7 B11 150 172 B11

A5 A11 151 173 A11

PD6

I/O FT

-

USART2_RX,

FMC_NWAIT, DCMI_D10,

LCD_B2, EVENTOUT

-

USART2_CK, FMC_NE1,

EVENTOUT

A8

PD7

PJ12

PJ13

I/O FT

-

LCD_G3, LCD_B0,

EVENTOUT

-

174 B10

175 B9

LCD_G4, LCD_B1,

EVENTOUT

-

176 C9

177 D10

PJ14

PJ15

I/O FT

-

LCD_B2, EVENTOUT

LCD_B3, EVENTOUT

-

USART6_RX,

QUADSPI_BK2_IO2,

FMC_NE2/FMC_NCE,

DCMI_VSYNC,

E6

D7 C10 152 178 D9

C7 B10 153 179 C8

PG9

I/O FT

-

EVENTOUT

LCD_G3, FMC_NE3,

DCMI_D2, LCD_B2,

EVENTOUT

E7

B6

PG10

PG11

I/O FT

-

ETH_MII_TX_EN/ETH_R

MII_TX_EN, DCMI_D3,

LCD_B3, EVENTOUT

B6

A6

B9 154 180 B8

B8 155 181 C7

SPI6_MISO,

USART6_RTS, LCD_B4,

FMC_NE4, LCD_B1,

EVENTOUT

A7

A6

PG12

PG13

I/O FT

-

TRACED0, SPI6_SCK,

USART6_CTS,

ETH_MII_TXD0/ETH_RMI

I_TXD0, FMC_A24,

E8

A8 156 182 B3

LCD_R0, EVENTOUT

TRACED1, SPI6_MOSI,

USART6_TX,

QUADSPI_BK2_IO3,

ETH_MII_TXD1/ETH_RMI

I_TXD1, FMC_A25,

LCD_B0, EVENTOUT

-

A7 157 183 A4

PG14

I/O FT

-

B7

A7

D7 158 184 F7

C7 159 185 E8

VSS

VDD

S

-

64/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

-

186 D8

187 D7

188 C6

189 C5

190 C4

PK3

PK4

PK5

PK6

PK7

I/O FT

-

LCD_B4, EVENTOUT

LCD_B5, EVENTOUT

LCD_B6, EVENTOUT

LCD_B7, EVENTOUT

LCD_DE, EVENTOUT

-

USART6_CTS,

FMC_SDNCAS,

DCMI_D13, EVENTOUT

F6

B5

D6

D8

B7 160 191 B7

PG15

I/O FT

-

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK/I2S3_CK,

EVENTOUT

PB3(JTDO/TRA

CESWO)

A8 A10 161 192 A10

NJTRST, TIM3_CH1,

SPI1_MISO, SPI3_MISO,

I2S3ext_SD, EVENTOUT

C8

B8

A9 162 193 A9

PB4(NJTRST) I/O FT

TIM3_CH2, I2C1_SMBA,

SPI1_MOSI,

SPI3_MOSI/I2S3_SD,

CAN2_RX,

OTG_HS_ULPI_D7,

ETH_PPS_OUT,

FMC_SDCKE1,

DCMI_D10, LCD_G7,

EVENTOUT

D5

C5

A6 163 194 A8

PB5

PB6

I/O FT

-

TIM4_CH1, I2C1_SCL,

USART1_TX, CAN2_TX,

QUADSPI_BK1_NCS,

FMC_SDNE1, DCMI_D5,

EVENTOUT

G8

B6 164 195 B6

I/O FT

TIM4_CH2, I2C1_SDA,

USART1_RX, FMC_NL,

DCMI_VSYNC,

B4

A5

A9

F8

B5 165 196 B5

D6 166 197 E6

PB7

-

EVENTOUT

BOOT0

I

B

-

VPP

TIM4_CH3, TIM10_CH1,

I2C1_SCL, CAN1_RX,

ETH_MII_TXD3,

D4

B9

A5 167 198 A7

PB8

I/O FT

-

SDIO_D4, DCMI_D6,

LCD_B6, EVENTOUT

DocID028010 Rev 2

65/208

79

Pinouts and pin description

STM32F479xx

Table 10. STM32F479xx pin and ball definitions (continued)

Pin Number

Pin name

(function after

reset)⁽¹⁾

Additional

functions

Alternate functions

TIM4_CH4, TIM11_CH1,

I2C1_SDA,

SPI2_NSS/I2S2_WS,

CAN1_TX, SDIO_D5,

DCMI_D7, LCD_B7,

EVENTOUT

C4

E9

B4 168 199 B4

PB9

I/O FT

-

TIM4_ETR, UART8_Rx,

FMC_NBL0, DCMI_D2,

EVENTOUT

A4 A10 A4 169 200 A6

PE0

PE1

I/O FT

-

UART8_Tx, FMC_NBL1,

DCMI_D3, EVENTOUT

A3

C9

A3 170 201 A5

E3 B10 D5

-

202 F6

VSS

PDR_ON

VDD

S

-

C3 D9 C6 171 203 E5

D3 A11 C5 172 204 E7

B3 D10 D4 173 205 C3

TIM8_BKIN, FMC_NBL2,

DCMI_D5, LCD_B4,

EVENTOUT

PI4

PI5

PI6

PI7

I/O FT

-

TIM8_CH1, FMC_NBL3,

DCMI_VSYNC, LCD_B5,

EVENTOUT

A2 C10 C4 174 206 D3

A1 B11 C3 175 207 D6

B1 A12 C2 176 208 D4

TIM8_CH2, FMC_D28,

DCMI_D6, LCD_B6,

EVENTOUT

TIM8_CH3, FMC_D29,

DCMI_D7, LCD_B7,

EVENTOUT

1. Function availability depends on the chosen device.

2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3

mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after

reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC

register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:

www.st.com.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

5. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the

BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).

6. PI0 and PI1 cannot be used for I2S2 full-duplex mode.

7. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the

output data register to avoid extra current consumption in low power modes.

66/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 11. FMC pin definition

NOR/PSRAM/SR

NOR/PSRAM

Mux

Pin name

NAND16

SDRAM

AM

PF0

PF1

A0

A1

-

A0

A1

-

PF2

A2

-

A2

PF3

A3

-

A3

PF4

A4

-

A4

PF5

A5

-

A5

PF12

PF13

PF14

PF15

PG0

PG1

PG2

PG3

PG4

PG5

PD11

PD12

PD13

PE3

A6

-

A6

A7

-

A7

A8

-

A8

A9

-

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

D0

-

A10

A11

A12

-

BA0

BA1

-

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

CLE

ALE

-

PE4

-

PE5

-

PE6

-

PE2

-

PG13

PG14

PD14

PD15

PD0

PD1

PE7

-

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D1

D2

D3

D4

PE8

D5

PE9

D6

PE10

D7

DocID028010 Rev 2

67/208

79

Pinouts and pin description

Pin name

STM32F479xx

SDRAM

Table 11. FMC pin definition (continued)

NOR/PSRAM/SR

NOR/PSRAM

Mux

NAND16

AM

PE11

PE12

PE13

PE14

PE15

PD8

PD9

PD10

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PI0

D8

D9

DA8

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

-

DA9

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

NE1

NE2

NE3

-

DA10

D10

DA11

D11

DA12

D12

DA13

D13

DA14

D14

DA15

D15

-

PI1

-

PI2

-

PI3

-

PI6

-

PI7

-

PI9

-

PI10

PD7

PG9

PG10

PG11

PG12

PD3

PD4

PD5

PD6

PB7

-

NE1

NE2

NE3

-

NCE

-

NE4

CLK

NOE

NWE

NWAIT

NADV

-

CLK

NOE

NWE

NWAIT

NADV

-

NOE

NWE

NWAIT

-

68/208

DocID028010 Rev 2

STM32F479xx

Pinouts and pin description

Table 11. FMC pin definition (continued)

NOR/PSRAM/SR

AM

NOR/PSRAM

Mux

Pin name

NAND16

SDRAM

PF6

PF7

PF8

PF9

PF10

PG6

PG7

PE0

PE1

PI4

-

INT

-

NBL0

-

NBL1

NBL2

NBL3

SDCLK

SDNWE

SDNRAS

SDNCAS

SDCKE0

SDNE0

SDNE1

SDCKE1

SDNWE

SDNE0

SDCKE0

SDCKE1

SDNE1

NBL2

-

PI5

NBL3

PG8

PC0

PF11

PG15

PH2

PH3

PH6

PH7

PH5

PC2

PC3

PB5

PB6

-

DocID028010 Rev 2

69/208

79

Memory mapping

STM32F479xx

4

Memory mapping

The memory map is shown in Figure 19.

Figure 19. Memory map

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80/208

DocID028010 Rev 2

STM32F479xx

Memory mapping

(1)

Table 13. STM32F479xx register boundary addresses

Bus

Boundary address

Peripheral

-

0xE00F FFFF - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0xD000 0000 - 0xDFFF FFFF

0xC000 0000 - 0xCFFF FFFF

0xA000 1000 - 0xA0001FFF

0xA000 2000 - 0xBFFF FFFF

0xA000 0000- 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5006 0C00- 0x5FFF FFFF

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5006 0000 - 0x5006 03FF

0x5005 0400 - 0x5005 FFFF

0x5005 0000 - 0x5005 03FF

0x5004 0000- 0x5004 FFFF

0x5000 0000 - 0x5003 FFFF

Reserved

Cortex^®-M4

Cortex^®-M4 internal peripherals

FMC bank 6

FMC bank 5

Quad-SPI control register

Reserved

AHB3

FMC control register

Quad-SPI bank

FMC bank 3

FMC bank 2 (reserved)

FMC bank 1

Reserved

-

RNG

HASH

CRYP

AHB2

Reserved

DCMI

Reserved

USB OTG FS

DocID028010 Rev 2

81/208

84

Memory mapping

STM32F479xx

(1)

Table 13. STM32F479xx register boundary addresses (continued)

Bus

Boundary address

Peripheral

-

0x4008 0000- 0x4FFF FFFF

0x4004 0000 - 0x4007 FFFF

0x4002 BC00- 0x4003 FFFF

0x4002 B000 - 0x4002 BBFF

0x4002 9400 - 0x4002 AFFF

0x4002 9000 - 0x4002 93FF

0x4002 8C00 - 0x4002 8FFF

0x4002 8800 - 0x4002 8BFF

0x4002 8400 - 0x4002 87FF

0x4002 8000 - 0x4002 83FF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2C00 - 0x4002 2FFF

0x4002 2800 - 0x4002 2BFF

0x4002 2400 - 0x4002 27FF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

Reserved

USB OTG HS

Reserved

Chrom (DMA2D)

Reserved

ETHERNET MAC

Reserved

DMA2

DMA1

Reserved

BKPSRAM

Flash interface register

RCC

AHB1

Reserved

CRC

Reserved

GPIOK

GPIOJ

GPIOI

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

82/208

DocID028010 Rev 2

STM32F479xx

Memory mapping

(1)

Table 13. STM32F479xx register boundary addresses (continued)

Bus

Boundary address

Peripheral

0x4001 7400 - 0x4001 FFFF

0x4001 6C00 - 0x4001 73FF

0x4001 6800 - 0x4001 6BFF

0x4001 5C00 - 0x4001 67FF

0x4001 5800 - 0x4001 5BFF

0x4001 5400 - 0x4001 57FF

0x4001 5000 - 0x4001 53FF

0x4001 4C00 - 0x4001 4FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

Reserved

DSI Host

LCD-TFT

Reserved

SAI1

SPI6

SPI5

Reserved

TIM11

TIM10

TIM9

EXTI

APB2

SYSCFG

SPI4

SPI1

SDIO

Reserved

ADC1 - ADC2 - ADC3

Reserved

USART6

USART1

Reserved

TIM8

TIM1

DocID028010 Rev 2

83/208

84

Memory mapping

STM32F479xx

(1)

Table 13. STM32F479xx register boundary addresses (continued)

Bus

Boundary address

Peripheral

-

0x4000 8000- 0x4000 FFFF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

Reserved

UART8

UART7

DAC

PWR

Reserved

CAN2

CAN1

Reserved

I2C3

I2C2

I2C1

UART5

UART4

USART3

USART2

I2S3ext

SPI3 / I2S3

SPI2 / I2S2

I2S2ext

IWDG

APB1

WWDG

RTC & BKP Registers

Reserved

TIM14

TIM13

TIM12

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

1. The reserved boundary address are shown in grayed cells

84/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

5

Electrical characteristics

5.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

5.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean±3σ).

5.1.2

5.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the

A

DD

1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

5.1.4

5.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 20.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 21.

Figure 20. Pin loading conditions

Figure 21. Pin input voltage

-#5 PIN

6

# ꢄ ꢅꢂ P&

).

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DocID028010 Rev 2

85/208

187

Electrical characteristics

STM32F479xx

5.1.6

Power supply scheme

Figure 22. Power supply scheme

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1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.

2. The two 2.2 µF ceramic capacitors on V_{CAP_1}and V_{CAP_2}should be replaced by two 100 nF decoupling

capacitors when the voltage regulator is OFF.

3. The 4.7 µF ceramic capacitor must be connected to one of the V_DDpin.

4. V_DDAand V_SSAmust be connected to V_DDand V_SS, respectively.

Caution:

Each power supply pair (V /V , V

/V

...) must be decoupled with filtering ceramic

DD SS

DDA SSA

capacitors as shown above. These capacitors must be placed as close as possible to, or

below, the appropriate pins on the underside of the PCB to ensure good operation of the

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

86/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

5.1.7

Current consumption measurement

Figure 23. Current consumption measurement scheme

)

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5.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14, Table 15, and Table 16

may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these conditions is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Table 14. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External main supply voltage

(including V_DDA, V_DD, V_DDUSB, V_DDDSIand V_BAT

V_DD–V_SS

− 0.3

4.0

(1)

)

Input voltage on FT pins⁽²⁾

V_SS− 0.3 V_DD+4.0

V

Input voltage on TTa pins

V_SS− 0.3

4.0

9.0

50

V_IN

Input voltage on any other pin

V_SS− 0.3

Input voltage on BOOT pin

V_SS

|ΔV_DDx

|V_SSX−V_SS

V_ESD(HBM)

|

Variations between different V_DDpower pins

Variations between all the different ground pins

-

mV

|

50

Electrostatic discharge voltage (human body model)

see Section 5.3.18

1. All main power (V_DD, V_DDA, V_DDUSB, V_DDDSI) and ground (V_SS, V_SSA) pins must always be connected to

the external power supply, in the permitted range.

2. V_INmaximum value must always be respected. Refer to Table 15 for the values of the maximum allowed

injected current.

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187

Electrical characteristics

Symbol

STM32F479xx

Table 15. Current characteristics

Ratings

Max.

Unit

ΣI_VDD

Σ I_VSS

Total current into sum of all V_{DD_x}power lines (source)⁽¹⁾

Total current out of sum of all V_{SS_x}ground lines (sink)⁽¹⁾

290

− 290

25

Σ I_VDDUSBTotal current into V_DDUSBpower line (source)

I_VDD

I_VSS

Maximum current into each V_{DD_x}power line (source)⁽¹⁾

Maximum current out of each V_{SS_x}ground line (sink)⁽¹⁾

Output current sunk by any I/O and control pin

100

− 100

25

I_IO

Output current sourced by any I/Os and control pin

Total output current sunk by sum of all I/O and control pins ⁽²⁾

Total output current sunk by sum of all USB I/Os

Total output current sourced by sum of all I/Os and control pins⁽²⁾

Injected current on FT pins ⁽⁴⁾

− 25

120

25

mA

ΣI_IO

− 120

− 5/+0

Injected current on NRST and BOOT0 pins ⁽⁴⁾

(3)

(5)

I_INJ(PIN)

Injected current on TTa pins⁽⁵⁾

±5

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁶⁾

±25

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output

current must not be sunk/sourced between two consecutive power supply pins referring to high pin count

LQFP packages.

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the

specified maximum value.

5. A positive injection is induced by V_IN>V_DDAwhile a negative injection is induced by V_IN<V_SS. I_INJ(PIN)must

never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.

6. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values).

Table 16. Thermal characteristics

Symbol

Ratings

Value

Unit

T_STG

T_J

Storage temperature range

− 65 to +150

°C

Maximum junction temperature

125

88/208

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STM32F479xx

Electrical characteristics

5.3

Operating conditions

5.3.1

General operating conditions

Table 17. General operating conditions

Symbol

Parameter

Conditions⁽¹⁾

Min Typ Max Unit

Power Scale 3 (VOS[1:0] bits in PWR_CR

register = 0x01),

Regulator ON, over-drive OFF

0

-

120

Over-drive

-

144

168

180

Power Scale 2 (VOS[1:0] bits

OFF

in PWR_CR register = 0x10),

Regulator ON

f_HCLK

Internal AHB clock frequency

Over-drive

ON

Over-drive

OFF

MHz

Power Scale 1 (VOS[1:0] bits

in PWR_CR register= 0x11),

Regulator ON

0

Over-drive

ON

Over-drive OFF

Over-drive ON

Over-drive OFF

Over-drive ON

-

0

-

42

45

84

90

3.6

f_PCLK1Internal APB1 clock frequency

f_PCLK2Internal APB2 clock frequency

0

V_DD

Standard operating voltage

1.7⁽²⁾

Analog operating voltage

1.7⁽²⁾

-

2.4

3.6

(ADC limited to 1.2 M samples)

(3)(4)

(5)

V_DDA

Must be the same potential as V_DD

Analog operating voltage

2.4

(ADC limited to 2.4 M samples)

V

USB supply voltage

V_DDUSB(supply voltage for PA11, PA12,

PB14 and PB15 pins)

USB not used

USB used

1.7

3.0

3.3

-

3.6

V_DDDSIDSI system operating voltage

-

1.7⁽²⁾

1.65

-

3.6

V_BAT

Backup operating voltage

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Electrical characteristics

STM32F479xx

Table 17. General operating conditions (continued)

Symbol

Parameter

Conditions⁽¹⁾

Min Typ Max Unit

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 120 MHz

HCLK max frequency

1.08 1.14 1.20

Power Scale 2 ((VOS[1:0] bits in

PWR_CR register = 0x10), 144 MHz

HCLK max frequency with over-drive OFF

or 168 MHz with over-drive ON

Regulator ON: 1.2 V internal

voltage on V_{CAP_1}/V_{CAP_2}pins

1.20 1.26 1.32

V₁₂

V

Power Scale 1 ((VOS[1:0] bits in

PWR_CR register = 0x11), 168 MHz

HCLK max frequency with over-drive OFF

or 180 MHz with over-drive ON

1.26 1.32 1.40

Regulator OFF: 1.2 V external Max frequency 120 MHz

1.10 1.14 1.20

1.20 1.26 1.32

1.26 1.32 1.38

voltage must be supplied from

Max frequency 144 MHz

external regulator on

V_{CAP_1}/V_{CAP_2}pins⁽⁶⁾

Max frequency 168 MHz

2 V ≤V_DD≤3.6 V

V_DD≤2 V

− 0.3

-

5.5

5.2

Input voltage on RST and FT

pins⁽⁷⁾

V_IN

V

V_DDA

+0.3

Input voltage on TTa pins

-

− 0.3

-

Input voltage on BOOT0 pin

0

-

9

WLCSP168

UFBGA169

LQFP176

-

645

385

526

513

1053

690

85

Power dissipation at T_A= 85 °C

for suffix 6 or T_A= 105 °C for

suffix 7⁽⁸⁾

-

P_D

mW

UFBGA176

LQFP208

-

TFBGA216

-

Maximum power dissipation

Low power dissipation⁽⁹⁾

Maximum power dissipation

Low power dissipation⁽⁹⁾

6 suffix version

− 40

Ambient temperature for 6

suffix version

105

125

105

125

TA

TJ

Ambient temperature for 7

suffix version

°C

Junction temperature range

7 suffix version

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. V_DD/V_DDAminimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).

3. When the ADC is used, refer to Table 77.

4. If V_REF+pin is present, it must respect the following condition: V_DDA-V_REF+< 1.2 V.

5. It is recommended to power V_DDand V_DDAfrom the same source. A maximum difference of 300 mV between V_DDand

V

_DDAcan be tolerated during power-up and power-down operation.

6. The over-drive mode is not supported when the internal regulator is OFF.

7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

8. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax

.

9. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax

.

90/208

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STM32F479xx

Electrical characteristics

Possible Flash

Table 18. Limitations depending on the operating power supply range

Maximum Flash

memory access

frequency with

no wait states

Maximum HCLK

frequency

Operating

power

supply range

ADC

operation

vs.

I/O operation

memory

Flash memory wait

operations

(f_Flashmax

)

states ⁽¹⁾⁽²⁾

168 MHz

with 8 wait states

and over-drive OFF

8-bit erase

and program

operations only

V_DD

=

20 MHz⁽⁴⁾

22 MHz

24 MHz

30 MHz

1.7 to 2.1 V⁽³⁾

Conversion time

up to 1.2 Msps

No I/O

compensation

180 MHz

with 8 wait states

and over-drive ON

16-bit erase

and program

operations

V_DD

2.1 to 2.4 V

=

180 MHz

with 7 wait states

and over-drive ON

16-bit erase

and program

operations

V_DD

2.4 to 2.7 V

=

Conversion time

up to 2.4 Msps

I/O compensation

works

180 MHz

with 5 wait states

and over-drive ON

32-bit erase

and program

operations

V_DD

=

2.7 to 3.6 V⁽⁵⁾

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is

required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the

execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state

program execution.

3. V_DD/V_DDAminimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).

4. Prefetch is not available.

5. When V_DDUSBis connected to V_DD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the

electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.

5.3.2

VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor C

to

EXT

the VCAP1/VCAP2 pins. C

is specified in Table 19.

EXT

Figure 24. External capacitor C

EXT

&

(65

5ꢍ_/HDN

06ꢅꢃꢇꢄꢄ9ꢂ

1. Legend: ESR is the equivalent series resistance.

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187

Electrical characteristics

Symbol

STM32F479xx

(1)

Table 19. VCAP1/VCAP2 operating conditions

Parameter

Conditions

CEXT

ESR

Capacitance of external capacitor

ESR of external capacitor

2.2 µF

< 2 Ω

1. When bypassing the voltage regulator, the two 2.2 µF V_CAPcapacitors are not required and should be

replaced by two 100 nF decoupling capacitors.

5.3.3

Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for T .

A

Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol

Parameter

V_DDrise time rate

V_DDfall time rate

Min

Max

Unit

20

∞

t_VDD

µs/V

5.3.4

Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for T .

A

(1)

Table 21. Operating conditions at power-up / power-down (regulator OFF)

Symbol

Parameter

V_DDrise time rate

_DDfall time rate

Conditions

Power-up

Power-down

Min

Max

Unit

20

∞

t_VDD

V

µs/V

V_{CAP_1}and V_{CAP_2}rise time rate Power-up

V_{CAP_1}and V_{CAP_2}fall time rate Power-down

t_VCAP

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V_DDreach below

1.08 V.

5.3.5

Reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 17.

DD

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DocID028010 Rev 2

STM32F479xx

Symbol

Electrical characteristics

Table 22. Reset and power control block characteristics

Parameter

Conditions

Min

Typ

Max

Unit

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

-

2.09

1.98

2.23

2.13

2.39

2.29

2.54

2.44

2.70

2.59

2.86

2.65

2.96

2.85

3.07

2.95

-

2.14

2.04

2.30

2.19

2.45

2.35

2.60

2.51

2.76

2.66

2.93

2.84

3.03

2.93

3.14

3.03

100

2.19

2.08

2.37

2.25

2.51

2.39

2.65

2.56

2.82

2.71

2.99

2.92

3.10

2.99

3.21

3.09

-

Programmable voltage

detector level selection

V_PVD

V

(1)

V_PVDhyst

PVD hysteresis

mV

V

Falling edge

1.60

1.64

-

1.68

1.72

40

1.76

1.80

-

Power-on/power-down

reset threshold

V_POR/PDR

Rising edge

(1)

V_PDRhyst

PDR hysteresis

-

mV

Falling edge

2.13

2.23

2.44

2.53

2.75

2.85

-

2.19

2.29

2.50

2.59

2.83

2.92

100

2.24

2.33

2.56

2.63

2.88

2.97

-

V_BOR1

V_BOR2

V_BOR3

Brownout level 1 threshold

Rising edge

Falling edge

Brownout level 2 threshold

Brownout level 3 threshold

V

Rising edge

Falling edge

Rising edge

(1)

V_BORhyst

BOR hysteresis

-

mV

ms

(1)(2)

T_RSTTEMPO

POR reset temporization

-

0.5

1.5

3.0

InRush current on voltage

regulator power-on (POR or

wakeup from Standby)

(1)

I_RUSH

-

160

-

200

5.4

mA

µC

InRush energy on voltage

regulator power-on (POR or

wakeup from Standby)

V_DD= 1.7 V, T_A= 105 °C,

I_RUSH= 171 mA for 31 µs

(1)

E_RUSH

1. Guaranteed by design.

2. The reset temporization is measured from the power-on (POR reset or wakeup from V_BAT) to the instant when first

instruction is read by the user application code.

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187

Electrical characteristics

STM32F479xx

5.3.6

Over-drive switching characteristics

When the over-drive mode switches from enabled to disabled or disabled to enabled, the

system clock is stalled during the internal voltage set-up.

The over-drive switching characteristics are given in Table 23. They are subject to general

operating conditions for T .

A

(1)

Table 23. Over-drive switching characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HSI

-

45

-

HSE max for 4 MHz

and min for 26 MHz

Over_drive switch

enable time

45

-

100

T_{od_swen}

External HSE

50 MHz

-

40

20

-

µs

HSI

HSE max for 4 MHz

and min for 26 MHz.

Over_drive switch

disable time

20

80

T_{od_swdis}

External HSE

50 MHz

-

15

-

1. Guaranteed by design.

5.3.7

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 23.

All the run-mode current consumption measurements given in this section are performed

®

with a reduced code that gives a consumption equivalent to CoreMark code.

94/208

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Electrical characteristics

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

All I/O pins are in input mode with a static value at V or V (no load).

DD SS

All peripherals are disabled except if it is explicitly mentioned.

The Flash memory access time is adjusted both to f frequency and V range

HCLK

DD

(see Table 18: Limitations depending on the operating power supply range).

•

When the regulator is OFF, the V is provided externally, as described in Table 17:

General operating conditions.

12

The voltage scaling and over-drive mode are adjusted to f

frequency as follows:

HCLK

–

Scale 3 for f

≤ 120 MHz

HCLK

Scale 2 for 120 MHz < f

Scale 1 for 144 MHz < f

≤ 144 MHz

HCLK

PCLK1

≤ 180 MHz. The over-drive is only ON at 180 MHz.

= f /4, and f = f /2.

•

The system clock is HCLK, f

HCLK

PCLK2

HCLK

External clock frequency is 25 MHz and PLL is ON when f

is higher than 25 MHz.

HCLK

The typical current consumption values are obtained for 1.7 V ≤ V ≤ 3.6 V voltage

DD

range and for ambient temperature T = 25 °C unless otherwise specified.

A

•

The maximum values are obtained for 1.7 V ≤ V ≤ 3.6 V voltage range and a

DD

maximum ambient temperature (T ), unless otherwise specified.

A

For the voltage range 1.7 V ≤ V ≤ 2.1 V the maximum frequency is 168 MHz.

DD

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187

Electrical characteristics

STM32F479xx

Table 24. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled except prefetch) or RAM,

regulator ON

Max⁽¹⁾

Symbol

Parameter Conditions f_HCLK(MHz)

Typ

Unit

T_A=

25 °C

85 °C

105 °C

180

168

150

144

120

103

94

84

77

57

43

30

16

14

7

109⁽⁴⁾

99

89

81

60

46

33

19

16

10

7

142

124

114

104

79

64

51

37

34

28

26

24

23

89

75

70

63

49

42

36

29

28

25

22

23

175⁽⁴⁾

149

140

127

98

90

84

All

Peripherals

60

30

25

16

8

70

enabled⁽²⁾⁽³⁾

57

54

48

4

46

4

3

6

44

Supply

current in

RUN mode

2

3

5

43

I_DD

mA

180

168

150

144

120

90

60

30

25

16

8

50

45

41

37

28

21

15

9

56⁽⁴⁾

51

46

42

31

24

17

11

10

7

124⁽⁴⁾

102

97

88

69

63

All

Peripherals

56

disabled⁽²⁾

49

7

48

4

45

3

6

44

4

3

5

43

2

5

43

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption

should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC

for the analog part.

4. Guaranteed by test in production.

96/208

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STM32F479xx

Electrical characteristics

Table 25. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled), regulator ON

Max⁽¹⁾

f_HCLK

(MHz)

Symbol

Parameter

Conditions

Typ

Unit

T_A=

25 °C

85 °C

105 °C

168

150

144

120

90

97

87

80

65

51

37

21

18

49

44

40

36

29

22

13

11

102

92

84

68

54

41

23

20

55

49

45

39

32

25

15

13

128

118

108

88

73

59

42

39

79

44

68

58

51

44

34

32

154

143

131

108

93

All Peripherals

enabled⁽²⁾⁽³⁾

60

79

30

62

25

59

Supply current in

RUN mode

I_DD

mA

168

150

144

120

90

105

100

92

78

All Peripherals

disabled

71

60

64

30

54

25

52

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption

should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC

for the analog part.

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Table 26. Typical and maximum current consumption in Run mode, code with data

processing running from Flash memory (ART accelerator enabled except prefetch),

regulator OFF

Typ

Max⁽¹⁾

f_HCLK

(MHz)

Symbol

Parameter

Conditions

T_A= 25 °C

T_A= 85 °C T_A= 105 °C Unit

I_DD12I_DD

I_DD12I_DDI_DD12I_DDI_DD12I_DD

168

150

144

120

90

93

83

76

56

43

29

15

13

44

40

36

27

20

14

8

1

98

88

80

59

45

32

18

15

50

45

40

30

23

16

10

9

1

123

113

103

78

64

50

36

34

72

68

62

48

41

35

28

27

1

148

138

126

97

83

70

56

53

94

90

82

66

60

53

47

46

1

AllPeripherals

enabled^{(2) (3)}

60

30

Supplycurrent

in RUN mode

from V₁₂and

V_DDsupply

25

I_DD12/ I_DD

mA

168

150

144

120

90

AllPeripherals

disabled

60

30

25

7

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power

consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC

for the analog part.

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Table 27. Typical and maximum current consumption in Sleep mode, regulator ON

Max^(1)(2)(3)

Symbol

Parameter Conditions f_HCLK(MHz)

Typ

Unit

T_A= 25 °C T_A= 85 °C T_A= 105 °C

180

168

150

144

120

78

71

64

58

43

33

23

13

11

5

88⁽⁴⁾

76

71

62

46

37

25

15

13

8

118

101

94

85

65

54

44

34

32

27

25

24

23

63

50

48

43

34

31

28

25

23

151⁽⁴⁾

127

119

109

85

90

74

All

Peripherals

enabled

60

30

25

16

8

63

53

52

47

4

7

45

4

3

5

44

Supply

current in

Sleep mode

2

5

43

I_DD

mA

180

168

150

144

120

90

60

30

25

16

8

23

21

19

17

13

10

7

29⁽⁴⁾

25

23

31

16

13

10

7

96⁽⁴⁾

76

74

67

54

51

All

Peripherals

disabled

48

5

45

4

7

45

2

5

43

2

5

43

4

2

5

43

2

4

42

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption

should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC

for the analog part.

4. Guaranteed by test in production.

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Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF

Typ

Max⁽¹⁾

f_HCLK

(MHz)

Symbol

Parameter

Conditions

T_A= 25 °C T_A= 85 °C T_A= 105 °C Unit

I_DD12I_DDI_DD12I_DDI_DD12I_DD

I_DD12I_DD

168

150

144

120

90

70

63

57

42

32

22

12

10

20

18

16

12

10

7

1

75

70

61

45

36

24

14

12

24

22

19

14

12

9

1

100

93

84

64

53

43

33

31

49

47

42

33

30

27

24

1

126

118

108

84

73

63

53

51

75

73

66

53

50

47

44

1

All

Peripherals

enabled

60

30

Supply current

in RUN mode

from V₁₂and

V_DDsupply

25

I_DD12/ I_DD

mA

168

150

144

120

90

All

Peripherals

disabled

60

30

4

6

25

4

6

1. Guaranteed based on test during characterization.

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Symbol

Electrical characteristics

Table 29. Typical and maximum current consumption in Stop mode

Max⁽¹⁾

Parameter

Conditions

Typ

Unit

T_A=

25 °C 85 °C 105 °C

Flash memory in Stop mode, all

oscillators OFF, no independent

watchdog

0.63

0.58

0.50

0.44

3

2

17

15

33

28

Supply current in Stop

mode with voltage

regulator in main

regulator mode

Flash memory in Deep power

down mode, all oscillators OFF,

no independent watchdog

I_{DD_STOP_NM}

(normal mode)

Flash memory in Stop mode, all

oscillators OFF, no independent

watchdog

Supply current in Stop

mode with voltage

regulator in Low Power

regulator mode

Flash memory in Deep power

down mode, all oscillators OFF,

no independent watchdog

mA

Supply current in Stop

mode with voltage

regulator in main

regulator and under-

drive mode

Flash memory in Deep power

down mode, main regulator in

under-drive mode, all oscillators

OFF, no independent watchdog

0.21

0.14

1

6

12

13

I_{DD_STOP_UDM}

(under-drive

mode)

Supply current in Stop Flash memory in Deep power

mode with voltage down mode, Low Power regulator

regulator in Low Power in under-drive mode, all

regulator and under-

drive mode

oscillators OFF, no independent

watchdog

1. Data based on characterization, tested in production.

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Table 30. Typical and maximum current consumption in Standby mode

Typ⁽¹⁾

Max⁽²⁾

T_A=

T_A= 25 °C

Symbol

Parameter

Conditions

25 °C 85 °C 105 °C Unit

V_DD

1.7 V

=

V_DD

2.4 V

=

V_DD=

3.3 V

V_DD= 3.3 V

Backup SRAM ON, RTC and

LSE oscillator OFF

1.7

2.5

2.9

6⁽³⁾

5⁽³⁾

18

15

35⁽³⁾

30⁽³⁾

Backup SRAM OFF, RTC and

LSE oscillator OFF

1.0

1.7

1.8

2.7

2.20

3.2

Backup SRAM OFF, RTC ON

and LSE oscillator in Power

Drive mode

7

8

20

25

29

25

39

48

57

48

Supply current

in Standby

mode

Backup SRAM ON, RTC ON

and LSE oscillator in Power

Drive mode

I_{DD_STBY}

µA

2.4

3.2

2.5

3.4

4.2

3.5

4.0

4.8

4.1

Backup SRAM ON, RTC ON

and LSE oscillator in High

Drive mode

10

8

Backup SRAM OFF, RTC ON

and LSE oscillator in High

Drive mode

1. PDR is off for V_DD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by

additional 1.2 μA

2. Based on characterization, not tested in production unless otherwise specified.

3. Based on characterization, tested in production.

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Electrical characteristics

Table 31. Typical and maximum current consumption in V

Typ

mode

Max⁽²⁾

BAT

T_A=

25 °C

T_A=

T_A= 25 °C

Symbol Parameter

Conditions⁽¹⁾

85 °C 105 °C Unit

V_BAT= V_BAT= V_BAT

1.7 V 2.4 V 3.3 V

=

V_BAT= 3.3 V

Backup SRAM ON, RTC ON

and LSE oscillator in Low

Power mode

1.431 1.577 1.825

1.9

1.1

12.0

24.0

13.9

34.6

24.5

Backup SRAM OFF, RTC ON

and LSE oscillator in Low

Power mode

0.720 0.849 1.060

2.212 2.368 2.630

1.499 1.637 1.862

7.0

Backup SRAM ON, RTC ON

and LSE oscillator in High

Drive mode

Backup

I_{DD_VBAT}domainsupply

current

2.80

2.0

17.3

12.3

µA

Backup SRAM OFF, RTC ON

and LSE oscillator in High

Drive mode

Backup SRAM ON, RTC and

LSE OFF

0.710 0.720 0.760 0.8⁽³⁾

0.018 0.020 0.024 0.2⁽³⁾

5.0

2.0

10.0⁽³⁾

4.0⁽³⁾

Backup SRAM OFF, RTC and

LSE OFF

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C_Lof 6 pF for typical values.

2. Based on characterization, tested in production.

3. Based on test during characterization.

Figure 25. Typical V

current consumption

BAT

(RTC ON / backup SRAM ON and LSE in Low drive mode)

6

5

4

3

2

1

0

1.65V

1.70V

1.80V

2.00V

2.40V

2.70V

3.00V

3.30V

3.60V

0

20

40

60

80

100

Temperature (°C)

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Figure 26. Typical V

current consumption

BAT

(RTC ON / backup SRAM ON and LSE in High drive mode)

7

6

5

4

3

2

1

0

1.65V

1.70V

1.80V

2.00V

2.40V

2.70V

3.00V

3.30V

3.60V

0

20

40

60

80

100

Temperature (°C)

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 58.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 33), the I/Os used by

an application also contribute to the current consumption. When an I/O pin switches, it uses

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Electrical characteristics

the current from the MCU supply voltage to supply the I/O pin circuitry and to

charge/discharge the capacitive load (internal or external) connected to the pin:

I_SW= V_DD× f_SW× C

where

I

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage

SW

V

DD

f

is the I/O switching frequency

SW

C is the total capacitance seen by the I/O pin: C = C + C

INT

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

(1)

Table 32. Switching output I/O current consumption

I/O toggling

Symbol

Parameter

Conditions

Typ

Unit

frequency

(fsw)

2 MHz

8 MHz

0.0

0.2

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

0.6

V_DD= 3.3 V

1.1

(2)

C= C_INT

1.3

1.8

1.9

I/O switching

Current

I_DDIO

mA

0.1

8 MHz

0.4

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

1.23

2.43

2.93

3.86

4.07

V_DD= 3.3 V

C_EXT= 0 pF

C = C_INT+ C_EXT+ C_S

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(1)

Table 32. Switching output I/O current consumption (continued)

I/O toggling

Symbol

Parameter

Conditions

Typ

Unit

frequency

(fsw)

2 MHz

8 MHz

0.18

0.67

2.09

3.6

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

V_DD= 3.3 V

C_EXT= 10 pF

C = C_INT+ C_EXT+ C_S

4.5

7.8

9.8

0.26

1.01

3.14

6.39

10.68

0.33

1.29

4.23

11.02

I/O switching

Current

I_DDIO

mA

8 MHz

V_DD= 3.3 V

C_EXT= 22 pF

25 MHz

50 MHz

60 MHz

2 MHz

C = C_INT+ C_EXT+ C_S

V_DD= 3.3 V

8 MHz

C_EXT= 33 pF

25 MHz

50 MHz

C = C_INT+ Cext + C_S

1. C_Sis the PCB board capacitance including the pad pin. C_S= 7 pF (estimated value).

2. This test is performed by cutting the LQFP176 package pin (pad removal).

On-chip peripheral current consumption

The MCU is placed under the following conditions:

•

At startup, all I/O pins are in analog input configuration.

All peripherals are disabled unless otherwise mentioned.

I/O compensation cell enabled.

The ART accelerator is ON.

Scale 1 mode selected, internal digital voltage V12 = 1.32 V.

HCLK is the system clock. f

= f

/4, and f

= f

/2.

PCLK1

HCLK

PCLK2

HCLK

The given value is calculated by measuring the difference of current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

f

= 180 MHz (Scale1 + over-drive ON), f

= 120 MHz (Scale 3)

= 144 MHz (Scale 2),

HCLK

•

Ambient operating temperature is 25 °C and V =3.3 V.

DD

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Table 33. Peripheral current consumption

I

_DD(Typ)⁽¹⁾

Peripheral

Unit

Scale 1

Scale 2

Scale 3

GPIOA

3.16

2.67

3.00

2.62

2.31

2.10

2.48

2.27

2.13

2.20

2.37

2.03

2.06

33.89

0.55

0.74

2.58

2.25

2.10

1.79

2.23

2.08

1.98

2.02

2.17

1.86

GPIOB

GPIOC

2.42

GPIOD

2.22

GPIOE

2.60

GPIOF

2.39

GPIOG

2.27

GPIOH

2.34

GPIOI

2.52

AHB1

(up to

GPIOJ

2.16

µA/MHz

GPIOK

2.20

1.89

180 MHz)

OTG_HS+ULPI

CRC

36.49

0.62

29.90

0.50

BKPSRAM

DMA1⁽²⁾

DMA2⁽²⁾

DMA2D

0.83

0.63

3.3 x N + 6.8

3.4 x N + 5.7

33.33

3 x N + 6.3

3.1 x N + 5.3

30.66

2.7 x N + 5.5

2.8 x N + 4.6

26.98

ETH_MAC

ETH_MAC_TX

ETH_MAC_RX

ETH_MAC_PTP

22.30

20.69

18.19

USB_OTG_FS

DVCMI

RNG

34.33

3.61

1.94

2.42

4.14

31.96

3.35

1.82

2.24

3.80

28.35

2.98

AHB2

1.61

2.00

3.35

µA/MHz

(up to

180 MHz)

CRYP

HASH

AHB3

QUADSPI

FMC

16.83

15.57

13.83

µA/MHz

(up to

180 MHz)

17.22

12.17

15.92

11.19

14.00

9.97

Bus matrix⁽³⁾

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Table 33. Peripheral current consumption (continued)

I

_DD(Typ)⁽¹⁾

Peripheral

Unit

Scale 1

Scale 2

Scale 3

TIM2

19.11

15.62

16.22

18.44

3.18

3.11

8.67

6.11

6.44

17.44

5.44

5.51

5.22

5.33

5.56

5.24

4.78

5.11

4.78

4.11

4.33

8.89

7.22

2.89

1.73

17.56

14.22

14.64

16.72

2.69

2.56

7.56

5.33

5.61

15.61

4.64

4.72

4.64

4.78

4.64

4.08

4.50

4.08

3.53

3.67

7.83

6.44

2.69

1.44

15.33

12.17

12.83

14.00

2.17

2.00

6.50

4.43

4.67

13.53

3.93

4.00

3.83

4.10

3.93

3.43

3.73

3.43

3.00

3.17

6.87

5.50

2.40

1.00

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

PWR

USART2

USART3

UART4

UART5

UART7

UART8

I2C1

APB1

µA/MHz

(up to

45 MHz)

I2C2

I2C3

SPI2/I2S2⁽⁴⁾

SPI3/I2S3⁽⁴⁾

CAN1

CAN2

DAC⁽⁵⁾

WWDG

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Electrical characteristics

Table 33. Peripheral current consumption (continued)

I

_DD(Typ)⁽¹⁾

Peripheral

Unit

Scale 1

Scale 2

Scale 3

SDIO

7.94

19.44

8.44

5.67

5.72

5.06

5.00

5.26

4.83

2.11

7.18

17.81

7.60

5.03

5.10

4.54

4.47

4.75

4.33

1.76

1.69

1.76

1.35

34.53

3.01

30.32

6.37

15.80

6.77

4.50

4.55

4.05

3.97

4.17

TIM1

TIM8

TIM9

TIM10

TIM11

ADC1⁽⁶⁾

ADC2⁽⁶⁾

ADC3⁽⁶⁾

USART1

USART6

SPI1

APB2

(up to

3.83

1.60

1.22

30.60

2.72

26.87

µA/MHz

90 MHz)

SPI4

2.11

SPI5

2.11

SPI6

2.11

SYSCFG

LTDC

1.72

37.61

3.44

32.98

SAI1

DSI

1. When the I/O compensation cell is ON, I_DDtypical value increases by 0.22 mA.

2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,

N= [1..8]

3. The BusMatrix is automatically active when at least one master is ON.

4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.

5. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of

0.8 mA per DAC channel for the analog part.

6. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of

1.6 mA per ADC for the analog part.

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5.3.8

Wakeup time from low-power modes

The wakeup times given in Table 34 are measured starting from the wakeup event trigger up

to the first instruction executed by the CPU:

•

For Stop or Sleep modes: the wakeup event is WFE.

WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V =3.3 V.

DD

Table 34. Low-power mode wakeup timings

Typ⁽¹⁾Max⁽¹⁾

Symbol

Parameter

Conditions

Unit

CPU clock

cycles

(2)

t_WUSLEEP

Wakeup from Sleep

-

5

6

Main regulator is ON

12.9

13.0

Main regulator is ON and Flash

memory in Deep power down mode

105

109

Wakeup from Stop mode

with MR/LP regulator in

normal mode

(2)

t_WUSTOP

Low power regulator is ON

22

25.4

121

Low power regulator is ON and Flash

memory in Deep power down mode

114

µs

Main regulator in under-drive mode

(Flash memory in Deep power-down

mode)

107

111

Wakeup from Stop mode

with MR/LP regulator in

Under-drive mode

(2)

t_WUSTOP

Low power regulator in under-drive

mode (Flash memory in Deep

power-down mode)

115

318

121

371

(2)(3)

t_WUSTDBY

Wakeup from Standby mode

-

1. Based on test during characterization.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first

3. t_WUSTDBYmaximum value is given at –40 °C.

5.3.9

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 58. However, the recommended clock input

waveform is shown in Figure 27.

The characteristics given in Table 35 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions

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Electrical characteristics

summarized in Table 17.

Table 35. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External user clock source

frequency⁽¹⁾

f_{HSE_ext}

1

-

50

MHz

V_HSEH

V_HSEL

t_w(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

0.7V_DD

V_SS

-

V_DD

V

0.3V_DD

-

OSC_IN high or low time⁽¹⁾

OSC_IN rise or fall time⁽¹⁾

5

-

t_w(HSE)

ns

t_r(HSE)

t_f(HSE)

10

C_in(HSE)OSC_IN input capacitance⁽¹⁾

-

45

-

5

-

pF

%

DuCy_(HSE)Duty cycle

-

55

±1

I_L

OSC_IN Input leakage current

V_SS≤V_IN≤V_DD

-

µA

1. Guaranteed by design.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

external clock signal has to respect the Table 58. However, the recommended clock input

waveform is shown in Figure 28.

The characteristics given in Table 36 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions

summarized in Table 17.

Table 36. Low-speed external user clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{LSE_ext}

V_LSEH

V_LSEL

User External clock source frequency⁽¹⁾

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

-

32.768

1000

V_DD

kHz

0.7V_DD

V_SS

-

V

0.3V_DD

-

t_w(LSE)

t_f(LSE)

OSC32_IN high or low time⁽¹⁾

450

-

ns

t_r(LSE)

t_f(LSE)

OSC32_IN rise or fall time⁽¹⁾

50

C_in(LSE)

OSC32_IN input capacitance⁽¹⁾

-

30

-

5

-

pF

%

DuCy_(LSE)Duty cycle

-

70

±1

I_L

OSC32_IN Input leakage current

V_SS≤V_IN≤V_DD

-

µA

1. Guaranteed by design.

DocID028010 Rev 2

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187

Electrical characteristics

STM32F479xx

Figure 27. High-speed external clock source AC timing diagram

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in Table 37. In

the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

(1)

Table 37. HSE 4-26 MHz oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f_{OSC_IN}

R_F

Oscillator frequency

Feedback resistor

-

4

-

26

-

MHz

200

kΩ

112/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

(1)

Table 37. HSE 4-26 MHz oscillator characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

V_DD=3.3 V,

ESR= 30 Ω,

-

450

-

C_L=5 pF@25 MHz

I_DD

HSE current consumption

HSE accuracy

µA

V_DD=3.3 V,

ESR= 30 Ω,

C_L=10 pF@25 MHz

-

530

-

(2)

ACC_HSE

-

− 500

-

500

ppm

mA/V

ms

G_m_crit_max Maximum critical crystal g_m

Startup

-

1

-

(3)

t_SU(HSE)

Startup time

V_DDis stabilized

2

1. Guaranteed by design.

2. This parameter depends on the crystal used in the application. The minimum and maximum values must

be respected to comply with USB standard specifications.

3. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is based on characterization and not tested in production. It is measured

for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 29). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C .

C

L1

L2

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from www.st.com.

Figure 29. Typical application with an 8 MHz crystal

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1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

resonator oscillator. All the informations given in this paragraph are based on

characterization results obtained with typical external components specified in Table 38.

In the application, the resonator and the load capacitors have to be placed as close as

possible to the oscillator pins in order to minimize output distortion and startup stabilization

time. Refer to the crystal resonator manufacturer for more details on the resonator

characteristics (frequency, package, accuracy).

DocID028010 Rev 2

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187

Electrical characteristics

STM32F479xx

(1)

Table 38. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

R_F

Feedback resistor

-

18.4

-

1

MΩ

µA

Low power mode⁽²⁾

High drive mode⁽²⁾

-

I_DD

LSE current consumption

LSE accuracy

-

3

(3)

ACC_LSE

− 500

-

500

0.56

1.5

-

ppm

µA/V

s

Low power mode⁽²⁾

High drive mode⁽²⁾

V_DDis stabilized

-

G_m_crit_max Maximum critical crystal g_m

-

(4)

t_SU(LSE)

Startup time

2

1. Guaranteed by design.

2. LSE mode cannot be changed “on the fly” otherwise, a glitch can be generated on OSCIN pin.

3. This parameter depends on the crystal used in the application. Refer to application note AN2867.

4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is

measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from www.st.com.

Figure 30. Typical application with a 32.768 kHz crystal

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5.3.10

Internal clock source characteristics

The parameters given in Table 39 and Table 40 are derived from tests performed under

ambient temperature and V supply voltage conditions summarized in Table 17.

DD

High-speed internal (HSI) RC oscillator

(1)

Table 39. HSI oscillator characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

f_HSI

Frequency

-

16

-

1

MHz

%

HSI user trimming step⁽²⁾

HSI oscillator accuracy

-

T_A= –40 to 105 °C⁽³⁾

T_A= –10 to 85 °C⁽³⁾

T_A= 25 °C⁽⁴⁾

− 8

− 4

− 1

-

4.5

4

%

ACC_HSI

-

%

-

1

%

114/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

(1)

Table 39. HSI oscillator characteristics

(continued)

Symbol

Parameter

Conditions

Min Typ Max Unit

(2)

t_su(HSI)

HSI oscillator startup time

-

2.2

60

4

µs

(2)

I_DD(HSI)

HSI oscillator power consumption

80

µA

1. V_DD= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design

3. Based on test during characterization.

4. Factory calibrated, parts not soldered.

Figure 31. HSI deviation vs. temperature

HSI deviation versus temperature ⁽¹⁾

1.5%

1.0%

0.5%

0.0%

-0.5%

-1.0%

-1.5%

T_A(°C)

-40°C

0°C

25°C

85°C

105°C

Min

Max

Typical

1. Based on test during characterization.

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187

Electrical characteristics

STM32F479xx

Low-speed internal (LSI) RC oscillator

(1)

Table 40. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

(2)

f_LSI

Frequency

17

-

32

15

47

40

kHz

µs

(3)

t_su(LSI)

Startup time

(3)

I_DD(LSI)

Power consumption

-

0.4

0.6

µA

1.

V_DD= 3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Based on test during characterization.

3. Guaranteed by design.

Figure 32. ACC versus temperature

LSI

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5.3.11

PLL characteristics

The parameters given in Table 41 and Table 42 are derived from tests performed under

temperature and V supply voltage conditions summarized in Table 17.

DD

Table 41. Main PLL characteristics

Symbol

Parameter

PLL input clock⁽¹⁾

PLL multiplier output clock

Conditions

Min

Typ

Max Unit

f_{PLL_IN}

-

0.95⁽²⁾

24

1

-

2.10

f_{PLL_OUT}

180

MHz

75

f_{PLL48_OUT}48 MHz PLL multiplier output clock

f_{VCO_OUT}PLL VCO output

-

48

-

192

432

116/208

DocID028010 Rev 2

STM32F479xx

Symbol

Electrical characteristics

Table 41. Main PLL characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

VCO freq = 192 MHz

VCO freq = 432 MHz

75

-

200

t_LOCK

PLL lock time

µs

100

-

300

RMS

-

25

150

15

200

-

Cycle-to-cycle jitter

Period Jitter

peak to peak

RMS

System clock

120 MHz

peak to peak

Jitter⁽³⁾

ps

Main clock output (MCO) for RMII Cycle to cycle at 50 MHz on

-

32

40

330

-

Ethernet

1000 samples

Main clock output (MCO) for MII

Ethernet

Cycle to cycle at 25 MHz on

1000 samples

Cycle to cycle at 1 MHz on

1000 samples

Bit Time CAN jitter

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

(4)

I_DD(PLL)

PLL power consumption on VDD

PLL power consumption on VDDA

mA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

(4)

I_DDA(PLL)

-

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared

between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of 2 PLLs in parallel can degrade the Jitter up to +30%.

4. Based on test during characterization.

Table 42. PLLI2S (audio PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

f_{PLLI2S_IN}

PLLI2S input clock⁽¹⁾

-

0.95⁽²⁾

1

2.10

PLLI2S multiplier output

clock

f_{PLLI2S_OUT}

f_{VCO_OUT}

-

216 MHz

432

PLLI2S VCO output

192

75

100

-

VCO freq = 192 MHz

200

µs

300

t_LOCK

PLLI2S lock time

VCO freq = 432 MHz

-

Cycle to cycle at

RMS

90

-

12.288 MHz on 48KHz

period, N=432, R=5

peak to peak

-

280

ps

Master I2S clock jitter

WS I2S clock jitter

Average frequency of 12.288 MHz,

N=432, R=5

Jitter⁽³⁾

-

90

-

ps

on 1000 samples

Cycle to cycle at 48 KHz

on 1000 samples

-

400

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187

Electrical characteristics

STM32F479xx

Table 42. PLLI2S (audio PLL) characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max Unit

VCO freq = 192 MHz

0.15

0.45

0.40

PLLI2S power consumption

on V_DD

(4)

I_DD(PLLI2S)

-

VCO freq = 432 MHz

0.75

mA

0.40

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

PLLI2S power consumption

on V_DDA

(4)

I_DDA(PLLI2S)

-

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Based on test during characterization.

Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_{PLLSAI_IN}

f_{PLLSAI_OUT}

f_{VCO_OUT}

PLLSAI input clock⁽¹⁾

-

0.95⁽²⁾

1

-

2.10

216

432

200

300

-

PLLSAI multiplier output clock

PLLSAI VCO output

-

MHz

192

75

100

-

VCO freq = 192 MHz

VCO freq = 432 MHz

-

t_LOCK

PLLSAI lock time

µs

ps

-

RMS

90

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

peak

to

peak

-

280

90

-

Main SAI clock jitter

Average frequency of

12.288 MHz

Jitter⁽³⁾

-

ps

N = 432, R = 5

on 1000 samples

Cycle to cycle at 48 KHz

on 1000 samples

FS clock jitter

400

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

PLLSAI power consumption on

V_DD

(4)

I_DD(PLLSAI)

-

mA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

PLLSAI power consumption on

V_DDA

(4)

I_DDA(PLLSAI)

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Based on test during characterization.

118/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

5.3.12

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 54). It is available only on the main PLL.

Table 44. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max⁽¹⁾

Unit

f_Mod

md

Modulation frequency

-

0.25

-

10

2

KHz

%

Peak modulation depth

-

MODEPER * INCSTEP

1. Guaranteed by design.

2

¹⁵− 1

-

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round[f_{PLL_IN}⁄ (4 × f_Mod)]

f

and f

must be expressed in Hz.

PLL_IN

Mod

As an example:

If f = 1 MHz, and f

= 1 kHz, the modulation depth (MODEPER) is given by

PLL_IN

MOD

equation 1:

MODEPER = round[10⁶⁄ (4 × 10³)] = 250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round[((2¹⁵– 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]

f

must be expressed in MHz.

VCO_OUT

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP = round[((2¹⁵– 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is

obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage

quantized modulation depth is given by the following formula:

md_quantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((2¹⁵– 1) × PLLN)

As a result:

md_quantized% = (250 × 126 × 100 × 5) ⁄ ((2¹⁵– 1) × 240) = 2.002%(peak)

DocID028010 Rev 2

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187

Electrical characteristics

STM32F479xx

Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

nominal.

PLL_OUT

T

is the modulation period.

mode

md is the modulation depth.

Figure 33. PLL output clock waveforms in center spread mode

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5.3.13

MIPI D-PHY characteristics

The parameters given in Table 45 and Table 46 are derived from tests performed under

temperature and V supply voltage conditions summarized in Table 17.

DD

(1)

Table 45. MIPI D-PHY characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Hi-Speed Input/Output Characteristics

U_INST

UI instantaneous

-

2

-

12.5

ns

120/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

(1)

Table 45. MIPI D-PHY characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HS transmit common mode

voltage

V_CMTX

-

150

200

250

V_CMTXmismatch when output

is Differential-1 or Differential-0

|∆V_CMTX

|

-

140

-

200

-

5

mV

|V_OD

|∆V_OD

V_OHHS

Z_OS

|

HS transmit differential voltage

270

14

V_ODmismatch when output is

Differential-1 or Differential-0

|

HS output high voltage

-

360

62.5

Single ended output

impedance

40

50

Ω

Single ended output

impedance mismatch

∆Z_OS

-

10

%

t_HSr& t_HSf20%-80% rise and fall time

100

0.35*UI

ps

LP Receiver Input Characteristics

Logic 0 input voltage (not in

ULP State)

V_IL

-

550

300

Logic 0 input voltage in ULP

State

V_IL-ULPS

mV

V_IH

Input high level voltage

Voltage hysteresis

-

880

25

-

V_hys

LP Emitter Output Characteristics

V_IL

Output low level voltage

-

1.1

-50

1.2

-

1.2

50

V

V_IL-ULPSOutput high level voltage

mV

Output impedance of LP

transmitter

V_IH

-

110

-

Ω

V_hys

15%-85% rise and fall time

25

ns

LP Contention Detector Characteristics

V_ILCD

V_IHCD

Logic 0 contention threshold

-

200

-

mV

450

1. Guaranteed based on test during characterization.

DocID028010 Rev 2

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187

Electrical characteristics

STM32F479xx

(1)

Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Transmitted length of any Low-

Power state period

T_LPX

-

50

-

Time that the transmitter drives

the Clock Lane LP-00 Line

T_CLK-PREPAREstate immediately before the

HS-0 Line state starting the HS

transmission.

-

38

300

8

-

95

-

ns

T_CLK-PREPARETime that the transmitter drives

+

the HS-0 state prior to starting

the clock.

T_CLK-ZERO

Time that the HS clock shall be

driven by the transmitter prior to

any associated Data Lane

beginning the transition from

LP to HS mode.

T_CLK-PRE

-

UI

Time that the transmitter

continues to send HS clock

after the last associated Data

Lane has transitioned to LP

Mode.

T_CLK-POST

-

62+52*UI

-

Time that the transmitter drives

the HS-0 state after the last

payload clock bit of an HS

transmission burst.

T_CLK-TRAIL

60

-

Time that the transmitter drives

the Data Lane LP-00 Line state

T_HS-PREPAREimmediately before the HS-0

Line state starting the HS

transmission.

40+4*UI

145+10*UI

85+6*UI

T_HS-PREPARE+Time that the

transmitter drives the HS-0

T_HS-PREPARE

ns

+

-

state prior to transmitting the

T_HS-ZERO

Sync sequence.

Time that the transmitter drives

the flipped differential state

after last payload data bit of a

HS transmission burst.

Max

(n*8*UI,

60+n*4*UI)

T_HS-TRAIL

Time that the transmitter drives

T_HS-EXIT

-

100

-

LP-11 following a HS burst.

T_REOT

30%-85% rise time and fall time

35

Transmitted time interval from

the start of T_HS-TRAILor

T_CLK-TRAIL, to the start of the

LP-11 state following a HS

burst.

105+

n*12UI

T_EOT

-

1. Guaranteed based on test during characterization.

122/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

Figure 35. MIPI D-PHY HS/LP clock lane transition timing diagram

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Figure 36. MIPI D-PHY HS/LP data lane transition timing diagram

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5.3.14

MIPI D-PHY PLL characteristics

The parameters given in Table 47 are derived from tests performed under temperature and

V

supply voltage conditions summarized in Table 17.

DD

(1)

Table 47. DSI-PLL characteristics

Symbol

Parameter

Conditions

Min Typ

Max Unit

f_{PLL_IN}PLL input clock

-

4

-

100

f_{PLL_INFIN}PFD input clock

25

MHz

500

f_{PLL_OUT}PLL multiplier output clock

f_{VCO_OUT}PLL VCO output

31.25

500

-

1000

t_LOCK

PLL lock time

200

µs

DocID028010 Rev 2

123/208

187

Electrical characteristics

Symbol

STM32F479xx

Min Typ Max Unit

(1)

Table 47. DSI-PLL characteristics (continued)

Parameter

Conditions

f_{VCO_OUT}= 500 MHz

-

0.55 0.70

0.65 0.80

0.95 1.20

I_DD(PLL)PLL power consumption on V_DD12

1. Based on test during characterization.

f

_{VCO_OUT}= 600 MHz

mA

f_{VCO_OUT}= 1000 MHz

5.3.15

MIPI D-PHY regulator characteristics

The parameters given in Table 48 are derived from tests performed under temperature and

V

supply voltage conditions summarized in Table 17.

DD

(1)

Table 48. DSI regulator characteristics

Symbol

Parameter

Conditions

Min Typ Max Unit

V_DD12DSI1.2 V internal voltage on V_DD12DSI

-

1.15 1.20 1.30

V

C_EXT

ESR

External capacitor on V_CAPDSI

External Serial Resistor

1.1

0

2.2

25

3.3

μF

600 mΩ

I_DDDSIREGRegulator power consumption

100 120 125

µA

Ultra Low Power Mode

(Reg. ON + PLL OFF)

-

290 600

DSI system (regulator, PLL and

I_DDDSI

D-PHY) current consumption on V_DDDSI

Stop State

(Reg. ON + PLL OFF)

10 MHz escape clock

(Reg. ON + PLL OFF)

4.3

8.0

5.0

8.8

DSI system current consumption on

I_DDDSILP

mA

V_DDDSIin LP mode communication⁽²⁾

20 MHz escape clock

(Reg. ON + PLL OFF)

300 Mbps - 1 data lane

(Reg. ON + PLL ON)

300 Mbps - 2data lane

(Reg. ON + PLL ON)

11.4 12.5

13.5 14.7

18.0 19.6

DSI system (regulator, PLL and

D-PHY) current consumption on V_DDDSI

in HS mode communication⁽³⁾

I_DDDSIHS

500 Mbps - 1 data lane

(Reg. ON + PLL ON)

mA

500 Mbps - 2data lane

(Reg. ON + PLL ON)

DSI system (regulator, PLL and

D-PHY) current consumption on V_DDDSI

in HS mode with CLK like payload

500 Mbps - 2data lane

(Reg. ON + PLL ON)

-

21.4 23.3

C

_EXT= 2.2 µF

-

110

-

t_WAKEUPStartup delay

µs

C_EXT= 3.3 µF

160

200

I_INRUSH

Inrush current on V_DDDSI

External capacitor load at start

60

mA

1. Based on test during characterization.

2. Values based on an average traffic in LP Command Mode.

3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

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5.3.16

Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Table 49. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Write / Erase 8-bit mode, V_DD= 1.7 V

-

5

8

-

I_DD

Supply current Write / Erase 16-bit mode, V_DD= 2.1 V

Write / Erase 32-bit mode, V_DD= 3.3 V

-

mA

12

Table 50. Flash memory programming

Symbol

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

Program/eraseparallelism

(PSIZE) = x 8/16/32

t_prog

Word programming time

-

16

100⁽²⁾µs

800

Program/eraseparallelism

(PSIZE) = x 8

400

300

250

Program/eraseparallelism

(PSIZE) = x 16

t_ERASE16KBSector (16 KB) erase time

t_ERASE64KBSector (64 KB) erase time

t_ERASE128KBSector (128 KB) erase time

600

500

ms

s

Program/eraseparallelism

(PSIZE) = x 32

Program/eraseparallelism

(PSIZE) = x 8

1200 2400

Program/eraseparallelism

(PSIZE) = x 16

700

550

2

1400

1100

4

Program/eraseparallelism

(PSIZE) = x 32

Program/eraseparallelism

(PSIZE) = x 8

Program/eraseparallelism

(PSIZE) = x 16

1.3

1

2.6

2

Program/eraseparallelism

(PSIZE) = x 32

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Symbol

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Table 50. Flash memory programming (continued)

Parameter

Conditions

Min⁽¹⁾Typ Max⁽¹⁾Unit

Program/eraseparallelism

(PSIZE) = x 8

-

16

11

8

32

22

16

32

22

16

Program/eraseparallelism

(PSIZE) = x 16

t_ME

Mass erase time

Program/eraseparallelism

(PSIZE) = x 32

s

Program/eraseparallelism

(PSIZE) = x 8

16

11

8

Program/eraseparallelism

(PSIZE) = x 16

t_BE

Bank erase time

Program/eraseparallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

2.7

2.1

1.7

-

3.6

V_prog

Programming voltage

V

1. Based on test during characterization.

2. The maximum programming time is measured after 100K erase operations.

Table 51. Flash memory programming with V

PP

Symbol

Parameter

Conditions

Min⁽¹⁾

Typ

Max⁽¹⁾Unit

t_prog

Double word programming

-

16

230

490

875

6.9

-

100⁽²⁾

µs

t_ERASE16KBSector (16 KB) erase time

t_ERASE64KBSector (64 KB) erase time

t_ERASE128KBSector (128 KB) erase time

-

T_A= 0 to +40 °C

V_DD= 3.3 V

-

ms

V_PP= 8.5 V

-

t_ME

t_BE

Mass erase time

Bank erase time

-

s

-

V_prog

V_PP

Programming voltage

V_PPvoltage range

2.7

7

3.6

9

V

-

Minimum current sunk on

the V_PPpin

I_PP

-

10

-

mA

Cumulative time during

which V_PPis applied

(3)

t_VPP

1

hour

1. Guaranteed by design.

2. The maximum programming time is measured after 100K erase operations.

3. V_PPshould only be connected during programming/erasing.

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Table 52. Flash memory endurance and data retention

Value

Min⁽¹⁾

Symbol

Parameter

Conditions

Unit

T_A= –40 to +85 °C (6 suffix versions)

T_A= –40 to +105 °C (7 suffix versions)

N_ENDEndurance

kcycles

10

1 kcycle⁽²⁾at T_A= 85 °C

30

10

20

t_RET

Data retention 1 kcycle⁽²⁾at T_A= 105 °C

Years

10 kcycles⁽²⁾at T_A= 55 °C

1. Based on test during characterization.

2. Cycling performed over the whole temperature range.

5.3.17

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A burst of fast transient voltage (positive and negative) is applied to V and V

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant

with the IEC 61000-4-4 standard.

DD

SS

A device reset allows normal operations to be resumed.

The test results are given in Table 53. They are based on the EMS levels and classes

defined in application note AN1709.

Table 53. EMS characteristics

Symbol

Parameter

Conditions

Level/Class

V_DD= 3.3 V, TFBGA216,

T_A= +25 °C, f_HCLK= 168 MHz,

conforming to IEC 61000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

2B

Fast transient voltage burst limits to be

V_EFTBapplied through 100 pF on V_DDand V_SST_A= +25 °C, f_HCLK= 168 MHz,

V_DD= 3.3 V, TFBGA216,

4A

pins to induce a functional disturbance

conforming to IEC 61000-4-2

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

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Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,

?

executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2

standard which specifies the test board and the pin loading.

Table 54. EMI characteristics

Max vs. [f_HSE/f_CPU

]

Monitored

Symbol Parameter

Conditions

Unit

frequency band

8/168 MHz 8/180 MHz

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

0.1 to 30 MHz

2

4

2

1

V

_DD= 3.3 V, T_A= 25 °C, TFBGA216

dBµV

package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks

enabled, clock dithering disabled.

10

3

10

3

-

dBµV

-

S_EMI

Peak level

5

-10

-15

0

V_DD= 3.3 V, T_A= 25 °C, TFBGA216

package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks

enabled, clock dithering enabled

30 to 130 MHz

130 MHz to 1GHz

SAE EMI level

3

8

2

5.3.18

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.

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Symbol

Electrical characteristics

Maximum

Table 55. ESD absolute maximum ratings

Conditions

Ratings

Class

Unit

value⁽¹⁾

Electrostatic discharge

voltage

(human body model)

T_A= +25 °C

conforming to ANSI/ESDA/JEDEC JS-001

V_ESD(HBM)

2

2000

V

Electrostatic discharge

voltage

(charge device model)

T_A= +25 °C conforming to ANSI/ESD S5.3.1,

LQFP176, LQFP208, UFBGA169, UFBGA176,

TFBGA216 and WLCSP148 packages

V_ESD(CDM)

C3

250

1. Guaranteed based on test during characterization.

Static latchup

Two complementary static tests are required on six parts to assess the latchup

performance:

•

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

(1)

Table 56. Electrical sensitivities

Symbol

Parameter

Conditions

Class

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

II level A

1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.

5.3.19

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V (for standard, 3 V-capable I/O pins) should be avoided during normal product

DD

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –

5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency

deviation).

Negative induced leakage current is caused by negative injection and positive induced

leakage current by positive injection.

The test results are given in Table 57.

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Table 57. I/O current injection susceptibility⁽¹⁾

Functional susceptibility

Symbol

Description

Negative

Unit

Positive

injection

Injected current on BOOT0 and NRST pins

− 0

NA

0

Injected current on DSIHOST_D0P,

DSIHOST_D0N, DSIHOST_D1P, DSIHOST_D0N,

DSIHOST_CKP, DSIHOST_CKN pins

I_INJ

mA

Injected current on PA0 and PC0 pins

Injected current on any other FT pin

Injected current on any other pin

− 0

− 5

NA

+ 5

1. NA = not applicable.

Note:

It is recommended to add a Schottky diode (pin to ground) to analog pins which may

potentially inject negative currents.

5.3.20

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 58 are derived from tests

performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL

compliant.

Table 58. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

0.35V_DD−0.04⁽¹⁾

FT, TTa and NRST I/O input low

level voltage

1.7 V≤V_DD≤3.6 V

-

(2)

0.3V_DD

1.75 V≤V_DD≤3.6 V,

–40 °C≤T_A≤105 °C

V_IL

-

BOOT0 I/O input low level

voltage

0.1V_DD+0.1⁽¹⁾

1.7 V≤V_DD≤3.6 V,

0 °C≤T_A≤105 °C

-

V

0.45V_DD+0.3⁽¹⁾

FT, TTa and NRST I/O input

high level voltage⁽⁵⁾

1.7 V≤V_DD≤3.6 V

-

(2)

0.7V_DD

1.75 V≤V_DD≤3.6 V,

–40 °C≤T_A≤105 °C

V_IH

BOOT0 I/O input high level

voltage

0.17V_DD+0.7⁽¹⁾

1.7 V≤V_DD≤3.6 V,

0 °C≤T_A≤105 °C

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Symbol

Electrical characteristics

Table 58. I/O static characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

FT, TTa and NRST I/O input

hysteresis

(3)

1.7 V≤V_DD≤3.6 V

10%V_DD

-

1.75 V≤V_DD≤3.6 V, –

40 °C≤T_A≤105 °C

V_HYS

V

BOOT0 I/O input hysteresis

0.1

-

1.7 V≤V_DD≤3.6 V,

0 °C≤T_A≤105 °C

I/O input leakage current ⁽⁴⁾

V_SS≤V_IN≤V_DD

V_IN= 5 V

-

1

3

I_lkg

µA

I/O FT input leakage current ⁽⁵⁾

All pins

except for

PA10/PB12

(OTG_FS_ID,

30

7

40

10

40

50

14

50

Weak pull-up

equivalent

resistor⁽⁶⁾

R_PU

V_IN= V_SS

OTG_HS_ID)

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

kΩ

All pins

except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

30

Weak pull-

down

R_PD

V_IN= V_DD

equivalent

resistor⁽⁷⁾

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

7

-

10

5

14

-

(8)

C_IO

I/O pin capacitance

-

pF

1. Guaranteed by design.

2. Tested in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 57

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 57

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the

series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the

series resistance is minimum (~10% order).

8. Hysteresis voltage between Schmitt trigger switching levels. Based on test during characterization.

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All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT I/Os is shown in Figure 37.

Figure 37. FT I/O input characteristics

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or

source up to ±20 mA (with a relaxed V /V ) except PC13, PC14, PC15 and PI8 which

OL OH

can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output

mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 5.2. In particular:

•

The sum of the currents sourced by all the I/Os on V

plus the maximum Run

DD,

consumption of the MCU sourced on V

cannot exceed the absolute maximum rating

DD,

ΣI

(see Table 15).

VDD

•

The sum of the currents sunk by all the I/Os on V plus the maximum Run

SS

consumption of the MCU sunk on V cannot exceed the absolute maximum rating

SS

ΣI

(see Table 15).

VSS

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Output voltage levels

Unless otherwise specified, the parameters given in Table 59 are derived from tests

performed under ambient temperature and V supply voltage conditions summarized in

DD

Table 17. All I/Os are CMOS and TTL compliant.

Table 59. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

(1)

V_OL

Output low level voltage for an I/O pin

CMOS port⁽²⁾

I_IO= +8 mA

-

0.4

(3)

V_OH

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

V_DD− 0.4

-

0.4

-

2.7 V ≤V_DD≤3.6 V

(1)

V_OL

TTL port⁽²⁾

I_IO=+ 8mA

-

(3)

V_OH

2.4

2.7 V ≤V_DD≤3.6 V

(1)

V_OL

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

-

1.3⁽⁴⁾

V

I_IO= +20 mA

(3)

V_DD−1.3⁽⁴⁾

-

2.7 V ≤V_DD≤3.6 V

V_OH

V_OL

-

0.4⁽⁴⁾

(1)

I_IO= +6 mA

(3)

V_DD−0.4⁽⁴⁾

-

0.4⁽⁵⁾

-

1.8 V ≤V_DD≤3.6 V

V_OH

(1)

V_OL

I_IO= +4 mA

V_OH

V_DD−0.4⁽⁵⁾

(3)

1.7 V ≤V_DD≤3.6V

1. The I_IOcurrent sunk by the device must always respect the absolute maximum rating specified in Table 15.

and the sum of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I_IOcurrent sourced by the device must always respect the absolute maximum rating specified in

Table 15 and the sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

4. Based on characterization data.

5. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 38 and

Table 60, respectively.

Unless otherwise specified, the parameters given in Table 60 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 17.

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Max Unit

(1)(2)

Table 60. I/O AC characteristics

[1:0] bit

Symbol

Parameter

Conditions

Min

Typ

value⁽¹⁾

C_L= 50 pF, V_DD≥ 2.7 V

C_L= 50 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥ 1.8 V

C_L= 10 pF, V_DD≥ 1.7 V

-

4

2

f_max(IO)outMaximum frequency⁽³⁾

8

4

3

MHz

ns

00

Output high to low level fall

time and output low to high

level rise time

t_f(IO)out

/

C_L= 50 pF, V_DD= 1.7 V to

3.6 V

-

100

t_r(IO)out

C_L= 50 pF, V_DD≥ 2.7 V

C_L= 50 pF, V_DD≥ 1.8 V

C_L= 50 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥ 1.8 V

C_L= 10 pF, V_DD≥ 1.7 V

C_L= 50 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 50 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 1.7 V

C_L= 40 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 40 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 1.8 V

C_L= 10 pF, V_DD≥ 1.7 V

C_L= 40 pF, V_DD≥2.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 40 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 1.7 V

-

25

12.5

10

f_max(IO)outMaximum frequency⁽³⁾

MHz

50

20

01

12.5

10

Output high to low level fall

time and output low to high

level rise time

6

t_f(IO)out

t_r(IO)out

/

ns

MHz

ns

20

10

50⁽⁴⁾

100⁽⁴⁾

25

f_max(IO)outMaximum frequency⁽³⁾

50

10

42.5

6

Output high to low level fall

time and output low to high

level rise time

4

t_f(IO)out

t_r(IO)out

/

10

6

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(1)(2)

Table 60. I/O AC characteristics

(continued)

OSPEEDRy

[1:0] bit

Symbol

Parameter

Conditions

Min

Typ

Max Unit

value⁽¹⁾

C_L= 30 pF, V_DD≥ 2.7 V

C_L= 30 pF, V_DD≥ 1.8 V

C_L= 30 pF, V_DD≥ 1.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥ 1.8 V

C_L= 10 pF, V_DD≥ 1.7 V

C_L= 30 pF, V_DD≥ 2.7 V

C_L= 30 pF, V_DD≥1.8 V

C_L= 30 pF, V_DD≥1.7 V

C_L= 10 pF, V_DD≥ 2.7 V

C_L= 10 pF, V_DD≥1.8 V

C_L= 10 pF, V_DD≥1.7 V

-

100⁽⁴⁾

50

42.5

MHz

f_max(IO)outMaximum frequency⁽³⁾

180⁽⁴⁾

100

72.5

4

11

6

Output high to low level fall

time and output low to high

level rise time

7

t_f(IO)out

/

ns

2.5

t_r(IO)out

3.5

4

Pulse width of external signals

-

tEXTIpw detected by the EXTI

controller

-

10

-

ns

1. Guaranteed by design.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of

the GPIOx_SPEEDR GPIO port output speed register.

3. The maximum frequency is defined in Figure 38.

4. For maximum frequencies above 50 MHz and V_DD> 2.4 V, the compensation cell should be used.

Figure 38. I/O AC characteristics definition

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187

Electrical characteristics

STM32F479xx

5.3.21

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, R (see Table 58).

PU

Unless otherwise specified, the parameters given in Table 61 are derived from tests

performed under the ambient temperature and V supply voltage conditions summarized

DD

in Table 17.

Table 61. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_PU

Weak pull-up equivalent resistor⁽¹⁾

NRST Input filtered pulse

V_IN= V_SS

-

30

-

40

-

50

kΩ

(2)

V_F(NRST)

100

ns

µs

(2)

V_NF(NRST)

NRST Input not filtered pulse

V_DD> 2.7 V

Internal Reset source

300

20

-

T_{NRST_OUT}Generated reset pulse duration

-

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance must be minimum (~10% order).

2. Guaranteed by design.

Figure 39. Recommended NRST pin protection

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 61. Otherwise the reset is not taken into account by the device.

136/208

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Electrical characteristics

5.3.22

TIM timer characteristics

The parameters given in Table 62 are guaranteed by design. Refer to Section 5.3.20 for

details on the input/output alternate function characteristics (output compare, input capture,

external clock, PWM output).

(1)(2)

Table 62. TIMx characteristics

Conditions⁽³⁾

Symbol

Parameter

Min

Max

Unit

AHB/APBx prescaler=1

or 2 or 4, f_TIMxCLK

=

t_TIMxCLK

1

-

180 MHz

t_res(TIM)

Timer resolution time

AHB/APBx prescaler>4,

f_TIMxCLK= 90 MHz

t_TIMxCLK

1

-

Timer external clock

frequency on CH1 to CH4

f_EXT

f_TIMxCLK/2

16/32

0

-

MHz

bit

f

_TIMxCLK= 180 MHz

Res_TIM

Timer resolution

Maximum possible count

with 32-bit counter

65536 ×

65536

t_{MAX_COUNT}

t_TIMxCLK

-

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the

RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =

4x PCLKx.

5.3.23

Communications interfaces

I²C interface characteristics

2

The I C interface meets the timings requirements of the I C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s.

2

The I C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to RM0386 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and V is disabled, but is still present. Refer to

DD

2

for more details on the I C I/O characteristics

Section 5.3.20

.

2

All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog

filter characteristics:

(1)

Table 63. I2C analog filter characteristics

Symbol

Parameter

Min

Max

Unit

Maximum pulse width of spikes

that are suppressed by the analog

filter

t_AF

50⁽²⁾

150⁽³⁾

ns

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187

Electrical characteristics

STM32F479xx

1. Guaranteed based on test during characterization.

2. Spikes with widths below t_AF(min)are filtered.

3. Spikes with widths above t_AF(max)are not filtered

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 64 for the SPI interface are

derived from tests performed under the ambient temperature, f frequency and V

PCLKx

DD

supply voltage conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO for SPI).

(1)

Table 64. SPI dynamic characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Master mode, 2.7 V≤V_DD≤3.6 V,

SPI1,4,5,6,

-

45

Master mode, 1.71 V≤V_DD≤3.6 V,

SPI1,4,5,6

-

22.5⁽²⁾

45

Master transmitter mode,

1.7 V≤V_DD≤3.6 V, SPI1,4,5,6

f_SCK

Slave full duplex mode,

2.7 V≤V_DD≤3.6 V, SPI1,4,5,6

SPI clock frequency

-

22.5

33

MHz

1/t_c(SCK)

Slave transmitter mode,

1.71 V≤V_DD≤3.6 V, SPI1,4,5,6

-

Slave transmitter mode,

2.7 V≤V_DD≤3.6 V, SPI1,4,5,6

-

45

Slave mode, 1.71 V≤V_DD≤3.6 V,

SPI2,3

-

22.5

70

Duty cycle of SPI clock

frequency

Duty(SCK)

Slave mode

30

50

%

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Electrical characteristics

(1)

Table 64. SPI dynamic characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_w(SCKH)

T_PCLK

SCK high and low time Master mode, SPI presc = 2

T_PCLK− 1.5

T_PCLK+1.5

t_w(SCKL)

t_su(NSS)

t_h(NSS)

t_su(MI)

t_su(SI)

NSS setup time

NSS hold time

Slave mode, SPI presc = 2

Master mode

4T_PCLK

-

2T_PCLK

2

3

4

2

7

5

-

Data input setup time

Data input hold time

Slave mode

t_h(MI)

Master mode

-

t_h(SI)

Slave mode

-

ns

t_a(SO

)

Data output access time Slave mode, SPI presc = 2

Data output disable time Slave mode

Slave mode (after enable edge),

21

12

t_dis(SO)

-

11

15

2.7V ≤ V_DD≤ 3.6V

Data output valid time

t_v(SO)

Slave mode (after enable edge),

1.71 V≤V_DD≤3.6 V

11.5

t_h(SO)

t_v(MO)

t_h(MO)

Data output hold time Slave mode (after enable edge)

Data output valid time Master mode (after enable edge)

Data output hold time Master mode (after enable edge)

6

-

4.5

-

5

-

2

1. Guaranteed based on test during characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t_v(SO)and t_su(MI)which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having t_su(MI)= 0 while Duty(SCK) = 50%

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Figure 40. SPI timing diagram - slave mode and CPHA = 0

NSS input

t

c(SCK)

t

h(NSS)

SU(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

r(SCK)

f(SCK)

v(SO)

a(SO)

h(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134c

(1)

Figure 41. SPI timing diagram - slave mode and CPHA = 1

NSS input

t

h(NSS)

SU(NSS)

t

c(SCK)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

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(1)

Figure 42. SPI timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

MSBIN

t

BIT6 IN

LSB IN

INPUT

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

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Electrical characteristics

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I²S interface characteristics

2

Unless otherwise specified, the parameters given in Table 65 for the I S interface are

derived from tests performed under the ambient temperature, f frequency and V

PCLKx

DD

supply voltage conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output alternate function characteristics

(CK, SD, WS).

2

(1)

Table 65. I S dynamic characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

f_MCK

I2S Main clock output

I2S clock frequency

-

256x8K

256xFs⁽²⁾

Master data

Slave data

-

64xFs

MHz

%

f_CK

64xFs

D_CK

I2S clock frequency duty cycle Slave receiver

30

0

70

5

-

t_v(WS)

t_h(WS)

WS valid time

WS hold time

Master mode

Slave mode

0

3.5

-

t_su(WS)

WS setup time

WS hold time

Slave mode

3.5

0.5

1

-

PCM short pulse mode⁽³⁾

Slave mode

t_h(WS)

Slave mode

PCM short pulse mode⁽³⁾

ns

t_{su(SD_MR)}

t_{su(SD_SR)}

t_{h(SD_MR)}

t_{h(SD_SR)}

t_{v(SD_ST)}

t_{v(SD_MT)}

t_{h(SD_ST)}

t_{h(SD_MT)}

Master receiver

Slave receiver

Master receiver

Slave receiver

5

1.5

5

-

Data input setup time

Data input hold time

Data output valid time

Data output hold time

-

1.5

-

19

2.50

-

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

-

5

0

-

1. Guaranteed based on test during characterization.

2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).

3. Measurement done with respect to I2S_CK rising edge.

Note:

Refer to the I2S section of RM0386 reference manual for more details on the sampling

frequency (F ).

S

f

, f , and D values reflect only the digital peripheral behavior, source clock precision

CK

MCK CK

might slightly change the values. The values of these parameters might be slightly impacted

by the source clock precision. D depends mainly on the value of ODD bit. The digital

CK

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Electrical characteristics

contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of

(I2SDIV+ODD)/(2*I2SDIV+ODD). F maximum value is supported for each mode/condition.

S

2

(1)

Figure 43. I S slave timing diagram (Philips protocol)

t

c(CK)

CPOL = 0

CPOL = 1

WS input

t

w(CKL)

h(WS)

w(CKH)

t

v(SD_ST)

h(SD_ST)

su(WS)

SD

transmit

(2)

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

su(SD_SR)

h(SD_SR)

(2)

LSB receive

Bitn receive

LSB receive

SD

receive

ai14881b

1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

2

(1)

Figure 44. I S master timing diagram (Philips protocol)

t

r(CK)

f(CK)

t

c(CK)

CPOL = 0

CPOL = 1

WS output

t

w(CKH)

t

h(WS)

t

v(WS)

w(CKL)

t

v(SD_MT)

h(SD_MT)

(2)

SD

transmit

receive

LSB transmit

MSB transmit

MSB receive

Bitn transmit

LSB transmit

t

h(SD_MR)

su(SD_MR)

(2)

SD

LSB receive

Bitn receive

LSB receive

ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

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Electrical characteristics

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SAI characteristics

Unless otherwise specified, the parameters given in Table 66 for SAI are derived from tests

performed under the ambient temperature, f frequency and VDD supply voltage

PCLKx

conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C=30 pF

Measurement points are performed at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output alternate function

characteristics (SCK,SD,WS).

(1)

Table 66. SAI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

f_MCKL

SAI Main clock output

-

256 x 8K

256xFs

128xFs⁽³⁾

128xFs

Master data: 32 bits

Slave data: 32 bits

-

MHz

f_CK

SAI clock frequency⁽²⁾

FS valid time

Master mode,

2.7V ≤ V_DD≤ 3.6V

-

17

23

t_v(FS)

Master mode,

1.71V ≤ V_DD≤ 3.6V

t_su(FS)

t_h(FS)

FS setup time

FS hold time

Slave mode

10

0

-

t_{su(SD_MR)}

t_{su(SD_SR)}

t_{h(SD_MR)}

t_{h(SD_SR)}

Master receiver

Slave receiver

Master receiver

Slave receiver

1

Data input setup time

Data input hold time

2

6

1

ns

Slave transmitter (after enable edge),

-

14

2.7V ≤ V_DD≤ 3.6V

t_{h(SD_B_ST)}

t_{v(SD_A_MT)}

t_{h(SD_A_MT)}

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave transmitter (after enable edge),

-

9

-

23

-

1.71V ≤ V_DD≤ 3.6V

Slave transmitter (after enable edge)

Master transmitter (after enable edge),

20

2.7V ≤ V_DD≤ 3.6V

Master transmitter (after enable edge),

-

26

-

1.71V ≤ V_DD≤ 3.6V

Master transmitter (after enable edge)

10

1. Guaranteed based on test during characterization.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With Fs = 192 kHz.

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Electrical characteristics

Figure 45. SAI master timing waveforms

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DocID028010 Rev 2

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187

Electrical characteristics

STM32F479xx

USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 67. USB OTG full speed startup time

Symbol

Parameter

Max

Unit

(1)

t_STARTUP

USB OTG full speed transceiver startup time

1

µs

1. Guaranteed by design.

Table 68. USB OTG full speed DC electrical characteristics

Symbol

Parameter

Conditions

Min.⁽¹⁾Typ. Max.⁽¹⁾Unit

USB OTG full speed

V_DDtransceiver operating

voltage

-

3.0⁽²⁾

-

3.6

I(USB_FS_DP/DM,

USB_HS_DP/DM)

(3)

V_DI

Differential input sensitivity

0.2

0.8

1.3

-

Input

levels

Differential common mode

range

(3)

V

V_CM

Includes V_DIrange

2.5

2.0

Single ended receiver

threshold

(3)

V_SE

-

V_OLStatic output level low

V_OHStatic output level high

R_Lof 1.5 kΩto 3.6 V⁽⁴⁾

-

0.3

3.6

Output

levels

(4)

R_Lof 15 kΩto V_SS

2.8

PA11, PA12, PB14, PB15

(USB_FS_DP/DM,

17

21

24

USB_HS_DP/DM)

R_PD

V_IN= V_DD

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

0.65

1.5

1.1

1.8

2.0

2.1

kΩ

PA12, PB15 (USB_FS_DP,

USB_HS_DP)

V_IN= V_SS

R_PU

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

0.25 0.37 0.55

1. All the voltages are measured from the local ground potential.

2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed

electrical characteristics which are degraded in the 2.7-to-3.0 V V_DDvoltage range.

3. Guaranteed by design.

R_Lis the load connected on the USB OTG full speed drivers.

4.

When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state

(floating input), not as alternate function. A typical 200 µA current consumption of the

sensing block (current to voltage conversion to determine the different sessions) can be

observed on PA9 and PB13 when the feature is enabled.

Note:

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Electrical characteristics

Figure 47. USB OTG full speed timings: definition of data signal rise and fall time

Crossover

points

Differential

Data Lines

V

CR S

V

SS

t

r

f

ai14137

Table 69. USB OTG full speed electrical characteristics⁽¹⁾

Driver characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

t_r

t_f

Rise time⁽²⁾

Fall time⁽²⁾

C_L= 50 pF

4

20

ns

C_L= 50 pF

t_rfm

V_CRS

Rise/ fall time matching

t_r/t_f

-

90

1.3

110

2.0

%

V

Output signal crossover voltage

Driving

high or low

Z_DRV

Output driver impedance⁽³⁾

28

44

Ω

1. Guaranteed by design.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

2.

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching

impedance is included in the embedded driver.

USB high speed (HS) characteristics

Unless otherwise specified, the parameters given in Table 72 for ULPI are derived from

tests performed under the ambient temperature, f_HCLKfrequency summarized in Table 71

and V supply voltage conditions summarized in Table 70, with the following configuration:

DD

•

Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified

Capacitive load C = 20 pF / 15 pF, unless otherwise specified

Measurement points are done at CMOS levels: 0.5 V

.

DD

Refer to Section 5.3.20 for more details on the input/output characteristics.

Table 70. USB HS DC electrical characteristics

Symbol

Input level

Parameter

Min.⁽¹⁾

Max.⁽¹⁾

Unit

V_DD

USB OTG HS operating voltage

1.7

3.6

V

1. All the voltages are measured from the local ground potential.

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187

Electrical characteristics

STM32F479xx

(1)

Table 71. USB HS clock timing parameters

Symbol

Parameter

Min

Typ

Max

Unit

f

_HCLKvalue to guarantee proper operation of

-

30

-

USB HS interface

MHz

F_{START_8BIT}

F_STEADY

D_{START_8BIT}

D_STEADY

Frequency (first transition)

8-bit ±10%

54

59.97

40

60

50

66

60.03

60

Frequency (steady state) ±500 ppm

Duty cycle (first transition)

8-bit ±10%

%

ms

µs

Duty cycle (steady state) ±500 ppm

49.975

50.025

Time to reach the steady state frequency and

duty cycle after the first transition

t_STEADY

-

1.4

t_{START_DEV}

Peripheral

-

5.6

-

Clock startup time after the

de-assertion of SuspendM

t_{START_HOST}

Host

PHY preparation time after the first transition

of the input clock

t_PREP

-

1. Guaranteed by design.

Figure 48. ULPI timing diagram

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(1)

Table 72. Dynamic characteristics: USB ULPI

Symbol

Parameter

Conditions

Min.

Typ. Max. Unit

Control in (ULPI_DIR, ULPI_NXT)

setup time

t_SC

t_HC

-

2.0

-

Control in (ULPI_DIR, ULPI_NXT)

hold time

-

1.5

t_SD

t_HD

Data in setup time

Data in hold time

-

1.0

-

ns

2.7 V < V_DD< 3.6 V,

C_L= 20 pF

-

7.5

9.0

2.7 V < V_DD< 3.6 V,

C_L= 15 pF and

12.0

t

_DC/t_DDData/control output delay

-40 < T < 125°C

1.7 V < V_DD< 3.6 V,

C_L= 15 pF and

-40 < T < 90°C

-

7.5

11.5

1. Guaranteed based on test during characterization.

Ethernet characteristics

Unless otherwise specified, the parameters given in Table 74, Table 75 and Table 76 for

SMI, RMII and MII are derived from tests performed under the ambient temperature, f_HCLK

frequency summarized in Table 17 and V supply voltage conditions summarized in

DD

Table 73, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

.

DD

Refer to Section 5.3.20 for more details on the input/output characteristics.

Table 73. Ethernet DC electrical characteristics

Symbol

Input level

Parameter

Min.⁽¹⁾

Max.⁽¹⁾

Unit

V_DD

Ethernet operating voltage

2.7

3.6

V

1. All the voltages are measured from the local ground potential.

Table 74 gives the list of Ethernet MAC signals for the SMI (station management interface)

and Figure 49 shows the corresponding timing diagram.

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Figure 49. Ethernet SMI timing diagram

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Table 74. Dynamics characteristics: Ethernet MAC signals for SMI

Symbol

Parameter

Min

Typ

Max

Unit

t_MDC

MDC cycle time(2.38 MHz)

400

T_HCLK- 1

12.5

400

403

T_d(MDIO)Write data valid time

t_su(MDIO)Read data setup time

T_HCLK

T_HCLK+ 1.5

ns

-

t_h(MDIO)Read data hold time

0

1. Guaranteed based on test during characterization.

Table 75 gives the list of Ethernet MAC signals for the RMII and Figure 50 shows the

corresponding timing diagram.

Figure 50. Ethernet RMII timing diagram

RMII_REF_CLK

t_d(TXEN)

t_d(TXD)

RMII_TX_EN

RMII_TXD[1:0]

t_su(RXD)

t_su(CRS)

t_ih(RXD)

t_ih(CRS)

RMII_RXD[1:0]

RMII_CRS_DV

ai15667

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Electrical characteristics

(1)

Table 75. Dynamics characteristics: Ethernet MAC signals for RMII

Symbol

Parameter

Min

Typ

Max

Unit

t_su(RXD)Receive data setup time

t_ih(RXD)Receive data hold time

t_su(CRS)Carrier sense setup time

t_ih(CRS)Carrier sense hold time

t_d(TXEN)Transmit enable valid delay time

2.5

2.0

0.5

1.5

5.5

6.0

-

ns

-

6.5

11

t_d(TXD)

Transmit data valid delay time

1. Guaranteed based on test during characterization.

Table 76 gives the list of Ethernet MAC signals for MII and Figure 50 shows the

corresponding timing diagram.

Figure 51. Ethernet MII timing diagram

MII_RX_CLK

t

su(RXD)

su(ER)

su(DV)

ih(RXD)

ih(ER)

ih(DV)

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER

MII_TX_CLK

t

d(TXEN)

d(TXD)

MII_TX_EN

MII_TXD[3:0]

ai15668

(1)

Table 76. Dynamics characteristics: Ethernet MAC signals for MII

Symbol

Parameter

Min

Typ

Max

Unit

t_su(RXD)Receive data setup time

t_ih(RXD)Receive data hold time

1

3

-

t_su(DV)

t_ih(DV)

t_su(ER)

t_ih(ER)

Data valid setup time

Data valid hold time

Error setup time

0

-

2.5

0

-

ns

-

Error hold time

2

-

t_d(TXEN)Transmit enable valid delay time

t_d(TXD)Transmit data valid delay time

0

7

13

0

1. Guaranteed based on test during characterization.

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CAN (controller area network) interface

Refer to Section 5.3.20 for more details on the input/output alternate function characteristics

(CANx_TX and CANx_RX).

5.3.24

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 77 are derived from tests

performed under the ambient temperature, f

frequency and V

supply voltage

PCLK2

DDA

conditions summarized in Table 17.

Table 77. ADC characteristics

Conditions

Symbol

Parameter

Power supply

Min

Typ

Max

Unit

V_DDA

1.7⁽¹⁾

0.6

-

3.6

V_DDA

18

V_DDA−V_REF+< 1.2 V

V

V_REF+

Positive reference voltage

V_DDA= 1.7⁽¹⁾to 2.4 V

15

30

f_ADC

ADC clock frequency

MHz

V_DDA= 2.4 to 3.6 V

0.6

36

f

_ADC= 30 MHz,

-

1764

17

kHz

(2)

12-bit resolution

f_TRIG

External trigger frequency

Conversion voltage range⁽³⁾

-

1/f_ADC

0

V_AIN

-

V_REF+

V

(V_SSAor V_REF-

tied to ground)

(2)

R_AIN

External input impedance

Sampling switch resistance

Details in Equation 1

-

50

6

kΩ

(2)(4)

R_ADC

-

Internal sample and hold

capacitor

(2)

C_ADC

-

4

7

pF

f

_ADC= 30 MHz

-

0.100

3⁽⁵⁾

0.067

2⁽⁵⁾

16

µs

1/f_ADC

µs

Injection trigger conversion

latency

(2)

t_lat

-

_ADC= 30 MHz

-

Regular trigger conversion

latency

(2)

t_latr

-

1/f_ADC

µs

f_ADC= 30 MHz

0.100

-

(2)

t_S

Sampling time

Power-up time

-

3

-

480

3

1/f_ADC

µs

(2)

t_STAB

2

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Symbol

Electrical characteristics

Table 77. ADC characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

f_ADC= 30 MHz

12-bit resolution

0.50

-

16.40

f

_ADC= 30 MHz

0.43

0.37

0.30

-

16.34

16.27

16.20

10-bit resolution

µs

Total conversion time

f_ADC= 30 MHz

8-bit resolution

(2)

t_CONV

(including sampling time)

f_ADC= 30 MHz

6-bit resolution

9 to 492

1/f_ADC

(t_Sfor sampling +n-bit resolution for successive approximation)

12-bit resolution

-

2

Single ADC

12-bit resolution

Sampling rate

3.75

Interleave Dual ADC

mode

(2)

f_S

Msps

(f_ADC= 30 MHz, and

t_S= 3 ADC cycles)

12-bit resolution

-

6

Interleave Triple ADC

mode

ADC V_REF

DC current consumption in

conversion mode

(2)

I_VREF+

-

300

1.6

500

1.8

µA

ADC V_DDA

DC current consumption in

conversion mode

(2)

I_VDDA

mA

1. V_DDAminimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).

2. Based on test during characterization.

3. V_REF+is internally connected to V_DDAand V_REF-is internally connected to V_SSA

.

4. R_ADCmaximum value is given for V_DD=1.7 V, and minimum value for V_DD=3.3 V.

5. For external triggers, a delay of 1/f_PCLK2must be added to the latency specified in Table 77.

Equation 1: R

max formula

AIN

(k – 0.5)

----------------------------------------------------------------

– R_ADC

R_AIN

=

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of

sampling periods defined in the ADC_SMPR1 register.

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187

Electrical characteristics

Symbol

STM32F479xx

(1)

Table 78. ADC static accuracy at f

= 18 MHz

Typ

ADC

Parameter

Test conditions

Max⁽²⁾

Unit

ET

Total unadjusted error

±3

±4

f

_ADC=18 MHz

EO

EG

ED

EL

Offset error

±2

±1

±2

±3

±2

±3

V_DDA= 1.7 to 3.6 V

V_REF= 1.7 to 3.6 V

V_DDA−V_REF< 1.2 V

LSB

Gain error

Differential linearity error

Integral linearity error

1. Better performance could be achieved in restricted V_DD, frequency and temperature ranges.

2. Based on test during characterization.

a

(1)

Table 79. ADC static accuracy at f

= 30 MHz

Typ

ADC

Symbol

Parameter

Test conditions

Max⁽²⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

±2

±5

±2.5

±3

f

_ADC= 30 MHz,

±1.5

±1

R_AIN< 10 kΩ,

Gain error

V_DDA= 2.4 to 3.6 V,

V_REF= 1.7 to 3.6 V,

V_DDA−V_REF< 1.2 V

LSB

Differential linearity error

Integral linearity error

±2

±1.5

±3

1. Better performance could be achieved in restricted V_DD, frequency and temperature ranges.

2. Based on test during characterization.

(1)

Table 80. ADC static accuracy at f

= 36 MHz

ADC

Symbol

Parameter

Test conditions

Typ

Max⁽²⁾

Unit

ET

Total unadjusted error

±4

±7

f

_ADC=36 MHz,

EO

EG

ED

EL

Offset error

±2

±3

±2

±3

±6

±3

±6

V

_DDA= 2.4 to 3.6 V,

LSB

Gain error

V_REF= 1.7 to 3.6 V

Differential linearity error

Integral linearity error

V_DDA−V_REF< 1.2 V

1. Better performance could be achieved in restricted V_DD, frequency and temperature ranges.

2. Based on test during characterization.

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Electrical characteristics

(1)

Table 81. ADC dynamic accuracy at f

= 18 MHz - limited test conditions

ADC

Symbol

Parameter

Test conditions

Min

Typ

Max Unit

ENOB

SINAD

SNR

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

10.3

64

10.4

64.2

65

-

bits

f_ADC=18 MHz

V_DDA= V_REF+= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

64

dB

THD

Total harmonic distortion

− 67

− 72

1. Guaranteed based on test during characterization.

(1)

Table 82. ADC dynamic accuracy at f

= 36 MHz - limited test conditions

ADC

Symbol

Parameter

Test conditions

Min

Typ

Max Unit

ENOB

SINAD

SNR

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

10.6

66

10.8

67

-

bits

f_ADC=36 MHz

V_DDA= V_REF+= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

64

68

dB

THD

Total harmonic distortion

− 70

− 72

1. Guaranteed based on test during characterization.

Note:

ADC accuracy vs. negative injection current: injecting a negative current on any analog

input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to

ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

Section 5.3.20 does not affect the ADC accuracy.

and ΣI

in

INJ(PIN)

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STM32F479xx

Figure 52. ADC accuracy characteristics

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1. See also Table 79.

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E_T= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point

correlation line.

Figure 53. Typical connection diagram using the ADC

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1. Refer to Table 77 for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 5 pF). A high C_parasiticvalue downgrades conversion accuracy. To remedy this,

f

_ADCshould be reduced.

156/208

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Electrical characteristics

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 54 or Figure 55,

depending on whether V is connected to V or not. The 10 nF capacitors should be

REF+

DDA

ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 54. Power supply and reference decoupling (V not connected to V

)

DDA

REF+

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1. V_REF+and V_REF–inputs are both available on UFBGA176. V_REF+is also available on LQFP100, LQFP144,

and LQFP176. When V_REF+and V_REF–are not available, they are internally connected to V_DDAand V_SSA

.

Figure 55. Power supply and reference decoupling (V

connected to V

)

DDA

REF+

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1. V_REF+and V_REF–inputs are both available on UFBGA176. V_REF+is also available on LQFP100, LQFP144,

and LQFP176. When V_REF+and V_REF–are not available, they are internally connected to V_DDAand V_SSA

.

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187

Electrical characteristics

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5.3.25

Temperature sensor characteristics

Table 83. Temperature sensor characteristics

Parameter

Symbol

Min

Typ Max

Unit

(1)

T_L

V_SENSElinearity with temperature

-

1

2.5

0.76

6

2

°C

mV/°C

V

Avg_Slope⁽¹⁾Average slope

-

(1)

V₂₅

Voltage at 25 °C

-

10

-

(2)

t_START

Startup time

-

µs

(2)

T_{S_temp}

ADC sampling time when reading the temperature (1 °C accuracy)

10

-

1. Based on test during characterization.

2. Guaranteed by design.

Table 84. Temperature sensor calibration values

Symbol

Parameter

Memory address

0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C, V_DDA= 3.3 V

TS ADC raw data acquired at temperature of 110 °C, V_DDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

5.3.26

V

monitoring characteristics

BAT

Table 85. V

monitoring characteristics

BAT

Symbol

Parameter

Resistor bridge for V_BAT

Min

Typ

Max

Unit

R

Q

-

50

4

-

KΩ

Ratio on V_BATmeasurement

Error on Q

Er⁽¹⁾

–1

-

+1

%

ADC sampling time when reading the V_BAT

1 mV accuracy

(2)(2)

T_{S_vbat}

5

-

µs

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

5.3.27

Reference voltage

The parameters given in Table 86 are derived from tests performed under ambient

temperature and V supply voltage conditions summarized in Table 17.

DD

Table 86. internal reference voltage

Symbol

V_REFINT

Parameter

Conditions

Min

Max

Unit

Typ

Internal reference voltage

–40 °C < T_A< +105 °C 1.18 1.21

1.24

V

ADC sampling time when reading the

internal reference voltage

(1)

T_{S_vrefint}

10

-

µs

Internal reference voltage spread over the

temperature range

(2)

V_{RERINT_s}

V_DD= 3V 10mV

3

5

mV

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Electrical characteristics

Table 86. internal reference voltage (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

Typ

(2)

T_Coeff

Temperature coefficient

Startup time

-

30

6

50

10

ppm/°C

µs

(2)

t_START

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design

Table 87. Internal reference voltage calibration values

Parameter Memory address

V_{REFIN_CAL}Raw data acquired at temperature of 30 °C _VDDA= 3.3 V

Symbol

0x1FFF 7A2A - 0x1FFF 7A2B

5.3.28

DAC electrical characteristics

Table 88. DAC characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Comments

V_DDA

Analog supply voltage

1.7⁽¹⁾

-

3.6

V

-

V_REF+

V_SSA

Reference supply voltage

Ground

1.7⁽¹⁾

-

3.6

0

V

V_REF+≤V_DDA

0

5

-

(2)

R_LOAD

Resistive load with buffer ON

-

kΩ

-

When the buffer is OFF, the Minimum

Impedance output with buffer

OFF

(2)

R_O

-

15

50

kΩ resistive load between DAC_OUT and

_SSto have a 1% accuracy is 1.5 MΩ

V

Maximum capacitive load at DAC_OUT

pin (when the buffer is ON).

(2)

C_LOAD

Capacitive load

pF

It gives the maximum output excursion of

the DAC.

DAC_OUT Lower DAC_OUT voltage

min⁽²⁾

with buffer ON

0.2

-

V

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V_REF+= 3.6 V and

(0x1C7) to (0xE38) at V_REF+= 1.7 V

DAC_OUT Higher DAC_OUT voltage

max⁽²⁾

with buffer ON

V_DDA

0.2

−

-

0.5

-

V

mV

V

DAC_OUT Lower DAC_OUT voltage

min⁽²⁾

with buffer OFF

-

It gives the maximum output excursion of

the DAC.

DAC_OUT Higher DAC_OUT voltage

V_REF+

1LSB

max⁽²⁾

with buffer OFF

With no load, worst code (0x800) at

-

170

50

240

V_REF+= 3.6 V in terms of DC

consumption on the inputs

DAC DC V_REFcurrent

consumption in quiescent

mode (Standby mode)

(4)

I_VREF+

µA

With no load, worst code (0xF1C) at

75

V_REF+= 3.6 V in terms of DC

consumption on the inputs

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Electrical characteristics

STM32F479xx

Table 88. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

Comments

With no load, middle code (0x800) on the

inputs

-

280

380

µA

DAC DC VDDA current

consumption in quiescent

mode⁽³⁾

(4)

I_DDA

With no load, worst code (0xF1C) at

µA V_REF+= 3.6 V in terms of DC

consumption on the inputs

-

475

-

625

Differential non linearity

Difference between two

consecutive code-1LSB)

±0.5

LSB Given for the DAC in 10-bit configuration.

DNL⁽⁴⁾

-

±2

±1

LSB Given for the DAC in 12-bit configuration.

LSB Given for the DAC in 10-bit configuration.

Integral non linearity

(difference between

measured value at Code i

and the value at Code i on a

line drawn between Code 0

and last Code 1023)

INL⁽⁴⁾

-

±4

LSB Given for the DAC in 12-bit configuration.

-

±10

±3

mV Given for the DAC in 12-bit configuration

Offset error

Given for the DAC in 10-bit at V_REF+

3.6 V

=

(difference between

measured value at Code

(0x800) and the ideal value =

V_REF+/2)

LSB

%

Offset⁽⁴⁾

Given for the DAC in 12-bit at V_REF+

3.6 V

-

±12

Gain

Gain error

±0.5

Given for the DAC in 12-bit configuration

error⁽⁴⁾

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

(4)

t_SETTLING

-

3

6

µs

Total Harmonic Distortion

Buffer ON

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

THD⁽⁴⁾

-

dB

Max frequency for a correct

Update DAC_OUT change when

C_LOAD≤ 50 pF,

R_LOAD≥ 5 kΩ

1

MS/s

rate⁽²⁾

small variation in the input

code (from code i to i+1LSB)

C_LOAD≤ 50 pF, R_LOAD≥ 5 kΩ

input code between lowest and highest

possible ones.

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

(4)

t_WAKEUP

-

6.5

10

µs

Power supply rejection ratio

PSRR+ ⁽²⁾(to V_DDA) (static DC

measurement)

–67

–40

dB No R_LOAD, C_LOAD= 50 pF

1. V_DDAminimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed based on test during characterization.

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Electrical characteristics

Figure 56. 12-bit buffered/non-buffered DAC

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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

5.3.29

FMC characteristics

Unless otherwise specified, the parameters given in Tables 89 through 102 for the FMC

interface are derived from tests performed under the ambient temperature, f

frequency

HCLK

and V supply voltage conditions summarized in Table 17, with the following configuration:

DD

•

Output speed is set to OSPEEDRy[1:0] = 11

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figures 57 through 60 represent asynchronous waveforms, and Tables 89 through 96

provide the corresponding timings. The results shown in these tables are obtained with the

following FMC configuration:

•

AddressSetupTime = 0x1

AddressHoldTime = 0x1

DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

BusTurnAroundDuration = 0x0

Capacitive load C = 30 pF

L

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Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

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1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

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(1)

Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings

Symbol

Parameter

FMC_NE low time

Min

Max

Unit

t_w(NE)

t_{v(NOE_NE)}

t_w(NOE)

2T_HCLK− 0.5 2 T_HCLK+0.5

FMC_NEx low to FMC_NOE low

FMC_NOE low time

0

1

2T_HCLK

2T_HCLK+ 0.5

t_{h(NE_NOE)}

t_{v(A_NE)}

t_{h(A_NOE)}

t_{v(BL_NE)}

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

0

-

2

0

-

2

ns

t_{h(BL_NOE)}

t_{su(Data_NE)}

t_{su(Data_NOE)}

t_{h(Data_NOE)}

t_{h(Data_NE)}

t_{v(NADV_NE)}

t_w(NADV)

0

-

T_HCLK+ 2.5

-

T_HCLK+2

-

0

-

0

-

T_HCLK+1

1. Based on test during characterization.

Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT

(1)

timings

Symbol

Parameter

Min

Max

Unit

t_w(NE)

FMC_NE low time

7T_HCLK+0.5

7T_HCLK+1

t_w(NOE)

FMC_NWE low time

5T_HCLK− 1.5 5T_HCLK+2

ns

t_{su(NWAIT_NE)}

FMC_NWAIT valid before FMC_NEx high

5T_HCLK+1.5

-

FMC_NEx hold time after FMC_NWAIT

invalid

t_{h(NE_NWAIT)}

4T_HCLK+1

-

1. Based on test during characterization.

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187

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Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

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1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

(1)

Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Symbol

t_w(NE)

Parameter

Min

Max

Unit

FMC_NE low time

3T_HCLK

3T_HCLK+1

t_{v(NWE_NE)}

t_w(NWE)

t_{h(NE_NWE)}

t_{v(A_NE)}

FMC_NEx low to FMC_NWE low

FMC_NWE low time

T_HCLK− 0.5 T_HCLK+ 0.5

T_HCLK

T_HCLK+ 0.5

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

T_HCLK+1.5

-

0

t_{h(A_NWE)}

t_{v(BL_NE)}

t_{h(BL_NWE)}

t_{v(Data_NE)}

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

T_HCLK+0.5

-

ns

-

1.5

T_HCLK+0.5

-

T_HCLK+ 2

-

t_{h(Data_NWE)}Data hold time after FMC_NWE high

t_{v(NADV_NE)}FMC_NEx low to FMC_NADV low

T_HCLK+0.5

-

0.5

t_w(NADV)

FMC_NADV low time

T_HCLK+ 0.5

1. Based on test during characterization.

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Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT

(1)

timings

Symbol

Parameter

Min

Max

Unit

t_w(NE)

FMC_NE low time

FMC_NWE low time

8T_HCLK+1

8T_HCLK+2

t_w(NWE)

6T_HCLK− 1

6T_HCLK+1.5

4T_HCLK+1

6T_HCLK+2

ns

t_{su(NWAIT_NE)}FMC_NWAIT valid before FMC_NEx high

t_{h(NE_NWAIT)}FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

-

Figure 59. Asynchronous multiplexed PSRAM/NOR read waveforms

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DocID028010 Rev 2

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187

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(1)

Table 93. Asynchronous multiplexed PSRAM/NOR read timings

Symbol

Parameter

FMC_NE low time

Min

Max

Unit

t_w(NE)

t_{v(NOE_NE)}

t_tw(NOE)

3T_HCLK− 1 3T_HCLK+0.5

FMC_NEx low to FMC_NOE low

FMC_NOE low time

2T_HCLK− 0.5

2T_HCLK

T_HCLK− 1

T_HCLK+1

t_{h(NE_NOE)}

t_{v(A_NE)}

t_{v(NADV_NE)}

t_w(NADV)

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1

-

2

0

T_HCLK− 0.5 T_HCLK+0.5

FMC_AD(address) valid hold time after

FMC_NADV high)

t_{h(AD_NADV)}

0

-

ns

t_{h(A_NOE)}

t_{h(BL_NOE)}

t_{v(BL_NE)}

Address hold time after FMC_NOE high

FMC_BL time after FMC_NOE high

FMC_NEx low to FMC_BL valid

T_HCLK− 0.5

-

0

-

2

-

t_{su(Data_NE)}

t_{su(Data_NOE)}

t_{h(Data_NE)}

t_{h(Data_NOE)}

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

T_HCLK+1.5

T_HCLK+1

-

0

-

1. Based on test during characterization.

(1)

Table 94. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

Symbol

Parameter

Min

Max

Unit

t_w(NE)

FMC_NE low time

FMC_NWE low time

8T_HCLK+0.5

8T_HCLK+2

ns

t_w(NOE)

5T_HCLK− 1 5T_HCLK+1.5

t_{su(NWAIT_NE)}FMC_NWAIT valid before FMC_NEx high

t_{h(NE_NWAIT)}FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

5T_HCLK+1.5

4T_HCLK+1

-

166/208

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Figure 60. Asynchronous multiplexed PSRAM/NOR write waveforms

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(1)

Table 95. Asynchronous multiplexed PSRAM/NOR write timings

Symbol

Parameter

Min

Max

4T_HCLK+0.5

Unit

t_w(NE)

FMC_NE low time

4T_HCLK

t_{v(NWE_NE)}FMC_NEx low to FMC_NWE low

t_w(NWE)FMC_NWE low time

t_{h(NE_NWE)}FMC_NWE high to FMC_NE high hold time

t_{v(A_NE)}FMC_NEx low to FMC_A valid

t_{v(NADV_NE)}FMC_NEx low to FMC_NADV low

T_HCLK− 1 T_HCLK+0.5

2T_HCLK

T_HCLK

-

2T_HCLK+0.5

-

0

1

0.5

t_w(NADV)

FMC_NADV low time

T_HCLK− 0.5 T_HCLK+ 0.5

ns

FMC_AD (address) valid hold time

after FMC_NADV high

t_{h(AD_NADV)}

T_HCLK− 2

-

t_{h(A_NWE)}Address hold time after FMC_NWE high

t_{h(BL_NWE)}FMC_BL hold time after FMC_NWE high

T_HCLK

-

T_HCLK− 2

-

t_{v(BL_NE)}

FMC_NEx low to FMC_BL valid

-

2

t_{v(Data_NADV)}FMC_NADV high to Data valid

t_{h(Data_NWE)}Data hold time after FMC_NWE high

1. Based on test during characterization.

-

T_HCLK+1.5

-

T_HCLK+0.5

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Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings

Symbol

Parameter

Min

Max

Unit

t_w(NE)

FMC_NE low time

FMC_NWE low time

9T_HCLK

9T_HCLK+0.5

t_w(NWE)

7T_HCLK

6T_HCLK+1.5

4T_HCLK–1

7T_HCLK+2

ns

t_{su(NWAIT_NE)}FMC_NWAIT valid before FMC_NEx high

t_{h(NE_NWAIT)}FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

-

Synchronous waveforms and timings

Figures 61 through 64 represent synchronous waveforms and Table 97 through Table 100

provide the corresponding timings. The results shown in these tables are obtained with the

following FMC configuration:

•

BurstAccessMode = FMC_BurstAccessMode_Enable;

MemoryType = FMC_MemoryType_CRAM;

WriteBurst = FMC_WriteBurst_Enable;

CLKDivision = 1;

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

C = 30 pF on data and address lines. C = 10 pF on FMC_CLK unless otherwise

L

specified.

In all timing tables, the T_HCLKis the HCLK clock period:

•

For 2.7 V≤ V ≤ 3.6 V, maximum FMC_CLK = 90 MHz at C = 30 pF (on FMC_CLK).

DD L

For 1.71 V≤ V <1.9 V, maximum FMC_CLK = 60 MHz at C = 10 pF (on FMC_CLK).

DD

L

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Figure 61. Synchronous multiplexed NOR/PSRAM read timings

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DocID028010 Rev 2

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(1)

Table 97. Synchronous multiplexed NOR/PSRAM read timings

Symbol

Parameter

Min

Max

Unit

t_w(CLK)

FMC_CLK period

2T_HCLK− 1

-

0

-

t_d(CLKL-NExL)FMC_CLK low to FMC_NEx low (x=0..2)

t_{d(CLKH_NExH)}FMC_CLK high to FMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FMC_CLK low to FMC_NADV low

t_{d(CLKL-NADVH)}FMC_CLK low to FMC_NADV high

-

T_HCLK

-

0

-

0

t_d(CLKL-AV)

t_d(CLKH-AIV)

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

-

0

-

0

t_d(CLKL-NOEL)FMC_CLK low to FMC_NOE low

t_d(CLKH-NOEH)FMC_CLK high to FMC_NOE high

t_d(CLKL-ADV)FMC_CLK low to FMC_AD[15:0] valid

t_d(CLKL-ADIV)FMC_CLK low to FMC_AD[15:0] invalid

t_su(ADV-CLKH)FMC_A/D[15:0] valid data before FMC_CLK high

t_h(CLKH-ADV)FMC_A/D[15:0] valid data after FMC_CLK high

t_{su(NWAIT-CLKH)}FMC_NWAIT valid before FMC_CLK high

t_{h(CLKH-NWAIT)}FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

-

T_HCLK+0.5 ns

T_HCLK− 0.5

-

0

5

0

4

0

0.5

-

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Electrical characteristics

Figure 62. Synchronous multiplexed PSRAM write timings

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DocID028010 Rev 2

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(1)

Table 98. Synchronous multiplexed PSRAM write timings

Symbol

Parameter

Min

Max

Unit

t_w(CLK)

FMC_CLK period, V_DDrange= 2.7 to 3.6 V

2T_HCLK− 1

-

1.5

-

t_d(CLKL-NExL)FMC_CLK low to FMC_NEx low (x=0…2)

t_d(CLKH-NExH)FMC_CLK high to FMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FMC_CLK low to FMC_NADV low

t_{d(CLKL-NADVH)}FMC_CLK low to FMC_NADV high

-

T_HCLK

-

0

-

0

t_d(CLKL-AV)

t_d(CLKH-AIV)

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

-

0

-

T_HCLK

t_d(CLKL-NWEL)FMC_CLK low to FMC_NWE low

t_(CLKH-NWEH)FMC_CLK high to FMC_NWE high

t_d(CLKL-ADV)FMC_CLK low to FMC_AD[15:0] valid

t_d(CLKL-ADIV)FMC_CLK low to FMC_AD[15:0] invalid

t_d(CLKL-DATA)FMC_A/D[15:0] valid data after FMC_CLK low

t_d(CLKL-NBLL)FMC_CLK low to FMC_NBL low

t_d(CLKH-NBLH)FMC_CLK high to FMC_NBL high

t_{su(NWAIT-CLKH)}FMC_NWAIT valid before FMC_CLK high

t_{h(CLKH-NWAIT)}FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

-

0

-

ns

T_HCLK−0.5

-

3

-

0

-

3

-

0

T_HCLK−0.5

-

4

0

-

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Figure 63. Synchronous non-multiplexed NOR/PSRAM read timings

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SUꢋ.7!)46ꢎ#,+(ꢌ

&-#?.7!)4

ꢋ7!)4#&' ꢄ ꢂBꢑ

7!)40/, ꢐ ꢂBꢌ

T

SUꢋ.7!)46ꢎ#,+(ꢌ

Hꢋ#,+(ꢎ.7!)46ꢌ

-3ꢊꢃꢈꢅꢁ6ꢀ

(1)

Table 99. Synchronous non-multiplexed NOR/PSRAM read timings

Symbol

Parameter

Min

Max

Unit

t_w(CLK)

FMC_CLK period

2T_HCLK− 1

-

t_(CLKL-NExL)FMC_CLK low to FMC_NEx low (x=0…2)

t_d(CLKH-NExH)FMC_CLK high to FMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FMC_CLK low to FMC_NADV low

t_{d(CLKL-NADVH)}FMC_CLK low to FMC_NADV high

-

0.5

T_HCLK

-

0

-

t_d(CLKL-AV)

t_d(CLKH-AIV)

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

-

0

T_HCLK− 0.5

-

ns

t_d(CLKL-NOEL)FMC_CLK low to FMC_NOE low

-

T_HCLK+2

t_d(CLKH-NOEH)FMC_CLK high to FMC_NOE high

t_su(DV-CLKH)FMC_D[15:0] valid data before FMC_CLK high

T_HCLK− 0.5

-

5

0

4

0

t_h(CLKH-DV)

FMC_D[15:0] valid data after FMC_CLK high

t_(NWAIT-CLKH)FMC_NWAIT valid before FMC_CLK high

t_{h(CLKH-NWAIT)}FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

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Figure 64. Synchronous non-multiplexed PSRAM write timings

T

Wꢋ#,+ꢌ

&-#?#,+

T

Dꢋ#,+,ꢎ.%X,ꢌ

&-#?.%X

Dꢋ#,+(ꢎ.%X(ꢌ

$ATA LATENCY ꢄ ꢂ

Dꢋ#,+,ꢎ.!$6(ꢌ

T

Dꢋ#,+,ꢎ.!$6,ꢌ

&-#?.!$6

&-#?!;ꢃꢅꢒꢂ=

&-#?.7%

T

Dꢋ#,+(ꢎ!)6ꢌ

T

Dꢋ#,+,ꢎ!6ꢌ

TDꢋ#,+(ꢎ.7%(ꢌ

Dꢋ#,+,ꢎ.7%,ꢌ

T

Dꢋ#,+,ꢎ$ATAꢌ

&-#?$;ꢀꢅꢒꢂ=

$ꢀ

$ꢃ

&-#?.7!)4

ꢋ7!)4#&' ꢄ ꢂBꢑ 7!)40/, ꢐ ꢂBꢌ

&-#?.",

T

Dꢋ#,+(ꢎ.",(ꢌ

SUꢋ.7!)46ꢎ#,+(ꢌ

T

Hꢋ#,+(ꢎ.7!)46ꢌ

-3ꢊꢃꢈꢇꢂ6ꢀ

(1)

Table 100. Synchronous non-multiplexed PSRAM write timings

Symbol

Parameter

Min

Max

Unit

t_(CLK)

FMC_CLK period

2T_HCLK− 1

-

0.5

-

t_d(CLKL-NExL)FMC_CLK low to FMC_NEx low (x=0…2)

t_(CLKH-NExH)FMC_CLK high to FMC_NEx high (x= 0…2)

t_{d(CLKL-NADVL)}FMC_CLK low to FMC_NADV low

t_{d(CLKL-NADVH)}FMC_CLK low to FMC_NADV high

-

T_HCLK

-

0

-

0

t_d(CLKL-AV)

t_d(CLKH-AIV)

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

-

0

-

0

ns

t_d(CLKL-NWEL)FMC_CLK low to FMC_NWE low

t_d(CLKH-NWEH)FMC_CLK high to FMC_NWE high

t_d(CLKL-Data)FMC_D[15:0] valid data after FMC_CLK low

t_d(CLKL-NBLL)FMC_CLK low to FMC_NBL low

t_d(CLKH-NBLH)FMC_CLK high to FMC_NBL high

t_{su(NWAIT-CLKH)}FMC_NWAIT valid before FMC_CLK high

t_{h(CLKH-NWAIT)}FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

-

0

-

T_HCLK−0.5

-

2.5

-

0

T_HCLK−0.5

-

4

0

-

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Electrical characteristics

NAND controller waveforms and timings

Figures 65 through 68 represent synchronous waveforms, and Table 101 and Table 102

provide the corresponding timings. The results shown in this table are obtained with the

following FMC configuration:

•

COM.FMC_SetupTime = 0x01;

COM.FMC_WaitSetupTime = 0x03;

COM.FMC_HoldSetupTime = 0x02;

COM.FMC_HiZSetupTime = 0x01;

ATT.FMC_SetupTime = 0x01;

ATT.FMC_WaitSetupTime = 0x03;

ATT.FMC_HoldSetupTime = 0x02;

ATT.FMC_HiZSetupTime = 0x01;

Bank = FMC_Bank_NAND;

MemoryDataWidth = FMC_MemoryDataWidth_16b;

ECC = FMC_ECC_Enable;

ECCPageSize = FMC_ECCPageSize_512Bytes;

TCLRSetupTime = 0;

TARSetupTime = 0;

Capacitive load C = 30 pF.

L

In all timing tables, the T_HCLKis the HCLK clock period.

Figure 65. NAND controller waveforms for read access

&-#?.#%X

!,% ꢋ&-#?!ꢀꢈꢌ

#,% ꢋ&-#?!ꢀꢇꢌ

&-#?.7%

T

THꢋ./%ꢎ!,%ꢌ

Dꢋ!,%ꢎ./%ꢌ

&-#?./% ꢋ.2%ꢌ

&-#?$;ꢀꢅꢒꢂ=

T

Hꢋ./%ꢎ$ꢌ

SUꢋ$ꢎ./%ꢌ

-3ꢊꢃꢈꢇꢈ6ꢀ

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Figure 66. NAND controller waveforms for write access

&-#?.#%X

!,% ꢋ&-#?!ꢀꢈꢌ

#,% ꢋ&-#?!ꢀꢇꢌ

T

Hꢋ.7%ꢎ!,%ꢌ

Dꢋ!,%ꢎ.7%ꢌ

&-#?.7%

&-#?./% ꢋ.2%ꢌ

&-#?$;ꢀꢅꢒꢂ=

T

Hꢋ.7%ꢎ$ꢌ

Vꢋ.7%ꢎ$ꢌ

-3ꢊꢃꢈꢇꢉ6ꢀ

Figure 67. NAND controller waveforms for common memory read access

&-#?.#%X

!,% ꢋ&-#?!ꢀꢈꢌ

#,% ꢋ&-#?!ꢀꢇꢌ

T

Hꢋ./%ꢎ!,%ꢌ

Dꢋ!,%ꢎ./%ꢌ

&-#?.7%

&-#?./%

T

Wꢋ./%ꢌ

T

Hꢋ./%ꢎ$ꢌ

SUꢋ$ꢎ./%ꢌ

&-#?$;ꢀꢅꢒꢂ=

-3ꢊꢃꢈꢇꢁ6ꢀ

176/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

Figure 68. NAND controller waveforms for common memory write access

&-#?.#%X

!,% ꢋ&-#?!ꢀꢈꢌ

#,% ꢋ&-#?!ꢀꢇꢌ

T

Hꢋ./%ꢎ!,%ꢌ

Dꢋ!,%ꢎ./%ꢌ

Wꢋ.7%ꢌ

&-#?.7%

&-#?. /%

T

Dꢋ$ꢎ.7%ꢌ

T

Vꢋ.7%ꢎ$ꢌ

Hꢋ.7%ꢎ$ꢌ

&-#?$;ꢀꢅꢒꢂ=

-3ꢊꢃꢈꢈꢂ6ꢀ

Table 101. Switching characteristics for NAND Flash read cycles

Parameter Min Max

FMC_NOE low width 4T_HCLK− 0.5 4T_HCLK+0.5

Symbol

Unit

t_w(N0E)

t_su(D-NOE)FMC_D[15-0] valid data before FMC_NOE high

t_h(NOE-D)FMC_D[15-0] valid data after FMC_NOE high

9

-

0

-

ns

t_d(ALE-NOE)FMC_ALE valid before FMC_NOE low

t_h(NOE-ALE)FMC_NWE high to FMC_ALE invalid

-

3T_HCLK− 0.5

3T_HCLK− 2

-

Table 102. Switching characteristics for NAND Flash write cycles

Symbol

Parameter

FMC_NWE low width

Min

Max

Unit

t_w(NWE)

t_v(NWE-D)

t_h(NWE-D)

t_d(D-NWE)

t_d(ALE-NWE)

t_h(NWE-ALE)

4T_HCLK

0

4T_HCLK+1

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

-

3T_HCLK− 1

5T_HCLK− 3

-

ns

-

3T_HCLK−0.5

3T_HCLK− 1

-

SDRAM waveforms and timings

•

C = 30 pF on data and address lines.

L

C = 10 pF on FMC_SDCLK unless otherwise specified.

L

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187

Electrical characteristics

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In all timing tables, the T_HCLKis the HCLK clock period.

•

For 2.7 V ≤ V ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at C = 30 pF (on

DD L

FMC_SDCLK).

•

For 1.71 V≤ V <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and

DD

60 MHz for CAS latency 1 or 2. C = 10 pF (on FMC_SDCLK).

L

Figure 69. SDRAM read access waveforms (CL = 1)

&-#?3$#,+

TDꢋ3$#,+,?!DD#ꢌ

THꢋ3$#,+,?!DD2ꢌ

TDꢋ3$#,+,?!DD2ꢌ

2OW N

#OLꢀ

#OLꢃ

#OLI

#OLN

&-#?!>ꢅꢂꢎꢇ@

THꢋ3$#,+,?!DD#ꢌ

THꢋ3$#,+,?3.$%ꢌ

THꢋ3$#,+,?.#!3ꢌ

TDꢋ3$#,+,?3.$%ꢌ

&-#?3$.%;ꢀꢒꢂ=

TDꢋ3$#,+,?.2!3ꢌ

THꢋ3$#,+,?.2!3ꢌ

&-#?3$.2!3

&-#?3$.#!3

TDꢋ3$#,+,?.#!3ꢌ

&-#?3$.7%

&-#?$;ꢊꢀꢒꢂ=

TSUꢋ3$#,+(?$ATAꢌ

THꢋ3$#,+(?$ATAꢌ

$ATAꢀ $ATAꢃ

$ATAI

$ATAN

-3ꢊꢃꢈꢅꢀ6ꢃ

(1)

Table 103. SDRAM read timings

Symbol

Parameter

Min

Max

Unit

t_w(SDCLK)

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

2T_HCLK− 0.5

2T_HCLK+0.5

t_{su(SDCLKH _Data)}

t_{h(SDCLKH_Data)}

t_{d(SDCLKL_Add)}

2

0

-

1.5

0.5

-

t_{d(SDCLKL- SDNE)}

t_{h(SDCLKL_SDNE)}

t_{d(SDCLKL_SDNRAS)}

t_{h(SDCLKL_SDNRAS)}

t_{d(SDCLKL_SDNCAS)}

t_{h(SDCLKL_SDNCAS)}

-

ns

0

-

0.5

-

0

-

0.5

-

0

1. Guaranteed based on test during characterization.

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Electrical characteristics

(1)

Table 104. LPSDR SDRAM read timings

Symbol

Parameter

Min

Max

Unit

t_W(SDCLK)

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

2T_HCLK− 0.5

2T_HCLK+0.5

t_{su(SDCLKH_Data)}

t_{h(SDCLKH_Data)}

t_{d(SDCLKL_Add)}

2.5

0

-

1

-

t_{d(SDCLKL_SDNE)}

t_{h(SDCLKL_SDNE)}

t_{d(SDCLKL_SDNRAS}

t_{h(SDCLKL_SDNRAS)}

t_{d(SDCLKL_SDNCAS)}

t_{h(SDCLKL_SDNCAS)}

-

ns

1

-

1

-

1

-

1

-

1

1. Guaranteed based on test during characterization.

Figure 70. SDRAM write access waveforms

&-#?3$#,+

TDꢋ3$#,+,?!DD#ꢌ

THꢋ3$#,+,?!DD2ꢌ

TDꢋ3$#,+,?!DD2ꢌ

2OW N

#OLꢀ

#OLꢃ

#OLI

#OLN

&-#?!>ꢅꢂꢎꢇ@

THꢋ3$#,+,?!DD#ꢌ

THꢋ3$#,+,?3.$%ꢌ

TDꢋ3$#,+,?3.$%ꢌ

&-#?3$.%;ꢀꢒꢂ=

TDꢋ3$#,+,?.2!3ꢌ

THꢋ3$#,+,?.2!3ꢌ

&-#?3$.2!3

&-#?3$.#!3

&-#?3$.7%

THꢋ3$#,+,?.#!3ꢌ

THꢋ3$#,+,?.7%ꢌ

TDꢋ3$#,+,?.#!3ꢌ

TDꢋ3$#,+,?.7%ꢌ

TDꢋ3$#,+,?$ATAꢌ

$ATAꢀ

$ATAꢃ

$ATAI

$ATAN

&-#?$;ꢊꢀꢒꢂ=

TDꢋ3$#,+,?.",ꢌ

&-#?.",;ꢊꢒꢂ=

THꢋ3$#,+,?$ATAꢌ

-3ꢊꢃꢈꢅꢃ6ꢃ

DocID028010 Rev 2

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187

Electrical characteristics

Symbol

STM32F479xx

(1)

Table 105. SDRAM write timings

Parameter

Min

Max

Unit

t_w(SDCLK)

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

NBL valid time

2T_HCLK− 0.5

2T_HCLK+0.5

t_{d(SDCLKL _Data}

)

-

3.5

-

2.5

-

t_{h(SDCLKL _Data)}

t_{d(SDCLKL_Add)}

1.5

1

t_{d(SDCLKL_SDNWE)}

t_{h(SDCLKL_SDNWE)}

t_{d(SDCLKL_ SDNE)}

t_{h(SDCLKL-_SDNE)}

t_{d(SDCLKL_SDNRAS)}

t_{h(SDCLKL_SDNRAS)}

t_{d(SDCLKL_SDNCAS)}

t_{d(SDCLKL_NBL)}

-

0

-

0.5

-

ns

0

-

2

0

-

0.5

-

0

-

0.5

-

t_{h(SDCLKL_NBL)}

NBL output time

0

1. Guaranteed based on test during characterization.

(1)

Table 106. LPSDR SDRAM write timings

Symbol

Parameter

Min

Max

Unit

t_w(SDCLK)

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

NBL valid time

2T_HCLK− 0.5

2T_HCLK+0.5

t_{d(SDCLKL _Data}

)

-

2

5

-

t_{h(SDCLKL _Data)}

t_{d(SDCLKL_Add)}

-

2.8

2

t_{d(SDCLKL-SDNWE)}

t_{h(SDCLKL-SDNWE)}

t_{d(SDCLKL- SDNE)}

t_{h(SDCLKL- SDNE)}

t_{d(SDCLKL-SDNRAS)}

t_{h(SDCLKL-SDNRAS)}

t_{d(SDCLKL-SDNCAS)}

t_{d(SDCLKL_NBL)}

-

1

-

1.5

-

ns

1

-

1.5

-

1.5

-

1.5

-

1.5

-

1.5

-

t_{h(SDCLKL-NBL)}

NBL output time

1.5

1. Guaranteed based on test during characterization.

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Electrical characteristics

5.3.30

Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 107 and Table 108 for Quad-SPI

are derived from tests performed under the ambient temperature, f

frequency and V

AHB

DD

supply voltage conditions summarized in Table xx, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output alternate function

characteristics.

(1)

Table 107. Quad-SPI characteristics in SDR mode

Symbol

Parameter

Test conditions

Min

Typ

Max

90

Unit

2.7 V ≤ V_DD≤ 3.6 V, C_L= 20 pF

1.71 V ≤ V_DD≤ 3.6 V, C_L= 15 pF

-

F_ck

1/t_(CK)

Quad-SPI clock frequency

MHz

84

t_w(CKH)

t_w(CKL)

t_s(IN)

Quad-SPI clock high time

Quad-SPI clock low time

Data input set-up time

Data input hold time

t_(CK)/2-1

-

t_(CK)/2

‐

t_(CK)/2

t_(CK)/2+1

0.5

3

-

ns

t_h(IN)

-

t_v(OUT)

t_h(OUT)

Data output valid time

Data output hold time

-

3

-

4

-

2.5

1. Guaranteed based on test during characterization.

Figure 71. Quad-SPI SDR timing diagram

W_Uꢐ&.ꢑ

W_ꢐ&.ꢑ

W_Zꢐ&.+ꢑ

W_Zꢐ&./ꢑ

W_Iꢐ&.ꢑ

&ORFN

W_Yꢐ287ꢑ

W_Kꢐ287ꢑ

'DWDꢍRXWSXW

'ꢇ

'ꢅ

'ꢂ

W_Vꢐ,1ꢑ

W_Kꢐ,1ꢑ

'DWDꢍLQSXW

'ꢇ

'ꢅ

'ꢂ

06Yꢀꢉꢁꢈꢁ9ꢅ

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187

Electrical characteristics

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(1)

Table 108. Quad-SPI characteristics in DDR mode

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

2.7 V ≤ V_DD≤ 3.6 V,

-

80

C_L= 20 pF

F_ck

1/t_(CK)

Quad-SPI clock frequency

MHz

1.71 V ≤ V_DD≤ 3.6 V,

-

70

C_L= 15 pF

t_w(CKH)Quad-SPI clock high time

t_(CK)/2-1

t_(CK)/2

‐

t_w(CKL)

Quad-SPI clock low time

Data input set-up time

-

t_(CK)/2

-

t_(CK)/2+1

2.7 V ≤ V_DD≤ 3.6 V

1.71 V ≤ V_DD≤ 3.6 V

2.7 V ≤ V_DD≤ 3.6 V

1.71 V ≤ V_DD≤ 3.6 V

DHHC=0

2

0.5

3

-

t_sr(IN)

t_sf(IN)

-

t_hr(IN)

t_hf(IN)

Data input hold time

Data output valid time

4.5

-

ns

8

10.5

t_vr(OUT)

t_vf(OUT)

DHHC=1

-

T_hclk/2+2 T_hclk/2+2.5

Pres=1,2…

DHHC=0

7

-

t_h(OUT)

t_f(OUT)

Data output hold time

DHHC=1

T_hclk/2+0.5

Pres=1,2…

1. Guaranteed based on test during characterization.

Figure 72. Quad-SPI DDR timing diagram

W_Uꢐ&.ꢑ

W_ꢐ&.ꢑ

W_Zꢐ&.+ꢑ

W_Zꢐ&./ꢑ

W_Iꢐ&.ꢑ

&ORFN

W_YIꢐ287ꢑW_KUꢐ287ꢑ

'ꢇ

W_YUꢐ287ꢑ

W_KIꢐ287ꢑ

'ꢀ

'DWDꢍRXWSXW

'ꢅ

'ꢂ

'ꢄ

'ꢆ

W_VIꢐ,1ꢑW_KIꢐ,1ꢑ

W_VUꢐ,1ꢑW_KUꢐ,1ꢑ

'DWDꢍLQSXW

'ꢇ

'ꢅ

'ꢂ

'ꢀ

'ꢄ

'ꢆ

06Yꢀꢉꢁꢈꢃ9ꢅ

5.3.31

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 109 for DCMI are derived

from tests performed under the ambient temperature, f_HCLKfrequency and V_DDsupply

voltage summarized in Table 17, with the following configuration:

•

DCMI_PIXCLK polarity: falling

DCMI_VSYNC and DCMI_HSYNC polarity: high

Data formats: 14 bits

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

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Electrical characteristics

(1)

Table 109. DCMI characteristics

Parameter

Symbol

Min

Max

Unit

-

Frequency ratio DCMI_PIXCLK/f

-

0.4

54

70

-

HCLK

DCMI_PIXCLK Pixel clock input

MHz

%

D_Pixel

t_su(DATA)

t_h(DATA)

Pixel clock input duty cycle

30

4

Data input setup time

Data input hold time

1

-

t_su(HSYNC)

t_su(VSYNC)

t_h(HSYNC)

t_h(VSYNC)

ns

DCMI_HSYNC/DCMI_VSYNC input setup time

DCMI_HSYNC/DCMI_VSYNC input hold time

3.5

0

-

1. 1.Guaranteed based on test during characterization.

Figure 73. DCMI timing diagram

ꢅꢊ'&0,B3,;&/.

'&0,B3,;&/.

'&0,B+6<1&

'&0,B96<1&

'$7$>ꢇꢎꢅꢀ@

W_Kꢐ+6<1&ꢑ

W_{VXꢐ+6<1&ꢑ}

W_Kꢐ+6<1&ꢑ

W_{VXꢐ96<1&ꢑ}

W_VXꢐ'$7$ꢑW_Kꢐ'$7$ꢑ

06ꢀꢂꢄꢅꢄ9ꢂ

5.3.32

LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 110 for LCD-TFT are derived

from tests performed under the ambient temperature, fHCLK frequency and VDD supply

voltage summarized in Table 17, with the following configuration:

•

LCD_CLK polarity: high

LCD_DE polarity: low

LCD_VSYNC and LCD_HSYNC polarity: high

Pixel formats: 24 bits

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C = 30 pF

L

Measurement points are done at CMOS levels: 0.5 V

DD

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Electrical characteristics

Symbol

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Unit

(1)

Table 110. LTDC characteristics

Parameter

Min

Max

f_CLK

LTDC clock output frequency

LTDC clock output duty cycle

-

65

55

MHz

%

D_CLK

45

t_w(CLKH)

t_w(CLKL)

Clock High time, low time

t_w(CLK)/2 − 0.5 t_w(CLK)/2+0.5

t_v(DATA)

t_h(DATA)

t_v(HSYNC)

t_v(VSYNC)

t_v(DE)

Data output valid time

Data output hold time

-

1.5

-

0

ns

HSYNC/VSYNC/DE output valid time

HSYNC/VSYNC/DE output hold time

-

0.5

-

t_h(HSYNC)

t_h(VSYNC)

0

th(DE)

1. Based on test during characterization.

Figure 74. LCD-TFT horizontal timing diagram

W&/.

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06ꢀꢂꢈꢄꢃ9ꢅ

184/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

Figure 75. LCD-TFT vertical timing diagram

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- LINES DATA

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5.3.33

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 111 for the SDIO/MMC interface

are derived from tests performed under the ambient temperature, f

frequency and V

PCLK2

DD

supply voltage conditions summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C = 30 pF

Measurement points are done at CMOS levels: 0.5 V

DD

Refer to Section 5.3.20 for more details on the input/output characteristics.

Figure 76. SDIO high-speed mode

T

R

F

T

#

T

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7ꢋ#+,ꢌ

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T

/6

/(

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T

)(

)35

$ꢑ #-$

ꢋINPUTꢌ

AIꢀꢆꢉꢉꢈ

DocID028010 Rev 2

185/208

187

Electrical characteristics

STM32F479xx

Figure 77. SD default mode

#+

T

/6$

/($

$ꢑ #-$

ꢋOUTPUTꢌ

AIꢀꢆꢉꢉꢉ

(1)

Table 111. Dynamic characteristics: SD / MMC characteristics, V = 2.7 to 3.6 V

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_PP

-

t_W(CKL)

t_W(CKH)

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio

Clock low time

-

0

-

50

8/3

-

MHz

-

9.5

8.5

10.5

9.5

f_pp=50 MHz

ns

Clock high time

-

CMD, D inputs (referenced to CK) in MMC and SD HS mode

t_ISU

t_IH

Input setup time HS

Input hold time HS

2.0

-

f_pp=50 MHz

CMD, D outputs (referenced to CK) in MMC and SD HS mode

t_OV

t_OH

Output valid time HS

Output hold time HS

-

13

-

13.5

-

f_pp=50 MHz

12.5

CMD, D inputs (referenced to CK) in SD default mode

Input setup time SD

Input hold time SD

2.0

2.5

-

t_ISUD

t_IHD

f_pp=25 MHz

ns

CMD, D outputs (referenced to CK) in SD default mode

Output valid default time SD

Output hold default time SD

-

1.5

-

2.0

-

t_OVD

t_OHD

f_pp=25 MHz

1.0

1. Guaranteed based on test during characterization.

186/208

DocID028010 Rev 2

STM32F479xx

Electrical characteristics

(1)(2)

Table 112. Dynamic characteristics: SD / MMC characteristics, V = 1.71 to 1.9 V

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_PP

-

t_W(CKL)

t_W(CKH)

Clock frequency in data transfer mode

SDIO_CK/fPCLK2 frequency ratio

Clock low time

-

0

-

50

8/3

-

MHz

-

9.5

8.5

10.5

9.5

f_pp=50 MHz

ns

Clock high time

-

CMD, D inputs (referenced to CK) in eMMC mode

t_ISU

t_IH

Input setup time HS

Input hold time HS

0.5

3.5

-

CMD, D outputs (referenced to CK) in eMMC mode

t_OV

t_OH

Output valid time HS

Output hold time HS

-

13.5

-

14.5

-

13.0

1. Guaranteed based on test during characterization.

2. C_load= 20 pF.

5.3.34

RTC characteristics

Table 113. RTC characteristics

Conditions

Symbol

Parameter

Min

Max

-

f_PCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register

4

-

DocID028010 Rev 2

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187

Package information

STM32F479xx

6

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

6.1

WLCSP168 package information

Figure 78. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip

scale package outline

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6LGHꢍYLHZ

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$ꢀ

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HHH

=

(

E

= ; <

6HDWLQJꢍ

SODQH

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$ꢇꢂ6B0(B9ꢂ

188/208

DocID028010 Rev 2

STM32F479xx

Package information

Table 114. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale

package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A3⁽²⁾

b⁽³⁾

D

0.525

0.555

0.170

0.380

0.025

0.250

4.891

5.692

0.400

4.400

5.200

0.2455

0.246

-

0.585

0.0207

0.0219

0.0067

0.0150

0.0010

0.0098

0.1926

0.2241

0.0157

0.1732

0.2047

0.0097

-

0.0230

-

0.220

0.280

4.926

5.727

-

0.0087

0.0110

0.1939

0.2255

-

4.856

0.1912

E

5.657

0.2227

e

-

e1

-

e2

-

F

-

G

-

aaa

bbb

ccc

ddd

eee

0.100

0.050

0.0039

0.0020

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

DocID028010 Rev 2

189/208

206

Package information

STM32F479xx

6.2

UFBGA169 package information

Figure 79. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package outline

=

6HDWLQJꢍSODQH

$ꢄ

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=

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0

$ꢇ<9B0(B9ꢂ

1. Drawing is not in scale.

Table 115. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array

package mechanical data

millimeters

Typ.

inches⁽¹⁾

Typ.

Symbol

Min.

Max.

Min.

Max.

A

A1

A2

A3

A4

b

0.460

0.050

0.400

-

0.530

0.080

0.450

0.130

0.320

0.280

7.000

6.000

7.000

6.000

0.500

0.600

0.110

0.500

-

0.0181

0.0020

0.0157

-

0.0209

0.0031

0.0177

0.0051

0.0126

0.0110

0.2756

0.2362

0.2756

0.2362

0.0197

0.0236

0.0043

0.0197

-

0.270

0.230

6.950

5.950

6.950

5.950

-

0.370

0.330

7.050

6.050

7.050

6.050

-

0.0106

0.0091

0.2736

0.2343

0.2736

0.2343

-

0.0146

0.0130

0.2776

0.2382

0.2776

0.2382

-

D

D1

E

E1

e

190/208

DocID028010 Rev 2

STM32F479xx

Package information

Table 115. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array

package mechanical data (continued)

millimeters

Typ.

inches⁽¹⁾

Typ.

Symbol

Min.

Max.

Min.

Max.

F

0.450

0.500

0.550

0.100

0.150

0.050

0.0177

0.0197

0.0217

0.0039

0.0059

0.0020

ddd

eee

fff

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Device Marking for UFBGA169

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

Figure 80. UFBGA169 marking example (package top view)

3LQꢍꢅ

LGHQWLILHU

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1. Samples marked "ES" are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

customer for electrical compatibility evaluation and may be used to start customer qualification where

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.

Only if ST has authorized in writing the customer qualification Engineering Samples can be used for

reliability qualification trials.

DocID028010 Rev 2

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206

Package information

STM32F479xx

6.3

LQFP176 package information

Figure 81. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline

3EATING PLANE

#

ꢂꢓꢃꢅ MM

GAUGE PLANE

K

!ꢀ

,

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,ꢀ

0). ꢀ

$

)$%.4)&)#!4)/.

:%

%

(%

E

:$

B

ꢀ4?-%?6ꢃ

1. Drawing is not to scale.

Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package

mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

0.150

1.450

0.270

0.200

24.100

-

0.0630

0.0059

0.0060

0.0106

0.0079

0.9488

0.050

1.350

0.170

0.090

23.900

0.0020

0.0531

0.0067

0.0035

0.9409

C

D

E

192/208

DocID028010 Rev 2

STM32F479xx

Package information

Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package

mechanical data (continued)

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

e

HD

HE

L

-

0.500

-

0.0197

-

25.900

-

26.100

1.0200

-

1.0276

25.900

-

26.100

1.0200

-

1.0276

0.450

-

0.750

0.0177

-

0.0295

L1

ZD

ZE

ccc

k

-

1.000

1.250

-

0.0394

0.0492

-

0.080

7 °

-

0.0031

7 °

0 °

-

0 °

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID028010 Rev 2

193/208

206

Package information

STM32F479xx

Figure 82. LQFP176 recommended footprint

ꢀꢓꢃ

ꢀꢈꢇ

ꢀꢊꢊ

ꢀꢊꢃ

ꢂꢓꢅ

ꢀ

ꢂꢓꢊ

ꢆꢆ

ꢆꢅ

ꢉꢁ

ꢉꢉ

ꢀꢓꢃ

ꢃꢀꢓꢉ

ꢃꢇꢓꢈ

ꢀ4?&0?6ꢀ

1. Dimensions are expressed in millimeters.

194/208

DocID028010 Rev 2

STM32F479xx

Package information

Device Marking for LQFP176

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 83. LQFP176 marking example (package top view)

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06Yꢀꢉꢆꢄꢄ9ꢅ

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

customer for electrical compatibility evaluation and may be used to start customer qualification where

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.

Only if ST has authorized in writing the customer qualification Engineering Samples can be used for

reliability qualification trials.

DocID028010 Rev 2

195/208

206

Package information

STM32F479xx

6.4

UFBGA176+25 package information

Figure 84. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,

ultra fine pitch ball grid array package outline

&

^ĞĂƚŝŶŐꢅƉůĂŶĞ

ꢀϮ ꢀϰ

ĚĚĚ

ꢁ

ꢀ

ꢀϭ

ď

$ꢅꢍEDOOꢍ

LQGH[ꢍ

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$

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LGHQWLILHU

ꢃ

Ğ

&

ꢀ

&

ꢂ

Ğ

ꢄ

Z

ϭϱ

ϭ

EꢍꢐꢅꢈꢉꢍꢌꢍꢂꢆꢍꢍEDOOVꢑ

ꢄKddKDꢅs/ꢃt

dKWꢅs/ꢃt

HHH 0

III

&

$ ꢄ

0

ꢀϬꢃϳͺDꢃͺsϲ

1. Drawing is not to scale.

Table 117. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,

ultra fine pitch ball grid array package mechanical data

millimeters

Typ.

inches⁽¹⁾

Symbol

Min.

Max.

Min.

Typ.

Max.

A

A1

A2

A4

b

0.460

0.050

0.400

0.270

0.230

9.950

-

0.530

0.080

0.450

0.320

0.280

10.000

0.650

0.450

-

0.600

0.110

0.500

0.370

0.330

10.050

-

0.0181

0.0020

0.0157

0.0106

0.0091

0.3917

-

0.0209

0.0031

0.0177

0.0126

0.0110

0.3937

0.0256

0.0177

-

0.0236

0.0043

0.0197

0.0146

0.0130

0.3957

-

D

E

e

F

0.400

-

0.500

0.080

0.150

0.080

0.0157

-

0.0197

0.0031

0.0059

0.0031

ddd

eee

fff

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

196/208

DocID028010 Rev 2

STM32F479xx

Package information

Figure 85. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball

grid array package recommended footprint

'SDG

'VP

ꢀϬꢃϳͺ&Wͺsϭ

Table 118. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)

Dimension

Recommended values

Pitch

0.65 mm

Dpad

Dsm

0.300 mm

0.400 mm typ. (depends on the soldermask

registration tolerance)

Stencil opening

Stencil thickness

Pad trace width

0.300 mm

Between 0.100 mm and 0.125 mm

0.100 mm

DocID028010 Rev 2

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206

Package information

STM32F479xx

6.5

LQFP208 package information

Figure 86. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline

6($7,1*

3/$1(

&

FFF

&

ꢇꢏꢂꢆꢍPP

*$8*(ꢍ3/$1(

.

/

'

/ꢅ

'ꢅ

'ꢀ

ꢅꢇꢆ

ꢅꢆꢉ

ꢅꢇꢄ

ꢅꢆꢈ

ꢂꢇꢁ

ꢆꢀ

3,1ꢍꢅ

,'(17,),&$7,21

ꢅ

ꢆꢂ

H

6)@.&@7ꢁ

1. Drawing is not to scale.

Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package

mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

1.600

0.150

1.450

0.270

--

-

0.0630

0.0059

0.0571

0.0106

0.050

1.350

0.170

0.0020

0.0531

0.0067

-

1.400

0.220

0.0551

0.0087

198/208

DocID028010 Rev 2

STM32F479xx

Package information

Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package

mechanical data (continued)

millimeters

inches⁽¹⁾

Typ

Symbol

Min

Typ

Max

Min

Max

c

D

0.090

-

0.200

30.200

28.200

-

0.0035

-

0.0079

1.1890

1.1102

-

29.800

30.000

28.000

25.500

30.000

28.000

25.500

0.500

0.600

1.000

3.5°

1.1732

1.1811

1.1024

1.0039

1.1811

1.1024

1.0039

0.0197

0.0236

0.0394

3.5°

D1

D3

E

27.800

1.0945

-

29.800

30.200

28.200

-

1.1732

1.1890

1.1102

-

E1

E3

e

27.800

1.0945

-

L

0.450

0.750

-

0.0177

0.0295

-

L1

k

-

0°

-

0°

-

7.0°

0.080

7.0°

ccc

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID028010 Rev 2

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206

Package information

STM32F479xx

Figure 87. LQFP208 recommended footprint

ꢃꢂꢉ

ꢀꢅꢈ

ꢀꢓꢃꢅ

ꢀ

ꢂꢓꢅ

ꢀꢅꢇ

ꢂꢓꢊ

ꢅꢃ

ꢀꢂꢅ

ꢀꢓꢃ

ꢅꢊ

ꢀꢂꢆ

ꢃꢅꢓꢉ

ꢊꢂꢓꢈ

-3ꢊꢂꢆꢃꢅ6ꢀ

1. Dimensions are expressed in millimeters.

200/208

DocID028010 Rev 2

STM32F479xx

Package information

Device Marking for LQFP208

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Figure 88. LQFP208 marking example (package top view)

5HYLVLRQꢍFRGH

3URGXFWꢍLGHQWLILFDWLRQ^ꢐꢅꢑ

ꢀ

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1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

customer for electrical compatibility evaluation and may be used to start customer qualification where

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.

Only if ST has authorized in writing the customer qualification Engineering Samples can be used for

reliability qualification trials.

DocID028010 Rev 2

201/208

206

Package information

STM32F479xx

6.6

TFBGA216 package information

Figure 89. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline

=

6HDWLQJꢍSODQH

GGG =

$ꢂ

$ꢅ

$

(ꢅ

;

$ꢅꢍEDOOꢍ

(

LGHQWLILHU LQGH[ꢍDUHD

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)

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)

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H

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5

ꢅꢆ

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EꢍꢐꢂꢅꢉꢍEDOOVꢑ

HHH 0 = < ;

III 0 =

%27720ꢍ9,(:

723ꢍ9,(:

$ꢇ/ꢂB0(B9ꢂ

1. Drawing is not to scale.

Table 120. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm

package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A4

b

-

1.100

-

0.0433

0.150

-

0.0059

-

0.760

0.210

0.400

13.000

11.200

13.000

11.200

0.800

0.900

-

0.0299

0.0083

0.0157

0.5118

0.4409

0.5118

0.4409

0.0315

0.0354

-

0.350

0.450

0.0138

0.0177

D

12.850

13.150

0.5118

0.5177

D1

E

-

12.850

13.150

0.5118

0.5177

E1

e

-

F

-

ddd

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package information

Device Marking for TFBGA216

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

Figure 90. TFBGA216 marking example (package top view)

3URGXFWꢍLGHQWLILFDWLRQ^ꢐꢅꢑ

ꢃ^ϯϮ&

5HYLVLRQꢍFRGH

ϰϳϵE/,ϲh

ꢀ

'DWHꢍFRGH

%DOOꢍꢅ

LGHQWLILHU

z tt

06Yꢀꢉꢆꢄꢉ9ꢅ

1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to

customer for electrical compatibility evaluation and may be used to start customer qualification where

specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.

Only if ST has authorized in writing the customer qualification Engineering Samples can be used for

reliability qualification trials.

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206

Package information

STM32F479xx

6.7

Thermal characteristics

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

•

T max is the maximum ambient temperature in ° C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ((V – V ) × I ),

OL OL DD OH OH

I/O

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 121. Package thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

WLCSP168

31

38

19

52

39

29

Thermal resistance junction-ambient

LQFP176 - 24 × 24 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP208 - 28 × 28 mm / 0.5 mm pitch

Θ

°C/W

JA

Thermal resistance junction-ambient

UFBGA169 - 7 × 7mm / 0.5 mm pitch

Thermal resistance junction-ambient

UFBGA176 - 10 × 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

TFBGA216 - 13 × 13 mm / 0.8 mm pitch

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

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Part numbering

7

Part numbering

Table 122. Ordering information scheme

Example:

STM32 F

479 V

I

T

6

xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

479= STM32F479xx, USB OTG FS/HS, camera interface,

Ethernet, LCD-TFT, DSIHost, cryptographic acceleration,

Quad-SPI,

Chrom-ART graphical accelerator.

Pin count

A = 168 and 169 pins

I = 176 pins

B = 208 pins

N = 216 pins

Flash memory size

G = 1024 Kbytes of Flash memory

I = 2048 Kbytes of Flash memory

Package

T = LQFP

H = BGA

Y = WLCSP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

7 = Industrial temperature range, –40 to 105 °C.

Options

xxx = programmed parts

TR = tape and reel

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

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206

Recommendations when using internal reset OFF

STM32F479xx

Appendix A

Recommendations when using internal reset

OFF

When the internal reset is OFF, the following integrated features are no longer supported:

•

The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.

The brownout reset (BOR) circuitry must be disabled.

The embedded programmable voltage detector (PVD) is disabled.

V

functionality is no more available and VBAT pin should be connected to V

.

BAT

DD

The over-drive mode is not supported.

A.1

Operating conditions

Table 123. Limitations depending on the operating power supply range

Maximum

Flash

Operating

power

supply

range

memory

access

frequency

Maximum Flash

memory access

frequency with

PossibleFlash

memory

operations

ADC

operation

I/O operation

with no wait wait states ⁽¹⁾⁽²⁾

states

(f_Flashmax

)

Conversion

time up to

1.2 Msps

168 MHz with 8

wait states and

over-drive OFF

8-bit erase and

program

operations only

V_DD=1.7 to

2.1 V⁽³⁾

– No I/O

compensation

20 MHz⁽⁴⁾

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no

wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does

not impact the execution speed from Flash memory since the ART accelerator allows to achieve a

performance equivalent to 0 wait state program execution.

3. V_DD/V_DDAminimum value of 1.7 V, with the use of an external power supply supervisor (refer to

Section 2.19.1: Internal reset ON).

4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and

power.

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Revision history

8

Revision history

Table 124. Document revision history

Changes

Date

Revision

01-Sep-2015

1

Initial release.

Updated Table 4: Regulator ON/OFF and internal reset ON/OFF

availability and Table 54: EMI characteristics.

Updated Figure 15: STM32F47x UFBGA176 ballout, Figure 33: PLL

output clock waveforms in center spread mode and Figure 34: PLL

output clock waveforms in down spread mode.

19-Oct-2015

2

Updated title of Section 6.6: TFBGA216 package information.

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207

STM32F479xx

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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型号：	STM32479VI
厂家：	ST
描述：	ARMCortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/3844KB RAM, USB OTG HS/FS, Ethernet, FMC, dual Quad-SPI, Crypto, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI CD
文件：	总208页 (文件大小：3020K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM32479VI [STMICROELECTRONICS]

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