STM32F101RBH6 [STMICROELECTRONICS]
Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces; 基于ARM的中等密度接入线路的32位MCU,具有64或128 KB的闪存,6个定时器, ADC和7个通信接口型号: | STM32F101RBH6 |
厂家: | ST |
描述: | Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces |
文件: | 总90页 (文件大小:1447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM32F101x8
STM32F101xB
Medium-density access line, ARM-based 32-bit MCU with 64 or
128 KB Flash, 6 timers, ADC and 7 communication interfaces
Datasheet - production data
Features
Core: ARM 32-bit Cortex™-M3 CPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
LQFP100
14 x 14 mm
LQFP64
10 x 10 mm
– Single-cycle multiplication and hardware
division
LQFP48
7 x 7 mm
UFQFPN48
7 × 7 mm
VFQFPN36
6 × 6 mm
Memories
– 64 to 128 Kbytes of Flash memory
– 10 to 16 Kbytes of SRAM
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
Six timers
– POR, PDR and programmable voltage
detector (PVD)
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
– PLL for CPU clock
Up to 7 communication interfaces
– 32 kHz oscillator for RTC with calibration
2
– Up to 2 x I C interfaces (SMBus/PMBus)
Low power
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
– Up to 2 SPIs (18 Mbit/s)
Debug mode
CRC calculation unit, 96-bit unique ID
– Serial wire debug (SWD) and JTAG
interfaces
®
ECOPACK packages
DMA
Table 1. Device summary
– 7-channel DMA controller
Reference
Part number
– Peripherals supported: timers, ADC, SPIs,
STM32F101C8,
2
I Cs and USARTs
STM32F101R8
STM32F101V8,
STM32F101T8
STM32F101x8
1 × 12-bit, 1 µs A/D converter (up to 16
channels)
STM32F101RB,
STM32F101VB,
STM32F101CB
STM32F101TB
– Conversion range: 0 to 3.6 V
– Temperature sensor
STM32F101xB
Up to 80 fast I/O ports
August 2013
DocID13586 Rev 16
1/90
This is information on a product in full production.
www.st.com
Contents
STM32F101x8, STM32F101xB
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
®
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
ARM Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
²
2.3.19 I C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
4
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 34
Embedded reset and power control block characteristics . . . . . . . . . . . 34
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1
6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.1
6.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Evaluating the maximum junction temperature for an application . . . . . 81
DocID13586 Rev 16
3/90
4
Contents
STM32F101x8, STM32F101xB
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7
8
4/90
DocID13586 Rev 16
STM32F101x8, STM32F101xB
List of tables
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features and peripheral counts (STM32F101xx
medium-density access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Medium-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Maximum current consumption in Run mode, code with data processing
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum current consumption in Sleep mode, code running from Flash
Table 13.
Table 14.
or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39
Typical current consumption in Run mode, code with data processing
Table 15.
Table 16.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 43
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SCL frequency (f
= 36 MHz, V
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PCLK1
DD_I2C
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
R
max for f
= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
AIN
ADC
DocID13586 Rev 16
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List of tables
STM32F101x8, STM32F101xB
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 74
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 76
LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data. . . . . . . . 77
LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 78
LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 79
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6/90
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STM32F101x8, STM32F101xB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F101xx medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 21
STM32F101xx medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F101xx medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F101xx medium-density access line UFQPFN48 pinout. . . . . . . . . . . . . . . . . . . . . 23
STM32F101xx medium-density access line VFQPFN36 pinout. . . . . . . . . . . . . . . . . . . . . 23
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 38
Figure 15. Typical current consumption on V
with RTC on versus temperature at different
BAT
V
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BAT
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DD
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DD
Figure 18. Typical current consumption in Standby mode versus temperature at V = 3.3 V and
DD
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 24. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 25. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 26. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 27. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2
(1)
Figure 29. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
(1)
Figure 31. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
(1)
Figure 33. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 35. Power supply and reference decoupling (V
Figure 36. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . . 71
). . . . . . . . . . . . . . . . . 72
REF+
DDA
connected to V
REF+
DDA
Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 38. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
(1)(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 40. VFQFPN36 recommended footprint (dimensions in mm)
Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 77
(1)
Figure 42. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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STM32F101x8, STM32F101xB
Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 78
(1)
Figure 44. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
(1)
Figure 46. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 47. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
D
A
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STM32F101x8, STM32F101xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For
more details on the whole STMicroelectronics STM32F101xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F101xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
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Description
STM32F101x8, STM32F101xB
2
Description
The STM32F101xB and STM32F101x8 medium-density access line family incorporates the
high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16
Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB
2
buses. All devices offer standard communication interfaces (two I Cs, two SPIs, and up to
three USARTs), one 12-bit ADC and three general-purpose 16-bit timers.
The STM32F101xx medium-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx medium-density access line family includes devices in four different
packages ranging from 36 pins to 100 pins. Depending on the device chosen, different sets
of peripherals are included, the description below gives an overview of the complete range
of peripherals proposed in this family.
These features make the STM32F101xx medium-density access line microcontroller family
suitable for a wide range of applications such as application control and user interface,
medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and
HVACs.
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STM32F101x8, STM32F101xB
Description
2.1
Device overview
Figure 1 shows the general block diagram of the device family.
Table 2. Device features and peripheral counts (STM32F101xx
medium-density access line)
STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx
Peripheral
Flash - Kbytes
SRAM - Kbytes
64
10
128
16
64
10
128
16
64
10
128
16
64
10
128
16
General -purpose
3
3
3
3
SPI
1
1
2
2
2
2
2
2
I2C
USART
2
1
3
1
3
1
3
1
12-bit synchronized ADC
number of channels
10 channels
10 channels
16 channels
16 channels
GPIOs
26
37
51
80
CPU frequency
Operating voltage
36 MHz
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 8)
Junction temperature: –40 to +105 °C (see Table 8)
Operating temperatures
Packages
LQFP48,
VFQFPN36
LQFP64
LQFP100
UFQFPN48
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Description
STM32F101x8, STM32F101xB
Figure 1. STM32F101xx medium-density access line block diagram
TRACECLK
TRACED[0:3]
as AS
TPIU
Trace
Cont rol ler
Trace/trig
pbus
POWER
SW/JTAG
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
V
= 2 to 3.6V
DD
VSS
VOLT. REG.
3.3V TO 1.8V
Ibus
Cortex M3 CPU
Fmax 36 MHz
Flash 128 KB
64 bit
JTDO
as AF
@VDD
:
Dbus
NVIC
SRAM
16 KB
NVIC
System
@VDD
OSC_IN
OSC_OUT
PCLK1
PCLK2
HCLK
FCLK
PLL &
XTAL OSC
4-16 MHz
GP DMA
CLOCK
MANAGT
7 channels
RC 8 MHz
RC 42 kHz
@VDDA
IWDG
@VDDA
Stand by
interface
SUPPLY
SUPERVISION
VBAT
NRST
VDDA
VSSA
@VBAT
Rst
Int
POR / PDR
OSC32_IN
OSC32_OUT
XTAL 32 kHz
Backup
PVD
RTC
AWU
AHB2
APB2
AHB2
APB1
TAMPER-RTC
reg
Backu p interface
EXTI
80AF
WAKEUP
4 Channels
4 Channels
TIM2
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
TIM3
4 Channels
TIM4
RX,TX, CTS, RTS,
CK, SmartCard as AF
USART2
USART3
RX,TX, CTS, RTS,
CK, SmartCard as AF
MOSI,MISO,SCK,NSS
as AF
SPI2
I2C1
I2C2
SCL,SDA,SMBAL
as AF
MOSI,MISO,
SCK,NSS as AF
SPI1
SCL,SDA
as AF
RX,TX, CTS, RTS,
Smart Card as AF
USART1
@VDDA
16AF
VREF+
12bit ADC1
IF
W W D G
VREF-
Temp sensor
ai14385B
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
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STM32F101x8, STM32F101xB
Description
Figure 2. Clock tree
FLITFCLK
to Flash programming interface
8 MHz
HSI RC
HSI
/2
HCLK
36 MHz max
to AHB bus, core,
memory and DMA
Clock
Enable (3 bits)
/8
to Cortex System timer
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
Prescaler
/1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
to APB1
peripherals
PLLCLK
HSE
36 MHz
max
Peripheral Clock
Enable (13 bits)
to TIM2, 3
and 4
TIMXCLK
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
CSS
Peripheral Clock
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
36 MHz max
PCLK2
to APB2
OSC_OUT
OSC_IN
peripherals
4-16 MHz
HSE OSC
Peripheral Clock
Enable (11 bits)
ADC
to ADC
Prescaler
/2, 4, 6, 8
ADCCLK
/128
LSE
OSC32_IN
to RTC
LSE OSC
RTCCLK
32.768 kHz
OSC32_OUT
RTCSEL[1:0]
to Independent Watchdog (IWDG)
IWDGCLK
LSI
LSI RC
40 kHz
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
Main
Clock Output
/2
PLLCLK
MCO
HSI
HSE
SYSCLK
MCO
ai15104
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
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STM32F101x8, STM32F101xB
2.2
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F101x8/B devices, they are
specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low-
density devices feature lower Flash memory and RAM capacities and a timer less. High-
density devices have higher Flash memory and RAM capacities, and additional peripherals
like FSMC and DAC, while remaining fully compatible with the other members of the
STM32F101xx family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the
user to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F101xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F101xx family
Memory size
Low-density devices Medium-density devices
High-density devices
16 KB
Flash
32 KB
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
Pinout
Flash(1)
32 KB
RAM
48 KB
RAM
48 KB
RAM
4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM
144
100
64
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Cs, 1 × ADC,
3 × USARTs
2 × DACs, FSMC (100 and 144 pins)
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C
1 × ADC
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
1 × ADC
48
36
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.
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STM32F101x8, STM32F101xB
Description
2.3
Overview
®
2.3.1
ARM Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx medium-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.
2.3.2
2.3.3
Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.3.4
2.3.5
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F101xx medium-density access line embeds a nested vectored interrupt
controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
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2.3.6
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9
Power supply schemes
V
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
V
, V
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
SSA DDA
and PLL (minimum voltage to be applied to V
is 2.4 V when the ADC is used).
DDA
V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 11: Power supply scheme.
2.3.10
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V is below a specified threshold, V
, without the need for an
DD
POR/PDR
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
/V power supply and compares it to the V threshold. An interrupt can be
V
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
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STM32F101x8, STM32F101xB
Description
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
V
and V
.
POR/PDR
PVD
2.3.11
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12
Low-power modes
The STM32F101xx medium-density access line supports three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.3.13
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
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Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, general purpose timers
TIMx and ADC.
2.3.14
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the VBAT pin. The backup registers are ten 16-bit
DD
registers used to store 20 bytes of user application data when V power is not present.
DD
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.3.16
2.3.17
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
2.3.18
General-purpose timers (TIMx)
There are three synchronizable general-purpose timers embedded in the STM32F101xx
medium-density access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
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STM32F101x8, STM32F101xB
Description
capture, output compare, PWM or one pulse mode output. This gives up to 12 input
captures / output compares / PWMs on the largest packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs. They all have independent DMA request
generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
²
2.3.19
I C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.20
2.3.21
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
2.3.22
2.3.23
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
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89
Description
STM32F101x8, STM32F101xB
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.3.24
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
< 3.6 V. The temperature sensor is internally
DDA
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.25
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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STM32F101x8, STM32F101xB
Pinouts and pin description
3
Pinouts and pin description
Figure 3. STM32F101xx medium-density access line LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
VDD_5 11
LQFP100
OSC_IN
OSC_OUT
NRST
PC0
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0-WKUP
PA1
PD8
PB15
PB14
PB13
PB12
PA2
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Pinouts and pin description
STM32F101x8, STM32F101xB
Figure 4. STM32F101xx medium-density access line LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
PC0
PC1
PC2
PC3
8
LQFP64
9
10
11
12
13
14
15
16
PC6
VSSA
VDDA
PA0-WKUP
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai14387b
Figure 5. STM32F101xx medium-density access line LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
LQFP48
PA8
VSSA
VDDA
PB15
PB14
PB13
PB12
PA0-WKUP 10
PA1 11
12
PA2
24
13 14 15 16 17 18 19 20 21 22 23
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STM32F101x8, STM32F101xB
Pinouts and pin description
Figure 6. STM32F101xx medium-density access line UFQPFN48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
36
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
1
35
34
33
32
31
30
29
28
27
26
25
2
3
4
5
6
7
8
9
QFPN48
PA8
VSSA
PB15
PB14
PB13
PB12
VDDA
10
11
12
PA0-WKUP
PA1
PA2
13 14 15 16 17 18 19 20 21 22 23 24
MS31472V1
Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout
36 35 34
33 32 31 30 29 28
27
V
V
V
1
DD_3
DD_2
SS_2
OSC_IN/PD0
OSC_OUT/PD1
NRST
2
3
4
5
6
7
8
9
26
PA13
PA12
PA11
PA10
PA9
25
24
QFN36
V
23
22
SSA
V
DDA
PA0-WKUP
PA1
21
20
PA8
PA2
V
19
DD_1
10 11 12 13
14 15 16 17
18
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Pinouts and pin description
STM32F101x8, STM32F101xB
Alternate functions(3)(4)
Table 4. Medium-density STM32F101xx pin definitions
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
FT
FT
FT
FT
FT
-
-
-
-
1
2
3
4
5
6
-
-
-
-
-
-
PE2
PE3
PE4
PE5
PE6
VBAT
I/O
I/O
I/O
I/O
I/O
S
PE2
PE3
PE4
PE5
PE6
VBAT
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
-
-
-
-
-
-
1
1
PC13-TAMPER-
RTC(5)
2
3
4
2
3
4
7
8
9
-
-
-
I/O
I/O
I/O
PC13(6)
PC14(6)
PC15(6)
TAMPER-RTC
OSC32_IN
PC14-
OSC32_IN(5)
PC15-
OSC32_OUT
OSC32_OUT(5)
-
-
-
10
11
12
13
14
15
16
-
-
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
S
S
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
-
5
6
7
-
5
6
7
8
9
2
3
4
-
I
PD0(7)
PD1(7)
O
I/O
I/O
I/O
I/O
I/O
S
ADC_IN10
ADC_IN11
ADC_IN12
ADC_IN13
-
-
PC1
PC1
-
10 17
11 18
12 19
-
PC2
PC2
-
-
PC3
PC3
8
-
5
-
VSSA
VSSA
-
-
20
21
VREF-
VREF+
VDDA
S
VREF-
VREF+
VDDA
-
-
S
9
13 22
6
S
WKUP/USART2_CTS(8)
ADC_IN0/
/
10 14 23
7
8
PA0-WKUP
PA1
I/O
I/O
PA0
PA1
TIM2_CH1_ETR(8)
USART2_RTS(8)
ADC_IN1/TIM2_CH2(8)
/
11
15 24
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STM32F101x8, STM32F101xB
Pinouts and pin description
Alternate functions(3)(4)
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
USART2_TX(8)
/
12 16 25
9
PA2
PA3
I/O
I/O
PA2
PA3
ADC_IN2/TIM2_CH3(8)
USART2_RX(8)
/
13 17 26 10
ADC_IN3/TIM2_CH4(8)
-
-
18 27
19 28
-
-
VSS_4
VDD_4
S
S
VSS_4
VDD_4
SPI1_NSS(8)/ADC_IN4
14 20 29 11
15 21 30 12
16 22 31 13
PA4
PA5
PA6
I/O
I/O
I/O
PA4
PA5
PA6
USART2_CK(8)
/
SPI1_SCK(8)/ADC_IN5
SPI1_MISO(8)/ADC_IN6
TIM3_CH1(8)
SPI1_MOSI(8)/ADC_IN7
TIM3_CH2(8)
17 23 32 14
PA7
I/O
PA7
-
-
24 33
25 34
PC4
PC5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PC4
PC5
ADC_IN14
ADC_IN15
18 26 35 15
19 27 36 16
20 28 37 17
PB0
PB0
ADC_IN8/TIM3_CH3(8)
ADC_IN9/TIM3_CH4(8)
PB1
PB1
PB2
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
PB2/BOOT1
PE7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
38
39
40
41
42
43
44
45
46
-
-
-
-
-
-
-
-
-
PE7
PE8
PE8
PE9
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE10
PE11
PE12
PE13
PE14
PE15
I2C2_SCL/
21 29 47
22 30 48
-
-
PB10
PB11
I/O
I/O
FT
FT
PB10
PB11
TIM2_CH3
TIM2_CH4
USART3_TX (8)
I2C2_SDA/
USART3_RX (8)
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Pinouts and pin description
STM32F101x8, STM32F101xB
Alternate functions(3)(4)
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
23 31 49 18
24 32 50 19
VSS_1
VDD_1
S
S
VSS_1
VDD_1
SPI2_NSS / I2C2_SMBA /
USART3_CK (8)
25 33 51
26 34 52
-
-
-
PB12
PB13
PB14
I/O
I/O
I/O
FT
FT
FT
PB12
PB13
PB14
SPI2_SCK/
USART3_CTS(8)
SPI2_MISO/
27 35 53
28 36 54
USART3_RTS(8)
-
-
-
-
-
PB15
PD8
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
PB15
PD8
SPI2_MOSI
-
-
-
-
-
-
-
-
55
56
57
58
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
PD9
PD9
PD10
PD11
PD10
PD11
TIM4_CH1 /
USART3_RTS
-
-
59
-
PD12
I/O
FT
PD12
-
-
-
-
-
-
-
60
61
62
-
-
-
-
-
-
-
PD13
PD14
PD15
PC6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
PD13
PD14
PD15
PC6
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
37 63
38 64
39 65
40 66
PC7
PC7
PC8
PC8
-
PC9
PC9
29 41 67 20
30 42 68 21
31 43 69 22
32 44 70 23
33 45 71 24
34 46 72 25
PA8
PA8
USART1_CK/MCO
USART1_TX(8)
USART1_RX(8)
USART1_CTS
USART1_RTS
PA9
PA9
PA10
PA11
PA12
PA13
PA10
PA11
PA12
FT JTMS-SWDIO
Not connected
VSS_2
PA13
-
-
73
-
35 47 74 26
VSS_2
S
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STM32F101x8, STM32F101xB
Pinouts and pin description
Alternate functions(3)(4)
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
36 48 75 27
37 49 76 28
VDD_2
PA14
S
VDD_2
I/O
FT JTCK/SWCLK
PA14
TIM2_CH1_ETR/
PA15/ SPI1_NSS
38 50 77 29
PA15
I/O
FT
JTDI
-
-
-
-
-
51 78
52 79
53 80
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
USART3_TX
USART3_RX
USART3_CK
-
-
81
82
2
3
-
54 83
TIM3_ETR
-
-
-
-
-
-
-
-
-
-
84
85
86
87
88
-
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
-
-
-
-
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
39 55 89 30
PB3
I/O
FT
FT
JTDO
PB4 / TIM3_CH1
SPI1_MISO
40 56 90 31
41 57 91 32
42 58 92 33
PB4
PB5
PB6
PB7
I/O
I/O
I/O
I/O
JNTRST
PB5
TIM3_CH2 /
SPI1_MOSI
I2C1_SMBAl
I2C1_SCL(8)
TIM4_CH1 (8)
/
FT
FT
PB6
USART1_TX
USART1_RX
I2C1_SDA(8)
/
43 59 93 34
44 60 94 35
PB7
TIM4_CH2 (8)
BOOT0
PB8
I
BOOT0
PB8
45 61 95
46 62 96
-
-
-
-
I/O
I/O
I/O
I/O
FT
FT
FT
FT
TIM4_CH3 (8)
TIM4_CH4 (8)
TIM4_ETR
I2C1_SCL
I2C1_SDA
PB9
PB9
-
-
-
-
97
98
PE0
PE0
PE1
PE1
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Pinouts and pin description
STM32F101x8, STM32F101xB
Alternate functions(3)(4)
Table 4. Medium-density STM32F101xx pin definitions (continued)
Pins
Main
Pin name
function(3)
(after reset)
Default
Remap
47 63 99 36
VSS_3
VDD_3
S
S
VSS_3
VDD_3
48 64 100
1
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48, UFQFPN48 and LQFP64 packages are
configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on
these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
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STM32F101x8, STM32F101xB
Memory mapping
4
Memory mapping
The memory map is shown in Figure 8.
Figure 8. Memory map
APB memory space
0xFFFF FFFF
0xE010 0000
reserved
reserved
reserved
CRC
0x6000 0000
0x4002 3400
0x4002 3000
0x4002 2400
0x4002 2000
0x4002 1400
0x4002 1000
0x4002 0400
0x4002 0000
4K
1K
3K
0xFFFF FFFF
reserved
1K
3K
1K
3K
1K
Flash interface
reserved
RCC
7
0xE010 0000
Cortex-M3 internal
peripherals
reserved
DMA
0xE000 0000
reserved
1K
6
0x4001 3C00
0x4001 3800
0x4001 3400
0x4001 3000
0x4001 2C00
0x4001 2800
0x4001 2400
1K
1K
USART1
reserved
SPI1
0xC000 0000
1K
1K
1K
1K
reserved
reserved
ADC1
5
0xA000 0000
reserved
2K
0x4001 1C00
0x4001 1800
0x4001 1400
0x4001 1000
0x4001 0C00
0x4001 0800
0x4001 0400
0x4001 0000
1K
1K
1K
1K
Port E
Port D
Port C
Port B
Port A
EXTI
4
0x1FFF FFFF
0x1FFF F80F
reserved
0x8000 0000
Option Bytes
0x1FFF F800
1K
System memory
1K
1K
3
AFIO
0x1FFF F000
0x6000 0000
reserved
35K
0x4000 7400
0x4000 7000
0x4000 6C00
0x4000 6800
0x4000 6400
0x4000 6000
0x4000 5C00
0x4000 5800
0x4000 5400
PWR
1K
1K
2
BKP
reserved
reserved
reserved
reserved
1K
1K
1K
1K
1K
reserved
Peripherals
0x4000 0000
1
I2C2
I2C1
1K
2K
SRAM
0x2000 0000
0x0801 FFFF
reserved
0x4000 4C00
0x4000 4800
0x4000 4400
USART3
USART2
1K
1K
Flash memory
0
0x0800 0000
0x0000 0000
reserved
SPI2
2K
0x0000 0000
Aliased to Flash or
system memory
depending on
BOOT pins
0x4000 3C00
0x4000 3800
0x4000 3400
0x4000 3000
0x4000 2C00
0x4000 2800
1K
1K
1K
1K
1K
reserved
IWDG
Reserved
WWDG
RTC
reserved
7K
0x4000 0C00
0x4000 0800
0x4000 0400
0x4000 0000
TIM4
TIM3
TIM2
1K
1K
1K
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Electrical characteristics
STM32F101x8, STM32F101xB
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
2 V V 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
30/90
DocID13586 Rev 16
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
STM32F10xxx pin
STM32F10xxx pin
C= 50 pF
V
IN
ai14124b
ai14123b
5.1.6
Power supply scheme
Figure 11. Power supply scheme
V
BAT
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Power switch
1.8-3.6V
Backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
& Memories)
V
DD
V
DD
1/2/3/4/5
Regulator
5 × 100 nF
+ 1 × 4.7 µF
V
SS
1/2/3/4/5
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
10 nF
+ 1 µF
10 nF
+ 1 µF
V
ADC
REF-
V
SSA
ai14125d
Caution:
In Figure 11, the 4.7 µF capacitor must be connected to V
.
DD3
DocID13586 Rev 16
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89
Electrical characteristics
STM32F101x8, STM32F101xB
5.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 5. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including
VDD VSS
–0.3
4.0
(1)
VDDA and VDD
)
V
Input voltage on five volt tolerant pin
Input voltage on any other pin
VSS 0.3
VSS 0.3
VDD 4.0
4.0
(2)
VIN
|VDDx
|
Variations between different VDD power pins
50
mV
Variations between all the different ground
pins
|VSSX VSS
|
50
see Section 5.3.11: Absolute
maximum ratings (electrical
sensitivity)
Electrostatic discharge voltage (human body
model)
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum
allowed injected current values.
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STM32F101x8, STM32F101xB
Symbol
Electrical characteristics
Table 6. Current characteristics
Ratings
Max.
Unit
IVDD
IVSS
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on five volt tolerant pins(3)
Injected current on any other pin(4)
150
150
25
IIO
25
-5/+0
± 5
mA
(2)
IINJ(PIN)
IINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 7. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 8. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
0
0
0
2
36
36
36
3.6
MHz
Analog operating voltage
(ADC not used)
2
3.6
Must be the same potential
as VDD
(1)
VDDA
V
(2)
Analog operating voltage
(ADC used)
2.4
1.8
3.6
3.6
VBAT
Backup operating voltage
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89
Electrical characteristics
Symbol
STM32F101x8, STM32F101xB
Table 8. General operating conditions (continued)
Parameter
Conditions
Standard IO
Min
Max
Unit
–0.3 VDD + 0.3
2 V < VDD 3.6 V –0.3
5.5
5.2
VIN
I/O input voltage
FT IO(3)
V
VDD = 2 V
–0.3
0
BOOT0
5.5
LQFP100
LQFP64
LQFP48
434
444
363
624
1000
85
Power dissipation at TA = 85 °C
PD
mW
°C
(4)
UFQFPN48
VFQFPN36
Maximum power dissipation
Low power dissipation(5)
–40
–40
–40
TA
TJ
Ambient temperature
105
105
Junction temperature range
1. When the ADC is used, refer to Table 42: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 80).
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 80).
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 9. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
0
tVDD
µs/V
VDD fall time rate
20
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
34/90
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STM32F101x8, STM32F101xB
Electrical characteristics
.
Table 10. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1
2
2.18 2.26
2.08 2.16
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
2.66 2.78 2.9
2.56 2.68 2.8
Programmable voltage
detector level selection
VPVD
V
2.76 2.88
3
2.66 2.78 2.9
100
(2)
VPVDhyst
PVD hysteresis
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
VPOR/PDR
1.84 1.92 2.0
40
(2)
VPDRhyst
PDR hysteresis
mV
ms
(2)
tRSTTEMPO
Reset temporization
1.5
2.5
4.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101x8, STM32F101xB
5.3.4
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 11. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VREFINT Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.20
5.1
1.24
V
ADC sampling time when reading
the internal reference voltage
(1)
17.1(2)
10
TS_vrefint
µs
Internal reference voltage spread
over the temperature range
(2)
VRERINT
VDD = 3 V ±10 mV
mV
ppm/
°C
(2)
TCoeff
Temperature coefficient
100
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f
PCLK1
HCLK/2 PCLK2
HCLK
The parameters given in Table 12 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
36/90
DocID13586 Rev 16
STM32F101x8, STM32F101xB
Electrical characteristics
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
28.6
19.9
14.7
8.6
External clock (2), all
peripherals enabled
24 MHz
16 MHz
8 MHz
Supply current
in Run mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
19.8
13.9
10.7
6.8
External clock (4), all
peripherals Disabled
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
24
17.5
12.5
7.5
External clock (2), all
peripherals enabled
24 MHz
16 MHz
8 MHz
Supply current in
Run mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
16
External clock(2) all
peripherals disabled
11.5
8.5
5.5
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
25
20
15
36MHz
16MHz
8MHz
10
5
0
-40
0
25
70
85
Temperature (°C)
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
16
14
12
10
36MHz
16MHz
8MHz
8
6
4
2
0
-40
0
25
70
85
Temperature (°C)
38/90
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STM32F101x8, STM32F101xB
Electrical characteristics
Table 14. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
24 MHz
16 MHz
8 MHz
15.5
11.5
8.5
5.5
5
External clock(2) all
peripherals enabled
Supply current in
Sleep mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
External clock(2), all
peripherals disabled
4.5
4
3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Max
V
DD/VBA
VDD/VBA
Symbol
Parameter
Conditions
Unit
VDD/VBAT
= 2.4 V
TA =
85 °C(2)
T
T
= 2.0 V
= 3.3 V
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)
-
23.5
13.5
24
14
200
180
Supply current
in Stop mode
Regulator in Low-Power mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)
-
IDD
Low-speed internal RC oscillator and
independent watchdog ON
µA
-
-
2.6
2.4
3.4
3.2
-
-
Supply current Low-speed internal RC oscillator ON,
in Standby
mode
independent watchdog OFF
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
-
1.7
1.1
2
4
Backup domain
I
Low-speed oscillator and RTC ON
0.9
1.4
1.9
DD_VBAT supply current
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not rested in production.
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 15. Typical current consumption on V
with RTC on versus temperature at different
BAT
V
values
BAT
2.5
2
2 V
1.5
1
2.4 V
3 V
0.5
0
3.6 V
–40 °C
25 °C
70 °C
Temperature (°C)
85 °C
105 °C
ai17351
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at V = 3.3 V and 3.6 V
DD
140
120
100
80
3.3 V
3.6 V
60
40
20
0
-45
25
70
90
Temperature (°C)
40/90
DocID13586 Rev 16
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V
DD
100
90
80
70
60
50
40
30
20
10
0
3.3 V
3.6 V
–45 °C
25 °C
85 °C
Temperature (°C)
Figure 18. Typical current consumption in Standby mode versus temperature at V = 3.3 V and
DD
3.6 V
3
2.5
2
3.3 V
1.5
3.6 V
1
0.5
0
-45
25
70
90
Temperature (°C)
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89
Electrical characteristics
STM32F101x8, STM32F101xB
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f , f
=
HCLK/2 ADCCLK
PCLK1
HCLK/4 PCLK2
f
/4
PCLK2
The parameters given in Table 16 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals
enabled(2)
All peripherals
disabled
36 MHz
24 MHz
16 MHz
8 MHz
19
14.8
10.1
7.4
12.9
9.3
5.5
4.6
External
clock(3)
4 MHz
3.3
2.8
2 MHz
2.2
1.9
1 MHz
1.6
1.45
1.25
1.06
14.1
9.5
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
1.3
Supply
1.08
18.3
12.2
8.5
IDD
current in
mA
Run mode
Running on
high speed
internal RC
(HSI), AHB
prescaler
6.8
4.9
4
4 MHz
2.7
2.2
used to
2 MHz
1.6
1.4
reduce the
frequency
1 MHz
1.02
0.73
0.5
0.9
500 kHz
125 kHz
0.67
0.48
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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STM32F101x8, STM32F101xB
Electrical characteristics
Table 17. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals All peripherals
enabled(2)
disabled
36 MHz
24 MHz
16 MHz
8 MHz
7.6
5.3
3.8
2.1
1.6
1.3
3.1
2.3
1.8
1.2
1.1
1
External clock(3)
4 MHz
2 MHz
1 MHz
1.11
1.04
0.98
7
0.98
0.96
0.95
2.5
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
Supply
IDD
current in
mA
Sleep mode
4.8
1.8
3.2
1.2
Running on High
Speed Internal RC
(HSI), AHB
prescaler used to
reduce the
1.6
0.6
4 MHz
1
0.5
2 MHz
0.72
0.56
0.49
0.43
0.47
0.44
0.42
0.41
frequency
1 MHz
500 kHz
125 kHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Electrical characteristics
STM32F101x8, STM32F101xB
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
ambient operating temperature and V supply voltage conditions summarized in
Table 5.
DD
Table 18. Peripheral current consumption
Peripheral
Typical consumption at 25 °C(1)
Unit
TIM2
0.6
TIM3
0.6
TIM4
0.6
SPI2
0.08
0.21
0.21
0.18
0.18
0.21
0.21
0.21
0.21
0.21
1.4
APB1
USART2
USART3
I2C1
I2C2
mA
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
ADC1(2)
SPI1
APB2
0.24
0.35
USART1
1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit
in the ADC_CR2 register is set to 1.
5.3.6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
44/90
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STM32F101x8, STM32F101xB
Electrical characteristics
Table 19. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
1
8
25
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
tw(HSE)
ns
tr(HSE)
tf(HSE)
20
Cin(HSE) OSC_IN input capacitance(1)
5
pF
%
DuCy(HSE) Duty cycle
45
55
±1
IL
OSC_IN Input leakage current
VSS VIN VDD
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
Table 20. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fLSE_ext
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
0.7VDD
VSS
VDD
V
OSC32_IN input pin low level
voltage
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
450
ns
tr(LSE)
tf(LSE)
50
Cin(LSE) OSC32_IN input capacitance(1)
5
pF
%
DuCy(LSE) Duty cycle
30
70
±1
IL
OSC32_IN Input leakage current VSS VIN VDD
µA
1. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 19. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
clock source
I
L
OSC _IN
STM32F10xxx
ai14127b
Figure 20. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
clock source
I
L
OSC32_IN
STM32F10xxx
ai14140c
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 21. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
46/90
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STM32F101x8, STM32F101xB
Symbol
Electrical characteristics
(1)(2)
Table 21. HSE 4-16 MHz oscillator characteristics
Parameter
Conditions
Min
Typ
Max Unit
fOSC_IN Oscillator frequency
4
8
16
MHz
RF
Feedback resistor
200
k
Recommended load capacitance
versus equivalent serial
C
RS = 30
30
pF
resistance of the crystal (RS)(3)
VDD = 3.3 V, VIN = VSS
with 30 pF load
i2
HSE driving current
1
mA
gm
Oscillator transconductance
Startup time
Startup
25
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
2
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
Figure 21. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
STM32F10xxx
OSC_OUT
(1)
R
EXT
C
L2
ai14128b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 22. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
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89
Electrical characteristics
STM32F101x8, STM32F101xB
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1) (2)
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ
Max
Unit
RF
5
M
Recommended load capacitance
versus equivalent serial
C
RS = 30 K
15
pF
resistance of the crystal (RS)
V
DD = 3.3 V
I2
LSE driving current
1.4
µA
VIN = VSS
gm
Oscillator transconductance
5
µA/V
TA = 50 °C
TA = 25 °C
TA = 10 °C
TA = 0 °C
1.5
2.5
4
6
VDD is
stabilized
(3)
tSU(LSE)
Startup time
s
TA = -10 °C
TA = -20 °C
TA = -30 °C
TA = -40 °C
10
17
32
60
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For C and C it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1 L2
15 pF range selected to match the requirements of the crystal or resonator. C and C are
L1
L2,
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C = 6 pF, and C
= 2 pF,
stray
L
then C = C = 8 pF.
L1
L2
48/90
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 22. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 KHz
resonator
R
F
STM32F10xxx
OSC32_OUT
C
L2
ai14129b
5.3.7
Internal clock source characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 23. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI
8
MHz
%
DuCy(HSI) Duty cycle
45
55
User-trimmed with the RCC_CR
register(2)
1(3)
%
TA = –40 to 105 °C
–2
2.5
2.2
2
%
%
%
%
Accuracy of the HSI
oscillator
ACCHSI
Factory-
TA = –10 to 85 °C
–1.5
–1.3
–1.1
calibrated
(4) (5)
TA = 0 to 70 °C
TA = 25 °C
1.8
HSI oscillator
startup time
(4)
tsu(HSI)
1
2
µs
HSI oscillator power
consumption
(4)
IDD(HSI)
80
100
µA
1.
VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified
range.
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Electrical characteristics
STM32F101x8, STM32F101xB
Low-speed internal (LSI) RC oscillator
(1)
Table 24. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
30
40
60
85
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
0.65
1.2
µA
1.
VDD = 3 V, TA = –40 to 85 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and V supply
DD
voltage conditions summarized in Table 8.
Table 25. Low-power mode wakeup timings
Symbol
Parameter
Wakeup from Sleep mode
Typ
Unit
(1)
1.8
µs
tWUSLEEP
Wakeup from Stop mode (regulator in run mode)
Wakeup from Stop mode (regulator in low-power mode)
Wakeup from Standby mode
3.6
5.4
50
(1)
µs
µs
tWUSTOP
(1)
tWUSTDBY
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 26 are derived from tests performed under the ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 26. PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
25
60
36
MHz
%
fPLL_IN
fPLL_OUT
PLL input clock duty cycle
PLL multiplier output clock
40
16
MHz
50/90
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STM32F101x8, STM32F101xB
Electrical characteristics
Table 26. PLL characteristics
Value
Typ
Symbol
Parameter
Min(1)
Unit
Max(1)
tLOCK
Jitter
PLL lock time
Cycle-to-cycle jitter
200
300
µs
ps
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 85 °C unless otherwise specified.
A
Table 27. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
tprog
tERASE
tME
16-bit programming time
Page (1 KB) erase time
Mass erase time
TA–40 to +85 °C
TA –40 to +85 °C
TA –40 to +85 °C
40
20
20
52.5
70
40
40
µs
ms
ms
Read mode
fHCLK = 36 MHz with 1 wait
state, VDD = 3.3 V
20
5
mA
mA
IDD
Supply current
Write / Erase modes
fHCLK = 36 MHz, VDD = 3.3 V
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
V
Vprog
Programming voltage
2
3.6
1. Guaranteed by design, not tested in production.
Table 28. Flash memory endurance and data retention
Value
Symbol
NEND Endurance
tRET Data retention
Parameter
Conditions
Unit
Min(1)
Typ
Max
TA = –40 °C to 85 °C
TA = 85 °C, 1 kcycle(2)
TA = 55 °C, 10 kcycle(2)
kcycles
Years
10
30
20
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
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Electrical characteristics
STM32F101x8, STM32F101xB
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 29. They are based on the EMS levels and classes
defined in application note AN1709.
Table 29. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VDD 3.3 V, TA +25 °C,
fHCLK 36 MHz
conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
VDD3.3 V, TA +25 °C,
VEFTB
applied through 100 pF on VDD and VSS pins fHCLK 36 MHz
to induce a functional disturbance conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32F101x8, STM32F101xB
Electrical characteristics
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC61967-2 standard which specifies the test board and the pin loading.
Table 30. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/36 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1GHz
SAE EMI Level
7
8
VDD 3.3 V, TA 25 °C,
LQFP100 package
compliant with
dBµV
-
SEMI
Peak level
13
3.5
IEC 61967-2
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
voltage (human body model) conforming to JESD22-A114
TA +25 °C
VESD(HBM)
2
2000
V
TA +25 °C
Electrostatic discharge
VESD(CDM)
conforming to
II
500
voltage (charge device model)
ANSI/ESD STM5.3.1
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
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89
Electrical characteristics
Symbol
STM32F101x8, STM32F101xB
Table 32. Electrical sensitivities
Parameter
Static latch-up class
Conditions
Class
LU
TA +85 °C conforming to JESD78A
II level A
5.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 33
Table 33. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
IINJ
mA
Injected current on all FT pins
Injected current on any other pin
-5
-5
+0
+5
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STM32F101x8, STM32F101xB
Electrical characteristics
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standard IO
input low level
voltage
-
-
0.28*(VDD-2 V)+0.8 V(1)
Low level input
voltage
VIL
IO FT(3) input low
level voltage
-
-
-
-
0.32*(VDD-2 V)+0.75 V(1)
All I/Os except
BOOT0
(2)
0.35VDD
V
Standard IO
input high level
voltage
0.41*(VDD-2 V)+1.3
V(1)
-
-
High level input
voltage
VIH
IO FT(3) input
high level voltage
0.42*(VDD-2 V)+1 V(1)
-
-
-
-
All I/Os except
BOOT0
(2)
0.65VDD
Standard IO Schmitt
trigger voltage
hysteresis(4)
200
-
-
Vhys
mV
µA
IO FT Schmitt trigger
voltage hysteresis(4)
(5)
5% VDD
-
-
-
VSS VIN VDD
Standard I/Os
-
-
1
3
Input leakage current
Ilkg
(6)
VIN = 5 V
I/O FT
-
Weak pull-up
RPU
VIN VSS
VIN VDD
30
40
50
equivalent resistor(7)
k
Weak pull-down
RPD
CIO
30
-
40
5
50
-
equivalent resistor(7)
I/O pin capacitance
pF
1. Data based on design simulation.
2. Tested in production.
3. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage could be higher than max. if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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89
Electrical characteristics
STM32F101x8, STM32F101xB
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
Figure 23. Standard I/O input characteristics - CMOS port
Area not
determined
V
/V (V)
IH IL
ꢀꢁꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢆꢀ
ꢀꢁꢇꢈ
ꢀꢁꢆꢀ
ꢀꢁꢇꢈ
ꢀꢁꢃꢄ
ꢀ
7IHmin
1.3
7ILmax
0.8
0.7
V
(V)
DD
2
2.7
3
3.3
3.6
ai17277c
Figure 24. Standard I/O input characteristics - TTL port
V
/V (V)
IH IL
Area not
determined
TTL requirements
V
=2V
IH
7IHmin
2.0
1.96
1.25
1.3
0.8
7ILmax
TTL requirements
V
=0.8V
IL
V
(V)
DD
2
2.16
3.6
ai17278b
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 25. 5 V tolerant I/O input characteristics - CMOS port
Area not
determined
V
/V (V)
IH IL
1.67
1
1.55
1.16
1.42
1.07
1.3
0.7
1.295
0.975
1
0.75
V
(V)
DD
2
2.7
3
3.3
3.6
VDD
ai17279c
Figure 26. 5 V tolerant I/O input characteristics - TTL port
V
/V (V)
IH IL
Area not
determined
TTL requirement V =2V
IH
2.0
1.67
1
7IHmin
7ILmax
0.8
0.75
TTL requirements V =0.8V
IL
V
(V)
DD
2
2.16
3.6
ai17280b
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Electrical characteristics
STM32F101x8, STM32F101xB
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can
OL OH
sink or source up to +/-3mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 6).
VDD
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 6).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 8. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
CMOS port(2),,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
0.4
VOL
V
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
(3)
VDD–0.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
TTL port(2)
IIO = +8 mA
0.4
VOL
V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(3)
2.7 V < VDD < 3.6 V
2.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
1.3
VOL
IIO = +20 mA(4)
V
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(3)
VDD–1.3
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
VOL
IIO = +6 mA(4)
V
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(3)
VDD–0.4
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data, not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 36, respectively.
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 8.
(1)
Table 36. I/O AC characteristics
MODEx
[1:0] bit Symbol
Parameter
Conditions
Max Unit
value(1)
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
2
MHz
ns
Output high to low level fall
tf(IO)out
time
125(3)
10
01
CL = 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
Output low to high level rise
tr(IO)out
time
125(3)
10
fmax(IO)out Maximum frequency(2)
MHz
ns
Output high to low level fall
tf(IO)out
time
25(3)
Output low to high level rise
tr(IO)out
time
25(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
50
30
20
MHz
MHz
MHz
Fmax(IO)out Maximum Frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
Output high to low level fall
tf(IO)out
time
11
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
ns
CL = 30 pF, VDD = 2.7 V to 3.6
V
5(3)
Output low to high level rise
tr(IO)out
time
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 27.
3. Guaranteed by design, not tested in production.
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89
Electrical characteristics
STM32F101x8, STM32F101xB
Figure 27. I/O AC characteristics definition
90%
10%
50%
50%
10%
90%
t
t
EXTERNAL
OUTPUT
ON 50pF
r(IO)out
f(IO)out
T
Maximum frequency is achieved if (t + t ) ≤ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 34).
PU
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 8.
Table 37. NRST pin characteristics
Symbol
Parameter
Conditions Min
Typ
Max
Unit
(1)
VIL(NRST)
NRST Input low level voltage
NRST Input high level voltage
–0.5
2
0.8
V
(1)
VIH(NRST)
Vhys(NRST)
RPU
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
200
40
mV
Weak pull-up equivalent resistor(2) VIN VSS
30
50
k
ns
ns
(1)
VF(NRST)
NRST Input filtered pulse
100
(1)
VNF(NRST)
NRST Input not filtered pulse
300
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
60/90
DocID13586 Rev 16
STM32F101x8, STM32F101xB
Electrical characteristics
Figure 28. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal reset
STM32F10x
NRST
Filter
0.1 µF
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 37. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
STM32F101x8, STM32F101xB
5.3.15
TIM timer characteristics
The parameters given in Table 38 are guaranteed by design.
Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
(1)
Table 38. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 36 MHz
TIMxCLK = 36 MHz
27.8
0
ns
MHz
MHz
bit
f
TIMxCLK/2
18
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
ResTIM
Timer resolution
16
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
1820
tCOUNTER
fTIMxCLK = 36 MHz
fTIMxCLK = 36 MHz
0.0278
µs
tTIMxCLK
s
65536 × 65536
119.2
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.16
Communications interfaces
I2C interface characteristics
2
The STM32F101xx medium-density access line I C interface meets the requirements of the
2
standard I C communication protocol with the following restrictions: t
he I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 39. Refer also to
Section 5.3.12: I/O current
for more details on the input/output alternate function characteristics
injection characteristics
(SDA and SCL)
.
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STM32F101x8, STM32F101xB
Electrical characteristics
2
Table 39. I C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL) SCL clock low time
4.7
4.0
250
0
1.3
0.6
100
0
µs
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
th(SDA)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
20+0.1Cb
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
300
th(STA)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
µs
Repeated Start condition setup
time
tsu(STA)
tsu(STO) Stop condition setup time
µs
µs
pF
Stop to Start condition time (bus
tw(STO:STA)
free)
Cb
Capacitive load for each bus line
400
400
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
3.
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89
Electrical characteristics
STM32F101x8, STM32F101xB
2
(1)
Figure 29. I C bus AC waveforms and measurement circuit
V
V
DD_I2C
DD_I2C
STM32F10x
SDA
Rp
Rp
Rs
Rs
I²C bus
SCL
Start repeated
Start
Start
t
su(STA)
SDA
t
t
t
su(SDA)
f(SDA)
r(SDA)
t
su(STO:STA)
Stop
t
t
t
h(SDA)
h(STA)
w(SCLL)
SCL
t
t
su(STO)
t
t
w(SCLH)
r(SCL)
f(SCL)
ai14133e
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
2. Rs = Series protection resistors, Rp = Pull-up resistors, VDD_I2C = I2C bus supply.
(1)(2)
Table 40. SCL frequency (f
fSCL (kHz)
= 36 MHz, VDD_I2C = 3.3 V)
PCLK1
I2C_CCR value
RP = 4.7 k
400
300
200
100
50
0x801E
0x8028
0x803C
0x00B4
0x0168
0x0384
20
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
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STM32F101x8, STM32F101xB
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under the ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
0
0
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
(1)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 tPCLK
73
(1)
th(NSS)
(1)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
50
60
(1)
SPI1
SPI2
1
5
Data input setup time
Master mode
(1)
tsu(MI)
tsu(SI)
th(MI)
Data input setup time
Slave mode
(1)
1
SPI1
SPI2
1
5
Data input hold time
Master mode
(1)
Data input hold time
Slave mode
(1)
th(SI)
3
0
ns
Slave mode, fPCLK = 36 MHz,
presc = 4
55
(1)(2)
ta(SO)
Data output access time
Slave mode, fPCLK = 24 MHz
0
4 tPCLK
(1)(3)
tdis(SO)
Data output disable time Slave mode
10
(1)
(1)
(1)
(1)
tv(SO)
tv(MO)
th(SO)
th(MO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
25
3
Master mode (after enable
edge)
Slave mode (after enable edge)
25
4
Data output hold time
Master mode (after enable
edge)
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Electrical characteristics
STM32F101x8, STM32F101xB
Figure 30. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 31. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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STM32F101x8, STM32F101xB
Electrical characteristics
(1)
Figure 32. SPI timing diagram - master mode
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
t
BIT6 IN
LSB IN
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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Electrical characteristics
STM32F101x8, STM32F101xB
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
Table 42. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
2.4
2.4
3.6
V
V
VREF+ Positive reference voltage
VDDA
Current on the VREF input
pin
IVREF
160(1) 220(1)
µA
fADC
ADC clock frequency
Sampling rate
0.6
14
1
MHz
MHz
(2)
0.05
fS
fADC = 14 MHz
823
17
kHz
(2)
External trigger frequency
Conversion voltage range(3)
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
V
See Equation 1 and
Table 43 for details
(2)
RAIN
RADC
CADC
External input impedance
Sampling switch resistance
50
1
k
k
pF
(2)
(2)
Internal sample and hold
capacitor
8
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
0.107
1.5
0
17.1
239.5
1
(2)
Sampling time
Power-up time
fADC = 14 MHz
fADC = 14 MHz
tS
1/fADC
µs
(2)
tSTAB
0
1
18
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin description for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 42.
68/90
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STM32F101x8, STM32F101xB
Electrical characteristics
Equation 1: R
max formula:
AIN
TS
RAIN ------------------------------------------------------------- – RADC
fADC CADC ln2N + 2
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 43. R
max for f
tS (µs)
= 14 MHz
ADC
AIN
Ts (cycles)
RAIN max (k)
1.5
0.11
0.54
0.96
2.04
2.96
3.96
5.11
17.1
0.4
5.9
7.5
13.5
28.5
41.5
55.5
71.5
239.5
11.4
25.2
37.2
50
NA
NA
1. Guaranteed by design, not tested in production.
(1) (2)
Table 44. ADC accuracy - limited test conditions
Symbol
Parameter
Test conditions
Typ
Max(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±1.3
±1
±2
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V
TA = 25 °C
±1.5
±1.5
±1
Gain error
±0.5
±0.7
±0.8
LSB
Differential linearity error
Integral linearity error
Measurements made after
ADC calibration
±1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should
be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially
inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
3. Based on characterization, not tested in production.
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Electrical characteristics
Symbol
STM32F101x8, STM32F101xB
(1) (2) (3)
Table 45. ADC accuracy
Test conditions
Parameter
Typ
Max(4)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±3
fPCLK2 = 28 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
±1.5
±1.5
±1
Gain error
LSB
Measurements made after
ADC calibration
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.
Figure 33. ADC accuracy characteristics
V
V
DDA
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
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STM32F101x8, STM32F101xB
Electrical characteristics
Figure 34. Typical connection diagram using the ADC
STM32F10xxx
V
DD
Sample and hold ADC
V
0.6 V
T
converter
(1)
C
(1)
R
R
AIN
ADC
AINx
12-bit
converter
V
T
V
AIN
0.6 V
C
(1)
ADC
parasitic
I
1 µA
L
ai14139d
1. Refer to Table 42 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 35 or Figure 36,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 35. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F10xxx
V
REF+
DDA
1 µF // 10 nF
V
V
1 µF // 10 nF
/V
SSA REF-
ai14380b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
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89
Electrical characteristics
STM32F101x8, STM32F101xB
Figure 36. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F10xxx
V
/V
REF+ DDA
1 µF // 10 nF
V
/V
REF– SSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
5.3.18
Temperature sensor characteristics
Table 46. TS characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
VSENSE linearity with temperature
°C
mV/°C
V
1
4.3
2
4.6
T
L
Avg_Slope(1) Average slope
4.0
(1)
Voltage at 25°C
Startup time
1.34
1.43
1.52
V25
(2)
4
10
µs
µs
tSTART
ADC sampling time when reading the
temperature
(3)(2)
17.1
TS_temp
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
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STM32F101x8, STM32F101xB
Package characteristics
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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89
Package characteristics
STM32F101x8, STM32F101xB
Figure 37. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
Pin 1 indentifier
laser marking area
D
A
E
Y
E
Seating
plane
T
ddd
A1
b
e
Detail Y
D
Exposed pad
area
D2
1
L
48
C 0.500x45°
pin1 corner
R 0.125 typ.
Detail Z
E2
1
48
Z
A0B9_ME_V3
1. Drawing is not to scale.
2. There is an exposed die pad on the underside of the QFPN package, this pad is not internally connected to
the VSS or VDD power pads. It is recommended to connect it to VSS.
3. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
Table 47. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
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STM32F101x8, STM32F101xB
Package characteristics
Table 47. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
b
e
0.200
-
0.250
0.500
0.080
0.300
-
0.0079
-
0.0098
0.0197
0.0031
0.0118
-
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 38. UFQFPN48 recommended footprint
7.30
6.20
48
37
1
36
5.60
0.20
7.30
5.80
6.20
5.60
0.30
12
25
13
24
0.75
0.50
0.55
5.80
A0B9_FP_V2
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Package characteristics
STM32F101x8, STM32F101xB
Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package Figure 40. VFQFPN36 recommended
(1)
(1)(2)
outline
footprint (dimensions in mm)
Seating plane
C
ddd
C
A2
A
1.00
4.30
27
19
A1
A3
E2
28
18
b
0.50
27
19
4.10
18
28
4.30
4.10
4.80
4.80
e
D2
D
36
10
0.75
9
1
0.30
36
10
6.30
ai14870b
1
9
Pin # 1 ID
R = 0.20
L
E
ZR_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.
Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.800
-
0.900
0.020
0.650
0.250
0.230
6.000
3.700
6.000
3.700
0.500
0.550
0.080
1.000
0.050
1.000
-
0.0315
-
0.0354
0.0008
0.0256
0.0098
0.0091
0.2362
0.1457
0.2362
0.1457
0.0197
0.0217
0.0031
0.0394
0.0020
0.0394
-
A1
A2
A3
b
-
-
-
-
0.180
5.875
1.750
5.875
1.750
0.450
0.350
0.300
6.125
4.250
6.125
4.250
0.550
0.750
0.0071
0.2313
0.0689
0.2313
0.0689
0.0177
0.0138
0.0118
0.2411
0.1673
0.2411
0.1673
0.0217
0.0295
D
D2
E
E2
e
L
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32F101x8, STM32F101xB
Package characteristics
Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile
Figure 42. LQFP100 recommended
(1)
(1)(2)
quad flat package outline
footprint
SEATING PLANE
C
75
51
0.25 mm
GAUGE PLANE
76
50
0.5
ccc
75
C
0.3
D
D1
D3
L
L1
16.7 14.3
51
50
76
100
26
1.2
1
25
12.3
16.7
100
26
ai14906
PIN 1
IDENTIFICATION
25
1
e
1L_ME_V5
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 49. LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.60
0.15
1.45
0.27
0.2
-
-
0.063
0.05
1.35
0.17
0.09
15.80
13.80
-
-
0.002
0.0531
0.0067
0.0035
0.622
0.5433
-
-
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
1.40
0.22
0.0551
0.0087
-
c
D
16.00
14.00
12.00
16.00
14.00
12.00
0.50
16.2
14.2
-
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.80
13.80
-
16.2
14.2
-
0.622
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.45
0.60
0.75
0.0177
0.0295
L1
k
1.00
0°
3.5°
7°
0.0°
7.0°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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89
Package characteristics
STM32F101x8, STM32F101xB
Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile
Figure 44. LQFP64 recommended
(1)
(1)(2)
quad flat package outline
footprint
SEATING PLANE
C
0.25 mm
GAUGE PLANE
48
33
0.3
49
32
0.5
ccc
C
D
D1
D3
L
12.7
L1
10.3
33
48
32
49
10.3
64
17
b
1.2
1
16
7.8
12.7
64
17
ai14909
16
1
PIN 1
IDENTIFICATION
e
5W_ME_V3
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.60
-
-
0.0630
0.05
-
0.15
0.0020
-
0.0059
1.35
1.40
0.22
-
1.45
0.0531
0.0551
0.0087
-
0.0571
0.17
0.27
0.0067
0.0106
c
0.09
0.20
0.0035
0.0079
D
-
12.00
10.00
12.00
10.00
0.50
3.5°
0.60
1.00
-
-
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
-
D1
E
-
-
-
-
-
-
-
-
E1
e
-
-
-
-
-
-
-
-
0°
0.45
-
7°
0.75
-
0°
0.0177
-
7°
0.0295
-
L
0.0236
0.0394
L1
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
78/90
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STM32F101x8, STM32F101xB
Package characteristics
Figure 46. LQFP48
Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
(1)
(1)(2)
package outline
recommended footprint
Seating plane
C
A
A2
0.50
1.20
A1
c
b
0.25 mm
Gage plane
ccc
C
0.30
36
25
D
37
24
D1
D3
k
0.20
7.30
A1
L
9.70 5.80
25
36
L1
7.30
24
48
13
12
37
1
1.20
5.80
E3
E1
E
9.70
ai14911b
48
13
Pin 1
identification
1
12
5B_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 51. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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89
Package characteristics
STM32F101x8, STM32F101xB
6.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 8: General operating conditions on page 33.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x )
J
A
D
JA
Where:
T max is the maximum ambient temperature in C,
A
is the package junction-to-ambient thermal resistance, in C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = (V × I ) + ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 52. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
46
45
55
32
18
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm / 0.5 mm pitch
JA
°C/W
Thermal resistance junction-ambient
UFQFPN 48 - 6 x 6 mm / 0.5 mm pitch
Thermal resistance junction-ambient
VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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STM32F101x8, STM32F101xB
Package characteristics
6.2.2
Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 53: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F101xx junction temperature range.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
mode at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 447 mW
Dmax
Using the values obtained in Table 52 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
Jmax
This is within the junction temperature range of the STM32F101xx (–40 < T < 105 °C).
J
Figure 47. LQFP64 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
65
75
85
95
105
115
TA (°C)
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89
Ordering information scheme
STM32F101x8, STM32F101xB
7
Ordering information scheme
Table 53. Ordering information scheme
STM32 F 101 C
Example:
8
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
101 = access line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size(1)
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
T = LQFP
U = VFQFPN or UFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Options
xxx = programmed parts
TR = tape and real
1. Although STM32F101x6 devices are not described in this datasheet, orderable part numbers that do not
show the A internal code after temperature range code 6 should be referred to this datasheet for the
electrical characteristics. The low-density datasheet only covers STM32F101x6 devices that feature the A
code.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Revision history
8
Revision history
Table 54. Document revision history
Changes
Date
Revision
06-Jun-2007
1
First draft.
IDD values modified in Table 11: Maximum current consumption in Run
and Sleep modes (TA = 85 °C).
VBAT range modified in Power supply schemes.
VREF+ min value, tSTAB, tlat and fTRIG added to Table 42: ADC
characteristics. Table 38: TIMx characteristics modified.
Note 6 modified and Note 8, Note 5 and Note 7 added below Table 4:
Medium-density STM32F101xx pin definitions.
Figure 20: Low-speed external clock source AC timing diagram,
Figure 11: Power supply scheme, Figure 28: Recommended NRST pin
protection and Figure 29: I2C bus AC waveforms and measurement
circuit(1) modified.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static latch-
up. 25 °C and 85 °C conditions removed and class name modified in
Table 32: Electrical sensitivities.
20-Jul-07
2
tSU(LSE) changed to tSU(LSE) in Table 21: HSE 4-16 MHz oscillator
characteristics.
In Table 28: Flash memory endurance and data retention, typical
endurance added, data retention for TA = 25 °C removed and data
retention for TA = 85 °C added. Note removed below Table 8: General
operating conditions.
VBG changed to VREFINT in Table 11: Embedded internal reference
voltage. IDD max values added to Table 11: Maximum current
consumption in Run and Sleep modes (TA = 85 °C).
IDD(HSI) max value added to Table 23: HSI oscillator characteristics.
RPU and RPD min and max values added to Table 34: I/O static
characteristics. RPU min and max values added to Table 37: NRST pin
characteristics (two notes removed).
Datasheet title corrected. USB characteristics section removed.
Features on page 1 list optimized. Small text changes.
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Revision history
STM32F101x8, STM32F101xB
Table 54. Document revision history (continued)
Date
Revision
Changes
VESD(CDM) value added to Table 31: ESD absolute maximum ratings.
Note added below Table 10: Embedded reset and power control block
characteristics. and below Table 21: HSE 4-16 MHz oscillator
characteristics.
Note added below Table 35: Output voltage characteristics and VOH
parameter description modified.
Table 42: ADC characteristics and Table 44: ADC accuracy - limited test
conditions modified.
Figure 33: ADC accuracy characteristics modified.
Packages are ECOPACK® compliant.
Tables modified in Section 5.3.5: Supply current characteristics.
ADC and ANTI_TAMPER signal names modified (see Table 4: Medium-
density STM32F101xx pin definitions). Table 4: Medium-density
STM32F101xx pin definitions modified. Note 4 removed and values
updated in Table 21: Typical current consumption in Standby mode.
Vhys modified in Table 34: I/O static characteristics.
Updated: Table 29: EMS characteristics and Table 30: EMI
characteristics.
tVDD modified in Table 9: Operating conditions at power-up / power-down.
Typical values modified, note 2 modified and note 3 removed in Table 25:
Low-power mode wakeup timings.
Maximum current consumption Table 12, Table 13 and Table 14 updated.
18-Oct-2007
3
Values added and notes added in Table 15: Typical and maximum current
consumptions in Stop and Standby modes.
On-chip peripheral current consumption on page 44 added.
Package mechanical data inch values are calculated from mm and
rounded to 4 decimal digits (see Section 6: Package characteristics).
Vprog added to Table 27: Flash memory characteristics.
TS_temp added to Table 46: TS characteristics.
TS_vrefint added to Table 11: Embedded internal reference voltage.
Handling of unused pins specified in General input/output characteristics
on page 55. All I/Os are CMOS and TTL compliant.
Table 4: Medium-density STM32F101xx pin definitions: table clarified and
Note 7 modified.
Internal LSI RC frequency changed from 32 to 40 kHz (see Table 24: LSI
oscillator characteristics). Values added to Table 25: Low-power mode
wakeup timings. NEND modified in Table 28: Flash memory endurance
and data retention.
Option byte addresses corrected in Figure 8: Memory map.
ACCHSI modified in Table 23: HSI oscillator characteristics.
tJITTER removed from Table 26: PLL characteristics.
Appendix A: Important notes on page 71 added.
Added: Figure 13, Figure 14, Figure 16 and Figure 18.
84/90
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Revision history
Table 54. Document revision history (continued)
Revision Changes
Date
Document status promoted from preliminary data to datasheet. Small text
changes.
STM32F101CB part number corrected in Table 1: Device summary.
Number of communication peripherals corrected for STM32F101Tx in
Table 2: Device features and peripheral counts (STM32F101xx medium-
density access line) and Number of GPIOs corrected for LQFP package.
Power supply schemes on page 16 modified.
Main function and default alternate function modified for PC14 and PC15
in Table 4: Medium-density STM32F101xx pin definitions, Note 6 added,
Remap column added.
Figure 11: Power supply scheme modified. VDD VSS ratings modified
and Note 1 modified in Table 5: Voltage characteristics. Note 1 modified in
Table 6: Current characteristics.
Note 2 added in Table 10: Embedded reset and power control block
characteristics.
48 and 72 MHz frequencies removed from Table 12, Table 13 and
Table 14. MCU ‘s operating conditions modified in Typical current
consumption on page 42.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum value
added in Table 15: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 16 on page 42 and Table 17 on
page 43. Table 18: Peripheral current consumption modified.
22-Nov-2007
4
Figure 17: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 30: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 31: SPI timing diagram - slave mode
and CPHA = 1(1).
Figure 34: Typical connection diagram using the ADC modified.
tSU(HSE) and tSU(LSE) conditions modified in Table 21 and Table 22,
respectively. Maximum values removed from Table 25: Low-power mode
wakeup timings. tRET conditions modified in Table 28: Flash memory
endurance and data retention. Conditions modified in Table 29: EMS
characteristics.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 71. Small text changes in Table 35: Output voltage characteristics.
Section 5.3.11: Absolute maximum ratings (electrical sensitivity) updated.
Details on unused pins removed from General input/output characteristics
on page 55.
Table 41: SPI characteristics updated. Notes added and Ilkg removed in
Table 42: ADC characteristics. Note added in Table 43 and Table 46.
Note 3 and Note 2 added below Table 44: ADC accuracy - limited test
conditions. Avg_Slope and V25 modified in Table 46: TS characteristics.
JAvalue for VFQFPN36 package added in Table 52: Package thermal
characteristicsI2C interface characteristics on page 62 modified.
Order codes replaced by Section 7: Ordering information scheme.
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Revision history
STM32F101x8, STM32F101xB
Table 54. Document revision history (continued)
Date
Revision
Changes
Figure 2: Clock tree on page 13 added.
CRC added (see CRC (cyclic redundancy check) calculation unit on
page 9 and Figure 8: Memory map on page 29 for address).
Maximum TJ value given in Table 7: Thermal characteristics on page 33.
PD, TA and TJ added, tprog values modified and tprog description clarified in
Table 27: Flash memory characteristics on page 51.
IDD modified in Table 15: Typical and maximum current consumptions in
Stop and Standby modes on page 39.
ACCHSI modified in Table 23: HSI oscillator characteristics on page 49,
note 2 removed.
tRET modified in Table 28: Flash memory endurance and data retention.
14-Mar-2008
5
VNF(NRST) unit corrected in Table 37: NRST pin characteristics on
page 60.
Table 41: SPI characteristics on page 65 modified.
IVREF added in Table 42: ADC characteristics on page 68.
Table 44: ADC accuracy - limited test conditions added. Table 45: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 73).
Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints
added (see Figure 42, Figure 44, Figure 46 and Figure 40).
Section 6.2: Thermal characteristics on page 80 modified.
Appendix A: Important notes removed.
Small text changes.
In Table 28: Flash memory endurance and data retention:
– NEND tested over the whole temperature range
– cycling conditions specified for tRET
21-Mar-2008
6
– tRET min modified at TA = 55 °C
Figure 2: Clock tree corrected. Figure 8: Memory map clarified.
V25, Avg_Slope and TL modified in Table 46: TS characteristics.
CRC feature removed.
Section 1: Introduction modified, Section 2.2: Full compatibility throughout
the family added. CRC feature added.
IDD_VBAT removed from Table 21: Typical current consumption in Standby
mode on page 42.
Values added to Table 40: SCL frequency (fPCLK1= 36 MHz, VDD_I2C =
3.3 V) on page 64.
22-May-2008
7
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 66
modified. Equation 1 corrected.
Section 6.2.2: Evaluating the maximum junction temperature for an
application on page 81 added.
Axx option added to Table 53: Ordering information scheme on page 82.
86/90
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Revision history
Table 54. Document revision history (continued)
Revision Changes
Date
Small text changes.
Power supply supervisor on page 16 modified and VDDA added to Table 8:
General operating conditions on page 33.
Capacitance modified in Figure 11: Power supply scheme on page 31.
Table notes revised in Section 5: Electrical characteristics.
Maximum value of tRSTTEMPO modified in Table 10: Embedded reset and
power control block characteristics on page 35.
Values added to Table 15: Typical and maximum current consumptions in
Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
fHSE_ext modified in Table 19: High-speed external user clock
characteristics on page 45. fPLL_IN modified in Table 26: PLL
characteristics on page 50.
fHCLK corrected in Table 29: EMS characteristics.
21-Jul-2008
8
Minimum SDA and SCL fall time value for Fast mode removed from
Table 39: I2C characteristics on page 63, note 1 modified.
th(NSS) modified in Table 41: SPI characteristics on page 65 and
Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 66.
CADC modified in Table 42: ADC characteristics on page 68 and
Figure 34: Typical connection diagram using the ADC modified.
fPCLK2 corrected in Table 44: ADC accuracy - limited test conditions and
Table 45: ADC accuracy.
Typical TS_temp value removed from Table 46: TS characteristics on
page 72.
LQFP48 package specifications updated (see Table 51, Table 45 and
Table 46).
Axx option removed from Table 53: Ordering information scheme on
page 82.
24-Jul-2008
9
First page modified: “Up to 2 x I²C interfaces” instead of “1 x I²C interface”
STM32F101xx devices with 32 Kbyte Flash memory capacity removed,
document updated accordingly.
Section 2.2: Full compatibility throughout the family on page 14 updated.
Notes modified in Table 4: Medium-density STM32F101xx pin definitions
on page 24.
Note 2 modified below Table 5: Voltage characteristics on page 32,
|VDDx| min and |VDDx| min removed.
Note 2 added to Table 8: General operating conditions on page 33.
23-Sep-2008
10
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 36.
IDD in standby mode at 85 °C modified in Table 15: Typical and maximum
current consumptions in Stop and Standby modes on page 39.
General input/output characteristics on page 55 modified.
Note added below Table 53: Ordering information scheme.
Section 7.1: Future family enhancements removed. Small text changes.
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89
Revision history
STM32F101x8, STM32F101xB
Table 54. Document revision history (continued)
Date
Revision
Changes
I/O information clarified on page 1. Figure 8: Memory map modified.
In Table 4: Medium-density STM32F101xx pin definitions: PB4, PB13,
PB14, PB15, PB3/TRACESWO moved from Default column to Remap
column.
Note modified in Table 12: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 14: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
21-Apr-2009
11
Figure 16, Figure 17 and Figure 18 show typical curves.
Table 19: High-speed external user clock characteristics and Table 20:
Low-speed external user clock characteristics modified.
ACCHSI max values modified in Table 23: HSI oscillator characteristics.
Small text changes.
Note 5 updated and Note 4 added in Table 4: Medium-density
STM32F101xx pin definitions.
VRERINT and TCoeff added to Table 11: Embedded internal reference
voltage. Typical IDD_VBAT value added in Table 15: Typical and maximum
current consumptions in Stop and Standby modes. Figure 15: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.
fHSE_ext min modified in Table 19: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator
characteristics and Table 22: LSE oscillator characteristics (fLSE =
32.768 kHz), notes modified and moved below the tables.
22-Sep-2009
12
Table 23: HSI oscillator characteristics modified. Conditions removed from
Table 25: Low-power mode wakeup timings.
Figure 28: Recommended NRST pin protection modified.
Note 1 modified below Figure 21: Typical application with an 8 MHz
crystal.
Figure 28: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 51.
Jitter added to Table 26: PLL characteristics. CADC and RAIN parameters
modified in Table 42: ADC characteristics. RAIN max values modified in
Table 43: RAIN max for fADC = 14 MHz.
Small text changes.
Added STM32F101TB devices.
Added VFQFPN48 package.
Updated note 2 below Table 39: I2C characteristics
Updated Figure 29: I2C bus AC waveforms and measurement circuit(1)
Updated Figure 28: Recommended NRST pin protection
Updated Section 5.3.12: I/O current injection characteristics
20-May-2010
13
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Revision history
Table 54. Document revision history (continued)
Revision Changes
Date
Updated footnotes below Table 5: Voltage characteristics on page 32 and
Table 6: Current characteristics on page 33
Updated tw min in Table 19: High-speed external user clock
characteristics on page 45
19-Apr-2011
14
Updated startup time in Table 22: LSE oscillator characteristics (fLSE =
32.768 kHz) on page 48
Added Section 5.3.12: I/O current injection characteristics
Updated Section 5.3.13: I/O port characteristics
Replaced VQFN48 package with UQFN48 in cover page packages,
Table 2: Device features and peripheral counts (STM32F101xx medium-
density access line), Figure 7: STM32F101xx medium-density access line
UVFQPFN48 pinout, Table 4: Medium-density STM32F101xx pin
definitions, Figure 4: STM32F101xx medium-density access line LQFP64
pinout, added Figure 37: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
outline, Table 47: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
mechanical data, Table 53: Ordering information scheme and updated
Table 52: Package thermal characteristics
Updated ‘All GPIOs are high current...’ in Section 2.3.22: GPIOs (general-
purpose inputs/outputs)
Updated Table 4: Medium-density STM32F101xx pin definitions
Corrected Sigma letter in Section 5.1.1: Minimum and maximum values
Updated Table 6: Current characteristics
Added ‘VIN’ in Table 8: General operating conditions
15-May-2013
15
Removed the first sentence in Section 5.3.16: Communications interfaces
Updated first sentence in Output driving current
Added note 5. in Table 23: HSI oscillator characteristics
Updated ‘VIL’ and ‘VIH’ in Table 34: I/O static characteristics
Added notes to Figure 23: Standard I/O input characteristics - CMOS port,
Figure 24: Standard I/O input characteristics - TTL port, Figure 25: 5 V
tolerant I/O input characteristics - CMOS port and Figure 26: 5 V tolerant
I/O input characteristics - TTL port
Updated note 2. in Table 45: ADC accuracy
Updated Figure 29: I2C bus AC waveforms and measurement circuit(1)
Updated note 2. and 3.,removed note “the device must internally...” in
Table 39: I2C characteristics
Updated title of Table 40: SCL frequency (fPCLK1= 36 MHz, VDD_I2C =
3.3 V)
Updated the reference for ‘VESD(CDM)’ in Table 31: ESD absolute
maximum ratings
05-Aug-2013
16
Corrected ‘tf(IO)out’ in Figure 27: I/O AC characteristics definition
Updated Table 47: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
mechanical data
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