STM32F101T6U6AXX [STMICROELECTRONICS]
32-BIT, FLASH, 36MHz, RISC MICROCONTROLLER, QCC36, 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-36;
| 型号： | STM32F101T6U6AXX |
| 厂家： | 
ST |
| 描述： | 32-BIT, FLASH, 36MHz, RISC MICROCONTROLLER, QCC36, 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-36 |
| 文件： | 总75页 (文件大小：1552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F101x6
STM32F101x8 STM32F101xB
Access line, advanced ARM-based 32-bit MCU with Flash memory,
six 16-bit timers, ADC and seven communication interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 36 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
VFQFPN36
6 × 6 mm
LQFP48
7 x 7 mm
LQFP64
10 x 10 mm
LQFP100
14 x 14 mm
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
■ Up to 6 timers
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
■ Memories
– 2 watchdog timers (Independent and
Window)
– 32 to 128 Kbytes of Flash memory
– 6 to 16 Kbytes of SRAM
– SysTick timer: 24-bit downcounter
■ Clock, reset and supply management
■ Up to 7 communication interfaces
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
2
– Up to 2 x I C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
■ CRC calculation unit, 96-bit unique ID
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
®
■ ECOPACK packages
Table 1.
Device summary
Root part number
■ Low power
– Sleep, Stop and Standby modes
Reference
– V
supply for RTC and backup registers
BAT
STM32F101C6, STM32F101R6,
STM32F101T6
STM32F101x6
STM32F101x8
STM32F101xB
■ Debug mode
STM32F101C8, STM32F101R8
STM32F101V8, STM32F101T8
– Serial wire debug (SWD) and JTAG
interfaces
STM32F101RB, STM32F101VB,
STM32F101CB
■ DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
2
I Cs and USARTs
■ 1 × 12-bit, 1 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■ Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors, all 5 V-tolerant
except for analog inputs
May 2008
Rev 7
1/75
www.st.com
1
Contents
STM32F101x6, STM32F101x8, STM32F101xB
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29
Embedded reset and power control block characteristics . . . . . . . . . . . 30
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 47
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2/75
STM32F101x6, STM32F101x8, STM32F101xB
Contents
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.1
6.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2.1
6.2.2
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Evaluating the maximum junction temperature for an application . . . . . 69
7
8
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.1
Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3/75
List of tables
STM32F101x6, STM32F101x8, STM32F101xB
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device features and peripheral counts (STM32F101xx High-density
access line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maximum current consumption in Run mode, code with data processing
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maximum current consumption in Run mode, code with data processing
Table 13.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 33
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34
Typical current consumption in Run mode, code with data processing
Table 14.
Table 15.
Table 16.
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Typical current consumption in Sleep mode, code with data processing
Table 17.
code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical current consumption in Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
High-speed user external (HSE) clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
LSE oscillator characteristics (
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
fLSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SCL frequency (f
= 36 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
R
max for f
= 10 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
AIN
ADC
4/75
STM32F101x6, STM32F101x8, STM32F101xB
List of tables
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 64
LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 65
LQFP64 – 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 66
LQFP48 – 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . 67
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5/75
List of figures
STM32F101x6, STM32F101x8, STM32F101xB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM32F101xx Medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32F101xx Medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 17
STM32F101xx Medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F101xx Medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F101xx access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 32
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33
Figure 14. Current consumption in Stop mode with regulator in Run mode versus temperature at
V
= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DD
Figure 15. Current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DD
Figure 16. Current consumption in Standby mode versus temperature at V = 3.3 V and 3.6 V . . . 35
DD
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
(1)
Figure 23. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24. SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
(1)
Figure 25. SPI timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
(1)
Figure 27. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 29. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . . 61
REF+
DDA
Figure 30. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . 62
(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 31. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
Figure 32. Recommended footprint (dimensions in mm)
(1)(2)(3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 33. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 65
(1)
Figure 34. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 35. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
(1)
Figure 36. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 37. LQFP48 – 48-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
(1)
Figure 38. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 39. LQFP64 P max vs. T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
D
A
6/75
STM32F101x6, STM32F101x8, STM32F101xB
Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x6, STM32F101xB and STM32F101x8 Medium-density access line
microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family,
please refer to Section 2.2: Full compatibility throughout the family.
The Medium-density STM32F101xx datasheet should be read in conjunction with the
Medium- and High-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2
Description
The STM32F101x6, STM32F101xB and STM32F101x8 Medium-density access line family
incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a
36 MHz frequency, high-speed embedded memories (Flash memory up to 128 Kbytes and
SRAM up to 16 Kbytes), and an extensive range of enhanced peripherals and I/Os
2
connected to two APB buses. All devices offer standard communication interfaces (two I Cs,
two SPIs, and up to three USARTs), one 12-bit ADC and three general purpose 16-bit
timers.
The STM32F101xx Medium-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.
The STM32F101xx Medium-density access line family includes devices in four different
package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F101xx High-density access line microcontroller family
suitable for a wide range of applications:
●
●
●
●
●
Application control and user interface
Medical and handheld equipment
PC peripherals, gaming and GPS platforms
Industrial applications: PLC, inverters, printers, and scanners
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
7/75
Description
STM32F101x6, STM32F101x8, STM32F101xB
2.1
Device overview
Table 2.
Device features and peripheral counts (STM32F101xx High-density
access line)
STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx
Peripheral
Flash - Kbytes
SRAM - Kbytes
32
6
64
10
32 64 128 32
64 128
10 16
64
10
128
16
6
2
10 16
6
2
General purpose
2
3
3
3
3
3
SPI
I2C
1
1
1
1
1
1
2
2
2
2
1
1
2
2
2
2
USART
2
2
2
3
3
2
3
3
12-bit synchronized ADC
number of channels
1
1
1
1
10 channels
10 channels
37
16 channels
16 channels
80
GPIOs
26
51
CPU frequency
Operating voltage
36 MHz
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 8)
Junction temperature: –40 to +105 °C (see Table 8)
Operating temperatures
Packages
VFQFPN36
LQFP48
LQFP64
LQFP100
8/75
STM32F101x6, STM32F101x8, STM32F101xB
Description
2.2
Full compatibility throughout the family
The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x6, STM32F101x8 and
STM32F101xB are referred to as Medium-density devices, while the STM32F101xC,
STM32F101xD and STM32F101xE are referred to as High-density devices.
High-density devices are an extension of the STM32F101x6/8/B devices, they are specified
in the STM32F101xC/D/E datasheet. They feature higher Flash memory and RAM
densities, and additional peripherals like FSMC and DAC, while remaining fully compatible
with the other members of the family.
The STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the
STM32F101x6/8/B devices, allowing the user to try different memory densities and
providing a greater degree of freedom during the development cycle.
Table 3.
STM32F101xx family
Memory size
Medium-density STM32F101xx devices
High-density STM32F101xx devices
Pinout
128 KB
32 KB Flash 64 KB Flash
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
6 KB RAM
10 KB RAM 16 KB RAM 32 KB RAM 48 KB RAM 48 KB RAM
144
100
64
5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Cs, 1 × ADC, 1 × DAC
3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs, 1 × ADC
FSMC (100 and 144 pins)
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C
1 × ADC
48
36
9/75
Description
STM32F101x6, STM32F101x8, STM32F101xB
2.3
Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xx Medium-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Embedded SRAM
Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F101xx Medium-density access line embeds a nested vectored interrupt
controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
10/75
STM32F101x6, STM32F101x8, STM32F101xB
Description
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.
Boot modes
At startup, boot pins are used to select one of five boot options:
●
●
●
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
V
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
DD
Provided externally through V pins.
DD
●
V
, V
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
DDA
SSA
and PLL (minimum voltage to be applied to V
is 2.4 V when the ADC is used).
DDA
V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
●
V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V is not present.
DD
For more details on how to connect power pins, refer to Figure 10: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V is below a specified threshold, V
, without the need for an
DD
POR/PDR
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
power supply and compares it to the V threshold. An interrupt can be generated
V
DD
PVD
when V drops below the V
and/or when V is higher than the V
threshold. The
DD
PVD
DD
PVD
11/75
Description
STM32F101x6, STM32F101x8, STM32F101xB
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 10: Embedded reset and power control block characteristics for the values of
V
and V
.
POR/PDR
PVD
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
Low-power modes
The STM32F101xx Medium-density access line supports three low-power modes to achieve
the best compromise between low power consumption, short startup time and available
wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
12/75
STM32F101x6, STM32F101x8, STM32F101xB
Description
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, general purpose timers
TIMx and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
supply when present or through the VBAT pin. The backup registers (ten 16-bit registers)
DD
can be used to store data when V power is not present.
DD
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
●
●
●
●
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
General-purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F101xx Medium-
density access line devices. These timers are based on a 16-bit auto-reload up/down
counter, a 16-bit prescaler and feature 4 independent channels each for input capture,
output compare, PWM or one pulse mode output. This gives up to 12 input captures / output
13/75
Description
STM32F101x6, STM32F101x8, STM32F101xB
compares / PWMs on the largest packages. They can work together via the Timer Link
feature for synchronization or event chaining.
The counter can be frozen in debug mode.
Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.
²
I C bus
Up to two I²C bus interfaces can operate in multi-master and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
14/75
STM32F101x6, STM32F101x8, STM32F101xB
Temperature sensor
Description
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2 V < V < 3.6 V. The temperature sensor is internally
DDA
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Figure 1.
STM32F101xx Medium-density access line block diagram
TRACECLK
TRACED[0:3]
as AS
TPIU
Trace
Cont rol ler
Trace/trig
pbus
POWER
SW/JTAG
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
V
= 2 to 3.6V
DD
VSS
VOLT. REG.
3.3V TO 1.8V
Ibus
Cortex M3 CPU
Fmax 36 MHz
Flash 128 KB
64 bit
JTDO
as AF
@VDD
:
Dbus
NVIC
SRAM
16 KB
NVIC
System
@VDD
OSC_IN
OSC_OUT
PCLK1
PCLK2
HCLK
FCLK
PLL &
XTAL OSC
4-16 MHz
GP DMA
CLOCK
MANAGT
7 channels
RC 8 MHz
RC 42 kHz
@VDDA
IWDG
@VDDA
Stand by
interface
SUPPLY
SUPERVISION
VBAT
NRST
VDDA
VSSA
@VBAT
Rst
Int
POR / PDR
OSC32_IN
OSC32_OUT
XTAL 32 kHz
Backup
PVD
RTC
AWU
AHB2
APB2
AHB2
APB1
TAMPER-RTC
reg
Backu p interface
EXTI
80AF
WAKEUP
4 Channels
4 Channels
TIM2
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
TIM3
4 Channels
TIM4
RX,TX, CTS, RTS,
CK, SmartCard as AF
USART2
USART3
RX,TX, CTS, RTS,
CK, SmartCard as AF
MOSI,MISO,SCK,NSS
as AF
SPI2
I2C1
I2C2
SCL,SDA,SMBAL
as AF
MOSI,MISO,
SCK,NSS as AF
SPI1
SCL,SDA
as AF
RX,TX, CTS, RTS,
Smart Card as AF
USART1
@VDDA
16AF
VREF+
12bit ADC1
IF
W W D G
VREF-
Temp sensor
ai14385B
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 125 °C).
15/75
Description
STM32F101x6, STM32F101x8, STM32F101xB
Figure 2.
Clock tree
8 MHz
HSI RC
HSI
/2
HCLK
36 MHz max
to AHB bus, core,
memory and DMA
Clock
Enable (3 bits)
to Cortex System timer
/8
SW
PLLSRC
FCLK Cortex
free running clock
36 MHz max
PLLMUL
HSI
AHB
Prescaler
/1, 2..512
APB1
Prescaler
/1, 2, 4, 8, 16
SYSCLK
..., x16
x2, x3, x4
PLL
PCLK1
PLLCLK
HSE
36 MHz
max
to APB1
peripherals
Peripheral Clock
Enable (13 bits)
to TIM2, 3
and 4
TIMXCLK
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
CSS
Peripheral Clock
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
/2
36 MHz max
PCLK2
to APB2
OSC_OUT
peripherals
4-16 MHz
HSE OSC
Peripheral Clock
Enable (11 bits)
OSC_IN
ADC
to ADC
Prescaler
/2, 4, 6, 8
ADCCLK
/128
LSE
OSC32_IN
to RTC
LSE OSC
RTCCLK
32.768 kHz
OSC32_OUT
RTCSEL[1:0]
to Independent Watchdog (IWDG)
IWDGCLK
LSI
LSI RC
40 kHz
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
Main
Clock Output
/2
PLLCLK
MCO
HSI
HSE
SYSCLK
MCO
ai15104
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
16/75
STM32F101x6, STM32F101x8, STM32F101xB
Pin descriptions
3
Pin descriptions
Figure 3.
STM32F101xx Medium-density access line LQFP100 pinout
PE2
PE3
PE4
PE5
PE6
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
VDD_5 11
LQFP100
OSC_IN
OSC_OUT
NRST
PC0
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0-WKUP
PA1
PD8
PB15
PB14
PB13
PB12
PA2
ai14386b
17/75
Pin descriptions
Figure 4.
STM32F101x6, STM32F101x8, STM32F101xB
STM32F101xx Medium-density access line LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
3
4
5
6
7
PC0
PC1
PC2
PC3
8
LQFP64
9
10
11
12
13
14
15
16
PC6
VSSA
VDDA
PA0-WKUP
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai14387b
Figure 5.
STM32F101xx Medium-density access line LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
LQFP48
PA8
VSSA
VDDA
PB15
PB14
PB13
PB12
PA0-WKUP 10
PA1 11
12
PA2
24
13 14 15 16 17 18 19 20 21 22 23
ai14378c
18/75
STM32F101x6, STM32F101x8, STM32F101xB
Figure 6. STM32F101xx access line VFQPFN36 pinout
Pin descriptions
36 35 34
33 32 31 30 29 28
27
V
V
V
1
DD_3
DD_2
SS_2
OSC_IN/PD0
OSC_OUT/PD1
NRST
2
3
4
5
6
7
8
9
26
PA13
PA12
PA11
PA10
PA9
25
24
QFN36
V
23
22
SSA
V
DDA
PA0-WKUP
PA1
21
20
PA8
PA2
V
19
DD_1
10 11 12 13
14 15 16 17
18
ai14654
19/75
Pin descriptions
STM32F101x6, STM32F101x8, STM32F101xB
Alternate functions(3)
Table 4.
Pins
Pin definitions
Main
Pin name
function(3)
(after reset)
Default
Remap
FT
FT
FT
FT
FT
-
-
-
-
1
-
-
-
-
-
-
PE2
PE3
PE4
PE5
PE6
VBAT
I/O
I/O
I/O
I/O
I/O
S
PE2
PE3
PE4
PE5
PE6
VBAT
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
2
3
4
5
6
-
-
-
-
-
-
1
1
PC13-TAMPER-
RTC(4)
2
3
4
2
3
4
7
8
9
-
-
-
I/O
PC13(5)
PC14(5)
PC15(5)
TAMPER-RTC
OSC32_IN
PC14-OSC32_IN(4) I/O
PC15-
I/O
OSC32_OUT
OSC32_OUT(4)
-
-
-
10
11
12
13
14
15
16
-
-
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
S
S
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
-
5
6
7
-
5
6
7
8
9
2
3
4
-
I
O
I/O
I/O
I/O
I/O
I/O
S
ADC_IN10
ADC_IN11
ADC_IN12
ADC_IN13
-
-
PC1
PC1
-
10 17
11 18
12 19
-
PC2
PC2
-
-
PC3
PC3
8
-
5
-
VSSA
VSSA
-
-
20
21
VREF-
VREF+
VDDA
S
VREF-
VREF+
VDDA
-
-
S
9
13 22
6
S
WKUP/USART2_CTS(8)
ADC_IN0/
/
10 14 23
7
PA0-WKUP
I/O
PA0
TIM2_CH1_ETR(8)
USART2_RTS(8)
ADC_IN1/TIM2_CH2(8)
/
11 15 24
12 16 25
8
9
PA1
PA2
I/O
I/O
PA1
PA2
USART2_TX(8)
ADC_IN2/TIM2_CH3(8)
/
USART2_RX(8)
ADC_IN3/TIM2_CH4(8)
/
13 17 26 10
PA3
I/O
S
PA3
-
18 27
-
VSS_4
VSS_4
20/75
STM32F101x6, STM32F101x8, STM32F101xB
Pin descriptions
Table 4.
Pins
Pin definitions (continued)
Pin name
Alternate functions(3)
Main
function(3)
(after reset)
Default
Remap
-
19 28
-
VDD_4
PA4
S
VDD_4
PA4
SPI1_NSS/ADC_IN4
14 20 29 11
15 21 30 12
16 22 31 13
I/O
I/O
I/O
USART2_CK(8)
/
PA5
PA5
SPI1_SCK/ADC_IN5
SPI1_MISO/ADC_IN6/
TIM3_CH1(8)
PA6
PA6
SPI1_MOSI/ADC_IN7/
TIM3_CH2(8)
17 23 32 14
PA7
I/O
PA7
-
-
24 33
25 34
PC4
PC5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PC4
PC5
ADC_IN14
ADC_IN15
18 26 35 15
19 27 36 16
20 28 37 17
PB0
PB0
ADC_IN8/TIM3_CH3(8)
ADC_IN9/TIM3_CH4(8)
PB1
PB1
PB2/BOOT1
PE7
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
PB2/BOOT1
PE7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
38
39
40
41
42
43
44
45
46
-
-
-
-
-
-
-
-
-
PE8
PE8
PE9
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE10
PE11
PE12
PE13
PE14
PE15
I2C2_SCL(6)
USART3_TX(6) (8)
/
21 29 47
22 30 48
-
-
PB10
PB11
I/O
I/O
FT
FT
PB10
PB11
TIM2_CH3
TIM2_CH4
I2C2_SDA(6)
USART3_RX(6) (8)
/
23 31 49 18
24 32 50 19
VSS_1
VDD_1
S
S
VSS_1
VDD_1
SPI2_NSS(6) (8)
I2C2_SMBAl(6)
USART3_CK(6) (8)
/
/
25 33 51
-
PB12
I/O
FT
PB12
SPI2_SCK(6)(8)
USART3_CTS(6)(8)
/
26 34 52
27 35 53
-
-
PB13
PB14
I/O
I/O
FT
FT
PB13
PB14
SPI2_MISO(6)(8)
USART3_RTS(6)(8)
/
21/75
Pin descriptions
STM32F101x6, STM32F101x8, STM32F101xB
Alternate functions(3)
Table 4.
Pins
Pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
28 36 54
-
-
-
-
-
PB15
PD8
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
PB15
PD8
SPI2_MOSI(6) (8)
-
-
-
-
-
-
-
-
55
56
57
58
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
PD9
PD9
PD10
PD11
PD10
PD11
TIM4_CH1 /
USART3_RTS
-
-
59
-
PD12
I/O
FT
PD12
-
-
-
-
-
-
-
60
61
62
-
-
-
-
-
-
-
PD13
PD14
PD15
PC6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
FT
PD13
PD14
PD15
PC6
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM3_CH1
TIM3_CH2
TIM3_CH3
TIM3_CH4
37 63
38 64
39 65
40 66
PC7
PC7
PC8
PC8
-
PC9
PC9
29 41 67 20
30 42 68 21
31 43 69 22
32 44 70 23
33 45 71 24
PA8
PA8
USART1_CK/MCO
USART1_TX(8)
USART1_RX(8)
USART1_CTS
USART1_RTS
PA13
PA9
PA9
PA10
PA11
PA12
PA10
PA11
PA12
34 46 72 25 PA13/JTMS/SWDIO I/O
73
FT JTMS-SWDIO
Not connected
VSS_2
-
-
-
35 47 74 26
36 48 75 27
VSS_2
VDD_2
S
S
VDD_2
37 49 76 28 PA14/JTCK/SWCLK I/O
FT JTCK/SWCLK
PA14
PA15
TIM2_CH1_ETR/
SPI1_NSS
38 50 77 29
PA15/JTDI
I/O
FT
JTDI
-
-
51 78
52 79
53 80
PC10
PC11
PC12
PD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
PC10
PC11
USART3_TX
USART3_RX
USART3_CK
-
PC12
5
6
5
6
81
82
2
3
-
OSC_IN(7)
OSC_OUT(7)
PD2
PD1
54 83
84
PD2
TIM3_ETR
-
-
-
PD3
PD3
USART2_CTS
22/75
STM32F101x6, STM32F101x8, STM32F101xB
Pin descriptions
Table 4.
Pins
Pin definitions (continued)
Pin name
Alternate functions(3)
Main
function(3)
(after reset)
Default
Remap
-
-
-
-
-
-
-
-
85
-
-
-
-
PD4
PD5
PD6
PD7
I/O
I/O
I/O
I/O
FT
FT
FT
FT
PD4
PD5
PD6
PD7
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
86
87
88
TIM2_CH2 /
SPI1_SCK
39 55 89 30
40 56 90 31
41 57 91 32
42 58 92 33
PB3/JTDO
PB4/JNTRST
PB5
I/O
I/O
I/O
I/O
I/O
FT
FT
JTDO
JNTRST
PB5
PB3/TRACESWO
PB4
TIM3_CH1 /
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
I2C1_SMBAl
I2C1_SCL(8)
TIM4_CH1(6) (8)
/
PB6
FT
FT
PB6
USART1_TX
USART1_RX
I2C1_SDA(8)
/
43 59 93 34
44 60 94 35
PB7
PB7
TIM4_CH2(6) (8)
BOOT0
PB8
I
BOOT0
PB8
45 61 95
46 62 96
-
-
-
-
I/O
I/O
I/O
I/O
S
FT
FT
FT
FT
TIM4_CH3(6) (8)
TIM4_CH4(6) (8)
TIM4_ETR(6)
I2C1_SCL
I2C1_SDA
PB9
PB9
-
-
-
-
97
98
PE0
PE0
PE1
PE1
47 63 99 36
48 64 100
VSS_3
VDD_3
VSS_3
VDD_3
1
S
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 8.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
6. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
23/75
Memory mapping
STM32F101x6, STM32F101x8, STM32F101xB
4
Memory mapping
The memory map is shown in Figure 7.
Figure 7. Memory map
APB memory space
0xFFFF FFFF
reserved
0xE010 0000
reserved
0x6000 0000
reserved
CRC
4K
1K
3K
0x4002 3400
0x4002 3000
0x4002 2400
0x4002 2000
0x4002 1400
0x4002 1000
0x4002 0400
0x4002 0000
0xFFFF FFFF
reserved
1K
3K
1K
3K
1K
Flash interface
reserved
RCC
7
0xE010 0000
Cortex-M3 internal
peripherals
reserved
DMA
0xE000 0000
reserved
1K
6
0x4001 3C00
0x4001 3800
0x4001 3400
0x4001 3000
0x4001 2C00
0x4001 2800
0x4001 2400
1K
1K
USART1
reserved
SPI1
0xC000 0000
1K
1K
1K
1K
reserved
reserved
ADC1
5
0xA000 0000
reserved
2K
0x4001 1C00
0x4001 1800
0x4001 1400
0x4001 1000
0x4001 0C00
0x4001 0800
0x4001 0400
0x4001 0000
1K
1K
1K
1K
Port E
Port D
Port C
Port B
Port A
EXTI
4
0x1FFF FFFF
0x1FFF F80F
reserved
0x8000 0000
Option Bytes
0x1FFF F800
1K
System memory
1K
1K
3
AFIO
0x1FFF F000
0x6000 0000
reserved
35K
0x4000 7400
0x4000 7000
0x4000 6C00
0x4000 6800
0x4000 6400
0x4000 6000
0x4000 5C00
0x4000 5800
0x4000 5400
PWR
1K
1K
2
BKP
reserved
reserved
reserved
reserved
1K
1K
1K
1K
1K
reserved
Peripherals
0x4000 0000
1
I2C2
I2C1
1K
2K
SRAM
0x2000 0000
0x0801 FFFF
reserved
0x4000 4C00
0x4000 4800
0x4000 4400
USART3
USART2
1K
1K
Flash memory
0
0x0800 0000
0x0000 0000
reserved
SPI2
2K
0x0000 0000
Aliased to Flash,
system memory or
SRAM depending on
BOOT pins
0x4000 3C00
0x4000 3800
0x4000 3400
0x4000 3000
0x4000 2C00
0x4000 2800
1K
1K
1K
1K
1K
reserved
IWDG
Reserved
WWDG
RTC
reserved
7K
0x4000 0C00
0x4000 0800
0x4000 0400
0x4000 0000
TIM4
TIM3
TIM2
1K
1K
1K
ai14379c
24/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5
Electrical characteristics
5.1
Test conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
5.1.2
5.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
2 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
5.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
25/75
Electrical characteristics
Figure 8.
STM32F101x6, STM32F101x8, STM32F101xB
Pin loading conditions
Figure 9.
Pin input voltage
STM32F10xxx pin
STM32F10xxx pin
C= 50 pF
V
IN
ai14124b
ai14123b
5.1.6
Power supply scheme
Figure 10. Power supply scheme
V
BAT
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Power switch
1.8-3.6V
Backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
& Memories)
V
DD
V
DD
1/2/3/4/5
Regulator
5 × 100 nF
+ 1 × 10 µF
V
SS
1/2/3/4/5
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
10 nF
+ 1 µF
10 nF
+ 1 µF
V
ADC
REF-
V
SSA
ai14125c
26/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
I
_V
DD BAT
V
BAT
I
DD
V
DD
V
DDA
ai14126
27/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 5.
Symbol
Voltage characteristics
Ratings
Min
Max
Unit
External main supply voltage (including
VDD −VSS
–0.3
4.0
(1)
VDDA and VDD
)
V
Input voltage on five volt tolerant pin(2)
Input voltage on any other pin(2)
VSS −0.3
VSS −0.3
50
+5.5
VDD+0.3
50
VIN
|ΔVDDx
|
Variations between different power pins
mV
Variations between all the different ground
pins
|VSSX −VSS
|
50
50
seeSection 5.3.11:Absolute
maximum ratings (electrical
sensitivity)
Electrostatic discharge voltage (human
body model)
VESD(HBM)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is
induced by VIN<VSS
.
Table 6.
Symbol
IVDD
IVSS
Current characteristics
Ratings
Max.
Unit
Total current into VDD power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on NRST pin
150
150
25
IIO
−25
5
mA
Injected current on High-speed external OSC_IN and Low-
speed external OSC_IN pins
(2)(3)
IINJ(PIN)
5
Injected current on any other pin(4)
5
(2)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(4)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS
.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
28/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Table 7.
Thermal characteristics
Ratings
Symbol
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
5.3
Operating conditions
5.3.1
General operating conditions
Table 8.
Symbol
General operating conditions
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
VDD
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Standard operating voltage
Backup operating voltage
0
0
36
36
MHz
0
36
2
3.6
V
V
VBAT
1.8
3.6
LQFP100
434
444
363
1110
85
LQFP64
Power dissipation at TA =
85 °C(1)
PD
mW
LQFP48
VFQFPN36
Maximum power dissipation –40
°C
°C
°C
TA
TJ
Ambient temperature
Low power dissipation(2)
–40
–40
105
105
Junction temperature range
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 68).
2. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 68).
5.3.2
Operating conditions at power-up / power-down
Subject to general operating conditions for T .
A
Table 9.
Symbol
Operating conditions at power-up / power-down
Parameter
Conditions
Min
Max
Unit
VDD rise time rate
VDD fall time rate
0
∞
∞
tVDD
µs/V
20
29/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 10 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
.
Table 10. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1
2
2.18 2.26
2.08 2.16
V
V
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
2.66 2.78 2.9
2.56 2.68 2.8
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
2.76 2.88
3
V
2.66 2.78 2.9
100
V
(2)
VPVDhyst
VPOR/PDR
VPDRhyst
PVD hysteresis
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
1.84 1.92 2.0
40
V
PDR hysteresis
mV
ms
(2)
tRSTTEMPO
Reset temporization
1.5
2.5
3.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
30/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5.3.4
Embedded reference voltage
The parameters given in Table 11 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 11. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Typ Max Unit
VREFINT
Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.20 1.24
V
ADC sampling time when reading
the internal reference voltage
(1)
TS_vrefint
5.1
17.1
µs
1. Shortest sampling time can be determined in the application by multiple iterations.
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
●
●
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f
PCLK1
HCLK/2 PCLK2
HCLK
The parameters given in Table 12 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz
28.6
19.9
14.7
8.6
External clock (2), all
peripherals enabled
24 MHz
16 MHz
8 MHz
Supply current
in Run mode
IDD
mA
36 MHz
24 MHz
16 MHz
8 MHz
19.8
13.9
10.7
6.8
External clock (4), all
peripherals Disabled
1. Data based on characterization results, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
31/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Max
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
36 MHz(2)
24 MHz(6)
16 MHz(6)
8 MHz(6)
36 MHz
24
17.5
12.5
7.5
mA
External clock (1), all
peripherals enabled
Supply current in
Run mode
IDD
16
External clock(4) all
24 MHz
11.5
8.5
peripherals disabled(6)
16 MHz
8 MHz
5.5
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
2. Based on characterization, not tested in production.
Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
25
20
15
36MHz
16MHz
8MHz
10
5
0
-40
0
25
70
85
Temperature (°C)
32/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
16
14
12
10
36MHz
16MHz
8MHz
8
6
4
2
0
-40
0
25
70
85
Temperature (°C)
Table 14. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Max
Symbol
Parameter
Conditions
fHCLK
Unit
TA = 85 °C
15.5
36 MHz(2)
24 MHz(5)
16 MHz(5)
8 MHz(5)
36 MHz
External clock(1) all
peripherals enabled
11.5
8.5
5.5
5
Supply current in
Sleep mode
IDD
mA
External clock(4), all
24 MHz
4.5
4
peripherals disabled(5)
16 MHz
8 MHz
3
1. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz; external clock is 9 MHz for fHCLK = 36 MHz.
2. Based on characterization, not tested in production.
33/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Table 15. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Max
Symbol
Parameter
Conditions
Unit
V
DD/ VBAT VDD/VBAT
TA = 85 °C
= 2.4 V
= 3.3 V
Regulator in Run mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
23.5
24
200(2)
Supply current in
Stop mode
Regulator in Low-Power mode,
IDD
Low-speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
13.5
14
180(6)
µA
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
Supply current in
Standby mode(3)
1.7
1.1
2
4(6)
Backup domain
supply current
IDD_VBAT
Low-speed oscillator and RTC ON
1.4
1.9(4)
1. Typical values are measured at TA = 25 °C, VDD = 3.3 V, unless otherwise specified.
2. Data based on characterization results, tested in production at VDDmax and fHCLK max.
3. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
DD is present the Backup Domain is powered by VDD supply).
V
4. Data based on characterization results, not rested in production.
Figure 14. Current consumption in Stop mode with regulator in Run mode versus temperature at
V
= 3.3 V and 3.6 V
DD
Stop regulator ON
140
120
100
80
3.3 V
3.6 V
60
40
20
0
-45
25
70
90
Temperature (°C)
34/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Figure 15. Current consumption in Stop mode with regulator in Low-power mode versus
temperature at V = 3.3 V and 3.6 V
DD
140
120
100
80
60
40
20
0
3.3 V
3.6 V
-40
0
25
70
85
Temperature (°C)
Figure 16. Current consumption in Standby mode versus temperature at V = 3.3 V and 3.6 V
DD
Standby mode
3
2.5
2
3.3 V
1.5
3.6 V
1
0.5
0
-45
25
70
90
Temperature (°C)
35/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Typical current consumption
The MCU is placed under the following conditions:
●
●
●
All I/O pins are in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if it is explicitly mentioned
The Flash access time is adjusted to f
wait state from 24 to 36 MHz)
frequency (0 wait state from 0 to 24 MHz, 1
HCLK
●
●
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled f = f , f = f , f
=
HCLK/2 ADCCLK
PCLK1
HCLK/4 PCLK2
f
/4
PCLK2
The parameters given in Table 16 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Typ(1)
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals
enabled(2)
All peripherals
disabled
36 MHz
24 MHz
16 MHz
8 MHz
19
14.8
10.1
7.4
12.9
9.3
5.5
4.6
External
clock(3)
4 MHz
3.3
2.8
2 MHz
2.2
1.9
1 MHz
1.6
1.45
1.25
1.06
14.1
9.5
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
1.3
Supply
1.08
18.3
12.2
8.5
IDD
current in
mA
Run mode
Running on
high speed
internal RC
(HSI), AHB
prescaler
6.8
4.9
4
4 MHz
2.7
2.2
used to
2 MHz
1.6
1.4
reduce the
frequency
1 MHz
1.02
0.73
0.5
0.9
500 kHz
125 kHz
0.67
0.48
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
36/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Table 17. Typical current consumption in Sleep mode, code with data processing
code running from Flash or RAM
Typ(1)
Typ(1)
Symbol Parameter
Conditions
fHCLK
Unit
All peripherals All peripherals
enabled(2)
disabled
36 MHz
24 MHz
16 MHz
8 MHz
7.6
5.3
3.8
2.1
1.6
1.3
3.1
2.3
1.8
1.2
1.1
1
External clock(3)
4 MHz
2 MHz
1 MHz
1.11
1.04
0.98
7
0.98
0.96
0.95
2.5
500 kHz
125 kHz
36 MHz
24 MHz
16 MHz
8 MHz
Supply
IDD
current in
mA
Sleep mode
4.8
1.8
3.2
1.2
Running on High
Speed Internal
RC (HSI), AHB
prescaler used to
reduce the
1.6
0.6
4 MHz
1
0.5
2 MHz
0.72
0.56
0.49
0.43
0.47
0.44
0.42
0.41
frequency
1 MHz
500 kHz
125 kHz
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 18. Typical current consumption in Standby mode
Typ(1)
VDD
Symbol
Parameter
Conditions
Unit
3.3 V
2.4 V
3.3 V
2.4 V
3.3 V
2.4 V
2
Low-speed internal RC oscillator and
independent watchdog OFF
1.5
3.4
2.6
3.2
2.4
Supply current in Low-speed internal RC oscillator and
Standby mode(2) independent watchdog ON
IDD
µA
Low-speed internal RC oscillator ON,
independent watchdog OFF
1. Typical values are measures at TA = 25 °C.
2. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator, RTC ON) to IDD
Standby.
37/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
●
ambient operating temperature and V supply voltage conditions summarized in
DD
Table 5.
Table 19. Peripheral current consumption
Peripheral
Typical consumption at 25 °C(1)
Unit
TIM2
0.6
TIM3
0.6
TIM4
0.6
SPI2
0.08
0.21
0.21
0.18
0.18
0.21
0.21
0.21
0.21
0.21
1.4
APB1
USART2
USART3
I2C1
I2C2
mA
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
ADC1(2)
SPI1
APB2
0.24
0.35
USART1
1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit
in the ADC_CR2 register is set to 1.
38/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5.3.6
External clock source characteristics
High-speed user external clock
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Table 20. High-speed user external (HSE) clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fHSE_ext
8
25
MHz
OSC_IN input pin high level
voltage
VHSEH
VHSEL
0.7VDD
VSS
VDD
V
OSC_IN input pin low level
voltage
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
16
ns
tr(HSE)
tf(HSE)
5
1
OSC_IN Input leakage
current
IL
VSS ≤ VIN ≤ VDD
µA
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
39/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Low-speed user external clock
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Table 21. Low-speed user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency(1)
fLSE_ext
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
VDD
V
OSC32_IN input pin low level
voltage
0.3VDD
OSC32_IN high or low time(1)
OSC32_IN rise or fall time(1)
450
tw(LSE)
ns
tr(LSE)
tf(LSE)
5
1
OSC32_IN Input leakage
current
IL
VSS ≤ VIN ≤ VDD
µA
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Figure 17. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
External
clock source
I
L
OSC _IN
STM32F10xxx
ai14127b
40/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Figure 18. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
External
clock source
I
L
OSC32_IN
STM32F10xxx
ai14140c
High-speed external clock
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)
Table 22. HSE 4-16 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOSC_IN Oscillator frequency
4
8
16
MHz
RF
Feedback resistor
200
kΩ
CL1
Recommended load capacitance versus
RS = 30 Ω
30
pF
equivalent serial resistance of the crystal (RS)(3)
(2)
CL2
VDD = 3.3 V
IN = VSS with 30 pF
i2
HSE driving current
V
1
mA
load
(4)
gm
tSU(HSE)
Oscillator transconductance
Startup time
Startup
25
mA/V
ms
VDD is stabilized
2
(5)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for
high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and
C
L2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of
the combined pin and board capacitance).
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. Based on characterization results, not tested in production.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
41/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Figure 19. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC_IN
HSE
Bias
controlled
gain
8 MHz
resonator
R
F
STM32F10xxx
OSC_OUT
(1)
R
EXT
C
L2
ai14128b
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Low-speed external clock
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 23. LSE oscillator characteristics ( LSE = 32.768 kHz)
f
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ
Max
Unit
RF
5
MΩ
Recommended load capacitance
versus equivalent serial
CL1
CL2
RS = 30 KΩ
15
pF
µA
resistance of the crystal (RS)(1)
VDD = 3.3 V
I2
LSE driving current
1.4
VIN = VSS
gm
Oscillator transconductance
Startup time
5
µA/V
s
(2)
tSU(LSE)
VDD is stabilized
3
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 KHz
resonator
R
F
STM32F10xxx
OSC32_OUT
C
L2
ai14129b
42/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 24. HSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fHSI
Frequency
8
1
1
1
1
MHz
%
TA = –40 to 85 °C
TA = –10 to 85 °C
TA = 0 to 70 °C
at TA = 25 °C
3
2.5
2.2
2
%
ACCHSI Accuracy of HSI oscillator
%
%
tsu(HSI) HSI oscillator startup time
1
2
µs
µA
IDD(HSI) HSI oscillator power consumption
80
100
1.
VDD = 3.3 V, TA = −40 to 85 °C unless otherwise specified.
LSI low speed internal RC oscillator
(1)
Table 25. LSI oscillator characteristics
Min(2)
Symbol
Parameter
Frequency
Conditions
Typ
Max
Unit
fLSI
30
40
60
85
kHz
µs
tsu(LSI) LSI oscillator startup time
LSI oscillator power
IDD(LSI)
0.65
1.2
µA
consumption
1.
VDD = 3 V, TA = −40 to 85 °C unless otherwise specified.
2. Value based on device characterization, not tested in production.
43/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Wakeup time from low power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
Stop or Standby mode: the clock source is the RC oscillator
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 8.
Table 26. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ
Unit
(1)
Wakeup from Sleep mode
Wakeup on HSI RC clock
1.8
µs
tWUSLEEP
Wakeup from Stop mode
(regulator in run mode)
HSI RC wakeup time = 2 µs
3.6
5.4
(1)
µs
µs
tWUSTOP
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP mode
time = 5 µs
Wakeup from Stop mode
(regulator in low-power mode)
HSI RC wakeup time = 2 µs,
Regulator wakeup from power down
time = 38 µs
(1)
tWUSTDBY
Wakeup from Standby mode
50
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 8.
DD
Table 27. PLL characteristics
Value
Test
conditions
Symbol
Parameter
Unit
Min
Typ Max(1)
PLL input clock
8.0
MHz
%
fPLL_IN
PLL input clock duty cycle
PLL multiplier output clock
PLL lock time
40
16
60
fPLL_OUT
tLOCK
36
MHz
µs
200
1. Data based on device characterization, not tested in production.
44/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
5.3.9
Memory characteristics
Flash memory
The characteristics are given at T = −40 to 85 °C unless otherwise specified.
A
Table 28. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
tprog
tERASE
tME
16-bit programming time
Page (1kB) erase time
Mass erase time
TA = −40 to +85 °C
TA = −40 to +85 °C
TA = −40 to +85 °C
40
20
20
52.5
70
40
40
µs
ms
ms
Read mode
HCLK = 36MHz with 2
wait states, VDD = 3.3 V
f
20
5
mA
mA
Write / Erase modes
IDD
Supply current
fHCLK = 36 MHz, VDD
=
3.3 V
Power-down mode / Halt,
DD = 3.0 to 3.6 V
50
µA
V
V
Vprog
Programming voltage
2
3.6
1. Values based on characterization and not tested in production.
Table 29. Flash memory endurance and data retention
Value
Typ
Symbol
Parameter
Conditions
Unit
Min(1)
Max
NEND Endurance
tRET Data retention
TA = –40 °C to 85 °C
TA = 85 °C, 1 kcycle(2)
TA = 55 °C, 10 kcycle(4)
kcycles
Years
10
30
20
1. Values based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
45/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 30. They are based on the EMS levels and classes
defined in application note AN1709.
Table 30. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VDD = 3.3 V, TA = +25 °C,
fHCLK=48 MHz
conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C,
VEFTB
applied through 100 pF on VDD and VSS pins fHCLK = 48 MHz
to induce a functional disturbance
4A
conforms to IEC 1000-4-4
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32F101x6, STM32F101x8, STM32F101xB
Electromagnetic Interference (EMI)
Electrical characteristics
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
Table 31. EMI characteristics
Max vs. [fHSE/fHCLK
]
Monitored
Symbol Parameter
Conditions
Unit
frequency band
8/36 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1GHz
SAE EMI Level
7
8
VDD = 3.3 V, TA = 25 °C,
LQFP100 package
compliant with
dBµV
-
SEMI
Peak level
13
3.5
SAE J 1752/3
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 32. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
TA = +25 °C
conforming to
JESD22-A114
Electrostatic discharge
voltage (human body model)
VESD(HBM)
2
2000
500
V
TA = +25 °C
conforming to
JESD22-C101
Electrostatic discharge
voltage (charge device model)
VESD(CDM)
II
1. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
●
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 33. Electrical sensitivities
Symbol
Parameter
Conditions
Class
II level A
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
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Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.3.12
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage(1)
–0.5
0.8
V
Standard IO input high level
voltage(1)
2
2
VDD+0.5
5.5V
TTL ports
VIH
IO FT(2) input high level
voltage(1)
VIL
VIH
Input low level voltage(1)
Input high level voltage(1)
–0.5
0.35 VDD
VDD+0.5
CMOS ports
V
0.65 VDD
Standard IO Schmitt trigger
voltage hysteresis(3)
200
mV
mV
Vhys
IO FT Schmitt trigger voltage
hysteresis(3)
(4)
5% VDD
VSS ≤VIN ≤VDD
Standard I/Os
1
3
Ilkg
Input leakage current (4)
µA
VIN = 5 V
I/O FT
Weak pull-up equivalent
resistor(5)
RPU
VIN = VSS
VIN = VDD
30
30
40
50
50
kΩ
Weak pull-down equivalent
resistor(6)
RPD
CIO
40
5
kΩ
I/O pin capacitance
pF
1. Values based on characterization results, and not tested in production.
2. FT = Five-volt tolerant.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. With a minimum of 100 mV.
5. Leakage could be higher than max. if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
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STM32F101x6, STM32F101x8, STM32F101xB
Output driving current
Electrical characteristics
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed V ).
OL
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 6).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 6).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 35 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 8. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
TTL port,
IIO = +8 mA,
2.7 V < VDD < 3.6 V
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
CMOS port
IIO = +8 mA
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
2.7 V < VDD < 3.6 V
2.4
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
1.3
V
VOL
IIO = +20 mA(3)
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–1.3
VOH
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
(1)
0.4
V
VOL
IIO = +6 mA(3)
2 V < VDD < 2.7 V
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
(2)
VDD–0.4
VOH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
3. Based on characterization data, not tested in production.
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Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 21 and
Table 36, respectively.
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 8.
(1)
Table 36. I/O AC characteristics
MODEx
[1:0] bit Symbol
Parameter
Conditions
Max Unit
value(1)
fmax(IO)out Maximum frequency(2)
CL = 50 pF, VDD = 2 V to 3.6 V
2
MHz
ns
Output high to low level fall
tf(IO)out
time
125(3)
10
01
CL = 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
CL= 50 pF, VDD = 2 V to 3.6 V
Output low to high level rise
tr(IO)out
time
125(3)
10
fmax(IO)out Maximum frequency(2)
MHz
ns
Output high to low level fall
tf(IO)out
time
25(3)
Output low to high level rise
tr(IO)out
time
25(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 2 V to 2.7 V
50
30
20
MHz
MHz
MHz
Fmax(IO)out Maximum Frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
Output high to low level fall
11
tf(IO)out
time
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
ns
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
Output low to high level rise
tr(IO)out
time
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 21.
3. Values based on design simulation and validated on silicon, not tested in production.
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STM32F101x6, STM32F101x8, STM32F101xB
Figure 21. I/O AC characteristics definition
Electrical characteristics
90%
10 %
50%
50%
90%
10%
t
EXTERNAL
OUTPUT
ON 50pF
t
r(IO)out
r(IO)out
T
Maximum frequency is achieved if (t + t ) £ 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 34).
PU
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 8.
Table 37. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST Input low level voltage
VIH(NRST) NRST Input high level voltage
–0.5
2
0.8
V
VDD+0.5
NRST Schmitt trigger voltage
Vhys(NRST)
hysteresis
200
40
RPU
Weak pull-up equivalent resistor(1)
VIN = VSS
30
50
kΩ
ns
ns
VF(NRST) NRST Input filtered pulse(2)
100
VNF(NRST) NRST Input not filtered pulse(2)
300
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
2. Values guaranteed by design, not tested in production.
Figure 22. Recommended NRST pin protection
V
DD
External
reset circuit
(1)
R
PU
(2)
Internal Reset
NRST
FILTER
0.1 µF
STM32F10xxx
ai14132b
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 37. Otherwise the reset will not be taken into account by the device.
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Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.3.14
TIM timer characteristics
The parameters given in Table 38 are guaranteed by fabrication.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 38. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 36 MHz
TIMxCLK = 36 MHz
27.8
0
ns
MHz
MHz
bit
f
TIMxCLK/2
18
Timer external clock
frequency on CH1 to CH4
fEXT
f
0
ResTIM
Timer resolution
16
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
1820
tCOUNTER
fTIMxCLK = 36 MHz
fTIMxCLK = 36 MHz
0.0278
µs
tTIMxCLK
s
65536 × 65536
119.2
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 8.
2
The STM32F101xx Medium-density access line I C interface meets the requirements of the
2
standard I C communication protocol with the following restrictions: t
he I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 39. Refer also to
Section 5.3.12: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
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STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
2
Table 39. I C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
1.3
0.6
100
0(4)
µs
250
0(3)
th(SDA)
SDA data hold time
900(3)
300
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
1000
300
20+0.1Cb
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
20+0.1Cb
0.6
300
th(STA)
4.0
4.7
4.0
4.7
µs
Repeated Start condition setup
time
tsu(STA)
0.6
tsu(STO) Stop condition setup time
0.6
µs
µs
pF
Stop to Start condition time (bus
tw(STO:STA)
free)
1.3
Cb
Capacitive load for each bus line
400
400
Values based on standard I2C protocol requirement, not tested in production.
1.
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
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Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
2
(1)
Figure 23. I C bus AC waveforms and measurement circuit
V
V
DD
DD
STM32F10xxx
4.7kΩ
4.7kΩ
100 Ω
100 Ω
SDA
SCL
I²C bus
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai14127c
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
(1)(2)
Table 40. SCL frequency (f
fSCL (kHz)
= 36 MHz, VDD = 3.3 V)
PCLK1
I2C_CCR value
RP = 4.7 kΩ
400
300
200
100
50
0x801E
0x8028
0x803C
0x00B4
0x0168
0x0384
20
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
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STM32F101x6, STM32F101x8, STM32F101xB
SPI interface characteristics
Electrical characteristics
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 8.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 41. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max
Unit
0
0
18
18
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 tPCLK
18
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode, fPCLK = 36 MHz,
presc = 4
SCK high and low time
50
60
(2)
SPI1
SPI2
1
5
Data input setup time
Master mode
(2)
tsu(MI)
tsu(SI)
th(MI)
Data input setup time
Slave mode
(2)
1
SPI1
SPI2
1
5
Data input hold time
Master mode
(2)
ns
Data input hold time
Slave mode
(2)
th(SI)
3
0
Slave mode, fPCLK = 36 MHz,
presc = 4
55
(2)(3)
ta(SO)
Data output access time
Slave mode, fPCLK = 24 MHz
0
4 tPCLK
(2)(4)
tdis(SO)
Data output disable time Slave mode
10
(2)(1)
tv(SO)
Data output valid time
Data output valid time
Slave mode (after enable edge)
25
3
Master mode (after enable
edge)
(2)(1)
(2)
tv(MO)
th(SO)
Slave mode (after enable edge)
25
4
Data output hold time
Master mode (after enable
edge)
(2)
th(MO)
1. Remapped SPI1 characteristics to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Figure 24. SPI timing diagram - slave mode and CPHA=0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134b
(1)
Figure 25. SPI timing diagram - slave mode and CPHA=1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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STM32F101x6, STM32F101x8, STM32F101xB
Figure 26. SPI timing diagram - master mode
Electrical characteristics
(1)
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
BIT6 IN
LSB IN
t
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
57/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
Table 42. ADC characteristics
Symbol
Parameter
Conditions
fADC = 14 MHz
fADC = 14 MHz
Min
Typ
Max
Unit
VDDA
ADC power supply
2.4
2.4
3.6
V
V
VREF+ Positive reference voltage
VDDA
Current on the VREF input
IVREF
pin
160(1) 220(1)
µA
fADC
ADC clock frequency
Sampling rate
0.6
14
1
MHz
MHz
(2)
0.05
fS
823
17
kHz
(2)
External trigger frequency
Conversion voltage range(3)
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
V
(2)
RAIN
External input impedance
Sampling switch resistance
See Equation 1 and Table 43
kΩ
kΩ
(2)
1
RADC
Internal sample and hold
capacitor
(2)
5
pF
CADC
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
0.214
Injection trigger conversion
latency
(2)
fADC = 14 MHz
tlat
3(4)
0.143
2(4)
1/fADC
µs
Regular trigger conversion
latency
(2)
fADC = 14 MHz
fADC = 14 MHz
tlatr
1/fADC
µs
0.107
1.5
0
17.1
239.5
1
(2)
Sampling time
Power-up time
tS
1/fADC
µs
(2)
tSTAB
0
1
18
µs
Total conversion time
(including sampling time)
(2)
fADC = 14 MHz
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 42.
58/75
STM32F101x6, STM32F101x8, STM32F101xB
Electrical characteristics
Equation 1: R
max formula:
AIN
TS
RAIN < --------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
(1)
Table 43.
R
max for f
= 10 MHz
AIN
ADC
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.11
1.2
10
7.5
0.54
0.96
2.04
2.96
3.96
5.11
17.1
13.5
28.5
41.5
55.5
71.5
239.5
19
41
60
80
104
350
1. Data guaranteed by design, not tested in production.
(1)
Table 44. ADC accuracy - limited test conditions
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
EO
EG
ED
Total unadjusted error(3)
Offset error(3)
fPCLK2 = 56 MHz,
1.3
1
2
1.5
1.5
1
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Gain error(3)
0.5
0.7
LSB
Differential linearity error(3)
Measurements made after
ADC calibration
VREF+ = VDDA
EL
Integral linearity error(3)
0.8
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. Data based on characterization, not tested in production.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
59/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
(1) (2)
Table 45. ADC accuracy
Symbol
Parameter
Test conditions
Typ
Max(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error(4)
Offset error(3)
2
5
2.5
3
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
1.5
1.5
1
Gain error(3)
LSB
Measurements made after
ADC calibration
Differential linearity error(3)
Integral linearity error(3)
2
1.5
3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
3. Data based on characterization, not tested in production.
4. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Figure 27. ADC accuracy characteristics
V
V
DDA
REF+
[1LSB
=
(or
depending on package)]
IDEAL
4096
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
60/75
STM32F101x6, STM32F101x8, STM32F101xB
Figure 28. Typical connection diagram using the ADC
Electrical characteristics
V
DD
STM32F10xxx
V
0.6 V
T
(1)
(1)
R
R
I
AIN
ADC
AINx
12-bit A/D
conversion
C
(1)
V
T
ADC
1 µA
V
C
L
AIN
AIN
0.6 V
ai14139c
1. Refer to Table 42 for the values of RAIN, RADC and CADC
.
2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 29 or Figure 30,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 29. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F10xxx
V
REF+
DDA
1 µF // 10 nF
V
V
1 µF // 10 nF
/V
SSA REF-
ai14380b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
61/75
Electrical characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Figure 30. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM32F10xxx
V
/V
REF+ DDA
1 µF // 10 nF
V
/V
REF– SSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
Temperature sensor characteristics
Table 46. TS characteristics
5.3.17
Symbol
Parameter
Conditions Min
Typ
Max
Unit
(1)
VSENSE linearity with temperature
°C
mV/°C
V
1
4.3
2
4.6
T
L
Avg_Slope(1) Average slope
4.0
(1)
Voltage at 25°C
Startup time
1.34
1.43
1.52
V25
(2)
4
10
µs
µs
tSTART
ADC sampling time when reading
the temperature
(3)(2)
2.2
17.1
TS_temp
1. Guaranteed by characterization, not tested in production.
2. Data guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
62/75
STM32F101x6, STM32F101x8, STM32F101xB
Package characteristics
6
Package characteristics
6.1
Package mechanical data
®
In order to meet environmental requirements, ST offers the STM32F101xx in ECOPACK
packages. These packages have a Lead-free second-level interconnect. The category of
second-level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
63/75
Package characteristics
STM32F101x6, STM32F101x8, STM32F101xB
Figure 31. VFQFPN36 6 x 6 mm, 0.5 mm pitch, Figure 32. Recommended footprint
(1)
(1)(2)(3)
package outline
(dimensions in mm)
Seating plane
C
ddd
C
4.30
A2
A
36
A1
A3
D
1
27
Pin # 1 ID
R = 0.20
e
4.80
36
28
27
1
4.80
4.10
6.30
4.30
b
4.10
E2
E
0.30
9
19
1.00
0.75
10
18
9
19
0.50
18
10
4.30
L
ai14870
D2
ZR_ME
1. Drawing is not to scale.
2. The back-side pad is not internally connected to the VSS or VDD power pads.
3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should
also be soldered to the PCB.
Table 47. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.800
0.900
0.020
0.650
0.250
0.230
6.000
3.700
6.000
3.700
0.500
0.550
0.080
1.000
0.050
1.000
0.0315
0.0354
0.0008
0.0256
0.0098
0.0091
0.2362
0.1457
0.2362
0.1457
0.0197
0.0217
0.0031
0.0394
0.0020
0.0394
A1
A2
A3
b
0.180
5.875
1.750
5.875
1.750
0.450
0.350
0.300
6.125
4.250
6.125
4.250
0.550
0.750
0.0071
0.2313
0.0689
0.2313
0.0689
0.0177
0.0138
0.0118
0.2411
0.1673
0.2411
0.1673
0.0217
0.0295
D
D2
E
E2
e
L
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
64/75
STM32F101x6, STM32F101x8, STM32F101xB
Package characteristics
(1)(2)
Figure 33. LQFP100, 100-pin low-profile quad flat
Figure 34. Recommended footprint
(1)
package outline
0.25 mm
0.10 inch
GAGE PLANE
75
51
k
D
L
76
50
D1
0.5
L1
D3
51
75
C
0.3
76
50
16.7 14.3
b
E3 E1
E
100
26
1.2
1
25
100
26
12.3
16.7
Pin 1
1
25
ccc
C
identification
e
A1
ai14906
A2
A
SEATING PLANE
C
1L_ME
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 48. LQPF100 – 100-pin low-profile quad flat package mechanical data
millimeters
inches(1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.2
0.063
0.05
1.35
0.002
0.0531
0.0067
0.0035
0.622
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
1.40
0.22
0.0551
0.0087
0.17
c
0.09
D
16.00
14.00
12.00
16.00
14.00
12.00
0.50
15.80
13.80
16.2
14.2
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
0.5433
15.80
13.80
16.2
14.2
0.622
0.6378
0.5591
E1
E3
e
0.5433
L
0.60
0.45
0.75
7°
0.0177
0.0295
7.0°
L1
k
1.00
3.5°
0°
0.0°
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
65/75
Package characteristics
STM32F101x6, STM32F101x8, STM32F101xB
(1)(2)
Figure 35. LQFP64 – 64 pin low-profile quad flat
Figure 36. Recommended footprint
(1)
package outline
D
A
48
33
D1
A2
0.3
A1
49
32
0.5
b
12.7
10.3
E1
E
e
10.3
64
17
1.2
1
16
c
7.8
L1
12.7
L
ai14398
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 49. LQFP64 – 64-pin low-profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.05
1.35
0.17
0.09
0.0020
0.0531
0.0067
0.0035
1.40
0.22
0.0551
0.0087
c
D
12.00
10.00
12.00
10.00
0.50
0.4724
0.3937
0.4724
0.3937
0.0197
3.5°
D1
E
E1
e
θ
0°
3.5°
7°
0°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0394
0.0295
L1
1.00
Number of pins
N
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
66/75
STM32F101x6, STM32F101x8, STM32F101xB
Package characteristics
Figure 37. LQFP48 – 48-pin low-profile quad flat
Figure 38. Recommended
(1)
(1)(2)
package outline
footprint
D
0.50
A
1.20
D1
A2
0.30
13
12
24
A1
25
b
e
0.20
7.30
9.70 5.80
E1
E
7.30
1
36
48
37
1.20
c
5.80
L1
9.70
L
θ
ai14911
ai14384
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Table 50. LQFP48 – 48-pin low-profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
1.60
0.15
1.45
0.27
0.20
0.0630
0.0059
0.0571
0.0106
0.0079
0.05
1.35
0.17
0.09
0.0020
0.0531
0.0067
0.0035
1.40
0.22
0.0551
0.0087
C
D
9.00
7.00
9.00
7.00
0.50
3.5°
0.60
1.00
0.3543
0.2756
0.3543
0.2756
0.0197
3.5°
D1
E
E1
e
θ
0°
7°
0°
7°
L
0.45
0.75
0.0177
0.0236
0.0394
0.0295
L1
Number of pins
N
48
1. Values in inches are converted from mm and rounded to 4 decimal digits.
67/75
Package characteristics
STM32F101x6, STM32F101x8, STM32F101xB
6.2
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 8: General operating conditions on page 29.
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in ° C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 51. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
45
55
18
Θ
°C/W
JA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm / 0.5 mm pitch
Thermal resistance junction-ambient
VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch
6.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
68/75
STM32F101x6, STM32F101x8, STM32F101xB
Package characteristics
6.2.2
Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 52: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F101xx junction temperature range.
Example: High-performance application
Assuming the following application conditions:
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2),
Amax
I
= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low
DDmax
DD
level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output
OL
OL
mode at low level with I = 20 mA, V = 1.3 V
OL
OL
P
P
= 50 mA × 3.5 V= 175 mW
INTmax
= 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
IOmax
This gives: P
= 175 mW and P
= 272 mW
IOmax
INTmax
P
= 175 + 272 = 447 mW
Dmax
Thus: P
= 464 mW
Dmax
Using the values obtained in Table 51 T
is calculated as follows:
Jmax
–
T
For LQFP64, 45 °C/W
= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
Jmax
This is within the junction temperature range of the STM32F101xx (–40 < T < 105 °C).
J
Figure 39. LQFP64 P max vs. T
D
A
700
600
500
400
300
200
100
0
Suffix 6
65
75
85
95
105
115
TA (°C)
69/75
Ordering information scheme
STM32F101x6, STM32F101x8, STM32F101xB
7
Ordering information scheme
Table 52. Ordering information scheme
Example:
STM32 F 101 C
6
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
101 = access line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
6 = 32 Kbytes of Flash memory
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
T = LQFP
U = VFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Options
xxx = programmed parts with 64 or 128 Kbytes of Flash memory
Axx = programmable parts with 32 Kbytes of Flash memory
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
7.1
Future family enhancements
Further developments of the STM32F101xx Medium-density access line will see an
expansion of the current options. Larger packages will soon be available with up to 512 KB
Flash, 48 KB SRAM and with extended features such as flexible static memory controller
(FSMC) support, DAC and additional timers and USARTS.
70/75
STM32F101x6, STM32F101x8, STM32F101xB
Revision history
8
Revision history
Table 53. Document revision history
Date
Revision
Changes
06-Jun-2007
1
First draft.
IDD values modified in Table 11: Maximum current consumption in Run
and Sleep modes (TA = 85 °C).
VBAT range modified in Power supply schemes.
VREF+ min value, tSTAB, tlat and fTRIG added to Table 42: ADC
characteristics. Table 38: TIMx characteristics modified.
Note 6 modified and Note 8, Note 4 and Note 7 added below Table 4: Pin
definitions.
Figure 18: Low-speed external clock source AC timing diagram,
Figure 10: Power supply scheme, Figure 22: Recommended NRST pin
protection and Figure 23: I2C bus AC waveforms and measurement
circuit(1) modified.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static latch-
up. 25 °C and 85 °C conditions removed and class name modified in
Table 33: Electrical sensitivities.
20-Jul-07
2
tSU(LSE) changed to tSU(LSE) in Table 22: HSE 4-16 MHz oscillator
characteristics.
In Table 29: Flash memory endurance and data retention, typical
endurance added, data retention for TA = 25 °C removed and data
retention for TA = 85 °C added. Note removed below Table 8: General
operating conditions.
VBG changed to VREFINT in Table 11: Embedded internal reference
voltage. IDD max values added to Table 11: Maximum current
consumption in Run and Sleep modes (TA = 85 °C).
IDD(HSI) max value added to Table 24: HSI oscillator characteristics.
RPU and RPD min and max values added to Table 34: I/O static
characteristics. RPU min and max values added to Table 37: NRST pin
characteristics (two notes removed).
Datasheet title corrected. USB characteristics section removed.
Features on page 1 list optimized. Small text changes.
71/75
Revision history
STM32F101x6, STM32F101x8, STM32F101xB
Table 53. Document revision history (continued)
Date
Revision
Changes
VESD(CDM) value added to Table 32: ESD absolute maximum ratings.
Note added below Table 10: Embedded reset and power control block
characteristics. and below Table 22: HSE 4-16 MHz oscillator
characteristics.
Note added below Table 35: Output voltage characteristics and VOH
parameter description modified.
Table 42: ADC characteristics and Table 44: ADC accuracy - limited test
conditions modified.
Figure 27: ADC accuracy characteristics modified.
Packages are ECOPACK® compliant.
Tables modified in Section 5.3.5: Supply current characteristics.
ADC and ANTI_TAMPER signal names modified (see Table 4: Pin
definitions). Table 4: Pin definitions modified. Note 4 removed and values
updated in Table 18: Typical current consumption in Standby mode.
Vhys modified in Table 34: I/O static characteristics.
Updated: Table 30: EMS characteristics and Table 31: EMI
characteristics.
tVDD modified in Table 9: Operating conditions at power-up / power-down.
Typical values modified, note 2 modified and note 3 removed in Table 26:
Low-power mode wakeup timings.
Maximum current consumption Table 12, Table 13 and Table 14 updated.
18-Oct-2007
3
Values added and notes added in Table 15: Typical and maximum current
consumptions in Stop and Standby modes.
On-chip peripheral current consumption on page 38 added.
Package mechanical data inch values are calculated from mm and
rounded to 4 decimal digits (see Section 6: Package characteristics).
Vprog added to Table 28: Flash memory characteristics.
TS_temp added to Table 46: TS characteristics.
TS_vrefint added to Table 11: Embedded internal reference voltage.
Handling of unused pins specified in General input/output characteristics
on page 48. All I/Os are CMOS and TTL compliant.
Table 4: Pin definitions: table clarified and Note 7 modified.
Internal LSI RC frequency changed from 32 to 40 kHz (see Table 25: LSI
oscillator characteristics). Values added to Table 26: Low-power mode
wakeup timings. NEND modified in Table 29: Flash memory endurance
and data retention.
Option byte addresses corrected in Figure 7: Memory map.
ACCHSI modified in Table 24: HSI oscillator characteristics.
tJITTER removed from Table 27: PLL characteristics.
Appendix A: Important notes on page 71 added.
Added: Figure 12, Figure 13, Figure 14 and Figure 16.
72/75
STM32F101x6, STM32F101x8, STM32F101xB
Table 53. Document revision history (continued)
Revision history
Date
Revision
Changes
Document status promoted from preliminary data to datasheet. Small text
changes.
STM32F101CB part number corrected in Table 1: Device summary.
Number of communication peripherals corrected for STM32F101Tx in
Table 2: Device features and peripheral counts (STM32F101xx High-
density access line) and Number of GPIOs corrected for LQFP package.
Power supply schemes on page 11 modified.
Main function and default alternate function modified for PC14 and PC15
in Table 4: Pin definitions, Note 5 added, Remap column added.
Figure 10: Power supply scheme modified. VDD −VSS ratings modified
and Note 1 modified in Table 5: Voltage characteristics. Note 1 modified
in Table 6: Current characteristics.
Note 2 added in Table 10: Embedded reset and power control block
characteristics.
48 and 72 MHz frequencies removed from Table 12, Table 13 and
Table 14. MCU ‘s operating conditions modified in Typical current
consumption on page 36.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum value
added in Table 15: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 16 on page 36 and Table 17 on
page 37. Table 19: Peripheral current consumption modified.
Figure 15: Current consumption in Stop mode with regulator in Low-
power mode versus temperature at VDD = 3.3 V and 3.6 V added.
22-Nov-2007
4
Note removed below Figure 24: SPI timing diagram - slave mode and
CPHA=0. Note added below Figure 25: SPI timing diagram - slave mode
and CPHA=1(1).
Figure 28: Typical connection diagram using the ADC modified.
tSU(HSE) and tSU(LSE) conditions modified in Table 22 and Table 23,
respectively. Maximum values removed from Table 26: Low-power mode
wakeup timings. tRET conditions modified in Table 29: Flash memory
endurance and data retention. Conditions modified in Table 30: EMS
characteristics.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 71. Small text changes in Table 35: Output voltage characteristics.
Section 5.3.11: Absolute maximum ratings (electrical sensitivity)
updated.
Details on unused pins removed from General input/output
characteristics on page 48.
Table 41: SPI characteristics updated. Notes added and Ilkg removed in
Table 42: ADC characteristics. Note added in Table 43 and Table 46.
Note 2 and Note 3 added below Table 44: ADC accuracy - limited test
conditions. Avg_Slope and V25 modified in Table 46: TS characteristics.
Θ value for VFQFPN36 package added in Table 51: Thermal
JA
characteristics. I2C interface characteristics on page 52 modified.
Order codes replaced by Section 7: Ordering information scheme.
73/75
Revision history
STM32F101x6, STM32F101x8, STM32F101xB
Table 53. Document revision history (continued)
Date
Revision
Changes
Figure 2: Clock tree on page 16 added.
CRC added (see CRC (cyclic redundancy check) calculation unit on
page 9 and Figure 7: Memory map on page 24 for address).
Maximum TJ value given in Table 7: Thermal characteristics on page 29.
PD, TA and TJ added, tprog values modified and tprog description clarified
in Table 28: Flash memory characteristics on page 45.
IDD modified in Table 15: Typical and maximum current consumptions in
Stop and Standby modes on page 34.
ACCHSI modified in Table 24: HSI oscillator characteristics on page 43,
note 2 removed.
tRET modified in Table 29: Flash memory endurance and data retention.
14-Mar-2008
5
VNF(NRST) unit corrected in Table 37: NRST pin characteristics on
page 51.
Table 41: SPI characteristics on page 55 modified.
IVREF added in Table 42: ADC characteristics on page 58.
Table 44: ADC accuracy - limited test conditions added. Table 45: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 63).
Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints
added (see Figure 34, Figure 36, Figure 38 and Figure 32).
Section 6.2: Thermal characteristics on page 68 modified.
Appendix A: Important notes removed.
Small text changes.
In Table 29: Flash memory endurance and data retention:
– NEND tested over the whole temperature range
– cycling conditions specified for tRET
21-Mar-2008
6
– tRET min modified at TA = 55 °C
Figure 2: Clock tree corrected. Figure 7: Memory map clarified.
V25, Avg_Slope and TL modified in Table 46: TS characteristics.
CRC feature removed.
Section 1: Introduction modified, Section 2.2: Full compatibility
throughout the family added. CRC feature added.
IDD_VBAT removed from Table 18: Typical current consumption in Standby
mode on page 37.
Values added to Table 40: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3
V) on page 54.
22-May-2008
7
Figure 24: SPI timing diagram - slave mode and CPHA=0 on page 56
modified. Equation 1 corrected.
Section 6.2.2: Evaluating the maximum junction temperature for an
application on page 69 added.
Axx option added to Table 52: Ordering information scheme on page 70.
74/75
STM32F101x6, STM32F101x8, STM32F101xB
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