STM32F413ZHJ6 [STMICROELECTRONICS]
High-performance access line, Arm Cortex-M4 core with DSP and FPU, 1,5 MByte of Flash memory, 100 MHz CPU, ART Accelerator, DFSDM;
| 型号： | STM32F413ZHJ6 |
| 厂家： | 
ST |
| 描述： | High-performance access line, Arm Cortex-M4 core with DSP and FPU, 1,5 MByte of Flash memory, 100 MHz CPU, ART Accelerator, DFSDM 时钟 外围集成电路 |
| 文件： | 总207页 (文件大小：3248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM32F413xG STM32F413xH
®
®
ARM -Cortex -M4 32b MCU+FPU, 125 DMIPS, up to 1.5MB Flash,
320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs
Datasheet - production data
Features
)%*$
• Dynamic Efficiency Line with eBAM (enhanced
Batch Acquisition Mode)
– 1.7 V to 3.6 V power supply
UFBGA100
LQFP64 (10x10mm)
LQFP100 (14x14mm)
LQFP144 (20x20mm)
WLCSP81
(4.039x3.951 mm)
(7x7mm)
UFBGA144
(10x10mm)
UFQFPN48
(7x7 mm)
– -40 °C to 85/105/125 °C temperature range
®
®
• Core: ARM 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit, 125 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
• Up to 18 timers: up to twelve 16-bit timers, two
32-bit timers up to 100 MHz each with up to
four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input, two
watchdog timers (independent and window),
one SysTick timer, and a low-power timer
• Debug mode
• Memories
– Serial wire debug (SWD) & JTAG
– Up to 1.5 Mbytes of Flash memory
– 320 Kbytes of SRAM
®
– Cortex -M4 Embedded Trace Macrocell™
• Up to 114 I/O ports with interrupt capability
– Up to 109 fast I/Os up to 100 MHz
– Up to 114 five V-tolerant I/Os
– Flexible external static memory controller
with up to 16-bit data bus: SRAM, PSRAM,
NOR Flash memory
– Dual mode Quad-SPI interface
• Up to 24 communication interfaces
2
• LCD parallel interface, 8080/6800 modes
– Up to 4x I C interfaces (SMBus/PMBus)
• Clock, reset and supply management
– 1.7 to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Up to 10 UARTS: 4 USARTs / 6 UARTs
(2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816
interface, LIN, IrDA, modem control)
– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
full-duplex I2S interfaces
– SDIO interface (SD/MMC/eMMC)
– Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with PHY
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Power consumption
– Run: 112 µA/MHz (peripheral off)
– 3x CAN (2.0B Active)
– 1xSAI
– Stop (Flash in Stop mode, fast wakeup
time): 42 µA Typ.; 80 µA max @25 °C
– Stop (Flash in Deep power down mode,
slow wakeup time): 15 µA Typ.;
46 µA max @25 °C
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
• All packages are ECOPACK 2
– Standby without RTC: 1.1 µA Typ.;
14.7 µA max at @85 °C
®
–
V
supply for RTC: 1 µA @25 °C
BAT
Table 1. Device summary
• 2x12-bit D/A converters
• 1×12-bit, 2.4 MSPS ADC: up to 16 channels
Reference
Part number
• 6x digital filters for sigma delta modulator,
12x PDM interfaces, with stereo microphone
and sound source localization support
STM32F413CH STM32F413MH STM32F413RH
STM32F413VH STM32F413ZH
STM32F413xH
STM32F413CG STM32F413MG STM32F413RG
STM32F413VG STM32F413ZG
STM32F413xG
• General-purpose DMA: 16-stream DMA
June 2017
DocID029162 Rev 5
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This is information on a product in full production.
www.st.com
Contents
STM32F413xG/H
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 19
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
Enhanced Batch Acquisition mode (eBAM) . . . . . . . . . . . . . . . . . . . . . . . 19
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 36
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.30 Dynamic tuning of PDM delays for sound source localization . . . . . . . . . 39
3.31 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.33 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.34 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.39 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.40 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1
4.2
4.3
4.4
4.5
4.6
WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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STM32F413xG/H
4.7
4.8
4.9
UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pins definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5
6
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating conditions at power-up/power-down (regulator ON) . . . . . . . 85
Operating conditions at power-up / power-down (regulator OFF) . . . . . 86
Embedded reset and power control block characteristics . . . . . . . . . . . 86
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 105
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 116
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 121
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.22
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
BAT
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.27 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 172
6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.8.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 201
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
B.1
B.2
B.3
Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 204
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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List of tables
STM32F413xG/H
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F413xG/H features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DFSDM feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F413xG/H pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STM32F413xG/H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
STM32F413xG/H register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 84
VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 85
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 86
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DD
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 89
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V. . . 90
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.6 V . . 91
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 3.6 V. . . . . . . . . . . . . . . 92
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 1.7 V. . . . . . . . . . . . . . . 93
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 3.6 V. . . . . 94
DD
Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 1.7 V. . . . . 95
DD
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Typical and maximum current consumption in Sleep mode - V = 3.6 V. . . . . . . . . . . . . 96
DD
Typical and maximum current consumption in Sleep mode - V = 1.7 V. . . . . . . . . . . . . 97
DD
Typical and maximum current consumptions in Stop mode - V = 1.7 V . . . . . . . . . . . . . 98
DD
Typical and maximum current consumption in Stop mode - V =3.6 V. . . . . . . . . . . . . . . 98
DD
Typical and maximum current consumption in Standby mode - V = 1.7 V . . . . . . . . . . . 98
DD
Typical and maximum current consumption in Standby mode - V = 3.6 V . . . . . . . . . . . 99
DD
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . . 99
BAT
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6/207
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List of tables
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LSE
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Flash memory programming with V voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
PP
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SCL frequency (f
= 50 MHz, V = V
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 131
PCLK1
DD
DD_I2C
2
FMPI C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
ADC accuracy at f
ADC accuracy at f
ADC accuracy at f
= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 146
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 146
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
BAT
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 161
Table 89.
Table 90.
DocID029162 Rev 5
7/207
8
List of tables
STM32F413xG/H
Table 91.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 163
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 101. eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 102. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 177
Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 110. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 194
Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 112. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 197
Table 113. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 114. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8/207
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F413xG/H block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 26
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 10. Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 11. STM32F413xG/H WLCSP81 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. STM32F413xG/H UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. STM32F413xG/H LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. STM32F413xG/H LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. STM32F413xG/H LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. STM32F413xG/H UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. STM32F413xG/H UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 20. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
EXT
Figure 24. Typical V
current consumption (LSE and RTC ON/LSE oscillator
BAT
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 25. Typical V current consumption (LSE and RTC ON/LSE oscillator
BAT
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 26. Low-power mode wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 31. ACC
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
HSI
Figure 32. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LSI
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 35. FT/TC I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
2
Figure 38. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2
Figure 39. FMPI C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
2
Figure 43. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
2
Figure 44. I S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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11
List of figures
STM32F413xG/H
Figure 45. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 46. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 47. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 143
Figure 48. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 50. Power supply and reference decoupling (V
Figure 51. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 149
). . . . . . . . . . . . . . . . 150
REF+
DDA
connected to V
REF+
DDA
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 159
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 161
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 58. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 62. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 65. WLCSP81 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 67. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 68. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 182
Figure 70. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 71. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 72. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 186
Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 74. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 75. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 189
Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 77. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 78. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 79. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 80. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 81. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 82. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 83. UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 84. Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 85. Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 204
Figure 87. USB peripheral-only Full speed mode with direct connection
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STM32F413xG/H
List of figures
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 205
Figure 89. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 205
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11
Introduction
STM32F413xG/H
1
Introduction
This datasheet provides the description of the STM32F413xG/H microcontrollers.
®
®
For information on the Cortex -M4 core, please refer to the Cortex -M4 programming
manual (PM0214) available from www.st.com.
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STM32F413xG/H
Description
2
Description
®
®
The STM32F413XG/H devices are based on the high-performance ARM Cortex -M4 32-
®
bit RISC core operating at a frequency of up to 100 MHz. Their Cortex -M4 core features a
Floating point unit (FPU) single precision which supports all ARM single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F413XG/H devices belong to the STM32F4 access product lines (with products
combining power efficiency, performance and integration) while adding a new innovative
feature called Batch Acquisition Mode (BAM) allowing to save even more power
consumption during data batching.
The STM32F413XG/H devices incorporate high-speed embedded memories (up to
1.5 Mbytes of Flash memory, 320 Kbytes of SRAM), and an extensive range of enhanced
I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB
bus matrix.
All devices offer a 12-bit ADC, two 12-bit DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timer for motor control, two general-purpose 32-bit timers
and a low power timer.
They also feature standard and advanced communication interfaces.
2
2
•
•
•
Up to four I Cs, including one I C supporting Fast-Mode Plus
Five SPIs
2
2
Five I Ss out of which two are full duplex. To achieve audio class accuracy, the I S
peripherals can be clocked via a dedicate internal audio PLL or via an external clock to
allow synchronization.
•
•
•
•
•
Four USARTs and six UARTs
An SDIO/MMC interface
An USB 2.0 OTG full-speed interface
Three CANs
An SAI.
In addition, the STM32F413xG/H devices embed advanced peripherals:
•
•
•
A flexible static memory control interface (FSMC)
A Quad-SPI memory interface
Two digital filter for sigma modulator (DFSDM) supporting microphone MEMs and
sound source localization, one with two filters and up to four inputs, and the second
one with four filters and up to eight inputs
They are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals
depends on the selected package. The STM32F413xG/H operate in the – 40 to + 125 °C
temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
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42
Description
STM32F413xG/H
These features make the STM32F413xG/H microcontrollers suitable for a wide range of
applications:
•
•
•
•
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub
Wearable devices
Connected objects
Wifi modules
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STM32F413xG/H
Description
Table 2. STM32F413xG/H features and peripheral counts
Peripherals
STM32F413xG
STM32F413xH
Flash memory (Kbyte)
1024
1536
SRAM
System
(Kbyte)
320 (256 + 64)
1
320 (256 + 64)
Quad-SPI memory
interface
-
-
-
-
-
-
1
(1)
(1)
1
(1)
(1)
(1)
1
(1)
FSMC memory controller
1
1
1
1
1
1
FSMC LCD parallel
interface Data bus size
8
16
8
16
General-
purpose
(2)
(3)
(2)
(3)
10
10
10
10
10
10
10
10
Advanced-
control
(4)
(4)
2
2
2
2
Timers
Basic
2
1
2
1
1
Low-power
timer
Random number generator
1
2
SPI/ I S
5/5 (2 full duplex)
5/5 (2 full duplex)
2
I C
3
1
3
1
2
I CFMP
USART/
UART
3/3
4/3
4/6
3/3
4/3
4/6
Comm.
interfaces
SDIO/MMC
1
1
USB/OTG FS
1
1
1
1
1
1
1
1
Dual power rail
No
Yes
No
Yes
No
Yes
No
Yes
CAN
SAI
3
1
6
3
1
6
Number of digital Filters for
Sigma-delta modulator
Number of channels
7
11
50
12
81
7
11
50
12
81
GPIOs
36
60
114
36
60
114
1
1
12-bit ADC
Number of channels
10
16
10
16
Yes
Yes
12-bit DAC
Number of channels
2
2
Maximum CPU frequency
Operating voltage
100 MHz
1.7 to 3.6 V
100 MHz
1.7 to 3.6 V
Ambient temperatures:
Ambient temperatures:
– 40 to +85 °C / – 40 to +105 °C / – 40 to +125 °C
– 40 to +85 °C / – 40 to +105 °C / – 40 to +125 °C
Operating temperatures
Package
Junction temperature: –40 to + 130 °C
Junction temperature: –40 to + 130 °C
UFQFPN
48
LQFP
64
WLCSP
81
UFBGA/
LQFP100 LQFP144
UFBGA/ UFQFPN
WLCSP
81
UFBGA/
LQFP100 LQFP144
UFBGA/
LQFP64
48
1. 64 pins package: support only 8 bits multiplexed mode interface
81 pins package: support 1 external memory of up to 64KB in multiplexed mode
100 pins: support 2 external memories of up to 64MB in multiplexed mode
Refer to Table 11: FSMC pin definition for more detailed information
2. 48 pins packages: TIM3 and TIM4: ETR pin not available.
3. 81 pins packages: TIM4: ETR pin not available.
4. 48 pins packages: TIM8:CH1, CH2, CH3 and CH4 pins not available.
DocID029162 Rev 5
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42
Description
STM32F413xG/H
2.1
Compatibility with STM32F4 series
The STM32F413xG/H are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F413xG/H can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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16/207
DocID029162 Rev 5
STM32F413xG/H
Description
Figure 2. Compatible board design for LQFP64 package
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DocID029162 Rev 5
17/207
42
Description
STM32F413xG/H
Figure 4. STM32F413xG/H block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
18/207
DocID029162 Rev 5
STM32F413xG/H
Functional overview
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU core with embedded Flash and
SRAM
®
®
The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The ARM Cortex -M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F413xG/H devices are compatible with all ARM tools and software.
Figure 4 shows the general block diagram of the STM32F413xG/H.
®
®
Note:
Cortex -M4 with FPU is binary compatible with Cortex -M3.
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
®
®
standard ARM Cortex -M4 with FPU processors. It balances the inherent performance
®
®
advantage of the ARM Cortex -M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3
Enhanced Batch Acquisition mode (eBAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the Flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (Flash and ART™ stopped) with the DMA using BAM followed by
some very short processing from Flash allows to drastically reduce the power consumption
of the application.
The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed
through the Ibus and Dbus, thus improving code execution performance.
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Functional overview
STM32F413xG/H
A dedicated application note (AN4515) describes how to implement the STM32F413xG/H
BAM to allow the best power efficiency.
3.4
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5
Embedded Flash memory
The devices embed up to 1.5 Mbytes of Flash memory available for storing programs and
data, plus 512 bytes of one-time programmable (OTP) memory organized in 16 blocks of
32 bytes, each which can be independently locked.
The user Flash memory area can be protected against read operations by an entrusted
code (read protection or RDP). Different protection levels are available. The user Flash
memory is divided into sectors, which can be individually protected against write operation.
Flash sectors can also be protected individually against D-bus read accesses by using the
proprietary readout protection (PCROP).
Refer to the product line reference manual for additional information on OTP area and
protection features.
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.20: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
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DocID029162 Rev 5
STM32F413xG/H
Functional overview
3.7
Embedded SRAM
All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states.
3.8
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
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CPU can access SRAM1 memory via S-bus, when SRAM1 is mapped at the address range:
0x2000 0000 to 0x2003 FFFF.
CPU can access SRAM2 memory via S-bus, when SRAM2 is mapped at the address range:
0x2004 0000 to 0x2004 FFFF.
CPU can access SRAM1 memory via I-bus and D-bus, when SRAM1 is remapped at
address 0x0000 0000 either by booting from RAM memory or by the remap mode.
CPU can access SRAM2 memory via I-bus and D-bus, when SRAM2 is mapped at the
address range: 0x1000 0000 to 0x1000 FFFF.
Performance boosts up, when the CPU access SRAM memory via the I-bus.
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Functional overview
STM32F413xG/H
3.9
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
•
•
SPI and I S
2
2
I C and I CFMP
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC/eMMC host interface
Quad-SPI
ADC
DAC
Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter
SAI.
3.10
Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
•
•
•
8-,16-bit data bus width
Write FIFO
Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
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Functional overview
3.11
Quad-SPI memory interface (QUAD-SPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
3.12
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 102 maskable interrupt channels plus the 16 interrupt lines of the
®
Cortex -M4 with FPU.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
3.14
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
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Functional overview
STM32F413xG/H
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
2
performance. In this case, the I S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
•
•
Boot from user Flash memory
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
Table 3. Embedded bootloader interfaces
SPI3
SPI1
PA4/
PA5/
PA6/
PA7
SPI4
I2C
USART1 USART2 USART3 I2C1 I2C2 I2C3
PE11/ CAN2 USB
PE12/ PB5/ PA11
PE13/ PB13 /P12
PE14
PA15/
PC10/
PC11/
PC12
FMP1
PB14/
PB15
Package
PA9/
PA10
PD6/
PD5
PB11/
PB10
PB6/ PF0/ PA8/
PB7 PF1 PB4
UFQFPN48
LQFP64
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
WLCSP81
LQFP100
LQFP144
UFBGA100
UFBGA144
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
-
Y
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
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STM32F413xG/H
Functional overview
3.16
Power supply schemes
•
V
= 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
DD
(POR/PDR) disabled, provided externally through V pins. Requires the use of an
DD
external power supply supervisor connected to the V and NRST pins.
DD
•
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
SSA DDA
and PLL. V
and V
must be connected to V and V , respectively, with
SSA DD SS
DDA
decoupling technique.
Note:
The V /V minimum value of 1.7 V is obtained with the use of an external power supply
DD DDA
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
•
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
•
V
can be connected either to VDD or an external independent power supply (3.0
DDUSB
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to V
. When the V
is connected to a separated power supply,
DDUSB
DDUSB
it is independent from V or V
but it must be the last supply to be provided and the
DD
DDA
first to disappear.
The following conditions VDDUSB must be respected:
–
During power-on phase (V < V
), V
should be always lower than
DDUSB
DD
DD_MIN
V
DD
–
During power-down phase (V < V
), V
should be always lower than
DDUSB
DD
DD_MIN
V
DD
–
–
V
rising and falling time rate specifications must be respected.
DDUSB
In operating mode phase, V
could be lower or higher than VDD:
DDUSB
– If USB is used, the associated GPIOs powered by V
are operating
DDUSB
between V
and V
.
DDUSB_MIN
DDUSB_MAX
– If USB is not used, the associated GPIOs powered by V
are operating
DDUSB
between V
and V
.
DD_MIN
DD_MAX
DocID029162 Rev 5
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Functional overview
STM32F413xG/H
Figure 6. V
connected to an external independent power supply
DDUSB
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3.17
Power supply supervisor
3.17.1
Internal reset ON
This feature is available for V operating voltage range 1.8 V to 3.6 V.
DD
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when V is below a specified threshold, V
or
POR/PDR
DD
V
, without the need for an external reset circuit.
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
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Functional overview
3.17.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor V and should set the device in reset
DD
mode when V is below 1.7 V. NRST should be connected to this external power supply
DD
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
(1)
Figure 7. Power supply supervisor interconnection with internal reset OFF
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A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
3.18
Voltage regulator
The regulator has three operating modes:
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
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42
Functional overview
STM32F413xG/H
3.18.1
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•
MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
•
•
LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available on 100- and 144-pin
packages.
All packages have the regulator ON feature.
3.18.2
Regulator OFF
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator
OFF mode allows to supply externally a V voltage source through V
and V
12
CAP_1
CAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V . An external power
12
supply supervisor should be used to monitor the V of the logic power domain. PA0 pin
12
should be used for this purpose, and act as power-on reset on V power domain.
12
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power
domain which is not reset by the NRST pin.
12
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
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Functional overview
Figure 8. Regulator OFF
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The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 9).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 10).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
The minimum value of V depends on the maximum frequency targeted in the application.
12
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Functional overview
STM32F413xG/H
Figure 9. Startup in regulator OFF: slow V slope
DD
power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast V slope
DD
power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
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Functional overview
3.18.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal power supply supervisor availability
Power supply
supervisor ON
Power supply
supervisor OFF
Package
Regulator ON
Regulator OFF
UFQFPN48
LQFP64
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
WLCSP81
BYPASS_REG
set to VSS
BYPASS_REG
set to VDD
PDR_ON
set to VDD
PDR_ON
set to VSS
LQFP100
LQFP144
Yes
Yes
No
No
Yes
No
Yes
Yes
UFBGA100
UFBGA144
BYPASS_REG
set to VSS
BYPASS_REG
set to VDD
Yes
PDR_ON
set to VDD
Yes
PDR_ON
set to VSS
Yes
Yes
BYPASS_REG
set to VSS
BYPASS_REG
set to VDD
3.19
Real-time clock (RTC) and backup registers
The backup domain includes:
•
•
The real-time clock (RTC)
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 byte of user application data
when V power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 3.20: Low-power
modes).
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Functional overview
STM32F413xG/H
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
V
supply when present or from the VBAT pin.
DD
3.20
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
To further reduce the power consumption, the Flash memory can be switched off
before entering in Sleep mode. Note that this requires a code execution from the RAM.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp
event occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.21
VBAT operation
The VBAT pin allows to power the device V
domain from an external battery, an external
BAT
super-capacitor, or from V when no external battery and an external super-capacitor are
DD
present.
V
operation is activated when V is not present.
DD
BAT
The VBAT pin supplies the RTC and the backup registers.
When the microcontroller is supplied from V , external interrupts and RTC alarm/events
Note:
BAT
do not exit it from V
operation. When PDR_ON pin is not connected to V (internal
BAT
DD
Reset OFF), the V
functionality is no more available and VBAT pin should be connected
BAT
to V
.
DD
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Functional overview
3.22
Timers and watchdogs
The devices embed two advanced-control timer, ten general-purpose timers, two basic
timers, one low-power timer, two watchdog timers and a SysTick timer.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control and general-purpose timers.
Table 5. Timer feature comparison
Max.
Max.
DMA
request
generation channels
Capture/
compare
Timer
type
Counter Counter Prescaler
Complemen- interface timer
Timer
resolution
type
factor
tary output
clock
(MHz) (MHz)
clock
Any
Up,
integer
Advance TIM1,
16-bit
Down, between1
Up/down
Yes
Yes
Yes
No
4
4
4
2
1
2
1
Yes
100
50
100
100
100
100
100
100
100
d-control
TIM8
and
65536
Any
integer
Down, between1
Up,
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
No
No
No
Up/down
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
50
Up/down
and
65536
Any
integer
between1
and
TIM9
Up
100
100
50
65536
General
purpose
Any
integer
between1
and
TIM10,
TIM11
Up
Up
Up
No
65536
Any
integer
between1
and
TIM12
No
65536
Any
integer
between1
and
TIM13,
TIM14
No
50
65536
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Functional overview
STM32F413xG/H
Table 5. Timer feature comparison (continued)
Max.
Max.
DMA
request
generation channels
Capture/
compare
Timer
type
Counter Counter Prescaler
Complemen- interface timer
Timer
resolution
type
factor
tary output
clock
(MHz) (MHz)
clock
Any
integer
between1
and
Basic
timers
TIM6,
TIM7
16-bit
16-bit
Up
Up
Yes
No
0
2
No
No
50
50
100
100
65536
Low-
power
timer
Between
1 and 128
LPTIM1
3.22.1
3.22.2
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Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator
multiplexed on 4 independent channels. They have complementary PWM outputs with
programmable inserted dead times. They can also be considered as complete general-
purpose timers. Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability
(0-100%).
The advanced-control timers can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
General-purpose timers (TIMx)
There are elven synchronizable general-purpose timers embedded in the STM32F413xG/H
(see Table 5 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F413xG/H devices include 4 full-featured general-purpose timers: TIM2.
TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four
DocID029162 Rev 5
STM32F413xG/H
Functional overview
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs
TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in
conjunction with the other general-purpose timers and TIM1 advanced-control timer via
the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM output.
TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and
TIM12 have two independent channels for input capture/output compare, PWM or one-
pulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 full-
featured general-purpose timers or used as simple time bases.
3.22.3
3.22.4
Basic timer (TIM6, TIM7)
TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request
generation.
Low-power timer (LPTIM1)
The low-power timer (LPTIM1) features an independent clock and runs in Stop mode if it is
clocked by LSE, LSI or by an external clock. LPTIM1 is able to wakeup the devices from
Stop mode.
The low-power timer main features are the following:
•
•
•
•
•
•
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one shot mode
Selectable software / hardware input trigger
Selectable clock source
–
–
Internal clock source: LSE, LSI, HSI or APB1 clock
External clock source over LPTIM1 input (working even with no internal clock
source running, used by the pulse counter application)
•
•
•
Programmable digital glitch filter
Encoder mode
Active in Stop mode.
3.22.5
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
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Functional overview
STM32F413xG/H
3.22.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.22.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.23
Inter-integrated circuit interface (I2C)
2
The devices feature up to four I C bus interfaces which can operate in multimaster and
slave modes:
2
•
One I C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to
400 kHz) modes and Fast-mode plus (up to 1 MHz).
2
•
Three I C interfaces support the Standard mode (up to 100 KHz) and the Fast mode
(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on
the complete solution, refer to the nearest STMicroelectronics sales office.
2
All I C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave)
and embed a hardware CRC generation/verification.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 6).
Table 6. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15 I2C peripheral clocks
3.24
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) as well as six universal asynchronous receiver
transmitters (UART4, UART5, UART7, UART8, UART9 and UART10).
These ten interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. USART1, USART6, UART9 and UART10 can
communicate at speeds up to 12.5 Mbit/s. The other interfaces communicate at up to
6.25 bit/s.
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USART1, USART2, USART3 and USART6 provide hardware management of the CTS and
RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 7. USART feature comparison
Max. baud
Max. baud
USART Standard Modem
SPI
master
Smartcard rate in Mbit/s rate in Mbit/s APB
(ISO 7816) (oversampling (oversampling mapping
LIN
irDA
name
features (RTS/CTS)
by 16)
by 8)
APB2
(max.
100 MHz)
USART1
USART2
USART3
UART4
UART5
USART6
UART7
UART8
UART9
UART10
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
X
X
-
6.25
12.5
APB1
(max.
50 MHz)
3.12
3.12
3.12
3.12
6.25
3.12
3.12
6.25
6.25
6.25
6.25
6.25
6.25
12.5
6.25
6.25
12.5
12.5
APB1
(max.
50 MHz)
APB1
(max.
50 MHz)
APB1
(max.
50 MHz)
-
-
-
APB2
(max.
100 MHz)
X
-
X
-
X
-
APB1
(max.
50 MHz)
APB1
(max.
50 MHz)
-
-
-
APB2
(max.
100 MHz)
-
-
-
APB2
(max.
-
-
-
100 MHz)
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Functional overview
STM32F413xG/H
3.25
3.26
3.27
Serial peripheral interface (SPI)
The devices feature five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and
SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interfaces can be configured to operate in TI mode for communications in master
mode and slave mode.
Inter-integrated sound (I2S)
2
Five standard I S interfaces (multiplexed with SPI1 to SPI5) are available. They can be
operated in master or slave mode, in simplex communication mode, and full duplex mode
2
for I2S2 and I2S3. All I S interfaces can be configured to operate with a 16-/32-bit resolution
as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz
2
are supported. When either or both of the I S interfaces is/are configured in master mode,
the master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency.
2
All I Sx interfaces can be served by the DMA controller.
Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
3.28
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S and SAI applications. It allows
2
to achieve error-free I S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
Different sources can be selected for the I2S master clock of the APB1 and the I2S master
clock of the APB2. This gives the flexibility to work with two different audio sampling
frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI
clocks or an external clock provided through a pin (external PLL or CODEC output)
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Functional overview
Different sources can also be selected for the SAI. The different possible sources are the
main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin
(external PLL or CODEC output).
2
The PLLI2S configuration can be modified to manage an I S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
3.29
Digital filter for sigma-delta modulators (DFSDM)
The device embeds two DFSDMs:
•
DFSDM1 has 2 digital filters modules and 4 external input serial channels
(transceivers) or alternately 2 internal parallel inputs support.
•
DFSDM2 features 4 digital filters modules and 8 external input serial channels
(transceivers) or alternately 4 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. It is also possible to introduce a programmable delay between different
microphones (beamforming feature). DFSDM features optional parallel data stream inputs
from microcontrollers memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
Table 8. DFSDM feature comparison
External input serial External input parallel
DFSDM instance
Digital filters
channels
channels
DFSDM1
DFSDM2
4
8
2
4
2
4
3.30
Dynamic tuning of PDM delays for sound source localization
A mechanism is implemented on top of the DFSDM allowing to dynamically tune PDM
delays of each microphone without the need to add external delay lines.
Audio application with several microphones require strong microphones placement
constraints, as the distance between the microphones must be a multiple of v/F where v is
the speed of the sound and F is the PCM sampling frequency.
The designed mechanism removes this constraint by programming delays for each digital
microphone with the granularity of the PDM clock rate prior to the conversion into PCM rate.
The tuning delay is performed by a clock skipping technique.
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The strong benefits of such mechanism coupled with DFSDM are:
•
•
•
•
•
Possibility to place the digital microphones close to each other
No need for external delay lines
The delay tuning is done in hardware, preventing the use of MIPs crunching algorithms
Possibility to change the delay tuning on the fly
The low power consumption and CPU time released due to the DFSDM hardware PDM
to PCM conversion
The impacted audio application are beam forming and sound source localization
3.31
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.32
3.33
Controller area network (bxCAN)
The three CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2, and 512 bytes for
CAN3.
Universal serial bus on-the-go full-speed (USB_OTG_FS)
The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with USB 2.0 and OTG 1.0
specifications. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock,
which is generated by a PLL connected to the HSE oscillator. The Battery Charging
Detection (BCD) can detect and identify the type of port it is connected to (standard USB or
charger). The charging type can also be detected: Dedicated Charging Port (DCP),
Charging Downstream Port (CDP) and Standard Downstream Port (SDP).
Some packages provide a dedicated USB power rail allowing to supply the USB from a
different voltage that the rest of the device. As an example, the device can be powered with
the minimum specified supply voltage while the USB runs at the level defined by the
standard.
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Functional overview
The main USB OTG FS features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Support of session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed when bus-powered devices are
connected
•
•
Link Power Management (LPM)
Battery Charging Detection (BCD) supporting DCP, CDP and SDP
3.34
3.35
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz.
3.36
Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.37
Digital to analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This digital interface supports the following features:
•
Two DAC output channels
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Functional overview
STM32F413xG/H
•
•
•
•
•
•
•
•
•
8-bit or 12-bit output mode
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference (V
)
REF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA channels.
3.38
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN18 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.39
3.40
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F413xG/H through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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Pinouts and pin description
4
Pinouts and pin description
4.1
WLCSP81 pinout description
Figure 11. STM32F413xG/H WLCSP81 pinout
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4.2
UFQFPN48 pinout description
Figure 12. STM32F413xG/H UFQFPN48 pinout
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Pinouts and pin description
4.3
LQFP64 pinout description
Figure 13. STM32F413xG/H LQFP64 pinout
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Pinouts and pin description
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4.4
LQFP100 pinout description
Figure 14. STM32F413xG/H LQFP100 pinout
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Pinouts and pin description
4.5
LQFP144 pinout description
Figure 15. STM32F413xG/H LQFP144 pinout
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Pinouts and pin description
STM32F413xG/H
4.6
UFBGA100 pinout description
Figure 16. STM32F413xG/H UFBGA100 pinout
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Pinouts and pin description
4.7
UFBGA144 pinout description
Figure 17. STM32F413xG/H UFBGA144 pinout
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1. The above figure shows the package top view.
4.8
Pins definition
Table 9. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
Input/ output pin
5 V tolerant I/O
FTf
TC
TTa
B
5 V tolerant I/O, I2C FM+ option
Standard 3.3 V I/O
I/O structure
3.3 V tolerant I/O directly connected to DAC
Dedicated BOOT0 pin
NRST
Bidirectional reset pin with embedded weak pull-up resistor
Notes
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
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Pinouts and pin description
STM32F413xG/H
Table 9. Legend/abbreviations used in the pinout table (continued)
Name
Abbreviation
Definition
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 10. STM32F413xG/H pin definition
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TRACECLK,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
UART10_RX,
(2)
-
-
NC
1
B2
A3
1
PE2
I/O
FT
-
FSMC_A23,
EVENTOUT
TRACED0, SAI1_SD_B,
UART10_TX,
(2)
-
-
-
-
NC
NC
2
3
A1
B1
A2
B2
2
3
PE3
PE4
I/O
I/O
FT
FT
-
-
FSMC_A19,
EVENTOUT
TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
SAI1_SD_A,
(2)(3)
DFSDM1_DATIN3,
FSMC_A20,
EVENTOUT
TRACED2, TIM9_CH1,
SPI4_MISO,
SPI5_MISO,
(2)
-
-
-
-
NC
NC
4
5
C2
D2
B3
B4
4
5
PE5
I/O
I/O
FT
FT
SAI1_SCK_A,
DFSDM1_CKIN3,
FSMC_A21,
-
-
EVENTOUT
TRACED3, TIM9_CH2,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
SAI1_FS_A,
(2)(3)
PE6
FSMC_A22,
EVENTOUT
1
2
1
2
B9
C8
6
7
E2
C1
C2
A1
6
7
VBAT
S
-
-
-
VBAT
PC13-
ANTI_TAMP
(4)(5)
I/O
FT
EVENTOUT
TAMP_1
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
PC14-
OSC32_IN
(4)(5)(6)
3
4
-
3
4
-
C9
8
9
-
D1
B1
C1
C3
C4
D4
E2
E3
E4
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
FT
EVENTOUT
OSC32_IN
PC15-
OSC32_OUT
(4)(6)
D9
E1
9
EVENTOUT
OSC32_OUT
I2C2_SDA, FSMC_A0,
-
-
-
-
-
-
-
-
-
-
-
-
10
11
12
13
14
15
PF0
PF1
PF2
PF3
PF4
PF5
-
-
-
-
-
-
-
EVENTOUT
I2C2_SCL, FSMC_A1,
-
-
-
-
EVENTOUT
I2C2_SMBA, FSMC_A2,
-
-
-
-
EVENTOUT
TIM5_CH1, FSMC_A3,
-
-
-
-
EVENTOUT
TIM5_CH2, FSMC_A4,
-
-
-
-
EVENTOUT
TIM5_CH3, FSMC_A5,
-
-
-
-
EVENTOUT
-
-
-
-
D8 10
F2
D2
D3
16
17
VSS
VDD
S
S
-
-
-
-
-
-
-
-
E8
11
G2
TRACED0, TIM10_CH1,
SAI1_SD_B,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F3
F2
G3
G2
18
19
20
PF6
PF7
PF8
I/O
I/O
I/O
FT
FT
FT
FT
-
-
-
-
UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
-
-
-
-
TRACED1, TIM11_CH1,
SAI1_MCLK_B,
UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
-
-
-
-
SAI1_SCK_B,
UART8_RX,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
SAI1_FS_B,
UART8_TX,
TIM14_CH1,
-
-
-
-
21
22
PF9
I/O
I/O
QUADSPI_BK1_IO1,
EVENTOUT
TIM1_ETR, TIM5_CH4,
EVENTOUT
-
-
-
G1
D1
PF10
FT
FT
-
-
(6)
5
5
E9 12
F1
23 PH0 - OSC_IN I/O
EVENTOUT
OSC_IN
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Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
PH1 -
OSC_OUT
(6)
6
7
6
7
F9
13
G1
H2
E1
F1
24
25
I/O
I/O
FT
EVENTOUT
-
OSC_OUT
NRST
G9 14
NRST
PC0
RST
-
LPTIM1_IN1,
DFSDM2_CKIN4,
SAI1_MCLK_B,
EVENTOUT
ADC1_IN10,
WKUP2
-
-
8
9
F8
15
H1
J2
H1
H2
26
27
I/O
I/O
FT
FT
-
-
LPTIM1_OUT,
DFSDM2_DATIN4,
SAI1_SD_B,
ADC1_IN11,
WKUP3
C7 16
PC1
PC2
EVENTOUT
LPTIM1_IN2,
DFSDM2_DATIN7,
SPI2_MISO,
I2S2ext_SD,
-
10 D7 17
J3
H3
H4
28
I/O
FT
-
ADC1_IN12
SAI1_SCK_B,
DFSDM1_CKOUT,
FSMC_NWE,
EVENTOUT
LPTIM1_ETR,
DFSDM2_CKIN7,
SPI2_MOSI/I2S2_SD,
SAI1_FS_B, FSMC_A0,
EVENTOUT
-
11 E7 18
K2
29
PC3
I/O
FT
-
ADC1_IN13
-
8
-
-
-
19
-
-
30
31
-
VDD
VSSA
VREF-
VREF+
VDDA
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 H9 20
J1
K1
L1
M1
J1
K1
L1
M1
-
-
-
-
-
G8 21
22
32
33
9
13 F7
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
ADC1_IN0,
WKUP1
10 14 G7 23
L2
J2
34
35
PA0
PA1
I/O
I/O
FT
FT
-
-
UART4_TX, EVENTOUT
TIM2_CH2, TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
11 15 H8 24
M2
K2
ADC1_IN1
UART4_RX,
QUADSPI_BK1_IO3,
EVENTOUT
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, I2S2_CKIN,
12 16 J9
25
K3
L3
L2
36
37
PA2
I/O
I/O
FT
FT
-
-
USART2_TX,
FSMC_D4/FSMC_DA4,
EVENTOUT
ADC1_IN2
ADC1_IN3
TIM2_CH4, TIM5_CH4,
TIM9_CH2, I2S2_MCK,
USART2_RX,
13 17 E6 26
M2
PA3
SAI1_SD_B,
FSMC_D5/FSMC_DA5,
EVENTOUT
-
-
-
18 H7 27
-
E3
-
-
38
-
VSS
S
I
-
FT
-
-
-
-
-
-
-
-
-
-
BYPASS_
REG
-
F6
-
H5
F4
19 J8
28
39
VDD
S
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
DFSDM1_DATIN1,
FSMC_D6/FSMC_DA6,
EVENTOUT
ADC1_IN4,
DAC_OUT1
14 20 E5 29
M3
K4
J3
40
41
PA4
I/O
I/O
TTa
TTa
-
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
DFSDM1_CKIN1,
FSMC_D7/FSMC_DA7,
EVENTOUT
ADC1_IN5,
DAC_OUT2
15 21 G6 30
K3
PA5
PA6
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO, I2S2_MCK,
DFSDM2_CKIN1,
TIM13_CH1,
16 22 F5
31
L4
L3
42
I/O
FT
-
ADC1_IN6
QUADSPI_BK2_IO0,
SDIO_CMD,
EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
DFSDM2_DATIN1,
TIM14_CH1,
17 23 J7
32
M4
M3
43
PA7
I/O
FT
-
ADC1_IN7
QUADSPI_BK2_IO1,
EVENTOUT
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Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
DFSDM2_CKIN2,
I2S1_MCK,
-
-
24 H6 33
K5
L5
J4
K4
L4
44
45
46
PC4
PC5
PB0
I/O
I/O
I/O
FT
FT
FT
-
-
-
QUADSPI_BK2_IO2,
FSMC_NE4,
ADC1_IN14
ADC1_IN15
ADC1_IN8
EVENTOUT
DFSDM2_DATIN2,
I2CFMP1_SMBA,
USART3_RX,
QUADSPI_BK2_IO3,
FSMC_NOE,
25 J6
34
EVENTOUT
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
18 26 E4 35
M5
SPI5_SCK/I2S5_CK,
EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
19 27 G5 36
M6
L6
M4
J5
47
48
PB1
PB2
I/O
I/O
FT
FT
-
-
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN0,
QUADSPI_CLK,
EVENTOUT
ADC1_IN9
BOOT1
LPTIM1_OUT,
DFSDM1_CKIN0,
QUADSPI_CLK,
EVENTOUT
20 28 H5 37
-
-
-
-
-
-
-
-
-
-
M5
L5
49
50
PF11
PF12
I/O
I/O
FT
FT
-
-
TIM8_ETR, EVENTOUT
-
-
TIM8_BKIN, FSMC_A6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
G4
G5
51
52
VSS
VDD
S
S
-
-
-
-
-
-
-
-
I2CFMP1_SMBA,
FSMC_A7, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K5
M6
L6
53
54
55
PF13
PF14
PF15
I/O
I/O
I/O
FT
FTf
FTf
-
-
-
-
-
-
I2CFMP1_SCL,
FSMC_A8, EVENTOUT
I2CFMP1_SDA,
FSMC_A9, EVENTOUT
CAN1_RX, UART9_RX,
FSMC_A10,
-
-
-
-
-
-
-
-
-
-
K6
J6
56
57
PG0
PG1
I/O
I/O
FT
FT
-
-
-
-
EVENTOUT
CAN1_TX, UART9_TX,
FSMC_A11, EVENTOUT
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM1_ETR,
DFSDM1_DATIN2,
UART7_Rx,
QUADSPI_BK2_IO0,
FSMC_D4/FSMC_DA4,
EVENTOUT
(2)
-
-
NC 38
M7
M7
58
PE7
I/O
FT
-
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_Tx,
(2)
-
-
-
-
NC 39
L7
L7
K7
59
60
PE8
PE9
I/O
I/O
FT
FT
-
-
QUADSPI_BK2_IO1,
FSMC_D5/FSMC_DA5,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
QUADSPI_BK2_IO2,
FSMC_D6/FSMC_DA6,
EVENTOUT
J5
40
M8
-
-
-
-
-
-
-
-
-
-
-
H6
G6
61
62
VSS
VDD
S
S
-
-
-
-
-
-
-
-
TIM1_CH2N,
DFSDM2_DATIN0,
QUADSPI_BK2_IO3,
FSMC_D7/FSMC_DA7,
EVENTOUT
-
-
-
-
G4 41
L8
J7
63
64
PE10
PE11
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH2,
DFSDM2_CKIN0,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
FSMC_D8/FSMC_DA8,
EVENTOUT
H4 42
M9
H8
TIM1_CH3N,
DFSDM2_DATIN7,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
FSMC_D9/FSMC_DA9,
EVENTOUT
-
-
-
-
J4
43
L9
J8
65
66
PE12
PE13
I/O
I/O
FT
FT
-
-
-
-
TIM1_CH3,
DFSDM2_CKIN7,
SPI4_MISO,
F4
44 M10 K8
SPI5_MISO,
FSMC_D10/FSMC_DA1
0, EVENTOUT
DocID029162 Rev 5
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73
Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
DFSDM2_DATIN1,
FSMC_D11/FSMC_DA1
1, EVENTOUT
-
-
-
-
G3 45 M11
L8
67
68
PE14
PE15
I/O
I/O
FT
FT
-
-
-
-
TIM1_BKIN,
DFSDM2_CKIN1,
FSMC_D12/FSMC_DA1
2, EVENTOUT
J3
46 M12 M8
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
21 29 H3 47
L10 M9
69
PB10
PB11
I/O
I/O
FTf
FT
-
-
USART3_TX,
I2CFMP1_SCL,
DFSDM2_CKOUT,
SDIO_D7, EVENTOUT
-
TIM2_CH4, I2C2_SDA,
I2S2_CKIN,
-
-
NC
-
K9 M10 70
-
USART3_RX,
EVENTOUT
22 30 H2 48
L11
F12
H7
-
71
-
VCAP_1
VSS
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
23 31 J2
24 32 J1
49
50 G12 G7
72
VDD
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
USART3_CK,
25 33 F3
51
L12 M11 73
PB12
I/O
FT
-
-
CAN2_RX,
DFSDM1_DATIN1,
UART5_RX,
FSMC_D13/FSMC_DA1
3, EVENTOUT
TIM1_CH1N,
I2CFMP1_SMBA,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
USART3_CTS,
26 34 G2 52 K12 M12 74
PB13
I/O
FT
-
-
CAN2_TX,
DFSDM1_CKIN1,
UART5_TX, EVENTOUT
56/207
DocID029162 Rev 5
STM32F413xG/H
Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM1_CH2N,
TIM8_CH2N,
I2CFMP1_SDA,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
27 35 E3 53
K11 L11 75
PB14
I/O
FTf
-
-
DFSDM1_DATIN2,
TIM12_CH1,
FSMC_D0/FSMC_DA0,
SDIO_D6, EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
I2CFMP1_SCL,
SPI2_MOSI/I2S2_SD,
28 36 H1 54 K10 L12 76
PB15
I/O
FTf
-
-
DFSDM1_CKIN2,
TIM12_CH2, SDIO_CK,
EVENTOUT
USART3_TX,
FSMC_D13/FSMC_DA1
(2)
-
-
-
-
NC 55
-
L9
K9
77
78
PD8
PD9
I/O
I/O
FT
FT
-
-
3, EVENTOUT
USART3_RX,
FSMC_D14/FSMC_DA1
4, EVENTOUT
F2
56
K8
-
USART3_CK,
UART4_TX,
FSMC_D15/FSMC_DA1
5, EVENTOUT
(7)
-
-
-
-
G1 57
J12
J11
J9
79
80
PD10
PD11
I/O
I/O
FT
FT
-
-
DFSDM2_DATIN2,
I2CFMP1_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
FSMC_A16,
(2)
NC 58
H9
EVENTOUT
TIM4_CH1,
DFSDM2_CKIN2,
I2CFMP1_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
FSMC_A17,
(2)
-
-
NC 59
J10 L10 81
PD12
I/O
FTf
-
-
EVENTOUT
TIM4_CH2,
I2CFMP1_SDA,
QUADSPI_BK1_IO3,
FSMC_A18,
(2)
-
-
-
-
NC 60 H12 K10 82
PD13
VSS
I/O
S
FTf
-
EVENTOUT
-
-
-
G8
83
-
-
-
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73
Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
-
-
-
-
-
-
-
F8
84
VDD
S
-
-
-
-
-
TIM4_CH3,
I2CFMP1_SCL,
DFSDM2_CKIN0,
UART9_RX,
(2)
NC 61 H11 K11 85
PD14
I/O
FTf
FSMC_D0/FSMC_DA0,
EVENTOUT
TIM4_CH4,
I2CFMP1_SDA,
DFSDM2_DATIN0,
UART9_TX,
(2)
-
-
NC 62 H10 K12 86
PD15
I/O
FTf
-
FSMC_D1/FSMC_DA1,
EVENTOUT
FSMC_A12,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J12 87
PG2
PG3
PG4
PG5
PG6
PG7
PG8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A13,
EVENTOUT
J11
88
FSMC_A14,
EVENTOUT
J10 89
H12 90
H11 91
H10 92
G11 93
FSMC_A15,
EVENTOUT
QUADSPI_BK1_NCS,
EVENTOUT
USART6_CK,
EVENTOUT
USART6_RTS,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
94
-
VSS
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
F10
F1
C11 95
VDDUSB
TIM3_CH1, TIM8_CH1,
I2CFMP1_SCL,
I2S2_MCK,
DFSDM1_CKIN3,
DFSDM2_DATIN6,
USART6_TX,
-
37 D5 63 E12 G12 96
PC6
I/O
FTf
-
-
FSMC_D1/FSMC_DA1,
SDIO_D6, EVENTOUT
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM3_CH2, TIM8_CH2,
I2CFMP1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
DFSDM2_CKIN6,
-
38 D4 64
E11 F12 97
PC7
I/O
FTf
-
-
USART6_RX,
DFSDM1_DATIN3,
SDIO_D7, EVENTOUT
TIM3_CH3, TIM8_CH3,
DFSDM2_CKIN3,
-
-
39 E1 65 E10 F11 98
PC8
PC9
I/O
I/O
FT
FT
-
-
USART6_CK,
QUADSPI_BK1_IO2,
SDIO_D0, EVENTOUT
-
-
MCO_2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S2_CKIN,
DFSDM2_DATIN3,
QUADSPI_BK1_IO0,
SDIO_D1, EVENTOUT
40 E2 66 D12 E11 99
MCO_1, TIM1_CH1,
I2C3_SCL,
DFSDM1_CKOUT,
USART1_CK,
29 41 D3 67 D11 E12 100
PA8
I/O
FT
-
-
UART7_RX,
USB_FS_SOF,
CAN3_RX, SDIO_D1,
EVENTOUT
TIM1_CH2,
DFSDM2_CKIN3,
I2C3_SMBA,
30 42 D2 68 D10 D12 101
PA9
I/O
I/O
FT
FT
-
-
SPI2_SCK/I2S2_CK,
USART1_TX,
USB_FS_VBUS,
SDIO_D2, EVENTOUT
-
-
TIM1_CH3,
DFSDM2_DATIN3,
SPI2_MOSI/I2S2_SD,
SPI5_MOSI/I2S5_SD,
USART1_RX,
31 43 D1 69 C12 D11 102
PA10
USB_FS_ID,
EVENTOUT
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Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM1_CH4,
DFSDM2_CKIN5,
SPI2_NSS/I2S2_WS,
SPI4_MISO,
USART1_CTS,
USART6_TX,
CAN1_RX,
32 44 C3 70 B12 C12 103
PA11
I/O
FT
-
-
USB_FS_DM,
UART4_RX,
EVENTOUT
TIM1_ETR,
DFSDM2_DATIN5,
SPI2_MISO,
SPI5_MISO,
USART1_RTS,
USART6_RX,
CAN1_TX, USB_FS_DP,
UART4_TX, EVENTOUT
33 45 B3 71 A12 B12 104
PA12
PA13
I/O
I/O
FT
FT
-
-
-
-
JTMS-SWDIO,
EVENTOUT
34 46 C2 72
C1 73 C11 G9 106
35 47 B1 74 F11 G10 107
75 G11
A11 A12 105
-
-
VCAP_2
VSS
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
48
-
-
-
-
VDD
36
A1
-
-
F9 108
VDD
JTCK-SWCLK,
EVENTOUT
37 49 B2 76 A10 A11 109
PA14
PA15
I/O
FT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART1_TX,
38 50 A3 77
A9
A10 110
I/O
FT
-
-
UART7_TX,
SAI1_MCLK_A,
CAN3_TX, EVENTOUT
DFSDM2_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
-
51 A2 78
B11 B11 111
PC10
I/O
FT
-
-
QUADSPI_BK1_IO1,
SDIO_D2, EVENTOUT
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
DFSDM2_DATIN5,
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
FSMC_D2/FSMC_DA2,
SDIO_D3, EVENTOUT
-
-
52 C4 79 C10 B10 112
PC11
PC12
I/O
I/O
FT
FT
-
-
-
SPI3_MOSI/I2S3_SD,
USART3_CK,
53 B4 80 B10 C10 113
-
UART5_TX,
FSMC_D3/FSMC_DA3,
SDIO_CK, EVENTOUT
DFSDM2_CKIN6,
CAN1_RX, UART4_RX,
FSMC_D2/FSMC_DA2,
EVENTOUT
-
-
-
-
A4 81
NC 82
C9 E10 114
B9 D10 115
PD0
PD1
I/O
I/O
FT
FT
-
-
-
DFSDM2_DATIN6,
CAN1_TX, UART4_TX,
FSMC_D3/FSMC_DA3,
EVENTOUT
(2)
TIM3_ETR,
DFSDM2_CKOUT,
UART5_RX,
FSMC_NWE,
SDIO_CMD,
-
-
54 C5 83
C8
B8
E9 116
PD2
PD3
I/O
I/O
FT
FT
-
-
-
EVENTOUT
TRACED1,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
USART2_CTS,
QUADSPI_CLK,
FSMC_CLK,
(2)
-
NC 84
D9 117
EVENTOUT
DFSDM1_CKIN0,
USART2_RTS,
FSMC_NOE,
(2)
(2)
-
-
-
-
NC 85
NC 86
B7
A6
C9 118
B9 119
PD4
PD5
I/O
I/O
FT
FT
-
-
EVENTOUT
DFSDM2_CKOUT,
USART2_TX,
FSMC_NWE,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
E7 120
F7 121
VSS
VDD
S
S
-
-
-
-
-
-
-
-
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Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
SPI3_MOSI/I2S3_SD,
DFSDM1_DATIN1,
USART2_RX,
(2)
-
-
NC 87
B6
A8 122
PD6
I/O
FT
-
FSMC_NWAIT,
EVENTOUT
DFSDM1_CKIN1,
USART2_CK,
FSMC_NE1,
(2)
-
-
-
-
NC 88
A5
-
A9 123
E8 124
PD7
PG9
I/O
I/O
FT
FT
-
-
EVENTOUT
USART6_RX,
QUADSPI_BK2_IO2,
FSMC_NE2,
-
-
-
EVENTOUT
FSMC_NE3,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
D8 125
C8 126
PG10
PG11
I/O
I/O
FT
FT
-
-
-
-
CAN2_RX,
UART10_RX,
EVENTOUT
USART6_RTS,
CAN2_TX, UART10_TX,
FSMC_NE4,
-
-
-
-
-
-
-
-
-
-
B8 127
D7 128
PG12
PG13
I/O
I/O
FT
FT
-
-
-
-
EVENTOUT
TRACED2,
USART6_CTS,
FSMC_A24,
EVENTOUT
TRACED3,
USART6_TX,
-
-
-
-
-
C7 129
PG14
I/O
FT
-
QUADSPI_BK2_IO3,
FSMC_A25,
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
130
VSS
VDD
S
S
-
-
-
-
-
-
-
-
F6 131
B7 132
USART6_CTS,
EVENTOUT
-
-
-
-
-
PG15
I/O
FT
-
-
JTDO-SWO, TIM2_CH2,
I2CFMP1_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART1_RX,
39 55 A5 89
A8
A7 133
PB3
I/O
FTf
-
-
UART7_RX, I2C2_SDA,
SAI1_SD_A, CAN3_RX,
EVENTOUT
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Pinouts and pin description
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
JTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD,
UART7_TX, I2C3_SDA,
40 56 B5 90
A7
A6 134
PB4
I/O
FT
-
-
SAI1_SCK_A,
CAN3_TX, SDIO_D0,
EVENTOUT
LPTIM1_IN1,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
41 57 A6 91
C5
B6 135
PB5
I/O
FT
-
-
CAN2_RX, SAI1_FS_A,
UART5_RX, SDIO_D3,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1, I2C1_SCL,
DFSDM2_CKIN7,
42 58 B6 92
B5
C6 136
PB6
I/O
FT
-
USART1_TX,CAN2_TX,
QUADSPI_BK1_NCS,
UART5_TX, SDIO_D0,
EVENTOUT
-
LPTIM1_IN2,
TIM4_CH2, I2C1_SDA,
DFSDM2_DATIN7,
USART1_RX,
43 59 B7 93
44 60 A7 94
B4
A4
D6 137
D5 138
PB7
I/O
I
FT
B
-
-
-
FSMC_NL, EVENTOUT
BOOT0
-
VPP
LPTIM1_OUT,
TIM4_CH3, TIM10_CH1,
I2C1_SCL,
SPI5_MOSI/I2S5_SD,
DFSDM2_CKIN1,
CAN1_RX, I2C3_SDA,
UART5_RX, SDIO_D4,
EVENTOUT
45 61 C6 95
A3
C5 139
PB8
I/O
FT
-
-
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
DFSDM2_DATIN1,
CAN1_TX, I2C2_SDA,
UART5_TX, SDIO_D5,
EVENTOUT
46 62 D6 96
B3
B5 140
PB9
I/O
FT
-
-
DocID029162 Rev 5
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Pinouts and pin description
STM32F413xG/H
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
Pin
I/O
Additional
functions
Notes Alternate functions
type structure
reset)(1)
TIM4_ETR,
DFSDM2_CKIN4,
UART8_Rx,
FSMC_NBL0,
EVENTOUT
(2)
(2)
-
-
-
-
NC 97
C3
A2
A5 141
A4 142
PE0
PE1
I/O
I/O
FT
FT
-
-
DFSDM2_DATIN4,
UART8_Tx,
FSMC_NBL1,
EVENTOUT
NC 98
47 63 A8 99
B8
D3
H3
E6
-
VSS
PDR_ON
VDD
S
I
-
FT
-
-
-
-
-
-
-
-
-
-
-
-
-
E5 143
F5 144
48 64 A9 100 C4
S
1. Function availability depends on the chosen device.
2. NC (Not Connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid extra power consumption in low power mode.
3. Compatibility issue on alternate function pin PE4 SAI1_SD_A and PE6 SAI1_FS_A: Pins have been swapped versus other
MCUs supporting those alternate SAI functions on those pins
4. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F413/423 reference manual.
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
7. Incompatibility issue on alternate function with other MCUs supporting UART4: UART4_TX wrongly mapped to PD10
instead of PC10
Table 11. FSMC pin definition
FSMC
Pins
64 pins
81 pins 100 pins 144 pins
NOR/PSRAM
Mux
LCD/NOR/
PSRAM/SRAM
PE2
A23
A19
A20
A21
A22
A0
A23
A19
A20
A21
A22
-
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
PE3
PE4
PE5
PE6
PF0
64/207
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Pinouts and pin description
Table 11. FSMC pin definition (continued)
FSMC
Pins
64 pins
81 pins 100 pins 144 pins
NOR/PSRAM
Mux
LCD/NOR/
PSRAM/SRAM
PF1
A1
A2
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PF2
-
-
-
PF3
A3
-
-
-
-
PF4
A4
-
-
-
-
PF5
A5
-
-
-
-
PC2
PC3
PA2
NWE
A0
NWE
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
D4
DA4
DA5
DA6
DA7
NE4
NOE
-
Yes
PA3
D5
Yes
PA4
D6
Yes
PA5
D7
Yes
PC4
PC5
PF12
PF13
PF14
PF15
PG0
PG1
PE7
NE4
NOE
A6
Yes
Yes
-
A7
-
-
-
-
A8
-
-
-
-
A9
-
-
-
-
A10
A11
D4
-
-
-
-
-
-
-
-
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA0
DA13
DA14
DA15
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
PE8
D5
-
-
PE9
D6
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
PE10
PE11
PE12
PE13
PE14
PE15
PB12
PB14
PD8
PD9
PD10
D7
-
D8
-
D9
-
D10
D11
D12
D13
D0
-
-
-
Yes
Yes
D13
D14
D15
-
-
-
Yes
Yes
Yes
Yes
DocID029162 Rev 5
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73
Pinouts and pin description
STM32F413xG/H
Table 11. FSMC pin definition (continued)
FSMC
Pins
64 pins
81 pins 100 pins 144 pins
NOR/PSRAM
Mux
LCD/NOR/
PSRAM/SRAM
PD11
PD12
PD13
PD14
PD15
PG2
PG3
PG4
PG5
PC6
A16
A17
A18
D0
A16
A17
A18
DA0
DA1
-
-
-
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
D1
-
-
A12
A13
A14
A15
D1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DA1
DA2
DA3
DA2
DA3
NWE
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
NE4
A24
A25
NL
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
PC11
PC12
PD0
D2
Yes
Yes
D3
Yes
Yes
D2
-
Yes
PD1
D3
-
-
PD2
NWE
CLK
NOE
NWE
NWAIT
NE1
NE2
NE3
NE4
A24
A25
NL
Yes
Yes
PD3
-
-
PD4
-
-
PD5
-
-
PD6
-
-
PD7
-
-
PG9
PG10
PG12
PG13
PG14
PB7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
PE0
NBL0
NBL1
NBL0
NBL1
-
-
-
-
PE1
66/207
DocID029162 Rev 5
4.9
Alternate functions
Table 12. STM32F413xG/H alternate functions
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
TIM2_CH1/
TIM2_
TIM5_
CH1
USART2_
CTS
UART4_
TX
EVENT
OUT
PA0
-
TIM8_ETR
-
-
-
-
-
-
-
-
-
-
ETR
TIM5_
CH2
SPI4_MOSI/I
2S4_SD
USART2_
RTS
UART4_
RX
QUADSPI_
BK1_IO3
EVENT
OUT
PA1
PA2
PA3
PA4
-
-
-
-
TIM2_CH2
TIM2_CH3
TIM2_CH4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM5_
CH3
USART2_
TX
FSMC_D4/
FSMC_DA4
EVENT
OUT
TIM9_CH1
TIM9_CH2
-
I2S2_CKIN
I2S2_MCK
-
-
-
-
-
-
TIM5_
CH4
USART2_
RX
FSMC_D5/
FSMC_DA5
EVENT
OUT
SAI1_SD_B
-
SPI1_NSS/I2 SPI3_NSS/I USART2_
DFSDM1_
DATIN1
FSMC_D6/
FSMC_DA6
EVENT
OUT
-
-
S1_WS
2S3_WS
CK
-
TIM2_CH1/
TIM2_
SPI1_SCK/I2
S1_CK
DFSDM1_
CKIN1
FSMC_D7/
FSMC_DA7
EVENT
OUT
PA5
-
TIM8_CH1N
TIM8_BKIN
-
-
-
-
-
-
-
ETR
TIM1_
BKIN
TIM3_
CH1
DFSDM2_
CKIN1
TIM13_
CH1
QUADSPI_B
K2_IO0
SDIO_
CMD
EVENT
OUT
PA6
PA7
-
-
-
-
SPI1_MISO I2S2_MCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
CH1N
TIM3_
CH2
TIM8_
CH1N
SPI1_MOSI/I
2S1_SD
DFSDM2_
DATIN1
TIM14_
CH1
QUADSPI_B
K2_IO1
EVENT
OUT
-
-
I2C3_
SCL
DFSDM1_
CKOUT
USART1_
CK
UART7_
RX
USB_FS_
SOF
CAN3_
RX
SDIO_
D1
EVENT
OUT
PA8 MCO_1 TIM1_CH1
-
-
-
-
-
-
-
-
-
-
DFSDM2_
CKIN3
I2C3_
SMBA
SPI2_SCK/I2
S2_CK
USART1_
TX
USB_FS_
VBUS
SDIO_
D2
EVENT
OUT
PA9
-
-
-
-
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_ETR
-
-
-
-
-
-
-
DFSDM2_
DATIN3
SPI2_MOSI/I SPI5_MOSI/ USART1_
USB_FS_
ID
EVENT
OUT
PA10
PA11
PA12
PA13
PA14
-
-
-
-
-
-
-
-
-
-
-
2S2_SD
I2S5_SD
RX
DFSDM2_
CKIN5
SPI2_NSS/I2
S2_WS
USART1_
CTS
USART6_
TX
USB_FS_
DM
UART4_
RX
EVENT
OUT
SPI4_MISO
CAN1_RX
DFSDM2_
DATIN5
USART1_
RTS
USART6_
RX
USB_FS_
DP
UART4_
TX
EVENT
OUT
SPI2_MISO SPI5_MISO
CAN1_TX
JTMS-
SWDIO
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK-
SWCLK
EVENT
OUT
-
TIM2_CH1/
TIM2_
SPI1_NSS/ SPI3_NSS/
I2S1_WS I2S3_WS
USART1_
TX
UART7_
TX
SAI1_
MCLK_A
CAN3_
TX
EVENT
OUT
PA15
JTDI
-
-
-
-
-
-
-
ETR
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
TIM1_
CH2N
TIM3_
CH3
TIM8_
CH2N
SPI5_SCK/I
2S5_CK
EVENT
OUT
PB0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
CH3N
TIM3_
CH4
TIM8_
CH3N
SPI5_NSS/
I2S5_WS
DFSDM1_ QUADSPI_C
DATIN0
EVENT
OUT
PB1
PB2
PB3
-
-
LK
LPTIM1_
OUT
DFSDM1_
CKIN0
QUADSPI_C
LK
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
JTDO-
SWO
I2CFMP1 SPI1_SCK/I2 SPI3_SCK/I USART1_
UART7_
RX
CAN3_
RX
EVENT
OUT
TIM2_CH2
-
I2C2_SDA
I2C3_SDA
CAN2_RX
CAN2_TX
-
SAI1_SD_A
-
_SDA
S1_CK
2S3_CK
RX
TIM3_
CH1
I2S3ext_
SD
UART7_
TX
SAI1_SCK_ CAN3_
EVENT
OUT
PB4 JTRST
-
SPI1_MISO SPI3_MISO
SPI1_MOSI/I SPI3_MOSI/
SDIO_D0
SDIO_D3
SDIO_D0
FSMC_NL
SDIO_D4
SDIO_D5
SDIO_D7
-
A
TX
LPTIM1_
IN1
TIM3_
CH2
I2C1_
SMBA
UART5_
RX
EVENT
OUT
PB5
PB6
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_FS_A
2S1_SD
I2S3_SD
LPTIM1_
ETR
TIM4_
CH1
DFSDM2_
CKIN7
USART1_
TX
QUADSPI_ UART5_
BK1_NCS
EVENT
OUT
I2C1_SCL
-
-
TX
LPTIM1_
IN2
TIM4_
CH2
I2C1_
SDA
DFSDM2_
DATIN7
USART1_
RX
EVENT
OUT
PB7
-
-
-
-
-
LPTIM1_
OUT
TIM4_
CH3
TIM10_
CH1
I2C1_
SCL
SPI5_MOSI/ DFSDM2_
I2S5_SD
UART5_
RX
EVENT
OUT
PB8
CAN1_RX
I2C3_SDA
I2C2_SDA
-
-
CKIN1
TIM4_
CH4
TIM11_
CH1
I2C1_
SDA
SPI2_NSS/I2 DFSDM2_
UART5_
TX
EVENT
OUT
PB9
-
-
CAN1_TX
S2_WS
DATIN1
I2C2_
SCL
SPI2_SCK/I2
S2_CK
USART3_
TX
I2CFMP1_
SCL
DFSDM2_
CKOUT
EVENT
OUT
PB10
PB11
PB12
PB13
PB14
PB15
TIM2_CH3
TIM2_CH4
-
-
-
-
-
-
-
-
-
-
I2S3_MCK
-
-
-
-
I2C2_
SDA
USART3_
RX
EVENT
OUT
I2S2_CKIN
-
-
-
TIM1_
BKIN
I2C2_
SMBA
SPI2_NSS/I2 SPI4_NSS/ SPI3_SCK/ USART3_
DFSDM1_ UART5_ FSMC_D13/F
DATIN1
EVENT
OUT
CAN2_RX
CAN2_TX
TIM12_CH1
TIM12_CH2
S2_WS
I2S4_WS
I2S3_CK
CK
RX
SMC_DA13
TIM1_
CH1N
I2CFMP1 SPI2_SCK/I2 SPI4_SCK/
USART3_
CTS
DFSDM1_ UART5_
CKIN1
EVENT
OUT
-
-
_SMBA
S2_CK
I2S4_CK
TX
-
TIM1_
CH2N
TIM8_
CH2N
I2CFMP1
_SDA
USART3_
RTS
DFSDM1_
DATIN2
FSMC_D0/
FSMC_DA0
EVENT
OUT
SPI2_MISO I2S2ext_SD
SDIO_D6
SDIO_CK
RTC_
REFIN
TIM1_
CH3N
TIM8_
CH3N
I2CFMP1 SPI2_MOSI/I
_SCL 2S2_SD
DFSDM1_
CKIN2
EVENT
OUT
-
-
-
-
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
LPTIM1_
IN1
DFSDM2_CK
SAI1_
MCLK_B
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IN4
LPTIM1_
OUT
DFSDM2_DA
TIN4
EVENT
OUT
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
SAI1_SD_B
-
LPTIM1_IN
2
DFSDM2_DA
TIN7
SAI1_SCK_ DFSDM1_
EVENT
OUT
SPI2_MISO I2S2ext_SD
FSMC_NWE
FSMC_A0
FSMC_NE4
FSMC_NOE
SDIO_D6
SDIO_D7
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_CK
-
B
CKOUT
LPTIM1_
ETR
DFSDM2_CK
IN7
SPI2_MOSI/I
2S2_SD
EVENT
OUT
-
SAI1_FS_B
-
DFSDM2_CK
IN2
QUADSPI_
BK2_IO2
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
I2S1_MCK
-
-
-
-
-
-
DFSDM2_DA I2CFMP1
USART3_
RX
QUADSPI_
BK2_IO3
EVENT
OUT
TIN2
_SMBA
TIM3_
CH1
I2CFMP1
_SCL
DFSDM1_
CKIN3
DFSDM2_
DATIN6
USART6_
TX
FSMC_D1/
FSMC_DA1
EVENT
OUT
TIM8_CH1
I2S2_MCK
TIM3_
CH2
I2CFMP1 SPI2_SCK/
_SDA
DFSDM2_
CKIN6
USART6_
RX
DFSDM1_
DATIN3
EVENT
OUT
TIM8_CH2
TIM8_CH3
TIM8_CH4
I2S3_MCK
I2S2_CK
TIM3_
CH3
DFSDM2_
CKIN3
USART6_
CK
QUADSPI_
BK1_IO2
EVENT
OUT
-
-
-
-
-
-
-
TIM3_
CH4
I2C3_
SDA
DFSDM2_
DATIN3
QUADSPI_
BK1_IO0
EVENT
OUT
PC9 MCO_2
I2S2_CKIN
-
-
-
DFSDM2_
CKIN5
SPI3_SCK/
I2S3_CK
USART3_
TX
QUADSPI_
BK1_IO1
EVENT
OUT
PC10
PC11
PC12
PC13
PC14
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM2_
DATIN5
USART3_
RX
UART4_
RX
QUADSPI_
BK2_NCS
FSMC_D2/
FSMC_DA2
EVENT
OUT
I2S3ext_SD SPI3_MISO
SPI3_MOSI/ USART3_
UART5_
TX
FSMC_D3/F
SMC_DA3
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
I2S3_SD
CK
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
-
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
DFSDM2_
CKIN6
UART4_
RX
FSMC_D2/
FSMC_DA2
EVENT
OUT
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_RX
CAN1_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM2_
DATIN6
UART4_
TX
FSMC_D3/
FSMC_DA3
EVENT
OUT
PD1
PD2
TIM3_
ETR
DFSDM2_
CKOUT
UART5_
RX
FSMC_
NWE
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
SDIO_CMD
FSMC_CLK
TRACE
D1
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN0
USART2_
CTS
QUADSPI_
CLK
EVENT
OUT
PD3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM1_
CKIN0
USART2_
RTS
FSMC_
NOE
EVENT
OUT
PD4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM2_
CKOUT
USART2_
TX
FSMC_
NWE
EVENT
OUT
PD5
-
SPI3_MOSI/ DFSDM1_
I2S3_SD
USART2_
RX
FSMC_
NWAIT
EVENT
OUT
PD6
-
-
-
-
-
DATIN1
DFSDM1_
CKIN1
USART2_
CK
EVENT
OUT
PD7
-
FSMC_NE1
USART3_
TX
FSMC_D13/F
SMC_DA13
EVENT
OUT
PD8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_
RX
FSMC_D14/F
SMC_DA14
EVENT
OUT
PD9
USART3_
CK
UART4_
TX
FSMC_D15/F
SMC_DA15
EVENT
OUT
PD10
PD11
PD12
PD13
PD14
PD15
DFSDM2_
DATIN2
I2CFMP1
_SMBA
USART3_
CTS
QUADSPI_
BK1_IO0
EVENT
OUT
-
-
-
-
-
FSMC_A16
FSMC_A17
FSMC_A18
TIM4_
CH1
DFSDM2_
CKIN2
I2CFMP1
_SCL
USART3_
RTS
QUADSPI_
BK1_IO1
EVENT
OUT
TIM4_
CH2
I2CFMP1
_SDA
QUADSPI_
BK1_IO3
EVENT
OUT
-
-
-
-
-
-
TIM4_
CH3
I2CFMP1
_SCL
DFSDM2_ UART9_
CKIN0 RX
FSMC_D0/
FSMC_DA0
EVENT
OUT
-
-
TIM4_
CH4
I2CFMP1
_SDA
DFSDM2_ UART9_
DATIN0 TX
FSMC_D1/
FSMC_DA1
EVENT
OUT
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
TIM4_
ETR
DFSDM2_
CKIN4
UART8_
Rx
FSMC_
NBL0
EVENT
OUT
PE0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DFSDM2_
DATIN4
UART8_
Tx
FSMC_
NBL1
EVENT
OUT
PE1
PE2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE
CLK
SPI4_SCK
/I2S4_CK
SPI5_SCK/
I2S5_CK
SAI1_
MCLK_A
QUADSPI_
BK1_IO2
UART10
FSMC_A23
_RX
EVENT
OUT
-
-
-
-
TRACE
D0
UART10
FSMC_A19
_TX
EVENT
OUT
PE3
-
-
-
-
SAI1_SD_B
SAI1_SD_A
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACE
D1
SPI4_NSS/ SPI5_NSS/
I2S4_WS I2S5_WS
DFSDM1_
DATIN3
EVENT
OUT
PE4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A20
FSMC_A21
FSMC_A22
TRACE
D2
SAI1_SCK_ DFSDM1_
EVENT
OUT
PE5
-
TIM9_CH1
SPI4_MISO SPI5_MISO
A
CKIN3
TRACE
D3
SPI4_MOSI/I SPI5_MOSI/
EVENT
OUT
PE6
-
TIM9_CH2
SAI1_FS_A
-
2S4_SD
-
I2S5_SD
DFSDM1_
DATIN2
UART7_
Rx
QUADSPI_
BK2_IO0
FSMC_D4/
FSMC_DA4
EVENT
OUT
PE7
-
-
-
-
-
-
-
-
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
CH1N
DFSDM1_
CKIN2
UART7_
Tx
QUADSPI_
BK2_IO1
FSMC_D5/
FSMC_DA5
EVENT
OUT
PE8
-
-
-
DFSDM1_
CKOUT
QUADSPI_
BK2_IO2
FSMC_D6/
FSMC_DA6
EVENT
OUT
PE9
TIM1_CH1
-
-
-
-
-
-
-
TIM1_
CH2N
DFSDM2_
DATIN0
QUADSPI_
BK2_IO3
FSMC_D7/
FSMC_DA7
EVENT
OUT
PE10
PE11
PE12
PE13
PE14
PE15
-
TIM1_
CH2
DFSDM2_
CKIN0
SPI4_NSS/ SPI5_NSS/
I2S4_WS I2S5_WS
FSMC_D8/
FSMC_DA8
EVENT
OUT
-
-
-
TIM1_
CH3N
DFSDM2_
DATIN7
SPI4_SCK/ SPI5_SCK/
I2S4_CK I2S5_CK
FSMC_D9/
FSMC_DA9
EVENT
OUT
TIM1_
CH3
DFSDM2_
CKIN7
FSMC_D10/
FSMC_DA10
EVENT
OUT
SPI4_MISO SPI5_MISO
SPI4_MOSI/I SPI5_MOSI/
TIM1_
CH4
DFSDM2_
DATIN1
FSMC_D11/
FSMC_DA11
EVENT
OUT
-
-
2S4_SD
I2S5_SD
TIM1_
BKIN
DFSDM2_
CKIN1
FSMC_D12/F
SMC_DA12
EVENT
OUT
-
-
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
I2C2_
SDA
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_
SCL
EVENT
OUT
PF1
PF2
-
-
-
FSMC_A1
I2C2_
SMBA
EVENT
OUT
-
-
-
FSMC_A2
TIM5_
CH1
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A3
TIM5_
CH2
EVENT
OUT
PF4
-
-
-
FSMC_A4
TIM5_
CH3
EVENT
OUT
PF5
-
-
-
FSMC_A5
TRACE
D0
UART7_
Rx
QUADSPI_
BK1_IO3
EVENT
OUT
PF6
-
-
-
-
-
TIM10_CH1
SAI1_SD_B
-
TRACE
D1
SAI1_
MCLK_B
UART7_
Tx
QUADSPI_
BK1_IO2
EVENT
OUT
PF7
-
TIM11_CH1
-
SAI1_SCK_
B
QUADSPI_B
K1_IO0
EVENT
OUT
PF8
-
-
-
-
-
-
-
-
-
-
UART8_RX TIM13_CH1
-
UART8_
TIM14_CH1
TX
QUADSPI_B
K1_IO1
EVENT
OUT
PF9
-
-
SAI1_FS_B
-
TIM5_
CH4
EVENT
OUT
PF10
PF11
PF12
PF13
PF14
PF15
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
TIM8_ETR
-
EVENT
OUT
TIM8_BKIN
FSMC_A6
FSMC_A7
FSMC_A8
FSMC_A9
I2CFMP1
_SMBA
EVENT
OUT
-
-
-
I2CFMP1
_SCL
EVENT
OUT
I2CFMP1
_SDA
EVENT
OUT
Table 12. STM32F413xG/H alternate functions (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13 AF14 AF15
SPI3/I2S3/
SAI1/
DFSDM2/ USART3/4/
USART1/
USART2/
USART3
SAI1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
UART4/
UART5/
UART9/ FSMC /SDIO
UART10
SPI1/I2S1/
I2C1/2/3/ SPI2/I2S2/
TIM8/9/10/11 I2CFMP1 SPI3/I2S3/
SPI4/I2S4
DFSDM1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
Port
SYS_
AF
TIM1/2/
LPTIM1
DFSDM2/
SYS_
AF
TIM3/4/5
-
RNG
5/6/7/8/
CAN1
/CAN3
/OTG1_FS
UART9_
FSMC_A10
RX
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART9_
FSMC_A11
TX
EVENT
OUT
PG1
PG2
CAN1_TX
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FSMC_A12
EVENT
OUT
PG3
FSMC_A13
EVENT
OUT
PG4
FSMC_A14
EVENT
OUT
PG5
FSMC_A15
QUADSPI_B
K1_NCS
EVENT
OUT
PG6
-
USART6_
CK
EVENT
OUT
PG7
-
-
-
-
-
-
-
-
-
-
-
-
USART6_
RTS
EVENT
OUT
PG8
-
USART6_
RX
QUADSPI_
BK2_IO2
EVENT
OUT
PG9
FSMC_NE2
EVENT
OUT
PG10
PG11
PG12
PG13
PG14
PG15
PH0
-
-
-
FSMC_NE3
UART10
_RX
EVENT
OUT
CAN2_RX
CAN2_TX
-
-
USART6_
RTS
UART10
_TX
EVENT
OUT
FSMC_NE4
TRACE
D2
USART6_
CTS
EVENT
OUT
-
-
-
-
-
FSMC_A24
TRACE
D3
USART6_
TX
QUADSPI_
BK2_IO3
EVENT
OUT
FSMC_A25
USART6_
CTS
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
EVENT
OUT
PH1
Memory mapping
STM32F413xG/H
5
Memory mapping
The memory map is shown in Figure 18.
Figure 18. Memory map
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DocID029162 Rev 5
STM32F413xG/H
Memory mapping
Table 13. STM32F413xG/H register boundary addresses
Bus
Boundary address
Peripheral
0xE010 0000 - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xA000 2000 - 0xDFFF FFFF
0xA000 1000 - 0xA000 1FFF
0xA000 0000 - 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x7000 0000 - 0x08FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00 - 0x5FFF FFFF
0x5006 0800 0x5006 0BFF
0x5004 0000 - 0x5006 07FF
0x5000 0000 - 0x5003 FFFF
0x4002 6800 - 0x4FFF FFFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0x4002 4000 - 0X4002 5FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0x4002 3400 - 0x4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2000 - 0x4002 2FFF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0x4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
®
Cortex -M4
Cortex-M4 internal peripherals
Reserved
QuadSPI control register
FSMC control register
QUADSPI
Reserved
FSMC
AHB3
Reserved
RNG
AHB2
Reserved
USB OTG FS
Reserved
DMA2
DMA1
Reserved
Flash interface register
RCC
Reserved
CRC
AHB1
Reserved
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
DocID029162 Rev 5
75/207
77
Memory mapping
STM32F413xG/H
Table 13. STM32F413xG/H register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4001 6800- 0x4001 FFFF
0x4001 6400 - 0x4001 67FF
0x4001 6000 - 0x4001 63FF
0x4001 5C00 - 0x4001 5FFF
0x4001 5800 - 0x4001 5BFF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1C00 - 0x4001 1FFF
0x4001 1800 - 0x4001 1BFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Reserved
DFSDM2
DFSDM1
Reserved
SAI1
Reserved
SPI5/I2S5
Reserved
TIM11
TIM10
TIM9
EXTI
APB2
SYSCFG
SPI4/I2S4
SPI1/I2S1
SDIO
Reserved
ADC1/2/3
UART10
UART9
USART6
USART1
Reserved
TIM8
TIM1
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Memory mapping
Table 13. STM32F413xG/H register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4000 8000 - 0x4000 FFFF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00- 0x4000 6FFF
0x4000 6800- 0x4000 6BFF
0x4000 6400- 0x4000 67FF
0x4000 6000- 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
UART8
UART7
DAC1
PWR
CAN3
CAN2
CAN1
I2CFMP1
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
IWDG
APB1
WWDG
RTC & BKP Registers
LPTIM1
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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Electrical characteristics
STM32F413xG/H
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 19.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions
Figure 20. Input voltage measurement
-#5 PIN
-#5 PIN
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-3ꢀꢂꢁꢀꢁ6ꢉ
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Electrical characteristics
6.1.6
Power supply scheme
Figure 21. Power supply scheme
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1. To connect PDR_ON pin, refer to Section: Power supply supervisor.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on 100-pin and 144-pin packages.
4. VDDA=VDD and VSSA=VSS
.
5. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and
associated DP/DM GPIOs. VDDUSB value does not depend on the VDD and VDDA values, but it must be the
last supply to be provided and the first to disappear.
Caution:
Each power supply pair (for example V /V , V
/V
) must be decoupled with filtering
DD SS
DDA SSA
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure good operation of
the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
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Electrical characteristics
STM32F413xG/H
6.1.7
Current consumption measurement
Figure 22. Current consumption measurement scheme
,
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6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 14. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD
,
VDD–VSS
–0.3
4.0
(1)
VDDUSB and VBAT
)
Input voltage on FT and TC pins(2)
VSS–0.3 VDD+4.0
V
Input voltage on TTa pins
V
SS–0.3
4.0
4.0
9.0
50
VIN
Input voltage on any other pin
Input voltage for BOOT0
VSS–0.3
VSS
-
|ΔVDDx
|
Variations between different VDD power pins
mV
Variations between all the different ground pins
including VREF-
|VSSX −VSS
|
-
50
see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
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Symbol
Electrical characteristics
Table 15. Current characteristics
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
Σ IVDDUSB
IVDD
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Total current into VDDUSB power lines (source)
180
-180
25
Maximum current into each VDD_x power line (source)(1)
Maximum current out of each VSS_x ground line (sink)(1)
Output current sunk by any I/O and control pin
100
-100
25
IVSS
IIO
Output current sourced by any I/O and control pin
Total output current sunk by sum of all I/O and control pins (2)
Total output current sunk by sum of all USB I/Os
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT and TC pins (4)
-25
mA
120
25
ΣIIO
-120
– 5/ + 0
Injected current on NRST and B pins (4)
(3)
IINJ(PIN)
Injected current on TTa pins(5)
± 5
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply,
in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. A positive injection is induced by VIN>VDDA in the same time a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
125
Maximum junction temperature
°C
Maximum lead temperature during soldering
(WLCSP81, LQFP64/100/144, UFQFPN48,
UFBGA100/144)
TLEAD
see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).
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6.3
Operating conditions
6.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power Scale3: Regulator ON,
VOS[1:0] bits in PWR_CR
register = 0x01
0
-
64
Power Scale2: Regulator ON,
VOS[1:0] bits in PWR_CR
register = 0x10
Internal AHB clock
frequency
fHCLK
0
-
84
MHz
Power Scale1: Regulator ON,
VOS[1:0] bits in PWR_CR
register = 0x11
0
0
-
-
100
50
Internal APB1 clock
frequency
fPCLK1
-
MHz
Internal APB2 clock
frequency
fPCLK2
VDD
-
-
0
-
-
100
3.6
MHz
V
Standard operating voltage
1.7(1)
Analog operating voltage
1.7(1)
-
-
2.4
3.6
(ADC limited to 1.2 M
samples)
(2)(3)
(4)
VDDA
Must be the same potential as VDD
V
Analog operating voltage
2.4
(ADC limited to 2.4 M
samples)
USB supply voltage
VDDUSB (supply voltage for PA11 and
PA12 pins)
USB not used
1.7
3.0
3.3
3.6
3.6
3.6
V
V
USB used(5)
-
-
VBAT
Backup operating voltage
-
1.65
VOS[1:0] bits in PWR_CR
register = 0x01
1.08(6) 1.14
1.20(6) 1.26
1.26 1.32
1.20(6)
1.32(6)
1.38
Max frequency 64 MHz
Regulator ON: 1.2 V
VOS[1:0] bits in PWR_CR
register = 0x10
V12
V
V
internal voltage on
VCAP_1/VCAP_2 pins
Max frequency 84 MHz
VOS[1:0] bits in PWR_CR
register = 0x11
Max frequency 100 MHz
Max frequency 64 MHz
Max frequency 84 MHz
Max frequency 100 MHz
1.10 1.14
1.20 1.26
1.26 1.32
1.20
1.32
1.38
Regulator OFF: 1.2 V
external voltage must be
supplied on
V12
VCAP_1/VCAP_2 pins
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Symbol
Electrical characteristics
Table 17. General operating conditions (continued)
Parameter
Conditions
2 V ≤ VDD ≤ 3.6 V
Min
Typ
Max
Unit
–0.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
5.2
Input voltage on
RST, FT and TC pins(7)
VDD ≤ 2 V
–0.3
VIN
V
Input voltage on TTa pins
-
-
- 0.3
VDDA + 0.3
9
Input voltage on BOOT0 pin
0
-
UFQFPN48
WLCSP81
LQFP64
625
504
426
465
571
351
417
156
126
106
116
-
-
Power dissipation at
TA = 85°C for range 6 or
LQFP100
LQFP144
UFBGA100
UFBGA144
UFQFPN48
WLCSP81
LQFP64
-
TA = 105°C for range 7(8)
-
-
PD
mW
-
-
-
Power dissipation at
LQFP100
LQFP144
UFBGA100
UFBGA144
-
TA = 125°C for range 3(8)
-
143
088
104
85
-
-
Maximum power dissipation
Low power dissipation(9)
Maximum power dissipation
Low power dissipation(9)
Maximum power dissipation
Low power dissipation(9)
Range 6
–40
–40
–40
–40
–40
–40
–40
–40
–40
Ambient temperature for
range 6
105
105
125
125
130
105
125
130
Ambient temperature for
range 7
TA
TJ
°C
Ambient temperature for
range 3
Junction temperature range Range 7
Range 3
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 75: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
V
DDA can be tolerated during power-up and power-down operation.
5. Only the DM (PA11) and DP (PA12) pads are supplied through VDDUSB. For application where the VBUS (PA9) is directly
connected to the chip, a minimum VDD supply of 2.7V is required.
(some application examples are shown in appendix B)
6. Guaranteed by test in production
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
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8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
Table 18. Features depending on the operating power supply range
Maximum
Flash
Operating
power
supply
range
memory
access
frequency
Maximum Flash
memory access
frequency with
Possible
Flash
memory
operations
Clock output
frequency on
I/O pins(3)
ADC
operation
I/O operation
with no wait wait states (1)(2)
states
(fFlashmax
)
8-bit erase
and program
operations
only
Conversion
time up to
1.2 Msps
VDD =1.7 to
2.1 V(4)
100 MHz with 6 – No I/O
wait states compensation
16 MHz(5)
up to 30 MHz
up to 30 MHz
Conversion
time up to
1.2 Msps
16-bit erase
and program
operations
VDD = 2.1 to
2.4 V
100 MHz with 5 – No I/O
18 MHz
20 MHz
wait states
compensation
Conversion
time up to
2.4 Msps
– I/O
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
100 MHz with 4
wait states
compensation up to 50 MHz
works
– up to
100 MHz
when VDD
3.0 to 3.6 V
=
Conversion
time up to
2.4 Msps
– I/O
compensation
works
32-bit erase
and program
operations
VDD = 2.7 to
3.6 V(6)
100 MHz with 3
wait states
25 MHz
– up to
50 MHz
when VDD
=
2.7 to 3.0 V
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. Refer to Table 61: I/O AC characteristics for frequencies vs. external load.
4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.17.2: Internal
reset OFF).
5. Prefetch available over the complete VDD supply range.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.
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6.3.2
VCAP_1/VCAP_2 external capacitors
Stabilization for the main regulator is achieved by connecting the external capacitor C
to
EXT
the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT
capacitors are replaced by a single capacitor.
C
is specified in Table 19.
EXT
Figure 23. External capacitor C
EXT
&
(65
5ꢉ/HDN
06ꢈꢊꢃꢇꢇ9ꢄ
1. Legend: ESR is the equivalent series resistance.
(1)
Table 19. VCAP_1/VCAP_2 operating conditions
Parameter
Symbol
Conditions
Capacitance of external capacitor with the pins
VCAP_1 and VCAP_2 available
CEXT
2.2 µF
< 2 Ω
4.7 µF
< 1 Ω
ESR of external capacitor with the pins VCAP_1 and
VCAP_2 available
ESR
CEXT
ESR
Capacitance of external capacitor with a single VCAP
pin available
ESR of external capacitor with a single VCAP pin
available
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3
Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 20. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Min
Max
Unit
20
20
∞
∞
tVDD
µs/V
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6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 21. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up
VCAP_1 and VCAP_2 fall time rate Power-down
tVCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Note:
This feature is only available for UFBGA100 and UFBGA144 packages.
6.3.5
Embedded reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V supply voltage @ 3.3V.
DD
Table 22. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
-
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
V
2.76 2.82
Programmable voltage
detector level selection
VPVD
2.66 2.71
2.93 2.99
2.84 3.02
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
(2)
VPVDhyst
PVD hysteresis
100
-
mV
V
1.60(1)
1.64
Falling edge
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
Rising edge
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Electrical characteristics
Table 22. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ Max Unit
(2)
VPDRhyst
PDR hysteresis
-
-
40
-
mV
Falling edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Brownout level 2
threshold
VBOR2
V
Brownout level 3
threshold
VBOR3
(2)
VBORhyst
BOR hysteresis
POR reset timing
-
-
100
1.5
-
mV
ms
TRSTTEMPO
0.5
3.0
(2)(3)
In-Rush current on
voltage regulator power-
on (POR or wakeup from
Standby)
(2)
IRUSH
-
-
160
-
200
5.4
mA
µC
In-Rush energy on
voltage regulator power-
on (POR or wakeup from IRUSH = 171 mA for 31 µs
Standby)
VDD = 1.7 V, TA = 125 °C,
(2)
ERUSH
-
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design.
3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is fetched by the user application code.
6.3.6
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
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Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to both f frequency and VDD ranges
HCLK
(refer to Table 18: Features depending on the operating power supply range).
•
The voltage scaling is adjusted to f frequency as follows:
HCLK
–
–
–
Scale 3 for f
≤ 64 MHz
HCLK
Scale 2 for 64 MHz < f
Scale 1 for 84 MHz < f
≤ 84 MHz
≤ 100 MHz
HCLK
HCLK
•
•
•
The system clock is HCLK, f
= f
/2, and f
= f
.
PCLK1
HCLK
PCLK2
HCLK
External clock is 4 MHz and PLL is ON except if it is explicitly mentioned.
The maximum values are obtained for V = 3.6 V and a maximum ambient
DD
temperature (T ), and the typical values for T = 25 °C and V = 3.3 V unless
A
A
DD
otherwise specified.
Table 23. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 1.7 V
DD
Typ
TA= 25 °C TA= 25 °C TA=85 °C TA=105 °C TA=125 °C
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Unit
100
84
64
50
25
20
16
32.9
26.5
18.3
14.4
7.5
34.96
28.13
19.44
15.28
8.10
35.30
28.58
20.11
16.12
9.35
37.21
30.50
21.76
17.95
11.09
9.96
40.79
33.96
25.03
21.11
14.38
13.17
11.46
External clock,
PLL ON,
all peripherals
enabled(2)(3)
6.4
6.99
8.17
HSI, PLL off, all
peripherals
4.6
5.17
6.42
8.28
enabled(2)(3)
Supply
1
0.7
1.28
2.64
4.30
7.66
IDD
current in
Run mode
mA
100
84
64
50
25
20
16
15.4
12.4
8.7
16.43
13.28
9.36
7.47
4.27
3.72
2.80
17.35
14.32
10.38
8.54
19.17
16.12
12.06
10.36
7.17
22.85
19.67
15.31
13.49
10.45
10.02
9.07
External clock,
PLL ON, all
peripherals
disabled(3)
6.9
3.7
5.47
3.2
5.01
6.67
HSI, PLL off, all
peripherals
2.3
4.05
5.90
disabled(3)
1
0.6
1.14
2.51
4.16
7.51
1. Guaranteed by characterization results.
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
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Electrical characteristics
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
Table 24. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Unit
TA=
TA=
TA=
TA=
TA=
25 °C
25 °C
85 °C
105 °C
125 °C
100
84
64
50
25
20
16
1
33.3
26.8
18.6
14.6
7.8
35.32(3) 35.65
28.45(3) 28.97
19.74(3) 20.35
37.65
30.82
22.11
18.21
11.32
10.25
8.20
41.26(3)
34.39(3)
25.35(3)
21.46
External clock,
PLL ON,
all peripherals enabled(2)
15.57
8.37
7.25
4.96
0.86
16.41
9.64
8.40
6.39
2.51
14.68
6.7
13.45
HSI, PLL OFF(4)
,
4.6
11.54
all peripherals enabled(2)
Supply
0.8
4.34
7.65
IDD
current in
Run mode
mA
100
84
64
50
25
20
16
15.7
12.7
9.0
16.74(3) 17.62
13.57(3) 14.60
19.50
16.38
12.37
10.63
7.44
23.16(3)
19.98(3)
15.58(3)
13.79
External clock,
PLL ON,
9.62(3)
10.60
8.79
5.68
5.23
4.00
all peripherals
7.1
7.69
disabled(2)
4.0
4.52
10.68
3.4
4.03
6.90
10.27
HSI, PLL OFF,
all peripherals
disabled(2)
2.3
2.44
5.81
9.13
1
0.6
0.70
2.35
4.18
7.49
1. Guaranteed by characterization results.
2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
3. Tested in production
4. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered
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Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Unit
TA =
TA =
TA =
TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
30.2
24.3
16.8
13.2
7.1
32.03
25.77
17.80
14.05
7.62
32.71 34.69 38.46
26.58 28.47 32.16
18.66 20.53 23.85
15.12 16.85 20.27
External clock,
PLL ON,
all peripherals enabled(2)(3)
8.92
7.95
6.28
2.88
10.81 14.11
6.1
6.69
9.72
8.18
4.58
13.09
11.45
8.00
4.4
4.99
HSI, PLL OFF,
all peripherals enabled(2)
Supply
current in
Run mode
0.9
1.50
IDD
mA
100
84
64
50
25
20
16
1
12.6
10.2
7.2
13.46
10.90
7.70
14.75 16.68 20.54
12.25 14.10 17.84
External clock,
8.95
7.56
5.11
4.79
3.91
2.72
10.81 14.14
PLL ON(4)
all peripherals disabled(2)
5.7
6.26
9.26
6.82
6.49
5.80
4.42
12.72
10.26
9.92
3.2
3.77
2.9
3.41
2.1
2.63
9.06
HSI, PLL OFF, all
peripherals disabled(2)
0.8
1.34
7.86
1. Guaranteed by characterization results..
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
4. Refer to Table 47 and RM0383 for the possible PLL VCO setting
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Table 26. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
30.7
24.7
17.2
13.6
7.4
32.85(4) 33.30 35.37 39.08
26.48 27.15 28.94 32.65
18.36 19.14 20.88 24.29
14.54 15.45 17.27 20.58
External clock,
PLL ON(2)
,
all peripherals enabled(3)
7.97
6.99
5.04
1.50
9.23 11.05 14.42
8.18 10.03 13.32
6.4
4.5
6.32
2.89
8.23
4.59
11.50
8.01
HSI, PLL OFF, all
peripherals enabled(3)
1.0
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
13.1
10.7
7.5
14.36 15.33 17.25 20.98
11.67 12.73 14.56 18.21
External clock, PLL ON(2)
all peripherals disabled(3)
8.23
6.74
4.19
3.71
2.67
1.35
9.40 11.13 14.52
6.1
7.89
5.37
5.02
3.95
2.72
9.61
7.08
6.72
5.84
4.43
12.98
10.48
10.15
9.10
3.5
3.2
2.1
HSI, PLL OFF, all
peripherals disabled(3)
0.8
7.87
1. Guaranteed by characterization results.
2. Refer to Table 47 and RM0383 for the possible PLL VCO setting
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
4. Tested in production.
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Table 27. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C
85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
39.9
32.6
24.2
19.7
10.8
9.2
42.46
34.71
25.86
21.01
11.55
9.82
43.17 45.32 49.19
35.45 37.58 41.24
26.73 28.47 31.96
22.00 23.74 27.26
12.83 14.66 18.03
11.16 13.09 16.36
External clock,
PLL ON(2)
,
all peripherals enabled(3)
6.8
7.33
8.77
3.08
10.69 14.00
4.83 8.19
HSI, PLL OFF, all
peripherals enabled(3)
1.2
1.83
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
22.3
18.5
14.6
12.2
7.0
24.11
20.00
15.81
13.14
7.52
25.26 27.35 31.11
21.15 23.20 26.87
17.02 18.74 22.20
14.45 16.18 19.66
External clock, PLL ON(2)
all peripherals disabled(3)
8.95
7.95
6.40
2.94
10.84 14.19
6.0
6.58
9.74
8.30
4.65
13.07
11.59
8.05
4.5
4.97
HSI, PLL OFF, all
peripherals disabled(3)
1.0
1.61
1. Guaranteed by characterization results.
2. Refer to Table 47 and RM0383 for the possible PLL VCO setting
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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Electrical characteristics
Table 28. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
36.1
30.6
23.9
18.9
10.8
9.2
38.48 39.08 40.91 44.59
32.60 33.14 35.10 38.56
25.67 26.27 27.94 31.19
20.32 21.04 22.85 26.10
External clock,
PLL ON,
all peripherals
enabled(2)(3)
11.63
9.84
7.69
12.75 14.56 17.87
11.06 12.98 16.23
HSI, PLL OFF,
all peripherals
enabled(2)(3)
7.1
9.02
3.10
10.87 14.25
4.84 8.20
1
1.2
1.84
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
18.6
16.5
14.3
11.5
7.0
20.33 21.23 23.15 26.71
18.09 19.01 20.81 24.29
15.76 16.67 18.28 21.50
12.57 13.53 15.33 18.49
External clock, PLL ON(3)
all peripherals disabled
7.67
6.68
5.33
1.62
8.90
7.87
6.66
2.95
10.76 14.05
6.0
9.65
8.49
4.66
12.96
11.86
8.06
4.8
HSI, PLL OFF,
all peripherals disabled(3)
1.0
1. Guaranteed by characterization results.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
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STM32F413xG/H
Table 29. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
42.3
34.6
25.5
20.2
10.9
9.3
45.08 45.76 47.88 51.71
36.87 37.58 39.64 43.32
27.18 27.93 29.90 33.23
21.55 22.50 24.34 27.73
External clock,
PLL ON,
all peripherals enabled(2)
11.61
9.86
7.37
1.83
12.87 14.72 18.08
11.20 13.13 16.41
6.9
8.81
3.09
10.72 14.04
4.83 8.19
HSI, PLL OFF,
all peripherals enabled
1.2
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
24.7
20.5
15.9
12.7
7.1
26.76 27.84 29.93 33.66
22.18 23.25 25.33 28.98
17.13 18.23 20.18 23.46
13.68 14.95 16.71 20.13
External clock,
PLL ON(2)
all peripherals disabled
7.57
6.61
5.00
1.61
9.01
7.98
6.44
2.94
10.88 14.25
6.1
9.80
8.33
4.65
13.11
11.63
8.06
4.5
HSI, PLL OFF,
all peripherals disabled
1.0
1. Guaranteed by characterization results.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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Electrical characteristics
Table 30. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
42.9
35.4
26.2
20.7
11.1
9.4
45.86 45.76 47.88 51.71
37.90 38.16 40.01 43.26
28.19 28.74 30.37 33.54
22.32 22.50 24.34 27.73
External clock,
PLL ON,
all peripherals enabled(2)
11.87
10.05
7.72
12.87 14.72 18.08
11.26 13.16 16.46
7.1
9.06
3.10
10.90 14.29
4.84 8.20
HSI, PLL OFF,
all peripherals enabled
1.2
1.84
Supply current
in Run mode
IDD
mA
100
84
64
50
25
20
16
1
25.4
21.4
16.6
13.2
7.2
27.83 27.84 29.93 33.66
23.44 24.10 25.77 29.04
18.31 19.17 20.72 23.86
15.10 14.95 16.71 20.13
External clock,
PLL ON(2)
all peripherals disabled
7.90
6.83
5.37
1.62
9.01
8.05
6.70
2.96
10.88 14.25
6.2
9.88
8.52
4.67
13.15
11.89
8.07
4.8
HSI, PLL OFF,
all peripherals disabled
1.0
1. Guaranteed by characterization results.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
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Electrical characteristics
STM32F413xG/H
Table 31. Typical and maximum current consumption in Sleep mode - V = 3.6 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol Parameter
Conditions
Unit
TA =
25 °C
TA =
25 °C
TA = TA = TA =
85 °C 105 °C 125 °C
100
84
64
50
25
20
16
1
21.6
17.4
12.0
9.5
5.2
4.6
3.0
0.7
22.0
17.7
12.4
9.8
5.5
4.9
3.3
0.9
3.5
2.9
2.2
1.8
1.3
1.3
0.6
0.5
4.0
3.3
2.5
2.2
1.6
1.6
0.9
0.7
22.97(4) 23.91 25.99 29.72
18.50
12.81
10.15
5.79
5.17
3.24
0.76
23.42
18.91
13.17
10.48
6.05
5.42
3.51
1.01
4.17
3.48
2.73
2.38
1.86
1.90
0.68
0.59
4.54
3.87
3.04
2.69
2.13
2.16
0.96
0.85
19.59 21.42 25.09
13.87 15.73 19.00
11.33 13.22 16.44
All peripherals enabled(2)(3)
External clock,
PLL ON,
,
Flash deep power down
7.11
6.41
4.78
2.41
8.82
8.28
6.60
4.23
12.18
11.48
9.94
All peripherals enabled(2)(3)
HSI, PLL OFF,
Flash deep power down
,
,
7.55
100
84
64
50
25
20
16
1
24.45 26.41 30.24
19.98 21.85 25.56
14.30 16.07 19.48
11.72 13.53 16.90
All peripherals enabled(2)(3)
External clock,
PLL ON Flash ON
7.41
6.72
5.06
2.67
5.56
4.94
3.94
3.57
3.11
3.13
2.33
2.24
5.97
5.32
4.33
3.93
3.37
3.39
2.62
2.50
9.11
8.57
6.91
4.52
7.54
6.76
5.80
5.42
4.82
4.85
4.16
4.07
8.09
7.19
6.15
5.82
5.20
5.22
4.47
4.36
12.55
11.89
10.30
7.88
11.23
10.40
8.98
8.60
8.12
8.15
7.47
7.38
11.74
10.84
9.47
9.04
8.46
8.48
7.82
7.71
All peripherals enabled(2)(3)
HSI, PLL ON, Flash ON
,
Supply
IDD
current in
mA
100
84
64
50
25
20
16
1
Sleep mode
All peripherals disabled,
External clock,
PLL ON(2)
,
Flash deep power down
All peripherals disabled,
HSI, PLL OFF(2)
,
Flash deep power down
100
84
64
50
25
20
16
1
All peripherals disabled,
External clock,
PLL ON(2), Flash ON
All peripherals disabled,
HSI, PLL OFF(2), Flash ON
1. Guaranteed by characterization results.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
4. Tested in production.
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Table 32. Typical and maximum current consumption in Sleep mode - V = 1.7 V
DD
Typ
Max(1)
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA = TA =
TA =
25 °C
25 °C 85 °C 105 °C 125 °C
100
84
64
50
25
20
16
21.2
17.1
11.8
9.3
22.64 23.56 25.66 29.30
18.20 19.27 21.14 24.75
12.53 13.59 15.47 18.66
External clock,
PLL ON,
Flash deep power down,
9.88
5.52
4.93
3.53
11.06 12.94 16.11
all peripherals enabled(2)
5.0
6.83
6.16
4.91
8.61
8.03
6.57
11.88
11.19
9.94
4.4
HSI, PLL OFF(2)
,
3.0
Flash deep power down,
all peripherals enabled
1
0.6
1.19
2.55
4.21
7.57
100
84
64
50
25
20
16
21.7
17.4
12.1
9.6
23.10 24.09 26.12 29.90
18.61 19.72 21.55 25.27
12.89 13.98 15.84 19.18
External clock, PLL ON(2)
all peripherals enabled,
Flash ON
10.20
5.80
5.18
3.79
11.43 13.32 16.62
5.2
7.19
6.47
5.17
8.91
8.37
6.88
12.33
11.63
10.32
4.6
HSI, PLL OFF(2), all
peripherals enabled,
Flash ON
3.2
1
0.9
1.43
2.80
4.50
7.92
Supply current
in Sleep mode
IDD
mA
100
84
64
50
25
20
16
3.3
2.7
1.9
1.6
1.0
1.1
0.6
3.82
3.22
2.48
2.13
1.61
1.66
1.12
5.34
4.70
3.70
3.35
2.90
2.93
2.49
7.25
6.54
5.55
5.15
4.57
4.59
4.14
10.97
10.13
8.71
8.35
7.91
7.93
7.49
All peripherals disabled,
External clock,
PLL ON(2)
,
Flash deep power down
All peripherals disabled,
HSI, PLL OFF(2)
,
1
0.5
1.04
2.40
4.06
7.40
Flash deep power down
100
84
64
50
25
20
16
3.7
3.1
2.3
1.9
1.3
1.4
0.8
4.28
3.60
2.80
2.44
1.89
1.92
1.38
5.76
5.11
4.09
3.70
3.18
3.20
2.75
7.83
6.96
5.96
5.59
4.94
4.97
4.44
11.49
10.64
9.23
8.82
8.27
8.29
7.87
All peripherals disabled,
External clock, PLL
ON(2), Flash ON
All peripherals disabled,
HSI, PLL OFF(2), Flash
ON
1
0.7
1.25
2.65
4.34
7.77
1. Guaranteed by characterization results.
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Electrical characteristics
STM32F413xG/H
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
Table 33. Typical and maximum current consumptions in Stop mode - V = 1.7 V
DD
Typ(1)
Max(1)
Symbol
Conditions
Parameter
Unit
TA = TA = TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C 125 °C
111.7 157.9 713.7 1323.5 2315.1
42.3 80.1 594.1 1167.6 2097.6
Flash in Stop mode,
all oscillators OFF, no
independent watchdog
Main regulator usage
Low power regulator usage
Main regulator usage
77.9 113.1 568.3 1073.6 1883.7
19.7 55.8 561.3 1123.2 2026.0
IDD_STOP
µA
Flash in Deep power
down mode, all
Low power regulator usage
oscillators OFF, no
independent watchdog
Low power low voltage regulator
usage
15.3 46.3 490.8 991.3 1793.9
1. Guaranteed by characterization results.
Table 34. Typical and maximum current consumption in Stop mode - V =3.6 V
DD
Max(1)
Typ
Symbol
Conditions
Parameter
Unit
TA =
TA =
TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C 125 °C
114.4 161.6(2) 723.0 1339.0 2342.7(2)
44.1 82.5(2) 600.6 1179.3 2119.1
80.6 116.7 572.3 1079.2 1896.3
Flash in Stop mode, all Main regulator usage
oscillators OFF, no
Low power regulator usage
independent watchdog
Main regulator usage
Flash in Deep power
IDD_STOP
µA
down mode, all
Low power regulator usage
21.4
58.9 567.9 1134.5 2049.6
oscillators OFF, no
independent watchdog
Low power low voltage
regulator usage
17.0 49.0(2) 497.4 1003.6 1817.0(2)
1. Guaranteed by characterization results.
2. Tested in production.
Table 35. Typical and maximum current consumption in Standby mode - V = 1.7 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA = TA = TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C 125 °C
Low-speed oscillator (LSE in low drive
mode) and RTC ON
2.3
3.7
15.9
32.5
76.8
Supply current in
Standby mode
IDD_STBY
Low-speed oscillator (LSE in high drive
mode) and RTC ON
µA
2.9
1.1
4.3
2.5
16.5
14.7
33.1
31.3
77.4
75.6
RTC and LSE OFF
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization results.
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Electrical characteristics
Table 36. Typical and maximum current consumption in Standby mode - V = 3.6 V
DD
Typ(1)
Max(2)
Symbol
Parameter
Conditions
Unit
TA = TA = TA =
TA =
TA =
25 °C 25 °C 85 °C 105 °C 125 °C
Low-speed oscillator (LSE in low drive
mode) and RTC ON
3.7
5.2
20.6
40.5
82.7
Supply current in
Standby mode
IDD_STBY
Low-speed oscillator (LSE in high drive
mode) and RTC ON
µA
4.5
2.5
6.0
4.0
21.4
19.4
41.3
83.5
RTC and LSE OFF
39.3 81.5(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Tested in production.
Table 37. Typical and maximum current consumptions in V
Typ
mode
BAT
Max(2)
TA = TA = TA =
TA = 25 °C
Symbol Parameter
Conditions(1)
85 °C 105 °C 125 °C Unit
VBAT = 3.6 V
VBAT = VBAT= VBAT = VBAT
1.7 V 2.4 V 3.3 V 3.6 V
=
Low-speed oscillator (LSE in
low-drive mode) and RTC ON
0.74
0.84 1.04
1.24 3.00 5.00 10.00
Backup
domain
I
Low-speed oscillator (LSE in
high-drive mode) and RTC ON
µA
DD_VBAT supply
current
1.51
0.03
1.64 1.89
0.03 0.04
2.00 3.80 5.80 11.60
0.04 2.00 4.00 8.00
RTC and LSE OFF
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
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Electrical characteristics
Figure 24. Typical V
STM32F413xG/H
current consumption (LSE and RTC ON/LSE oscillator
BAT
“low power” mode selection)
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Figure 25. Typical V
current consumption (LSE and RTC ON/LSE oscillator
“high drive” mode selection)
BAT
06Yꢇꢀꢃꢊꢀ9ꢈ
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Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 39: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
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Table 38. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions(1)
Typ
Unit
frequency (fSW
)
2 MHz
8 MHz
0.05
0.15
0.45
0.85
1.00
1.40
1.67
0.10
0.35
1.05
2.20
2.40
3.55
4.23
0.20
0.65
1.85
2.45
4.70
8.80
10.47
0.25
1.00
3.45
7.15
11.55
0.32
1.27
3.88
12.34
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
C = CINT
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT + CS
I/O switching
current
IDDIO
mA
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
VDD = 3.3 V
CEXT =10 pF
C = CINT + CEXT + CS
8 MHz
VDD = 3.3 V
CEXT = 22 pF
25 MHz
50 MHz
60 MHz
2 MHz
C = CINT + CEXT + CS
VDD = 3.3 V
8 MHz
CEXT = 33 pF
25 MHz
50 MHz
C = CINT + CEXT + CS
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
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Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The ART accelerator is ON.
Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
HCLK is the system clock at 100 MHz. f = f /2, and f = f .
HCLK
PCLK1
HCLK
PCLK2
The given value is calculated by measuring the difference of current consumption
–
–
–
–
–
with all peripherals clocked off,
with only one peripheral clocked on,
scale 1 with f
scale 2 with f
scale 3 with f
= 100 MHz,
= 84 MHz,
= 64 MHz.
HCLK
HCLK
HCLK
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
Table 39. Peripheral current consumption
IDD (Typ)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
CRC
1.89
1.75
1.70
1.72
1.78
1.68
1.66
0.72
0.30
1.82
1.68
1.64
1.65
1.71
1.62
1.61
0.69
0.30
1.64
1.52
1.48
1.48
1.55
1.45
1.44
0.63
0.28
AHB1
µA/MHz
DMA1(1)
DMA2(1)
RNG
1.75N + 3.14 1.66N + 3.00 1.49N + 2.70
1.79N + 3.29 1.71N + 3.14 1.53N + 2.82
0.72
19.26
5.42
0.70
18.37
5.18
0.63
16.47
4.64
AHB2
AHB3
µA/MHz
µA/MHz
USB_OTG_FS
FSMC
QSPI
10.33
9.86
8.84
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Electrical characteristics
STM32F413xG/H
Table 39. Peripheral current consumption (continued)
DD (Typ)
I
Peripheral
Unit
Scale 1
Scale 2
Scale 3
AHB-APB1 bridge
0.90
13.08
9.98
9.88
13.14
1.94
1.86
5.56
3.44
3.66
7.34
0.64
3.02
3.06
3.30
3.32
3.18
3.26
3.20
3.30
3.26
5.22
5.58
5.14
5.70
0.90
2.14
3.08
3.10
0.88
12.48
9.50
9.43
12.52
1.86
1.79
5.29
3.29
3.48
7.00
0.62
2.88
2.90
3.14
3.14
3.02
3.10
3.05
3.14
3.10
4.98
5.31
4.88
5.43
0.86
2.05
2.93
2.95
0.81
11.16
8.50
8.44
11.19
1.66
1.56
4.72
2.94
3.09
6.25
0.53
2.56
2.59
2.81
2.81
2.69
2.75
2.72
2.81
2.78
4.44
4.75
4.38
4.84
0.75
1.81
2.59
2.63
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
LPTIM1
WWDG
SPI2/I2S2
SPI3/I2S3
USART2
USART3
UART4
UART5
I2C1
APB1
µA/MHz
I2C2
I2C3
I2CFMP1
CAN1
CAN2
CAN3
PWR
DAC1
UART7
UART8
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Electrical characteristics
Table 39. Peripheral current consumption (continued)
DD (Typ)
I
Peripheral
Unit
Scale 1
Scale 2
Scale 3
AHB-APB2 bridge
0.10
6.78
6.94
3.14
3.12
2.89
2.91
3.45
3.54
1.52
1.50
0.58
0.91
2.95
1.88
1.86
1.50
2.89
4.43
7.08
4.06
0.11
6.46
6.62
3.00
2.98
1.98
2.00
3.29
3.37
1.46
1.43
0.55
0.86
2.81
1.79
1.77
1.43
2.75
4.21
6.76
3.87
0.09
5.80
5.94
2.69
2.67
1.75
1.77
2.95
3.03
1.31
1.28
0.50
0.78
2.53
1.61
1.59
1.30
2.47
3.80
6.05
3.45
TIM1
TIM8
USART1
USART6
UART9
UART10
ADC1
SDIO
SPI1
APB2
SPI4
µA/MHz
SYSCFG
EXT1
TIM9
TIM10
TIM11
SPI5
SAI
DFSDM1
DFSDM2
Bus Matrix
1. N is the number of stream enable (1...8).
6.3.7
Wakeup time from low-power modes
The wakeup times given in Table 40 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0/PC0/PC1) pins are used to wakeup from Standby, Stop and Sleep modes.
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Figure 26. Low-power mode wakeup
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All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
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Electrical characteristics
(1)
Table 40. Low-power mode wakeup timings
Min(1)
Typ(1) Max(1)
Symbol
Parameter
Conditions
Unit
clk
cycles
tWUSLEEP
-
-
4
6
Wakeup from Sleep mode
Flash memory in Deep
power down mode
tWUSLEEPFDSM
-
-
-
50.0
15.0
Main regulator
12.7
Main regulator, Flash
memory in Deep power
down mode
-
-
-
104.1 120.0
Wakeup from Stop mode,
regulator in low power
mode(2)
20.9
28.0
Wakeup from STOP mode
Code execution on Flash
tWUSTOP
Regulator in low power
mode, Flash memory in
Deep power down mode(2)
112.5
130.0
Regulator in low power
mode low voltage, Flash
memory in Deep power
down mode
-
-
-
112.5
4.2
130.0
7.0
µs
Main regulator with Flash in
Stop mode or Deep power
down(2)
Wakeup from STOP mode
code execution on RAM(3)
tWUSTOP
Wakeup from Stop mode,
regulator in low power
mode and Flash in Stop
mode or Deep power down
12.6
20.0
Wakeup from Standby
mode
tWUSTDBY
-
-
-
-
328.2 400.0
From Flash_Stop mode
-
-
11.0
40.0
tWUFLASH
Wakeup of Flash
From Flash Deep power
down mode
1. Guaranteed by characterization results.
2. The specification is valid for wakeup from regulator in low power mode or low power low voltage mode, since the timing
difference is negligible.
3. For the faster wakeup time for code execution on RAM, the Flash must be in STOP or DeepPower Down mode (see
reference manual RM0430).
6.3.8
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59. However, the recommended clock input
waveform is shown in Figure 27.
The characteristics given in Table 41 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
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Electrical characteristics
STM32F413xG/H
summarized in Table 17.
Table 41. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
55
±1
IL
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59. However, the recommended clock input
waveform is shown in Figure 28.
The characteristics given in Table 42 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 42. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
Cin(LSE)
OSC32_IN input capacitance(1)
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
70
±1
IL
OSC32_IN Input leakage current
VSS ≤ VIN ≤ VDD
-
µA
1. Guaranteed by design.
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Electrical characteristics
Figure 27. High-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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Symbol
STM32F413xG/H
(1)
Table 43. HSE 4-26 MHz oscillator characteristics
Parameter
Conditions
Min
Typ Max Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
4
-
-
26
-
MHz
200
kΩ
VDD=3.3 V,
ESR= 30 Ω,
-
-
450
530
-
-
CL=5 pF @25 MHz
IDD
HSE current consumption
HSE accuracy
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF @25 MHz
(2)
ACCHSE
-
-500
-
-
500
ppm
mA/V
ms
Gm_crit_max Maximum critical crystal gm
Startup
-
-
1
-
(3)
tSU(HSE)
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 29. Typical application with an 8 MHz crystal
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 44. In
the application, the resonator and the load capacitors have to be placed as close as
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possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
The LSE high-power mode allows to cover a wider range of possible crystals but with a cost
of higher power consumption.
(1)
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
-
-
18.4
-
MΩ
Low-power mode
(default)
-
-
1
IDD
LSE current consumption
LSE accuracy
µA
High-drive mode
-
-
-
-
3
(2)
ACCLSE
-500
500
ppm
Startup, low-power
mode
-
-
0.56
Gm_crit_max Maximum critical crystal gm
µA/V
s
Startup, high-drive
mode
-
-
-
1.50
-
(3)
tSU(LSE)
startup time
VDD is stabilized
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. Refer to the application note AN2867.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in
production. It is measured for a standard crystal resonator and it can vary significantly with the crystal
manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
For information about the LSE high-power mode, refer to the reference manual RM0383.
Figure 30. Typical application with a 32.768 kHz crystal
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STM32F413xG/H
6.3.9
Internal clock source characteristics
The parameters given in Table 45 and Table 46 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 17.
DD
High-speed internal (HSI) RC oscillator
L
(1)
Table 45. HSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fHSI
Frequency
-
-
16
-
1
MHz
%
HSI user trimming step(2)
Accuracy of the HSI oscillator
HSI oscillator startup time
-
-
-
TA = – 40 to 125 °C(3)
TA = – 40 to 105 °C(3)
TA = –10 to 85 °C(3)
TA = 25 °C(4)
–8
–8
–4
–1
-
-
6.75
4.5
4
%
ACCHSI
-
-
%
%
-
1
%
(2)
tsu(HSI)
-
2.2
4
µs
HSI oscillator power
consumption
(2)
IDD(HSI)
-
-
60
80
µA
1. VDD = 3.3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design
3. Based on characterization
4. Factory calibrated, parts not soldered.
Figure 31. ACC
versus temperature
HSI
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Electrical characteristics
Low-speed internal (LSI) RC oscillator
(1)
Table 46. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
16.1
32.0
15.0
0.4
47.0
40.0
0.6
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
-
-
(3)
IDD(LSI)
LSI oscillator power consumption
µA
1.
VDD = 3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.
Figure 32. ACC versus temperature
LSI
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STM32F413xG/H
6.3.10
PLL characteristics
The parameters given in Table 47 and Table 48 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 47. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
-
-
0.95(2)
24
1
-
2.10
100
fPLLP_OUT
PLLP multiplier output clock
48 MHz PLLQ multiplier
output clock
fPLLQ_OUT
-
-
-
-
48
-
75
MHz
PLLR multiplier output clock
for I2S and SAI
fPLLR_OUT
fVCO_OUT
216
PLL VCO output
PLL lock time
-
100
75
100
-
-
-
432
200
300
-
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
µs
ps
-
Cycle-to-cycle jitter
Period Jitter
RMS
25
peak
to
peak
-
-
-
150
15
-
-
-
System clock
100 MHz
RMS
Jitter(3)
peak
to
200
peak
Cycle to cycle at 1 MHz
on 1000 samples.
Bit Time CAN jitter
-
330
-
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
-
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLL power consumption on
VDDA
(4)
IDDA(PLL)
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of two PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
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Symbol
Electrical characteristics
Table 48. PLLI2S (audio PLL) characteristics
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
-
0.95(2)
1
2.10
48 MHz PLLI2SQ
multiplier output clock
fPLLI2SQ_OUT
-
-
-
48
-
75
MHz
PLLI2SR multiplier output clock
for I2S and SAI
fPLLI2SR_OUT
fVCO_OUT
-
216
PLLI2S VCO output
-
100
75
100
-
-
-
432
200
300
-
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
PLLI2S lock time
µs
-
RMS
90
Cycle to cycle at
12.288 MHz on
48 kHz period,
N=432, R=5
peak
to
peak
-
280
90
-
Master I2S clock jitter
WS I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
ps
-
-
-
-
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
400
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
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6.3.11
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 55: EMI characteristics for LQFP144). It is available only on the
main PLL.
Table 49. SSCG parameter constraints
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
Peak modulation depth
-
0.25
-
-
-
-
10
2
kHz
%
MODEPER * INCSTEP
1. Guaranteed by design.
(Modulation period) * (Increment Step)
215-1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
PLL_IN
MOD
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
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Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
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6.3.12
Memory characteristics
Flash memory
The characteristics are given at T = –40 to 125 °C unless otherwise specified.
A
The devices are shipped to customers with the Flash memory erased.
Table 50. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Write / Erase 8-bit mode, VDD = 1.7 V
Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
-
5
8
-
-
-
IDD
Supply current
mA
12
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STM32F413xG/H
Table 51. Flash memory programming
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8/16/32
tprog
Word programming time
-
-
-
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
800
Program/eraseparallelism
(PSIZE) = x 8
400
300
250
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
600
500
ms
ms
s
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1200 2400
Program/eraseparallelism
(PSIZE) = x 16
700
550
2
1400
1100
4
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
Program/eraseparallelism
(PSIZE) = x 16
1.3
1
2.6
2
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
24
15
11
48
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
30
s
Program/eraseparallelism
(PSIZE) = x 32
22
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.
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Table 52. Flash memory programming with V voltage
PP
Symbol
tprog
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
Double word programming
-
-
16
230
490
875
9.8
-
100(2)
µs
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
-
-
TA = 0 to +40 °C
VDD = 3.3 V
-
ms
VPP = 8.5 V
-
-
tME
Vprog
VPP
Mass erase time
-
-
s
V
V
Programming voltage
VPP voltage range
-
-
2.7
7
3.6
9
-
Minimum current sunk on
the VPP pin
IPP
-
-
10
-
-
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
1
hour
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 53. Flash memory endurance and data retention
Value
Symbol
Parameter
Conditions
Unit
Min(1)
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
TA = –40 to +125 °C (3 suffix versions)
NEND Endurance
kcycles
Years
10
1 kcycle(2) at TA = 85 °C
1 kcycle(2) at TA = 105 °C
1 kcycle(2) at TA = 125 °C
10 kcycle(2) at TA = 55 °C
30
10
3
tRET
Data retention
20
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
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STM32F413xG/H
6.3.13
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.
Table 54. EMS characteristics for LQFP144 package
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP144
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
TA = +25 °C, fHCLK = 100 MHz,
conforms to IEC 61000-4-2
1B
3B
V
DD = 3.3 V, LQFP144
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VEFTB
TA = +25 °C, fHCLK = 100 MHz,
conforms to IEC 61000-4-4
When the application is exposed to a noisy environment, it is recommended to avoid pin
exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP144 packages and PDR_ON on WLCSP81.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with IEC61967-2
standard which specifies the test board and the pin loading.
Table 55. EMI characteristics for LQFP144
Max vs.
[fHSE/fCPU
Monitored
frequency band
]
Symbol
Parameter
Conditions
Unit
8/100 MHz
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1 GHz
1 GHz to 2 GHz
EMI Level
13
21
25
19
4
VDD = 3.6 V, TA = 25 °C, LQFP144
package, conforming to IEC 61967-2,
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering disabled.
dBµV
-
SEMI
Peak level
6.3.14
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
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Table 56. ESD absolute maximum ratings
Conditions
Maximum
Unit
Symbol
Ratings
Class
value(1)
Electrostatic
VESD(HBM) discharge voltage
TA = +25 °C conforming to JESD22-A114
2
2000
(human body model)
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
UFBGA144, UFBGA100, LQFP144, LQFP100,
WLCSP81, LQFP64
V
3
4
250
Electrostatic
VESD(CDM) discharge voltage
(charge device model)
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
UFQFPN48
500
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 57. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +125 °C conforming to JESD78A
II level A
6.3.15
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 58.
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Table 58. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0, PDR_ON, BYPASS_REG
Injected current on NRST
- 0
- 0
0
NA
Injected current on PE6, PC13, PC14, PC15, PF0, PF1,
PF2, PC0, PC1, PC2, PC3
IINJ
- 0
NA
mA
Injected current on any other FT and FTf pins
Injected current on any other pins
- 5
- 5
NA
+ 5
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 59. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FT, TTa, TC and NRST I/O input
low level voltage
(1)
1.7 V≤VDD≤3.6 V
-
-
0.3VDD
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤125 °C
VIL
-
-
-
-
-
V
V
BOOT0 I/O input low level
voltage
0.1VDD+0.1(2)
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤125 °C
FT, TTa, TC and NRST I/O input
high level voltage(5)
(1)
1.7 V≤VDD≤3.6 V
0.7VDD
-
-
-
-
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤125 °C
VIH
BOOT0 I/O input high level
voltage
0.17VDD+0.7(2)
-
-
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤125 °C
FT, TTa, TC and NRST I/O input
hysteresis
(2)(3)
1.7 V≤VDD≤3.6 V
10% VDD
1.75 V≤VDD ≤3.6 V,
-40 °C≤TA ≤125 °C
VHYS
V
BOOT0 I/O input hysteresis
0.1
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤125 °C
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Table 59. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I/O input leakage current (4)
VSS ≤VIN ≤VDD
-
-
1
Ilkg
µA
I/O FT/TC input leakage current
VIN = 5 V
VIN = VSS
-
-
-
3
(5)
All pins
except for
PA10
(OTG_FS_ID)
30
7
40
10
40
50
14
50
Weak pull-up
equivalent
resistor(6)
RPU
PA10
(OTG_FS_ID)
kΩ
All pins
except for
PA10
(OTG_FS_ID)
VIN = VDD
30
Weak pull-down
equivalent
RPD
resistor(7)
PA10
-
-
7
-
10
5
14
-
(OTG_FS_ID)
(8)
CIO
I/O pin capacitance
pF
1. Guaranteed by test in production.
2. Guaranteed by design.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 58: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 58: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT and TC I/Os is shown in Figure 35.
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Figure 35. FT/TC I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14 and PC15 which can
OL OH
sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 15).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 15).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 17. All I/Os are CMOS and TTL compliant.
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Table 60. Output voltage characteristics
Symbol
Parameter
Output low level voltage for an I/O pin
Conditions
Min
Max
Unit
VOL
VOH
VOL
VOH
CMOS port(2)
IIO = +8 mA
-
0.4
(1)
V
(3)
(1)
(3)
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
VDD–0.4
-
0.4
-
2.7 V ≤VDD ≤3.6 V
TTL port(2)
IIO =+8 mA
-
V
2.4
2.7 V ≤VDD ≤3.6 V
(1)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3(4)
IIO = + 20 mA
V
V
V
(3)
VDD–1.3(4)
-
2.7 V ≤VDD ≤3.6 V
VOH
VOL
VOH
-
0.4(4)
(1)
IIO = + 6 mA
(3)
VDD–0.4(4)
-
0.4(5)
-
1.8 V ≤VDD ≤3.6 V
(1)
VOL
-
IIO = +4 mA
VOH
VDD–0.4(5)
(3)
1.7 V ≤VDD ≤3.6 V
IIO = + 20 mA
Output low level voltage for an FTf I/O pin in
FM+ mode
(1)
(1)
VOLFM
-
-
0.4
0.4
V
V
2.7 V ≤ VDD ≤ 3.6 V
Output low level voltage for an FTf I/O pin in
FM+ mode
IIO = + 10 mA
1.8 V ≤ VDD ≤ 3.6 V
VOLFM
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15. and the sum of
IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 15 and the sum
of IIO (I/O ports and control pins) must not exceed IVDD
4. Guaranteed by characterization results.
5. Guaranteed by design.
.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 36 and
Table 61, respectively.
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 17.
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OSPEEDRy
Electrical characteristics
(1)(2)
Table 61. I/O AC characteristics
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
Output high to low level
MHz
8
00
4
tf(IO)out
/
fall time and output low to CL = 50 pF, VDD = 1.7 V to 3.6 V
high level rise time
-
-
100
ns
tr(IO)out
CL = 50 pF, VDD ≥ 2.70 V
CL = 50 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
50
fmax(IO)out Maximum frequency(3)
MHz
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 50 pF, VDD ≥2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.70 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.70 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD≥ 2.70 V
CL = 40 pF, VDD≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.70 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.70 V
CL = 10 pF, VDD≥ 1.7 V
20
01
10
Output high to low level
fall time and output low to
high level rise time
20
tf(IO)out
tr(IO)out
/
ns
6
10
50(4)
25
fmax(IO)out Maximum frequency(3)
MHz
100(4)
50(4)
6
10
Output high to low level
fall time and output low to
high level rise time
10
tf(IO)out
tr(IO)out
/
ns
MHz
ns
4
6
100(4)
50(4)
4
Fmax(IO)ou
Maximum frequency(3)
t
11
Output high to low level
fall time and output low to
high level rise time
6
tf(IO)out
tr(IO)out
/
2.5
4
Fmax Maximum frequency
1
MHz
ns
FM+
-
CL = 50 pF, 1.6 ≤ VDD ≤ 3.6 V
Output high to low level
fall time
Tf
-
-
-
5
-
Pulse width of external
tEXTIpw signals detected by the
EXTI controller
-
10
ns
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1. Guaranteed by characterization results.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 36. I/O AC characteristics definition
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6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 59).
PU
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 17. Refer to Table 59: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Table 62. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Weak pull-up equivalent
resistor(1)
RPU
VIN = VSS
30
40
50
kΩ
(2)
VF(NRST)
NRST Input filtered pulse
-
-
-
-
100
-
ns
ns
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
300
Internal Reset
source
TNRST_OUT Generated reset pulse duration
20
-
-
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
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Figure 37. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 62. Otherwise the reset is not taken into account by the device.
6.3.18
TIM timer characteristics
The parameters given in Table 63 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 63. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
tTIMxCLK
1
-
-
or 2 or 4, fTIMxCLK
100 MHz
=
11.9
ns
tTIMxCLK
ns
tres(TIM)
Timer resolution time
1
11.9
0
-
AHB/APBx prescaler>4,
fTIMxCLK = 100 MHz
-
fTIMxCLK/2
MHz
MHz
bit
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 100 MHz
0
50
ResTIM
Timer resolution
-
16/32
16-bit counter clock
period when internal clock
is selected
tCOUNTER
fTIMxCLK = 100 MHz
0.0119
780
µs
65536 ×
65536
tTIMxCLK
S
-
-
-
Maximum possible count
with 32-bit counter
tMAX_COUNT
fTIMxCLK = 100 MHz
51.1
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE
bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise
TIMxCLK >= 4x PCLKx.
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STM32F413xG/H
6.3.19
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the requirements of the standard I C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and V is
DD
disabled, but is still present.
2
The I C characteristics are described in Table 64. Refer also to Section 6.3.16: I/O port
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL)
.
2
The I C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
2
kHz). The I C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, contact your local ST sales representative.
2
Table 64. I C characteristics
Standard mode I2C(1)(2)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
4.70
4.0
0.25
0
-
1.30
0.60
0.10
0
-
SCL clock high time
SDA setup time
-
-
-
-
-
-
SDA data hold time
tv(SDA,ACK) SDA data hold time
-
3.45(3)
-
0.90(4)
tr(SDA)
SDA and SCL rise time
tr(SCL)
-
0.100
-
0.30
tf(SDA)
SDA and SCL fall time
tf(SCL)
-
4
0.30
-
0.30
µs
th(STA)
tsu(STA)
Start condition hold time
-
-
-
-
0.6
0.6
0.60
1.3
-
-
-
-
Repeated Start condition setup
time
4.7
4
tsu(STO)
Stop condition setup time
Stop to Start condition time (bus
free)
tw(STO:STA)
4.70
Pulse width of the spikes that are
suppressed by the analog filter
for standard fast mode
tSP
Cb
-
-
-
0.05
-
0.10(5)
400
Capacitive load for each bus line
400
pF
Guaranteed by design.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode
I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
5. The minimum width of the spikes filtered by the analog filter is above tSP (max)
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2
Figure 38. I C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
(1)(2)
Table 65. SCL frequency (f
= 50 MHz, VDD = VDD_I2C = 3.3 V)
I2C_CCR value
PCLK1
fSCL (kHz)
RP = 4.7 kΩ
400
300
200
100
50
0x8019
0x8021
0x8032
0x0096
0x012C
0x02EE
20
1. RP = External pull-up resistance, fSCL = I2C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external
components used to design the application.
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FMPI2C characteristics
2
The following table presents FMPI C characteristics.
Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output
function characteristics (SDA and SCL).
2
(1)
Table 66. FMPI C characteristics
Standard mode Fast mode
Fast+ mode
Min Max
18
Parameter
Unit
Min
Max
Min
Max
fFMPI2CC
FMPI2CCLK frequency
2
-
8
-
-
tw(SCLL)
tw(SCLH)
tsu(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
0.25
0
-
1.3
0.6
0.10
0
-
-
0.5
0.26
0.05
0
-
-
-
-
-
-
-
-
tH(SDA)
SDA data hold time
Data, ACK valid time
-
tv(SDA,ACK)
-
3.45
-
0.9
-
0.45
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1.0
-
0.30
-
0.12
tf(SDA)
tf(SCL)
µs
SDA and SCL fall time
Start condition hold time
-
4
0.30
-
0.30
-0
0.12
th(STA)
tsu(STA)
-
-
-
-
0.6
0.6
0.6
1.3
-
-
-
-
0.26
0.26
0.26
0.5
-
-
-
-
Repeated Start condition
setup time
4.7
4
tsu(STO)
Stop condition setup time
Stop to Start condition time
(bus free)
tw(STO:STA)
4.7
Pulse width of the spikes that
are suppressed by the
analog filter for standard and
fast mode
tSP
Cb
-
-
-
0.05
-
0.1
0.05
-
0.1
Capacitive load for each bus
Line
550(2)
400
400
pF
1. Based on characterization results.
2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = (VDD -VOL(max)) / IOL(max)
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Electrical characteristics
2
Figure 39. FMPI C timing diagram and measurement circuit
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DocID029162 Rev 5
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174
Electrical characteristics
STM32F413xG/H
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 67 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 67. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode,
SPI1,4,5
-
-
50
3.0 V < VDD < 3.6 V
Master mode,
SPI1,4,5
-
-
-
-
42
25
2.7 V < VDD < 3.6 V
Master mode
SPI1,4,5
1.7 V < VDD < 3.6 V
Master transmitter mode
-
-
-
-
-
-
-
-
-
-
50
50
SPI1,4,5
1.71 V < VDD < 3.6 V
fSCK
SPI clock frequency
MHz
1/tc(SCK)
Slave receiver mode
SPI1,4,5
1.71 V < VDD < 3.6 V
Slave mode transmitter/full duplex
SPI1,4,5
2.7 V < VDD < 3.6 V
40(2)
26
Slave mode transmitter/full duplex
SPI1,4,5
1.71 V < VDD < 3.6 V
Master & Slave mode,
SPI2/3
25
1.71 V < VDD < 3.6 V
tsu(NSS)
th(NSS)
tw(SCKH)
tw(SCKL)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
4*TPCLK
2*TPCLK
-
-
-
-
ns
ns
SCK high and low time Master mode
TPCLK - 2 TPCLK TPCLK +2 ns
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Master mode
Data input setup time
2.5
4.5
5
-
-
-
-
-
-
-
-
ns
ns
Slave mode
Master mode
Data input hold time
Slave mode
2
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Symbol
Electrical characteristics
(1)
Table 67. SPI dynamic characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
ta(SO)
Data output access time Slave mode
Data output disable time Slave mode
7
5
-
-
21
12
ns
ns
tdis(SO)
Slave mode (after enable edge),
2.7 V < VDD < 3.6 V
-
7
12.5
tv(SO)
Data output valid time Slave mode (after enable edge),
1.71 V < VDD < 3.6 V
ns
ns
-
-
7
2
-
19
3
-
tv(MO)
th(SO)
th(MO)
Master mode
Slave mode
1.71 V < VDD < 3.6 V
Data output hold time
6
Master mode
1.5
-
-
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Figure 40. SPI timing diagram - slave mode and CPHA = 0
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Figure 41. SPI timing diagram - slave mode and CPHA = 1
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136/207
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Electrical characteristics
I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 68 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 68. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256 * 8K 256 * Fs(2) MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64 * Fs
fCK
MHz
%
64 * Fs
DCK
I2S clock frequency duty cycle Slave receiver
30
-
70
tv(WS)
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
3.5
th(WS)
1.5
2.5
0.5
3
-
-
tsu(WS)
th(WS)
Slave mode
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Master receiver
Slave receiver
Master receiver
Slave receiver
-
Data input setup time
Data input hold time
Data output valid time
Data output hold time
2.5
5
-
ns
-
1.5
-
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
15
6
-
-
3.5
1.5
-
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).
Note:
Refer to the I2S section of RM0430 reference manual for more details on the sampling
frequency (F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
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2
Figure 43. I S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
Figure 44. I S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
SAI characteristics
Unless otherwise specified, the parameters given in Table 69 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(1)
Table 69. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCKL
SAI Main clock output
-
256 * 8K 256 * Fs(2)
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
128 * Fs
128 * Fs
FSCK
tv(FS)
th(FS)
SAI clock frequency
FS valid time
MHz
Master mode
-
-
19
28
2.7 V <= VDD <= 3.6 V
Master mode
1.71 V <= VDD <= 3.6 V
Master mode
Slave mode
13
0
-
-
-
-
-
-
-
FS hold time
FS setup time
tsu(FS)
Slave mode
3
tsu(SD_ A_MR)
tsu(SD_B_SR)
th(SD_ A_MR)
th(SD_B_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
0.5
1.5
5
Data input setup time
Data input hold time
ns
2.5
Slave transmitter (after enable edge)
2.7 V <= VDD <= 3.6 V
-
15
tv(SD_B_ST) Data output valid time
th(SD_B_ST) Data output hold time
tv(SD_A_MT) Data output valid time
Slave transmitter (after enable edge)
1.71 V <= VDD <= 3.6 V
-
10
-
28
-
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
2.7 V <= VDD <= 3.6 V
15
Master transmitter (after enable edge)
1.71 V <= VDD <= 3.6 V
-
29
-
th(SD_A_MT) Data output hold time Master transmitter (after enable edge)
13
1. Guaranteed by characterization results.
2. 256 * Fs maximum corresponds to 45 MHz (APB2 maximum frequency)
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Figure 45. SAI master timing waveforms
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Electrical characteristics
QSPI interface characteristics
Unless otherwise specified, the parameters given in the following tables for QSPI are
derived from tests performed under the ambient temperature, f frequency and V
AHB
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C=20pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics.
(1)
Table 70. QSPI dynamic characteristics in SDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
Cload = 20 pF
-
-
100
fSCK
QSPI clock frequency
MHz
1/tc(SCK)
1.71 V < VDD < 3.6 V
Cload = 15 pF
-
-
80
tw(CKH)
tw(CKL)
ts(IN)
t
(CK) / 2 - 1
-
t(CK) / 2
QSPI clock high and low
-
t(CK) / 2
-
-
t(CK) / 2 + 1
Data input setup time
Data input hold time
-
1.5
3
-
-
th(IN)
-
-
ns
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
-
-
0.5
0.5
-
1
3
0
tv(OUT)
Data output valid time
-
th(OUT)
Data output hold time
0
1. Guaranteed by characterization results.
(1)
Table 71. QSPI dynamic characteristics in DDR mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7 V < VDD < 3.6 V
Cload = 20 pF
-
-
80
fSCK
1/tc(SCK)
QSPI clock frequency
MHz
1.71 V< VDD < 3.6 V
Cload = 15 pF
-
-
70
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(1)
Table 71. QSPI dynamic characteristics in DDR mode (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tw(CKH)
tw(CKL)
t
(CK) / 2 - 1
-
t(CK) / 2
QSPI clock high and low time
-
t(CK) / 2
-
t(CK) / 2 + 1
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
2.7 V<VDD<3.6 V
1.71 V<VDD<3.6 V
2.7 V<VDD<3.6 V
1.71 V<VDD<3.6 V
0.5
0.5
2
-
-
-
tsr(IN),
tsf(IN)
Data input setup time
Data input hold time
-
-
-
-
thr(IN),
thf(IN)
ns
2
-
-
8.5
8.5
9
tvr(OUT),
tvf(OUT)
Data output valid time
Data output hold time
-
11.5
thr(OUT),
thf(OUT)
-
7.5
-
-
1. Guaranteed by characterization results.
USB OTG full speed (FS) characteristics
This interface is present in USB OTG FS controller.
Table 72. USB OTG FS startup time
Parameter
USB OTG FS transceiver startup time
Symbol
Max
Unit
µs
(1)
tSTARTUP
1
1. Guaranteed by design.
Table 73. USB OTG FS DC electrical characteristics
Symbol
VDD
Parameter
Conditions
Min.(1) Typ. Max.(1) Unit
USB OTG FS operating
voltage
3.0(2)
0.2
-
-
-
3.6
-
V
(3)
VDI
Differential input sensitivity
I(USB_FS_DP/DM)
Includes VDI range
Input
Differential common mode
range
(3)
levels
VCM
0.8
2.5
V
Single ended receiver
threshold
(3)
VSE
1.3
-
2.0
VOL Static output level low
VOH Static output level high
RL of 1.5 kΩto 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
V
(4)
RL of 15 kΩto VSS
2.8
PA11, PA12
(USB_FS_DM/DP)
17
0.65
1.5
21
1.1
1.8
24
2.0
2.1
RPD
VIN = VDD
PA9 (OTG_FS_VBUS)
kΩ
PA11, PA12
(USB_FS_DM/DP)
VIN = VSS
VIN = VSS
RPU
PA9 (OTG_FS_VBUS)
0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
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2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design.
RL is the load connected on the USB OTG FS drivers.
4.
When VBUS sensing feature is enabled, PA9 should be left at their default state (floating
input), not as alternate function. A typical 200 µA current consumption of the embedded
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 when the feature is enabled.
Note:
Figure 47. USB OTG FS timings: definition of data signal rise and fall time
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Table 74. USB OTG FS electrical characteristics(1)
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -
Chapter 7 (version 2.0).
2.
CAN (controller area network) interface
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
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6.3.20
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 75 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 17.
Table 75. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
-
-
-
3.6
VDDA
-
VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage
V
VREF-
Negative reference voltage
-
0
VDDA = 1.7(1) to 2.4 V
0.6
15
18
MHz
MHz
fADC
ADC clock frequency
VDDA = 2.4 to 3.6 V
0.6
30
-
36
fADC = 30 MHz,
-
-
1764
17
kHz
1/fADC
V
(2)
12-bit resolution
fTRIG
External trigger frequency
Conversion voltage range(3)
-
-
0 (VSSA or VREF-
tied to ground)
VAIN
-
-
VREF+
See Equation 1 for
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
50
6
kΩ
kΩ
pF
details
(2)(4)
RADC
-
-
Internal sample and hold
capacitor
(2)
CADC
4
7
f
f
ADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
-
ADC = 30 MHz
-
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
0.100
-
(2)
tS
Sampling time
Power-up time
-
-
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
2
fADC = 30 MHz
12-bit resolution
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
f
ADC = 30 MHz
10-bit resolution
ADC = 30 MHz
8-bit resolution
ADC = 30 MHz
6-bit resolution
Total conversion time (including
sampling time)
f
(2)
tCONV
µs
f
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
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Electrical characteristics
Table 75. ADC characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Unit
12-bit resolution
Single ADC
-
-
2
Msps
12-bit resolution
Sampling rate
-
-
3.75
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
-
-
6
Msps
µA
Interleave Triple ADC
mode
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
-
-
300
1.6
500
1.8
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
mA
1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 75.
Equation 1: R
max formula
AIN
(k – 0.5)
RAIN = ---------------------------------------------------------------- – RADC
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
(1)
Table 76. ADC accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(2)
Unit
ET
Total unadjusted error
±3
±4
f
ADC =18 MHz
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization results.
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Electrical characteristics
Symbol
STM32F413xG/H
(1)
Table 77. ADC accuracy at f
= 30 MHz
ADC
Parameter
Test conditions
Typ
Max(2)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±4
f
ADC = 30 MHz,
±1.5
±1.5
±1
RAIN < 10 kΩ,
Gain error
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
LSB
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization results.
(1)
Table 78. ADC accuracy at f
= 36 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(2)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
V
DDA = 2.4 to 3.6 V,
LSB
Gain error
VREF = 1.7 to 3.6 V
Differential linearity error
Integral linearity error
VDDA −VREF < 1.2 V
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Guaranteed by characterization results.
(1)
Table 79. ADC dynamic accuracy at f
Parameter
= 18 MHz - limited test conditions
ADC
Symbol
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
10.3
64
64
-
10.4
64.2
65
-
-
bits
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 kHz
Temperature = 25 °C
-
dB
THD
Total harmonic distortion
-72
-67
1. Guaranteed by characterization results.
(1)
Table 80. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
64
-
10.8
67
-
-
bits
fADC = 36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 kHz
Temperature = 25 °C
68
-
dB
THD
Total harmonic distortion
-72
-70
1. Guaranteed by characterization results.
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Electrical characteristics
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.16 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
Figure 48. ADC accuracy characteristics
6
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1. See also Table 77.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
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STM32F413xG/H
Figure 49. Typical connection diagram using the ADC
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1. Refer to Table 75 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
f
ADC should be reduced.
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Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA
.
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Electrical characteristics
STM32F413xG/H
Figure 51. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA
.
6.3.21
Temperature sensor characteristics
Table 81. Temperature sensor characteristics
Symbol
Parameter
Min
Typ Max
Unit
(1)
TL
VSENSE linearity with temperature
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
-
(1)
V25
Voltage at 25 °C
Startup time
-
-
10
-
(2)
tSTART
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 82. Temperature sensor calibration values
Symbol
Parameter
Memory address
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
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Electrical characteristics
6.3.22
V
monitoring characteristics
BAT
Table 83. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
Ratio on VBAT measurement
Error on Q
Er(1)
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23
Embedded reference voltage
The parameters given in Table 84 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 84. Embedded internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Max
Unit
Typ
Internal reference voltage
–40 °C < TA < +125 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
-
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
(2)
TCoeff
Temperature coefficient
Startup time
-
-
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design
Table 85. Internal reference voltage calibration values
Symbol
Parameter
Memory address
Raw data acquired at temperature of
30 °C VDDA = 3.3 V
VREFIN_CAL
0x1FFF 7A2A - 0x1FFF 7A2B
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6.3.24
DAC electrical characteristics
Table 86. DAC characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
Comments
Analog supply
voltage
VDDA
-
1.7(1)
-
3.6
V
Reference supply
voltage
VREF+
VSSA
-
-
1.7(1)
0
-
-
3.6
0
V
V
VREF+ ≤VDDA
Ground
-
RLOAD
connected
to VSSA
5
-
-
-
-
kΩ -
kΩ -
DAC
output
buffer ON
(2)
RLOAD
Resistive load
RLOAD
connected 25
to VDDA
When the buffer is OFF, the
Impedance output
with buffer OFF
Minimum resistive load between
DAC_OUT and VSS to have a 1%
accuracy is 1.5 MΩ
(2)
RO
-
-
-
15
kΩ
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
(2)
CLOAD
Capacitive load
-
-
-
-
-
50
-
Lower DAC_OUT
voltage with buffer
ON
It gives the maximum output
excursion of the DAC.
DAC_OUT
min(2)
0.2
V
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x1C7) to
(0xE38) at VREF+ = 1.7 V
Higher DAC_OUT
voltage with buffer
ON
DAC_OUT
max(2)
VDDA
− 0.2
-
-
-
-
-
-
-
-
-
0.5
-
V
mV
V
Lower DAC_OUT
voltage with buffer
OFF
DAC_OUT
min(2)
-
It gives the maximum output
excursion of the DAC.
Higher DAC_OUT
voltage with buffer
OFF
VREF+
−
1LSB
DAC_OUT
max(2)
With no load, worst code (0x800)
at VREF+ = 3.6 V in terms of DC
consumption on the inputs
DAC DC VREF
current
consumption in
quiescent mode
(Standby mode)
170
240
(4)
IVREF+
µA
µA
With no load, worst code (0xF1C)
at VREF+ = 3.6 V in terms of DC
consumption on the inputs
-
-
-
-
-
-
50
75
With no load, middle code
(0x800) on the inputs
280
475
380
625
DAC DC VDDA
current
(4)
IDDA
With no load, worst code (0xF1C)
µA at VREF+ = 3.6 V in terms of DC
consumption on the inputs
consumption in
quiescent mode(3)
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Electrical characteristics
Comments
Table 86. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
Differential non
Given for the DAC in 10-bit
configuration.
-
-
-
±0.5 LSB
linearity Difference
DNL(4) between two
consecutive code-
1LSB)
Given for the DAC in 12-bit
configuration.
-
-
-
-
-
-
±2
±1
LSB
LSB
Integral non
linearity (difference
between measured
value at Code i and
INL(4) the value at Code i
on a line drawn
Given for the DAC in 10-bit
configuration.
Given for the DAC in 12-bit
configuration.
-
-
-
±4
LSB
between Code 0
and last Code
1023)
Given for the DAC in 12-bit
configuration
Offset error
-
-
-
-
-
-
-
-
-
-
-
-
±10 mV
(difference between
Given for the DAC in 10-bit at
VREF+ = 3.6 V
measured value at
Offset(4)
±3
LSB
Code (0x800) and
the ideal value =
VREF+/2)
Given for the DAC in 12-bit at
±12 LSB
VREF+ = 3.6 V
Gain
Given for the DAC in 12-bit
configuration
Gain error
error(4)
±0.5
%
Settling time (full
scale: for a 10-bit
input code transition
(
tSETTLING between the lowest
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
-
-
3
6
µs
4)
and the highest
input codes when
DAC_OUT reaches
final value ±4LSB
Total Harmonic
Distortion
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4)
-
-
-
-
-
-
-
dB
Buffer ON
Max frequency for a
correct DAC_OUT
Update change when small
rate(2) variation in the input
code (from code i to
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
1
MS/s
i+1LSB)
Wakeup time from
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
off state (Setting the
ENx bit in the DAC
Control register)
(4)
tWAKEUP
-
-
-
-
6.5
10
µs
Power supply
rejection ratio (to
VDDA) (static DC
measurement)
PSRR+ (2)
–67
–40
dB No RLOAD, CLOAD = 50 pF
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STM32F413xG/H
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization results.
Figure 52. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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6.3.25
DFSDM characteristics
Unless otherwise specified, the parameters given in Table 87 for DFSDM are derived from
tests performed under the ambient temperature, f
frequency and V supply voltage
APB2
DD
conditions summarized in Table 17: General operating conditions.
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 * V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
(1)
Table 87. DFSDM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK DFSDM clock
1.71 < VDD < 3.6 V
-
-
fSYSCLK
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0,
1.71 < VDD < 3.6 V
20
-
-
-
-
(fDFBDMCLK / 4
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0,
2.7 < VDD < 3.6 V
20
(fDFBDMCLK / 4
fCKIN
(1/TCKIN
Input clock
frequency
)
MHz
SPI mode
(SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] ≠ 0,
1.71 < VDD < 3.6 V
20
-
-
-
-
(fDFBDMCLK / 4
SPI mode (SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] ≠ 0,
2.7 < VDD < 3.6 V
20
(fDFBDMCLK / 4
Output clock
frequency
fCKOUT
1.71 < VDD < 3.6 V
1.71 < VDD < 3.6 V
-
-
20
55
Output clock
DuCyCKOUT frequency duty
cycle
45
50
%
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Electrical characteristics
STM32F413xG/H
(1)
Table 87. DFSDM characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI mode
(SITP[1:0] = 01),
twh(CKIN) Input clock high
External clock mode
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
t
CKIN / 2 - 0.5
tCKIN / 2
-
twl(CKIN)
and low time
SPI mode
(SITP[1:0]=01),
Data input
setup time
tsu
External clock mode
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
3.5
2.5
-
-
-
-
-
ns
SPI mode
(SITP[1:0]=01),
External clock mode
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
Data input hold
time
th
Manchester mode
(SITP[1:0] = 10 or 11),
Internal clock mode
(SPICKSEL[1:0] ≠ 0)
1.71 < VDD < 3.6 V
Manchester
data period
(recovered
clock period)
(CKOUTDIV + 1)
* tDFBDMCLK
(2 * CKOUTDIV
) * tDFBDMCLK
TManchester
1. Data based on characterization results.
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Electrical characteristics
Figure 16: DFSDM timing diagram
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Electrical characteristics
STM32F413xG/H
6.3.26
FSMC characteristics
Unless otherwise specified, the parameters given in Table 88 to Table 95 for the FSMC
interface are derived from tests performed under the ambient temperature, f frequency
HCLK
and V supply voltage conditions summarized in Table 16, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitance load C = 30 pF
Measurement points are done at CMOS levels: 0.5.V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 53 through Figure 56 represent asynchronous waveforms and Table 88 through
Table 95 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
In all timing tables, the T
is the HCLK clock period.
HCLK
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Electrical characteristics
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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Electrical characteristics
STM32F413xG/H
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
(1)(2)
read timings
Parameter
FSMC_NE low time
Symbol
Min
2 * tHCLK - 1 2 * tHCLK + 1
0.5
2 * tHCLK - 1 2 * tHCLK + 1
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
0
FSMC_NOE high to FSMC_NE high hold
time
th(NE_NOE)
0
-
tv(A_NE)
th(A_NOE)
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
-
0.5
0
-
tv(BL_NE)
-
0.5
ns
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
0
-
tHCLK - 2
-
tHCLK - 2
-
0
0
-
-
-
0
-
tHCLK + 1
1. CL = 30 pF.
2. Based on characterization.
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
7 * tHCLK + 1 7 * tHCLK + 1
tw(NOE)
FSMC_NWE low time
FSMC_NWAIT low time
5 * tHCLK - 1
tHCLK - 0.5
5 * tHCLK + 1
-
tw(NWAIT)
ns
FSMC_NWAIT valid before FSMC_NEx
high
tsu(NWAIT_NE)
5 * tHCLK + 1.5
4 * tHCLK + 1
-
-
FSMC_NEx hold time after
FSMC_NWAIT invalid
th(NE_NWAIT)
1. CL = 30 pF.
2. Based on characterization.
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Electrical characteristics
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
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1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
(1)(2)
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
Parameter
Min
Max
Unit
FSMC_NE low time
3 * tHclk - 1
3 * tHclk - 1
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
tHCLK - 1
tHCLK + 0.5
tHCLK - 1.5
tHCLK + 0.5
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
Data to FSMC_NEx low to Data valid
tHCLK
-
-
0
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
tHCLK - 0.5
-
ns
-
0.5
tHCLK - 0.5
-
-
tHCLK + 2.5
th(Data_NWE) Data hold time after FSMC_NWE high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tHCLK
-
0
-
-
tw(NADV)
FSMC_NADV low time
tHCLK + 1
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Electrical characteristics
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1. CL = 30 pF.
2. Based on characterization.
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
FSMC_NWE low time
8 * tHCLK - 1
8 * tHCLK + 1
tw(NWE)
6 * tHCLK - 1.5 6 * tHCLK + 0.5
ns
tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6 * tHCLK - 1
-
-
FSMC_NEx hold time after FSMC_NWAIT
th(NE_NWAIT)
4 * tHCLK + 2
invalid
1. CL = 30 pF.
2. Based on characterization.
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms
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Electrical characteristics
(1)(2)
Table 92. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
FSMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
3 * tHCLK - 1
2 * tHCLK
3 * tHCLK + 1
2 * tHCLK + 0.5
tHCLK + 1
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
tHCLK - 1
FSMC_NOE high to FSMC_NE high hold
time
th(NE_NOE)
tv(A_NE)
0
-
FSMC_NEx low to FSMC_A valid
-
0.5
0.5
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
0
tw(NADV)
FSMC_NADV low time
tHCLK - 0.5
tHCLK + 1
FSMC_AD(address) valid hold time after
FSMC_NADV high)
ns
th(AD_NADV)
tHCLK + 0.5
-
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
tHCLK - 0.5
-
0
-
-
0.5
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
tHCLK - 2
-
-
-
-
tHCLK - 2
th(Data_NE)
Data hold time after FSMC_NEx high
0
0
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 30 pF.
2. Based on characterization.
(1)(2)
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
8 * tHCLK + 1
tw(NE)
FSMC_NE low time
8 * tHCLK - 1
tw(NOE)
FSMC_NWE low time
5 * tHCLK - 1.5 5 * tHCLK + 0.5
ns
FSMC_NWAIT valid before FSMC_NEx
high
tsu(NWAIT_NE)
5 * tHCLK + 1.5
4 * tHCLK + 1
-
-
FSMC_NEx hold time after
FSMC_NWAIT invalid
th(NE_NWAIT)
1. CL = 30 pF.
2. Based on characterization.
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Electrical characteristics
STM32F413xG/H
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms
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DocID029162 Rev 5
STM32F413xG/H
Electrical characteristics
(1)(2)
Table 94. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
4 * THCLK - 1
THCLK - 1
4 * THCLK + 1
THCLK + 0.5
tv(NWE_NE) FSMC_NEx low to FSMC_NWE low
tw(NWE) FSMC_NWE low time
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time
tv(A_NE) FSMC_NEx low to FSMC_A valid
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
2 * THCLK - 0.5 2 * THCLK - 0.5
THCLK - 0.5
-
-
0
0
0.5
tw(NADV)
th(AD_NADV)
th(A_NWE)
FSMC_NADV low time
THCLK
THCLK + 1
ns
FSMC_AD (address) valid hold time after FSMC_NADV
high)
T
HCLK + 0.5
-
Address hold time after FSMC_NWE high
THCLK + 0.5
-
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high
tv(BL_NE) FSMC_NEx low to FSMC_BL valid
THCLK - 0.5
-
-
-
0.5
tv(Data_NADV) FSMC_NADV high to Data valid
THCLK + 2.5
-
th(Data_NWE) Data hold time after FSMC_NWE high
THCLK
1. CL = 30 pF.
2. Guaranteed by characterization results.
(1)(2)
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
9 * THCLK - 1
9 * THCLK + 1
ns
tw(NWE)
tsu(NWAIT_NE)
th(NE_NWAIT)
1. CL = 30 pF.
FSMC_NWE low time
7 * THCLK - 0.5 7 * THCLK + 0.5
FSMC_NWAIT valid before FSMC_NEx high
FSMC_NEx hold time after FSMC_NWAIT invalid
6 * THCLK + 2
4 * THCLK - 1
-
-
2. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 57 through Figure 60 represent synchronous waveforms and Table 96 through
Table 99 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
•
•
•
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
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Electrical characteristics
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In all timing tables, the T
is the HCLK clock period (with maximum
HCLK
FSMC_CLK = 90 MHz).
Figure 57. Synchronous multiplexed NOR/PSRAM read timings
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Electrical characteristics
(1)(2)
Table 96. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2 * THCLK - 0.5
-
2
-
td(CLKL-NExL)
td(CLKH_NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
FSMC_CLK low to FSMC_NADV low
-
THCLK + 0.5
-
1
-
FSMC_CLK low to FSMC_NADV high
0
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
-
2.5
-
td(CLKH-AIV)
THCLK
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(NWAIT-CLKH)
th(CLKH-NWAIT)
-
1.5
-
ns
FSMC_CLK high to FSMC_NOE high
THCLK - 0.5
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data before FSMC_CLK high
FSMC_A/D[15:0] valid data after FSMC_CLK high
FSMC_NWAIT valid before FSMC_CLK high
FSMC_NWAIT valid after FSMC_CLK high
-
3
-
0
1.5
3.5
2.5
3.5
-
-
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Electrical characteristics
STM32F413xG/H
Figure 58. Synchronous multiplexed PSRAM write timings
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STM32F413xG/H
Symbol
Electrical characteristics
(1)(2)
Table 97. Synchronous multiplexed PSRAM write timings
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period, VDD range= 2.7 to 3.6 V
FSMC_CLK low to FSMC_NEx low (x= 0...2)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
2 * THCLK - 0.5
-
2
-
td(CLKL-NExL)
td(CLKH-NExH)
-
THCLK + 0.5
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
1
-
0
td(CLKL-AV)
td(CLKH-AIV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NWE low
-
2.5
-
THCLK
td(CLKL-NWEL)
t(CLKH-NWEH)
td(CLKL-ADV)
td(CLKL-ADIV)
td(CLKL-DATA)
td(CLKL-NBLL)
td(CLKH-NBLH)
-
1.5
-
ns
FSMC_CLK high to FSMC_NWE high
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL low
THCLK + 0.5
-
3
-
0
-
4
2
-
0
FSMC_CLK high to FSMC_NBL high
THCLK + 0.5
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
-
3.5
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Electrical characteristics
STM32F413xG/H
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings
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(1)(2)
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK – 0.5
-
t(CLKL-NExL)
td(CLKH-NExH)
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK high to FSMC_NEx high (x= 0…2)
-
2
THCLK +0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
0.5
0
-
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
-
2.5
THCLK
-
ns
-
THCLK - 0.5
1.5
1.5
FSMC_CLK high to FSMC_NOE high
-
-
-
-
-
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
3.5
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2.5
3.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Electrical characteristics
Figure 60. Synchronous non-multiplexed PSRAM write timings
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(1)(2)
Table 99. Synchronous non-multiplexed PSRAM write timings
Parameter Min
Symbol
Max
Unit
tw(CLK)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
2 * THCLK - 0.5
-
2
td(CLKL-NExL)
-
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
THCLK + 0.5
-
-
0.5
-
0
td(CLKL-AV)
td(CLKH-AIV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
-
2.5
-
THCLK
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
-
1.5
-
THCLK + 1
td(CLKL-Data)
td(CLKL-NBLL)
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL low
-
4
-
2
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
THCLK + 1
-
2
-
3.5
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
DocID029162 Rev 5
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174
Electrical characteristics
STM32F413xG/H
6.3.27
SD/SDIO MMC/eMMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 100 for the SDIO are derived
from tests performed under the ambient temperature, f
frequency and V supply
PCLK2
DD
voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Figure 61. SDIO high-speed mode
T
T
R
F
T
#
T
T
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#+
T
T
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/($
$ꢒ #-$
ꢎOUTPUTꢏ
AIꢀꢇꢃꢃꢃ
172/207
DocID029162 Rev 5
STM32F413xG/H
Symbol
Electrical characteristics
(1)(2)
Table 100. SD / MMC characteristics
Parameter
Clock frequency in data transfer mode
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
-
0
-
-
50
MHz
-
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
8 / 3
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
5
1
-
-
-
-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
12
-
13.5
-
10.5
CMD, D inputs (referenced to CK) in SD default mode
5
1
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp =25MHz
fpp =25MHz
ns
ns
CMD, D outputs (referenced to CK) in SD default mode
-
2
-
3
-
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =25 MHz
fpp =25 MHz
1
1. Guaranteed by characterization results.
2. VDD = 2.7 to 3.6 V.
(1)(2)
Typ
Table 101. eMMC characteristics V = 1.7 V to 1.9 V
DD
Symbol
Parameter
Conditions
Min
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
-
-
0
-
-
-
50
MHz
-
8 / 3
fpp =50MHz
fpp =50MHz
9.5
8.5
10.5
9.5
-
-
ns
ns
ns
Clock high time
CMD, D inputs (referenced to CK) in eMMC mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =50MHz
fpp =50MHz
3
-
-
-
-
2.5
CMD, D outputs (referenced to CK) in eMMC mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =50MHz
fpp =50MHz
-
15
-
15.5
-
13
1. Guaranteed by characterization results.
2. CLOAD = 20 pF.
DocID029162 Rev 5
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174
Electrical characteristics
STM32F413xG/H
6.3.28
RTC characteristics
Table 102. RTC characteristics
Symbol
Parameter
Conditions
Min
Max
Any read/write operation
from/to an RTC register
-
fPCLK1/RTCCLK frequency ratio
4
-
174/207
DocID029162 Rev 5
STM32F413xG/H
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
WLCSP81 package information
Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package outline
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1. Drawing is not to scale.
DocID029162 Rev 5
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205
Package information
STM32F413xG/H
Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
0.555
0.175
0.380
0.025
0.250
4.039
3.951
0.400
3.200
3.200
0.4195
0.3755
-
Max
Min
Typ
0.0219
0.0069
0.0150
0.0010
0.0098
0.1590
0.1556
0.0157
0.1260
0.1260
0.0165
0.0148
-
Max
A
A1
A2
A3(2)
Ø b(3)
D
0.525
0.585
0.0207
0.0230
-
-
-
-
-
-
-
-
-
-
-
-
0.220
0.280
4.074
3.986
-
0.0087
0.0110
0.1604
0.1569
-
4.004
0.1576
E
3.916
0.1542
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
-
-
e2
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
176/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint
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Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
Pitch
Dpad
0.4 mm
0.225 mm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.250 mm
0.100 mm
DocID029162 Rev 5
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205
Package information
STM32F413xG/H
Device marking for WLCSP81
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 65. WLCSP81 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
7.2
UFQFPN48 package information
Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DocID029162 Rev 5
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Package information
STM32F413xG/H
Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters
inches(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
-
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
-
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
-
0.080
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 67. UFQFPN48 recommended footprint
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1. Dimensions are in millimeters.
180/207
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STM32F413xG/H
Package information
Device marking for UFQFPN48
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 68. UFQFPN48 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DocID029162 Rev 5
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Package information
STM32F413xG/H
7.3
LQFP64 package information
Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
6($7,1*ꢉ3/$1(
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1. Drawing is not to scale.
182/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
millimeters
inches(1)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.600
-
-
0.0630
0.050
-
0.150
0.0020
-
0.0059
1.350
1.400
0.220
-
1.450
0.0531
0.0551
0.0087
-
0.0571
0.170
0.270
0.0067
0.0106
c
0.090
0.200
0.0035
0.0079
D
-
12.000
10.000
7.500
12.000
10.000
7.500
0.500
3.5°
-
-
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
3.5°
-
D1
D3
E
-
-
-
-
-
-
-
-
-
-
-
-
E1
E3
e
-
-
-
-
-
-
-
-
-
-
7°
-
-
7°
Κ
0°
0°
L
0.450
0.600
1.000
-
0.750
-
0.0177
0.0236
0.0394
-
0.0295
-
L1
ccc
-
-
-
-
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID029162 Rev 5
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205
Package information
STM32F413xG/H
Figure 70. LQFP64 recommended footprint
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1. Dimensions are in millimeters.
184/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Device marking for LQFP64
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 71. LQFP64 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DocID029162 Rev 5
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205
Package information
STM32F413xG/H
7.4
LQFP100 package information
Figure 72. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline
3%!4).' 0,!.%
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1. Drawing is not to scale. Dimensions are in millimeters.
Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
0.6299
0.5512
0.4724
0.6299
D1
D3
E
15.800
16.200
0.6220
0.6378
186/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data (continued)
millimeters
inches(1)
Typ
Symbol
Min
Typ
Max
Min
Max
E1
E3
e
13.800
14.000
12.000
0.500
0.600
1.000
3.5°
14.200
0.5433
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
0.5591
-
-
-
-
-
-
-
-
L
0.450
0.750
-
0.0177
0.0295
-
L1
k
-
0.0°
-
-
0.0°
-
7.0°
0.080
7.0°
0.0031
ccc
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
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1. Dimensions are in millimeters.
DocID029162 Rev 5
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205
Package information
STM32F413xG/H
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 74. LQFP100 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
7.5
LQFP144 package information
Figure 75. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline
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1. Drawing is not to scale.
DocID029162 Rev 5
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Package information
STM32F413xG/H
Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
190/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint
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1. Dimensions are expressed in millimeters.
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Package information
STM32F413xG/H
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 77. LQFP144 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
192/207
DocID029162 Rev 5
STM32F413xG/H
Package information
7.6
UFBGA100 package information
Figure 78. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline
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1. Drawing is not to scale.
Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.450
0.130
0.320
0.290
7.000
5.500
7.000
5.500
0.500
0.750
-
-
0.0177
0.0051
0.0126
0.0114
0.2756
0.2165
0.2756
0.2165
0.0197
0.0295
-
-
-
-
0.0094
-
-
-
-
0.240
0.340
0.0094
0.0134
D
6.850
7.150
0.2697
0.2815
D1
E
-
-
-
-
6.850
7.150
0.2697
0.2815
E1
e
-
-
-
-
-
-
-
-
-
-
-
Z
-
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Package information
STM32F413xG/H
Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
ddd
eee
fff
-
-
-
-
-
-
0.080
0.150
0.050
-
-
-
-
-
-
0.0031
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 79. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint
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Table 110. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.280 mm
0.370 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
0.280 mm
Between 0.100 mm and 0.125 mm
194/207
DocID029162 Rev 5
STM32F413xG/H
Package information
Device marking for UFBGA100
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 80. UFBGA100 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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Package information
STM32F413xG/H
7.7
UFBGA144 package information
Figure 81. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline
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1. Drawing is not to scale.
Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid
array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.400
10.000
8.800
10.000
8.800
0.800
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0236
0.0043
0.0197
-
-
-
-
-
0.360
9.950
8.750
9.950
8.750
0.750
0.440
10.050
8.850
10.050
8.850
0.850
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
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DocID029162 Rev 5
STM32F413xG/H
Package information
Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid
array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
F
0.550
0.600
0.650
0.080
0.150
0.080
0.0177
0.0197
0.0217
0.0039
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 82. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint
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Table 112. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.80 mm
0.400 mm
0.550 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Note:
Non solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
Stencil opening is 0.400 mm.
Stencil thickness is between 0.100 mm and 0.125 mm.
Pad trace width is 0.120 mm.
DocID029162 Rev 5
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Package information
STM32F413xG/H
Device marking for UFBGA144
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 83. UFBGA144 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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DocID029162 Rev 5
STM32F413xG/H
Package information
7.8
Thermal characteristics
The maximum chip junction temperature (T max) must never exceed the values given in
J
Table 17: General operating conditions.
The maximum chip-junction temperature, T max., in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (PD max x Θ )
J
A
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
PD max is the sum of P
max and P max (PD max = P
max + P max),
INT I/O
INT
I/O
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 113. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm
35
43
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm
47
Thermal resistance junction-ambient
UFBGA144 - 10 x 10 mm / 0.8 mm pitch
Θ
48
°C/W
JA
Thermal resistance junction-ambient
UFBGA100 - 7 x 7 mm
57
Thermal resistance junction-ambient
WLCSP81 - 4.039 x 3.951 mm
39.7
32
Thermal resistance junction-ambient
UFQFPN48 - 7 x 7 mm
7.8.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID029162 Rev 5
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Ordering information
STM32F413xG/H
8
Ordering information
Table 114. Ordering information scheme
STM32 F 413 C H T
Example:
6
TR
Device family
®
STM32 = ARM -based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
413 = 413 line
Pin count
C = 48 pins
R = 64 pins
M = 81 pins
V = 100 pins
Z = 144 pins
Flash memory size
G = 1024 Kbytes of Flash memory
H = 1536 Kbytes of Flash memory
Package
H = UFBGA 7 x 7 mm
J = UFBGA 10 x 10 mm
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, – 40 to 85 °C
3 = Industrial temperature range, – 40 to 125 °C
Packing
TR = tape and reel
No character = tray or tube
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STM32F413xG/H
Recommendations when using the internal reset OFF
Appendix A
Recommendations when using the internal
reset OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
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Application block diagrams
STM32F413xG/H
Appendix B
Application block diagrams
B.1
Sensor Hub application example
Figure 84. Sensor Hub application example
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202/207
DocID029162 Rev 5
STM32F413xG/H
Application block diagrams
B.2
Display application example
Figure 85. Display application example
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Note:
16 bit displays interfaces can be addressed with 100 and 144 pins packages.
MSv40843
DocID029162 Rev 5
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205
Application block diagrams
STM32F413xG/H
B.3
USB OTG full speed (FS) interface solutions
Figure 86. USB controller configured as peripheral-only and used in Full speed mode
9''
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1. External voltage regulator only needed when building a VBUS powered device.
Figure 87. USB peripheral-only Full speed mode with direct connection
for VBUS sense
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1. External voltage regulator only needed when building a VBUS powered device.
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DocID029162 Rev 5
STM32F413xG/H
Application block diagrams
Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO
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1. External voltage regulator only needed when building a VBUS powered device.
Figure 89. USB controller configured as host-only and used in full speed mode
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2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
DocID029162 Rev 5
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205
Revision history
STM32F413xG/H
Revision history
Table 115. Document revision history
Date
Revision
Changes
29-Aug-2016
1
Initial release.
Updated:
– Table 10: STM32F413xG/H pin definition
– Section 7: Package information
21-Oct-2016
2
– Figure 65: WLCSP81 marking example (package top
view)
Updated:
– Table 39: Peripheral current consumption
– Table 55: EMI characteristics for LQFP144
– Table 56: ESD absolute maximum ratings
– Table 70: QSPI dynamic characteristics in SDR mode
13-Dec-2016
3
– Table 111: UFBGA144 - 144-ball, 10 x 10 mm,
0.80 mm pitch, ultra fine pitch ball grid array package
mechanical data
– Figure 81: UFBGA144 - 144-pin, 10 x 10 mm,
0.80 mm pitch, ultra fine pitch ball grid array package
outline
Updated:
– Table 2: STM32F413xG/H features and peripheral
counts
09-Mar-2017
4
– Table 12: STM32F413xG/H alternate functions
Added:
– Table 11: FSMC pin definition
Added:
– Section 4.1: WLCSP81 pinout description
– Section 4.2: UFQFPN48 pinout description
– Section 4.3: LQFP64 pinout description
– Section 4.4: LQFP100 pinout description
– Section 4.5: LQFP144 pinout description
– Section 4.6: UFBGA100 pinout description
– Section 4.7: UFBGA144 pinout description
– Section 4.8: Pins definition
14-Jun-2017
5
– Section 4.9: Alternate functions
Updated:
– Table 10: STM32F413xG/H pin definition
– Table 11: FSMC pin definition
– Table 38: Switching output I/O current consumption
– Table 39: Peripheral current consumption
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DocID029162 Rev 5
STM32F413xG/H
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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