STM32F429BG [STMICROELECTRONICS]
ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT;型号: | STM32F429BG |
厂家: | ST |
描述: | ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT CD |
文件: | 总239页 (文件大小:3112K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM32F427xx
STM32F429xx
ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
Datasheet - production data
Features
®
®
• Core: ARM 32-bit Cortex -M4 CPU with FPU,
Adaptive real-time accelerator (ART
&"'!
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
UFBGA176 (10 x 10 mm)
UFBGA169 (7 × 7 mm)
TFBGA216 (13 x 13 mm)
• Memories
WLCSP143
– Up to 2 MB of Flash memory organized into
LQFP208 (28 x 28 mm)
two banks allowing read-while-write
– Up to 256+4 KB of SRAM including 64-KB
of CCM (core coupled memory) data RAM
• Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 90 MHz
– Up to 166 5 V-tolerant I/Os
– Flexible external memory controller with up
to 32-bit data bus:
SRAM,PSRAM,SDRAM/LPSDR SDRAM ,
Compact Flash/NOR/NAND memories
• Up to 21 communication interfaces
2
– Up to 3 × I C interfaces (SMBus/PMBus)
• LCD parallel interface, 8080/6800 modes
– Up to 4 USARTs/4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
• LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for
enhanced graphic content creation (DMA2D)
– Up to 6 SPIs (45 Mbits/s), 2 with muxed
2
full-duplex I S for audio class accuracy via
• Clock, reset and supply management
internal audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface
• Advanced connectivity
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
– USB 2.0 full-speed device/host/OTG
accuracy)
controller with on-chip PHY
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Low power
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
•
– 10/100 Ethernet MAC with dedicated DMA:
– Sleep, Stop and Standby modes
supports IEEE 1588v2 hardware, MII/RMII
– V
supply for RTC, 20×32 bit backup
BAT
• 8- to 14-bit parallel camera interface up to
registers + optional 4 KB backup SRAM
54 Mbytes/s
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• True random number generator
• CRC calculation unit
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
• Debug mode
– SWD & JTAG interfaces
– Cortex-M4 Trace Macrocell™
July 2016
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This is information on a product in full production.
www.st.com
STM32F427xx STM32F429xx
Table 1. Device summary
Part number
Reference
STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI,
STM32F427II, STM32F427AI
STM32F427xx
STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG,
STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI,
STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE,
STM32F429NE
STM32F429xx
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Contents
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 20
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 20
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10 LCD-TFT controller (available only on STM32F429xx) . . . . . . . . . . . . . . 23
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 31
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 36
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 39
3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 39
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 40
3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 40
3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.40 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.41 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.42 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4
5
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating conditions at power-up / power-down (regulator ON) . . . . . . 97
Operating conditions at power-up / power-down (regulator OFF) . . . . . 97
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 98
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 116
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 126
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.23
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
BAT
6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 192
6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 192
6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 195
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6.3.30 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 226
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
B.1
B.2
B.3
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 227
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 229
Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
STM32F427xx and STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 28
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 31
Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32F427xx and STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 52
FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
STM32F427xx and STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 74
STM32F427xx and STM32F429xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 86
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 96
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 97
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 97
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM. . . . . . 101
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 103
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 104
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 105
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Typical and maximum current consumptions in V
mode. . . . . . . . . . . . . . . . . . . . . . . 105
BAT
Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Typical current consumption in Run mode, code with data processing running
Table 31.
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 108
Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 109
Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 110
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LSE
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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STM32F427xx STM32F429xx
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Flash memory programming with V
PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
2
I S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 153
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 154
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
ADC static accuracy at f
ADC static accuracy at f
ADC static accuracy at f
= 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
= 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
= 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC
ADC
ADC
ADC dynamic accuracy at f
ADC dynamic accuracy at f
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158
ADC
ADC
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
BAT
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
Table 87.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 170
Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
Table 88.
Table 89.
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 90.
Table 91.
Table 92.
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Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 174
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 178
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Switching characteristics for PC Card/CF read and write cycles
Table 99.
in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 106. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 107. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 108. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 109. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 198
Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 203
Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 217
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 220
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 121. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 122. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 123. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 226
Table 124. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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List of figures
STM32F427xx STM32F429xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F427xx and STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM32F427xx and STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 26
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Startup in regulator OFF: slow V slope
DD
- power-down reset risen after V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 10. Startup in regulator OFF mode: fast V slope
DD
- power-down reset risen before V
/V
stabilization . . . . . . . . . . . . . . . . . . . . . . 30
CAP_1 CAP_2
Figure 11. STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 12. STM32F42x WLCSP143 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 14. STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16. STM32F42x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 17. STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 18. STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 19. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 20. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 21. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 22. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 23. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 24. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
EXT
Figure 25. Typical V
Figure 26. Typical V
current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 106
current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 106
BAT
BAT
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 31. ACCHSI accuracy versus temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 32. ACC versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LSI
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 35. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 39. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 40. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
2
(1)
Figure 41. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2
(1)
Figure 42. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 43. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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List of figures
Figure 44. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 45. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 150
Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 52. Power supply and reference decoupling (V
Figure 53. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 161
). . . . . . . . . . . . . . . . 162
REF+
DDA
connected to V
REF+
DDA
Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 168
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 170
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 181
Figure 64. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . 181
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory
read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory
write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 183
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 184
Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 187
Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 187
Figure 73. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 74. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 79. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 197
Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 82. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 84. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 85. WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 204
Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 88. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 208
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12
List of figures
STM32F427xx STM32F429xx
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 210
Figure 91. LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 212
Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 94. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch
ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 97. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 100. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 102. TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 103. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 104. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 227
Figure 105. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 228
Figure 106. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 107. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 108. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 109. RMII with a 25 MHz crystal and PHY with PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
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STM32F427xx STM32F429xx
Introduction
1
Introduction
This datasheet provides the description of the STM32F427xx and STM32F429xx line of
microcontrollers. For more details on the whole STMicroelectronics STM32 family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
®
®
For information on the Cortex -M4 core, please refer to the Cortex -M4 programming
manual (PM0214), available from www.st.com.
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43
Description
STM32F427xx STM32F429xx
2
Description
®
The STM32F427xx and STM32F429xx devices are based on the high-performance ARM
®
Cortex -M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4
®
core features a Floating point unit (FPU) single precision which supports all ARM single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances application security.
The STM32F427xx and STM32F429xx devices incorporate high-speed embedded
memories (Flash memory up to 2 Mbyte, up to 256 kbytes of SRAM), up to 4 Kbytes of
backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
They also feature standard and advanced communication interfaces.
2
•
•
Up to three I Cs
2
2
Six SPIs, two I Ss full duplex. To achieve audio class accuracy, the I S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
•
•
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•
•
•
•
•
•
Two CANs
One SAI serial audio interface
An SDIO/MMC interface
Ethernet and camera interface
LCD-TFT display controller
Chrom-ART Accelerator™.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors. Refer to Table 2: STM32F427xx and STM32F429xx
features and peripheral counts for the list of peripherals available on each part number.
The STM32F427xx and STM32F429xx devices operates in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F427xx and STM32F429xx devices offer devices in 8 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
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These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a wide range of applications:
•
•
•
•
•
•
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Figure 4 shows the general block diagram of the device family.
Table 2. STM32F427xx and STM32F429xx features and peripheral counts
STM32F427
Vx
STM32F427
Zx
STM32F427 STM32F429 STM32F427
Ax Ax Ix
Peripherals
STM32F429Vx
STM32F429Zx
STM32F429Ix
STM32F429Bx
STM32F429Nx
Flash memory in Kbytes
1024 2048 512 1024 2048 1024 2048 512 1024 2048 1024 2048 1024 2048 1024 2048 512 1024 2048 512 1024 2048 512 1024 2048
System
256(112+16+64+64)
4
SRAM in
Kbytes
Backup
(1)
FMC memory controller
Ethernet
Yes
Yes
10
General-
purpose
Timers
Advanced
-control
2
Basic
2
Random number generator
Yes
Table 2. STM32F427xx and STM32F429xx features and peripheral counts (continued)
STM32F427
Vx
STM32F427
Zx
STM32F427 STM32F429 STM32F427
Peripherals
STM32F429Vx
STM32F429Zx
STM32F429Ix
STM32F429Bx
STM32F429Nx
Ax
Ax
Ix
2
(2)
(2)
SPI / I S
4/2 (full duplex)
6/2 (full duplex)
2
I C
3
USART/
UART
4/4
USBOTG
FS
Yes
Yes
Communication
interfaces
USBOTG
HS
CAN
SAI
2
1
SDIO
Yes
Yes
Camera interface
LCD-TFT (STM32F429xx
only)
No
Yes
No
Yes
No
Yes
No
Yes
Chrom-ART Accelerator™
GPIOs
Yes
82
114
130
140
168
3
12-bit ADC
Number of channels
16
24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency
Operating voltage
180 MHz
(3)
1.8 to 3.6 V
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Operating temperatures
Packages
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP100
UFBGA169
LQFP208
TFBGA216
1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. For UFBGA169 package, only SDRAM, NAND and multiplexed
static memories are supported.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3.
V
/V
minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset
DD DDA
OFF).
STM32F427xx STM32F429xx
Description
2.1
Full compatibility throughout the family
The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are
fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the
user to try different memory densities, peripherals, and performances (FPU, higher
frequency) for a greater degree of freedom during the development cycle.
The STM32F427xx and STM32F429xx devices maintain a close compatibility with the
whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F427xx
and STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices:
the two families do not have the same power scheme, and so their power pins are different.
Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as
only a few pins are impacted.
Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx,
STM32F2xx, and STM32F10xx families.
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package
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43
Description
STM32F427xx STM32F429xx
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package
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Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages
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STM32F427xx STM32F429xx
Description
Figure 4. STM32F427xx and STM32F429xx block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. The LCD-TFT is available only on STM32F429xx devices.
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STM32F427xx STM32F429xx
3
Functional overview
3.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
®
®
The ARM Cortex -M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
®
®
The ARM Cortex -M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F42x family is compatible with all ARM tools and software.
Figure 4 shows the general block diagram of the STM32F42x family.
Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
Note:
3.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
®
®
standard ARM Cortex -M4 with FPU processors. It balances the inherent performance
®
®
advantage of the ARM Cortex -M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
3.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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3.4
Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
3.5
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6
Embedded SRAM
All devices embed:
•
Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
•
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
3.7
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several high-speed
peripherals work simultaneously.
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Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix
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3.8
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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The DMA can be used with the main peripherals:
2
•
•
•
•
•
•
•
•
•
SPI and I S
2
I C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1.
3.9
Flexible memory controller (FMC)
All devices embed an FMC. It has four Chip Select outputs supporting the following modes:
PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND
Flash.
Functionality overview:
•
•
•
•
8-,16-, 32-bit data bus width
Read FIFO for SDRAM controller
Write FIFO
Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10
LCD-TFT controller (available only on STM32F429xx)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•
•
•
•
•
•
•
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
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3.11
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
•
•
•
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
®
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex -
M4 with FPU core.
•
•
•
•
•
•
•
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
3.14
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
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detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
2
class performance. In this case, the I S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
•
•
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
3.16
Power supply schemes
•
•
•
V
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
DD
enabled), provided externally through V pins.
DD
V
, V
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
DDA
SSA
blocks, RCs and PLL. V
and V
must be connected to V and V , respectively.
DDA
SSA DD SS
V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V is not present.
DD
Note:
V
/V
minimum value of 1.7 V is obtained with the use of an external power supply
DD DDA
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator
configuration mode versus device operating mode to identify the packages supporting this
option.
3.17
Power supply supervisor
3.17.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
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Functional overview
STM32F427xx STM32F429xx
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when V is below a specified threshold,
DD
V
or V
, without the need for an external reset circuit.
POR/PDR
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V /V power supply and compares it to the V threshold. An interrupt can be
DD DDA
PVD
generated when V /V
drops below the V
threshold and/or when V /V
is
DD DDA
PVD
DD DDA
higher than the V
threshold. The interrupt service routine can then generate a warning
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.17.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V and should maintain the device in
DD
reset mode as long as V is below a specified threshold. PDR_ON should be connected to
DD
this external power supply supervisor. Refer to Figure 6: Power supply supervisor
interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
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The V specified threshold, below which the device must be maintained under reset, is
DD
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
V
functionality is no more available and V
pin should be connected to V
.
DD
BAT
BAT
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal.
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Figure 7. PDR_ON control with internal reset OFF
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3.18
Voltage regulator
The regulator has four operating modes:
•
Regulator ON
–
–
–
Main regulator mode (MR)
Low power regulator (LPR)
Power-down
•
Regulator OFF
3.18.1
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
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The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
–
–
LPR operates in normal mode (default mode when LPR is ON)
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on V and V pin. Refer to
CAP_1
CAP_2
Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions.
All packages have the regulator ON feature.
(1)
Table 3. Voltage regulator configuration mode versus device operating mode
Voltage regulator
Run mode
Sleep mode
Stop mode
Standby mode
configuration
Normal mode
MR
MR
-
MR
MR
-
MR or LPR
-
Over-drive
mode(2)
-
-
-
Under-drive mode
MR or LPR
-
Power-down
mode
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.18.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V voltage source through V
and V
pins.
12
CAP_1
CAP_2
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 17: General operating
conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 22: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V . An external power
12
supply supervisor should be used to monitor the V of the logic power domain. PA0 pin
12
should be used for this purpose, and act as power-on reset on V power domain.
12
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Functional overview
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V logic power
domain which is not reset by the NRST pin.
12
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
•
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 8. Regulator OFF
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The following conditions must be respected:
•
V
should always be higher than V
and V
to avoid current injection
CAP_2
DD
CAP_1
between power domains.
•
If the time for V and V
to reach V minimum value is faster than the time for
CAP_1
CAP_2
12
V
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
DD
CAP_1
and V
reach V minimum value and until V reaches 1.7 V (see Figure 9).
12 DD
CAP_2
•
•
Otherwise, if the time for V
and V
to reach V minimum value is slower
CAP_2 12
CAP_1
than the time for V to reach 1.7 V, then PA0 could be asserted low externally (see
DD
Figure 10).
If V
and V
go below V minimum value and V is higher than 1.7 V, then a
CAP_2 12 DD
CAP_1
reset must be asserted on PA0 pin.
Note:
The minimum value of V depends on the maximum frequency targeted in the application
12
(see Table 17: General operating conditions).
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STM32F427xx STM32F429xx
Figure 9. Startup in regulator OFF: slow V slope
DD
- power-down reset risen after V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast V slope
DD
- power-down reset risen before V
/V
stabilization
CAP_1 CAP_2
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1. This figure is valid whatever the internal reset mode (ON or OFF).
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3.18.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON
Regulator OFF Internal reset ON Internal reset OFF
LQFP100
Yes
No
Yes
No
LQFP144,
LQFP208
Yes
Yes
PDR_ON
WLCSP143,
LQFP176,
UFBGA169,
UFBGA176,
TFBGA216
PDR_ON set to
VDD
connected to an
external power
supply supervisor
Yes
Yes
BYPASS_REGset BYPASS_REGset
to VSS to VDD
3.19
Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
•
•
•
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 3.20: Low-power modes). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 3.20: Low-power
modes).
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Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the V supply when present or from the V
pin.
DD
BAT
3.20
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
–
–
Normal mode (default mode when MR or LPR is enabled)
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Table 5. Voltage regulator modes in stop mode
Voltage regulator
Main regulator (MR)
Low-power regulator (LPR)
configuration
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
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3.21
VBAT operation
The V
pin allows to power the device V
domain from an external battery, an external
BAT
BAT
supercapacitor, or from V when no external battery and an external supercapacitor are
DD
present.
V
operation is activated when V is not present.
DD
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:
When the microcontroller is supplied from V , external interrupts and RTC alarm/events
BAT
do not exit it from V
operation.
BAT
When PDR_ON pin is not connected to V (Internal Reset OFF), the V
functionality is
BAT
DD
no more available and V
pin should be connected to VDD.
BAT
3.22
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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Table 6. Timer feature comparison
Max
Max
DMA
request
generation channels
Capture/
compare
timer
Complementary interface
clock
Timer
type
Counter Counter Prescaler
Timer
resolution
type
factor
output
clock
(MHz)
(MHz)
(1)
Any
Up,
integer
Advanced TIM1,
16-bit
Down, between1
Up/down
Yes
Yes
Yes
No
4
4
4
2
1
2
1
0
Yes
90
45
45
90
90
45
45
45
180
-control
TIM8
and
65536
Any
integer
Down, between1
Up,
TIM2,
TIM5
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
No
No
No
No
No
No
No
90/180
90/180
180
Up/down
and
65536
Any
integer
Down, between1
Up,
TIM3,
TIM4
Up/down
and
65536
Any
integer
between1
and
TIM9
Up
65536
General
purpose
Any
integer
between1
and
TIM10
,
TIM11
Up
Up
Up
Up
No
180
65536
Any
integer
between1
and
TIM12
No
90/180
90/180
90/180
65536
Any
integer
between1
and
TIM13
,
TIM14
No
65536
Any
integer
between1
and
TIM6,
TIM7
Basic
Yes
65536
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
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3.22.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
•
•
•
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.22.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F42x devices
(see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F42x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.22.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
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3.22.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.22.5
3.22.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
•
•
•
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.23
Inter-integrated circuit interface ( I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
Table 7. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
Programmable length from 1 to 15
I2C peripheral clocks
≥ 50 ns
3.24
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
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communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
(1)
Table 8. USART feature comparison
Max. baud
Smartcard rate in Mbit/s rate in Mbit/s
(ISO 7816) (oversampling (oversampling mapping
Max. baud
USART Standard
Modem
SPI
master
APB
LIN
irDA
name
features (RTS/CTS)
by 16)
by 8)
APB2
(max.
90 MHz)
USART1
USART2
USART3
UART4
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
-
X
X
X
X
X
X
X
X
X
X
X
-
5.62
11.25
APB1
(max.
45 MHz)
2.81
2.81
2.81
2.81
5.62
2.81
2.81
5.62
5.62
5.62
5.62
11.25
5.62
5.62
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
UART5
-
-
-
APB2
(max.
90 MHz)
USART6
UART7
X
-
X
-
X
-
APB1
(max.
45 MHz)
APB1
(max.
UART8
-
-
-
45 MHz)
1. X = feature supported.
3.25
Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
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3.26
Inter-integrated sound (I2S)
2
Two standard I S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
2
the I S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note:
For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
3.27
Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
3.28
Audio PLL (PLLI2S)
2
The devices feature an additional dedicated PLL for audio I S and SAI applications. It allows
2
to achieve error-free I S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
2
The PLLI2S configuration can be modified to manage an I S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
2
I S/SAI flow with an external PLL (or Codec output).
3.29
Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
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3.30
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.31
Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
•
•
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
•
•
•
•
•
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
•
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.32
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
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FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
3.33
Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.34
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator.
The major features are:
•
•
•
•
•
•
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
•
•
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
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STM32F427xx STM32F429xx
Functional overview
3.35
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
•
•
•
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
•
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
3.36
3.37
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
3.38
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
•
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
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43
Functional overview
STM32F427xx STM32F429xx
3.39
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as V , ADC1_IN18, which is used to convert the
BAT
sensor output voltage into a digital value. When the temperature sensor and V
BAT
conversion are enabled at the same time, only V
conversion is performed.
BAT
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.40
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
•
•
•
•
•
•
•
•
•
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
REF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.41
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
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DocID024030 Rev 9
STM32F427xx STM32F429xx
Functional overview
3.42
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F42x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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43
Pinouts and pin description
STM32F427xx STM32F429xx
4
Pinouts and pin description
Figure 11. STM32F42x LQFP100 pinout
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1. The above figure shows the package top view.
44/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Figure 12. STM32F42x WLCSP143 ballout
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DocID024030 Rev 9
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84
Pinouts and pin description
STM32F427xx STM32F429xx
Figure 13. STM32F42x LQFP144 pinout
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46/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Figure 14. STM32F42x LQFP176 pinout
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DocID024030 Rev 9
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84
Figure 15. STM32F42x LQFP208 pinout
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1. The above figure shows the package top view.
STM32F427xx STM32F429xx
Pinouts and pin description
Figure 16. STM32F42x UFBGA169 ballout
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1. The above figure shows the package top view.
2. The 4 corners balls, A1,A13, N1 and N13, are not bonded internally and should be left not connected on the PCB.
DocID024030 Rev 9
49/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Figure 17. STM32F42x UFBGA176 ballout
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1. The above figure shows the package top view.
50/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Figure 18. STM32F42x TFBGA216 ballout
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1. The above figure shows the package top view.
DocID024030 Rev 9
51/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 9. Legend/abbreviations used in the pinout table
Abbreviation Definition
Name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
S
I
Supply pin
Input only pin
Pin type
I/O
FT
TTa
B
Input / output pin
5 V tolerant I/O
3.3 V tolerant I/O directly connected to ADC
Dedicated BOOT0 pin
I/O structure
Notes
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Functions selected through GPIOx_AFR registers
Alternate
functions
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 10. STM32F427xx and STM32F429xx pin and ball definitions
Pin number
Pin name
Additional
functions
(functionafter
Alternate functions
reset)(1)
TRACECLK,
SPI4_SCK,
1
1
B2
A2
1
D8
1
A3
PE2
I/O FT
-
SAI1_MCLK_A,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
TRACED0,
SAI1_SD_B, FMC_A19,
EVENTOUT
2
3
2
3
C1
C2
A1
B1
2
3
C10
B11
2
3
A2
A1
PE3
PE4
I/O FT
I/O FT
-
-
-
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
52/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TRACED2, TIM9_CH1,
SPI4_MISO,
4
5
4
5
D1
D2
B2
B3
4
5
D9
E8
4
5
B1
B2
PE5
PE6
I/O FT
I/O FT
-
-
SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
-
TRACED3, TIM9_CH2,
SPI4_MOSI,
SAI1_SD_A, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G6
F5
C1
VSS
VDD
VBAT
S
S
S
-
-
-
-
-
-
-
-
-
-
-
6
6
E5
C1
6
C11
6
-
(3)
(4)
NC
-
-
D2
D1
7
8
-
7
8
C2
D1
PI8
I/O FT
I/O FT
EVENTOUT
EVENTOUT
TAMP_2
TAMP_1
(2)
(3)
(4)
7
7
E4
E1
D10
PC13
PC14-
OSC32_IN
(3)
(4)
OSC32_IN
8
8
E1
9
D11
9
E1
I/O FT
I/O FT
EVENTOUT
(5)
(PC14)
PC15-
OSC32_OUT
(3)
(4)
OSC32_
OUT(5)
9
-
9
-
F1
-
F1
-
10 E11 10
F1
G5
E4
EVENTOUT
-
(PC15)
-
-
-
-
VDD
S
-
-
-
-
-
CAN1_RX, FMC_D30,
LCD_VSYNC,
-
-
E2
D3
11
11
PI9
I/O FT
EVENTOUT
ETH_MII_RX_ER,
FMC_D31,
LCD_HSYNC,
EVENTOUT
-
-
-
-
E3
E3
E4
12
13
-
-
12 D5
PI10
PI11
I/O FT
I/O FT
-
-
-
-
NC
OTG_HS_ULPI_DIR,
EVENTOUT
13
F3
(2)
-
-
-
-
F6
F4
F2
F3
14 E7 14
15 E10 15
F2
F4
VSS
VDD
S
S
-
-
-
-
-
-
-
-
DocID024030 Rev 9
53/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
I2C2_SDA, FMC_A0,
-
-
-
-
-
10
11
F2
F3
E2
H3
H2
-
16 F11 16 D2
PF0
PF1
PF2
PI12
PI13
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
EVENTOUT
I2C2_SCL, FMC_A1,
17 E9 17 E2
18 F10 18 G2
-
EVENTOUT
I2C2_SMBA, FMC_A2,
12 G5
-
EVENTOUT
LCD_HSYNC,
EVENTOUT
-
-
-
-
19 E3
-
LCD_VSYNC,
EVENTOUT
-
-
-
-
-
-
-
-
-
20 G3
21 H3
-
-
-
-
PI14
PF3
I/O FT
I/O FT
LCD_CLK, EVENTOUT
-
(5)
(5)
13 G4
14 G3
J2
19 G11 22 H2
20 F9 23 J2
21 F8 24 K3
FMC_A3, EVENTOUT ADC3_IN9
ADC3_
FMC_A4, EVENTOUT
IN14
-
-
J3
PF4
PF5
I/O FT
I/O FT
ADC3_
FMC_A5, EVENTOUT
IN15
(5)
15 H3
K3
10 16 G7
11 17 G8
G2 22 H7 25 H6
G3 23 26 H5
VSS
VDD
S
S
-
-
-
-
-
-
-
-
-
TIM10_CH1,
SPI5_NSS,
NC
SAI1_SD_B,
UART7_Rx,
FMC_NIORD,
EVENTOUT
(5)
-
18
K2
24 G10 27 K2
PF6
I/O FT
ADC3_IN4
(2)
TIM11_CH1,
SPI5_SCK,
NC
SAI1_MCLK_B,
UART7_Tx,
FMC_NREG,
EVENTOUT
(5)
(5)
-
-
19
20
K1
L3
25 F7 28 K1
PF7
PF8
I/O FT
ADC3_IN5
ADC3_IN6
(2)
SPI5_MISO,
SAI1_SCK_B,
TIM13_CH1,
FMC_NIOWR,
EVENTOUT
NC
26 H11 29
L3
I/O FT
(2)
54/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
SPI5_MOSI,
NC
SAI1_FS_B,
TIM14_CH1, FMC_CD,
(5)
(5)
-
-
21
L2
L1
27 G8 30
L2
L1
PF9
I/O FT
ADC3_IN7
(2)
EVENTOUT
FMC_INTR,
DCMI_D11, LCD_DE, ADC3_IN8
EVENTOUT
22 H1
28 G9 31
PF10
I/O FT
I/O FT
I/O FT
PH0-OSC_IN
(PH0)
12 23 G2
G1 29 J11 32 G1
-
-
EVENTOUT
EVENTOUT
-
OSC_IN(5)
PH1-
OSC_OUT
OSC_OUT
13 24 G1
14 25 H2
15 26 G6
16 27 H5
H1
J1
30 H10 33 H1
(5)
(PH1)
RS
31 H9 34
J1
NRST
I/O
T
-
-
OTG_HS_ULPI_STP,
FMC_SDNWE,
EVENTOUT
ADC123_
IN10
(5)
M2 32 H8 35 M2
M3 33 K11 36 M3
PC0
PC1
I/O FT
I/O FT
ETH_MDC,
EVENTOUT
ADC123_
IN11
(5)
(5)
SPI2_MISO,
I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_
IN12
17 28 H6
M4 34 J10 37 M4
PC2
PC3
I/O FT
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
ADC123_
IN13
(5)
18 29 H7
M5 35 J9 38
L4
I/O FT
EVENTOUT
19 30
-
-
-
36 G7 39
J5
J6
VDD
VSS
S
S
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 31
J1
J2
J3
M1 37 K10 40 M1
VSSA
-
-
N1
P1
-
-
-
N1
VREF
–
21 32
38 L11 41 P1
VREF+
DocID024030 Rev 9
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84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
22 33
23 34
J4
J5
R1
N3
39 L10 42 R1
VDDA
S
-
-
-
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
ADC123_
PA0-WKUP
(PA0)
(6)
40 K9 43 N3
I/O FT
IN0/WKUP
UART4_TX,
(5)
ETH_MII_CRS,
EVENTOUT
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
ADC123_
IN1
(5)
(5)
24 35
K1
K2
N2
41 K8 44 N2
PA1
PA2
I/O FT
ETH_MII_RX_CLK/ETH
_RMII_REF_CLK,
EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM9_CH1,
ADC123_
IN2
25 36
P2
F4
42 L9 45 P2
I/O FT
USART2_TX,
ETH_MDIO,
EVENTOUT
ETH_MII_CRS,
FMC_SDCKE0,
LCD_R0, EVENTOUT
-
-
-
-
-
-
-
-
L2
L1
M2
L3
43
-
-
-
-
46 K4
PH2
PH3
PH4
PH5
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
ETH_MII_COL,
FMC_SDNE0,LCD_R1,
EVENTOUT
G4 44
47
J4
I2C2_SCL,
OTG_HS_ULPI_NXT,
EVENTOUT
H4
J4
45
46
48 H4
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
49
J3
EVENTOUT
TIM2_CH4, TIM5_CH4,
TIM9_CH2,
USART2_RX,
OTG_HS_ULPI_D0,
ETH_MII_COL,
ADC123_
IN3
(5)
26 37
27 38
K3
-
R2
-
47 M11 50 R2
PA3
VSS
I/O FT
LCD_B5, EVENTOUT
-
51 K6
S
-
-
-
-
56/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
BYPASS_
REG
-
-
M1
L4
48 N11
-
L5
I
FT
-
-
-
-
-
-
-
28 39 J11 K4
49 J8 52 K5
VDD
S
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
ADC12_
IN4 /DAC_
OUT1
(5)
(5)
(5)
29 40 N2
30 41 M3
31 42 N3
N4
P4
P3
50 M10 53 N4
PA4
I/O TTa
I/O TTa
I/O FT
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK,
OTG_HS_ULPI_CK,
EVENTOUT
ADC12_
IN5/DAC_
OUT2
51 M9 54 P4
PA5
PA6
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
TIM13_CH1,
ADC12_
IN6
52 N10 55 P3
DCMI_PIXCLK,
LCD_G2, EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI,
TIM14_CH1,
ETH_MII_RX_DV/ETH_
RMII_CRS_DV,
EVENTOUT
ADC12_
IN7
(5)
32 43
K4
L4
R3
53 L8 56 R3
PA7
I/O FT
ETH_MII_RXD0/ETH_
RMII_RXD0,
ADC12_
IN14
(5)
(5)
33 44
N5
P5
54 M8 57 N5
55 N9 58 P5
PC4
PC5
I/O FT
I/O FT
EVENTOUT
ETH_MII_RXD1/ETH_
RMII_RXD1,
ADC12_
IN15
34 45 M4
EVENTOUT
-
-
-
-
-
-
-
-
-
-
J7 59
60
L7
L6
VDD
VSS
S
S
-
-
-
-
-
-
-
-
-
DocID024030 Rev 9
57/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
ADC12_
IN8
(5)
35 46 N4
R5
R4
56 N8 61 R5
PB0
PB1
I/O FT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
EVENTOUT
ADC12_
IN9
(5)
36 47
37 48
K5
L5
57 K7 62 R4
I/O FT
I/O FT
PB2-BOOT1
(PB2)
M6 58 L7 63 M5
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
64 G4
65 R6
66 R7
67 P7
68 N8
69 M9
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
LCD_R0, EVENTOUT
LCD_R1, EVENTOUT
LCD_R2, EVENTOUT
LCD_R3, EVENTOUT
LCD_R4, EVENTOUT
LCD_R5, EVENTOUT
-
-
-
-
-
-
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12,
-
49 M5
R6
P6
59 M7 70 P8
60 N7 71 M6
PF11
I/O FT
-
-
EVENTOUT
-
-
-
-
-
-
-
-
50 N5
51 G9
PF12
VSS
I/O FT
S
-
-
-
-
-
-
-
-
FMC_A6, EVENTOUT
-
-
-
-
-
-
-
-
-
M8 61
62
-
-
72 K7
73 L8
52 D10 N8
VDD
S
-
53 M6
N6
R7
P7
N7
63 K6 74 N6
64 L6 75 P6
65 M6 76 M8
66 N6 77 N7
PF13
PF14
PF15
PG0
PG1
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
FMC_A7, EVENTOUT
FMC_A8, EVENTOUT
FMC_A9, EVENTOUT
FMC_A10, EVENTOUT
FMC_A11, EVENTOUT
54
55
K7
L7
56 N6
57 M7 M7 67 K5 78 M7
58/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TIM1_ETR,UART7_Rx,
FMC_D4, EVENTOUT
38 58 N7
R8
P8
P9
68 L5 79 R8
PE7
PE8
PE9
I/O FT
I/O FT
I/O FT
-
-
-
-
TIM1_CH1N,
UART7_Tx, FMC_D5,
EVENTOUT
39 59
40 60
J8
69 M5 80 N9
70 N5 81 P9
-
-
TIM1_CH1, FMC_D6,
EVENTOUT
K8
J6
-
-
61
M9 71 H3 82 K8
72 J5 83 L9
VSS
VDD
S
S
-
-
-
-
62 G10 N9
L8 R9
TIM1_CH2N, FMC_D7,
EVENTOUT
41 63
73 J4 84 R9
PE10
PE11
I/O FT
I/O FT
-
-
-
-
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
42 64 M8 P10 74 K4 85 P10
43 65 N8 R10 75 L4 86 R10
44 66 H9 N11 76 N4 87 R12
TIM1_CH3N,
SPI4_SCK, FMC_D9,
LCD_B4, EVENTOUT
PE12
PE13
I/O FT
I/O FT
-
-
-
-
TIM1_CH3,
SPI4_MISO,FMC_D10,
LCD_DE, EVENTOUT
TIM1_CH4,
45 67
46 68
J9 P11 77 M4 88 P11
K9 R11 78 L3 89 R11
PE14
PE15
I/O FT
I/O FT
-
-
SPI4_MOSI, FMC_D11,
LCD_CLK, EVENTOUT
-
-
TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
47 69
L9 R12 79 M3 90 P12
PB10
PB11
I/O FT
-
-
-
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, LCD_G5,
EVENTOUT
48 70 M9 R13 80 N3 91 R13
I/O FT
-
DocID024030 Rev 9
59/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
49 71 N9 M10 81 N2 92 L11
VCAP_1
VSS
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H2 93 K9
-
50 72
F8 N10 82 J6 94 L10
VDD
S
-
-
-
-
-
-
-
-
95 M14
96 P13
PJ5
I/O
LCD_R6, EVENTOUT
I2C2_SMBA,
SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1,
-
-
N10 M11 83
PH6
I/O FT
-
-
DCMI_D8, EVENTOUT
I2C3_SCL,SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-
-
-
-
-
M10 N12 84
L10 M12 85
K10 M13 86
-
-
-
97 N13
98 P14
99 N14
PH7
PH8
PH9
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
I2C3_SDA, FMC_D16,
DCMI_HSYNC,
LCD_R2, EVENTOUT
I2C3_SMBA,
TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
-
-
-
-
-
N11 L13 87
M11 L12 88
L11 K12 89
-
-
-
100 P15
101 N15
102 M15
PH10
PH11
PH12
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
-
-
-
E7 H12 90
H8 J12 91
-
-
-
K10
VSS
VDD
S
S
-
-
-
-
-
-
-
-
103 K11
60/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK,
CAN2_RX,
OTG_HS_ULPI_D5,
51 73 N12 P12 92 M2 104 L13
PB12
I/O FT
-
-
ETH_MII_TXD0/ETH_R
MII_TXD0,
OTG_HS_ID,
EVENTOUT
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
CAN2_TX,
OTG_HS_ULPI_D6,
OTG_HS_
VBUS
52 74 M12 P13 93 N1 105 K14
53 75 M13 R14 94 K3 106 R14
54 76 L13 R15 95 J3 107 R15
PB13
PB14
PB15
I/O FT
I/O FT
I/O FT
-
-
-
ETH_MII_TXD1/ETH_R
MII_TXD1, EVENTOUT
TIM1_CH2N,
TIM8_CH2N,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
-
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2,
-
OTG_HS_DP,
EVENTOUT
USART3_TX,
FMC_D13, EVENTOUT
55 77 L12 P15 96 L2 108 L15
56 78 K13 P14 97 M1 109 L14
PD8
PD9
I/O FT
I/O FT
-
-
-
-
USART3_RX,
FMC_D14, EVENTOUT
USART3_CK,
FMC_D15, LCD_B3,
EVENTOUT
57 79 K11 N15 98 H4 110 K15
PD10
I/O FT
-
-
DocID024030 Rev 9
61/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
USART3_CTS,
FMC_A16, EVENTOUT
58 80 H10 N14 99 K2 111 N10
59 81 J13 N13 100 H6 112 M10
60 82 K12 M15 101 H5 113 M11
PD11
PD12
PD13
I/O FT
I/O FT
I/O FT
-
-
-
-
TIM4_CH1,
USART3_RTS,
FMC_A17, EVENTOUT
-
-
TIM4_CH2, FMC_A18,
EVENTOUT
-
-
83
84
-
-
102
-
114 J10
VSS
VDD
S
S
-
-
-
-
-
-
F7 J13 103 L1 115 J11
TIM4_CH3, FMC_D0,
EVENTOUT
61 85 H11 M14 104 J2 116 L12
62 86 J12 L14 105 K1 117 K13
PD14
PD15
I/O FT
I/O FT
-
-
-
-
TIM4_CH4, FMC_D1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
118 K12
119 J12
120 H12
121 J13
122 H13
123 G12
124 H11
125 H10
126 G13
127 F12
128 F13
PJ6
PJ7
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7, EVENTOUT
LCD_G0, EVENTOUT
LCD_G1, EVENTOUT
LCD_G2, EVENTOUT
LCD_G3, EVENTOUT
LCD_G4, EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
PJ8
PJ9
PJ10
PJ11
VDD
VSS
PK0
PK1
PK2
PG2
-
LCD_G5, EVENTOUT
LCD_G6, EVENTOUT
LCD_G7, EVENTOUT
FMC_A12, EVENTOUT
87 H13 L15 106 J1 129 M13
NC
-
-
-
88
K15 107 G3 130 M12
PG3
PG4
PG5
I/O FT
I/O FT
I/O FT
-
-
-
FMC_A13, EVENTOUT
-
-
-
(2)
FMC_A14/FMC_BA0,
EVENTOUT
89 H12 K14 108 G5 131 N12
90 G13 K13 109 G6 132 N11
FMC_A15/FMC_BA1,
EVENTOUT
62/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
FMC_INT2, DCMI_D12,
LCD_R7, EVENTOUT
-
-
91 G11 J15 110 G4 133 J15
92 G12 J14 111 H1 134 J14
PG6
PG7
I/O FT
I/O FT
-
-
-
USART6_CK,
FMC_INT3, DCMI_D13,
LCD_CLK, EVENTOUT
-
-
SPI6_NSS,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK,
EVENTOUT
-
93 F13 H14 112 G2 135 H14
PG8
I/O FT
-
-
-
94
95
J7 G12 113 D2 136 G10
E6 H13 114 G1 137 G11
VSS
VDD
S
S
-
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
I2S2_MCK,
USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC,
63 96
F9 H15 115 F2 138 H15
PC6
PC7
I/O FT
-
-
-
-
EVENTOUT
TIM3_CH2, TIM8_CH2,
I2S3_MCK,
64 97 F10 G15 116 F3 139 G15
I/O FT
USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
TIM3_CH3, TIM8_CH3,
USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
65 98 F11 G14 117 E4 140 G14
66 99 F12 F14 118 E3 141 F14
PC8
PC9
I/O FT
I/O FT
-
-
-
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, SDIO_D1,
DCMI_D3, EVENTOUT
MCO1, TIM1_CH1,
I2C3_SCL,
67 100 E13 F15 119 F1 142 F15
PA8
I/O FT
-
USART1_CK,
-
OTG_FS_SOF,
LCD_R6, EVENTOUT
DocID024030 Rev 9
63/238
84
Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TIM1_CH2,
I2C3_SMBA,
USART1_TX,
DCMI_D0, EVENTOUT
OTG_FS_
VBUS
68 101 E8 E15 120 E2 143 E15
69 102 E9 D15 121 D5 144 D15
PA9
I/O FT
I/O FT
-
-
TIM1_CH3,
USART1_RX,
OTG_FS_ID,
PA10
-
-
DCMI_D1, EVENTOUT
TIM1_CH4,
USART1_CTS,
CAN1_RX, LCD_R4,
OTG_FS_DM,
EVENTOUT
70 103 E10 C15 122 D4 145 C15
PA11
I/O FT
-
TIM1_ETR,
USART1_RTS,
CAN1_TX, LCD_R5,
OTG_FS_DP,
71 104 E11 B15 123 E1 146 B15
72 105 E12 A15 124 D3 147 A15
PA12
PA13
I/O FT
I/O FT
-
-
-
-
EVENTOUT
JTMS-SWDIO,
EVENTOUT
(JTMS-
SWDIO)
73 106 D12 F13 125 D1 148 E11
74 107 J10 F12 126 D2 149 F10
75 108 H4 G13 127 C1 150 F11
VCAP_2
VSS
S
S
S
-
-
-
-
-
-
-
-
-
VDD
TIM8_CH1N,
-
-
-
-
-
-
D13 E12 128
C13 E13 129
C12 D13 130
-
-
-
151 E12
152 E13
153 D13
PH13
PH14
PH15
I/O FT
I/O FT
I/O FT
-
-
-
CAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
-
TIM8_CH2N,
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
TIM8_CH3N,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS(7)
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
,
-
-
B13 E14 131
-
154 E14
PI0
I/O FT
-
-
64/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
SPI2_SCK/I2S2_CK(7)
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
,
-
-
-
-
C11 D14 132
B12 C14 133
-
-
155 D14
156 C14
PI1
PI2
I/O FT
I/O FT
-
-
-
-
TIM8_CH4,
SPI2_MISO,
I2S2ext_SD,FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
A12 C13 134
-
157 C13
PI3
I/O FT
-
-
-
-
-
-
D11 D9 135 F5
-
F9
VSS
VDD
S
S
-
-
-
-
-
-
D3 C9 136 A1 158 E10
PA14
JTCK-SWCLK/
EVENTOUT
76 109 A11 A14 137 B1 159 A14
77 110 B11 A13 138 C2 160 A13
I/O FT
-
-
(JTCK-
SWCLK)
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
PA15
I/O FT
-
-
(JTDI)
SPI3_SCK/I2S3_CK,
USART3_TX,
78 111 C10 B14 139 A2 161 B14
PC10
PC11
I/O FT
I/O FT
-
-
UART4_TX, SDIO_D2,
DCMI_D8, LCD_R2,
EVENTOUT
-
-
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
79 112 B10 B13 140 B2 162 B13
UART4_RX, SDIO_D3,
DCMI_D4, EVENTOUT
SPI3_MOSI/I2S3_SD,
USART3_CK,
UART5_TX, SDIO_CK,
DCMI_D9, EVENTOUT
80 113 A10 A12 141 C3 163 A12
81 114 D9 B12 142 B3 164 B12
PC12
PD0
I/O FT
I/O FT
-
-
-
-
CAN1_RX, FMC_D2,
EVENTOUT
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Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
CAN1_TX, FMC_D3,
82 115 C9 C12 143 C4 165 C12
83 116 B9 D12 144 A3 166 D12
PD1
PD2
I/O FT
I/O FT
-
-
-
EVENTOUT
TIM3_ETR,
UART5_RX,
SDIO_CMD,
DCMI_D11,
EVENTOUT
-
-
SPI2_SCK/I2S2_CK,
USART2_CTS,
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
84 117 A9 D11 145 B4 167 C11
PD3
I/O FT
-
USART2_RTS,
FMC_NOE,
EVENTOUT
85 118 D8 D10 146 B5 168 D11
86 119 C8 C11 147 A4 169 C10
PD4
PD5
I/O FT
I/O FT
-
-
-
-
USART2_TX,
FMC_NWE,
EVENTOUT
-
-
120
-
D8 148
-
170 F8
VSS
VDD
S
S
-
-
-
-
-
-
121 D6
C8 149 C5 171 E9
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
USART2_RX,
FMC_NWAIT,
87 122 B8 B11 150 F4 172 B11
PD6
I/O FT
-
-
DCMI_D10, LCD_B2,
EVENTOUT
USART2_CK,
FMC_NE1/FMC_NCE2,
EVENTOUT
88 123 A8 A11 151 A5 173 A11
PD7
I/O FT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
174 B10
175 B9
176 C9
177 D10
PJ12
PJ13
PJ14
PJ15
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
LCD_B0, EVENTOUT
LCD_B1, EVENTOUT
LCD_B2, EVENTOUT
LCD_B3, EVENTOUT
-
-
-
-
USART6_RX,
NC
FMC_NE2/FMC_NCE3,
-
124
C10 152 E5 178 D9
PG9
I/O FT
-
-
(2)
DCMI_VSYNC(8)
EVENTOUT
,
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STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
LCD_G3,
FMC_NCE4_1/FMC_N
E3, DCMI_D2,
LCD_B2, EVENTOUT
-
-
-
-
125 C7 B10 153 C6 179 C8
PG10
PG11
PG12
PG13
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
ETH_MII_TX_EN/ETH_
RMII_TX_EN,
FMC_NCE4_2,
DCMI_D3, LCD_B3,
EVENTOUT
126 B7
B9 154 B6 180 B8
B8 155 A6 181 C7
A8 156 D6 182 B3
-
-
-
SPI6_MISO,
USART6_RTS,
LCD_B4, FMC_NE4,
LCD_B1, EVENTOUT
127 A7
SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
EVENTOUT
NC
128
129
(2)
SPI6_MOSI,
USART6_TX,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
EVENTOUT
NC
-
A7 157 F6 183 A4
PG14
I/O FT
-
-
(2)
-
-
-
-
-
-
-
130 D7
131 L6
D7 158
-
184 F7
VSS
VDD
PK3
PK4
PK5
PK6
PK7
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C7 159 E6 185 E8
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
186 D8
187 D7
188 C6
189 C5
190 C4
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
LCD_B4, EVENTOUT
LCD_B5, EVENTOUT
LCD_B6, EVENTOUT
LCD_B7, EVENTOUT
LCD_DE, EVENTOUT
USART6_CTS,
FMC_SDNCAS,
DCMI_D13,
-
132 C6
B7 160 A7 191 B7
PG15
I/O FT
-
-
EVENTOUT
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Pinouts and pin description
STM32F427xx STM32F429xx
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
PB3
89 133 B6 A10 161 B7 192 A10
I/O FT
I/O FT
-
-
-
(JTDO/TRACE
SWO)
EVENTOUT
NJTRST, TIM3_CH1,
SPI1_MISO,
PB4
90 134 A6
91 135 D5
92 136 C5
A9 162 C7 193 A9
A6 163 C8 194 A8
B6 164 A8 195 B6
SPI3_MISO,
I2S3ext_SD,
EVENTOUT
-
-
-
(NJTRST)
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10,
PB5
PB6
I/O FT
-
-
EVENTOUT
TIM4_CH1, I2C1_SCL,
USART1_TX,
CAN2_TX,
FMC_SDNE1,
DCMI_D5, EVENTOUT
I/O FT
I/O FT
TIM4_CH2, I2C1_SDA,
USART1_RX,FMC_NL,
DCMI_VSYNC,
93 137 B5
94 138 A5
B5 165 B8 196 B5
D6 166 C9 197 E6
PB7
-
-
-
EVENTOUT
BOOT0
I
B
VPP
TIM4_CH3,
TIM10_CH1,
I2C1_SCL, CAN1_RX,
ETH_MII_TXD3,
95 139 D4
A5 167 A9 198 A7
PB8
I/O FT
-
-
SDIO_D4, DCMI_D6,
LCD_B6, EVENTOUT
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STM32F427xx STM32F429xx
Pinouts and pin description
Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued)
Pin number
Pin name
(functionafter
reset)(1)
Additional
Alternate functions
functions
TIM4_CH4,
TIM11_CH1,
I2C1_SDA,
96 140 C4
B4 168 B9 199 B4
PB9
I/O FT
-
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
-
TIM4_ETR,
UART8_RX,
FMC_NBL0, DCMI_D2,
EVENTOUT
97 141 B4
98 142 A4
A4 169 B10 200 A6
A3 170 A10 201 A5
PE0
PE1
I/O FT
I/O FT
-
-
-
-
UART8_Tx,
FMC_NBL1, DCMI_D3,
EVENTOUT
99
-
-
F5
D5
-
-
202 F6
VSS
PDR_ON
VDD
S
S
S
-
-
-
-
-
-
143 C3
C6 171 A11 203 E5
C5 172 D7 204 E7
100 144 K6
TIM8_BKIN,
-
-
-
-
B3
A3
D4 173
C4 174
-
-
205 C3
206 D3
PI4
PI5
I/O FT
I/O FT
-
-
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
-
TIM8_CH1,
FMC_NBL3,
DCMI_VSYNC,
LCD_B5, EVENTOUT
TIM8_CH2, FMC_D28,
DCMI_D6, LCD_B6,
EVENTOUT
-
-
-
-
A2
B1
C3 175
C2 176
-
-
207 D6
208 D4
PI6
PI7
I/O FT
I/O FT
-
-
-
-
TIM8_CH3, FMC_D29,
DCMI_D7, LCD_B7,
EVENTOUT
1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid extra current consumption in low power modes.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
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Pinouts and pin description
STM32F427xx STM32F429xx
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:
www.st.com.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
6. If the device is delivered in an WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).
7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.
8. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
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STM32F427xx STM32F429xx
Pin name
Pinouts and pin description
Table 11. FMC pin definition
NOR/PSRAM/ NOR/PSRAM
CF
NAND16
SDRAM
SRAM
Mux
PF0
PF1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A0
A1
PF2
A2
A2
PF3
A3
A3
PF4
A4
A4
PF5
A5
A5
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PD11
PD12
PD13
PE3
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
D0
A10
A11
A12
BA0
BA1
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
CLE
ALE
PE4
PE5
PE6
PE2
PG13
PG14
PD14
PD15
PD0
PD1
PE7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
PE8
D5
PE9
D6
PE10
D7
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Pinouts and pin description
Pin name
STM32F427xx STM32F429xx
Table 11. FMC pin definition (continued)
NOR/PSRAM/ NOR/PSRAM
CF
NAND16
SDRAM
SRAM
Mux
PE11
PE12
PE13
PE14
PE15
PD8
PD9
PD10
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
D8
D8
DA8
DA9
D8
D8
D9
D9
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
NE1
NE2
NE3
DA10
DA11
DA12
DA13
DA14
DA15
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
PI1
PI2
PI3
PI6
PI7
PI9
PI10
PD7
PG9
PG10
PG11
PG12
PD3
PD4
PD5
PD6
PB7
NE1
NE2
NE3
NCE2
NCE3
NCE4_1
NCE4_2
NE4
CLK
NE4
CLK
NOE
NWE
NOE
NOE
NOE
NWE
NWE
NWE
NWAIT
NWAIT
NL(NADV)
NWAIT
NL(NADV)
NWAIT
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STM32F427xx STM32F429xx
Pin name
Pinouts and pin description
Table 11. FMC pin definition (continued)
NOR/PSRAM/ NOR/PSRAM
CF
NAND16
SDRAM
SRAM
Mux
PF6
PF7
PF8
PF9
PF10
PG6
PG7
PE0
PE1
PI4
NIORD
NREG
NIOWR
CD
INTR
INT2
INT3
NBL0
NBL1
NBL2
NBL3
NBL0
NBL1
NBL0
NBL1
NBL2
PI5
NBL3
PG8
PC0
PF11
PG15
PH2
PH3
PH6
PH7
PH5
PC2
PC3
PB5
PB6
SDCLK
SDNWE
SDNRAS
SDNCAS
SDCKE0
SDNE0
SDNE1
SDCKE1
SDNWE
SDNE0
SDCKE0
SDCKE1
SDNE1
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84
Table 12. STM32F427xx and STM32F429xx alternate function mapping
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
TIM2_
CH1/TIM2
_ETR
TIM5_
CH1
TIM8_
ETR
USART2_
CTS
ETH_MII_
CRS
EVEN
TOUT
PA0
PA1
-
-
-
-
-
-
UART4_TX
-
-
-
-
-
-
-
-
ETH_MII_
RX_CLK/E
TH_RMII_
REF_CLK
TIM2_
CH2
TIM5_
CH2
USART2_
RTS
EVEN
TOUT
-
-
-
UART4_RX
-
-
-
TIM2_
CH3
TIM5_
CH3
TIM9_
CH1
USART2_
TX
ETH_
MDIO
EVEN
TOUT
PA2
PA3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM2_
CH4
TIM5_
CH4
TIM9_
CH2
USART2_
RX
OTG_HS_ ETH_MII_
EVEN
TOUT
LCD_B5
ULPI_D0
COL
SPI3_
NSS/
I2S3_WS
SPI1_
NSS
USART2_
CK
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC TOUT
EVEN
PA4
-
-
-
-
-
-
-
-
-
-
TIM2_
CH1/TIM2
_ETR
TIM8_
CH1N
SPI1_
SCK
OTG_HS_
ULPI_CK
EVEN
TOUT
PA5
PA6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Port A
TIM1_
BKIN
TIM3_
CH1
TIM8_
BKIN
SPI1_
MISO
DCMI_
PIXCLK
EVEN
LCD_G2
TIM13_CH1
-
-
TOUT
ETH_MII_
RX_DV/
ETH_RMII
_CRS_DV
TIM1_
CH1N
TIM3_
CH2
TIM8_
CH1N
SPI1_
MOSI
EVEN
TOUT
PA7
-
-
-
-
-
TIM14_CH1
-
-
-
TIM1_
CH1
I2C3_
SCL
USART1_
CK
OTG_FS_
SOF
EVEN
LCD_R6
PA8
PA9
MCO1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TOUT
TIM1_
CH2
I2C3_
SMBA
USART1_
TX
DCMI_
D0
EVEN
TOUT
-
-
-
-
-
-
-
TIM1_
CH3
USART1_
RX
OTG_FS_
ID
DCMI_
D1
EVEN
TOUT
PA10
PA11
PA12
-
-
-
-
-
TIM1_
CH4
USART1_
CTS
OTG_FS_
DM
EVEN
LCD_R4
CAN1_RX
CAN1_TX
-
-
TOUT
TIM1_
ETR
USART1_
RTS
OTG_FS_
DP
EVEN
LCD_R5
TOUT
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
SYS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
JTMS-
PA13 SWDI
O
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
JTCK-
Port A PA14 SWCL
K
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
TIM2_
CH1/TIM2
_ETR
SPI3_
NSS/
I2S3_WS
SPI1_
NSS
EVEN
TOUT
PA15
JTDI
TIM1_
CH2N
TIM3_
CH3
TIM8_
CH2N
OTG_HS_ ETH_MII_
ULPI_D1 RXD2
EVEN
TOUT
PB0
PB1
PB2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R3
LCD_R6
-
-
-
-
-
-
-
-
-
-
TIM1_
CH3N
TIM3_
CH4
TIM8_
CH3N
OTG_HS_ ETH_MII_
EVEN
TOUT
ULPI_D2
RXD3
EVEN
TOUT
-
-
-
-
-
-
-
-
-
JTDO/
TRAC
ESWO
SPI3_
SCK/
I2S3_CK
TIM2_
CH2
SPI1_
SCK
EVEN
TOUT
PB3
PB4
PB5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NJTR
ST
TIM3_
CH1
SPI1_
MISO
SPI3_
MISO
I2S3ext_
SD
EVEN
TOUT
-
-
-
SPI3_
MOSI/
I2S3_SD
TIM3_
CH2
I2C1_
SMBA
SPI1_
MOSI
OTG_HS_ ETH_PPS
FMC_
SDCKE1
DCMI_
D10
EVEN
TOUT
-
-
CAN2_RX
Port B
ULPI_D7
_OUT
TIM4_
CH1
I2C1_
SCL
USART1_
TX
FMC_
SDNE1
DCMI_
D5
EVEN
TOUT
PB6
PB7
PB8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN2_TX
-
-
-
-
-
-
-
TIM4_
CH2
I2C1_
SDA
USART1_
RX
DCMI_
VSYNC
EVEN
TOUT
FMC_NL
SDIO_D4
-
TIM4_
CH3
TIM10_ I2C1_
CH1 SCL
ETH_MII_
TXD3
DCMI_
D6
EVEN
TOUT
-
-
CAN1_RX
LCD_B6
SPI2_
NSS/I2
S2_WS
TIM4_
CH4
TIM11_ I2C1_
DCMI_
D7
EVEN
TOUT
PB9
-
-
-
-
-
-
-
CAN1_TX
-
-
-
SDIO_D5
-
LCD_B7
LCD_G4
CH1
-
SDA
SPI2_
SCK/I2
S2_CK
TIM2_
CH3
I2C2_
SCL
USART3_
TX
OTG_HS_ ETH_MII_
ULPI_D3 RX_ER
EVEN
TOUT
PB10
-
-
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
ETH_MII_
TX_EN/
ULPI_D4 ETH_RMII
_TX_EN
TIM2_
CH4
I2C2_
SDA
USART3_
RX
OTG_HS_
EVEN
TOUT
PB11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G5
ETH_MII_
OTG_HS_ TXD0/ETH OTG_HS_
SPI2_
NSS/I2
S2_WS
TIM1_
BKIN
I2C2_
SMBA
USART3_
CK
EVEN
TOUT
PB12
PB13
-
-
-
-
CAN2_RX
CAN2_TX
-
-
ULPI_D5
_RMII_
TXD0
ID
Port B
ETH_MII_
OTG_HS_ TXD1/ETH
SPI2_
SCK/I2
S2_CK
TIM1_
CH1N
USART3_
CTS
EVEN
TOUT
-
-
-
-
ULPI_D6
_RMII_TX
D1
TIM1_
CH2N
TIM8_
CH2N
SPI2_
MISO
I2S2ext_ USART3_
OTG_HS_
DM
EVEN
TOUT
PB14
PB15
-
-
-
-
-
-
TIM12_CH1
TIM12_CH2
-
-
-
-
-
-
-
-
SD
RTS
SPI2_
MOSI/I2
S2_SD
RTC_
REFIN
TIM1_
CH3N
TIM8_
CH3N
OTG_HS_
DP
EVEN
TOUT
-
-
OTG_HS_
ULPI_STP
FMC_SDN
WE
EVEN
TOUT
PC0
PC1
PC2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
ETH_MDC
-
SPI2_
MISO
I2S2ext_
SD
OTG_HS_ ETH_MII_
ULPI_DIR TXD2
FMC_
SDNE0
EVEN
TOUT
SPI2_
MOSI/I2
S2_SD
OTG_HS_ ETH_MII_
FMC_
SDCKE0
EVEN
TOUT
PC3
PC4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ULPI_NXT
TX_CLK
ETH_MII_
RXD0/ETH
_RMII_
Port
C
EVEN
TOUT
-
-
-
-
-
RXD0
ETH_MII_
RXD1/ETH
_RMII_
EVEN
TOUT
PC5
-
-
-
-
-
-
-
-
-
-
-
-
-
RXD1
TIM3_
CH1
TIM8_
CH1
I2S2_
MCK
USART6_
TX
DCMI_
D0
LCD_
EVEN
HSYNC TOUT
PC6
PC7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIO_D6
SDIO_D7
TIM3_
CH2
TIM8_
CH2
I2S3_
MCK
USART6_
RX
DCMI_
D1
EVEN
LCD_G6
-
TOUT
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
TIM3_
CH3
TIM8_
CH3
USART6_
CK
DCMI_
D2
EVEN
TOUT
PC8
-
-
-
-
-
-
-
-
-
-
-
-
-
SDIO_D0
SDIO_D1
-
-
TIM3_
CH4
TIM8_
CH4
I2C3_
SDA
I2S_
CKIN
DCMI_
D3
EVEN
TOUT
PC9 MCO2
-
-
-
-
-
-
SPI3_
SCK/I2S
3_CK
USART3_
TX
DCMI_
D8
EVEN
TOUT
PC10
PC11
PC12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART4_TX
UART4_RX
UART5_TX
-
-
-
-
-
-
SDIO_D2
SDIO_D3
SDIO_CK
LCD_R2
I2S3ext
_SD
SPI3_
MISO
USART3_
RX
DCMI_
D4
EVEN
TOUT
-
-
Port
C
SPI3_
MOSI/I2
S3_SD
USART3_
CK
DCMI_
D9
EVEN
TOUT
-
EVEN
TOUT
PC13
PC14
PC15
PD0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
-
-
EVEN
TOUT
-
-
-
EVEN
TOUT
-
CAN1_RX
CAN1_TX
-
FMC_D2
FMC_D3
EVEN
TOUT
PD1
-
TIM3_
ETR
SDIO_
CMD
DCMI_
D11
EVEN
TOUT
PD2
UART5_RX
SPI2_S
CK/I
2S2_CK
USART2_
CTS
DCMI_
D5
EVEN
TOUT
Port
D
PD3
-
-
-
-
-
-
-
-
-
-
FMC_CLK
LCD_G7
USART2_
RTS
EVEN
TOUT
PD4
PD5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NOE
FMC_NWE
-
-
-
-
USART2_
TX
EVEN
TOUT
SPI3_
MOSI/I2
S3_SD
SAI1_
SD_A
USART2_
RX
FMC_
NWAIT
DCMI_
D10
EVEN
TOUT
PD6
-
-
-
-
-
-
-
-
-
LCD_B2
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
FMC_NE1/
FMC_
NCE2
USART2_
CK
EVEN
TOUT
PD7
-
-
-
-
-
-
-
-
-
-
-
-
-
USART3_
TX
EVEN
TOUT
PD8
PD9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D13
FMC_D14
FMC_D15
FMC_A16
FMC_A17
FMC_A18
FMC_D0
FMC_D1
-
-
-
-
-
-
-
-
-
USART3_
RX
EVEN
TOUT
-
-
USART3_
CK
EVEN
TOUT
PD10
PD11
PD12
PD13
PD14
PD15
PE0
-
LCD_B3
Port
D
USART3_
CTS
EVEN
TOUT
-
-
TIM4_
CH1
USART3_
RTS
EVEN
TOUT
-
-
TIM4_
CH2
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
TIM4_
CH3
EVEN
TOUT
-
-
TIM4_
CH4
EVEN
TOUT
-
-
TIM4_
ETR
FMC_
NBL0
DCMI_
D2
EVEN
TOUT
UART8_Rx
-
FMC_
NBL1
DCMI_
D3
EVEN
TOUT
PE1
-
-
-
-
-
-
UART8_Tx
-
TRAC
ECLK
SPI4_
SCK
SAI1_
MCLK_A
ETH_MII_
TXD3
EVEN
TOUT
PE2
-
-
-
-
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
-
-
-
TRAC
ED0
SAI1_
SD_B
EVEN
TOUT
Port E PE3
PE4
-
-
-
-
-
-
TRAC
ED1
SPI4_
NSS
SAI1_
FS_A
DCMI_
D4
EVEN
TOUT
LCD_B0
LCD_G0
LCD_G1
TRAC
ED2
TIM9_
CH1
SPI4_M
ISO
SAI1_
SCK_A
DCMI_
D6
EVEN
TOUT
PE5
TRAC
ED3
TIM9_
CH2
SPI4_
MOSI
SAI1_
SD_A
DCMI_
D7
EVEN
TOUT
PE6
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
TIM1_
ETR
EVEN
TOUT
PE7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART7_Rx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D4
FMC_D5
FMC_D6
FMC_D7
FMC_D8
FMC_D9
FMC_D10
FMC_D11
FMC_D12
FMC_A0
FMC_A1
FMC_A2
FMC_A3
FMC_A4
FMC_A5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
CH1N
EVEN
TOUT
PE8
PE9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART7_Tx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM1_
CH1
EVEN
TOUT
-
-
TIM1_
CH2N
EVEN
TOUT
PE10
-
-
TIM1_
CH2
SPI4_
NSS
EVEN
TOUT
Port E PE11
PE12
-
LCD_G3
LCD_B4
LCD_DE
TIM1_
CH3N
SPI4_
SCK
EVEN
TOUT
-
TIM1_
CH3
SPI4_
MISO
EVEN
TOUT
PE13
-
TIM1_
CH4
SPI4_
MOSI
LCD_
CLK
EVEN
TOUT
PE14
-
TIM1_
BKIN
EVEN
TOUT
PE15
-
LCD_R7
I2C2_
SDA
EVEN
TOUT
PF0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_
SCL
EVEN
TOUT
PF1
-
I2C2_
SMBA
EVEN
TOUT
PF2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PF3
Port F
-
EVEN
TOUT
PF4
-
EVEN
TOUT
PF5
PF6
PF7
-
TIM10_
CH1
SPI5_
NSS
SAI1_
SD_B
FMC_
NIORD
EVEN
TOUT
-
-
UART7_Rx
UART7_Tx
TIM11_
CH1
SPI5_
SCK
SAI1_
MCLK_B
FMC_
NREG
EVEN
TOUT
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
SPI5_
MISO
SAI1_
SCK_B
FMC_
NIOWR
EVEN
TOUT
PF8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM13_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI5_
MOSI
SAI1_
FS_B
EVEN
TOUT
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM14_CH1
FMC_CD
-
DCMI_
D11
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_INTR
LCD_DE
SPI5_
MOSI
FMC_
SDNRAS
DCMI_
D12
EVEN
TOUT
-
Port F
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
FMC_A7
FMC_A8
FMC_A9
FMC_A10
FMC_A11
FMC_A12
FMC_A13
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
EVEN
TOUT
-
Port
G
FMC_A14/
FMC_BA0
EVEN
TOUT
-
FMC_A15/
FMC_BA1
EVEN
TOUT
-
DCMI_
D12
EVEN
TOUT
FMC_INT2
FMC_INT3
LCD_R7
USART6_
CK
DCMI_
D13
LCD_
CLK
EVEN
TOUT
SPI6_
NSS
USART6_
RTS
ETH_PPS FMC_SDC
_OUT LK
EVEN
TOUT
-
-
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
FMC_NE2/ DCMI_
USART6_
RX
EVEN
TOUT
PG9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_
NCE3
VSYNC
-
(1)
FMC_
NCE4_1/
FMC_NE3
DCMI_
D2
EVEN
TOUT
PG10
-
-
-
-
-
-
-
LCD_G3
LCD_B2
ETH_MII_
TX_EN/
ETH_RMII
_TX_EN
FMC_
NCE4_2
DCMI_
D3
EVEN
TOUT
PG11
PG12
PG13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
LCD_B1
-
Port
G
SPI6_
MISO
USART6_
RTS
EVEN
TOUT
LCD_B4
-
-
FMC_NE4
FMC_A24
-
-
ETH_MII_
TXD0/
ETH_RMII
_TXD0
SPI6_
SCK
USART6_
CTS
EVEN
TOUT
ETH_MII_
TXD1/
ETH_RMII
_TXD1
SPI6_
MOSI
USART6_
TX
EVEN
TOUT
PG14
-
-
-
-
-
-
-
-
-
FMC_A25
-
-
USART6_
CTS
FMC_
SDNCAS
DCMI_
D13
EVEN
TOUT
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
-
-
ETH_MII_
CRS
FMC_
SDCKE0
EVEN
TOUT
-
LCD_R0
Port
H
ETH_MII_ FMC_SDN
EVEN
TOUT
-
LCD_R1
COL
E0
I2C2_
SCL
OTG_HS_
ULPI_NXT
EVEN
TOUT
-
-
-
-
-
-
I2C2_ SPI5_N
SDA
FMC_SDN
WE
EVEN
TOUT
-
-
-
-
-
SS
I2C2_
SMBA
SPI5_
SCK
FMC_
SDNE1
DCMI_
D8
TIM12_CH1
-
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
DCMI_
D9
I2C3_
SCL
SPI5_
MISO
ETH_MII_
RXD3
FMC_
SDCKE1
PH7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_
SDA
DCMI_
HSYNC
EVEN
TOUT
PH8
PH9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D16
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
FMC_D23
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
LCD_G4
I2C3_
SMBA
DCMI_
D0
EVEN
TOUT
TIM12_CH2
TIM5_
CH1
DCMI_
D1
EVEN
TOUT
PH10
PH11
PH12
PH13
PH14
PH15
-
-
-
-
-
-
-
Port
H
TIM5_
CH2
DCMI_
D2
EVEN
TOUT
-
TIM5_
CH3
DCMI_
D3
EVEN
TOUT
-
TIM8_
CH1N
EVEN
TOUT
-
-
-
CAN1_TX
-
TIM8_
CH2N
DCMI_
D4
EVEN
TOUT
-
-
TIM8_
CH3N
DCMI_
D11
EVEN
TOUT
SPI2_
NSS/I2
S2_WS
TIM5_
CH4
DCMI_
D13
EVEN
TOUT
PI0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D24
LCD_G5
SPI2_
SCK/I2
S2_CK
DCMI_
D8
EVEN
TOUT
PI1
PI2
PI3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D25
FMC_D26
FMC_D27
LCD_G6
LCD_G7
TIM8_
CH4
SPI2_
MISO
I2S2ext_
SD
DCMI_
D9
EVEN
TOUT
Port I
SPI2_M
OSI/I2S
2_SD
TIM8_
ETR
DCMI_D
10
EVEN
TOUT
TIM8_
BKIN
FMC_
NBL2
DCMI_D
5
EVEN
TOUT
PI4
PI5
PI6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
LCD_B5
LCD_B6
TIM8_
CH1
FMC_
NBL3
DCMI_
VSYNC
EVEN
TOUT
TIM8_
CH2
DCMI_
D6
EVEN
TOUT
FMC_D28
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
TIM8_
CH3
DCMI_
D7
EVEN
TOUT
PI7
PI8
PI9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D29
LCD_B7
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
EVEN
VSYNC TOUT
CAN1_RX
FMC_D30
ETH_MII_
RX_ER
LCD_ EVEN
HSYNC TOUT
PI10
Port I PI11
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D31
OTG_HS_
ULPI_DIR
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
EVEN
HSYNC TOUT
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
EVEN
VSYNC TOUT
PI13
LCD_
CLK
EVEN
TOUT
PI14
EVEN
TOUT
PI15
LCD_R0
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
EVEN
TOUT
PJ0
EVEN
TOUT
PJ1
EVEN
TOUT
PJ2
EVEN
TOUT
PJ3
Port J
EVEN
TOUT
PJ4
EVEN
TOUT
PJ5
PJ6
PJ7
EVEN
TOUT
EVEN
TOUT
Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued)
AF0
SYS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
DCMI
AF14
LCD
AF15
SYS
Port
SPI3/
USART6/
CAN1/2/
OTG2_HS
/OTG1_
FS
TIM8/9/ I2C1/ SPI1/2/
10/11
SPI2/3/
SAI1
FMC/SDIO
/OTG2_FS
TIM1/2
TIM3/4/5
USART1/ UART4/5/7 TIM12/13/14
ETH
2/3
3/4/5/6
2/3
/8
/LCD
EVEN
TOUT
PJ8
PJ9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
LCD_B3
LCD_G5
LCD_G6
LCD_G7
LCD_B4
LCD_B5
LCD_B6
LCD_B7
LCD_DE
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PJ10
PJ11
PJ12
PJ13
PJ14
PJ15
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
EVEN
TOUT
Port J
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port K
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
STM32F427xx STM32F429xx
Memory mapping
5
Memory mapping
The memory map is shown in Figure 19.
Figure 19. Memory map
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06ꢉꢄꢂꢃꢂ9ꢂ
DocID024030 Rev 9
85/238
89
Memory mapping
STM32F427xx STM32F429xx
Table 13. STM32F427xx and STM32F429xx register boundary addresses
Bus
Boundary address
Peripheral
0xE00F FFFF - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xD000 0000 - 0xDFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xA000 1000 - 0xBFFF FFFF
0xA000 0000- 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x8000 0000 - 0x8FFF FFFF
0x7000 0000 - 0x7FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00- 0x5FFF FFFF
0x5006 0800 - 0X5006 0BFF
0x5005 0400 - X5006 07FF
0x5005 0000 - 0X5005 03FF
0x5004 0000- 0x5004 FFFF
0x5000 0000 - 0X5003 FFFF
Reserved
Cortex-M4
Cortex-M4 internal peripherals
FMC bank 6
FMC bank 5
Reserved
FMC control register
FMC bank 4
FMC bank 3
FMC bank 2
FMC bank 1
Reserved
AHB3
RNG
Reserved
AHB2
DCMI
Reserved
USB OTG FS
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Memory mapping
Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4008 0000- 0x4FFF FFFF
0x4004 0000 - 0x4007 FFFF
0x4002 BC00- 0x4003 FFFF
0x4002 B000 - 0x4002 BBFF
0x4002 9400 - 0x4002 AFFF
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0X4002 5000 - 0X4002 5FFF
0x4002 4000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0X4002 3400 - 0X4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2C00 - 0x4002 2FFF
0x4002 2800 - 0x4002 2BFF
0x4002 2400 - 0x4002 27FF
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0X4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
USB OTG HS
Reserved
DMA2D
Reserved
ETHERNET MAC
Reserved
DMA2
DMA1
Reserved
BKPSRAM
Flash interface register
RCC
AHB1
Reserved
CRC
Reserved
GPIOK
GPIOJ
GPIOI
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
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Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4001 6C00- 0x4001 FFFF
0x4001 6800 - 0x4001 6BFF
0x4001 5C00 - 0x4001 67FF
0x4001 5800 - 0x4001 5BFF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Reserved
LCD-TFT
Reserved
SAI1
SPI6
SPI5
SPI6
SPI5
Reserved
TIM11
TIM10
TIM9
EXTI
APB2
SYSCFG
SPI4
SPI1
SDIO
Reserved
ADC1 - ADC2 - ADC3
Reserved
USART6
USART1
Reserved
TIM8
TIM1
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Memory mapping
Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued)
Bus
Boundary address
Peripheral
0x4000 8000- 0x4000 FFFF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
UART8
UART7
DAC
PWR
Reserved
CAN2
CAN1
Reserved
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
SPI2 / I2S2
I2S2ext
IWDG
APB1
WWDG
RTC & BKP Registers
Reserved
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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Electrical characteristics
STM32F427xx STM32F429xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.3 V (for the
A
DD
1.7 V ≤V ≤3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 20.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 21.
Figure 20. Pin loading conditions
Figure 21. Pin input voltage
-#5 PIN
-#5 PIN
6
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).
-3ꢃꢒꢈꢃꢃ6ꢁ
-3ꢃꢒꢈꢃꢈ6ꢁ
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Electrical characteristics
6.1.6
Power supply scheme
Figure 22. Power supply scheme
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1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.17: Power supply supervisor and Section 3.18: Voltage
regulator
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is
OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4.
VDDA=VDD and VSSA=VSS.
Caution:
Each power supply pair (V /V , V
/V
...) must be decoupled with filtering ceramic
DD SS
DDA SSA
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
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Electrical characteristics
STM32F427xx STM32F429xx
6.1.7
Current consumption measurement
Figure 23. Current consumption measurement scheme
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6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
Table 14. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage (including VDDA, VDD and
VBAT)(1)
VDD–VSS
− 0.3
4.0
Input voltage on FT pins(2)
VSS − 0.3 VDD+4.0
V
Input voltage on TTa pins
VSS − 0.3
VSS − 0.3
VSS
4.0
4.0
9.0
50
VIN
Input voltage on any other pin
Input voltage on BOOT0 pin
Variations between different VDD power pins
|ΔVDDx
|
-
mV
Variations between all the different ground pins
including VREF-
|VSSX −VSS
|
-
50
see Section 6.3.15:
Absolute maximum
ratings (electrical
sensitivity)
VESD(HBM)
Electrostatic discharge voltage (human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
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Symbol
Electrical characteristics
Table 15. Current characteristics
Ratings
Max.
Unit
ΣIVDD
Σ IVSS
IVDD
Total current into sum of all VDD_x power lines (source)(1)
Total current out of sum of all VSS_x ground lines (sink)(1)
Maximum current into each VDD_x power line (source)(1)
Maximum current out of each VSS_x ground line (sink)(1)
Output current sunk by any I/O and control pin
270
− 270
100
IVSS
− 100
25
IIO
Output current sourced by any I/Os and control pin
Total output current sunk by sum of all I/O and control pins (2)
Total output current sourced by sum of all I/Os and control pins(2)
Injected current on FT pins (4)
− 25
120
mA
ΣIIO
− 120
− 5/+0
Injected current on NRST and BOOT0 pins (4)
(3)
IINJ(PIN)
Injected current on TTa pins(5)
±5
Total injected current (sum of all I/O and control pins)(6)
±25
(5)
ΣIINJ(PIN)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
− 65 to +150
°C
°C
Maximum junction temperature
125
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6.3
Operating conditions
6.3.1
General operating conditions
Table 17. General operating conditions
Symbol
Parameter
Conditions(1)
Min Typ
Max Unit
Power Scale 3 (VOS[1:0] bits in
PWR_CR register = 0x01), Regulator
ON, over-drive OFF
0
0
-
120
Over-
drive OFF
-
-
-
-
144
168
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
fHCLK Internal AHB clock frequency
Over-
drive ON
Over-
drive OFF
168
180
MHz
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
0
Over-
drive ON
Over-drive OFF
Over-drive ON
Over-drive OFF
Over-drive ON
0
-
-
-
-
-
42
45
84
90
3.6
fPCLK1 Internal APB1 clock frequency
fPCLK2 Internal APB2 clock frequency
0
0
0
VDD
Standard operating voltage
1.7(2)
Analog operating voltage
1.7(2)
-
2.4
(ADC limited to 1.2 M samples)
VDDA
(5)
Must be the same potential as VDD
V
(3)(4)
Analog operating voltage
2.4
-
-
3.6
3.6
(ADC limited to 2.4 M samples)
VBAT
Backup operating voltage
1.65
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz
HCLK max frequency
1.08 1.14 1.20
1.20 1.26 1.32
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
HCLK max frequency with over-drive
OFF or 168 MHz with over-drive ON
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
V12
V
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
HCLK max frequency with over-drive
OFF or 180 MHz with over-drive ON
1.26 1.32 1.40
Max frequency 120 MHz
Max frequency 144 MHz
Max frequency 168 MHz
1.10 1.14 1.20
1.20 1.26 1.32
1.26 1.32 1.38
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(6)
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Table 17. General operating conditions (continued)
Symbol
Parameter
Conditions(1)
Min Typ
Max Unit
2 V ≤VDD ≤3.6 V
− 0.3
− 0.3
-
-
5.5
Input voltage on RST and FT
pins(7)
VDD ≤2 V
5.2
VIN
V
VDDA
0.3
+
Input voltage on TTa pins
− 0.3
-
Input voltage on BOOT0 pin
0
-
-
-
-
-
-
-
-
-
9
LQFP100
-
465
641
500
385
526
513
WLCSP143
-
LQFP144
-
-
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(8)
UFBGA169
PD
mW
LQFP176
-
UFBGA176
-
LQFP208
-
1053
690
85
TFBGA216
-
Maximum power dissipation
Low power dissipation(9)
Maximum power dissipation
Low power dissipation(9)
6 suffix version
7 suffix version
− 40
− 40
− 40
− 40
− 40
− 40
Ambient temperature for 6 suffix
version
°C
°C
°C
105
105
125
105
125
TA
TJ
Ambient temperature for 7 suffix
version
Junction temperature range
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. DD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
V
Internal reset OFF).
3. When the ADC is used, refer to Table 74: ADC characteristics.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
6. The over-drive mode is not supported when the internal regulator is OFF.
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax
.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
.
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Table 18. Limitations depending on the operating power supply range
Maximum Flash
memory access
powersupply ADC operation frequency with
Maximum HCLK
frequency vs Flash
Operating
Possible Flash
memory
operations
I/O operation
memory wait states
range
no wait states
(fFlashmax
(1)(2)
)
168 MHz with 8 wait
states and over-drive
OFF
8-bit erase and
program
operations only
VDD =1.7 to Conversion time
No I/O
compensation
20 MHz(4)
22 MHz
24 MHz
30 MHz
2.1 V(3)
up to 1.2 Msps
180 MHz with 8 wait
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.1 to Conversion time
2.4 V up to 1.2 Msps
No I/O
compensation
180 MHz with 7 wait
states and over-drive
ON
16-bit erase and
program
operations
VDD = 2.4 to Conversion time
2.7 V up to 2.4 Msps
I/O compensation
works
180 MHz with 5 wait
states and over-drive
ON
32-bit erase and
program
operations
VDD = 2.7 to Conversion time
3.6 V(5)
up to 2.4 Msps
I/O compensation
works
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
4. Prefetch is not available.
5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
6.3.2
VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
to
EXT
the VCAP1/VCAP2 pins. C
is specified in Table 19.
EXT
Figure 24. External capacitor C
EXT
&
(65
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06ꢀꢅꢄꢂꢂ9ꢃ
1. Legend: ESR is the equivalent series resistance.
(1)
Table 19. VCAP1/VCAP2 operating conditions
Symbol
Parameter
Conditions
CEXT
ESR
Capacitance of external capacitor
ESR of external capacitor
2.2 µF
< 2 Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
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Electrical characteristics
6.3.3
Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for T .
A
Table 20. Operating conditions at power-up / power-down (regulator ON)
Symbol
Parameter
VDD rise time rate
VDD fall time rate
Min
Max
Unit
20
20
∞
∞
tVDD
µs/V
6.3.4
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for T .
A
(1)
Table 21. Operating conditions at power-up / power-down (regulator OFF)
Symbol
Parameter
VDD rise time rate
DD fall time rate
Conditions
Power-up
Power-down
Min
Max
Unit
20
20
20
20
∞
∞
∞
∞
tVDD
V
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up
VCAP_1 and VCAP_2 fall time rate Power-down
tVCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
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6.3.5
Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 22. reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.09
1.98
2.23
2.13
2.39
2.29
2.54
2.44
2.70
2.59
2.86
2.65
2.96
2.85
3.07
2.95
-
2.14 2.19
2.04 2.08
2.30 2.37
2.19 2.25
2.45 2.51
2.35 2.39
2.60 2.65
2.51 2.56
2.76 2.82
2.66 2.71
2.93 2.99
2.84 2.92
3.03 3.10
2.93 2.99
3.14 3.21
3.03 3.09
V
V
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
V
V
(1)
VPVDhyst
PVD hysteresis
100
-
mV
V
Falling edge
Rising edge
1.60
1.64
-
1.68 1.76
1.72 1.80
Power-on/power-down
reset threshold
VPOR/PDR
V
(1)
VPDRhyst
PDR hysteresis
40
-
mV
V
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
2.13
2.23
2.44
2.53
2.75
2.85
-
2.19 2.24
2.29 2.33
2.50 2.56
2.59 2.63
2.83 2.88
2.92 2.97
Brownout level 1
threshold
VBOR1
VBOR2
VBOR3
V
V
Brownout level 2
threshold
V
V
Brownout level 3
threshold
V
(1)
VBORhyst
BOR hysteresis
100
1.5
-
mV
TRSTTEMPO
POR reset temporization
0.5
3.0
ms
(1)(2)
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Electrical characteristics
Table 22. reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ Max Unit
InRush current on
voltage regulator power-
on (POR or wakeup
from Standby)
(1)
IRUSH
-
160
-
200
5.4
mA
µC
InRush energy on
voltage regulator power-
on (POR or wakeup
from Standby)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs
(1)
ERUSH
-
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6
Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are sbject to general
operating conditions for T .
A
(1)
Table 23. Over-drive switching characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HSI
-
45
-
HSE max for 4 MHz
and min for 26 MHz
Over_drive switch
enable time
45
-
100
Tod_swen
External HSE
50 MHz
-
-
40
20
-
-
-
µs
HSI
HSE max for 4 MHz
and min for 26 MHz.
Over_drive switch
disable time
20
80
Tod_swdis
External HSE
50 MHz
-
15
-
1. Guaranteed by design.
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STM32F427xx STM32F429xx
6.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 23: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are in input mode with a static value at V or V (no load).
DD SS
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted both to f frequency and V range
HCLK
DD
(see Table 18: Limitations depending on the operating power supply range).
•
•
Regulator ON
The voltage scaling and over-drive mode are adjusted to f
frequency as follows:
HCLK
–
–
–
Scale 3 for f
≤120 MHz
HCLK
Scale 2 for 120 MHz < f
Scale 1 for 144 MHz < f
≤144 MHz
HCLK
HCLK
PCLK1
≤180 MHz. The over-drive is only ON at 180 MHz.
= f /4, and f = f /2.
•
•
•
The system clock is HCLK, f
HCLK
PCLK2
HCLK
External clock frequency is 4 MHz and PLL is ON when f
is higher than 25 MHz.
HCLK
The maximum values are obtained for V = 3.6 V and a maximum ambient
DD
temperature (T ), and the typical values for T = 25 °C and V = 3.3 V unless
A
A
DD
otherwise specified.
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Electrical characteristics
Table 24. Typical and maximum current consumption in Run mode, code with data processing
(1)
running from Flash memory (ART accelerator enabled except prefetch) or RAM
Max(2)
Symbol
Parameter Conditions fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
180
168
150
144
120
98
89
75
72
54
43
29
16
13
11
5
104(5)
98(5)
84
81
58
45
30
20
16
13
9
123
116
100
96
72
56
38
34
30
27
23
21
20
69
66
57
56
43
32
22
12
10
22
21
20
20
141(5)
133(5)
115
112
85
90
66
All
Peripherals
60
30
25
16
8
45
enabled(3)(4)
46
43
39
36
4
4
8
34
Supply
current in
RUN mode
2
2
7
33
IDD
mA
180
168
150
144
120
90
60
30
25
16
8
44
41
36
33
25
20
14
8
47(5)
45(5)
39
37
29
21
15
8
87(5)
83(5)
73
72
56
41
All
Peripherals
28
disabled(3)
26
7
7
24
7
9
35
3
7
34
4
3
6
33
2
2
6
33
1. Code and data processing running from SRAM1 using boot pins.
2. Guaranteed by characterization.
3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
5. Guaranteed by test in production.
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STM32F427xx STM32F429xx
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Max(1)
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
TA=
25 °C
TA=85 °C TA=105 °C
180
168
150
144
120
90
60
30
25
16
8
103
98
87
85
66
54
37
20
17
12
7
112
107
95
92
71
58
39
24
21
16
11
8
140
126
112
108
85
69
47
39
35
30
24
22
21
87
76
70
68
56
46
33
31
28
25
23
21
20
151
144
128
124
99
80
55
51
48
42
37
35
34
106
93
86
84
69
57
41
44
41
38
35
34
33
All Peripherals
enabled(2)(3)
4
5
Supply
current in
RUN mode
2
3
7
IDD
mA
180
168
150
144
120
90
60
30
25
16
8
57
50
46
45
36
29
21
13
11
8
62
54
50
49
41
34
24
17
15
12
9
All Peripherals
disabled(3)
5
4
4
7
2
3
6.5
1. Guaranteed by characterization unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
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Electrical characteristics
Table 26. Typical and maximum current consumption in Sleep mode
Max(1)
Symbol
Parameter Conditions fHCLK (MHz)
Typ
Unit
TA =
TA =
TA =
25 °C
85 °C
105 °C
180
168
150
144
120
90
60
30
25
16
8
78
66
56
54
40
32
22
10
9
89(3)
75(3)
61
58
44
34
23
16
14
12
8
110
93
80
78
59
46
31
30
28
25
22
21
20
54
41
36
35
28
26
17
22
21
21
20
20
20
130(3)
110(3)
96
94
72
56
All
Peripherals
38
enabled(2)
43
40
5
40
3
35
4
3
7
34
Supply
current in
Sleep mode
2
2
6.5
26(3)
20(3)
17
16.5
14
13
9
33
IDD
mA
180
168
150
144
120
90
60
30
25
16
8
21
16
14
13
10
8
76(3)
58(3)
52
51
41
37
All
Peripherals
disabled
6
25
5
8
35
3
7
34
3
7
34
2
6
33
4
2
6
33
2
2
6
33
1. Guaranteed by characterization unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. Based on characterization, tested in production.
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Table 27. Typical and maximum current consumptions in Stop mode
Max(1)
VDD = 3.6 V
TA =
Typ
Symbol
Parameter
Conditions
Unit
TA =
TA =
TA =
25 °C
25 °C 85 °C 105 °C
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
0.40
0.35
0.29
0.23
1.50
1.50
1.10
1.10
14.00 25.00
14.00 25.00
10.00 18.00
10.00 18.00
Supply current in Stop
mode with voltage
regulator in main
regulator mode
Flash memory in Deep power
down mode, all oscillators OFF, no
independent watchdog
IDD_STOP_NM
(normal mode)
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
Supply current in Stop
mode with voltage
regulator in Low Power
regulator mode
Flash memory in Deep power
down mode, all oscillators OFF, no
independent watchdog
mA
Supply current in Stop
mode with voltage
regulator in main
regulator and under-
drive mode
Flash memory in Deep power
down mode, main regulator in
under-drive mode, all oscillators
OFF, no independent watchdog
0.19
0.10
0.50
0.40
6.00
4.00
9.00
7.00
IDD_STOP_UDM
(under-drive
mode)
Supply current in Stop
mode with voltage
regulator in Low Power
regulator and under-
drive mode
Flash memory in Deep power
down mode, Low Power regulator
in under-drive mode, all oscillators
OFF, no independent watchdog
1. Data based on characterization, tested in production.
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Table 28. Typical and maximum current consumptions in Standby mode
Typ(1)
Max(2)
TA =
TA =
TA =
TA = 25 °C
Symbol
Parameter
Conditions
25 °C 85 °C 105 °C Unit
VDD
1.7 V
=
VDD
2.4 V
=
VDD =
3.3 V
VDD = 3.6 V
Backup SRAM ON, low-speed
oscillator (LSE) and RTC ON
2.80
3.00
3.60
7.00
6.00
19.00 36.00
Backup SRAM OFF, low-
speed oscillator (LSE) and
RTC ON
2.30
2.60
3.10
16.00 31.00
Supply current
in Standby
mode
IDD_STBY
µA
Backup SRAM ON, RTC and
LSE OFF
2.30
1.70
2.50
1.90
2.90 6.00(3) 18.00(3) 35.00(3)
2.20 5.00(3) 15.00(3) 30.00(3)
Backup SRAM OFF, RTC and
LSE OFF
1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset
OFF), the typical current consumption is reduced by additional 1.2 µA.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Table 29. Typical and maximum current consumptions in V
Typ
mode
Max(2)
BAT
TA =
105 °C
TA = 25 °C
TA = 85 °C
Symbol Parameter
Conditions(1)
Unit
VBAT = VBAT= VBAT
1.7 V 2.4 V 3.3 V
=
VBAT = 3.6 V
Backup SRAM ON, low-speed
oscillator (LSE) and RTC ON
1.28
0.66
0.70
0.10
1.40
0.76
0.72
0.10
1.62
0.97
0.74
0.10
6
3
5
2
11
5
Backup SRAM OFF, low-speed
oscillator (LSE) and RTC ON
Backup
IDD_VBAT domainsupply
current
µA
Backup SRAM ON, RTC and
LSE OFF
10
4
Backup SRAM OFF, RTC and
LSE OFF
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization results.
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STM32F427xx STM32F429xx
Figure 25. Typical V
current consumption (LSE and RTC ON/backup RAM OFF)
BAT
ꢍ
ꢁꢂꢆ
ꢁ
ꢃꢂꢄꢆ6
ꢃꢂꢎ6
ꢃꢂꢅ6
ꢁ6
ꢁꢂꢉ6
ꢁꢂꢎ6
ꢍ6
ꢃꢂꢆ
ꢃ
ꢈꢂꢆ
ꢍꢂꢍ6
ꢍꢂꢄ6
ꢈ
ꢈ #
ꢁꢆ #
ꢆꢆ #
ꢅꢆ #
ꢃꢈꢆ #
4EMPERATURE
-3ꢍꢈꢉꢒꢈ6ꢃ
Figure 26. Typical V
current consumption (LSE and RTC ON/backup RAM ON)
BAT
ꢄ
ꢆ
ꢉ
ꢍ
ꢁ
ꢃ
ꢃꢂꢄꢆ6
ꢃꢂꢎ6
ꢃꢂꢅ6
ꢁ6
ꢁꢂꢉ6
ꢁꢂꢎ6
ꢍ6
ꢍꢂꢍ6
ꢍꢂꢄ6
ꢈ
ꢈ #
ꢁꢆ #
ꢆꢆ #
ꢅꢆ #
ꢃꢈꢆ #
4EMPERATURE
-3ꢍꢈꢉꢒꢃ6ꢃ
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Electrical characteristics
Additional current consumption
The MCU is placed under the following conditions:
•
•
•
All I/O pins are configured in analog mode.
The Flash memory access time is adjusted to fHCLK frequency.
The voltage scaling is adjusted to fHCLK frequency as follows:
–
–
–
Scale 3 for f
≤ 120 MHz,
HCLK
Scale 2 for 120 MHz < f
Scale 1 for 144 MHz < f
≤ 144 MHz
HCLK
HCLK
PCLK1
≤ 180 MHz. The over-drive is only ON at 180 MHz.
•
•
•
The system clock is HCLK, f
= f
/4, and f
= f
/2.
HCLK
HCLK
PCLK2
HSE crystal clock frequency is 25 MHz.
When the regulator is OFF, V12 is provided externally as described in Table 17:
General operating conditions
•
T = 25 °C .
A
Table 30. Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
(1)
V
=1.7 V
DD
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
168
150
144
120
90
88.2
74.3
71.3
52.9
42.6
28.6
15.7
12.3
40.6
30.6
32.6
24.7
19.7
13.6
7.7
All Peripheral
enabled
60
30
Supply current in
RUN mode from
VDD supply
25
IDD
mA
168
150
144
120
90
All Peripheral
disabled
60
30
25
6.7
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherls (such as ADC, or
DAC) is not included.
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Table 31. Typical current consumption in Run mode, code with data processing running
(1)
from Flash memory, regulator OFF (ART accelerator enabled except prefetch)
VDD=3.3 V
VDD=1.7 V
fHCLK
(MHz)
Symbol
Parameter
Conditions
Unit
IDD12
IDD
IDD12
IDD
168
150
144
120
90
77.8
70.8
64.5
49.9
39.2
27.2
15.6
13.6
38.2
34.6
31.3
24.0
18.1
12.9
7.2
1.3
1.3
1.3
1.2
1.3
1.2
1.2
1.2
1.3
1.3
1.3
1.2
1.4
1.2
1.2
1.2
76.8
69.8
63.6
49.3
38.7
26.8
15.4
13.5
37.0
33.4
30.3
23.2
18.0
12.5
6.9
1.0
1.0
1.0
0.9
1.0
0.9
0.9
0.9
1.0
1.0
1.0
0.9
1.0
0.9
0.9
0.9
All Peripherals
enabled
60
30
Supply current in
RUN mode from
V12 and VDD
supply
25
IDD12 / IDD
mA
168
150
144
120
90
All Peripherals
disabled
60
30
25
6.3
6.1
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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(1)
Table 32. Typical current consumption in Sleep mode, regulator ON, V =1.7 V
DD
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
Unit
168
150
144
120
90
65.5
55.5
53.5
39.0
31.6
21.7
9.8
All Peripherals enabled
60
30
25
8.8
Supply current in Sleep
mode from VDD supply
IDD
mA
168
150
144
120
90
15.7
13.7
12.7
9.7
All Peripherals disabled
7.7
60
5.7
30
4.7
25
2.8
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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STM32F427xx STM32F429xx
(1)
Table 33. Tyical current consumption in Sleep mode, regulator OFF
VDD=3.3 V
VDD=1.7 V
IDD12 IDD
Unit
Symbol
Parameter
Conditions
fHCLK (MHz)
IDD12
IDD
180
168
150
144
120
90
61.5
59.4
53.9
49.0
38.0
29.3
20.2
11.9
10.4
14.9
14.0
12.6
11.5
8.7
1.4
1.3
1.3
1.3
1.2
1.4
1.2
1.2
1.2
1.4
1.3
1.3
1.3
1.2
1.4
1.2
1.2
1.2
-
-
59.4
53.9
49.0
38.0
29.3
20.2
11.9
10.4
-
1.0
1.0
1.0
0.9
1.1
0.9
0.9
0.9
-
All Peripherals
enabled
60
30
Supply current
in Sleep mode
from V12 and
VDD supply
25
IDD12/IDD
mA
180
168
150
144
120
90
14.0
12.6
11.5
8.7
1.0
1.0
1.0
0.9
1.1
0.9
0.9
0.9
All Peripherals
disabled
7.1
7.1
60
5.0
5.0
30
3.1
3.1
25
2.8
2.8
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC,
or DAC) is not included.
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I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 56: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
ISW = VDD × fSW × C
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
is the MCU supply voltage
SW
V
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C + C
INT
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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STM32F427xx STM32F429xx
(1)
Table 34. Switching output I/O current consumption
I/O toggling
Symbol
Parameter
Conditions
Typ
Unit
frequency
(fsw)
2 MHz
8 MHz
0.0
0.2
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
0.6
VDD = 3.3 V
1.1
(2)
C= CINT
1.3
1.8
1.9
I/O switching
Current
IDDIO
mA
0.1
8 MHz
0.4
VDD = 3.3 V
CEXT = 0 pF
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
1.23
2.43
2.93
3.86
4.07
0.18
0.67
2.09
3.6
C = CINT + CEXT
+ CS
8 MHz
VDD = 3.3 V
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
CEXT = 10 pF
C = CINT + CEXT
+ CS
4.5
7.8
9.8
0.26
1.01
3.14
6.39
10.68
0.33
1.29
4.23
11.02
I/O switching
Current
IDDIO
mA
VDD = 3.3 V
8 MHz
CEXT = 22 pF
25 MHz
50 MHz
60 MHz
2 MHz
C = CINT + CEXT
+ CS
VDD = 3.3 V
8 MHz
CEXT = 33 pF
C = CINT + Cext
+ CS
25 MHz
50 MHz
1.
CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP176 package pin (pad removal).
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Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
•
•
•
•
•
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
I/O compensation cell enabled.
The ART accelerator is ON.
Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
HCLK is the system clock. f
= f
/4, and f
= f /2.
HCLK
PCLK1
HCLK
PCLK2
The given value is calculated by measuring the difference of current consumption
–
–
–
with all peripherals clocked off
with only one peripheral clocked on
f
f
= 180 MHz (Scale1 + over-drive ON), f
= 120 MHz (Scale 3)"
= 144 MHz (Scale 2),
HCLK
HCLK
HCLK
•
Ambient operating temperature is 25 °C and V =3.3 V.
DD
Table 35. Peripheral current consumption
I
DD( Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
GPIOA
2.50
2.56
2.44
2.50
2.44
2.44
2.39
2.33
2.39
2.33
2.33
27.00
0.44
0.78
25.33
24.72
28.50
2.36
2.36
2.29
2.36
2.29
2.29
2.22
2.15
2.22
2.15
2.15
24.86
0.42
0.69
23.26
22.71
26.32
2.08
2.08
2.00
2.08
2.00
2.00
2.00
1.92
2.00
1.92
1.92
21.92
0.33
0.58
20.50
20.00
23.33
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
AHB1
(up to
GPIOJ
µA/MHz
GPIOK
180 MHz)
OTG_HS+ULPI
CRC
BKPSRAM
DMA1
DMA2
DMA2D
ETH_MAC
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
21.56
20.07
17.75
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Table 35. Peripheral current consumption (continued)
I
DD( Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
OTG_FS
DCMI
25.67
3.72
2.28
26.67
3.40
2.36
23.58
AHB2
3.00
2.17
µA/MHz
(up to
180 MHz)
RNG
AHB3
FMC
21.39
19.79
17.50
µA/MHz
µA/MHz
(up to
180 MHz)
Bus matrix(2)
14.06
13.19
11.75
TIM2
TIM3
17.56
14.22
14.89
17.33
2.89
3.11
7.33
4.89
5.56
11.11
4.22
4.44
4.00
4.00
4.00
3.78
4.00
4.00
4.00
3.11
3.56
2.89
3.33
6.89
6.67
2.89
0.89
16.42
13.36
13.64
16.42
2.53
2.81
6.97
4.47
5.31
10.31
3.92
4.19
3.92
3.92
3.92
3.92
3.92
3.92
3.92
3.08
3.36
2.81
3.08
6.42
6.14
2.25
0.86
14.47
11.80
12.13
14.47
2.47
2.47
6.13
4.13
4.80
9.13
3.47
3.80
3.47
3.47
3.47
3.47
3.47
3.47
3.47
2.80
3.13
2.47
2.80
5.80
5.47
2.13
0.80
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
PWR
USART2
USART3
UART4
UART5
UART7
UART8
I2C1
APB1
µA/MHz
(up to
45 MHz)
I2C2
I2C3
SPI2(3)
SPI3(3)
I2S2
I2S3
CAN1
CAN2
DAC(4)
WWDG
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Electrical characteristics
Table 35. Peripheral current consumption (continued)
I
DD( Typ)(1)
Peripheral
Unit
Scale 1
Scale 2
Scale 3
SDIO
8.11
17.11
17.33
7.22
4.56
4.78
4.67
4.78
4.56
1.44
4.00
4.00
1.44
1.44
1.44
0.78
39.89
3.78
8.75
15.97
16.11
6.67
4.31
4.44
4.31
4.44
4.17
1.39
3.75
3.75
1.39
1.39
1.39
0.69
37.22
3.47
7.83
14.17
14.33
6.00
3.83
4.00
3.83
4.00
TIM1
TIM8
TIM9
TIM10
TIM11
ADC1(5)
ADC2(5)
ADC3(5)
SPI1
APB2
3.67
µA/MHz
1.17
(up to
90 MHz)
USART1
USART6
SPI4
3.33
3.33
1.17
1.17
1.17
0.67
33.17
3.17
SPI5
SPI6
SYSCFG
LCD_TFT
SAI1
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.8 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.6 mA per ADC for the analog part.
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6.3.8
Wakeup time from low-power modes
The wakeup times given in Table 36 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
•
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V =3.3 V.
DD
Table 36. Low-power mode wakeup timings
Typ(1)
Max(1)
Symbol
Parameter
Conditions
Unit
CPU
clock
cycle
(2)
tWUSLEEP
Wakeup from Sleep
-
6
-
-
Main regulator is ON
13.6
Main regulator is ON and Flash
memory in Deep power down mode
93
111
Wakeup from Stop mode
with MR/LP regulator in
normal mode
(2)
tWUSTOP
Low power regulator is ON
22
32
Low power regulator is ON and Flash
memory in Deep power down mode
103
126
µs
Main regulator in under-drive mode
(Flash memory in Deep power-down
mode)
105
128
Wakeup from Stop mode
with MR/LP regulator in
Under-drive mode
(2)
tWUSTOP
Low power regulator in under-drive
mode
125
318
155
412
(Flash memory in Deep power-down
mode )
tWUSTDBY Wakeup from Standby
(2)(3)
mode
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. WUSTDBY maximum value is given at –40 °C.
t
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Electrical characteristics
6.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 27.
The characteristics given in Table 37 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 37. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External user clock source
frequency(1)
fHSE_ext
1
-
50
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time(1)
OSC_IN rise or fall time(1)
5
-
-
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
10
Cin(HSE) OSC_IN input capacitance(1)
-
45
-
5
-
-
pF
%
DuCy(HSE) Duty cycle
55
±1
IL
OSC_IN Input leakage current
VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design.
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Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 28.
The characteristics given in Table 38 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 38. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User External clock source
frequency(1)
fLSE_ext
-
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level voltage
OSC32_IN high or low time(1)
450
tf(LSE)
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
OSC32_IN input capacitance(1)
-
-
50
Cin(LSE)
-
30
-
5
-
-
pF
%
DuCy(LSE) Duty cycle
70
±1
IL
OSC32_IN Input leakage current
VSS ≤VIN ≤VDD
-
µA
1. Guaranteed by design.
Figure 27. High-speed external clock source AC timing diagram
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Electrical characteristics
Figure 28. Low-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 39. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 39. HSE 4-26 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fOSC_IN
RF
Oscillator frequency
Feedback resistor
4
-
-
26
-
MHz
200
kΩ
V
DD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
-
-
450
530
-
-
IDD
HSE current consumption
HSE accuracy
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
(2)
ACCHSE
− 500
-
-
500
ppm
mA/V
ms
Gm_crit_max Maximum critical crystal gm
Startup
-
-
1
-
(3)
tSU(HSE
Startup time
VDD is stabilized
2
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization and not tested in production. It is measured
for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C .
C
L1
L2
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 29. Typical application with an 8 MHz crystal
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
(1)
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RF
Feedback resistor
LSE current consumption
LSE accuracy
-
18.4
-
1
MΩ
µA
IDD
-
-
-
(2)
ACCLSE
− 500
500
ppm
Gm_crit_max Maximum critical crystal gm
Startup
-
-
-
0.56 µA/V
(3)
tSU(LSE)
startup time
VDD is stabilized
2
-
s
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. Refer to application note AN2867.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 30. Typical application with a 32.768 kHz crystal
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6.3.10
Internal clock source characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
ambient temperature and V supply voltage conditions summarized in Table 17.
DD
High-speed internal (HSI) RC oscillator
(1)
Table 41. HSI oscillator characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
fHSI
Frequency
-
-
-
-
16
-
1
MHz
%
HSI user-trimming step (2)
Accuracy of the HSI oscillator
HSI oscillator startup time
-
-
TA = –40 to 105 °C(3) − 8
TA = –10 to 85 °C(3) − 4
4.5
4
%
ACCHSI
-
%
TA = 25 °C(4)
− 1
-
1
%
(2)
tsu(HSI)
-
-
2.2
4
µs
HSI oscillator power
consumption
(2)
IDD(HSI)
-
-
60
80
µA
1.
VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
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Figure 31. ACCHSI accuracy versus temperature
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1. Guaranteed by characterization results.
Low-speed internal (LSI) RC oscillator
(1)
Table 42. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(2)
fLSI
Frequency
17
-
32
15
47
40
kHz
µs
(3)
tsu(LSI)
LSI oscillator startup time
(3)
IDD(LSI)
LSI oscillator power consumption
-
0.4
0.6
µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.
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Electrical characteristics
Figure 32. ACC
versus temperature
LSI
-3ꢃꢒꢈꢃꢍ6ꢃ
6.3.11
PLL characteristics
The parameters given in Table 43 and Table 44 are derived from tests performed under
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 43. Main PLL characteristics
Symbol
Parameter
PLL input clock(1)
Conditions
Min
Typ
Max
Unit
fPLL_IN
0.95(2)
24
1
-
2.10
180
MHz
MHz
fPLL_OUT
PLL multiplier output clock
48 MHz PLL multiplier output
clock
fPLL48_OUT
fVCO_OUT
-
48
75
MHz
MHz
PLL VCO output
100
75
-
-
-
432
200
300
VCO freq = 100 MHz
VCO freq = 432 MHz
tLOCK
PLL lock time
µs
100
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Table 43. Main PLL characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RMS
-
25
-
peak
to
peak
Cycle-to-cycle jitter
Period Jitter
-
-
-
150
15
-
-
-
System clock
120 MHz
RMS
peak
to
200
Jitter(3)
ps
peak
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-
-
-
32
40
330
-
-
-
-
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
Ethernet
on 1000 samples
Cycle to cycle at 1 MHz
on 1000 samples
Bit Time CAN jitter
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
(4)
IDD(PLL)
PLL power consumption on VDD
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLL power consumption on
VDDA
(4)
IDDA(PLL)
-
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
Table 44. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
fPLLI2S_OUT
fVCO_OUT
PLLI2S input clock(1)
0.95(2)
1
-
2.10
216
432
200
300
-
MHz
MHz
MHz
PLLI2S multiplier output clock
PLLI2S VCO output
-
100
75
100
-
-
VCO freq = 100 MHz
VCO freq = 432 MHz
-
tLOCK
PLLI2S lock time
µs
-
RMS
90
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
-
ps
Master I2S clock jitter
WS I2S clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
90
-
-
ps
ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
400
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Table 44. PLLI2S (audio PLL) characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLI2S power consumption on
VDD
(4)
IDD(PLLI2S)
-
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLI2S power consumption on
VDDA
(4)
IDDA(PLLI2S)
-
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLSAI_IN
fPLLSAI_OUT
fVCO_OUT
PLLSAI input clock(1)
0.95(2)
1
-
2.10
216
432
200
300
-
MHz
MHz
MHz
PLLSAI multiplier output clock
PLLSAI VCO output
-
100
75
100
-
-
VCO freq = 100 MHz
VCO freq = 432 MHz
-
tLOCK
PLLSAI lock time
µs
-
RMS
90
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
peak
-
280
90
-
ps
ps
Main SAI clock jitter
Average frequency of
12.288 MHz
Jitter(3)
-
-
-
-
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
on 1000 samples
FS clock jitter
400
ps
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.40
0.75
PLLSAI power consumption on
VDD
(4)
IDD(PLLSAI)
-
-
mA
mA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
0.40
0.85
PLLSAI power consumption on
VDDA
(4)
IDDA(PLLSAI)
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
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6.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics). It is available only on the main PLL.
Table 46. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
md
Modulation frequency
Peak modulation depth
-
0.25
-
-
-
-
10
2
KHz
%
MODEPER * INCSTEP
1. Guaranteed by design.
2
15 − 1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
f
and f
must be expressed in Hz.
PLL_IN
Mod
As an example:
If f = 1 MHz, and f
= 1 kHz, the modulation depth (MODEPER) is given by
PLL_IN
MOD
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)]
f
must be expressed in MHz.
VCO_OUT
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN)
As a result:
mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak)
126/238
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Electrical characteristics
Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
nominal.
PLL_OUT
T
is the modulation period.
mode
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
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6.3.13
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 47. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Write / Erase 8-bit mode, VDD = 1.7 V
-
-
-
5
8
-
IDD
Supply current Write / Erase 16-bit mode, VDD = 2.1 V
Write / Erase 32-bit mode, VDD = 3.3 V
-
-
mA
12
Table 48. Flash memory programming
Symbol
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8/16/32
tprog
Word programming time
-
-
-
-
-
-
-
-
-
-
-
-
-
16
100(2) µs
800
Program/eraseparallelism
(PSIZE) = x 8
400
300
250
Program/eraseparallelism
(PSIZE) = x 16
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
600
500
ms
ms
s
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
1200 2400
Program/eraseparallelism
(PSIZE) = x 16
700
550
2
1400
1100
4
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
Program/eraseparallelism
(PSIZE) = x 16
1.3
1
2.6
2
Program/eraseparallelism
(PSIZE) = x 32
Program/eraseparallelism
(PSIZE) = x 8
16
11
8
32
Program/eraseparallelism
(PSIZE) = x 16
tME
Mass erase time
22
s
Program/eraseparallelism
(PSIZE) = x 32
16
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Symbol
Electrical characteristics
Table 48. Flash memory programming (continued)
Parameter
Conditions
Min(1) Typ Max(1) Unit
Program/eraseparallelism
(PSIZE) = x 8
-
-
-
16
11
8
32
22
16
Program/eraseparallelism
(PSIZE) = x 16
tBE
Bank erase time
s
Program/eraseparallelism
(PSIZE) = x 32
32-bit program operation
16-bit program operation
8-bit program operation
2.7
2.1
1.7
-
-
-
3.6
3.6
3.6
V
V
V
Vprog
Programming voltage
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.
Table 49. Flash memory programming with V
PP
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1) Unit
tprog
Double word programming
-
-
16
230
490
875
6.9
6.9
-
100(2)
µs
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
-
-
TA = 0 to +40 °C
VDD = 3.3 V
-
ms
VPP = 8.5 V
-
-
tME
tBE
Mass erase time
Bank erase time
-
-
s
s
-
-
Vprog
VPP
Programming voltage
VPP voltage range
2.7
7
3.6
9
V
V
-
Minimum current sunk on
the VPP pin
IPP
10
-
-
-
-
mA
Cumulative time during
which VPP is applied
(3)
tVPP
1
hour
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
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Table 50. Flash memory endurance and data retention
Value
Min(1)
Symbol
Parameter
Conditions
Unit
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
NEND Endurance
kcycles
10
1 kcycle(2) at TA = 85 °C
30
10
20
tRET
Data retention 1 kcycle(2) at TA = 105 °C
Years
10 kcycles(2) at TA = 55 °C
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
6.3.14
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
DD
SS
A device reset allows normal operations to be resumed.
The test results are given in Table 51. They are based on the EMS levels and classes
defined in application note AN1709.
Table 51. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP176, TA =
+25 °C, fHCLK = 168 MHz, conforms
to IEC 61000-4-2
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
4A
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP176, TA =+25 °C,
fHCLK = 168 MHz, conforms to
IEC 61000-4-2
VEFTB
When the application is exposed to a noisy environment, it is recommended to avoid pin
exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, PH2, PH3, PH4, PH5, PA3, PA4, PA5, PA6, PA7, PC4, and PC5.
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
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Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
•
•
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
?
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 52. EMI characteristics
Max vs.
Max vs.
Monitored
frequency band
[fHSE/fCPU
]
[fHSE/fCPU]
Symbol Parameter
Conditions
Unit
25/168 MHz 25/180 MHz
0.1 to 30 MHz
30 to 130 MHz
16
23
19
23
VDD = 3.3 V, TA = 25 °C, LQFP176
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral
clocks enabled, clock dithering
disabled.
dBµV
130 MHz to
1GHz
25
22
SAE EMI Level
0.1 to 30 MHz
30 to 130 MHz
4
17
8
4
-
dBµV
-
SEMI
Peak level
16
10
VDD = 3.3 V, TA = 25 °C, LQFP176
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral
clocks enabled, clock dithering
enabled
130 MHz to
1GHz
11
16
SAE EMI level
3.5
3.5
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6.3.15
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.
Table 53. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS-001
2
2000
TA = +25 °C conforming to ANSI/ESD S5.3.1,
LQFP100/144/176, UFBGA169/176,
TFBGA176 and WLCSP143 packages
V
C3
C3
250
250
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to ANSI/ESD S5.3.1,
LQFP208 package
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
•
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 54. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
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6.3.16
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard, 3 V-capable I/O pins) should be avoided during normal product
DD
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 55.
Table 55. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on BOOT0 pin
− 0
− 0
NA
NA
Injected current on NRST pin
Injected current on PA0, PA1, PA2, PA3, PA6, PA7, PB0,
PC0, PC1, PC2, PC3, PC4, PC5, PH1, PH2, PH3, PH4, PH5
IINJ
− 0
NA
mA
Injected current on TTa pins: PA4 and PA5
Injected current on any other FT pin
− 0
− 5
+5
NA
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
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6.3.17
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 17. All I/Os are
CMOS and TTL compliant.
Table 56. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.35VDD − 0.04
(1)
FT, TTa and NRST I/O input
low level voltage
1.7 V≤VDD≤3.6 V
-
-
(2)
0.3VDD
VIL
V
1.75 V≤VDD ≤3.6 V, –
40 °C≤TA ≤105 °C
-
-
-
BOOT0 I/O input low level
voltage
0.1VDD+0.1(1)
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
-
0.45VDD+0.3(1)
FT, TTa and NRST I/O input
high level voltage(5)
1.7 V≤VDD≤3.6 V
-
-
(2)
0.7VDD
1.75 V≤VDD ≤3.6 V, –
40 °C≤TA ≤105 °C
VIH
V
BOOT0 I/O input high level
voltage
0.17VDD+0.7(1)
-
-
-
-
-
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
FT, TTa and NRST I/O input
hysteresis
(3)
1.7 V≤VDD≤3.6 V
10%VDD
1.75 V≤VDD ≤3.6 V, –
40 °C≤TA ≤105 °C
VHYS
V
BOOT0 I/O input hysteresis
0.1
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
I/O input leakage current (4)
VSS ≤VIN ≤VDD
VIN = 5 V
-
-
-
-
1
3
Ilkg
µA
I/O FT input leakage current (5)
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Electrical characteristics
Table 56. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
30
40
50
Weak pull-up
equivalent
resistor(6)
RPU
VIN = VSS
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7
10
40
14
50
kΩ
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
30
Weak pull-
down
RPD
VIN = VDD
equivalent
resistor(7)
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7
-
10
5
14
-
(8)
CIO
I/O pin capacitance
-
pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 35.
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Figure 35. FT I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA (with a relaxed V /V ) except PC13, PC14, PC15 and PI8 which
OL OH
can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
•
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
ΣI
(see Table 15).
VDD
•
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
ΣI
(see Table 15).
VSS
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Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 17. All I/Os are CMOS and TTL compliant.
Table 57. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
(1)
VOL
Output low level voltage for an I/O pin
CMOS port(2)
IIO = +8 mA
-
0.4
V
(3)
VOH
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
VDD − 0.4
-
2.7 V ≤VDD ≤3.6 V
(1)
VOL
TTL port(2)
IIO =+ 8mA
-
0.4
V
(3)
VOH
2.4
-
2.7 V ≤VDD ≤3.6 V
(1)
VOL
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
-
1.3(4)
IIO = +20 mA
V
(3)
VDD−1.3(4)
-
2.7 V ≤VDD ≤3.6 V
VOH
VOL
-
0.4(4)
(1)
IIO = +6 mA
V
(3)
VDD−0.4(4)
-
-
1.8 V ≤VDD ≤3.6 V
VOH
VOL
0.4(5)
(1)
IIO = +4 mA
V
VOH
VDD−0.4(5)
-
(3)
1.7 V ≤VDD ≤3.6V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data.
5. Guaranteed by design.
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 36 and
Table 58, respectively.
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 17.
(1)(2)
Table 58. I/O AC characteristics
OSPEEDRy
[1:0] bit
Symbol
Parameter
Conditions
Min
Typ
Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
4
2
fmax(IO)out Maximum frequency(3)
8
4
3
MHz
ns
00
Output high to low level fall
time and output low to high
level rise time
tf(IO)out
/
CL = 50 pF, VDD = 1.7 V to
3.6 V
-
-
100
tr(IO)out
CL = 50 pF, VDD≥ 2.7 V
CL = 50 pF, VDD≥ 1.8 V
CL = 50 pF, VDD≥ 1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD≥ 1.8 V
CL = 10 pF, VDD≥ 1.7 V
CL = 50 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 50 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 40 pF, VDD ≥2.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 40 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD ≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
12.5
10
fmax(IO)out Maximum frequency(3)
MHz
50
20
01
12.5
10
Output high to low level fall
time and output low to high
level rise time
6
tf(IO)out
tr(IO)out
/
ns
MHz
ns
20
10
50(4)
100(4)
25
fmax(IO)out Maximum frequency(3)
50
10
42.5
6
Output high to low level fall
time and output low to high
level rise time
4
tf(IO)out
tr(IO)out
/
10
6
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Electrical characteristics
(1)(2)
Table 58. I/O AC characteristics
Parameter
(continued)
OSPEEDRy
[1:0] bit
Symbol
Conditions
Min
Typ
Max Unit
value(1)
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥ 1.8 V
CL = 30 pF, VDD ≥ 1.7 V
CL = 10 pF, VDD≥ 2.7 V
CL = 10 pF, VDD ≥ 1.8 V
CL = 10 pF, VDD ≥ 1.7 V
CL = 30 pF, VDD ≥ 2.7 V
CL = 30 pF, VDD ≥1.8 V
CL = 30 pF, VDD ≥1.7 V
CL = 10 pF, VDD ≥ 2.7 V
CL = 10 pF, VDD ≥1.8 V
CL = 10 pF, VDD ≥1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100(4)
50
42.5
MHz
fmax(IO)out Maximum frequency(3)
180(4)
100
72.5
4
11
6
Output high to low level fall
time and output low to high
level rise time
7
tf(IO)out
/
ns
2.5
tr(IO)out
3.5
4
Pulse width of external signals
-
tEXTIpw detected by the EXTI
controller
-
10
-
-
ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 36. I/O AC characteristics definition
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STM32F427xx STM32F429xx
6.3.18
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R (see Table 56: I/O static characteristics).
PU
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the ambient temperature and V supply voltage conditions summarized
DD
in Table 17.
Table 59. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
NRST Input filtered pulse
VIN = VSS
30
-
40
-
50
kΩ
ns
ns
µs
(2)
VF(NRST)
100
(2)
VNF(NRST)
NRST Input not filtered pulse
VDD > 2.7 V
300
20
-
-
-
TNRST_OUT Generated reset pulse duration
Internal Reset source
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 37. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
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Electrical characteristics
6.3.19
TIM timer characteristics
The parameters given in Table 60 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)(2)
Table 60. TIMx characteristics
Conditions(3)
Symbol
Parameter
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK
=
tTIMxCLK
1
-
180 MHz
tres(TIM)
Timer resolution time
AHB/APBx prescaler>4,
fTIMxCLK = 90 MHz
tTIMxCLK
1
-
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK/2
16/32
0
-
MHz
bit
f
TIMxCLK = 180 MHz
ResTIM
Timer resolution
Maximum possible count
with 32-bit counter
65536 ×
65536
tMAX_COUNT
tTIMxCLK
-
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
6.3.20
Communications interfaces
I2C interface characteristics
2
2
The I C interface meets the timings requirements of the I C-bus specification and user
manual rev. 03 for:
•
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
2
The I C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0090 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V is disabled, but is still present. Refer to
DD
2
for more details on the I C I/O characteristics
Section 6.3.17: I/O port characteristics
.
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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Electrical characteristics
STM32F427xx STM32F429xx
(1)
Table 61. I2C analog filter characteristics
Symbol
Parameter
Min
Max
Unit
Maximum pulse width of spikes that
are suppressed by the analog filter
tAF
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 62 for the SPI interface are
derived from tests performed under the ambient temperature, f frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
(1)
Table 62. SPI dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode, SPI1/4/5/6,
2.7 V≤VDD≤3.6 V
45
45
Receiver
-
-
Slave mode,
SPI1/4/5/6,
2.7 V≤VDD≤3.6 V
Transmitter/
full-duplex
38(2)
fSCK
SPI clock frequency
MHz
1/tc(SCK)
Master mode, SPI1/2/3/4/5/6,
1.7 V≤VDD≤3.6 V
22.5
22.5
70
-
-
Slave mode, SPI1/2/3/4/5/6,
1.7 V≤VDD≤3.6 V
Duty cycle of SPI clock
frequency
Duty(SCK)
Slave mode
30
50
%
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(1)
Table 62. SPI dynamic characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Master mode, SPI presc = 2,
2.7 V≤VDD≤3.6 V
TPCLK
tw(SCKH)
TPCLK − 0.5
TPCLK+0.5
SCK high and low time
Master mode, SPI presc = 2,
1.7 V≤VDD≤3.6 V
TPCLK
tw(SCKL)
TPCLK − 2
TPCLK+2
tsu(NSS)
th(NSS)
tsu(MI)
tsu(SI)
th(MI)
NSS setup time
NSS hold time
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
4TPCLK
-
-
2TPCLK
3
0
-
-
-
-
-
-
Data input setup time
Data input hold time
Slave mode
-
ns
Master mode
0.5
2
-
th(SI)
Slave mode
-
ta(SO
)
Data output access time Slave mode, SPI presc = 2
Slave mode, SPI1/4/5/6,
2.7 V≤VDD≤3.6 V
Data output disable time
0
4TPCLK
0
0
-
-
-
8.5
16.5
13
tdis(SO)
Slave mode, SPI1/2/3/4/5/6 and
1.7 V≤VDD≤3.6 V
Slave mode (after enable edge),
SPI1/4/5/6 and 2.7V ≤ VDD ≤ 3.6V
11
14
15.5
15.5
-
Slave mode (after enable edge),
SPI2/3, 2.7 V≤VDD≤3.6 V
-
15
tv(SO)
th(SO)
Data output valid/hold
time
Slave mode (after enable edge),
SPI1/4/5/6, 1.7 V≤VDD≤3.6 V
-
19
Slave mode (after enable edge),
SPI2/3, 1.7 V≤VDD≤3.6 V
ns
-
17.5
2.5
Master mode (after enable edge),
-
SPI1/4/5/6, 2.7 V≤VDD≤3.6 V
Data output valid time
tv(MO)
Master mode (after enable edge),
SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V
-
-
-
4.5
-
th(MO)
Master mode (after enable edge)
0
Data output hold time
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
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Electrical characteristics
STM32F427xx STM32F429xx
Figure 38. SPI timing diagram - slave mode and CPHA = 0
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144/238
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Electrical characteristics
Figure 40. SPI timing diagram - master mode
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Electrical characteristics
STM32F427xx STM32F429xx
I2S interface characteristics
2
Unless otherwise specified, the parameters given in Table 63 for the I S interface are
derived from tests performed under the ambient temperature, f
frequency and V
PCLKx
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
2
(1)
Table 63. I S dynamic characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
I2S clock frequency
-
256x8K
256xFs(2)
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
fCK
MHz
%
64xFs
DCK
tv(WS)
I2S clock frequency duty cycle Slave receiver
30
0
70
6
-
WS valid time
WS hold time
WS setup time
WS hold time
Master mode
Master mode
Slave mode
th(WS)
0
tsu(WS)
1
-
th(WS)
Slave mode
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
7.5
2
-
Data input setup time
Data input hold time
-
ns
0
-
0
-
tv(SD_ST)
th(SD_ST)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
-
-
27
Data output valid time
tv(SD_MT)
20
-
th(SD_MT) Data output hold time
Master transmitter (after enable edge)
2.5
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
Note:
Refer to the I2S section of RM0090 reference manual for more details on the sampling
frequency (F ).
S
f
, f , and D values reflect only the digital peripheral behavior. The values of these
CK
MCK CK
parameters might be slightly impacted by the source clock precision. D depends mainly
CK
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
maximum value is supported for each mode/condition.
S
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Electrical characteristics
2
(1)
Figure 41. I S slave timing diagram (Philips protocol)
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byte.
2
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Figure 42. I S master timing diagram (Philips protocol)
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T
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1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
STM32F427xx STM32F429xx
SAI characteristics
Unless otherwise specified, the parameters given in Table 64 for SAI are derived from tests
performed under the ambient temperature, f frequency and VDD supply voltage
PCLKx
conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C=30 pF
Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
(1)
Table 64. SAI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCKL
SAI Main clock output
-
256 x 8K 256xFs(2)
MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
64xFs
FSCK
SAI clock frequency
MHz
%
SAI clock frequency duty
cycle
DSCK
Slave receiver
30
70
tv(FS)
FS valid time
FS setup time
Master mode
Slave mode
8
2
8
0
5
3
0
0
22
-
tsu(FS)
Master mode
Slave mode
-
th(FS)
FS hold time
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Master receiver
Slave receiver
Master receiver
Slave receiver
-
Data input setup time
Data input hold time
-
-
ns
-
tv(SD_ST)
th(SD_ST)
Slave transmitter (after enable
edge)
-
-
22
20
-
Data output valid time
Data output hold time
Master transmitter (after enable
edge)
tv(SD_MT)
th(SD_MT)
Master transmitter (after enable
edge)
8
1. Guaranteed by characterization results.
2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)
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Electrical characteristics
Figure 43. SAI master timing waveforms
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Electrical characteristics
STM32F427xx STM32F429xx
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 65. USB OTG full speed startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB OTG full speed transceiver startup time
1
µs
1. Guaranteed by design.
Table 66. USB OTG full speed DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1) Typ. Max.(1) Unit
USB OTG full speed
VDD transceiver operating
voltage
3.0(2)
-
3.6
V
I(USB_FS_DP/DM,
USB_HS_DP/DM)
(3)
VDI
Differential input sensitivity
0.2
0.8
1.3
-
-
-
-
Input
levels
Differential common mode
range
(3)
VCM
Includes VDI range
2.5
2.0
V
V
Single ended receiver
threshold
(3)
VSE
VOL Static output level low
VOH Static output level high
RL of 1.5 kΩto 3.6 V(4)
-
-
-
0.3
3.6
Output
levels
(4)
RL of 15 kΩto VSS
2.8
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
17
21
24
USB_HS_DP/DM)
RPD
VIN = VDD
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
0.65
1.5
1.1
1.8
2.0
2.1
kΩ
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
VIN = VSS
VIN = VSS
RPU
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design.
RL is the load connected on the USB OTG full speed drivers.
4.
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
Note:
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Figure 45. USB OTG full speed timings: definition of data signal rise and fall time
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Table 67. USB OTG full speed electrical characteristics(1)
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
Driving high or
low
ZDRV
Output driver impedance(3)
28
44
Ω
1. Guaranteed by design.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 70 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 69
and V supply voltage conditions summarized in Table 68, with the following configuration:
DD
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified
Capacitive load C = 30 pF, unless otherwise specified
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 68. USB HS DC electrical characteristics
Symbol
Input level
Parameter
Min.(1)
Max.(1)
Unit
VDD
USB OTG HS operating voltage
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
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Symbol
STM32F427xx STM32F429xx
(1)
Table 69. USB HS clock timing parameters
Parameter
Min
Typ
Max
Unit
f
HCLK value to guarantee proper operation of
30
-
-
MHz
USB HS interface
FSTART_8BIT
FSTEADY
DSTART_8BIT
DSTEADY
Frequency (first transition)
8-bit ±10%
54
59.97
40
60
60
50
50
66
60.03
60
MHz
MHz
%
Frequency (steady state) ±500 ppm
Duty cycle (first transition)
8-bit ±10%
Duty cycle (steady state) ±500 ppm
49.975
50.025
%
Time to reach the steady state frequency and
duty cycle after the first transition
tSTEADY
-
-
1.4
ms
ms
µs
tSTART_DEV
Peripheral
-
-
-
-
5.6
-
Clock startup time after the
de-assertion of SuspendM
tSTART_HOST
Host
PHY preparation time after the first transition
of the input clock
tPREP
-
-
-
1. Guaranteed by design.
Figure 46. ULPI timing diagram
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(1)
Table 70. Dynamic characteristics: USB ULPI
Symbol
Parameter
Conditions
Min.
Typ.
Max. Unit
tSC
tHC
tSD
tHD
Control in (ULPI_DIR, ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
2
-
-
-
-
-
-
-
-
0.5
1.5
2
Data in hold time
2.7 V < VDD < 3.6 V,
CL = 15 pF and
OSPEEDRy[1:0] = 11
-
-
-
9
9.5
ns
2.7 V < VDD < 3.6 V,
tDC/tDD Data/control output delay
CL = 20 pF and
OSPEEDRy[1:0] = 10
12
15
1.7 V < VDD < 3.6 V,
CL = 15 pF and
OSPEEDRy[1:0] = 11
1. Guaranteed by characterization results.
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Ethernet characteristics
Unless otherwise specified, the parameters given in Table 71, Table 72 and Table 73 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 17 with the following configuration:
•
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF for 2.7 V < V < 3.6 V
DD
Capacitive load C = 20 pF for 1.71 V < V < 3.6 V
DD
Measurement points are done at CMOS levels: 0.5V
.
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Table 71 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 47 shows the corresponding timing diagram.
Figure 47. Ethernet SMI timing diagram
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Table 71. Dynamics characteristics: Ethernet MAC signals for SMI
Symbol
Parameter
Min
Typ
Max
Unit
tMDC
MDC cycle time(2.38 MHz)
411
6
420
425
Td(MDIO) Write data valid time
tsu(MDIO) Read data setup time
th(MDIO) Read data hold time
1. Guaranteed by characterization results.
10
-
13
-
ns
12
0
-
-
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Electrical characteristics
Table 72 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the
corresponding timing diagram.
Figure 48. Ethernet RMII timing diagram
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Table 72. Dynamics characteristics: Ethernet MAC signals for RMII
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tsu(RXD) Receive data setup time
tih(RXD) Receive data hold time
tsu(CRS) Carrier sense setup time
tih(CRS) Carrier sense hold time
1.5
0
-
-
-
-
1.71 V < VDD < 3.6 V
1
-
-
1
-
-
ns
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
8
10.5
10.5
11
11
12
14
12.5
14.5
Transmit enable valid delay
td(TXEN)
time
8
8
td(TXD)
Transmit data valid delay time
8
1. Guaranteed by characterization results.
Table 73 gives the list of Ethernet MAC signals for MII and Figure 48 shows the
corresponding timing diagram.
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STM32F427xx STM32F429xx
Figure 49. Ethernet MII timing diagram
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Table 73. Dynamics characteristics: Ethernet MAC signals for MII
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tsu(RXD) Receive data setup time
tih(RXD) Receive data hold time
9
10
9
-
-
-
-
tsu(DV)
tih(DV)
tsu(ER)
tih(ER)
Data valid setup time
Data valid hold time
Error setup time
-
-
1.71 V < VDD < 3.6 V
8
-
-
6
-
-
ns
Error hold time
8
-
-
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
2.7 V < VDD < 3.6 V
1.71 V < VDD < 3.6 V
8
10
10
10
10
14
16
15
17
td(TXEN) Transmit enable valid delay time
8
7.5
7.5
td(TXD)
Transmit data valid delay time
1. Guaranteed by characterization results.
CAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
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6.3.21
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 74 are derived from tests
performed under the ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 17.
Table 74. ADC characteristics
Conditions
Symbol
Parameter
Power supply
Min
Typ
Max
Unit
VDDA
1.7(1)
1.7(1)
-
-
-
3.6
VDDA
-
VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage
V
VREF-
Negative reference voltage
-
0
VDDA = 1.7(1) to 2.4 V
0.6
15
30
18
MHz
MHz
fADC
ADC clock frequency
V
DDA = 2.4 to 3.6 V
ADC = 30 MHz,
12-bit resolution
0.6
36
f
-
-
-
1764
17
kHz
(2)
fTRIG
External trigger frequency
Conversion voltage range(3)
-
1/fADC
0
VAIN
-
VREF+
V
(VSSA or VREF-
tied to ground)
See Equation 1 for
(2)
RAIN
External input impedance
Sampling switch resistance
-
-
-
-
-
50
6
kΩ
kΩ
pF
details
(2)(4)
RADC
Internal sample and hold
capacitor
(2)
CADC
4
7
f
f
ADC = 30 MHz
ADC = 30 MHz
-
-
-
0.100
3(5)
0.067
2(5)
16
µs
1/fADC
µs
Injection trigger conversion
latency
(2)
tlat
-
-
-
Regular trigger conversion
latency
(2)
tlatr
-
-
1/fADC
µs
fADC = 30 MHz
0.100
-
(2)
tS
Sampling time
Power-up time
3
-
-
480
3
1/fADC
µs
(2)
tSTAB
2
fADC = 30 MHz
12-bit resolution
0.50
0.43
0.37
0.30
-
-
-
-
16.40
16.34
16.27
16.20
µs
µs
f
ADC = 30 MHz
10-bit resolution
ADC = 30 MHz
Total conversion time (including
sampling time)
f
(2)
tCONV
µs
8-bit resolution
fADC = 30 MHz
6-bit resolution
µs
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
1/fADC
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Table 74. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
12-bit resolution
Single ADC
-
-
2
Msps
12-bit resolution
Sampling rate
-
-
3.75
Msps
Interleave Dual ADC
mode
(2)
fS
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
-
-
-
-
6
Msps
µA
Interleave Triple ADC
mode
ADC VREF DC current
consumption in conversion
mode
(2)
IVREF+
300
1.6
500
1.8
ADC VDDA DC current
consumption in conversion
mode
(2)
IVDDA
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by characterization results.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA
4. ADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74.
.
R
Equation 1: R
max formula
AIN
(k – 0.5)
----------------------------------------------------------------
– RADC
RAIN
=
fADC × CADC × ln(2N + 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 75. ADC static accuracy at f
= 18 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(1)
Unit
ET
Total unadjusted error
±3
±4
f
ADC =18 MHz
EO
EG
ED
EL
Offset error
±2
±1
±1
±2
±3
±3
±2
±3
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
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a
Table 76. ADC static accuracy at f
= 30 MHz
Typ
ADC
Symbol
Parameter
Test conditions
Max(1)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
±2
±5
±2.5
±3
f
ADC = 30 MHz,
±1.5
±1.5
±1
RAIN < 10 kΩ,
Gain error
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
LSB
Differential linearity error
Integral linearity error
±2
±1.5
±3
1. Guaranteed by characterization results.
Table 77. ADC static accuracy at f
= 36 MHz
ADC
Symbol
Parameter
Test conditions
Typ
Max(1)
Unit
ET
Total unadjusted error
±4
±7
f
ADC =36 MHz,
EO
EG
ED
EL
Offset error
±2
±3
±2
±3
±3
±6
±3
±6
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
LSB
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
(1)
Table 78. ADC dynamic accuracy at f
= 18 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
10.3
64
10.4
64.2
65
-
-
-
-
bits
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
dB
THD
Total harmonic distortion
− 67
− 72
1. Guaranteed by characterization results.
(1)
Table 79. ADC dynamic accuracy at f
= 36 MHz - limited test conditions
ADC
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
ENOB
SINAD
SNR
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
10.6
66
10.8
67
-
-
-
-
bits
f
ADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
64
68
dB
THD
Total harmonic distortion
− 70
− 72
1. Guaranteed by characterization results.
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Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
Section 6.3.17 does not affect the ADC accuracy.
and ΣI
in
INJ(PIN)
INJ(PIN)
Figure 50. ADC accuracy characteristics
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6
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1. See also Table 76.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
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Figure 51. Typical connection diagram using the ADC
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1. Refer to Table 74 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
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General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 52 or Figure 53,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 52. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
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1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA
.
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Figure 53. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
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1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA
.
6.3.22
Temperature sensor characteristics
Table 80. Temperature sensor characteristics
Symbol
Parameter
Min
Typ Max
Unit
(1)
TL
VSENSE linearity with temperature
-
-
1
2.5
0.76
6
2
°C
mV/°C
V
Avg_Slope(1) Average slope
(1)
V25
Voltage at 25 °C
Startup time
-
(2)
tSTART
-
10
-
µs
(2)
TS_temp
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
µs
1. Guaranteed by characterization results.
2. Guaranteed by design.
Table 81. Temperature sensor calibration values
Symbol
Parameter
Memory address
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL1
TS_CAL2
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
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STM32F427xx STM32F429xx
6.3.23
V
monitoring characteristics
BAT
Table 82. V
monitoring characteristics
BAT
Symbol
Parameter
Resistor bridge for VBAT
Min
Typ
Max
Unit
R
Q
-
-
50
4
-
-
KΩ
Ratio on VBAT measurement
Error on Q
Er(1)
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
(2)(2)
TS_vbat
5
-
-
µs
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.24
Reference voltage
The parameters given in Table 83 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 17.
DD
Table 83. internal reference voltage
Symbol
VREFINT
Parameter
Conditions
Min
Max
Unit
Typ
Internal reference voltage
–40 °C < TA < +105 °C 1.18 1.21
1.24
V
ADC sampling time when reading the
internal reference voltage
(1)
TS_vrefint
10
-
-
-
µs
Internal reference voltage spread over the
temperature range
(2)
VRERINT_s
VDD = 3V 10mV
3
5
mV
(2)
TCoeff
Temperature coefficient
Startup time
-
-
30
6
50
10
ppm/°C
µs
(2)
tSTART
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production
Table 84. Internal reference voltage calibration values
Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B
Symbol
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Electrical characteristics
6.3.25
DAC electrical characteristics
Table 85. DAC characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
Comments
VDDA Analog supply voltage
-
1.7(1)
1.7(1)
0
-
-
-
3.6
3.6
0
V
V
V
-
Reference supply
voltage
VREF+
-
VREF+ ≤VDDA
VSSA Ground
-
-
RLOAD
connected
to VSSA
5
-
-
-
-
DAC output
buffer ON
(2)
RLOAD Resistive load
kΩ
RLOAD
connected
to VDDA
25
When the buffer is OFF, the
Minimum resistive load
kΩ between DAC_OUT and VSS
to have a 1% accuracy is
1.5 MΩ
Impedance output with
buffer OFF
(2)
RO
-
-
-
15
Maximum capacitive load at
pF DAC_OUT pin (when the
buffer is ON).
(2)
CLOAD Capacitive load
-
-
-
-
-
50
-
DAC_O
It gives the maximum output
excursion of the DAC.
Lower DAC_OUT
UT
0.2
V
voltage with buffer ON
min(2)
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x1C7) to
(0xE38) at VREF+ = 1.7 V
DAC_O
Higher DAC_OUT
UT
VDDA
− 0.2
-
-
-
-
-
-
-
0.5
-
V
mV
V
voltage with buffer ON
max(2)
DAC_O Lower DAC_OUT
UT
voltage with buffer
-
min(2) OFF
It gives the maximum output
excursion of the DAC.
DAC_O Higher DAC_OUT
VREF+
−
1LSB
UT
voltage with buffer
max(2) OFF
With no load, worst code
(0x800) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
-
-
-
-
170 240
DAC DC VREF current
consumption in
quiescent mode
(Standby mode)
(4)
IVREF+
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
50
75
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Electrical characteristics
STM32F427xx STM32F429xx
Table 85. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
Comments
With no load, middle code
(0x800) on the inputs
-
-
280 380 µA
DAC DC VDDA
(4)
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs
IDDA
current consumption in
quiescent mode(3)
-
-
-
475 625 µA
Differential non
linearity Difference
Given for the DAC in 10-bit
configuration.
-
-
±0.5 LSB
DNL(4) between two
consecutive code-
1LSB)
Given for the DAC in 12-bit
configuration.
-
-
-
-
-
-
±2 LSB
±1 LSB
Integral non linearity
(difference between
Given for the DAC in 10-bit
configuration.
measured value at
INL(4) Code i and the value
at Code i on a line
Given for the DAC in 12-bit
configuration.
-
-
-
±4 LSB
drawn between Code
0 and last Code 1023)
Given for the DAC in 12-bit
configuration
-
-
-
-
-
-
-
-
-
-
-
-
±10 mV
±3 LSB
±12 LSB
Offset error
(difference between
measured value at
Code (0x800) and the
ideal value = VREF+/2)
Given for the DAC in 10-bit at
VREF+ = 3.6 V
Offset(4)
Given for the DAC in 12-bit at
VREF+ = 3.6 V
Gain
Given for the DAC in 12-bit
configuration
Gain error
error(4)
±0.5
%
Settling time (full
scale: for a 10-bit input
code transition
tSETTLIN between the lowest
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
-
-
3
6
µs
(4)
and the highest input
G
codes when
DAC_OUT reaches
final value ±4LSB
Total Harmonic
Distortion
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(4)
-
-
-
-
-
-
-
dB
Buffer ON
Max frequency for a
correct DAC_OUT
Update change when small
rate(2) variation in the input
code (from code i to
MS/ CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
1
s
i+1LSB)
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Electrical characteristics
Table 85. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min Typ Max Unit
Comments
Wakeup time from off
tWAKEUP state (Setting the ENx
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
(
-
-
-
6.5
10
µs
4)
bit in the DAC Control
register)
Power supply rejection
PSRR+
ratio (to VDDA) (static
DC measurement)
-
–67 –40 dB No RLOAD, CLOAD = 50 pF
(2)
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization.
Figure 54. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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STM32F427xx STM32F429xx
6.3.26
FMC characteristics
Unless otherwise specified, the parameters given in Table 86 to Table 101 for the FMC
interface are derived from tests performed under the ambient temperature, f
frequency
HCLK
and V supply voltage conditions summarized in Table 17, with the following configuration:
DD
•
Output speed is set to OSPEEDRy[1:0] = 10 except at V range 1.7 to 2.1V where
OSPEEDRy[1:0] = 11
DD
•
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 55 through Figure 58 represent asynchronous waveforms and Table 86 through
Table 93 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
AddressSetupTime = 0x1
AddressHoldTime = 0x1
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
BusTurnAroundDuration = 0x0
For SDRAM memories, V ranges from 2.7 to 3.6 V and maximum frequency
FMC_SDCLK = 90 MHz
DD
•
For Mobile LPSDR SDRAM memories, V ranges from 1.7 to 1.95 V and maximum
frequency FMC_SDCLK = 84 MHz
DD
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Electrical characteristics
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
(1)(2)
read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
2THCLK − 0.5 2 THCLK+0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FMC_NEx low to FMC_NOE low
FMC_NOE low time
0
1
2THCLK
2THCLK+ 0.5
th(NE_NOE)
tv(A_NE)
th(A_NOE)
tv(BL_NE)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
0
-
2
-
-
Address hold time after FMC_NOE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
0
-
2
-
th(BL_NOE)
tsu(Data_NE)
tsu(Data_NOE)
0
THCLK + 2.5
THCLK +2
-
-
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Electrical characteristics
STM32F427xx STM32F429xx
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
(1)(2)
read timings
(continued)
Symbol
Parameter
Min
Max
Unit
th(Data_NOE)
th(Data_NE)
tv(NADV_NE)
tw(NADV)
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0
0
-
-
ns
ns
ns
ns
-
0
-
THCLK +1
1. CL = 30 pF.
2. Guaranteed by characterization results.
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
7THCLK+0.5
7THCLK+1
tw(NOE)
FMC_NWE low time
5THCLK − 1.5 5THCLK +2
ns
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5THCLK+1.5
-
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK+1
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
170/238
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Electrical characteristics
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
T
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(1)(2)
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FMC_NE low time
3THCLK
3THCLK+1
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
FMC_NEx low to FMC_NWE low
FMC_NWE low time
THCLK − 0.5 THCLK+ 0.5
THCLK
THCLK+ 0.5
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
THCLK +1.5
-
-
0
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
THCLK+0.5
-
-
1.5
THCLK+0.5
-
THCLK+ 2
-
-
th(Data_NWE) Data hold time after FMC_NWE high
tv(NADV_NE) FMC_NEx low to FMC_NADV low
THCLK+0.5
-
-
0.5
tw(NADV)
FMC_NADV low time
THCLK+ 0.5
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
(1)(2)
NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
8THCLK+1
8THCLK+2
ns
tw(NWE)
6THCLK − 1
6THCLK+2
-
ns
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK+1.5
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
4THCLK+1
ns
1. CL = 30 pF.
2. Guaranteed by characterization results.
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms
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Electrical characteristics
(1)(2)
Table 90. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
Parameter
FMC_NE low time
Min
Max
Unit
tw(NE)
tv(NOE_NE)
ttw(NOE)
3THCLK − 1 3THCLK+0.5
ns
ns
ns
ns
ns
ns
ns
FMC_NEx low to FMC_NOE low
FMC_NOE low time
2THCLK − 0.5
2THCLK
THCLK − 1
THCLK+1
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
1
-
-
2
2
0
THCLK − 0.5 THCLK+0.5
FMC_AD(address) valid hold time after
FMC_NADV high)
th(AD_NADV)
0
-
ns
th(A_NOE)
th(BL_NOE)
Address hold time after FMC_NOE high
FMC_BL time after FMC_NOE high
FMC_NEx low to FMC_BL valid
THCLK − 0.5
-
-
ns
ns
ns
ns
ns
ns
ns
0
tv(BL_NE)
-
2
-
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NE)
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
THCLK+1.5
THCLK+1
-
0
0
-
th(Data_NOE)
1. CL = 30 pF.
-
2. Guaranteed by characterization results.
(1)(2)
Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
8THCLK+0.5
8THCLK+2
ns
tw(NOE)
5THCLK − 1
5THCLK +1.5
-
ns
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5
FMC_NEx hold time after FMC_NWAIT
invalid
th(NE_NWAIT)
4THCLK+1
ns
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
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Table 92. Asynchronous multiplexed PSRAM/NOR write timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
FMC_NE low time
4THCLK
THCLK − 1
2THCLK
THCLK
-
4THCLK+0.5 ns
THCLK+0.5 ns
2THCLK+0.5 ns
FMC_NEx low to FMC_NWE low
FMC_NWE low time
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
th(AD_NADV)
th(A_NWE)
th(BL_NWE)
tv(BL_NE)
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
-
ns
ns
ns
ns
ns
ns
ns
ns
0
1
FMC_NEx low to FMC_NADV low
FMC_NADV low time
0.5
THCLK − 0.5 THCLK+ 0.5
FMC_AD(adress) valid hold time after FMC_NADV high)
Address hold time after FMC_NWE high
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
THCLK − 2
-
-
THCLK
THCLK − 2
-
-
2
tv(Data_NADV)
th(Data_NWE)
1. CL = 30 pF.
-
THCLK +1.5 ns
ns
Data hold time after FMC_NWE high
THCLK +0.5
-
2. Guaranteed by characterization results.
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Electrical characteristics
(1)(2)
Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
FMC_NWE low time
9THCLK
9THCLK+0.5
ns
tw(NWE)
7THCLK
7THCLK+2
-
ns
ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
6THCLK+1.5
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT)
invalid
4THCLK–1
-
ns
1. CL = 30 pF.
2. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 59 through Figure 62 represent synchronous waveforms and Table 94 through
Table 97 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
•
•
•
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
MemoryType = FMC_MemoryType_CRAM;
WriteBurst = FMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period (with maximum
FMC_CLK = 90 MHz).
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STM32F427xx STM32F429xx
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
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Dꢊ#,+,ꢑ./%,ꢋ
&-#?./%
T
T
T
Hꢊ#,+(ꢑ!$6ꢋ
Dꢊ#,+,ꢑ!$)6ꢋ
T
T
T
SUꢊ!$6ꢑ#,+(ꢋ
SUꢊ!$6ꢑ#,+(ꢋ
Dꢊ#,+,ꢑ!$6ꢋ
Hꢊ#,+(ꢑ!$6ꢋ
&-#?!$;ꢃꢆꢇꢈ=
!$;ꢃꢆꢇꢈ=
T
$ꢃ
$ꢁ
T
SUꢊ.7!)46ꢑ#,+(ꢋ
Hꢊ#,+(ꢑ.7!)46ꢋ
&-#?.7!)4
ꢊ7!)4#&' ꢏ ꢃBꢌ
7!)40/, ꢓ ꢈBꢋ
T
T
SUꢊ.7!)46ꢑ#,+(ꢋ
Hꢊ#,+(ꢑ.7!)46ꢋ
&-#?.7!)4
ꢊ7!)4#&' ꢏ ꢈBꢌ
7!)40/, ꢓ ꢈBꢋ
T
T
Hꢊ#,+(ꢑ.7!)46ꢋ
SUꢊ.7!)46ꢑ#,+(ꢋ
-3ꢍꢁꢎꢆꢎ6ꢃ
(1)(2)
Max
Table 94. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Unit
tw(CLK)
FMC_CLK period
2THCLK − 1
-
0
-
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKH_NExH)
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
-
THCLK
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
0
-
0
td(CLKL-AV)
td(CLKH-AIV)
td(CLKL-NOEL)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
-
0
-
0
-
THCLK+0.5
ns
ns
ns
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high
THCLK −0.5
-
0.5
-
td(CLKL-ADV)
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
-
0
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Electrical characteristics
(1)(2)
Table 94. Synchronous multiplexed NOR/PSRAM read timings
(continued)
Parameter
Min
Max
Unit
FMC_A/D[15:0] valid data before FMC_CLK
high
tsu(ADV-CLKH)
th(CLKH-ADV)
5
-
ns
FMC_A/D[15:0] valid data after FMC_CLK high
0
4
0
-
-
ns
ns
ns
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
Figure 60. Synchronous multiplexed PSRAM write timings
"53452. ꢏ ꢈ
T
T
Wꢊ#,+ꢋ
Wꢊ#,+ꢋ
&-#?#,+
$ATA LATENCY ꢏ ꢈ
Dꢊ#,+,ꢑ.%X,ꢋ
T
T
Dꢊ#,+(ꢑ.%X(ꢋ
&-#?.%X
T
T
Dꢊ#,+,ꢑ.!$6,ꢋ
Dꢊ#,+,ꢑ.!$6(ꢋ
&-#?.!$6
T
Dꢊ#,+(ꢑ!)6ꢋ
T
T
Dꢊ#,+,ꢑ!6ꢋ
&-#?!;ꢁꢆꢇꢃꢄ=
T
Dꢊ#,+(ꢑ.7%(ꢋ
Dꢊ#,+,ꢑ.7%,ꢋ
&-#?.7%
T
T
T
Dꢊ#,+,ꢑ!$)6ꢋ
T
Dꢊ#,+,ꢑ$ATAꢋ
Dꢊ#,+,ꢑ$ATAꢋ
Dꢊ#,+,ꢑ!$6ꢋ
&-#?!$;ꢃꢆꢇꢈ=
!$;ꢃꢆꢇꢈ=
$ꢃ
$ꢁ
&-#?.7!)4
ꢊ7!)4#&' ꢏ ꢈBꢌ
7!)40/, ꢓ ꢈBꢋ
T
T
Hꢊ#,+(ꢑ.7!)46ꢋ
SUꢊ.7!)46ꢑ#,+(ꢋ
T
Dꢊ#,+(ꢑ.",(ꢋ
&-#?.",
-3ꢍꢁꢎꢆꢅ6ꢃ
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(1)(2)
Table 95. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK − 1
-
1.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
THCLK
-
0
-
0
td(CLKL-AV)
td(CLKH-AIV)
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
-
0
-
THCLK
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
-
0
-
THCLK−0.5
-
3
-
0
-
3
-
0
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
THCLK−0.5
-
4
0
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
T
T
Wꢊ#,+ꢋ
Wꢊ#,+ꢋ
&-#?#,+
T
T
Dꢊ#,+(ꢑ.%X(ꢋ
Dꢊ#,+,ꢑ.%X,ꢋ
$ATA LATENCY ꢏ ꢈ
Dꢊ#,+,ꢑ.!$6(ꢋ
&-#?.%X
T
T
Dꢊ#,+,ꢑ.!$6,ꢋ
&-#?.!$6
&-#?!;ꢁꢆꢇꢈ=
T
T
Dꢊ#,+(ꢑ!)6ꢋ
Dꢊ#,+,ꢑ!6ꢋ
T
T
Dꢊ#,+,ꢑ./%,ꢋ
Dꢊ#,+(ꢑ./%(ꢋ
&-#?./%
T
T
SUꢊ$6ꢑ#,+(ꢋ
Hꢊ#,+(ꢑ$6ꢋ
T
T
Hꢊ#,+(ꢑ$6ꢋ
SUꢊ$6ꢑ#,+(ꢋ
&-#?$;ꢃꢆꢇꢈ=
&-#?.7!)4
$ꢃ
$ꢁ
T
T
T
SUꢊ.7!)46ꢑ#,+(ꢋ
Hꢊ#,+(ꢑ.7!)46ꢋ
ꢊ7!)4#&' ꢏ ꢃBꢌ
7!)40/, ꢓ ꢈBꢋ
T
T
Hꢊ#,+(ꢑ.7!)46ꢋ
SUꢊ.7!)46ꢑ#,+(ꢋ
&-#?.7!)4
ꢊ7!)4#&' ꢏ ꢈBꢌ
7!)40/, ꢓ ꢈBꢋ
T
SUꢊ.7!)46ꢑ#,+(ꢋ
Hꢊ#,+(ꢑ.7!)46ꢋ
-3ꢍꢁꢎꢆꢒ6ꢃ
(1)(2)
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
2THCLK − 1
-
ns
ns
t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
-
0.5
td(CLKH-
FMC_CLK high to FMC_NEx high (x= 0…2)
THCLK
-
0
-
ns
ns
ns
NExH)
td(CLKL-
FMC_CLK low to FMC_NADV low
-
NADVL)
td(CLKL-
FMC_CLK low to FMC_NADV high
0
NADVH)
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25)
-
0
ns
ns
ns
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25)
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low
THCLK − 0.5
-
-
THCLK+2
td(CLKH-
FMC_CLK high to FMC_NOE high
THCLK − 0.5
-
-
ns
ns
NOEH)
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
5
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Symbol
STM32F427xx STM32F429xx
(1)(2)
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
(continued)
Parameter
Min
Max
Unit
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
0
4
-
ns
th(CLKH-
FMC_NWAIT valid after FMC_CLK high
0
NWAIT)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Figure 62. Synchronous non-multiplexed PSRAM write timings
T
T
Wꢊ#,+ꢋ
Wꢊ#,+ꢋ
&-#?#,+
T
T
Dꢊ#,+,ꢑ.%X,ꢋ
&-#?.%X
Dꢊ#,+(ꢑ.%X(ꢋ
$ATA LATENCY ꢏ ꢈ
Dꢊ#,+,ꢑ.!$6(ꢋ
T
T
Dꢊ#,+,ꢑ.!$6,ꢋ
&-#?.!$6
&-#?!;ꢁꢆꢇꢈ=
&-#?.7%
T
Dꢊ#,+(ꢑ!)6ꢋ
T
T
Dꢊ#,+,ꢑ!6ꢋ
TDꢊ#,+(ꢑ.7%(ꢋ
Dꢊ#,+,ꢑ.7%,ꢋ
T
T
Dꢊ#,+,ꢑ$ATAꢋ
Dꢊ#,+,ꢑ$ATAꢋ
&-#?$;ꢃꢆꢇꢈ=
$ꢃ
$ꢁ
&-#?.7!)4
ꢊ7!)4#&' ꢏ ꢈBꢌ 7!)40/, ꢓ ꢈBꢋ
&-#?.",
T
T
Dꢊ#,+(ꢑ.",(ꢋ
SUꢊ.7!)46ꢑ#,+(ꢋ
T
Hꢊ#,+(ꢑ.7!)46ꢋ
-3ꢍꢁꢎꢄꢈ6ꢃ
(1)(2)
Max
Table 97. Synchronous non-multiplexed PSRAM write timings
Symbol
Parameter
Min
Unit
t(CLK)
FMC_CLK period
2THCLK − 1
-
0.5
-
ns
ns
ns
ns
ns
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
-
THCLK
-
0
-
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
0
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Electrical characteristics
(1)(2)
Table 97. Synchronous non-multiplexed PSRAM write timings
(continued)
Parameter
FMC_CLK high to FMC_Ax invalid (x=16…25)
Min
Max
Unit
td(CLKH-AIV)
0
-
0
ns
ns
ns
ns
ns
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
-
THCLK−0.5
-
-
2.5
-
0
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
THCLK−0.5
-
4
0
1. CL = 30 pF.
2. Guaranteed by characterization results.
PC Card/CompactFlash controller waveforms and timings
Figure 63 through Figure 68 represent synchronous waveforms, and Table 98 and Table 99
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x04;
COM.FMC_WaitSetupTime = 0x07;
COM.FMC_HoldSetupTime = 0x04;
COM.FMC_HiZSetupTime = 0x00;
ATT.FMC_SetupTime = 0x04;
ATT.FMC_WaitSetupTime = 0x07;
ATT.FMC_HoldSetupTime = 0x04;
ATT.FMC_HiZSetupTime = 0x00;
IO.FMC_SetupTime = 0x04;
IO.FMC_WaitSetupTime = 0x07;
IO.FMC_HoldSetupTime = 0x04;
IO.FMC_HiZSetupTime = 0x00;
TCLRSetupTime = 0;
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
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Figure 63. PC Card/CompactFlash controller waveforms for common memory read
access
ꢊꢃꢋ
&-#?.#%ꢉ?ꢁ
&-#?.#%ꢉ?ꢃ
T
Hꢊ.#%Xꢑ!)ꢋ
T
Vꢊ.#%Xꢑ!ꢋ
&-#?!;ꢃꢈꢇꢈ=
T
T
T
Hꢊ.#%Xꢑ.2%'ꢋ
Hꢊ.#%Xꢑ.)/2$ꢋ
T
T
Dꢊ.2%'ꢑ.#%Xꢋ
Dꢊ.)/2$ꢑ.#%Xꢋ
Hꢊ.#%Xꢑ.)/72
ꢋ
&-#?.2%'
&-#?.)/72
&-#?.)/2$
&-#?.7%
T
T
Wꢊ./%ꢋ
Dꢊ.#%ꢉ?ꢃꢑ./%ꢋ
&-#?./%
T
T
Hꢊ./%ꢑ$ꢋ
SUꢊ$ꢑ./%ꢋ
&-#?$;ꢃꢆꢇꢈ=
-3ꢍꢁꢎꢄꢃ6ꢃ
1. FMC_NCE4_2 remains high (inactive during 8-bit access.
Figure 64. PC Card/CompactFlash controller waveforms for common memory write
access
&-#?.#%ꢉ?ꢃ
&-#?.#%ꢉ?ꢁ
&-#?!;ꢃꢈꢇꢈ=
(IGH
T
T
Hꢊ.#%ꢉ?ꢃꢑ!)ꢋ
Vꢊ.#%ꢉ?ꢃꢑ!ꢋ
T
T
T
Hꢊ.#%ꢉ?ꢃꢑ.2%'ꢋ
Hꢊ.#%ꢉ?ꢃꢑ.)/2$ꢋ
Hꢊ.#%ꢉ?ꢃꢑ.)/72ꢋ
T
T
Dꢊ.2%'ꢑ.#%ꢉ?ꢃꢋ
Dꢊ.)/2$ꢑ.#%ꢉ?ꢃꢋ
&-#?.2%'
&-#?.)/72
&-#?.)/2$
T
T
T
Dꢊ.#%ꢉ?ꢃꢑ.7%ꢋ
Wꢊ.7%ꢋ
Dꢊ.7%ꢑ.#%ꢉ?ꢃꢋ
&-#?.7%
&-#?./%
-%-X(): ꢏꢃ
T
Dꢊ$ꢑ.7%ꢋ
T
T
Vꢊ.7%ꢑ$ꢋ
Hꢊ.7%ꢑ$ꢋ
&-#?$;ꢃꢆꢇꢈ=
-3ꢍꢁꢎꢄꢁ6ꢃ
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Electrical characteristics
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory
read access
&-#?.#%ꢉ?ꢃ
T
T
Hꢊ.#%ꢉ?ꢃꢑ!)ꢋ
Vꢊ.#%ꢉ?ꢃꢑ!ꢋ
&-#?.#%ꢉ?ꢁ
&-#?!;ꢃꢈꢇꢈ=
(IGH
&-#?.)/72
&-#?.)/2$
T
T
Hꢊ.#%ꢉ?ꢃꢑ.2%'ꢋ
Dꢊ.2%'ꢑ.#%ꢉ?ꢃꢋ
&-#?.2%'
&-#?.7%
T
T
T
Dꢊ./%ꢑ.#%ꢉ?ꢃꢋ
Dꢊ.#%ꢉ?ꢃꢑ./%ꢋ
Wꢊ./%ꢋ
&-#?./%
T
T
Hꢊ./%ꢑ$ꢋ
SUꢊ$ꢑ./%ꢋ
ꢊꢃꢋ
&-#?$;ꢃꢆꢇꢈ=
-3ꢍꢁꢎꢄꢍ6ꢃ
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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Figure 66. PC Card/CompactFlash controller waveforms for attribute memory
write access
&-#?.#%ꢉ?ꢃ
(IGH
&-#?.#%ꢉ?ꢁ
&-#?!;ꢃꢈꢇꢈ=
T
T
Hꢊ.#%ꢉ?ꢃꢑ!)ꢋ
Vꢊ.#%ꢉ?ꢃꢑ!ꢋ
&-#?.)/72
&-#?.)/2$
T
T
Dꢊ.2%'ꢑ.#%ꢉ?ꢃꢋ
Hꢊ.#%ꢉ?ꢃꢑ.2%'ꢋ
&-#?.2%'
T
T
Wꢊ.7%ꢋ
Dꢊ.#%ꢉ?ꢃꢑ.7%ꢋ
&-#?.7%
T
Dꢊ.7%ꢑ.#%ꢉ?ꢃꢋ
&-#?./%
T
Vꢊ.7%ꢑ$ꢋ
&-#?$;ꢎꢇꢈ=ꢊꢃꢋ
-3ꢍꢁꢎꢄꢉ6ꢃ
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access
&-#?.#%ꢉ?ꢃ
&-#?.#%ꢉ?ꢁ
T
T
Hꢊ.#%ꢉ?ꢃꢑ!)ꢋ
Vꢊ.#%Xꢑ!ꢋ
&-#?!;ꢃꢈꢇꢈ=
&-#?.2%'
&-#?.7%
&-#?./%
&-#?.)/72
T
T
Wꢊ.)/2$ꢋ
Dꢊ.)/2$ꢑ.#%ꢉ?ꢃꢋ
&-#?.)/2$
T
T
Dꢊ.)/2$ꢑ$ꢋ
SUꢊ$ꢑ.)/2$ꢋ
&-#?$;ꢃꢆꢇꢈ=
-3ꢍꢁꢎꢄꢆ6ꢃ
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Electrical characteristics
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access
&-#?.#%ꢉ?ꢃ
&-#?.#%ꢉ?ꢁ
T
T
Hꢊ.#%ꢉ?ꢃꢑ!)ꢋ
Vꢊ.#%Xꢑ!ꢋ
&-#?!;ꢃꢈꢇꢈ=
&-#?.2%'
&-#?.7%
&-#?./%
&-#?.)/2$
T
T
Wꢊ.)/72ꢋ
Dꢊ.#%ꢉ?ꢃꢑ.)/72ꢋ
&-#?.)/72
!44X(): ꢏꢃ
T
Hꢊ.)/72ꢑ$ꢋ
T
Vꢊ.)/72ꢑ$ꢋ
&-#?$;ꢃꢆꢇꢈ=
-3ꢍꢁꢎꢄꢄ6ꢃ
Table 98. Switching characteristics for PC Card/CF read and write cycles
(1)(2)
in attribute/common space
Symbol
Parameter
Min
Max
Unit
tv(NCEx-A)
th(NCEx_AI)
td(NREG-NCEx)
th(NCEx-NREG)
td(NCEx-NWE)
tw(NWE)
FMC_Ncex low to FMC_Ay valid
FMC_NCEx high to FMC_Ax invalid
FMC_NCEx low to FMC_NREG valid
FMC_NCEx high to FMC_NREG invalid
FMC_NCEx low to FMC_NWE low
FMC_NWE low width
-
0
ns
ns
ns
ns
ns
0
-
-
1
THCLK − 2
-
-
5THCLK
8THCLK − 0.5
5THCLK+1
-
8THCLK+0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(NWE_NCEx)
tV(NWE-D)
FMC_NWE high to FMC_NCEx high
FMC_NWE low to FMC_D[15:0] valid
FMC_NWE high to FMC_D[15:0] invalid
FMC_D[15:0] valid before FMC_NWE high
FMC_NCEx low to FMC_NOE low
FMC_NOE low width
-
0
-
th(NWE-D)
9THCLK − 0.5
13THCLK − 3
-
td(D-NWE)
td(NCEx-NOE)
tw(NOE)
5THCLK
8 THCLK − 0.5 8 THCLK+0.5
td(NOE_NCEx)
tsu (D-NOE)
th(NOE-D)
FMC_NOE high to FMC_NCEx high
FMC_D[15:0] valid data before FMC_NOE high
FMC_NOE high to FMC_D[15:0] invalid
5THCLK − 1
-
-
-
THCLK
0
1. CL = 30 pF.
2. Guaranteed by characterization results.
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Table 99. Switching characteristics for PC Card/CF read and write cycles
(1)(2)
in I/O space
Parameter
FMC_NIOWR low width
Symbol
Min
Max
Unit
tw(NIOWR)
tv(NIOWR-D)
th(NIOWR-D)
8THCLK − 0.5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FMC_NIOWR low to FMC_D[15:0] valid
FMC_NIOWR high to FMC_D[15:0] invalid
-
0
9THCLK − 2
-
td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid
th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid
td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid
th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid
-
5THCLK
-
5THCLK
-
5THCLK
6THCLK+2
8THCLK − 0.5
THCLK
0
-
tw(NIORD)
tsu(D-NIORD)
td(NIORD-D)
FMC_NIORD low width
8THCLK+0.5
FMC_D[15:0] valid before FMC_NIORD high
FMC_D[15:0] valid after FMC_NIORD high
-
-
1. CL = 30 pF.
2. Guaranteed by characterization results.
NAND controller waveforms and timings
Figure 69 through Figure 72 represent synchronous waveforms, and Table 100 and
Table 101 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
COM.FMC_SetupTime = 0x01;
COM.FMC_WaitSetupTime = 0x03;
COM.FMC_HoldSetupTime = 0x02;
COM.FMC_HiZSetupTime = 0x01;
ATT.FMC_SetupTime = 0x01;
ATT.FMC_WaitSetupTime = 0x03;
ATT.FMC_HoldSetupTime = 0x02;
ATT.FMC_HiZSetupTime = 0x01;
Bank = FMC_Bank_NAND;
MemoryDataWidth = FMC_MemoryDataWidth_16b;
ECC = FMC_ECC_Enable;
ECCPageSize = FMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
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Figure 69. NAND controller waveforms for read access
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T
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T
Hꢊ./%ꢑ$ꢋ
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Figure 70. NAND controller waveforms for write access
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T
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Vꢊ.7%ꢑ$ꢋ
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Figure 71. NAND controller waveforms for common memory read access
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T
T
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Figure 72. NAND controller waveforms for common memory write access
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T
T
T
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T
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(1)
Table 100. Switching characteristics for NAND Flash read cycles
Parameter Min Max
FMC_NOE low width 4THCLK − 0.5 4THCLK+0.5
Symbol
Unit
tw(N0E)
ns
ns
ns
tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high
9
-
-
0
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid
1. CL = 30 pF.
-
3THCLK − 0.5 ns
ns
3THCLK − 2
-
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(1)
Table 101. Switching characteristics for NAND Flash write cycles
Symbol
Parameter
FMC_NWE low width
Min
Max
Unit
tw(NWE)
tv(NWE-D)
4THCLK
0
4THCLK+1
ns
ns
ns
ns
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
-
-
-
th(NWE-D)
3THCLK − 1
5THCLK − 3
-
td(D-NWE)
td(ALE-NWE)
th(NWE-ALE)
1. CL = 30 pF.
3THCLK−0.5 ns
ns
3THCLK − 1
-
SDRAM waveforms and timings
Figure 73. SDRAM read access waveforms (CL = 1)
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$ATAN
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Electrical characteristics
Symbol
STM32F427xx STM32F429xx
(1)(2)
Table 102. SDRAM read timings
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2THCLK − 0.5
2THCLK+0.5
tsu(SDCLKH _Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2
0
-
-
-
1.5
0.5
-
td(SDCLKL- SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
0
-
0.5
-
0
-
0.5
-
0
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed by characterization results.
(1)(2)
Table 103. LPSDR SDRAM read timings
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
2THCLK − 0.5
2THCLK+0.5
tsu(SDCLKH_Data)
th(SDCLKH_Data)
td(SDCLKL_Add)
2.5
0
-
-
-
1
1
-
td(SDCLKL_SDNE)
th(SDCLKL_SDNE)
td(SDCLKL_SDNRAS
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
th(SDCLKL_SDNCAS)
-
ns
1
-
1
-
1
-
1
-
1
1. CL = 10 pF.
2. Guaranteed by characterization results.
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Figure 74. SDRAM write access waveforms
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Electrical characteristics
Symbol
STM32F427xx STM32F429xx
(1)(2)
Table 104. SDRAM write timings
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
NBL valid time
2THCLK − 0.5
2THCLK+0.5
td(SDCLKL _Data
)
-
0
-
3.5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
1.5
1
td(SDCLKL_SDNWE)
th(SDCLKL_SDNWE)
td(SDCLKL_ SDNE)
th(SDCLKL-_SDNE)
td(SDCLKL_SDNRAS)
th(SDCLKL_SDNRAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_SDNCAS)
td(SDCLKL_NBL)
-
0
-
-
0.5
-
ns
0
-
2
0
-
-
0.5
-
0
-
0.5
-
th(SDCLKL_NBL)
NBLoutput time
0
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK.
2. Guaranteed by characterization results.
(1)(2)
Table 105. LPSDR SDRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
NBL valid time
2THCLK − 0.5
2THCLK+0.5
td(SDCLKL _Data
)
-
2
5
-
th(SDCLKL _Data)
td(SDCLKL_Add)
-
2.8
2
td(SDCLKL-SDNWE)
th(SDCLKL-SDNWE)
td(SDCLKL- SDNE)
th(SDCLKL- SDNE)
td(SDCLKL-SDNRAS)
th(SDCLKL-SDNRAS)
td(SDCLKL-SDNCAS)
td(SDCLKL-SDNCAS)
td(SDCLKL_NBL)
-
1
-
-
1.5
-
ns
1
-
1.5
-
1.5
-
1.5
-
1.5
-
1.5
-
th(SDCLKL-NBL)
NBL output time
1.5
1. CL = 10 pF.
2. Guaranteed by characterization results.
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6.3.27
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 106 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
•
•
•
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Table 106. DCMI characteristics
Parameter
Frequency ratio DCMI_PIXCLK/f
Symbol
Min
Max
Unit
-
-
0.4
54
70
-
HCLK
DCMI_PIXCLK Pixel clock input
MHz
%
DPixel
tsu(DATA)
th(DATA)
Pixel clock input duty cycle
30
2
Data input setup time
Data input hold time
2.5
-
tsu(HSYNC)
tsu(VSYNC)
th(HSYNC)
th(VSYNC)
ns
DCMI_HSYNC/DCMI_VSYNC input setup time
DCMI_HSYNC/DCMI_VSYNC input hold time
0.5
1
-
-
Figure 75. DCMI timing diagram
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06ꢉꢃꢂꢀꢂ9ꢃ
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STM32F427xx STM32F429xx
6.3.28
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 107 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
•
•
•
•
LCD_CLK polarity: high
LCD_DE polarity : low
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
Table 107. LTDC characteristics
Symbol
Parameter
Min
Max
Unit
fCLK
DCLK
tw(CLKH)
LTDC clock output frequency
LTDC clock output duty cycle
-
42
55
MHz
%
45
Clock High time, low time
Data output valid time
Data output hold time
tw(CLK)/2 − 0.5 tw(CLK)/2+0.5
tw(CLKL)
tv(DATA)
-
3.5
-
th(DATA)
1.5
tv(HSYNC)
tv(VSYNC)
tv(DE)
ns
HSYNC/VSYNC/DE output valid
time
-
2.5
th(HSYNC)
HSYNC/VSYNC/DE output hold
time
th(VSYNC)
2
-
th(DE)
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Figure 76. LCD-TFT horizontal timing diagram
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STM32F427xx STM32F429xx
6.3.29
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, f
frequency and V
PCLK2
DD
supply voltage conditions summarized in Table 17, with the following configuration:
•
•
•
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Figure 78. SDIO high-speed mode
T
T
R
F
T
#
T
T
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T
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Figure 79. SD default mode
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T
T
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ꢊOUTPUTꢋ
AIꢃꢉꢅꢅꢅ
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Electrical characteristics
(1)(2)
Table 108. Dynamic characteristics: SD / MMC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
-
tW(CKL)
tW(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
0
-
48
8/3
-
MHz
-
-
9
fpp =48 MHz
fpp =48 MHz
8.5
8.3
ns
ns
ns
Clock high time
10
-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
tIH
Input setup time HS
Input hold time HS
fpp =48 MHz
fpp =48 MHz
3.5
0
-
-
-
-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
tOH
Output valid time HS
Output hold time HS
fpp =48 MHz
fpp =48 MHz
-
4.5
-
7
-
3
CMD, D inputs (referenced to CK) in SD default mode
1.5
0.5
-
-
-
-
tISUD
tIHD
Input setup time SD
Input hold time SD
fpp =24 MHz
fpp =24 MHz
ns
ns
CMD, D outputs (referenced to CK) in SD default mode
-
4.5
-
6.5
-
tOVD
tOHD
Output valid default time SD
Output hold default time SD
fpp =24 MHz
fpp =24 MHz
3.5
1. Guaranteed by characterization results.
2. VDD = 2.7 to 3.6 V.
6.3.30
RTC characteristics
Table 109. RTC characteristics
Conditions
Symbol
Parameter
Min
Max
Any read/write operation
from/to an RTC register
-
f
PCLK1/RTCCLK frequency ratio
4
-
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Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
7.1
LQFP100 package information
Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline
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#
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CCC
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E
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1. Drawing is not to scale.
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Package information
STM32F427xx STM32F429xx
Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
15.800
13.800
-
-
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
3.5°
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
-
16.200
14.200
-
0.6220
0.5433
-
0.6378
0.5591
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0.0°
-
7.0°
0.0°
7.0°
ccc
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint
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ꢃꢁꢂꢍ
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1. Dimensions are expressed in millimeters.
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Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 82. LQFP100 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
200/238
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Package information
7.2
WLCSP143 package information
Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package outline
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1. Drawing is not to scale.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters
inches(1)
Symbol
Min
Typ
0.555
0.175
0.380
0.025
0.250
4.521
5.547
0.400
4.000
4.800
0.2605
0.3735
-
Max
0.585
0.195
-
Min
Typ
0.0219
0.0069
0.0150
0.0010
0.0098
0.1780
0.2184
0.0157
0.1575
0.1890
0.0103
0.0147
-
Max
A
A1
A2
A3(2)
b(3)
D
0.525
0.0207
0.0230
0.155
-
-
-
-
-
-
-
-
-
0.220
0.280
4.556
5.582
-
0.0087
0.0110
0.1794
0.2198
-
4.486
0.1766
E
5.512
0.2170
e
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
e1
-
-
e2
-
-
F
-
-
G
-
-
aaa
bbb
ccc
ddd
eee
0.100
0.100
0.100
0.050
0.050
0.0039
0.0039
0.0039
0.0020
0.0020
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 84. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
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06ꢀꢁꢅꢇꢆ9ꢃ
202/238
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Package information
Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch)
Dimension
Recommended values
0.4
Pitch
260 µm max. (circular)
220 µm recommended
Dpad
Dsm
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed.
Device marking for WLCSP143
The following figure gives an example of topside marking orientation versus ball A 1
identifier location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 85. WLCSP143 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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231
Package information
STM32F427xx STM32F429xx
7.3
LQFP144 package information
Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline
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1. Drawing is not to scale.
204/238
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STM32F427xx STM32F429xx
Package information
Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Typ
Symbol
Min
Max
Min
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
21.800
19.800
-
-
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.874
0.7953
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
3.5°
0.8661
0.7874
0.689
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
-
22.200
20.200
-
0.8583
0.7795
-
0.8740
0.7953
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint
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1. Dimensions are expressed in millimeters.
206/238
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Package information
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 88. LQFP144 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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Package information
STM32F427xx STM32F429xx
7.4
LQFP176 package information
Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline
3EATING PLANE
#
ꢈꢂꢁꢆ MM
GAUGE PLANE
K
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1. Drawing is not to scale.
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
-
-
-
-
-
-
1.600
0.150
1.450
0.270
0.200
24.100
26.100
-
-
-
-
-
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.9488
1.0276
0.050
1.350
0.170
0.090
23.900
25.900
0.0020
0.0531
0.0067
0.0035
0.9409
1.0197
c
D
HD
208/238
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STM32F427xx STM32F429xx
Package information
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package
mechanical data (continued)
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
ZD
E
-
1.250
-
-
0.0492
-
23.900
-
24.100
0.9409
-
0.9488
HE
ZE
e
25.900
-
26.100
1.0197
-
1.0276
-
1.250
-
-
0.0492
-
-
0.500
-
0.750
-
-
0.0197
-
0.0295
-
L(2)
L1
k
0.450
-
0.0177
-
-
0°
-
1.000
-
0°
-
0.0394
-
-
7°
-
-
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
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Package information
STM32F427xx STM32F429xx
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended
footprint
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ꢃ4?&0?6ꢃ
1. Dimensions are expressed in millimeters.
210/238
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Package information
Device marking for LQFP176
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 91. LQFP176 marking (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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231
Package information
STM32F427xx STM32F429xx
7.5
LQFP208 package information
Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline
6($7,1*
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,'(17,),&$7,21
ꢀ
ꢆꢃ
H
6)@.&@7ꢁ
1. Drawing is not to scale.
212/238
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STM32F427xx STM32F429xx
Package information
Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.170
0.090
29.800
27.800
-
-
1.600
0.150
1.450
0.270
0.200
30.200
28.200
-
--
0.0020
0.0531
0.0067
0.0035
1.1732
1.0945
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
1.1890
1.1102
-
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
30.000
28.000
25.500
30.000
28.000
25.500
0.500
0.600
1.000
3.5°
1.1811
1.1024
1.0039
1.1811
1.1024
1.0039
0.0197
0.0236
0.0394
3.5°
D1
D3
E
29.800
27.800
-
30.200
28.200
-
1.1732
1.0945
-
1.1890
1.1102
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7.0°
0°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
recommended footprint
ꢃꢄꢁ
ꢀꢆꢈ
ꢄꢐꢆ
ꢀ
ꢀꢆꢇ
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8+B)3B9ꢃ
1. Dimensions are expressed in millimeters.
214/238
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STM32F427xx STM32F429xx
Package information
Device marking for LQFP208
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 94. LQFP208 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
7.6
UFBGA169 package information
Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package outline
=
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1. Drawing is not to scale.
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
A3
A4
b
0.460
0.050
0.400
-
0.530
0.080
0.450
0.130
0.320
0.280
7.000
6.000
7.000
6.000
0.500
0.600
0.110
0.500
-
0.0181
0.0020
0.0157
-
0.0209
0.0031
0.0177
0.0051
0.0126
0.0110
0.2756
0.2362
0.2756
0.2362
0.0197
0.0236
0.0043
0.0197
-
0.270
0.230
6.950
5.950
6.950
5.950
-
0.370
0.330
7.050
6.050
7.050
6.050
-
0.0106
0.0091
0.2736
0.2343
0.2736
0.2343
-
0.0146
0.0130
0.2776
0.2382
0.2776
0.2382
-
D
D1
E
E1
e
216/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Package information
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
F
0.450
0.500
0.550
0.100
0.150
0.050
0.0177
0.0197
0.0217
0.0039
0.0059
0.0020
ddd
eee
fff
-
-
-
-
-
-
-
-
-
-
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch
ball grid array recommended footprint
'SDG
'VP
06ꢀꢁꢅꢇꢆ9ꢃ
Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.5
0.27 mm
0.35 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Solder paste
0.27 mm aperture diameter.
Note:
Non-solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
Device marking for UFBGA169
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 97. UFBGA169 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
218/238
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Package information
7.7
UFBGA176+25 package information
Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch
ball grid array package outline
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1. Drawing is not to scale.
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
A3
A4
b
-
-
0.600
-
-
0.0236
-
-
0.110
-
-
0.0043
-
0.130
0.450
0.320
0.290
10.000
9.100
10.000
9.100
0.650
0.450
-
-
-
0.0051
0.0177
0.0126
0.0114
0.3937
0.3583
0.3937
0.3583
0.0256
0.0177
-
-
-
-
-
-
-
-
-
-
0.240
0.340
0.0094
0.0134
D
9.850
10.150
0.3878
0.3996
D1
E
-
-
-
-
9.850
10.150
0.3878
0.3996
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
Z
-
ddd
0.080
0.0031
DocID024030 Rev 9
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Package information
STM32F427xx STM32F429xx
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
eee
fff
-
-
-
-
0.150
0.050
-
-
-
-
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array package recommended footprint
'SDG
'VP
ꢁϬꢄϳͺ&Wͺsϭ
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
0.65 mm
0.300 mm
0.400 mm typ. (depends on the soldermask
registration tolerance)
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.300 mm
Between 0.100 mm and 0.125 mm
0.100 mm
220/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Package information
Device marking for UFBGA176+25
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 100. UFBGA176+25 marking example (package top view)
3URGXFWꢊLGHQWLILFDWLRQꢌꢀꢍ
5HYLVLRQꢊFRGH
5
670ꢀꢁ)ꢂꢁꢃ
,,+ꢄ8
'DWHꢊFRGHꢊ ꢊ\HDUꢊꢓꢊZHHN
< ::
%DOOꢊꢀꢊ
LQGHQWLILHU
06ꢉꢂꢈꢈꢃ9ꢃ
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024030 Rev 9
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231
Package information
STM32F427xx STM32F429xx
7.8
TFBGA216 package information
Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch
ball grid array package outline
=
6HDWLQJꢊSODQH
GGG =
$ꢃ
$ꢀ
$
'ꢀ
;
$ꢀꢊEDOOꢊ
$ꢀꢊEDOOꢊ
'
LGHQWLILHU LQGH[ꢊDUHD
H
)
$
*
(ꢀ
(
H
<
5
ꢀꢆ
ꢀ
EꢊꢌꢃꢀꢇꢊEDOOVꢍ
HHH 0 = < ;
III 0 =
%27720ꢊ9,(:
723ꢊ9,(:
$ꢄ/ꢃB0(B9ꢉ
1. Drawing is not to scale.
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.100
-
-
0.0433
0.150
-
-
0.0059
-
-
-
0.760
0.400
13.000
11.200
13.000
11.200
0.800
0.900
-
-
-
0.0299
0.0157
0.5118
0.4409
0.5118
0.4409
0.0315
0.0354
-
-
0.350
0.450
0.0138
0.0177
D
12.850
13.150
0.5118
0.5177
D1
E
-
-
-
-
12.850
13.150
0.5118
0.5177
E1
e
-
-
-
-
-
-
-
-
-
-
-
-
-
F
-
ddd
0.100
0.0039
222/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Package information
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
eee
fff
-
-
-
-
0.150
0.080
-
-
-
-
0.0059
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Device marking for TFBGA176
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.
Figure 102. TFBGA176 marking example (package top view)
3URGXFWꢊLGHQWLILFDWLRQꢌꢀꢍ
670ꢀꢁ)ꢂꢁꢃ
5HYLVLRQꢊFRGH
1,+ꢄ
5
'DWHꢊFRGHꢊ ꢊ\HDUꢊꢓꢊZHHN
%DOOꢊ$ꢀꢊLGHQWLILHU
< ::
06ꢉꢀꢁꢀꢈ9ꢉ
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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231
Package information
STM32F427xx STM32F429xx
7.9
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max x Θ )
J
A
D
JA
Where:
•
•
•
•
T max is the maximum ambient temperature in ° C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 121. Package thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
43
31.2
40
Thermal resistance junction-ambient
WLCSP143
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
38
Θ
°C/W
JA
Thermal resistance junction-ambient
LQFP208 - 28 × 28 mm / 0.5 mm pitch
19
Thermal resistance junction-ambient
UFBGA169 - 7 × 7mm / 0.5 mm pitch
52
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.5 mm pitch
39
Thermal resistance junction-ambient
TFBGA216 - 13 × 13 mm / 0.8 mm pitch
29
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
224/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Part numbering
8
Part numbering
Table 122. Ordering information scheme
STM32
Example:
F
429 V
I
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
427= STM32F427xx, USB OTG FS/HS, camera interface,
Ethernet
429= STM32F429xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT
Pin count
V = 100 pins
Z = 143 and 144 pins
A = 169 pins
I = 176 pins
B = 208 pins
N = 216 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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231
Recommendations when using internal reset OFF
STM32F427xx STM32F429xx
Appendix A
Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
•
•
•
•
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
V
functionality is no more available and VBAT pin should be connected to V
.
BAT
DD
The over-drive mode is not supported.
A.1
Operating conditions
Table 123. Limitations depending on the operating power supply range
Maximum
Flash
Operating
power
supply
range
memory
access
frequency
Maximum Flash
memory access
frequency with
PossibleFlash
memory
operations
ADC
operation
I/O operation
with no wait wait states (1)(2)
states
(fFlashmax
)
Conversion
time up to
1.2 Msps
168 MHz with 8
wait states and
over-drive OFF
8-bit erase and
program
operations only
VDD =1.7 to
2.1 V(3)
– No I/O
compensation
20 MHz(4)
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does
not impact the execution speed from Flash memory since the ART accelerator allows to achieve a
performance equivalent to 0 wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.17.1: Internal reset ON).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and
power.
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STM32F427xx STM32F429xx
Application block diagrams
Appendix B
Application block diagrams
B.1
USB OTG full speed (FS) interface solutions
Figure 103. USB controller configured as peripheral-only and used
in Full speed mode
6$$
ꢆ6 TO 6$$
6OLATGE REGULATOR
ꢊꢃꢋ
34-ꢂꢅ&ꢁXX
6"53
$-
$0
0!ꢃꢃꢀꢀ0"ꢃꢉ
0!ꢃꢁꢀ0"ꢃꢆ
/3#?).
6
33
/3#?/54
-3ꢃꢒꢈꢈꢈ6ꢆ
1. External voltage regulator only needed when building a VBUS powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Figure 104. USB controller configured as host-only and used in full speed mode
6$$
%.
'0)/
#URRENT LIMITER
ꢆ 6 0WR
ꢊꢃꢋ
POWER SWITCH
/VERCURRENT
'0)/ꢓ)21
34-ꢂꢅ&ꢁXX
6"53
$-
0!ꢃꢃꢀꢀ0"ꢃꢉ
/3#?).
$0
0!ꢃꢁꢀ0"ꢃꢆ
633
/3#?/54
-3ꢃꢒꢈꢈꢃ6ꢉ
1. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
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231
Application block diagrams
STM32F427xx STM32F429xx
Figure 105. USB controller configured in dual mode and used in full speed mode
6$$
ꢆ 6 TO 6$$
VOLTAGE REGULATOR
ꢊꢃꢋ
6$$
%.
'0)/
ꢆ 6 0WR
#URRENT LIMITER
POWER SWITCH
ꢊꢁꢋ
/VERCURRENT
'0)/ꢓ)21
34-ꢂꢅ&ꢁXX
6"53
0!ꢒꢀ0"ꢃꢍ
$-
0!ꢃꢃꢀ0"ꢃꢉ
/3#?).
$0
ꢊꢍꢋ
0!ꢃꢁꢀ0"ꢃꢆ
0!ꢃꢈꢀ0"ꢃꢁ
)$
/3#?/54
6
33
-3ꢃꢒꢈꢈꢁ6ꢍ
1. External voltage regulator only needed when building a VBUS powered device.
2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
228/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Application block diagrams
B.2
USB OTG high speed (HS) interface solutions
Figure 106. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode
34-ꢂꢅ&ꢁXX
$0
&3 0(9
NOT CONNECTED
$-
53" (3
/4' #TRL
$0
5,0)?#,+
$-
5,0)?$;ꢎꢇꢈ=
ꢊꢁꢋ
)$
53"
5,0)?$)2
5,0)?340
CONNECTOR
6"53
633
5,0)
5,0)?.84
(IGH SPEED
/4' 0(9
84ꢃ
0,,
ꢁꢉ OR ꢁꢄ -(Z 84ꢊꢃꢋ
-#/ꢃ OR -#/ꢁ
8)
-3ꢃꢒꢈꢈꢆ6ꢁ
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F42x
with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible
connection.
2. The ID pin is required in dual role only.
DocID024030 Rev 9
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231
Application block diagrams
STM32F427xx STM32F429xx
B.3
Ethernet interface solutions
Figure 107. MII mode using a 25 MHz crystal
34-ꢍꢁ
-))?48?#,+
-))?48?%.
-))?48$;ꢍꢇꢈ=
-))?#23
-#5
%THERNET
-!# ꢃꢈꢀꢃꢈꢈ
%THERNET
0(9 ꢃꢈꢀꢃꢈꢈ
-))
ꢏ ꢃꢆ PINS
-))?#/,
ꢊꢃꢋ
(#,+
-))?28?#,+
-))?28$;ꢍꢇꢈ=
-))?28?$6
-))?28?%2
-)) ꢓ -$#
ꢏ ꢃꢎ PINS
)%%%ꢃꢆꢅꢅ 040
4IMER
INPUT
TRIGGER
4IMESTAMP
COMPARATOR
-$)/
-$#
4)-ꢁ
ꢊꢁꢋ
003?/54
(#,+
-#/ꢃꢀ-#/ꢁ
0,,
84!,
ꢁꢆ -(Z
/3#
0(9?#,+ ꢁꢆ -(Z
84ꢃ
-3ꢃꢒꢒꢄꢅ6ꢃ
1. fHCLK must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP optional signal.
Figure 108. RMII with a 50 MHz oscillator
34-ꢍꢁ
%THERNET
0(9 ꢃꢈꢀꢃꢈꢈ
-#5
2-))?48?%.
%THERNET
2-))?48$;ꢃꢇꢈ=
2-))?28$;ꢃꢇꢈ=
2-))?#28?$6
2-))?2%&?#,+
-!# ꢃꢈꢀꢃꢈꢈ
2-))
ꢏ ꢎ PINS
ꢊꢃꢋ
(#,+
2-)) ꢓ -$#
ꢏ ꢒ PINS
)%%%ꢃꢆꢅꢅ 040
-$)/
-$#
4IMER
INPUT
TRIGGER
4IMESTAMP
COMPARATOR
4)-ꢁ
ꢀꢁ OR ꢀꢁꢈ
ꢁꢂꢆ OR ꢁꢆ -(Z
ꢆꢈ -(Z
SYNCHRONOUS
(#,+
0,,
/3#
ꢆꢈ -(Z
0(9?#,+ ꢆꢈ -(Z 84ꢃ
ꢆꢈ -(Z
-3ꢃꢒꢒꢄꢒ6ꢃ
1. fHCLK must be greater than 25 MHz.
230/238
DocID024030 Rev 9
STM32F427xx STM32F429xx
Application block diagrams
Figure 109. RMII with a 25 MHz crystal and PHY with PLL
34-ꢍꢁ&
%THERNET
0(9 ꢃꢈꢀꢃꢈꢈ
-#5
2-))?48?%.
%THERNET
2-))?48$;ꢃꢇꢈ=
2-))?28$;ꢃꢇꢈ=
2-))?#28?$6
2-))?2%&?#,+
-!# ꢃꢈꢀꢃꢈꢈ
2-))
ꢊꢃꢋ
(#,+
ꢏ ꢎ PINS
2%&?#,+
2-)) ꢓ -$#
ꢏ ꢒ PINS
)%%%ꢃꢆꢅꢅ 040
-$)/
-$#
4IMER
INPUT
TRIGGER
4IMESTAMP
COMPARATOR
4)-ꢁ
ꢀꢁ OR ꢀꢁꢈ
SYNCHRONOUS
ꢁꢂꢆ OR ꢁꢆ -(Z
ꢆꢈ -(Z
0,,
84ꢃ
(#,+
-#/ꢃꢀ-#/ꢁ
84!,
ꢁꢆ -(Z
0,,
/3#
0(9?#,+ ꢁꢆ -(Z
-3ꢃꢒꢒꢎꢈ6ꢃ
1. fHCLK must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.
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Revision history
STM32F427xx STM32F429xx
9
Revision history
Table 124. Document revision history
Changes
Date
Revision
19-Mar-2013
1
Initial release.
Added STM32F429xx part numbers and related informations.
STM32F427xx part numbers:
Replaced FSMC by FMC added Chrom-ART Accelerator and SAI
interface.
Increased core, timer, GPIOs, SPI maximum frequencies
Updated Figure 8.Updated Figure 9.
Removed note in Section ·: Standby mode.
Updated Figure 18.
Updated Table 10: STM32F427xx and STM32F429xx pin and ball
definitions and Table 12: STM32F427xx and STM32F429xx alternate
function mapping..
Modified Figure 19: Memory map.
Updated Table 17: General operating conditions, Table 18: Limitations
depending on the operating power supply range. Removed note 1 in
Table 22: reset and power control block characteristics. Added
Table 23: Over-drive switching characteristics.
Updated Section : Typical and maximum current consumption,
Table 34: Switching output I/O current consumption, Table 35:
Peripheral current consumption and Section : On-chip peripheral
current consumption.
10-Sep-2013
2
Updated Table 36: Low-power mode wakeup timings.
Modified Section : High-speed external user clock generated from an
external source, Section : Low-speed external user clock generated
from an external source, and Section 6.3.10: Internal clock source
characteristics.
Updated Table 43: Main PLL characteristics and Table 45: PLLISAI
(audio and LCD-TFT PLL) characteristics.
Updated Table 52: EMI characteristics.
Updated Table 57: Output voltage characteristics and Table 58: I/O AC
characteristics.
Updated Table 60: TIMx characteristics, Table 61: I2C characteristics,
Table 62: SPI dynamic characteristics, Section : SAI characteristics.
Updated Table 102: SDRAM read timings and Table 104: SDRAM write
timings.
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DocID024030 Rev 9
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Revision history
Table 124. Document revision history
Revision Changes
Date
Added STM32F429xE part numbers featuring 512 Mbytes of Flash
memory and UFBGA169 package.
Added LPSDR SDRAM.
Changed INTN into INTR in Figure 4: STM32F427xx and
STM32F429xx block diagram.
Added note 4 in Table 2: STM32F427xx and STM32F429xx features
and peripheral counts.
Updated Section 3.15: Boot modes.
Updated for PA4 and PA5 in Table 10: STM32F427xx and
STM32F429xx pin and ball definitions.
Added VIN for BOOT0 pins in Table 14: Voltage characteristics.
Updated Note 6., added Note 1.,and updated maximum VIN for B pins
in Table 17: General operating conditions.
Updated maximum Flash memory access frequency with wait states
for VDD =1.8 to 2.1 V in Table 18: Limitations depending on the
operating power supply range.
Updated Table 24: Typical and maximum current consumption in Run
mode, code with data processing running from Flash memory (ART
accelerator enabled except prefetch) or RAM and Table 25: Typical
and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator disabled).
24-Jan-2014
3
Updated Table 30: Typical current consumption in Run mode, code
with data processing running from Flash memory or RAM, regulator
ON (ART accelerator enabled except prefetch), VDD=1.7 V, Table 31:
Typical current consumption in Run mode, code with data processing
running from Flash memory, regulator OFF (ART accelerator enabled
except prefetch), and Table 32: Typical current consumption in Sleep
mode, regulator ON, VDD=1.7 V.
Updated Table 57: Output voltage characteristics.
Updated Table 58: I/O AC characteristics. Added Figure 35.
Updated th(SDA), tr(SDA) and tr(SCL) and added tSP in Table 61: I2C
characteristics.
Updated fSCK in Table 62: SPI dynamic characteristics.
Updated Table 70: Dynamic characteristics: USB ULPI.
Updated Section 6.3.26: FMC characteristics conditions. Updated
Figure 73: SDRAM read access waveforms (CL = 1) and Figure 74:
SDRAM write access waveforms. Added Table 103: LPSDR SDRAM
read timings and Table 105: LPSDR SDRAM write timings. Updated
Table 102: SDRAM read timings and Table 104: SDRAM write timings
and added note 2.Table 108: Dynamic characteristics: SD / MMC
characteristics.
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237
Revision history
STM32F427xx STM32F429xx
Table 124. Document revision history
Date
Revision
Changes
In the whole document, minimum supply voltage changed to 1.7 V
when external power supply supervisor is used.
Added DCMI_VSYNC alternate function on PG9 and updated note 6.
in Table 10: STM32F427xx and STM32F429xx pin and ball definitions
and Table 12: STM32F427xx and STM32F429xx alternate function
mapping. Added note 2.belowFigure 16: STM32F42x UFBGA169
ballout.
Changed SVGA (800x600) into XGA1024x768) on cover page and in
Section 3.10: LCD-TFT controller (available only on STM32F429xx).
Updated Section 3.18.2: Regulator OFF.
Updated signal corresponding to pin L5 in Figure 12: STM32F42x
WLCSP143 ballout.
Added ACCHSE in Table 39: HSE 4-26 MHz oscillator characteristics
and ACCLSE in Table 40: LSE oscillator characteristics (fLSE = 32.768
kHz).
24-Apr-2014
4
Updated Table 53: ESD absolute maximum ratings.
Updated VIH in Table 56: I/O static characteristics. Added condition
VDD>1.7 V in Table 58: I/O AC characteristics.
Updated conditions in Table 62: SPI dynamic characteristics.
Added ZDRV in Table 67: USB OTG full speed electrical characteristics
Removed note 3 in Table 80: Temperature sensor characteristics.
Added Figure 82: LQFP100 marking example (package top view),
Figure 85: WLCSP143 marking example (package top view),
Figure 88: LQFP144 marking example (package top view), Figure 91:
LQFP176 marking (package top view), Figure 94: LQFP208 marking
example (package top view), Figure 97: UFBGA169 marking example
(package top view) and Figure 100: UFBGA176+25 marking example
(package top view).
Added Appendix A: Recommendations when using internal reset OFF.
Removed Internal reset OFF hardware connection appendix.
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Revision history
Table 124. Document revision history
Revision Changes
Date
Update SPI/IS2 in Table 2: STM32F427xx and STM32F429xx features
and peripheral counts.
Updated LQFP208 in Table 4: Regulator ON/OFF and internal reset
ON/OFF availability.
Updated Figure 19: Memory map.
Changed PLS[2:0]=101 (falling edge) maximum value in Table 22:
reset and power control block characteristics.
Updated current consumption with all peripherals disabled in Table 24:
Typical and maximum current consumption in Run mode, code with
data processing running from Flash memory (ART accelerator
enabled except prefetch) or RAM. Updated note 1. in Table 28: Typical
and maximum current consumptions in Standby mode.
Updated tWUSTOP in Table 36: Low-power mode wakeup timings.
Updated ESD standards and Table 53: ESD absolute maximum
ratings.
Updated Table 56: I/O static characteristics.
Section : I2C interface characteristics: updated section introduction,
removed Table I2C characteristics, Figure I2C bus AC waveforms and
measurement circuit and Table SCL frequency; added Table 61: I2C
analog filter characteristics.
Updated measurement conditions in Table 62: SPI dynamic
characteristics.
Updated Figure 51: Typical connection diagram using the ADC.
Updated Section : Device marking for LQFP100.
19-Feb-2015
5
Updated Figure 83: WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm
pitch wafer level chip scale package outline and Table 111: WLCSP143
- 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data; added Figure 84: WLCSP143 - 143-ball,
4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended
footprint and Table 112: WLCSP143 recommended PCB design rules
(0.4 mm pitch). Updated Figure 85: WLCSP143 marking example
(package top view) and related note. Updated Section : Device
marking for WLCSP143.
Updated Section : Device marking for LQFP144.
Updated Section : Device marking for LQFP176.
Updated Figure 92: LQFP208 - 208-pin, 28 x 28 mm low-profile quad
flat package outline; Updated Section : Device marking for LQFP208.
Modified UFBGA169 pitch, updated Figure 95: UFBGA169 - 169-ball 7
x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline
and Table 116: UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra
fine pitch ball grid array package mechanical data; updated Section :
Device marking for LQFP208.
updated Section : Device marking for UFBGA169, Section : Device
marking for UFBGA176+25 and Section : Device marking for
TFBGA176.
Updated Z pin count in Table 122: Ordering information scheme.
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Revision history
STM32F427xx STM32F429xx
Table 124. Document revision history
Date
Revision
Changes
Updated notes related to the minimum and maximum values
guaranteed by design, characterization or test in production.
Updated IDD_STOP_UDM in Table 27: Typical and maximum current
consumptions in Stop mode.
Removed note related to tests in production in Table 24: Typical and
maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled
except prefetch) or RAM and Table 26: Typical and maximum current
consumption in Sleep mode.
Updated Table 41: HSI oscillator characteristics. Figure 31 renamed
ACCHSI accuracy versus temperature and updated.
Updated Figure 38: SPI timing diagram - slave mode and CPHA = 0.
Updated Section : Ethernet characteristics.
Updated Table 43: Main PLL characteristics, Table 44: PLLI2S (audio
PLL) characteristics and Table 45: PLLISAI (audio and LCD-TFT PLL)
characteristics.
17-Sep-2015
6
Removed note 1 in Table 75: ADC static accuracy at fADC = 18 MHz,
Table 76: ADC static accuracy at fADC = 30 MHz and Table 77: ADC
static accuracy at fADC = 36 MHz.
Updated td(SDCLKL _Data) and th(SDCLKL _Data) in Table 104: SDRAM
write timings.
Added Figure 96: UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra
fine pitch ball grid array recommended footprint and Table 117:
UFBGA169 recommended PCB design rules (0.5 mm pitch BGA).
Added Figure 99: UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package recommended footprint and
Table 119: UFBGA176+25 recommended PCB design rules (0.65 mm
pitch BGA).
Updated |VSSX −VSS| in Table 14: Voltage characteristics to add VREF-
.
Updated td(TXEN) and td(TXD) minimum value in Table 72: Dynamics
characteristics: Ethernet MAC signals for RMII and Table 73: Dynamics
characteristics: Ethernet MAC signals for MII.
Added VREF- in Table 74: ADC characteristics.
Added A1 minimum and maximum values in Table 111: WLCSP143 -
143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data. Updated Figure 86: LQFP144-144-pin, 20 x
20 mm low-profile quad flat package outline.
30-Nov-2015
7
Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch
ultra thin fine pitch ball grid array package outline and Table 118:
UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package mechanical data. Updated Figure 101: TFBGA216 -
216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package outline and Table 120: TFBGA216 - 216 ball 13 × 13 mm
0.8 mm pitch thin fine pitch ball grid array package mechanical data.
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Revision history
Table 124. Document revision history
Revision Changes
Date
Updated Figure 22: Power supply scheme.
21-Jan-2016
8
Added td(TXD) values corresponding to 1.71 V < VDD < 3.6 V in
Table 72: Dynamics characteristics: Ethernet MAC signals for RMII.
Updated Figure 1: Compatible board design
STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package.
Added mission profile compliance with JEDEC JESD47 in
Section 6.2: Absolute maximum ratings.
Changed Figure 31 HSI deviation versus temperature to ACCHSI
versus temperature.
Updated RLOAD in Table 85: DAC characteristics.
Added note 2. related to the position of the 0.1 µF capacitor below
Figure 37: Recommended NRST pin protection.
Updated Figure 40: SPI timing diagram - master mode.
18-Jul-2016
9
Added reference to optional marking or inset/upset marks in all
package device marking sections. Updated Figure 85: WLCSP143
marking example (package top view), Figure 88: LQFP144
marking example (package top view), Figure 91: LQFP176
marking (package top view), Figure 94: LQFP208 marking
example (package top view).
Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch
ultra thin fine pitch ball grid array package outline and Table 118:
UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package mechanical data.
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STM32F427xx STM32F429xx
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