STM32L151RD [STMICROELECTRONICS]
Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash;型号: | STM32L151RD |
厂家: | ST |
描述: | Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash |
文件: | 总140页 (文件大小:1476K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM32L151xD STM32L152xD
Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash,
48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F
Datasheet − production data
Features
■ Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40°C to 85°C/105°C Temperature range
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm) UFBGA132
LQFP64 (10 × 10 mm)
WLCSP64
(0.400 mm pitch)
(7 × 7 mm)
– 0.35 µA Standby mode (3 wakeup pins)
– 1.3 µA Standby mode + RTC
– 0.65 µA Stop mode (16 wakeup lines)
– 1.5 µA Stop mode + RTC
– 11 µA Low-power Run mode
– 238 µA/MHz Run mode
■ Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
■ Memories
– 384 KB Flash with ECC (with 2 bank of
192 KB enabling Rww capability)
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
– 48 KB RAM
– 12 KB of true EEPROM with ECC
– 128 Byte Backup Register
™
■ Core: ARM 32-bit Cortex -M3 CPU
– Memory interface controller supporting
SRAM, PSRAM and NOR Flash
– From 32 kHz up to 32 MHz max
– 33.3 DMIPS peak (Dhrystone 2.1)
– Memory protection unit
■ LCD driver for up to 8x40 segments (contrast
adjustment, blinking mode, step-up converter)
■ Up to 34 capacitive sensing channels
■ CRC calculation unit, 96-bit unique ID
■ Rich analog peripherals (down to 1.8V)
– 3x Operational Amplifier
■ Reset and supply management
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– Low power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– 2x ultra-low-power-comparators
– Ultralow power POR/PDR
– Programmable voltage detector (PVD)
(window mode and wake up capability)
■ DMA controller 12x channels
■ 12x peripherals communication interface
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USART
■ Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz factory-
trimmed RC (+/- 1%)
– Internal low power 37 kHz RC
– Internal multispeed low power 65 kHz to
4.2 MHz
– 3x SPI 16 Mbits/s (2x SPI with I2S)
– 2x I2C (SMBus/PMBus)
– 1x SDIO interface
■ 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timer, 2x
watchdog timers (independent and window)
– PLL for CPU clock and USB (48 MHz)
■ Pre-programmed bootloader
Table 1.
Device summary
Part number
– USB and USART supported
Reference
■ Serial wire debug, JTAG and trace
STM32L151QD STM32L151RD
STM32L151VD STM32L151ZD
STM32L151xx
STM32L152xx
STM32L152QD STM32L152RD
STM32L152VD STM32L152ZD
February 2013
Doc ID 022027 Rev 6
1/140
This is information on a product in full production.
www.st.com
1
Contents
STM32L151xD STM32L152xD
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1
2.2.2
2.2.3
2.2.4
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
3.3
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ARM® Cortex™-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1
3.3.2
3.3.3
3.3.4
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . . 24
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.12 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.15 System configuration controller and routing interface . . . . . . . . . . . . . . . 27
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3.16 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 30
3.18.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.5 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.6 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 31
3.20 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
5
6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1
6.3.2
6.3.3
6.3.4
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics . . . . . . . . . . . 56
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Contents
STM32L151xD STM32L152xD
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 95
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.17 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.18 SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.23 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.24 LCD controller (STM32L152xD only) . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.1
7.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8
9
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ultra-low-power STM32L15xxD device features and peripheral counts. . . . . . . . . . . . . . . 11
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32L15xxD pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Current consumption in Run mode, code with data processing running from Flash. . . . . . 60
Current consumption in Run mode, code with data processing running from RAM . . . . . . 61
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 65
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 66
Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LSE
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 82
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 84
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 85
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 92
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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List of tables
STM32L151xD STM32L152xD
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SCL frequency (f
= 32 MHz, V = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PCLK1
DD
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SDIO characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
R
max for f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
AIN
ADC
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 126
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 128
LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 130
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array mechanical data. . . . 131
WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 133
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
STM32L15xxD ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Ultra-low-power STM32L15xxD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32L15xZD LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32L15xQD UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L15xVD LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L15xRD LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L15xRD WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 13. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 17. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 83
Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 84
Figure 19. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 20. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 21. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 22. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 23. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 24. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 25. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2
Figure 27. I C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
(1)
Figure 29. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
(1)
Figure 30. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2
(1)
Figure 31. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2
(1)
Figure 32. I S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 33. SDIO timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 34. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 35. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 36. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 37. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 38. Power supply and reference decoupling (V
Figure 39. Power supply and reference decoupling (V
not connected to V
). . . . . . . . . . . . . 116
). . . . . . . . . . . . . . . . 116
REF+
DDA
connected to V
REF+
DDA
Figure 40. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 41. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 125
Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 43. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 127
Figure 44. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 45. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 129
Figure 46. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 47. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . . 131
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List of figures
STM32L151xD STM32L152xD
Figure 48. WLCSP64, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 132
Figure 49. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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Introduction
1
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xD and STM32L152xD ultra-low-power ARM Cortex™-based
microcontrollers product line. STM32L15xD devices are microcontrollers with a Flash
memory density of 384 Kbytes.
The ultra-low-power STM32L15xxD family includes devices in 5 different package types:
from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the ultra-low-power STM32L15xxD microcontroller family suitable for a
wide range of applications:
●
●
●
●
●
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, wired and wireless sensors, Video intercom
Utility metering
This STM32L151xD and STM32L152xD datasheet should be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The document "Getting started with
STM32L1xxx hardware development" AN3216 gives a hardware implementation overview.
Both documents are available from the STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g.
Figure 1 shows the general block diagram of the device family.
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Description
STM32L151xD STM32L152xD
2
Description
The ultra-low-power STM32L15xxD incorporates the connectivity power of the universal
serial bus (USB) with the high-performance ARM Cortex™-M3 32-bit RISC core operating
at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories
(Flash memory up to 384 Kbytes and RAM up to 48 Kbytes), a flexible static memory
controller (FSMC) interface (for devices with packages of 100 pins and more) and an
extensive range of enhanced I/Os and peripherals connected to two APB buses.
The STM32L15xxD devices offer three operational amplifiers, one 12-bit ADC, two DACs,
two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16-
bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L15xxD devices contain standard and advanced communication
interfaces: up to two I2Cs, three SPIs, two I2S, one SDIO, three USARTs, two UARTs and a
USB. The STM32L15xxD devices offer up to 34 capacitive sensing channels to simply add
touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to
drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.
The ultra-low-power STM32L15xxD operates from a 1.8 to 3.6 V power supply (down to
1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.
It is available in the -40 to +85 °C temperature range, extended to 105°C in low power
dissipation state. A comprehensive set of power-saving modes allows the design of low-
power applications.
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Description
2.1
Device overview
Table 2.
Ultra-low-power STM32L15xxD device features and peripheral counts
Peripheral
STM32L15xRD STM32L15xVD STM32L15xQD STM32L15xZD
Flash (Kbytes)
Data EEPROM (Kbytes)
RAM (Kbytes)
FSMC
384
12
48
No
multiplexed only
Yes
32 bit
1
6
2
Timers
General-purpose
Basic
SPI/(I2S)
I2C
3/(2)
2
5
1
1
Communication
interfaces
USART
USB
SDIO
GPIOs
51
83
109
115
Operation amplifiers
3
12-bit synchronized ADC
Number of channels
1
21
1
25
1
40
1
40
12-bit DAC
Number of channels
2
2
LCD (1)
1
1
COM x SEG
4x32 or 8x28
4x44 or 8x40
Comparators
2
Capacitive sensing channels
Max. CPU frequency
23
33
34
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating voltage
Ambient temperature: –40 to +85 °C
Junction temperature: –40 to +105 °C
Operating temperatures
LQFP64,
WLCSP64
Packages
LQFP100
UFBGA132
LQFP144
1. STM32L152xx devices only.
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Description
STM32L151xD STM32L152xD
2.2
Ultra-low-power device continuum
The ultra-low-power STM32L15xxD, STM32L162xD, STM32L15xxC and STM32L162xC are
fully pin-to-pin and software compatible. Besides the full compatibility within the family, the
devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also
includes STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a
continuum of performance, peripherals, system architecture and features.
They are all based on STMicroelectronics ultralow leakage process.
Note:
The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
devices. Please refer to the STM32F and STM8L documentation for more information on
these devices.
2.2.1
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
2.2.3
Shared peripherals
STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy
migration from one family to another:
●
Analog peripherals: ADC, DAC and comparators
●
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L15xxx and STM32L15xxx families
use a common architecture:
●
Same power supply range from 1.65 V to 3.6 V
●
Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
●
●
●
Fast startup strategy from low power modes
Flexible system clock
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4
Features
ST ultra-low-power continuum also lies in feature compatibility:
●
More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 384 Kbytes
●
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Functional overview
3
Functional overview
Figure 1.
Ultra-low-power STM32L15xxD block diagram
TRACECK, TRACED0, TRACED1, TRACED2, TRACED4
@VDD 33
P OWE R
VDDC OR E
J TA G & S W
Trace C ontroller E TM
EE P R OM
pbus
Ibus
VDD 33=1.65V to 3.6V
VS S
NJ TR S T
VOL T. R E G .
J TDI
J TCK /S WCLK
J TMS /SWDAT
J TDO
M3 C P U
: 32 MHz
64 bit
384 KB P R OG RA M
12KB DA TA
Vref
f
Dbu s
max
Supply monitoring
8KB B OO T
as A F
DUA L BANK - RW W
MP U
NRST
S ys tem
P DR
S RA M 48K
P DR
NVIC
G P D MA 7 c hannels
A (25:0)
@VDD 33
D(15:0)
C L K
OS C_IN
OS C_OUT
X TA L O S C
1-24 MHz
@VDDA
OE N
WE N
WA IT N
E BAR (2:0)
L BA R
G P D MA2 5 c hannels
AH B P C L K
PLL &
Clock
Mgmt
A P B P C L K
HC L K
F C L K
FS MC
WD G 32K
B L N(1:0)
S tandby
interface
Supply
monitoring
RC HS I
R C MS I
VDD A /
VS S A
B OR / B g ap
B OR
Int
OS C 32_ IN
OS C 32_ OUT
X TA L 32kHz
P VD
RC L S I
RTC_OUT
TAMPER
Cap. sens
G P C omp
B ack up
R TC V2
AW U
reg 128
C OMP x_ INx
B ackup interfac e
@VDD 33
P U / P D
@VDDA
P A [15:0]
P B [15:0]
P C [15:0]
P D[15:0]
G P IO P OR T A
G P IO P OR T B
VL C D =2.5V to 3.6V
L CD B oos ter
4 C hannels
4 C hannels
TIME R 2
TIME R 3
TIME R 4
G P IO P OR TC
G P IO P OR T D
4 C hannels
4 C hannels
P E [15:0]
P H[2:0]
G P IO P OR T E
G P IO P OR T H
G P IO P OR T F
G P IO P OR T G
TIME R 5 (32bits )
US A R T2
R X ,TX , C TS , R TS ,
S martC ard as A F
P F [15:0]
P G [15:0]
R X ,TX , C TS , R TS ,
S martC ard as A F
US A R T3
R X ,TX as A F
US A R T4
E X T.IT
WKU P
115 A F
AHB/APB2
AHB/APB1
R X ,TX as A F
US A R T5
MOS I,MIS O,
S P I1
MO S I,MIS O, S CK ,NS S ,WS ,C K
MCK ,S D as A F
S CK ,NS S as A F
SPI2/I2S
SPI3/I2S
R X ,TX , C TS , R TS ,
S martC ard as A F
MOS I,MIS O, S CK ,NS S ,WS ,C K
MCK ,S D as A F
US AR T1
@VDDA
US B S RA M 512 B
WinWA TCH DOG
40 AF
S C L ,S DA
as A F
*
I2C 1
I2C 2
VDDR E F _AD C
12bit AD C
IF
*
VS S R E F _AD C
S C L ,S DA ,S MB us ,P MB us
as A F
Temp sensor
TIME R 6
TIME R 7
US B _ DP
US B _ DM
D(7:0)
C MD
US B 2. 0 F S devic e
Cap. sensing
S DIO
C K
P x
General purpose
timers
S E Gx
C OMx
L CD 8x 40
@VDDA
OP A MP 1
2 C hann els
1 C hannel
TIME R 9
TIME R 10
TIME R 11
OP A MP 2
OP A MP 3
DAC_OUT1 as AF
DAC_OUT2 as AF
12bit DAC 1
IF
1 C hannel
12bit DAC 2
VINP
VINP
VINP
VINM
VOUT
VINM VINM
VOUT VOUT
MS18272V4
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Functional overview
STM32L151xD STM32L152xD
1. Legend:
AF: alternate function
ADC: analog-to-digital converter
BOR: brown out reset
DMA: direct memory access
DAC: digital-to-analog converter
I²C: inter-integrated circuit multimaster interface
3.1
Low power modes
The ultra-low-power STM32L15xxD supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the internal low-drop regulator that supplies the
logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
●
●
●
Range 1 (V range limited to 2.0V-3.6V), with the CPU running at up to 32 MHz
DD
Range 2 (full V range), with a maximum CPU frequency of 16 MHz
DD
Range 3 (full V range), with a maximum CPU frequency limited to 4 MHz (generated
DD
only with the multispeed internal RC oscillator clock source)
Seven low power modes are provided to achieve the best compromise between low power
consumption, short startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
●
Low power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low power mode to minimize the regulator's operating current. In Low
power run mode, the clock frequency and the number of enabled peripherals are both
limited.
●
Low power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low power mode to minimize the regulator’s operating current. In Low power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
●
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
domain are stopped, the
CORE
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be
the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event
or the RTC wakeup.
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STM32L151xD STM32L152xD
Functional overview
●
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
●
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire V
domain is
CORE
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
●
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire V
domain is powered off. The PLL, MSI
CORE
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
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Functional overview
Table 3.
STM32L151xD STM32L152xD
Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Dynamic
voltage scaling
range
Operating power
supply range
DAC and ADC
operation
USB
I/O operation
Range 2 or
range 3
Degraded speed
performance
VDD = 1.65 to 1.8 V
Not functional Not functional
Conversion time
Not functional
up to 500 Ksps
Range 2 or
range 3
Degraded speed
performance
VDD = 1.8 to 2.0 V
Conversion time
Range 1, range 2
or range 3
V
DD = 2.0 to 2.4 V
DD = 2.4 to 3.6 V
up to
500 Ksps
Functional(1)
Functional(1)
Full speed operation
Full speed operation
Conversion time
up to
Range 1, range 2
or range 3
V
1 Msps
1. To be USB compliant from the IO voltage standpoint, the minimum VDD is 3.0 V.
Table 4.
CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
Range 3
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
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STM32L151xD STM32L152xD
Functional overview
Standby
Table 5.
Functionalities depending on the working mode (from Run/active down to
standby)
Stop
Low-
power
Run
Low-
power
Sleep
Ips
Run/Active
Sleep
Wakeup
Wakeup
capability
capability
CPU
Flash
RAM
Y
Y
Y
Y
Y
--
Y
Y
Y
--
Y
Y
Y
Y
Y
--
N
Y
Y
Y
--
--
Y
Y
Y
--
--
--
Y
--
Backup Registers
EEPROM
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
--
DMA
Programable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
Y
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
--
Y
Y
Y
Y
Y
Y
--
--
Y
Y
Y
Y
Y
Y
--
--
Y
Y
--
--
Y
Y
--
--
--
--
--
--
Power Down Rest
(PDR)
High Speed
Internal (HSI)
High Speed
External (HSE)
Low Speed Internal
(LSI)
Low Speed
External (LSE)
Multi-Speed
Internal (MSI)
Inter-Connect
Controler
RTC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
RTC Tamper
Y
Y
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
Y
LCD
USB
USART
SPI
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
--
--
--
--
--
Y
(1)
(1)
I2C
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Functional overview
STM32L151xD STM32L152xD
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Run/Active
Stop
Standby
Wakeup
Low-
power
Run
Low-
power
Sleep
Ips
Sleep
Wakeup
capability
capability
ADC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
Y
--
--
--
--
--
DAC
Tempsensor
OP amp
Comparators
Y
Y
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
--
Y
Y
Y
Y
--
Y
Y
Y
--
--
Y
--
--
--
Y
WWDG
Touch sensing
Systic Timer
GPIOs
Y
Y
3Pins
50 µs
Wakeup time to
Run mode
0 µs
0.36 µs
3 µs
32 µs
< 8 µs
0.65 µA (No
0.35 µA (No
RTC) VDD=1.8V RTC) VDD=1.8V
1.5 µA (with
RTC) VDD=1.8V
1 µA (with RTC)
VDD=1.8V
Consumption
VDD=1.8V to 3.6V
(Typ)
Down to
238 µA/MHz
(from Flash)
Down to
55 µA/MHz
(from Flash)
Down to Down to
11 µA 4.4 µA
0.65µA (No
RTC) VDD=3.0V RTC) VDD=3.0V
0.35 µA (No
1.7 µA (with 1.3 µA (with
RTC) VDD=3.0V RTC) VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
ARM® Cortex™-M3 core with MPU
The ARM Cortex™-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
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Functional overview
Owing to its embedded ARM core, the STM32L15xxD is compatible with all ARM tools and
software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L15xxD embeds a nested vectored interrupt controller able to
handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
●
●
●
●
●
●
●
●
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
●
V
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
DD
externally through V pins.
DD
●
V
, V
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
SSA
and PLL (minimum voltage to be applied to V
is 1.8 V when the ADC is used). V
DDA
DDA
and V
must be connected to V and V , respectively.
SSA
DD SS
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
●
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
●
After the V threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
DD
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V min value becomes
DD
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V at least 1 ms after it exits
DD
the POR area.
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Functional overview
STM32L151xD STM32L152xD
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
) in Stop mode. The device remains in reset mode when
REFINT
V
is below a specified threshold, V
or V
, without the need for any external
DD
POR/PDR
BOR
reset circuit.
Note:
3.3.3
3.3.4
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
/V
power supply and compares it to the V
threshold. This PVD offers 7 different
DD DDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V /V drops below the V threshold and/or when
DD DDA
PVD
V
/V
is higher than the V
threshold. The interrupt service routine can then generate
DD DDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
MR is used in Run mode (nominal regulation)
LPR is used in the Low power run, Low power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
Boot from Flash memory
Boot from System memory
Boot from embedded RAM
The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See STM32™ microcontroller system memory boot mode
AN2606 for details.
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Functional overview
3.4
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low power modes and ensures clock
robustness. It features:
●
Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
●
●
●
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
–
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a 0.5% accuracy.
●
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
–
32.768 kHz low-speed external crystal (LSE)
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
●
●
●
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
●
●
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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Functional overview
Figure 2.
STM32L151xD STM32L152xD
Clock tree
Standby supplied voltage domain
enable
Watchdog
Watchdog
LS
LSI RC
LSI tempo
RTC enable
RTC
LSE OSC
LSE tempo
LS
LS LS
LS
@V
DDCORE
CK_LCD
1 MHz
LCD enable
@V33
CK_ADC
ADC enable
MSI RC
ck_lsi
ck_lse
level shifters
MCO
@V
DDCORE
/ 1,2,4,8,16
not deepsleep
not deepsleep
/ 2,4,8,16
CK_PWR
CK_FCLK
CK_CPU
@V33
HSI RC
not (sleep or
deepsleep
level shifters
@V
DDCORE
System
clock
not (sleep or
deepsleep)
@V33
ck_msi
ck_hsi
ck_hse
HSE
CK_TIMSYS
/ 8
OSC
AHB
prescaler
/ 1,2,..512
level shifters
@V
DDCORE
ck_pll
@V33
PLL
APB1
APB2
ck_pllin
X 3,4,6,8,12
16,24,32,48
prescaler prescaler
/ 1,2,4,8,16 / 1,2,4,8,16
LS
@V33
1 MHz clock
detector
/ 2, 3, 4
level shifters
Clock
source
control
@V
DDCORE
HSE present or not
usben and (not deepsleep)
LS
CK_USB48
ck_usb = Vco / 2 (Vco must be at 96 MHz)
timer9en and (not deepsleep)
CK_TIMTGO
CK_APB1
CK_APB2
if (APB1 presc = 1)x1
x2
else
apb1 periphen and (not deepsleep)
apb2 periphen and (not deepsleep)
MS18583V1
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
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Functional overview
3.5
Low power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronisation.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
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Functional overview
STM32L151xD STM32L152xD
3.7
Memories
The STM32L15xxD devices have the following features:
●
48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
●
The non-volatile memory is divided into three arrays:
–
–
–
384 Kbytes of embedded Flash program memory
12 Kbytes of data EEPROM
Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
–
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)
and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8
FSMC (flexible static memory controller)
The FSMC supports the following modes: SRAM, PSRAM, NOR/OneNAND Flash.
Functionality overview:
●
●
●
●
●
●
●
Up to 26 bit address bus
Up to 16-bit data bus
Write FIFO
Burst mode
Code execution from external memory
Four chip select signals
Up to 32 MHz external access
3.9
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
2
The DMA can be used with the main peripherals: SPI, I C, USART, SDIO, general-purpose
timers, DAC and ADC.
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Functional overview
3.10
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
●
Internal step-up converter to guarantee functionality and contrast control irrespective of
. This converter can be deactivated, in which case the V pin is used to provide
V
DD
LCD
the voltage to the LCD
●
●
●
●
●
●
●
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
Supports static, 1/2, 1/3 and 1/4 bias
Phase inversion to reduce power consumption and EMI
Up to 8 pixels can be programmed to blink
Unneeded segments and common pins can be used as general I/O pins
LCD RAM can be updated at any time owing to a double-buffer
The LCD controller can operate in Stop mode
3.11
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L15xxD devices with up to 40
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs with up to 29
external channel in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.11.1
Temperature sensor
The temperature sensor (T
temperature.
) generates a voltage V
that varies linearly with
SENSE
SENSE
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
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Functional overview
STM32L151xD STM32L152xD
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 6.
Temperature sensor calibration values
Calibration value name
Description
Memory address
TS ADC raw data acquired at
temperature of 30 °C,
TSENSE_CAL1
TSENSE_CAL2
0x1FF8 00FA - 0x1FF8 00FB
VDDA= 3 V
TS ADC raw data acquired at
temperature of 110 °C
0x1FF8 00FE - 0x1FF8 00FF
VDDA= 3 V
3.11.2
Internal voltage reference (V
)
REFINT
The internal voltage reference (V
) provides a stable (bandgap) voltage output for the
REFINT
ADC and Comparators. V
is internally connected to the ADC_IN17 input channel. It
REFINT
enables accurate monitoring of the V
value (when no external voltage, VREF+, is
DD
available for ADC). The precise voltage of V
is individually measured for each part by
REFINT
ST during production test and stored in the system memory area. It is accessible in read-
only mode.
Table 7.
Internal voltage reference measured values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 30 °C
VDDA= 3 V
VREFINT_CAL
0x1FF8 00F8 - 0x1FF8 00F9
3.12
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
●
●
●
●
●
●
●
●
●
●
Two DAC converters: one for each output channel
Up to 10-bit output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channels, independent or simultaneous conversions
DMA capability for each channel (including the underrun interrupt)
External triggers for conversion
Input reference voltage V
REF+
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STM32L151xD STM32L152xD
Functional overview
Eight DAC trigger inputs are used in the STM32L15xxD. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
3.13
Operational amplifier
The STM32L15xxD embeds three operational amplifiers with external or internal follower
routing capability (or even amplifier and filter capability with external components). When
one operational amplifier is selected, one external ADC channel is used to enable output
measurement.
The operational amplifiers feature:
●
●
●
●
Low input bias current
Low offset voltage
Low power mode
Rail-to-rail input
3.14
Ultra-low-power comparators and reference voltage
The STM32L15xxD embeds two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
●
One comparator with fixed threshold
●
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
–
–
DAC output
External I/O
Internal reference voltage (V
) or a submultiple (1/4, 1/2, 3/4)
REFINT
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low power / low current output
buffer (driving current capability of 1 µA typical).
3.15
3.16
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
V
.
REFINT
Touch sensing
The STM32L15xxD devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 34 capacitive sensing channels
distributed over 11 analog I/O groups. Both software and timer capacitive sensing
acquisition modes are supported.
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Functional overview
STM32L151xD STM32L152xD
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate.
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.17
Timers and watchdogs
The ultra-low-power STM32L15xxD devices include seven general-purpose timers, two
basic timers, and two watchdog timers.
Table 8 compares the features of the general-purpose and basic timers.
Table 8.
Timer
Timer feature comparison
Counter
DMArequest Capture/compare Complementary
Counter type
Prescaler factor
resolution
generation
channels
outputs
TIM2,
TIM3,
TIM4
Up, down,
up/down
Any integer between
1 and 65536
16-bit
Yes
4
No
Up, down,
up/down
Any integer between
1 and 65536
TIM5
TIM9
32-bit
16-bit
16-bit
16-bit
Yes
No
4
2
1
0
No
No
No
No
Up, down,
up/down
Any integer between
1 and 65536
TIM10,
TIM11
Any integer between
1 and 65536
Up
Up
No
TIM6,
TIM7
Any integer between
1 and 65536
Yes
3.17.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L15xxD
devices (see Table 8 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32-
bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
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STM32L151xD STM32L152xD
Functional overview
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.17.2
3.17.3
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.17.4
3.17.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.18
Communication interfaces
3.18.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
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Functional overview
STM32L151xD STM32L152xD
3.18.2
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave
capability. The three USARTs provide hardware management of the CTS and RTS signals.
All USART/UART interfaces can be served by the DMA controller.
3.18.3
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
2
3.18.4
3.18.5
Inter-integrated sound (I S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 24 MHz in 8-bit mode, and is compliant with the
SD Memory Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol
Rev1.1.
3.18.6
Universal serial bus (USB)
The STM32L15xxD embeds a USB device peripheral compatible with the USB full-speed
12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and supports suspend/resume. The dedicated
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STM32L151xD STM32L152xD
Functional overview
48 MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).
3.19
3.20
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Development support
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L15xxD through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
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Pin descriptions
STM32L151xD STM32L152xD
4
Pin descriptions
Figure 3.
STM32L15xZD LQFP144 pinout
PE2
PE3
PE4
PE5
1
108
107
106
105
104
103
102
101
100
99
VDD_2
VSS_2
PH2
2
3
4
PA13
PA12
PA11
PA10
PA9
PE6-WKUP3
5
V
LCD
6
PC13-WKUP2
PC14-OSC32_IN
7
8
PC15-OSC32_OUT
PF0
9
PA8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PC9
PF1
98
PC8
PF2
97
PC7
PF3
96
PC6
PF4
95
VDD_9
VSS_9
PG8
PF5
94
VSS_5
VDD_5
PF6
93
LQFP144
92
PG7
91
PG6
PF7
90
PG5
PF8
89
PG4
PF9
88
PG3
PF10
OSC_IN
OSC_OUT
NRST
PC0
87
PG2
86
PD15
PD14
VDD_8
VSS_8
PD13
PD12
PD11
PD10
PD9
85
84
83
82
81
80
79
78
77
76
75
74
73
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0 -WKUP1
PA1
PA2
MS18581V2
32/140
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STM32L151xD STM32L152xD
Pin descriptions
Figure 4.
STM32L15xQD UFBGA132 ballout
ꢆ
ꢅ
ꢄ
ꢃ
ꢂ
ꢁ
ꢀ
ꢉ
ꢈ
ꢆꢇ
ꢆꢆ
ꢆꢅ
PB3
PD3
PD2
PA15
PD1
PD0
PA14
PC12
PC11
PA13
PC10
PH2
PA12
PA11
PA10
PE3
PE4
PE1
PE2
PE5
PB8
PB9
PE0
BOOT0
PB7
PD7
PB6
PD5
PD6
PB4
PD4
A
B
C
PC13-
WKUP2
VDD_3 PB5
PG14
PG13
PC14-
OSC32
_IN
PE6-
D
E
PG10
PA8
PC7
PC9
PC6
VSS_3
VSS_6
PF4
PF0
PG12
PA9
PF1
PG9
PG5
PG3
PF2
PF3
WKUP3
PC15-
OSC32
_OUT
VLCD
PC8
PG4
PH0
OSC_IN
F
PF5
PF7
VSS_10
VDD_10
VSS_2
VSS_1
VSS_5
VSS_9
VDD_9
PH1
OSC_
OUT
G
PG2
PG1
VDD_2
VDD_1
VDD_5
PF6
H
PF8
PA4
PA5
PG0
PF15
PD8
PD15
PD12
PB15
PD14
PD11
PB14
PD13
PD10
PB13
PC0
NRST
PC1
VDD_6
PC2
PF14
PD9
PA7
PC4
PC5
PB0
PF9
PF12
PF13
VSSA
J
OPAMP3
_VINM
PC3
PA2
PF11
K
L
PA0-
WKUP1
PE10
PE9
PE12
PE11
PB10
PE13
PB11
PE14
PB12
PE15
VREF+
VDDA
PA3
PA6
PB2
PB1
PE8
PE7
OPAMP2
_VINM
OPAMP1
_VINM
PA1
M
MS31072V1
1. This figure shows the package top view.
Doc ID 022027 Rev 6
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Pin descriptions
STM32L151xD STM32L152xD
Figure 5.
STM32L15xVD LQFP100 pinout
PE2
PE3
PE4
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
PH2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PE5
PE6-WKUP3
VLCD
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD_5
PH0-OSC_IN
PH1-OSC_OUT
NRST
LQFP100
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PD8
PB15
PB14
PB13
PB12
PA0-WKUP1
PA1
PA2
ai15692c
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Figure 6. STM32L15xRD LQFP64 pinout
Pin descriptions
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
VDD_2
V
1
LCD
VSS_
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC13-WKUP2
PC14-OSC32_IN
PC15-OSC32_OUT
PH0 -OSC_IN
PH1-OSC_OUT
NRST
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
2
3
4
5
6
7
PC0
PC1
PC2
PC3
8
LQFP64
9
10
11
12
13
14
15
16
PC6
VSSA
VDDA
PA0-WKUP1
PB15
PB14
PB13
PB12
PA1
PA2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ai15693c
Doc ID 022027 Rev 6
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Pin descriptions
Figure 7.
STM32L151xD STM32L152xD
STM32L15xRD WLCSP64 ballout
ꢆ
ꢅ
ꢄ
ꢃ
ꢂ
ꢁ
ꢀ
ꢉ
VDD_2
VSS_2
PA11
PC10
PA14
PA12
PD2
PC11
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0 VSS_3 VDD_3
A
B
C
PC14-
OSC32_IN
OSC32_OUT
PB9
PC15-
PC13-
WKUP2
PC12
VLCD
NRST
D
E
PH1-
PH0-
PC9
PC6
PA9
PC7
PA10
PC8
PC2
PA1
PB8
PA13
OSC_OUT
OSC_IN
VSSA
PC3
PC0
PC1
PA8
PB1
PA5
PA0-
WKUP1
F
PB15
PB14
PB11
VSS_4
G
PB13
PB12
PB10
PB2
PA7
PB0
PA6
PC5
VDD_4
PC4
PA3
PA4
VDDA
PA2
H
VDD_1 VSS_1
MS31070V1
1. This figure shows the package top view.
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Pin descriptions
Table 9.
Pins
STM32L15xxD pin definitions
Main
Pin name
function(3)
(after reset)
Alternate functions
1
2
3
4
B2
A1
B1
C2
1
2
3
4
-
-
-
-
-
-
-
-
PE2
PE3
PE4
PE5
I/O FT
I/O FT
I/O FT
I/O FT
PE2
PE3
PE4
PE5
TIM3_ETR/LCD_SEG38/FSMC_A23/TRACECLK
TIM3_CH1/LCD_SEG39/FSMC_A19/TRACED0
TIM3_CH2/FSMC_A20/TRACED1
TIM9_CH1/FSMC_A21/TRACED2
PE6-
WKUP3
5
D2
5
-
-
I/O FT
S
PE6
WKUP3/RTC_TAMP3/TIM9_CH2/TRACED3
(4)
6
7
E2
C1
6
7
1 C6
VLCD
VLCD
2 C8 PC13-WKUP2 I/O FT
PC14-
PC13
WKUP2/RTC_TAMP1/RTC_TS/RTC_OUT
OSC32_IN
8
9
D1
E1
8
9
3 B8
I/O
PC14
PC15
OSC32_IN(5)
PC15-
OSC32_OUT
4 B7
I/O
OSC32_OUT
10 D6
11 D5
12 D4
13 E4
14 F3
15 F4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF0
PF1
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
PF0
PF1
FSMC_A0
FSMC_A1
FSMC_A2
FSMC_A3
FSMC_A4
FSMC_A5
PF2
PF2
PF3
PF3
PF4
PF4
PF5
PF5
16 F2 10
17 G2 11
VSS_5
VDD_5
PF6
VSS_5
VDD_5
PF6
S
18 G3
19 G4
20 H4
21 J6
-
-
-
-
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I
TIM5_CH1/TIM5_ETR/ADC_IN27
TIM5_CH2/ADC_IN28/COMP1_INP
TIM5_CH3/ADC_IN29/COMP1_INP
TIM5_CH4/ADC_IN30/COMP1_INP
ADC_IN30/COMP1_INP
PF7
PF7
PF8
PF8
PF9
PF9
22
-
PF10
PF10
PH0
23 F1 12 5 D8 PH0-OSC_IN(6)
OSC_IN
PH1-
24 G1 13 6 D7
OSC_OUT(6)
O
PH1
OSC_OUT
25 H2 14 7 C7
26 H1 15 8 E8
NRST
PC0
I/O
NRST
PC0
I/O FT
LCD_SEG18/ADC_IN10/COMP1_INP
LCD_SEG19/ADC_IN11/COMP1_INP
/OPAMP3_VINP
27 J2 16 9 F8
PC1
I/O FT
PC1
LCD_SEG20/ADC_IN12/COMP1_INP
/OPAMP3_VINM
28
-
-
17 10 D6
PC2
PC2
I/O FT
I/O FT
I
PC2
PC2
J3
K1
-
-
-
-
-
LCD_SEG20/ADC_IN12/COMP1_INP
OPAMP3
_VINM
-
- OPAMP3_VINM
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Pin descriptions
STM32L151xD STM32L152xD
Table 9.
Pins
STM32L15xxD pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Alternate functions
LCD_SEG21/ADC_IN13/COMP1_INP
/OPAMP3_VOUT
29 K2 18 11 F7
30 J1 19 12 E7
PC3
I/O
PC3
VSSA
VREF-
VREF+
VDDA
S
S
S
S
VSSA
VREF-
VREF+
VDDA
31
-
20
-
-
-
-
32 L1 21
33 M1 22 13 G8
WKUP1/RTC_TAMP2/TIM2_CH1_ETR/TIM5_CH1/
USART2_CTS/ADC_IN0/COMP1_INP
34 L2 23 14 F6 PA0-WKUP1 I/O FT
PA0
PA1
PA2
PA2
TIM2_CH2/TIM5_CH2/ USART2_RTS/LCD_SEG0/
ADC_IN1/COMP1_INP/OPAMP1_VINP
35 M2 24 15 E6
PA1
PA2
PA2
I/O FT
I/O FT
I/O FT
I
TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/
LCD_SEG1/ADC_IN2/ COMP1_INP/OPAMP1_VINM
36
-
-
25 16 H8
TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/
LCD_SEG1/ADC_IN2/COMP1_INP
K3
M3
-
-
-
-
-
OPAMP1_
VINM
-
- OPAMP1_VINM
TIM2_CH4/TIM5_CH4/TIM9_CH2/USART2_RX/
LCD_SEG2/ ADC_IN3/COMP1_INP/OPAMP1_VOUT
37 L3 26 17 G7
PA3
I/O
PA3
38
39
-
-
27 18 F5
28 19 G6
VSS_4
VDD_4
S
S
VSS_4
VDD_4
SPI1_NSS/SPI3_NSS/I2S3_WS/USART2_CK/
ADC_IN4/DAC_OUT1/COMP1_INP
40 J4 29 20 H7
41 K4 30 21 E5
42 L4 31 22 G5
PA4
PA5
PA6
PA7
PA7
I/O
PA4
PA5
PA6
PA7
PA7
TIM2_CH1_ETR/SPI1_SCK/ADC_IN5/DAC_OUT2/
COMP1_INP
I/O
TIM3_CH1/TIM10_CH1/SPI1_MISO/LCD_SEG3/
ADC_IN6/COMP1_INP/OPAMP2_VINP
I/O FT
I/O FT
I/O FT
I
TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/
ADC_IN7/COMP1_INP/OPAMP2_VINM
43
-
-
32 23 G4
TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/
ADC_IN7/COMP1_INP
J5
M4
-
-
-
-
-
OPAMP2_VI
NM
-
- OPAMP2_VINM
44 K5 33 24 H6
45 L5 34 25 H5
PC4
PC5
I/O FT
I/O FT
PC4
PC5
LCD_SEG22/ADC_IN14/COMP1_INP
LCD_SEG23/ADC_IN15/COMP1_INP
TIM3_CH3/LCD_SEG5/ADC_IN8/COMP1_INP/
VREF_OUT/ OPAMP2_VOUT
46 M5 35 26 H4
47 M6 36 27 F4
PB0
PB1
I/O
PB0
PB1
TIM3_CH4/LCD_SEG6/ADC_IN9/COMP1_INP/
VREF_OUT
I/O FT
-
-
37 28 H3
PB2
PB2
I/O FT PB2/BOOT1
I/O FT PB2/BOOT1
COMP1_INP
48 L6
-
-
ADC_IN0b/COMP1_INP
38/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Pin descriptions
Table 9.
Pins
STM32L15xxD pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Alternate functions
49 K6
50 J7
51 E3
52 H3
53 K7
54 J8
55 J9
56 H9
57 G9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF11
PF12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
I/O FT
I/O FT
S
PF11
PF12
VSS_6
VDD_6
PF13
PF14
PF15
PG0
ADC_IN1b/COMP1_INP
ADC_IN2b/COMP1_INP/FSMC_A6
S
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O
ADC_IN3b/COMP1_INP/FSMC_A7
ADC_IN6b/COMP1_INP/FSMC_A8
ADC_IN7b/COMP1_INP/FSMC_A9
ADC_IN8b/COMP1_INP/FSMC_A10
ADC_IN9b/COMP1_INP/FSMC_A11
FSMC_D4/ADC_IN22/COMP1_INP
PG1
PG1
58 M7 38
59 L7 39
PE7
PE7
PE8
I/O
PE8
FSMC_D5/ADC_IN23/COMP1_INP
60 M8
-
-
-
PE9
I/O
PE9
TIM2_CH1_ETR/FSMC_D6/ ADC_IN24/COMP1_INP
61
62
-
-
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
S
VSS_7
VDD_7
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
S
63 L8 41
64 M9 42
65 L9 43
66 M10 44
67 M11 45
68 M12 46
I/O
TIM2_CH2/ FSMC_D7/ADC_IN25/COMP1_INP
TIM2_CH3/FSMC_D8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
TIM2_CH4/SPI1_NSS/FSMC_D9
SPI1_SCK/FSMC_D10
SPI1_MISO/FSMC_D11
SPI1_MOSI/FSMC_D12
69 L10 47 29 G3
70 L11 48 30 F3
71 F12 49 31 H2
72 G12 50 32 H1
TIM2_CH3/I2C2_SCL/USART3_TX/LCD_SEG10
TIM2_CH4/I2C2_SDA/ USART3_RX/LCD_SEG11
S
TIM10_CH1/I2C2_SMBA/SPI2_NSS/I2S2_WS/
USART3_CK/ LCD_SEG12/ADC_IN18/COMP1_INP
73 L12 51 33 G2
74 K12 52 34 G1
75 K11 53 35 F2
76 K10 54 36 F1
PB12
PB13
PB14
PB15
I/O FT
I/O FT
I/O FT
I/O FT
PB12
PB13
PB14
PB15
TIM9_CH1/SPI2_SCK/ I2S2_CK/ USART3_CTS/
LCD_SEG13/ADC_IN19/COMP1_INP
TIM9_CH2/SPI2_MISO/ USART3_RTS/LCD_SEG14/
ADC_IN20/COMP1_INP
TIM11_CH1/SPI2_MOSI/I2S2_SD/LCD_SEG15/
ADC_IN21/COMP1_INP/RTC_REFIN
77 K9 55
78 K8 56
79 J12 57
80 J11 58
81 J10 59
-
-
-
-
-
-
-
-
-
-
PD8
PD9
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
PD8
PD9
USART3_TX/LCD_SEG28/FSMC_D13
USART3_RX/LCD_SEG29/FSMC_D14
PD10
PD11
PD12
PD10
PD11
PD12
USART3_CK/LCD_SEG30/FSMC_D15
USART3_CTS/LCD_SEG31/FSMC_A16
TIM4_CH1 / USART3_RTS/LCD_SEG32/FSMC_A17
Doc ID 022027 Rev 6
39/140
Pin descriptions
STM32L151xD STM32L152xD
Table 9.
Pins
STM32L15xxD pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Alternate functions
82 H12 60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD13
VSS_8
VDD_8
PD14
PD15
PG2
PG3
PG4
I/O FT
S
PD13
VSS_8
VDD_8
PD14
PD15
PG2
PG3
PG4
PG5
PG6
PG7
PG8
VSS_9
VDD_9
PC6
TIM4_CH2/LCD_SEG33/FSMC_A18
83
84
-
-
-
-
S
85 H11 61
86 H10 62
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
TIM4_CH3/LCD_SEG34/FSMC_D0
TIM4_CH4/LCD_SEG35/FSMC_D1
FSMC_A12/ADC_IN10b/COMP1_INP
FSMC_A13/ADC_IN11b/COMP1_INP
FSMC_A14/ADC_IN12b/COMP1_INP
FSMC_A15
87 G10
88 F9
89 F10
90 E9
-
-
-
-
-
-
-
-
-
PG5
PG6
PG7
PG8
VSS_9
VDD_9
PC6
91
92
93
-
-
-
94 F6
95 G6
S
96 E12 63 37 E1
97 E11 64 38 E2
98 E10 65 39 E3
99 D12 66 40 D1
100 D11 67 41 E4
101 D10 68 42 D2
102 C12 69 43 D3
103 B12 70 44 C1
104 A12 71 45 C2
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
TIM3_CH1/I2S2_MCK/LCD_SEG24/SDIO_D6
TIM3_CH2/I2S3_MCK/LCD_SEG25/SDIO_D7
TIM3_CH3/LCD_SEG26/SDIO_D0
TIM3_CH4/LCD_SEG27/SDIO_D1
USART1_CK/MCO/LCD_COM0
PC7
PC7
PC8
PC8
PC9
PC9
PA8
PA8
PA9
PA9
USART1_TX / LCD_COM1
PA10
PA11
PA12
PA10
PA11
PA12
USART1_RX / LCD_COM2
USART1_CTS/ USB_DM/SPI1_MISO
USART1_RTS/USB_DP/SPI1_MOSI
JTMS-
SWDAT
105 A11 72 46 D4
PA13
I/O FT
106 C11 73
-
-
PH2
VSS_2
VDD_2
I/O FT
PH2
VSS_2
VDD_2
FSMC_A22
107 F11 74 47 B1
108 G11 75 48 A1
S
S
JTCK-
SWCLK
109 A10 76 49 B2
110 A9 77 50 C3
111 B11 78 51 A2
112 C10 79 52 B3
113 B10 80 53 C4
PA14
PA15
PC10
PC11
PC12
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
TIM2_CH1_ETR/ SPI1_NSS/SPI3_NSS/
I2S3_WS/LCD_SEG17
JTDI
PC10
PC11
PC12
SPI3_SCK/I2S3_CK/USART3_TX/ UART4_TX/
LCD_SEG28/LCD_SEG40/LCD_COM4/SDIO_D2
SPI3_MISO/USART3_RX/UART4_RX/
LCD_SEG29/LCD_SEG41/LCD_COM5/SDIO_D3
SPI3_MOSI/I2S3_SD/USART3_CK/ UART5_TX/
LCD_SEG30/ LCD_SEG42/LCD_COM6/SDIO_CK
40/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Pin descriptions
Table 9.
Pins
STM32L15xxD pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Alternate functions
114 C9 81
115 B9 82
-
-
-
-
PD0
PD1
I/O FT
I/O FT
PD0
PD1
TIM9_CH1/SPI2_NSS/I2S2_WS/ FSMC_D2
SPI2_SCK/I2S2_CK/FSMC_D3
TIM3_ETR/UART5_RX/LCD_SEG31/LCD_SEG43/
LCD_COM7/SDIO_CMD
116 C8 83 54 A3
PD2
I/O FT
PD2
117 B8 84
118 B7 85
119 A6 86
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD3
PD4
I/O FT
I/O FT
I/O FT
S
PD3
PD4
SPI2_MISO/USART2_CTS/FSMC_CLK
SPI2_MOSI/I2S2_SD/USART2_RTS/FSMC_NOE
USART2_TX/FSMC_NWE
PD5
PD5
120 F7
121 G7
-
-
VSS_10
VDD_10
PD6
VSS_10
VDD_10
PD6
S
122 B6 87
123 A5 88
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
USART2_RX/FSMC_NWAIT
TIM9_CH2/USART2_CK/FSMC_NE1
FSMC_NE2
PD7
PD7
124 D9
125 D8
-
-
-
-
-
-
-
-
-
PG9
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
FSMC_NE3
126
-
127 D7
128 C7
129 C6
FSMC_NE4
FSMC_A24
FSMC_A25
130
131
132
-
-
-
S
I/O FT
TIM2_CH2/SPI1_SCK/SPI3_SCK/ I2S3_CK/
LCD_SEG7/COMP2_INM
133 A8 89 55 A4
134 A7 90 56 B4
PB3
PB4
I/O FT
JTDO
TIM3_CH1/ SPI1_MISO/SPI3_MISO/LCD_SEG8/
COMP2_INP
I/O FT NJTRST
TIM3_CH2 /I2C1_SMBA/SPI1_MOSI/SPI3_MOSI/
I2S3_SD/LCD_SEG9/COMP2_INP
135 C5 91 57 A5
136 B5 92 58 B5
137 B4 93 59 C5
138 A4 94 60 A6
139 A3 95 61 D5
PB5
PB6
I/O FT
I/O FT
I/O FT
I
PB5
PB6
TIM4_CH1/I2C1_SCL/USART1_TX/COMP2_INP
TIM4_CH2/I2C1_SDA/USART1_RX/PVD_IN/
FSMC_NADV/ COMP2_INP
PB7
PB7
BOOT0
PB8
BOOT0
PB8
TIM4_CH3/TIM10_CH1/I2C1_SCL/LCD_SEG16/
SDIO_D4
I/O FT
TIM4_CH4/ TIM11_CH1/I2C1_SDA/LCD_COM3/
SDIO_D5
140 B3 96 62 B6
PB9
I/O FT
PB9
141 C3 97
142 A2 98
-
-
-
-
PE0
PE1
I/O FT
I/O FT
S
PE0
PE1
TIM4_ETR/TIM10_CH1/LCD_SEG36 /FSMC_NBL0
TIM11_CH1/LCD_SEG37/FSMC_NBL1
143 D3 99 63 A7
144 C4 100 64 A8
VSS_3
VDD_3
VSS_3
VDD_3
S
Doc ID 022027 Rev 6
41/140
Pin descriptions
STM32L151xD STM32L152xD
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. Applicable to STM32L152xD devices only. In STM32L151xD devices, this pin should be connected to VDD
.
5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).
6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
42/140
Doc ID 022027 Rev 6
Table 10. Alternate function input/output
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
BOOT0 BOOT0
NRST
PA0-
NRST
COMP1_INP/
TIMx_IC1_0/
G1IO1
WKUP1/
TIM2_CH1_
ETR
EVENT
OUT
TIM5_CH1
TIM5_CH2
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
WKUP1 TAMPER2
COMP1_INP/
TIMx_IC2_0
G1IO2
EVENT
OUT
PA1
TIM2_CH2
TIM2_CH3
TIM2_CH4
SEG0
COMP1_INP/
TIMx_IC3_0/
G1IO3
EVENT
OUT
PA2
PA3
TIM5_CH3 TIM9_CH1
TIM5_CH4 TIM9_CH2
SEG1
SEG2
COMP1_INP/
TIMx_IC4_0/
G1IO4
EVENT
OUT
SPI3_NSS
USART2_CK
I2S3_WS
COMP1_INP/
TIMx_IC1_1
EVENT
OUT
PA4
PA5
SPI1_NSS
SPI1_SCK
COMP1_INP/
TIMx_IC2_1
EVENT
OUT
TIM2_CH1_ETR
COMP1_INP/
TIMx_IC3_1
G2IO1
TIM10_
TIM3_CH1
CH1
EVENT
OUT
PA6
PA7
SPI1_MISO
SPI1_MOSI
SEG3
SEG4
COMP1_INP/
TIMx_IC4_1/
G2IO2
TIM11_
TIM3_CH2
CH1
EVENT
OUT
TIMx_IC1_2/
G4IO1
EVENT
OUT
PA8
MCO
USART1_CK
USART1_TX
USART1_RX
COM0
COM1
COM2
TIMx_IC2_2/
G4IO2
EVENT
OUT
PA9
TIMx_IC3_2/
G4IO3
EVENT
OUT
PA10
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
TIMx_IC4_2/
G4IO4
EVENT
OUT
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
SPI1_MISO
SPI1_MOSI
USART1_CTS
USART1_RTS
USBDM
USBDP
EVENT
OUT
TIMx_IC1_3/
TIMx_IC2_3/
G5IO1
EVENT
OUT
JTMS-SWDIO
JTCK-SWCLK
JTDI
TIMx_IC3_3/
G5IO2
EVEN
TOUT
SPI3_NSS
I2S3_WS
TIMx_IC4_3/
G5IO3
EVEN
TOUT
TIM2_CH1_ETR
SPI1_NSS
SEG17
SEG5
SEG6
COMP1_INP/
G3IO1
EVEN
TOUT
TIM3_CH3
TIM3_CH4
COMP1_INP/
G3IO2
EVENT
OUT
COMP1_INP/
G3IO3
EVENT
OUT
BOOT1
JTDO
SPI3_SCK
I2S3_CK
EVENT
OUT
TIM2_CH2
SPI1_SCK
SEG7
SEG8
SEG9
EVENT
OUT
JTRST
TIM3_CH1
TIM3_CH2
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
SPI1_MISO SPI3_MISO
G6IO1
G6IO2
G6IO3
G6IO4
I2C1_
SMBA
SPI3_MOSI
I2S3_SD
EVENT
OUT
SPI1_MOSI
EVENT
OUT
I2C1_SCL
USART1_TX
USART1_RX
EVENT
OUT
I2C1_SDA
I2C1_SCL
I2C1_SDA
NADV
TIM10_
CH1
EVENT
OUT
SEG16
COM3
SDIO_D4
SDIO_D5
TIM11_
CH1
EVENT
OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PB10
PB11
PB12
PB13
PB14
PB15
TIM2_CH3
TIM2_CH4
I2C2_SCL
I2C2_SDA
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
EVENT
OUT
TIM10_
CH1
SPI2_NSS
I2C2_SMBA
COMP1_INP/
G7IO1
EVENT
OUT
I2S2_WS
TIM9_
CH1
SPI2_SCK
I2S2_CK
COMP1_INP/
G7IO2
EVENT
OUT
TIM9_
CH2
COMP1_INP/
G7IO3
EVENT
OUT
SPI2_MISO
TIM11_
CH1
SPI2_MOSI
I2S2_SD
COMP1_INP/
G7IO4
EVENT
OUT
RTC_REFIN
COMP1_INP/
TIMx_IC1_4/
G8IO1
EVENT
OUT
PC0
PC1
PC2
PC3
PC4
SEG18
SEG19
SEG20
SEG21
SEG22
COMP1_INP/
TIMx_IC2_4/
G8IO2
EVENT
OUT
COMP1_INP/
TIMx_IC3_4/
G8IO3
EVENT
OUT
COMP1_INP/
TIMx_IC4_4/
G8IO4
EVENT
OUT
COMP1_INP/
TIMx_IC1_5/
G9IO1
EVENT
OUT
COMP1_INP/
TIMx_IC2_5/
G9IO2
EVENT
OUT
PC5
PC6
SEG23
SEG24
TIMx_IC3_5/
G10IO1
EVENT
OUT
TIM3_CH1
I2S2_MCK
SDIO_D6
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
TIMx_IC4_5/
G10IO2
EVENT
OUT
PC7
TIM3_CH2
TIM3_CH3
TIM3_CH4
I2S3_MCK
SEG25
SEG26
SEG27
SDIO_D7
SDIO_D0
SDIO_D1
TIMx_IC1_6/
G10IO3
EVENT
OUT
PC8
PC9
TIMx_IC2_6/
G10IO4
EVENT
OUT
COM4/
SEG28/
SEG40
SPI3_SCK
I2S3_CK
TIMx_IC3_6/
G5IO4
EVENT
OUT
PC10
PC11
PC12
USART3_TX
UART4_TX
UART4_RX
UART5_TX
SDIO_D2
SDIO_D3
SDIO_CK
COM5/
SEG29
/SEG41
EVENT
OUT
SPI3_MISO USART3_RX
TIMx_IC4_6
TIMx_IC1_7
COM6/
SEG30/
SEG42
SPI3_MOSI
USART3_CK
I2S3_SD
EVENT
OUT
WKUP2/
TAMPER1/
TIMESTAMP/
ALARM_OUT/
512Hz
PC13-
WKUP2
EVENT
OUT
TIMx_IC2_7
PC14
OSC32_ OSC32_IN
IN
EVENT
OUT
TIMx_IC3_7
TIMx_IC4_7
PC15
EVENT
OUT
OSC32_ OSC32_OUT
OUT
SPI2_NSS
I2S2_WS
EVENT
OUT
PD0
PD1
TIM9_CH1
D2 /DA2
D3 /DA3
TIMx_IC1_8
TIMx_IC2_8
SPI2 SCK
I2S2_CK
EVENT
OUT
COM7/
SEG31/
SEG43
SDIO_
CMD
EVENT
OUT
PD2
TIM3_ETR
UART5_RX
TIMx_IC3_8
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PD3
SPI2_MISO
USART2_CTS
USART2_RTS
USART2_TX
USART2_RX
USART2_CK
USART3_TX
USART3_RX
USART3_CK
USART3_CTS
USART3_RTS
CLK
TIMx_IC4_8
TIMx_IC1_9
TIMx_IC2_9
TIMx_IC3_9
TIMx_IC4_9
TIMx_IC1_10
TIMx_IC2_10
TIMx_IC3_10
TIMx_IC4_10
TIMx_IC1_11
TIMx_IC2_11
TIMx_IC3_11
TIMx_IC4_11
TIMx_IC1_12
TIMx_IC2_12
SPI2_MOSI
I2S2_SD
EVENT
OUT
PD4
NOE
EVENT
OUT
PD5
NWE
EVENT
OUT
PD6
NWAIT
NE1
EVENT
OUT
PD7
TIM9_CH2
EVENT
OUT
PD8
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
D13/DA13
D14/DA14
D15/DA15
A16
EVENT
OUT
PD9
EVENT
OUT
PD10
PD11
PD12
PD13
PD14
PD15
PE0
EVENT
OUT
EVENT
OUT
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM4_CH4
TIM4_ETR
A17
EVENT
OUT
A18
EVENT
OUT
D0/DA0
D1/DA1
NBL0
EVENT
OUT
TIM10_
CH1
EVENT
OUT
TIM11_
CH1
EVENT
OUT
PE1
NBL1
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PE2
TRACECK
TRACED0
TRACED1
TRACED2
TIM3_ETR
TIM3_CH1
TIM3_CH2
SEG 38
SEG 39
A23
A19
A20
A21
TIMx_IC3_12
TIMx_IC4_12
TIMx_IC1_13
TIMx_IC2_13
EVENT
OUT
PE3
PE4
PE5
EVENT
OUT
EVENT
OUT
TIM9_CH1
TIM9_CH2
WKUP3/
TAMPER3 /
TRACED3
PE6-
WKUP3
EVENT
OUT
TIMx_IC3_13
COMP1_INP/
TIMx_IC4_13
EVENT
OUT
PE7
D4/DA4
D5/DA5
D6/DA6
D7/DA7
D8/DA8
D9/DA9
D10/DA10
D11/DA11
D12/DA12
A0
COMP1_INP/
TIMx_IC1_14
EVENT
OUT
PE8
COMP1_INP/
TIMx_IC2_14
EVENT
OUT
PE9
TIM2_CH1_ETR
TIM2_CH2
COMP1_INP/
TIMx_IC3_14
EVENT
OUT
PE10
PE11
PE12
PE13
PE14
PE15
PF0
EVENT
OUT
TIM2_CH3
TIMx_IC4_14
TIMx_IC1_15
TIMx_IC2_15
TIMx_IC3_15
TIMx_IC4_15
EVENT
OUT
TIM2_CH4
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PF1
A1
EVENT
OUT
PF2
A2
A3
A4
A5
EVENT
OUT
PF3
EVENT
OUT
PF4
EVENT
OUT
PF5
COMP1_INP
G11IO1
EVENT
OUT
PF6
TIM5_ETR
TIM5_CH2
TIM5_CH3
TIM5_CH4
COMP1_INP
G11IO2
EVENT
OUT
PF7
COMP1_INP
G11IO3
EVENT
OUT
PF8
COMP1_INP
G11IO4
EVENT
OUT
PF9
COMP1_INP
G11IO5
EVENT
OUT
PF10
PF11
PF12
PF13
PF14
PF15
COMP1_INP
G3IO4
EVENT
OUT
EVENT
OUT
A6
A7
A8
A9
G3IO5
G9IO3
G9IO4
G2IO3
EVENT
OUT
EVENT
OUT
EVENT
OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PG0
A10
A11
A12
A13
A14
A15
G2IO4
EVENT
OUT
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
G2IO5
G7IO5
G7IO6
G7IO7
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
EVENT
OUT
NE2
NE3
EVENT
OUT
EVENT
OUT
EVENT
OUT
NE4
A24
A25
EVENT
OUT
EVENT
OUT
Table 10. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
TIM2
AFIO2 AFIO3 AFIO4 AFIO5 AFIO6
AFIO7
AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14
AFIO15
Port
name
Alternate function
TIM9/
10/11
FSMC/
SDIO
SYSTEM
TIM3/4/5
I2C1/2 SPI1/2
SPI3 USART1/2/3UART4/5
USB
LCD
CPRI
SYSTEM
EVENT
OUT
PG15
PH0OSC
_IN
OSC_IN
PH1OSC
_OUT
OSC_OUT
PH2
A22
Memory mapping
STM32L151xD STM32L152xD
5
Memory mapping
Figure 8.
Memory map
0x40 02 67FF
DMA2
0x40 02 6400
DMA1
0x40 02 6000
reserved
0x40 02 4000
Flash Interface
0x40 02 3C00
RCC
0x40 02 3800
0xFFFF F FFF
reserved
0x40 02 3400
CRC
0x40 02 3000
reserved
7
0x40 02 2000
Port G
0x4002 1C00
0xE010 0 000
Cortex-M3 Internal
Peripherals
Port F
0x4002 1800
0xE000 0 000
Port H
0x4002 1400
Port E
0x4002 1000
Port D
0x4002 0C00
6
Port C
0x4002 0800
Port B
0x4002 0400
0xC000 000
0
0
Port A
0x40 02 0000
0x40 01 3C00
0x40 01 3800
reserved
USART1
reserved
5
0x40 01 3400
SPI1
0x40 01 3000
0x40 01 2C00
0x40 01 2800
FSMC registers
0xA000 000
SDIO
reserved
ADC
0x40 01 2400
4
reserved
TIM11
0x40 01 1400
0x40 01 1000
0x80 00 0000
TIM10
TIM9
EXTI
0x1 FF8 009F
0x1 FF8 0080
0x40 01 0C00
0x40 01 0800
Option Bytes
Bank 2
reserved
0x70 00 0000
3
0x40 01 0400
0x40 01 0000
0x1 FF8 001F
0x1 FF8 0000
Option Bytes
Bank 1
SYSCFG
reserved
FSMC
external memory
0x6 000 000
0
0x40 00 8000
0x40 00 7C00
0x4000 7800
reserved
COMP + RI
reserved
0x1 FF0 1FFF
0x1 FF0 0FFF
System memory
Bank 2
DAC1 & 2
PWR
2
0x40 00 7400
0x40 00 7000
System memory
Bank 1
reserved
Peripherals
0x1 FF0 0000
0x40 00 0000
0x40 00 6400
0x40 00 6000
512 byte USB
USB Registers
0x40 00 5C00
0x40 00 5800
0x40 00 5400
0x40 00 5000
0x40 00 4C00
0x40 00 4800
reserved
I2C2
I2C1
1
SRAM
0x200 0 0 000
UART5
0x0 808 2FFF
0x0 808 17FF
UART4
Data EEPROM
Bank 2
USART3
Non-
volatile
0
USART2
Data EEPROM
Bank 1
0x40 00 4400
0x40 00 4000
memory
reserved
SPI3
0x0 808 0000
0x0 805 FFFF
0x0 000 000
0
reserved
0x40 00 3C00
SPI2
0x40 00 3800
0x40 00 3400
Flash memory
Bank 2
reserved
0x0 802 FFFF
IWDG
0x40 00 3000
Flash memory
Bank 1
WWDG
0x40 00 2C00
0x40 00 2800
0x4000 2400
Reserve d
RTC
LCD
0x0 800 0000
0x0000 0000
Aliased to Flash or system
memory depending on
BOOT pins
reserved
TIM7
0x4000 1C00
0x4000 1400
TIM6
TIM5
0x4000 1000
0x40 00 0C00
TIM4
TIM3
TIM2
0x40 00 0800
0x40 00 0400
0x40 00 0000
MS18582V1
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to V
.
SS
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3Σ).
6.1.2
6.1.3
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3.6 V (for the
A
DD
1.65 V ≤ V ≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2Σ).
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
6.1.5
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9.
Pin loading conditions
Figure 10. Pin input voltage
STM32L15xxx pin
STM32L15xxx pin
C = 50 pF
V
IN
ai17852
ai17851
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53/140
Electrical characteristics
STM32L151xD STM32L152xD
6.1.6
Power supply scheme
Figure 11. Power supply scheme
Standby-power circuitry
(OSC32K,RTC,
Wake-up logic
RTC backup registers)
OUT
IN
IO
Logic
GP I/Os
Kernel logic
(CPU,
Digital
& Memories)
V
DD
V
DD1/2/.../N
Regulator
N × 100 nF
+ 1 × 4.7 µF
V
SS1/2/.../N
V
DD
V
DDA
V
REF
V
REF+
Analog:
RCs, PLL,
...
10 nF
+ 1 µF
10 nF
+ 1 µF
V
ADC
REF-
V
SSA
MS18291V2
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
I
DD
V
DD
V
DDA
ai14126b
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External main supply voltage
VDD–VSS
–0.3
4.0
(1)
(including VDDA and VDD
)
V
Input voltage on five-volt tolerant pin
Input voltage on any other pin
VSS − 0.3
VSS − 0.3
VDD+4.0
4.0
(2)
VIN
|ΔVDDx
|
Variations between different VDD power pins
Variations between all different ground pins
50
mV
|VSSX − VSS
|
50
Electrostatic discharge voltage
(human body model)
VESD(HBM)
see Section 6.3.11
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values.
Table 12. Current characteristics
Symbol
Ratings
Max.
Unit
IVDD
IVSS
Total current into VDD/VDDA power lines (source)(1)
Total current out of VSS ground lines (sink)(1)
Output current sunk by any I/O and control pin
Output current sourced by any I/O and control pin
Injected current on five-volt tolerant I/O(3)
80
80
25
IIO
- 25
+0 /-5
5
mA
(2)
IINJ(PIN)
Injected current on any other pin (4)
ΣIINJ(PIN)
Total injected current (sum of all I/O and control pins)(5)
25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.19.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 11 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Doc ID 022027 Rev 6
55/140
Electrical characteristics
Table 13. Thermal characteristics
STM32L151xD STM32L152xD
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
–65 to +150
150
°C
°C
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Table 14. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
fPCLK1
fPCLK2
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
0
0
32
32
32
3.6
MHz
0
BOR detector disabled
1.65
BOR detector enabled,
at power on
1.8
1.65
1.65
1.8
3.6
3.6
3.6
3.6
333
VDD
Standard operating voltage
V
BOR detector disabled,
after power on
Analog operating voltage
(ADC and DAC not used)
Must be the same voltage
(1)
VDDA
V
(2)
as VDD
Analog operating voltage
(ADC or DAC used)
Power dissipation at
TA = 85 °C(3)
PD
UFBGA132 package
mW
Maximum power dissipation –40
85
TA
TJ
Temperature range
°C
°C
Low power dissipation(4)
–40
–40
105
105
Junction temperature range
-40 °C ≤ TA ≤ 105 °C
1. When the ADC is used, refer to Table 64: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 78: Thermal
characteristics on page 134).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max
(see Table 78: Thermal characteristics on page 134).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 14.
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
Table 15. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
BOR detector enabled
BOR detector disabled
BOR detector enabled
BOR detector disabled
Min
0
Typ
Max Unit
∞
VDD rise time rate
0
1000
µs/V
∞
(1)
tVDD
20
0
V
DD fall time rate
1000
V
DD rising, BOR enabled
2
3.3
ms
1.6
(1)
TRSTTEMPO
Reset temporization
VDD rising, BOR disabled(2)
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
0.4
1
0.7
1.5
1.5
1.7
1.65
1.65
1.74
1.8
Power on/power down reset
threshold
VPOR/PDR
VBOR0
VBOR1
VBOR2
VBOR3
VBOR4
VPVD0
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
1.3
1.67
Brown-out reset threshold 0
Brown-out reset threshold 1
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
1.69 1.76
1.87 1.93 1.97
1.96 2.03 2.07
2.22 2.30 2.35
2.31 2.41 2.44
2.45 2.55 2.60
2.54 2.66
2.7
2.68
2.78
1.8
2.8
2.9
2.85
2.95
1.85 1.88
Programmable voltage detector
threshold 0
V
1.88 1.94 1.99
1.98 2.04 2.09
2.08 2.14 2.18
2.20 2.24 2.28
2.28 2.34 2.38
2.39 2.44 2.48
2.47 2.54 2.58
2.57 2.64 2.69
2.68 2.74 2.79
2.77 2.83 2.88
2.87 2.94 2.99
2.97 3.05 3.09
3.08 3.15 3.20
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
Doc ID 022027 Rev 6
57/140
Electrical characteristics
STM32L151xD STM32L152xD
Table 15. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
BOR0 threshold
Min
Typ
Max Unit
-
40
-
-
Vhyst
Hysteresis voltage
mV
All BOR and PVD thresholds
excepting BOR0
-
100
1. Guaranteed by characterisation, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
6.3.3
Embedded internal reference voltage
The parameters given in Table 16 are based on characterization results, unless otherwise
specified.
Table 16. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
(1)
VREFINT out
Internal reference voltage
– 40 °C < TJ < +105 °C 1.202 1.224 1.242
V
Internal reference current
consumption
IREFINT
-
-
1.4
2
2.3
3
µA
ms
V
TVREFINT
Internal reference startup time
VDDA and VREF+ voltage during
VVREF_MEAS
2.99
3
3.01
VREFINT factory measure
Including uncertainties
due to ADC and
VDDA/VREF+ values
Accuracy of factory-measured
VREF value(2)
AVREF_MEAS
-
-
5
mV
–40 °C < TJ < +105 °C
0 °C < TJ < +50 °C
-
-
-
-
20
-
50
20
(3)
TCoeff
Temperature coefficient
ppm/°C
(3)
ACoeff
Long-term stability
Voltage coefficient
1000 hours, T= 25 °C
3.0 V < VDDA < 3.6 V
-
1000
2000
ppm
VDDCoeff(3)
-
ppm/V
ADC sampling time when
reading the internal reference
voltage
(3)(4)
TS_vrefint
-
5
10
µs
Startup time of reference voltage
buffer for ADC
(3)
TADC_BUF
-
-
-
10
25
µs
Consumption of reference
voltage buffer for ADC
(3)
IBUF_ADC
13.5
µA
(3)
VREF_OUT output current(5)
VREF_OUT output load
IVREF_OUT
-
-
-
-
1
µA
pF
(3)
CVREF_OUT
50
Consumption of reference
voltage buffer for VREF_OUT
and COMP
(3)
ILPBUF
-
730
1200
nA
(3)
VREFINT_DIV1
VREFINT_DIV2
VREFINT_DIV3
1/4 reference voltage
1/2 reference voltage
3/4 reference voltage
24
49
74
25
50
75
26
51
76
%
VREFINT
(3)
(3)
1. Tested in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
5. To guarantee less than 1% VREF_OUT deviation.
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Electrical characteristics
STM32L151xD STM32L152xD
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code. The current consumption is measured as described in Figure 12: Current
consumption measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●
●
●
●
V
= 3.6 V
DD
All I/O pins are in input mode with a static value at V or V (no load)
DD
SS
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted depending on f
range
frequency and voltage
HCLK
●
Prefetch and 64-bit access are enabled in configurations with 1 wait state
The parameters given in Table 17, Table 14 and Table 15 are derived from tests performed
under ambient temperature and V supply voltage conditions summarized in Table 14.
DD
Table 17. Current consumption in Run mode, code with data processing running from Flash
Max(1)
Symbol Parameter
Conditions
fHCLK
Typ
Unit
55 °C 85 °C 105 °C
1 MHz
2 MHz
360
620
500
750
500
750
500
750
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
µA
4 MHz 1070 1200 1200 1200
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
4 MHz 1.30
8 MHz 2.4
16 MHz 4.6
8 MHz 2.9
1.6
2.9
5.2
3.5
6.5
12
1.6
2.9
5.2
3.5
6.5
12
1.6
2.9
5.2
3.5
6.5
12
Range 2,
VCORE=1.5 V
above 16 MHz (PLL VOS[1:0] = 10
ON)(2)
Supply
Range 1,
IDD
current in
Run mode,
code
executed
from Flash
VCORE=1.8 V
16 MHz 5.7
32 MHz 10.4
(Run
from
Flash)
VOS[1:0] = 01
Range 2,
mA
VCORE=1.5 V
16 MHz 4.5
5.2
5.2
5.2
VOS[1:0] = 10
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 10.9 12.3 12.3
12.3
MSI clock, 65 kHz
65 kHz 0.05 0.079 0.092 0.13
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
524 kHz 0.17
4.2 MHz 1.0
0.2
1.1
0.21
1.1
0.25
1.2
VOS[1:0] = 11
MSI clock, 4.2 MHz
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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STM32L151xD STM32L152xD
Electrical characteristics
Table 18. Current consumption in Run mode, code with data processing running from RAM
Max(1)
Symbol
Parameter
Conditions
fHCLK
Typ
Unit
55 °C 85 °C 105 °C
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
16 MHz
8 MHz
16 MHz
32 MHz
310
590
470
780
470
780
470
780
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
µA
1030 1200 1200 1200(3)
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
1.2
2.3
4.3
2.7
5.0
9.8
1.5
3
1.5
3
1.5
3
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
5
5
5
3.5
3.5
3.5
5.55
10.9
Supply current
in Run mode,
code executed
from RAM,
Flash switched
off
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
IDD
5.55 5.55
10.9 10.9
(Run
from
RAM)
mA
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz
4.3
4.8
4.8
4.8
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 10.1 11.7 11.7
11.7
MSI clock, 65 kHz
65 kHz
40
48.5
175
63
100
215
Range 3,
MSI clock, 524 kHz VCORE=1.2 V
524 kHz 148
183
µA
VOS[1:0] = 11
MSI clock, 4.2 MHz
4.2 MHz 990 1032 1034
1100
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Tested in production.
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Electrical characteristics
STM32L151xD STM32L152xD
Max(1)
Table 19. Current consumption in Sleep mode
Symbol Parameter
Conditions
fHCLK
Typ
Unit
55 °C 85 °C 105 °C
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
180
225
300
360
570
220
300
380
500
700
220
300
380
500
700
220
300
380(3)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
500
Range 2,
VCORE=1.5 V
700
above 16 MHz (PLL VOS[1:0] = 10
Supply
current in
Sleep
mode,
code
executed
from RAM,
Flash
switched
OFF
16 MHz 990 1100 1100 1100
8 MHz 675 800 800 800
ON)(2)
Range 1,
VCORE=1.8 V
16 MHz 1150 1250 1250 1250
32 MHz 2300 2700 2700 2700
VOS[1:0] = 01
µA
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 1025 1100 1100 1100
32 MHz 2460 2700 2700 2700
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
MSI clock, 65 kHz
MSI clock, 524 kHz
MSI clock, 4.2 MHz
65 kHz
30
36
46
72
Range 3,
IDD
(Sleep)
VCORE=1.2 V
524 kHz 50
4.2 MHz 210
58
67
92
VOS[1:0] = 11
245
250
300
380
500
700
251
250
300
380
500
700
273
250
300
380
500
700
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
190
235
315
390
600
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
Range 2,
VCORE=1.5 V
Supply
current in
Sleep
above 16 MHz (PLL VOS[1:0] = 10
16 MHz 1000 1120 1120 1120
8 MHz 690 800 800 800
ON)(2)
Range 1,
mode,
µA
V
CORE=1.8 V
16 MHz 1160 1300 1300 1300
32 MHz 2310 2700 2700 2700
code
VOS[1:0] = 01
executed
from Flash
Range 2,
V
CORE=1.5 V
16 MHz 1040 1160 1160 1160
32 MHz 2500 2800 2800 2800
VOS[1:0] = 10
HSI clock source
(16 MHz)
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
Supply
current in
Sleep
MSI clock, 65 kHz
MSI clock, 524 kHz
65 kHz
42
50
72
60
82
90
524 kHz 63
110
Range 3,
IDD
mode,
VCORE=1.2V
VOS[1:0] = 11
µA
(Sleep)
code
MSI clock, 4.2 MHz
4.2 MHz 230
263
265
290
executed
from Flash
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
3. Tested in production.
Table 20. Current consumption in Low power run mode
Max
Symbol
Parameter
Conditions
Typ
Unit
(1)
TA = -40 °C to 25 °C
TA = 85 °C
11
26
53
18
33
60
36
39
50
78
36
53
81
44
61
89
64
68
80
101
14
32
MSI clock, 65 kHz
fHCLK = 32 kHz
All
TA = 105 °C
72
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
TA =-40 °C to 25 °C
TA = 85 °C
21
MSI clock, 65 kHz
fHCLK = 65 kHz
40
TA = 105 °C
78
TA = -40 °C to 25 °C
TA = 55 °C
41
44
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = 85 °C
58
Supply
TA = 105 °C
95
IDD
current in
(LP Run) Low power
run mode
TA = -40 °C to 25 °C
TA = 85 °C
40.5
60
MSI clock, 65 kHz
fHCLK = 32 kHz
µA
TA = 105 °C
100
49
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
TA = -40 °C to 25 °C
TA = 85 °C
MSI clock, 65 kHz
fHCLK = 65 kHz
67
TA = 105 °C
107
71
TA = -40 °C to 25 °C
TA = 55 °C
73
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = 85 °C
88
TA = 105 °C
110
Max allowed
IDD max current in
(LP Run) Low power
run mode
VDD from
1.65 V to
3.6 V
-
200
1. Based on characterization, not tested in production, unless otherwise specified.
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Electrical characteristics
STM32L151xD STM32L152xD
Table 21. Current consumption in Low power sleep mode
Max
Symbol Parameter
Conditions
Typ
Unit
(1)
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
TA = -40 °C to 25 °C 4.4
TA = -40 °C to 25 °C 18
-
21
27
43
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
TA = 85 °C
24
35
All
TA = 105 °C
peripherals
OFF, VDD
TA = -40 °C to 25 °C 18.6 21
MSI clock, 65 kHz
from1.65 V fHCLK = 65 kHz,
TA = 85 °C
24.5 28
to 3.6 V
Flash ON
TA = 105 °C
35
42
25
TA = -40 °C to 25 °C 22
MSI clock, 131 kHz
fHCLK = 131 kHz,
Flash ON
Supply
TA = 55 °C
TA = 85 °C
TA = 105 °C
23.5 26
28.5 31
current in
Low power
sleep
IDD
(LP Sleep)
39
45
mode
TA = -40 °C to 25 °C 18 20.5
µA
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = 85 °C
24
35
27
43
TA = 105 °C
TIM9 and
USART1
enabled,
Flash ON,
VDD from
1.65 V to
3.6 V
TA = -40 °C to 25 °C 18.6 21
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = 85 °C
24.5 28
TA = 105 °C
35
42
25
TA = -40 °C to 25 °C 22
TA = 55 °C
TA = 85 °C
TA = 105 °C
23.5 26
28.5 31
MSI clock, 131 kHz
fHCLK = 131 kHz
39
45
Max
allowed
current in
(LP Sleep) Low power
VDD from
1.65 V to
3.6 V
IDD max
-
200
Sleep
mode
1. Based on characterization, not tested in production, unless otherwise specified.
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Electrical characteristics
Table 22. Typical and maximum current consumptions in Stop mode
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
TA = -40°C to 25°C
VDD = 1.8 V
1.5
TA = -40°C to 25°C 1.7
4
6
LCD OFF
TA = 55°C
TA= 85°C
TA = 105°C
2.4
5.4
10
23
6
11.0
RTC clocked by LSI or
LSE external clock
(32.768kHz), regulator
in LP mode,HSI and
HSE OFF (no
TA = -40°C to 25°C 3.8
LCD ON
(static
TA = 55°C
TA= 85°C
TA = 105°C
4.4
7.4
7
duty)(2)
12
27
10
11
16
44
-
independent watchdog)
14.4
TA = -40°C to 25°C 7.8
LCD ON
(1/8
TA = 55°C
TA= 85°C
TA = 105°C
8.3
duty)(3)
11.4
20.5
TA = -40°C to 25°C 2.1
IDD (Stop Supply current in Stop
with RTC) mode with RTC enabled
TA = 55°C
TA= 85°C
TA = 105°C
2.8
3.8
-
µA
LCD OFF
-
11.1
-
TA = -40°C to 25°C 4.2
-
LCD ON
(static
TA = 55°C
TA= 85°C
TA = 105°C
4.8
7.9
-
duty)(2)
RTC clocked by LSE
external quartz
(32.768kHz), regulator
in LP mode, HSI and
HSE OFF (no
-
15.0
-
TA = -40°C to 25°C 8.2
-
LCD ON
(1/8
TA = 55°C
TA= 85°C
TA = 105°C
8.7
-
independent
watchdog(4)
duty)(3)
11.9
21.4
-
-
TA = -40°C to 25°C
VDD = 1.8V
1.6
1.9
2.1
-
-
-
TA = -40°C to 25°C
VDD = 3.0V
LCD OFF
TA = -40°C to 25°C
VDD = 3.6V
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Electrical characteristics
STM32L151xD STM32L152xD
Table 22. Typical and maximum current consumptions in Stop mode (continued)
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
Regulator in LP mode, HSI and
HSE OFF, independent watchdog TA = -40°C to 25°C 1.6
and LSI enabled
2.2
Supply current in Stop
mode (RTC disabled)
TA = -40°C to 25°C 0.65
1
3
9
IDD (Stop)
µA
Regulator in LP mode, LSI, HSI
and HSE OFF (no independent
watchdog)
TA = 55°C
TA= 85°C
TA = 105°C
1.3
4.4
10.0 22(5)
MSI = 4.2 MHz
MSI = 1.05 MHz
MSI = 65 kHz(6)
2
-
-
-
IDD
(WU from
Stop)
Supply current during
wakeup from Stop mode
TA = -40°C to 25°C 1.45
1.45
mA
1. Based on characterization, not tested in production, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. Tested in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
Table 23. Typical and maximum current consumptions in Standby mode
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
TA = -40 °C to 25 °C
TA = 55 °C
1.3
1.9
2.2
4
1.44
RTC clocked by LSI (no
independent watchdog)
TA= 85 °C
1.90
IDD
(Standby
with RTC)
TA = 105 °C
3.05 8.3(2)
Supply current in Standby
mode with RTC enabled
TA = -40 °C to 25 °C
TA = 55 °C
1.7
-
-
-
-
RTC clocked by LSE
external quartz(no
1.84
2.33
3.59
independent watchdog)(3)
TA= 85 °C
TA = 105 °C
µA
Independent watchdog and
LSI enabled
TA = -40 °C to 25 °C
1
1.7
TA = -40 °C to 25 °C
TA = 55 °C
0.35
0.47
1.2
0.6
0.9
IDD
(Standby)
Supply current in Standby
mode (RTC disabled)
Independent watchdog and
LSI OFF
TA = 85 °C
2.75
7(2)
TA = 105 °C
2.9
IDD
(WU from
Standby)
Supply current during wakeup
time from Standby mode
TA = -40 °C to 25 °C
1
-
1. Based on characterization, not tested in production, unless otherwise specified
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STM32L151xD STM32L152xD
Electrical characteristics
2. Tested in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
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Electrical characteristics
STM32L151xD STM32L152xD
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
●
Sleep mode: the clock source is the clock that was set before entering Sleep mode
●
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
●
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and V supply
DD
voltage conditions summarized in Table 14.
Table 24. Typical and maximum timings in Low power modes
Max(1)
Symbol
Parameter
Conditions
Typ
Unit
tWUSLEEP
Wakeup from Sleep mode fHCLK = 32 MHz
0.4
-
f
HCLK = 262 kHz
46
46
-
-
Wakeup from Low power
sleep mode
fHCLK = 262 kHz
Flash enabled
tWUSLEEP_LP
fHCLK = 262 kHz
Flash switched OFF
Wakeup from Stop mode,
regulator in Run mode
f
HCLK = fMSI = 4.2 MHz
HCLK = fMSI = 4.2 MHz
8.2
7.7
8.2
-
f
8.9
13.1
Voltage range 1 and 2
HCLK = fMSI = 4.2 MHz
Voltage range 3
HCLK = fMSI = 2.1 MHz
f
µs
tWUSTOP
f
10.2 13.4
Wakeup from Stop mode,
regulator in low power mode
fHCLK = fMSI = 1.05 MHz
fHCLK = fMSI = 524 kHz
fHCLK = fMSI = 262 kHz
fHCLK = fMSI = 131 kHz
fHCLK = MSI = 65 kHz
16
31
20
37
57
66
112
221
123
236
Wakeup from Standby mode
FWU bit = 1
f
HCLK = MSI = 2.1 MHz
58
104
tWUSTDBY
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
2.6
3.25
ms
1. Based on characterization, not tested in production, unless otherwise specified
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Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
●
●
●
all I/O pins are in input mode with a static value at V or V (no load)
DD SS
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
–
with all peripherals clocked off
with only one peripheral clocked on
(1)
Table 25. Peripheral current consumption
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
Range 2,
Range 3,
VCORE
1.8 V
=
VCORE
1.5 V
=
VCORE
1.2 V
=
Low power
sleep and
run
Peripheral
Unit
VOS[1:0] = VOS[1:0] = VOS[1:0] =
01
10
11
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
LCD
13
12
12
16
4
11
10
10
13
4
9
9
11
11
11
14
4
9
11
4
4
4
4
4
4
3
3
4
WWDG
3
2.5
7
2.5
9
3
SPI2
8
7.5
6
SPI3
7
6
7
µA/MHz
APB1
(fHCLK
)
USART2
USART3
USART4
USART5
I2C1
8
7
7
7
8
7
7
7
8
7
7
7
8
7
7
7
8
7
6
7
I2C2
7
6
5
6
USB
15
3
7
7
7
PWR
3
3
3
DAC
6
5
4.5
3.5
5
COMP
4
3.5
4
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Electrical characteristics
STM32L151xD STM32L152xD
(1)
Table 25. Peripheral current consumption (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
Range 2,
VCORE
1.5 V
Range 3,
VCORE
1.2 V
VCORE
=
=
=
Low power
sleep and
run
Peripheral
Unit
1.8 V
VOS[1:0] = VOS[1:0] = VOS[1:0] =
01
10
11
SYSCFG &
RI
3
2
2
3
TIM9
8
6
7
5
6
5
7
5
5
8
6
4
7
6
6
6
6
6
6
6
2
1
TIM10
TIM11
ADC(2)
SDIO
6
5
5
APB2
10
20
4
8
7
6
5
SPI1
4
4
USART1
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
CRC
8
7
6
7
6
5
7
6
5
µA/MHz
7
6
5
(fHCLK
)
7
6
5
7
6
5
7
6
5
AHB
7
6
5
2
2
1
0.5
26
18
16
15
279
0.5
26
15
14
12
221
0.5
29
13
12
10
219
(3)
FLASH
DMA1
DMA2
FSMC
-
18
16
12
All enabled
215
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Electrical characteristics
(1)
Table 25. Peripheral current consumption (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
Range 2,
VCORE
1.5 V
Range 3,
VCORE
1.2 V
VCORE
=
=
=
Low power
sleep and
run
Peripheral
Unit
1.8 V
VOS[1:0] = VOS[1:0] = VOS[1:0] =
01 10 11
IDD (RTC)
IDD (LCD)
0.4
3.1
1450
340
0.16
2
(4)
IDD (ADC)
(5)
IDD (DAC)
IDD (COMP1)
µA
Slow mode
IDD (COMP2)
Fast mode
5
(6)
IDD (PVD / BOR)
IDD (IWDG)
2.6
0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. In low power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
External clock source characteristics
High-speed external user clock generated from an external source
(1)
Table 26. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
1
8
32
MHz
VHSEH
VHSEL
tw(HSE)
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
0.7VDD
VSS
-
-
VDD
V
0.3VDD
OSC_IN high or low time
OSC_IN rise or fall time
12
-
-
tw(HSE)
ns
tr(HSE)
tf(HSE)
-
-
-
20
-
Cin(HSE) OSC_IN input capacitance
2.6
pF
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Electrical characteristics
STM32L151xD STM32L152xD
(1)
Table 26. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DuCy(HSE) Duty cycle
45
-
-
-
55
1
%
IL
OSC_IN Input leakage current
VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design, not tested in production.
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Electrical characteristics
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
(1)
Table 27. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fLSE_ext
1
32.768
1000
kHz
OSC32_IN input pin high level
voltage
VLSEH
VLSEL
tw(LSE)
0.7VDD
VSS
465
-
-
-
-
-
VDD
0.3VDD
-
V
OSC32_IN input pin low level
voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
tw(LSE)
ns
tr(LSE)
tf(LSE)
10
CIN(LSE) OSC32_IN input capacitance
DuCy(LSE) Duty cycle
-
45
-
0.6
-
pF
%
-
-
55
1
IL
OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD
µA
1. Guaranteed by design, not tested in production
Figure 13. Low-speed external clock source AC timing diagram
V
LSEH
90%
10%
V
LSEL
t
t
t
W(LSE)
t
t
W(LSE)
r(LSE)
f(LSE)
T
LSE
f
LSE_ext
EXTERNAL
I
L
OSC32_IN
CLOCK SOURCE
STM32Lxx
ai18233
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Electrical characteristics
STM32L151xD STM32L152xD
Figure 14. High-speed external clock source AC timing diagram
V
HSEH
90%
10%
V
HSEL
t
t
t
W(HSE)
t
t
W(HSE)
r(HSE)
f(HSE)
T
HSE
f
HSE_ext
EXTERNAL
I
L
OSC _IN
CLOCK SOURCE
STM32Lxx
ai18232
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 28. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
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Electrical characteristics
(1)(2)
Table 28. HSE 1-24 MHz oscillator characteristics
Symbol
Parameter
Conditions
Min Typ
Max
Unit
fOSC_IN Oscillator frequency
1
-
24
-
MHz
RF
C
Feedback resistor
200
20
kΩ
Recommended load
capacitance versus
equivalent serial resistance
RS = 30 Ω
-
-
pF
of the crystal (RS)(3)
V
DD= 3.3 V, VIN = VSS
with 30 pF load
IHSE
IDD(HSE)
gm
HSE driving current
-
-
-
-
3
mA
C = 20 pF
fOSC = 16 MHz
2.5 (startup)
0.7 (stabilized)
HSE oscillator power
consumption
mA
C = 10 pF
fOSC = 16 MHz
2.5 (startup)
0.46 (stabilized)
-
-
mA
/V
Oscillator transconductance
Startup time
Startup
3.5
-
-
-
-
tSU(HSE)
VDD is stabilized
1
ms
(4)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
For C and C , it is recommended to use high-quality external ceramic capacitors in the
L1
L2
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 15). C and C are usually the
L1
L2
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C and C . PCB and MCU pin capacitance must be included (10 pF
L1
L2
can be used as a rough estimate of the combined pin and board capacitance) when sizing
and C . Refer to the application note AN2867 “Oscillator design guide for ST
C
L1
L2
microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 15. HSE oscillator circuit diagram
STM32L151xD STM32L152xD
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSC_IN
C
m
g
m
Resonator
Consumption
control
Resonator
STM32
ai18235
OSC_OUT
C
L2
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 29. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
(1)
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Low speed external oscillator
frequency
fLSE
RF
C(2)
ILSE
-
-
32.768
1.2
-
-
kHz
Feedback resistor
MΩ
Recommended load capacitance
versus equivalent serial
RS = 30 kΩ
-
8
-
pF
µA
resistance of the crystal (RS)(3)
LSE driving current
VDD = 3.3 V, VIN = VSS
VDD = 1.8 V
-
-
-
1.1
450
600
750
-
-
-
-
-
LSE oscillator current
consumption
IDD (LSE)
VDD = 3.0 V
-
nA
VDD = 3.6V
-
gm
Oscillator transconductance
Startup time
3
-
µA/V
s
(4)
tSU(LSE)
VDD is stabilized
1
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
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Electrical characteristics
Note:
For C and C , it is recommended to use high-quality ceramic capacitors in the 5 pF to
L1
L2
15 pF range selected to match the requirements of the crystal or resonator (see Figure 16).
and C are usually the same size. The crystal manufacturer typically specifies a load
C
L1
L2,
capacitance which is the series combination of C and C .
L1
L2
Load capacitance C has the following formula: C = C x C / (C + C ) + C where
L
L
L1
L2
L1
L2
stray
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of C and C (15 pF) it is strongly recommended
L1
L2
to use a resonator with a load capacitance C ≤ 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C = 6 pF and C
= 2 pF,
stray
L
then C = C = 8 pF.
L1
L2
Figure 16. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C
L1
f
OSC32_IN
LSE
Bias
controlled
gain
32.768 kHz
resonator
R
F
STM32L15xxx
OSC32_OUT
C
L2
ai17853
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Electrical characteristics
STM32L151xD STM32L152xD
6.3.6
Internal clock source characteristics
The parameters given in Table 30 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 14.
DD
High-speed internal (HSI) RC oscillator
Table 30. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ Max Unit
fHSI
VDD = 3.0 V
-
-
16
-
MHz
%
Trimming code is not a multiple of 16
Trimming code is a multiple of 16
VDDA = 3.0 V, TA = 25 °C
0.4 0.7
HSI user-trimmed
resolution
(1)(2)
TRIM
-
-
-
-
-
-
-
1.5
%
-1(3)
-1.5
-2
1(3)
1.5
2
%
VDDA = 3.0 V, TA = 0 to 55 °C
VDDA = 3.0 V, TA = -10 to 70 °C
%
%
Accuracy of the
factory-calibrated
HSI oscillator
(2)
ACCHSI
V
DDA = 3.0 V, TA = -10 to 85 °C
VDDA = 3.0 V, TA = -10 to 105 °C
DDA = 1.65 V to 3.6 V
-2.5
-4
2
%
2
%
V
-4
-
-
3
6
%
µs
µA
TA = -40 to 105 °C
HSI oscillator
startup time
(2)
tSU(HSI)
3.7
100
HSI oscillator
power consumption
(2)
IDD(HSI)
-
140
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Based on characterization, not tested in production.
3. Tested in production.
Low-speed internal (LSI) RC oscillator
Table 31. LSI oscillator characteristics
Symbol
Parameter
LSI frequency
Min
Typ
Max
Unit
(1)
fLSI
26
38
56
kHz
%
LSI oscillator frequency drift
0°C ≤ TA ≤ 85°C
(2)
DLSI
-10
-
4
(3)
tsu(LSI)
LSI oscillator startup time
-
-
-
200
510
µs
(3)
IDD(LSI)
LSI oscillator power consumption
400
nA
1. Tested in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
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Electrical characteristics
Multi-speed internal (MSI) RC oscillator
Table 32. MSI oscillator characteristics
Symbol
Parameter
Condition
Typ Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
65.5
131
262
524
1.05
2.1
-
-
-
-
-
-
-
-
kHz
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
fMSI
MHz
4.2
ACCMSI
Frequency error after factory calibration
0.5
%
%
MSI oscillator frequency drift
0 °C ≤ TA ≤ 85 °C
(1)
DTEMP(MSI)
3
-
-
MSI oscillator frequency drift
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
(1)
DVOLT(MSI)
2.5 %/V
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
MSI range 6
0.75
1
-
-
-
1.5
2.5
4.5
8
(2)
IDD(MSI)
MSI oscillator power consumption
-
-
-
-
µA
15
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Electrical characteristics
Table 32. MSI oscillator characteristics (continued)
STM32L151xD STM32L152xD
Symbol
Parameter
Condition
Typ Max Unit
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
30
20
15
10
6
-
-
-
-
-
-
tSU(MSI)
MSI oscillator startup time
5
MSI range 6,
Voltage range 1
and 2
3.5
5
-
-
MSI range 6,
Voltage range 3
µs
MSI range 0
MSI range 1
MSI range 2
MSI range 3
MSI range 4
MSI range 5
-
-
-
-
-
-
40
20
10
4
2.5
2
(2)
tSTAB(MSI)
MSI oscillator stabilization time
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
-
-
3
4
6
Any range to
range 5
fOVER(MSI)
MSI oscillator frequency overshoot
MHz
Any range to
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Based on characterization, not tested in production.
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Electrical characteristics
6.3.7
PLL characteristics
The parameters given in Table 33 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 14.
DD
Table 33. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
45
2
-
-
-
24
55
32
MHz
%
fPLL_IN
fPLL_OUT
tLOCK
PLL input clock duty cycle
PLL output clock
MHz
Worst case PLL lock time
PLL input = 2 MHz
-
100
130
µs
PLL VCO = 96 MHz
Jitter
Cycle-to-cycle jitter
-
-
-
600
450
150
ps
IDDA(PLL)
IDD(PLL)
Current consumption on VDDA
Current consumption on VDD
220
120
µA
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
6.3.8
Memory characteristics
The characteristics are given at T = -40 to 105 °C unless otherwise specified.
A
RAM memory
Table 34. RAM and hardware registers
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VRM Data retention mode(1)
STOP mode (or RESET)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Electrical characteristics
STM32L151xD STM32L152xD
Flash memory and data EEPROM
Table 35. Flash memory and data EEPROM characteristics
Symbol
Parameter
Conditions
Min
Typ
Max(1) Unit
Operating voltage
VDD
1.65
-
3.6
V
Read / Write / Erase
Erasing
-
-
3.28
3.28
3.94
3.94
Programming time for
word or half-page
tprog
ms
Programming
Average current during
the whole programming /
erase operation
-
-
600
1.5
900
2.5
µA
IDD
TA = 25 °C, VDD = 3.6 V
Maximum current (peak)
during the whole
programming / erase
operation
mA
1. Guaranteed by design, not tested in production.
Table 36. Flash memory and data EEPROM endurance and retention
Value
Symbol
Parameter
Conditions
Unit
Min(1) Typ Max
Cycling (erase / write)
Program memory
-
-
-
-
-
-
-
-
-
-
-
-
10
300
30
TA = -40°C to
(2)
NCYC
kcycles
105 °C
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
TRET = +85 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
30
(2)
tRET
years
Data retention (program memory) after
10 kcycles at TA = 105 °C
10
TRET = +105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
10
1. Based on characterization not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
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Electrical characteristics
6.3.9
FSMC characteristics
Asynchronous waveforms and timings
Figure 17 through Figure 20 represent asynchronous waveforms and Table 37 through
Table 40 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
AddressSetupTime = 0 (AddressSetupTime = 1, for asynchronous multiplexed modes)
AddressHoldTime = 1
DataSetupTime = 1
Figure 17. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
v(NOE_NE)
t
t
h(NE_NOE)
w(NOE)
FSMC_NOE
FSMC_NWE
tv(A_NE)
t
h(A_NOE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FSMC_NADV
MS18586V1
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
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Electrical characteristics
STM32L151xD STM32L152xD
(1)
Table 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
ns
THCLK -2
THCLK
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
0
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
THCLK
THCLK - 1
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
0
-
-
4
th(A_NOE)
tv(BL_NE)
th(BL_NOE)
THCLK + 1.5
-
-
0.5
2*THCLK - 0.5
-
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE) Data hold time after FSMC_NOE high
THCLK
-
THCLK
-
0
0
-
-
th(Data_NE)
Data hold time after FSMC_NEx high
-
2
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tw(NADV)
FSMC_NADV low time
-
THCLK
1. CL = 30 pF.
Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
FSMC_NADV(1)
t
v(NADV_NE)
t
w(NADV)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
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Electrical characteristics
(1)
Table 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
2*THCLK -3
2*THCLK +2 ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
0.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
THCLK - 2
THCLK + 3
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
THCLK - 2.5
-
-
0
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
THCLK - 2.5
-
-
0
THCLK - 4
-
-
THCLK
-
th(Data_NWE) Data hold time after FSMC_NWE high
1. CL = 30 pF.
THCLK - 2.5
Figure 19. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
t
h(NE_NOE)
v(NOE_NE)
FSMC_NOE
t
w(NOE)
FSMC_NWE
t
tv(A_NE)
h(A_NOE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
NBL
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
su(Data_NOE)
Address
Data
FSMC_AD[15:0]
FSMC_NADV
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
ai14892b
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Electrical characteristics
STM32L151xD STM32L152xD
(1)
Table 39. Asynchronous multiplexed PSRAM/NOR read timings
Symbol Parameter Min
tw(NE) FSMC_NE low time 3*THCLK - 1.5 3*THCLK + 1
tv(NOE_NE) 2*THCLK - 1 2*THCLK
tw(NOE) THCLK - 0.5 THCLK + 0.5
th(NE_NOE)
tv(A_NE)
Max
Unit
ns
ns
ns
ns
ns
ns
ns
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
0
-
-
1.5
5
2
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tw(NADV)
FSMC_NADV low time
THCLK - 0.5
THCLK
FSMC_AD(address) valid hold time after
FSMC_NADV high
th(AD_NADV)
THCLK - 6
-
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
2*THCLK - 1
-
-
ns
ns
ns
ns
ns
ns
ns
1.5
-
THCLK
THCLK
0
0
-
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
-
th(Data_NE)
Data hold time after FSMC_NEx high
-
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 30 pF.
0
-
Figure 20. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
FSMC_NWE
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
FSMC_AD[15:0]
NBL
t
t
h(Data_NWE)
t
v(A_NE)
v(Data_NADV)
Address
Data
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
FSMC_NADV
ai14891B
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STM32L151xD STM32L152xD
Electrical characteristics
(1)
Table 40. Asynchronous multiplexed PSRAM/NOR write timings
Symbol Parameter Min
tw(NE) FSMC_NE low time 4*THCLK - 3 4*THCLK + 2 ns
tv(NWE_NE) THCLK THCLK + 1 ns
tw(NWE) 2*THCLK - 2 2*THCLK + 4 ns
th(NE_NWE)
tv(A_NE)
Max
Unit
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
THCLK - 2.5
-
ns
ns
ns
ns
-
6
2
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
1.5
tw(NADV)
FSMC_NADV low time
THCLK - 4
THCLK + 4
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
THCLK - 5
-
ns
th(A_NWE)
th(BL_NWE)
tv(BL_NE)
Address hold time after FSMC_NWE high
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
THCLK - 2.5
-
ns
ns
ns
ns
ns
THCLK - 3
-
-
0.5
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE) Data hold time after FSMC_NWE high
1. CL = 30 pF.
-
THCLK + 6
-
THCLK - 2.5
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Electrical characteristics
STM32L151xD STM32L152xD
Synchronous waveforms and timings
Figure 21 through Figure 24 represent synchronous waveforms and Table 42 through
Table 44 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
●
●
●
●
●
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1;
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 21. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
t
d(CLKL-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:16]
t
t
d(CLKL-NOEH)
d(CLKL-NOEL)
FSMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FSMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
ai14893g
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STM32L151xD STM32L152xD
Electrical characteristics
(1)
Table 41. Synchronous multiplexed NOR/PSRAM read timings
Symbol
tw(CLK)
td(CLKL-NExL)
td(CLKL-NExH)
Parameter
Min
Max
Unit
2*THCLK
0.5
-
FSMC_CLK period
-
0
-
ns
ns
ns
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
-
THCLK
1.5
+
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NADV low
-
3.5
-
3
-
ns
ns
ns
ns
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NOE low
0
-
td(CLKL-AIV)
0
td(CLKL-NOEL)
td(CLKL-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
-
THCLK - 1 ns
FSMC_CLK low to FSMC_NOE high
2.5
-
-
4
-
ns
ns
ns
ns
ns
ns
ns
FSMC_CLK low to FSMC_AD[15:0] valid
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data before FSMC_CLK high
FSMC_A/D[15:0] valid data after FSMC_CLK high
0
6
-
4
-
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
TBD
TBD
-
-
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Electrical characteristics
STM32L151xD STM32L152xD
Figure 22. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
d(CLKL-NExH)
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
t
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:16]
FSMC_NWE
t
d(CLKL-NWEL)
d(CLKL-NWEH)
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
D1
t
d(CLKL-Data)
d(CLKL-ADV)
FSMC_AD[15:0]
AD[15:0]
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKL-NBLH)
ai14992f
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STM32L151xD STM32L152xD
Electrical characteristics
(1)
Table 42. Synchronous multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
Max
Unit
FSMC_CLK period
2*THCLK
-
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
0
-
0
-
FSMC_CLK low to FSMC_NADV high
0
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
-
0
-
td(CLKL-AIV)
THCLK + 4
td(CLKL-NWEL)
td(CLKL-NWEH)
td(CLKL-ADIV)
td(CLKL-DATA)
-
1
0
-
FSMC_CLK low to FSMC_NWE high
FSMC_CLK low to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid after FSMC_CLK low
5
-
-
6
-
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
TBD
TBD
1
th(CLKH-NWAITV)
td(CLKL-NBLH)
FSMC_NWAIT valid after FSMC_CLK high
FSMC_CLK low to FSMC_NBL high
-
-
1. CL = 30 pF.
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Electrical characteristics
STM32L151xD STM32L152xD
Figure 23. Synchronous non-multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
d(CLKL-NExH)
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FSMC_NEx
t
t
d(CLKL-NADVL)
FSMC_NADV
t
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:0]
FSMC_NOE
t
t
d(CLKL-NOEL)
d(CLKL-NOEH)
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FSMC_D[15:0]
FSMC_NWAIT
D1
D2
h(CLKH-NWAITV)
t
t
su(NWAITV-CLKH)
(WAITCFG = 1b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
ai14894f
(1)
Table 43. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Max
Unit
2*THCLK
0.5
-
tw(CLK)
FSMC_CLK period
-
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
0
0
-
ns
ns
ns
ns
ns
ns
-
3
-
FSMC_CLK low to FSMC_NADV high
3.5
-
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NOE low
0
-
td(CLKL-AIV)
0
td(CLKL-NOEL)
td(CLKL-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
-
THCLK + 1 ns
FSMC_CLK low to FSMC_NOE high
2.5
4
-
-
-
-
-
ns
ns
ns
ns
ns
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
4
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
TBD
TBD
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STM32L151xD STM32L152xD
Electrical characteristics
Figure 24. Synchronous non-multiplexed PSRAM write timings
BUSTURN = 0
d(CLKL-NExH)
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExL)
FSMC_NEx
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FSMC_NADV
FSMC_A[25:0]
FSMC_NWE
t
t
t
d(CLKL-AIV)
d(CLKL-AV)
t
d(CLKL-NWEL)
d(CLKL-NWEH)
t
t
d(CLKL-Data)
d(CLKL-Data)
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
d(CLKL-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993g
(1)
Table 44. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
Max Unit
FSMC_CLK period
2*THCLK -3
-
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL)
td(CLKL-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
-
1
-
5
-
FSMC_CLK low to FSMC_NADV high
7
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
-
0
-
td(CLKL-AIV)
THCLK + 4
td(CLKL-NWEL)
td(CLKL-NWEH)
td(CLKL-DATA)
td(CLKL-NBLH)
-
5
2
-
FSMC_CLK low to FSMC_NWE high
FSMC_D[15:0] valid data after FSMC_CLK low
FSMC_CLK low to FSMC_NBL high
-
7
-
3
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
TBD
TBD
-
-
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Electrical characteristics
STM32L151xD STM32L152xD
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and
DD
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Table 45. EMS characteristics
Level/
Class
Symbol
Parameter
Conditions
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VFESD
2B
4A
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
VEFTB
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
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STM32L151xD STM32L152xD
Prequalification trials
Electrical characteristics
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs. frequency range
Monitored
4 MHz 16 MHz
32MHz
voltage
range 1
Symbol Parameter
Conditions
Unit
frequency band
voltage voltage
range 3 range 2
0.1 to 30 MHz
30 to 130 MHz
130 MHz to 1GHz
SAE EMI Level
3
-6
4
-5
-7
-7
1
VDD = 3.3 V,
TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
18
15
2.5
dBµV
-
SEMI
Peak level
5
2
6.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class Maximum value(1) Unit
Electrostatic discharge
voltage (human body model) to JESD22-A114
TA = +25 °C, conforming
VESD(HBM)
2
II
2000
500
V
Electrostatic discharge
TA = +25 °C, conforming
V
ESD(CDM) voltage (charge device model) to JESD22-C101
1. Based on characterization results, not tested in production.
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Electrical characteristics
Static latch-up
STM32L151xD STM32L152xD
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
●
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA = +105 °C conforming to JESD78A
II level A
6.3.12
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation. However,
DD
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 49. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on true open-drain pins
Injected current on all 5 V tolerant (FT) pins
Injected current on any other pin
-5
-5
-5
+0
+0
+5
IINJ
mA
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Electrical characteristics
6.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics
Symbol
Parameter
Input low level voltage
Conditions
Min
Typ
Max
Unit
VIL
VSS - 0.3
-
-
-
0.8
VDD+0.3
5.5V
TTL ports
2.7 V ≤ VDD≤ 3.6 V
Standard I/O input high level voltage
FT(2) I/O input high level voltage
VIH
VIL
2(1)
CMOS ports
1.65 V ≤ VDD≤ 3.6 V
(3)
Input low level voltage
–0.3
-
-
-
-
-
-
0.3VDD
CMOS ports
1.65 V ≤ VDD≤ 3.6 V
Standard I/O Input high level voltage
VDD+0.3
V
CMOS ports
1.65 V ≤ VDD≤ 2.0 V
(3)(4)
VIH
0.7 VDD
5.25
5.5
-
FT(5) I/O input high level voltage
CMOS ports
2.0 V≤ VDD≤ 3.6 V
Standard I/O Schmitt trigger voltage
hysteresis(6)
(7)
Vhys
10% VDD
VSS ≤ VIN ≤ VDD
I/Os with LCD
-
50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches
-
-
-
-
50
50
VSS ≤ VIN ≤ VDD
I/Os with analog
switches and LCD
Ilkg
Input leakage current (8)(3)
nA
VSS ≤ VIN ≤ VDD
I/Os with USB
-
-
-
-
TBD
50
VSS ≤ VIN ≤ VDD
Standard I/Os
RPU
RPD
CIO
Weak pull-up equivalent resistor(9)(3)
Weak pull-down equivalent resistor(9)(3)
I/O pin capacitance
VIN = VSS
VIN = VDD
30
30
-
45
45
5
60
60
-
kΩ
kΩ
pF
1. Guaranteed by design.
2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled.
3. Tested in production
4. 0.7VDD for 5V-tolerant receiver
5. FT = Five-volt tolerant.
6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
7. With a minimum of 200 mV. Based on characterization, not tested in production.
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Electrical characteristics
STM32L151xD STM32L152xD
8. The max. value may be exceeded if negative current is injected on adjacent pins.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or
source up to 20 mA with the non-standard V /V specifications given in Table 51.
OL OH
in the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
●
The sum of the currents sourced by all the I/Os on V
plus the maximum Run
DD,
consumption of the MCU sourced on V
cannot exceed the absolute maximum rating
DD,
I
(see Table 12).
VDD
●
The sum of the currents sunk by all the I/Os on V plus the maximum Run
SS
consumption of the MCU sunk on V cannot exceed the absolute maximum rating
SS
I
(see Table 12).
VSS
Output voltage levels
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 14. All I/Os are CMOS and TTL compliant.
Table 51. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max Unit
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(2)
VOL
-
0.4
IIO = +8 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)(2)
VOH
2.4
-
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
(1)(4)
VOL
-
0.45
IIO =+ 4 mA
1.65 V < VDD
2.7 V
<
V
Output high level voltage for an I/O pin
when 8 pins are sourced at same time
(3)(4)
VOH
VDD-0.45
-
-
Output low level voltage for an I/O pin
when 4 pins are sunk at same time
(1)(4)
VOL
1.3
-
I
IO = +20 mA
2.7 V < VDD < 3.6 V
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(3)(4)
VOH
VDD-1.3
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS
.
2. Tested in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD
.
4. Based on characterization data, not tested in production.
98/140
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STM32L151xD STM32L152xD
Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 25 and
Table 52, respectively.
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 14.
(1)
Table 52. I/O AC characteristics
OSPEEDRx
[1:0] bit
Symbol
Parameter
Conditions
Min Max(2) Unit
value(1)
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 50 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
CL = 30 pF, VDD = 2.7 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
400
625
625
2
fmax(IO)out Maximum frequency(3)
kHz
ns
00
01
10
tf(IO)out
Output rise and fall time
tr(IO)out
fmax(IO)out Maximum frequency(3)
MHz
ns
1
125
250
10
2
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
ns
25
125
50
8
tf(IO)out
Output rise and fall time
tr(IO)out
Fmax(IO)out Maximum frequency(3)
MHz
11
-
5
tf(IO)out
Output rise and fall time
tr(IO)out
30
ns
Pulse width of external
tEXTIpw
signals detected by the
EXTI controller
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design. Not tested in production.
3. The maximum frequency is defined in Figure 25.
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Electrical characteristics
Figure 25. I/O AC characteristics definition
STM32L151xD STM32L152xD
90%
10 %
50%
50%
90%
10%
External
Output
t
t
r(IO)out
r(IO)out
on 50pF
T
Maximum frequency is achieved if (t + t ) 2/3)T and if the duty cycle is (45-55%)
r
f
when loaded by 50 pF
ai14131
6.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology.
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and V supply voltage conditions summarized in
DD
Table 14.
Table 53. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
(1)
VIL(NRST)
NRST input low level voltage
NRST input high level voltage
VSS
1.4
-
-
0.8
(1)
VIH(NRST)
VDD
IOL = 2 mA
2.7 V < VDD < 3.6 V
V
-
-
-
NRST output low level
voltage
(1)
VOL(NRST)
0.4
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
10%VDD
30
NRST Schmitt trigger voltage
hysteresis
(1)
(1)
(2)
Vhys(NRST)
-
-
mV
Weak pull-up equivalent
resistor(3)
RPU
VIN = VSS
45
60
kΩ
(1)
VF(NRST)
NRST input filtered pulse
-
-
-
50
-
ns
ns
VNF(NRST)
NRST input not filtered pulse
350
1. Guaranteed by design, not tested in production.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Figure 26. Recommended NRST pin protection
Electrical characteristics
V
DD
External
reset circuit(1)
R
PU
(2)
Internal reset
NRST
Filter
0.1 μF
STM32L15xxx
ai17854
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset will not be taken into account by the device.
6.3.15
TIM timer characteristics
The parameters given in the following table are guaranteed by design.
Refer to Section 6.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
(1)
Table 54. TIMx characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tTIMxCLK
ns
1
-
tres(TIM)
Timer resolution time
fTIMxCLK = 32 MHz 31.25
0
-
fTIMxCLK/2
MHz
Timer external clock
frequency on CH1 to CH4
fEXT
fTIMxCLK = 32 MHz
0
16
16
MHz
ResTIM
Timer resolution
bit
16-bit counter clock period
when internal clock is
selected (timer’s prescaler
disabled)
tTIMxCLK
1
65536
tCOUNTER
fTIMxCLK = 32 MHz 0.0312
-
2048
µs
tTIMxCLK
s
65536 × 65536
134.2
tMAX_COUNT
Maximum possible count
fTIMxCLK = 32 MHz
-
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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Electrical characteristics
STM32L151xD STM32L152xD
6.3.16
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLK1
DD
summarized in Table 14.
2
I
The STM32L151xD and STM32L152xD product line C interface meets the requirements of
2
the standard I C communication protocol with the following restrictions: SDA and SCL are
not “true” open-drain I/O pins. When configured as open-drain, the PMOS connected
between the I/O pin and V is disabled, but is still present.
DD
2
The I C characteristics are described in Table 55. Refer also to Section 6.3.12: I/O current
for more details on the input/output alternate function characteristics
injection characteristics
(SDA and SCL)
.
2
Table 55. I C characteristics
Standard mode I2C(1)
Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
Max
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
SCL clock high time
SDA setup time
4.7
4.0
250
0
-
-
-
-
1.3
0.6
100
0
-
µs
-
-
SDA data hold time
900(3)
tr(SDA)
tr(SCL)
ns
SDA and SCL rise time
-
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
Start condition hold time
-
300
300
-
th(STA)
tsu(STA)
4.0
4.7
4.0
4.7
-
-
-
-
0.6
-
-
-
-
µs
Repeated Start condition
setup time
0.6
0.6
1.3
tsu(STO)
Stop condition setup time
μs
μs
Stop to Start condition time
(bus free)
tw(STO:STA)
Capacitive load for each bus
line
Cb
-
400
-
400
pF
Guaranteed by design, not tested in production.
1.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
3.
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STM32L151xD STM32L152xD
Electrical characteristics
2
Figure 27. I C bus AC waveforms and measurement circuit
V
V
DD
DD
STM32L15xxx
SDA
4.7k
4.7k
100
100
I2C bus
SCL
START REPEATED
START
START
t
su(STA)
SDA
t
t
t
r(SDA)
f(SDA)
su(SDA)
t
su(STA:STO)
STOP
t
t
t
w(SCKL)
h(SDA)
h(STA)
SCL
t
t
t
su(STO)
r(SCK)
t
f(SCK)
w(SCKH)
ai17855
Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
1.
(1)(2)
Table 56. SCL frequency (f
= 32 MHz, VDD = 3.3 V)
PCLK1
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
300
200
100
50
0x801B
0x8024
0x8035
0x00A0
0x0140
0x0320
20
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
STM32L151xD STM32L152xD
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, f
frequency and V supply voltage
PCLKx
DD
conditions summarized in Table 14.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 57. SPI characteristics
Symbol
Parameter
Conditions
Master mode
Min
Max(2)
Unit
-
-
-
16
16
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode
MHz
Slave transmitter
12(3)
(2)
tr(SCK)
tf(SCK)
SPI clock rise and fall time
Capacitive load: C = 30 pF
-
6
ns
%
(2)
DuCy(SCK)
tsu(NSS)
SPI slave input clock duty cycle Slave mode
30
70
-
NSS setup time
NSS hold time
Slave mode
Slave mode
4tHCLK
2tHCLK
th(NSS)
-
(2)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2−5 tSCK/2+3
(2)
(2)
tsu(MI)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
5
6
-
(2)
tsu(SI)
-
(2)
th(MI)
5
-
ns
Data input hold time
(2)
th(SI)
5
-
(4)
ta(SO)
Data output access time
Data output valid time
Data output valid time
0
3tHCLK
(2)
tv(SO)
-
33
6.5
-
(2)
tv(MO)
-
(2)
th(SO)
17
0.5
Data output hold time
(2)
th(MO)
-
1. The characteristics above are given for voltage range 1.
2. Based on characterization, not tested in production.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
104/140
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Electrical characteristics
Figure 28. SPI timing diagram - slave mode and CPHA = 0
NSS input
t
c(SCK)
t
t
h(NSS)
SU(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
t
dis(SO)
r(SCK)
f(SCK)
v(SO)
a(SO)
h(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134c
(1)
Figure 29. SPI timing diagram - slave mode and CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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Electrical characteristics
Figure 30. SPI timing diagram - master mode
STM32L151xD STM32L152xD
(1)
High
NSS input
t
c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t
t
t
t
w(SCKH)
w(SCKL)
r(SCK)
f(SCK)
t
su(MI)
MISO
INPUT
MSBIN
t
BIT6 IN
LSB IN
h(MI)
MOSI
M SB OUT
BIT1 OUT
LSB OUT
OUTPUT
t
t
v(MO)
h(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
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STM32L151xD STM32L152xD
Electrical characteristics
6.3.17
I2S characteristics
Table 58. I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main Clock Output
256 x 8K 256xFs (1) MHz
Master data: 32 bits
Slave data: 32 bits
-
-
64xFs
fCK
I2S clock frequency
MHz
%
64xFs
DCK
tr(CK)
tf(CK)
tv(WS)
th(WS)
I2S clock frequency duty cycle Slave receiver, 48KHz
30
70
8
8
24
-
I2S clock rise time
Capacitive load CL=30pF
I2S clock fall time
-
WS valid time
WS hold time
Master mode
Master mode
Slave mode
4
0
tsu(WS) WS setup time
th(WS) WS hold time
15
0
-
Slave mode
-
tsu(SD_MR) Data input setup time
tsu(SD_SR) Data input setup time
Master receiver
Slave receiver
Master receiver
Slave receiver
8
-
9
-
ns
th(SD_MR)
Data input hold time
th(SD_SR)
5
-
4
-
Slave transmitter
(after enable edge)
tv(SD_ST) Data output valid time
th(SD_ST) Data output hold time
tv(SD_MT) Data output valid time
-
22
-
64
-
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
12
-
Master transmitter
(after enable edge)
th(SD_MT) Data output hold time
1. The maximum for 256xFs is 8 MHz
8
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), f , f and D values. These values reflect only the digital peripheral
MCK CK
CK
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Electrical characteristics
STM32L151xD STM32L152xD
2
(1)
Figure 31. I S slave timing diagram (Philips protocol)
t
c(CK)
CPOL = 0
CPOL = 1
t
t
t
t
w(CKL)
h(WS)
w(CKH)
WS input
t
t
t
v(SD_ST)
h(SD_ST)
su(WS)
SD
transmit
LSB transmit(2)
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
su(SD_SR)
h(SD_SR)
LSB receive(2)
Bitn receive
LSB receive
SD
receive
ai14881b
1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
2
(1)
Figure 32. I S master timing diagram (Philips protocol)
t
t
r(CK)
f(CK)
t
c(CK)
CPOL = 0
t
w(CKH)
CPOL = 1
t
t
h(WS)
t
v(WS)
w(CKL)
WS output
t
t
v(SD_MT)
h(SD_MT)
SD
transmit
LSB transmit(2)
MSB transmit
MSB receive
Bitn transmit
LSB transmit
t
t
h(SD_MR)
su(SD_MR)
LSB receive(2)
Bitn receive
LSB receive
SD
receive
ai14884b
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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STM32L151xD STM32L152xD
Electrical characteristics
6.3.18
SDIO characteristics
Table 59. SDIO characteristics
(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fPP
Clock frequency in data transfer mode
CL ≤ 30 pF
CL ≤ 30 pF
CL ≤ 30 pF
CL ≤ 30 pF
CL ≤ 30 pF
0
20(2)
18(2)
-
24
-
MHz
tW(CKL) Clock low time, fPP = 24 MHz
tW(CKH) Clock high time, fPP = 24 MHz
-
ns
tr
tf
Clock rise time, fPP = 24 MHz
Clock fall time, fPP = 24 MHz
5
5
-
CMD, D inputs (referenced to CK) in SD default mode
From 2.8
to 3.6 V
tISU
tIH
Input setup time, fPP = 24 MHz
Input hold time, fPP = 24 MHz
CL ≤ 30 pF
CL ≤ 30 pF
2
-
-
ns
ns
1.6
CMD, D outputs (referenced to CK) in SD default mode
tOVD
tOHD
Output valid default time, fPP = 24 MHz
Output hold default time, fPP = 24 MHz
CL ≤ 30 pF
CL ≤ 30 pF
0
0
14
-
1. Based on characterization, not tested in production.
2. Values measured with a threshold level equal to VDD/2.
Figure 33. SDIO timings
tf
tr
tC
tW(CKH)
tW(CKL)
CK
tOHD
tOVD
D, CMD(output)
tISU
tIH
D, CMD(input)
MS31068V1
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Electrical characteristics
STM32L151xD STM32L152xD
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 60. USB startup time
Symbol
Parameter
Max
Unit
(1)
tSTARTUP
USB transceiver startup time
1
µs
1. Guaranteed by design, not tested in production.
Table 61. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1) Unit
Input levels
VDD
USB operating voltage
3.0
0.2
0.8
1.3
3.6
-
V
V
(2)
VDI
Differential input sensitivity
I(USB_DP, USB_DM)
(2)
VCM
Differential common mode range Includes VDI range
Single ended receiver threshold
2.5
2.0
(2)
VSE
Output levels
(3)
VOL
VOH
Static output level low
Static output level high
RL of 1.5 kΩ to 3.6 V(4)
-
0.3
3.6
V
(3)
(4)
RL of 15 kΩ to VSS
2.8
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization, not tested in production.
3. Tested in production.
RL is the load connected on the USB drivers.
4.
Figure 34. USB timings: definition of data signal rise and fall time
Crossover
points
Differential
Data Lines
V
CR S
V
SS
t
t
r
f
ai14137
Table 62. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
tf
Rise time(2)
Fall Time(2)
CL = 50 pF
CL = 50 pF
tr/tf
4
4
20
20
ns
ns
%
V
trfm
VCRS
Rise/ fall time matching
90
1.3
110
2.0
Output signal crossover voltage
110/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
1. Guaranteed by design, not tested in production.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
2.
6.3.19
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 64 are guaranteed by design.
Table 63. ADC clock frequency
Symbol Parameter
Conditions
Min
Max
Unit
VREF+ = VDDA
16
VREF+ < VDDA
8
4
2.4 V ≤ VDDA ≤ 3.6 V VREF+ > 2.4 V
Voltage
range 1 & 2
VREF+ < VDDA
VREF+ ≤ 2.4 V
ADC clock
fADC
0.480
MHz
frequency
V
REF+ = VDDA
8
4
4
1.8 V ≤ VDDA ≤ 2.4 V
VREF+ < VDDA
Voltage range 3
Table 64. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
1.8
-
3.6
2.4 V ≤ VDDA ≤ 3.6 V
VREF+ must be below 1.8(1)
or equal to VDDA
VREF+
Positive reference voltage
Negative reference voltage
-
VDDA
V
VREF-
IVDDA
-
-
VSSA
1000
-
Current on the VDDA input
pin
1450
µA
Peak
-
700
450
VREF+
1
Current on the VREF input
pin
(2)
IVREF
400
Average
-
Conversion voltage range(3)
0(4)
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
-
-
-
-
-
-
-
-
-
V
VAIN
Direct channels
Multiplexed channels
Direct channels
12-bit sampling rate
Msps
0.76
1.07
0.8
10-bit sampling rate
8-bit sampling rate
6-bit sampling rate
Msps
Msps
Msps
Multiplexed channels
Direct channels
fS
1.23
0.89
1.54
1
Multiplexed channels
Direct channels
Multiplexed channels
Doc ID 022027 Rev 6
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Electrical characteristics
Table 64. ADC characteristics (continued)
STM32L151xD STM32L152xD
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Direct channels
2.4 V ≤ VDDA ≤ 3.6 V
0.25(5)
-
-
Multiplexed channels
2.4 V ≤ VDDA ≤ 3.6 V
0.56(5)
0.56(5)
1(5)
-
-
-
-
-
-
µs
tS
Sampling time
Direct channels
1.8 V ≤ VDDA ≤ 2.4 V
Multiplexed channels
1.8 V ≤ VDDA ≤ 2.4 V
4
1
-
-
384
1/fADC
µs
fADC = 16 MHz
24.75
Total conversion time
(including sampling time)
4 to 384 (sampling
phase) +12 (successive
approximation)
tCONV
1/fADC
Direct channels
Multiplexed channels
12-bit conversions
6/8/10-bit conversions
12-bit conversions
6/8/10-bit conversions
-
-
-
Internal sample and hold
capacitor
CADC
fTRIG
fTRIG
16
pF
-
-
-
-
-
-
-
-
-
-
-
-
-
Tconv+1 1/fADC
Tconv 1/fADC
Tconv+2 1/fADC
Tconv+1 1/fADC
External trigger frequency
Regular sequencer
-
-
-
External trigger frequency
Injected sequencer
-
50
kΩ
0.5
(6)
RAIN
External input impedance
-
fADC = 16 MHz
fADC = 16 MHz
219
3.5
156
2.5
-
281
4.5
219
3.5
3.5
ns
1/fADC
ns
Injection trigger conversion
latency
tlat
Regular trigger conversion
latency
tlatr
1/fADC
µs
tSTAB
Power-up time
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an
external voltage reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x
400 = 450 µA at 1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ.
6. For 1 Msps, maximum Rext is 0.5 kΩ.
112/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Electrical characteristics
(1)(2)
Table 65. ADC accuracy
Symbol
Parameter
Test conditions
Min(3)
Typ
Max(3)
Unit
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
-
2
1
4
2
-
2.4 V ≤ VDDA ≤ 3.6 V
2.4 V ≤ VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Gain error
-
-
1.5
1
3.5
2
LSB
Differential linearity error
Integral linearity error
-
1.7
10
3
ENOB Effective number of bits
9.2
-
bits
dB
2.4 V ≤ VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
1 kHz ≤ Finput ≤ 100 kHz
Signal-to-noise and
SINAD
57.5
62
-
distortion ratio
SNR
THD
ET
Signal-to-noise ratio
Total harmonic distortion
Total unadjusted error
Offset error
57.5
62
-75
4
-
-
-74
-
-
-
-
-
-
-
-
-
-
6.5
4
EO
EG
ED
EL
2
2.4 V ≤ VDDA ≤ 3.6 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Gain error
4
6
LSB
LSB
Differential linearity error
Integral linearity error
Total unadjusted error
Offset error
1
2
1.5
2
3
ET
3
EO
EG
ED
EL
1
1.5
2
1.8 V ≤ VDDA ≤ 2.4 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 °C
Gain error
1.5
1
Differential linearity error
Integral linearity error
2
1
1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Based on characterization, not tested in production.
Doc ID 022027 Rev 6
113/140
Electrical characteristics
Figure 35. ADC accuracy characteristics
STM32L151xD STM32L152xD
VREF+
VDDA
4096
[1LSBIDEAL
=
(or
depending on package)]
4096
E
G
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
E =Total Unadjusted Error: maximum deviation
T
E
between the actual and the ideal transfer curves.
T
(3)
7
6
5
4
3
2
1
E
=Offset Error: deviation between the first actual
O
(1)
transition and the first ideal one.
=Gain Error: deviation between the last ideal
E
G
transition and the last actual one.
E
E
O
L
E =Differential Linearity Error: maximum deviation
D
between actual steps and the ideal one.
E =Integral Linearity Error: maximum deviation
L
E
between any actual transition and the end point
correlation line.
D
1 LSB
IDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
V
V
DDA
SSA
ai14395b
Figure 36. Typical connection diagram using the ADC
V
DD
STM32L15xxx
Sample and hold ADC
V
0.6 V
T
converter
(1)
(1)
R
R
ADC
AIN
AINx
12-bit
converter
I
50 nA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
ai17856b
1. Refer to Table 64 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
114/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Figure 37. Maximum dynamic current consumption on V
Electrical characteristics
supply pin during ADC
REF+
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
I
ref+
700µA
300µA
(1)
Table 66.
R
max for f
= 16 MHz
ADC
AIN
RAIN max (kΩ)
Ts
(cycles)
Ts
(µs)
Multiplexed channels
Direct channels
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V
4
9
0.25
Not allowed
0.8
Not allowed
Not allowed
0.8
0.7
2.0
Not allowed
1.0
0.5625
16
24
48
96
192
384
1
1.5
3
2.0
4.0
3.0
3.0
1.8
6.0
4.5
6.8
4.0
15.0
30.0
50.0
50.0
10.0
6
15.0
32.0
50.0
10.0
20.0
12
24
25.0
40.0
50.0
50.0
1. Guaranteed by design, not tested in production.
Doc ID 022027 Rev 6
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Electrical characteristics
STM32L151xD STM32L152xD
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 38 or Figure 39,
depending on whether V is connected to V or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed as close as possible to the chip.
Figure 38. Power supply and reference decoupling (V not connected to V
)
REF+
DDA
STM32L15xxx
VREF+
(see note 1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA /VREF–
(see note 1)
ai17857b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
Figure 39. Power supply and reference decoupling (V
connected to V
)
REF+
DDA
STM32L15xxx
V
/V
REF+ DDA
(See note 1)
1 μF // 100 nF
V
/V
REF– SSA
(See note 1)
ai17858a
1. VREF+ and VREF– inputs are available only on 100-pin packages.
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STM32L151xD STM32L152xD
Electrical characteristics
6.3.20
DAC electrical specifications
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 67. DAC characteristics
Symbol
VDDA
VREF+
VREF-
Parameter
Conditions
Min
Typ
Max
Unit
Analog supply voltage
1.8
-
3.6
V
VDDA
REF+ must always be below
V
Reference supply voltage
Lower reference voltage
1.8
-
3.6
VSSA
Current consumption on No load, middle code (0x800)
VREF+ supply
-
-
-
-
130
220
210
320
220
350
320
520
(1)
IDDVREF+
No load, worst code (0x000)
VREF+ = 3.3 V
µA
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
(1)
IDDA
(2)
RL
Resistive load
5
-
-
-
-
kΩ
pF
kΩ
DAC output buffer ON
Capacitive load
(2)
CL
50
10
RO
Output impedance
DAC output buffer OFF
6
8
DAC output buffer ON
0.2
-
VDDA – 0.2
V
Voltage on DAC_OUT
output
VDAC_OUT
DAC output buffer OFF
0.5
-
-
VREF+ – 1LSB mV
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
1.5
3
DNL(1)
Differential non linearity(3)
Integral non linearity(4)
No RLOAD, CL ≤ 50 pF
-
-
-
-
-
-
1.5
2
3
4
DAC output buffer OFF
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
INL(1)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
LSB
4
2
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
10
5
25
8
Offset error at code
0x800 (5)
Offset(1)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
Offset error at code
0x001(6)
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
Offset1(1)
1.5
5
Doc ID 022027 Rev 6
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Electrical characteristics
STM32L151xD STM32L152xD
Table 67. DAC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA = 3.3V
VREF+ = 3.0V
-20
-10
0
TA = 0 to 50 °C
DAC output buffer OFF
Offset error temperature
coefficient (code 0x800)
dOffset/dT(1)
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
0
20
50
TA = 0 to 50 °C
DAC output buffer ON
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
+0.1 / -0.2% +0.2 / -0.5%
DAC output buffer ON
Gain(1)
Gain error(7)
%
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
+0 / -0.2%
-2
+0 / -0.4%
0
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer OFF
-10
-40
Gain error temperature
coefficient
dGain/dT(1)
µV/°C
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 °C
DAC output buffer ON
-8
0
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
12
8
30
12
DAC output buffer ON
TUE(1)
Total unadjusted error
LSB
µs
No RLOAD, CL ≤ 50 pF
DAC output buffer OFF
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes till
DAC_OUT reaches final
value 1LSB
tSETTLING
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
7
12
1
Max frequency for a
correct DAC_OUT change
Update rate (95% of final value) with 1 CL ≤ 50 pF, RL ≥ 5 kΩ
Msps
LSB variation in the input
code
Wakeup time from off
state (setting the ENx bit
tWAKEUP
PSRR+
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
9
15
µs
in the DAC Control
register)(8)
VDDA supply rejection ratio
CL ≤ 50 pF, RL ≥ 5 kΩ
-60
-35
dB
(static DC measurement)
1. Data based on characterization results.
2. Connected between DAC_OUT and V
.
SSA
3. Difference between two consecutive codes - 1 LSB.
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
118/140
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STM32L151xD STM32L152xD
Electrical characteristics
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (V – 0.2) V when buffer is ON.
DDA
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 40. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RLOAD
DAC_OUTx
12-bit
digital to
analog
converter
CLOAD
ai17157V2
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.21
Operational amplifier characteristics
Table 68. Operational amplifier characteristics
Symbol
CMIR
Parameter
Condition(1)
Min(2)
Typ
Max(2)
Unit
Common mode input range
0
-
VDD
Maximum
calibration range
-
-
-
-
15
VIOFFSET
Input offset voltage
mV
After offset
calibration
1.5
Normal mode
-
-
-
-
-
-
40
80
1
µV/°C
Input offset voltage
drift
ΔVIOFFSET
Low power mode
Dedicated input
IIB
Input current bias
75 °C
nA
General purpose
input
-
-
10
Normal mode
-
-
-
-
-
-
-
-
-
500
ILOAD
Drive current
Consumption
µA
µA
dB
dB
Low power mode
Normal mode
-
100
100
30
220
No load,
quiescent mode
IDD
Low power mode
Normal mode
60
-
-85
-90
-85
-90
Common mode
rejection ration
CMRR
PSRR
Low power mode
Normal mode
-
-
Power supply
rejection ratio
DC
Low power mode
-
Doc ID 022027 Rev 6
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Electrical characteristics
STM32L151xD STM32L152xD
Table 68. Operational amplifier characteristics (continued)
Symbol
Parameter
Normal mode
Condition(1)
Min(2)
Typ
Max(2)
Unit
400
150
200
70
1000
300
500
150
3000
800
VDD>2.4 V
Low power mode
Normal mode
GBW
Bandwidth
kHZ
2200
800
V
DD<2.4 V
Low power mode
VDD>2.4 V
Normal mode
(between 0.1 V and
VDD-0.1 V)
-
700
-
SR
AO
Slew rate
V/ms
dB
Low power mode
Normal mode
V
DD>2.4 V
-
-
100
300
50
100
110
-
-
-
VDD<2.4 V
Low power mode
Normal mode
-
-
55
65
4
-
Open loop gain
Low power mode
Normal mode
-
-
RLOAD
CLOAD
Resistive load
Capacitive load
VDD<2.4 V
kΩ
Low power mode
20
-
-
-
-
50
pF
VDD
100
-
Normal mode
-
-
High saturation
voltage
VOHSAT
VOLSAT
ILOAD = max or
RLOAD = min
Low power mode
Normal mode
VDD-50
-
-
-
100
50
-
mV
-
-
-
-
Low saturation
voltage
low power mode
-
ϕm
Phase margin
Gain margin
60
-12
°
GM
-
dB
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
tOFFTRIM
-
1
-
ms
µs
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode
Wakeup time
-
-
10
30
-
-
tWAKEUP
CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
Low power mode
1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise, the operating
temperature range is 105 °C to -40 °C.
2. Data based on characterization results, not tested in production.
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STM32L151xD STM32L152xD
Electrical characteristics
6.3.22
Temperature sensor characteristics
Table 69. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
(1)
TL
VSENSE linearity with temperature
-
1.48
612
-
1
1.61
626.8
3.4
2
1.75
641.5
6
°C
mV/°C
mV
Avg_Slope(1) Average slope
V110
Voltage at 110°C 5°C(2)
(3)
IDDA(TEMP)
Current consumption
Startup time
µA
(3)
tSTART
-
-
10
µs
ADC sampling time when reading the
temperature
(4)(3)
TS_temp
10
-
-
1. Guaranteed by characterization, not tested in production.
2. Measured at VDD = 3 V 10 mV. V110 ADC conversion result is stored in the TSENSE_CAL2 byte.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23
Comparator
Table 70. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1) Typ
Max(1)
Unit
VDDA
R400K
R10K
Analog supply voltage
R400K value
1.65
3.6
V
-
-
400
10
-
-
kΩ
R10K value
Comparator 1 input
voltage range
VIN
0.6
-
VDDA
V
tSTART
td
Comparator startup time
Propagation delay(2)
Comparator offset
-
-
-
7
3
3
10
10
10
µs
Voffset
mV
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 °C
Comparator offset
dVoffset/dt variation in worst voltage
stress conditions
0
-
1.5
10
mV/1000 h
nA
ICOMP1
Current consumption(3)
160
260
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Doc ID 022027 Rev 6
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Electrical characteristics
STM32L151xD STM32L152xD
Table 71. Comparator 2 characteristics
Symbol
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
VIN
Analog supply voltage
1.65
-
3.6
VDDA
20
25
3.5
6
V
V
Comparator 2 input voltage range
0
-
-
-
-
-
-
-
-
Fast mode
15
20
1.8
2.5
0.8
1.2
4
tSTART
Comparator startup time
Slow mode
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
td slow
Propagation delay(2) in slow mode
µs
2
td fast
Propagation delay(2) in fast mode
Comparator offset error
4
Voffset
20
mV
VDDA = 3.3V
dThreshold/ Threshold voltage temperature
TA = 0 to 50 °C
ppm
/°C
-
15
30
dt
coefficient
V- = VREF+, 3/4 VREF+,
1/2 VREF+, 1/4 VREF+
.
Fast mode
-
-
3.5
0.5
5
2
ICOMP2
Current consumption(3)
µA
Slow mode
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
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STM32L151xD STM32L152xD
Electrical characteristics
6.3.24
LCD controller (STM32L152xD only)
The STM32L152xD embeds a built-in step-up converter to provide a constant LCD
reference voltage independently from the V voltage. An external capacitor C must be
DD
ext
connected to the V
pin to decouple this converter.
LCD
Table 72. LCD controller characteristics
Symbol
Parameter
LCD external voltage
Min
Typ
Max
Unit
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
VLCD6
VLCD7
Cext
-
-
3.6
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
VLCD external capacitance
-
2.6
-
-
2.73
2.86
2.98
3.12
3.26
3.4
-
-
-
-
-
V
-
-
-
-
-
-
-
3.55
-
0.1
2
µF
µA
Supply current at VDD = 2.2 V
-
3.3
3.1
-
(1)
ILCD
Supply current at VDD = 3.0 V
-
-
(2)
RHtot
Low drive resistive network overall value
High drive resistive network total value
Segment/Common highest level voltage
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
5.28
6.6
7.92
MΩ
kΩ
V
(2)
RL
192
240
288
V44
V34
V23
V12
V13
V14
V0
-
-
-
VLCD
3/4 VLCD
2/3 VLCD
1/2 VLCD
1/3 VLCD
1/4 VLCD
-
-
-
-
-
-
-
-
-
V
-
-
0
Segment/Common level voltage error
ΔVxx(3)
-
-
50
mV
TA = -40 to 85 °C
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design, not tested in production.
3. Based on characterization, not tested in production.
Doc ID 022027 Rev 6
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Package characteristics
STM32L151xD STM32L152xD
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
124/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Package characteristics
Figure 41. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
Seating plane
C
A
A2 A1
c
b
0.25 mm
gage plane
ccc
C
k
D
D1
A1
L
D3
L1
108
73
72
109
E3 E1
E
144
37
Pin 1
identification
1
36
ME_1A
e
Drawing is not to scale.
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Package characteristics
STM32L151xD STM32L152xD
Table 73. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical
data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
22.200
20.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.8740
0.7953
0.050
1.350
0.170
0.090
21.800
19.800
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
1.400
0.220
0.0551
0.0087
c
D
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.8661
0.7874
0.6890
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
D1
D3
E
21.800
19.800
22.200
20.200
0.8583
0.7795
0.8740
0.7953
E1
E3
e
L
0.450
0°
0.600
0.750
0.0177
0°
0.0295
L1
k
1.000
3.5°
7°
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. Recommended footprint
1.35
108
73
109
72
0.35
0.5
17.85
22.6
19.9
144
37
1
36
19.9
22.6
ai14905c
1. Dimensions are in millimeters.
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Package characteristics
Figure 43. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
L
D
L1
D1
D3
51
75
50
76
100
26
PIN 1
1
25
IDENTIFICATION
e
1L_ME_V3
1. Drawing is not to scale.
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Package characteristics
STM32L151xD STM32L152xD
Table 74. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
16.200
14.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
0.050
1.350
0.170
0.090
15.800
13.800
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
1.400
0.220
0.0551
0.0087
c
D
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.6299
0.5512
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
D1
D3
E
15.800
13.800
16.200
14.200
0.6220
0.5433
0.6378
0.5591
E1
E3
e
L
0.450
0.0°
0.600
0.750
0.0177
0.0°
0.0295
L1
k
1.000
3.5°
7.0°
7.0°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 44. Recommended footprint
75
51
76
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906
1. Dimensions are in millimeters.
128/140
Doc ID 022027 Rev 6
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Package characteristics
Figure 45. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc
C
L
D
L1
D1
D3
33
48
32
49
b
64
17
16
1
PIN 1
IDENTIFICATION
e
5W_ME_V2
1. Drawing is not to scale.
Doc ID 022027 Rev 6
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Package characteristics
STM32L151xD STM32L152xD
Table 75. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
1.600
0.150
1.450
0.270
0.200
12.200
10.200
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
0.050
1.350
0.170
0.090
11.800
9.800
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
1.400
0.220
0.0551
0.0087
c
D
12.000
10.000
7.500
12.000
10.000
7.500
0.500
0.600
1.000
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
0.0236
0.0394
D1
D3
E
11.800
9.800
12.200
10.200
0.4646
0.3858
0.4803
0.4016
E1
E3
e
L
0.450
0.750
0.0177
0.0
0.0295
L1
ccc
K
0.080
7.0
0.0031
7.0
3.5
0.0
3.5
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 46. Recommended footprint
48
33
0.3
49
32
0.5
12.7
10.3
10.3
64
17
1.2
1
16
7.8
12.7
ai14909
1. Dimensions are in millimeters.
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Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Package characteristics
Figure 47. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
outline
Z
Seating plane
ddd Z
A3
A
A2
A1
A
X
A1 ball
A1 ball
e
E
F
identifier index area
F
D
e
Y
M
12
1
Øb (132 balls)
BOTTOM VIEW
TOP VIEW
M
Øeee Z Y X
M Z
Ø fff
A0G8_ME_V1
1. Drawing is not to scale.
Table 76. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array
mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
0.530
0.460
0.050
0.400
0.270
0.170
6.950
6.950
0.600
0.0209
0.0181
0.0236
A1
A2
A3
b
0.080
0.450
0.320
0.280
7.000
7.000
0.110
0.500
0.370
0.330
7.050
7.050
0.0031
0.0177
0.0126
0.0110
0.2756
0.2756
0.0020
0.0157
0.0106
0.0067
0.2736
0.2736
0.0043
0.0197
0.0146
0.0130
0.2776
0.2776
D
E
e
0.500
0.750
0.0197
0.0295
F
0.700
0.800
0.080
0.0276
0.0315
0.0031
ddd
eee
fff
0.150
0.050
0.0059
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32L151xD STM32L152xD
Figure 48. WLCSP64, 0.400 mm pitch wafer level chip size package outline
D
A1 corner
Detail A
E
A
A2
Side view
Wafer back side
Detail A
Bump
(rotated 90 °)
A1
eee
b
Seating plane
e1
F
A
G
8
1
e1
e
H
G
e
F
Bump side
A0JV_ME
1. Drawing is not to scale.
132/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Package characteristics
Table 77. WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
0.540
0.570
0.19
0.600
0.0205
0.0067
0.0138
0.0094
0.1779
0.1926
0.0224
0.0075
0.0150
0.0106
0.1787
0.1933
0.0157
0.1102
0.0343
0.0416
0.0244
0.0083
0.0161
0.0118
0.1795
0.1941
0.380
0.270
4.539
4.911
0.400
2.800
0.870
1.056
0.240
4.504
4.876
0.300
4.574
4.946
D
E
e
e1
F
G
eee
0.050
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32L151xD STM32L152xD
7.2
Thermal characteristics
The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated
J
using the following equation:
T max = T max + (P max × Θ )
J
A
D
JA
Where:
●
●
●
●
T max is the maximum ambient temperature in °C,
A
Θ
is the package junction-to-ambient thermal resistance, in °C/W,
JA
P max is the sum of P
max and P max (P max = P
max + P max),
INT I/O
D
INT
I/O
D
P
max is the product of I and V , expressed in Watts. This is the maximum chip
DD DD
INT
internal power.
P
max represents the maximum power dissipation on output pins where:
I/O
P
max = Σ (V × I ) + Σ((V – V ) × I ),
OL OL DD OH OH
I/O
taking into account the actual V / I and V / I of the I/Os at low and high level in the
OL OL
OH OH
application.
Table 78. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
UFBGA132 - 7 x 7 mm
60
43
46
46
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
ΘJA
°C/W
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
WLCSP64 - 0.400 mm pitch
134/140
Doc ID 022027 Rev 6
STM32L151xD STM32L152xD
Figure 49. Thermal resistance
Package characteristics
3000.00
2500.00
2000.00
'PSCJEEFOꢊBSFB
5+ꢊꢋꢊ5+ꢊNBY
PD (mW)
LQFP64 10x10mm
WLCSP64
1500.00
1000.00
500.00
0.00
UFBGA132 7x7mm
LQFP144 20x20 7x7mm
100
75
50
25
0
Temperature(°C)
MS31407V1
7.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Doc ID 022027 Rev 6
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Ordering information scheme
STM32L151xD STM32L152xD
8
Ordering information scheme
Table 79. STM32L15xxD ordering information scheme
Example:
STM32 L 151 R
C
T
6
D xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Q = 132 pins
Flash memory size
D = 384 Kbytes of Flash memory
Package
H = BGA
T = LQFP
Y = WLCSP64
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
136/140
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STM32L151xD STM32L152xD
Revision history
9
Revision history
Table 80. Document revision history
Date
Revision
Changes
03-Oct-2011
1
Initial release.
Status of the document changed (datasheet instead of preliminary
data).
Updated low power features on page 1.
Removed references to devices with 256 KB of Flash memory.
GPIOF replaced with GIOPH.
Added SDIO in Table 2: Ultra-low-power STM32L15xxD device
features and peripheral counts on page 11 and in Table 10: Alternate
function input/output on page 43 (FSMC/SDIO instead of FSMC).
Table 2: Ultra-low-power STM32L15xxD device features and
peripheral counts: replaced STM32L15xWx with STM32L15xQx.
Figure 1: Ultra-low-power STM32L15xxD block diagram: updated
legend.
Modified Section 3.4: Clock management on page 21.
Table 4: STM32L15xQD UFBGA132 ballout: replaced
STM32L15xWC/D with STM32L15xQD.
Figure 5, Figure 5, Figure 6: updated titles.
Table 9: STM32L15xxD pin definitions: updated title, updated pins
PF0, PF1, PH2, PF12, PF13, PF14, PF15, PG0, PG1, PG12, PG15,
PD0, and PD1.
03-Feb-2012
2
Table 10: Alternate function input/output: Modified alternate function
for PA13 and PA14; removed EVENT OUT for PH2.
Figure 8: Memory map: removed the text “APB memory space”.
Modified Figure 11: Power supply scheme on page 54.
Modified Table 3: Functionalities depending on the operating power
supply range on page 16.
Table 18: Current consumption in Run mode, code with data
processing running from RAM: added footnote 3.
Table 19: Current consumption in Sleep mode: updated condition for
fHSE; added footnote 3.
Table 23: Typical and maximum current consumptions in Standby
mode: modified max values.
Table 61: USB DC electrical characteristics: removed two footnotes.
Modified Table 35: Flash memory and data EEPROM characteristics
on page 82.
Table 78: Thermal characteristics: updated “TBDs” with values.
Modified tables in Section 6.3.4: Supply current characteristics on
page 60.
Doc ID 022027 Rev 6
137/140
Revision history
Table 80. Document revision history (continued)
STM32L151xD STM32L152xD
Date
Revision
Changes
Added WLCSP64 package.
Section 3.1: Low power modes: changed ‘128 kHz’ to ‘131 kHz’ in
section “Low power run mode”.
Section 3.17.1: General-purpose timers (TIM2, TIM3, TIM4, TIM5,
TIM9, TIM10 and TIM11): changed ‘six’ to ‘seven’ synchronizable
general-purpose timers.
Table 9: STM32L15xxD pin definitions on page 37: updated name of
reference manual in footnote 5.
18-Apr-2012
3
I2C updated: footnote 3. from Table 55
Note about I2C clock updated: footnote 2. from Table 55 modified.
Note [non-robust] updated: footnote 2. from Table 65 modified.
GPIOs high current capability updated: Section 3.6: GPIOs (general-
purpose inputs/outputs) ‘except for analog inputs’ was removed.
Changed maximum number of touch sensing channels to 34, and
updated Table 2: Ultra-low-power STM32L15xxD device features and
peripheral counts.
Updated Section 3.11: ADC (analog-to-digital converter) to add
Section 3.11.1: Temperature sensor and Section 3.11.2: Internal
voltage reference (VREFINT).
Removed caution note below Figure 11: Power supply scheme.
Added note below Table 4: STM32L15xQD UFBGA132 ballout.
Modified Table 7: STM32L15xRD WLCSP64 ballout to match top
view.
Changed FSMC_LBAR into FSMC_NADV, and I2C1_SMBAI into
I2C1_SMBA in Table 9: STM32L15xxD pin definitions.
15-Jun-2012
4
Modified PB10/11/12 for AFIO4 alternate function, and replaced
LBAR by NADV for AFIO12 in Table 10: Alternate function
input/output.
Updated Table 22: Typical and maximum current consumptions in
Stop mode and added Note 6. Updated Table 23: Typical and
maximum current consumptions in Standby mode. Updated tWUSTOP
in Table 24: Typical and maximum timings in Low power modes.
Updated Table 25: Peripheral current consumption.
Updated Table 57: SPI characteristics, added Note 1 and Note 3, and
applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI)
th(MI), and th(SI)
,
.
Updated IDD maximum value in Table 35: Flash memory and data
EEPROM characteristics.
138/140
Doc ID 022027 Rev 6
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Table 80. Document revision history (continued)
Revision history
Date
Revision
Changes
Updated Features
Updated Figure 1: Ultra-low-power STM32L15xxD block diagram
Added Table 5: Functionalities depending on the working mode (from
Run/active down to standby), and Table 4: CPU frequency range
depending on dynamic voltage scaling
Updated Figure 5: STM32L15xVD LQFP100 pinout
Updated Table 9: STM32L15xxD pin definitions
Added Note 2 in Table 15: Embedded reset and power control block
characteristics
Replaced TBD values in Table 27: Low-speed external user clock
characteristics, Table 35: Flash memory and data EEPROM
characteristics and Table 52: I/O AC characteristics
25-Oct-2012
5
Added Table 58: I2S characteristics, Figure 31: I2S slave timing
diagram (Philips protocol)(1) and Figure 32: I2S master timing
diagram (Philips protocol)(1)
Added Table 59: SDIO characteristics
Added Figure 33: SDIO timings
Updated Section 6.3.9: FSMC characteristics
Updated Table 69: Temperature sensor characteristics
Added Figure 49: Thermal resistance
Removed AHB1/AHB2 and corrected typo on APB1/APB2 in
Figure 1: Ultra-low-power STM32L15xxD block diagram
Updated “OP amp” line in Table 5: Functionalities depending on the
working mode (from Run/active down to standby)
Added IWDG and WWDG rows in Table 5: Functionalities depending
on the working mode (from Run/active down to standby)
Added OneNAND support in Section 3.8: FSMC (flexible static
memory controller)
The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16
MHz)" replaced by "fHSE = fHCLK up to 16 MHz included, fHSE =
fHCLK/2 above 16 MHz (PLL ON)(2)” in table Table 19: Current
consumption in Sleep mode
01-Feb-2013
6
Updated Stop mode current to 1.5 µA in Ultra-low-power platform
Replaced BGA132 by UFBGA132 in Table 2: Ultra-low-power
STM32L15xxD device features and peripheral counts
Replaced BGA132 by UFBGA132 in Figure 4:
STM32L15xQD UFBGA132 ballout
Updated entire Section 7: Package characteristics
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STM32L151xD STM32L152xD
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STMICROELECTR
STM32L151V8H6DTR
Ultra-low-power 32-bit MCU ARM-based Cortex-M3Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM32L151V8H6TR
32-BIT, FLASH, 32MHz, RISC MICROCONTROLLER, PBGA100, 7 X 7 MM, 0.50 MM PITCH, ROHS COMPLIANT, UFBGA-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM32L151V8T6DTR
Ultra-low-power 32-bit MCU ARM-based Cortex-M3Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
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