STM6513 [STMICROELECTRONICS]
Dual push-button Smart ResetTM with dual reset outputs and user-selectable setup delay; 与双复位输出和用户可选的设置延时双按钮式智能ResetTM
| 型号： | STM6513 |
| 厂家： | 
ST |
| 描述： | Dual push-button Smart ResetTM with dual reset outputs and user-selectable setup delay |
| 文件： | 总29页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM6513
Dual push-button Smart
ResetTM with dual reset outputs and user-selectable setup delay
Features
■ Dual Smart Reset push-button inputs with
user-selectable extended reset setup delay (by
three-state input logic): t
= 2, 6, 10 s (min.)
SRC
■ Capacitor-adjustable reset pulse duration
(t
)
REC1
■ Power-on reset
■ Dual reset output (RST1 is active-high, push-
pull type, RST2 is active-low, open-drain)
TDFN8 (DG)
2 mm x 2 mm
■ Factory-programmable thresholds to monitor
V
in the range of 1.575 to 4.625 V typ.
CC
■ Operating voltage 1.0 V (active-low output
valid) to 5.5 V
Applications
■ Low supply current 3 µA
■ Mobile phones, smartphones
■ e-books
■ Operating temperature: industrial grade –40 °C
to +85 °C
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability.
June 2010
Doc ID 16490 Rev 2
1/29
www.st.com
1
Contents
STM6513
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Ground (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
Smart Reset inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
User-programmable Smart Reset delay (TSR pin) . . . . . . . . . . . . . . . . . . 8
Reset outputs (RST1, RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Adjustable output reset timeout period input pin (TREC
) . . . . . . . . . . . 8
ADJ
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
6
7
8
9
10
11
12
13
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STM6513
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
t
REC1
Possible V voltage thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 21
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of figures
STM6513
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Smart Reset delay t
vs. temperature and supply voltage V
,
SRC
CC
TSR = V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SS
Figure 7.
Output reset timeout period t
vs. temperature and supply voltage V
REC2 CC
(t
option E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REC
Figure 8.
Figure 9.
Supply current I vs. temperature and supply voltage V
. . . . . . . . . . . . . . . . . . . . . . . 13
CC
CC
Reset voltage V
(falling) vs. temperature
RST
(threshold option S, 2.925 V typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply voltage V . . . . . . 14
CC
Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply voltage V . . . . . 15
CC
Figure 12. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 18. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STM6513
Description
1
Description
The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken
low simultaneously provide three user-selectable delayed Smart Reset setup time (t
)
SRC
options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when
connected to ground, t
= 2 s; when left open, t
= 6 s; when connected to V
,
SRC
SRC
CC
t
= 10 s (all the times are minimum). There are two reset outputs, both going active
SRC
simultaneously after both the Smart Reset inputs were held active for the selected t
SRC
delay time. The first reset output, RST1, is active-high, push-pull; the second reset output,
RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the
output reset pulses is independently programmable: t
is user-programmable (by
REC1
external capacitor C
), t
is factory-programmed to 210 ms (typ.), with the option of
tREC REC2
360 ms typ. Additionally, the V is monitored and if it drops below the selected V
CC
RST
threshold, both the reset outputs go active and remain so while V is below the V
CC
RST
threshold, plus the defined duration of the reset pulse t
on each output.
REC
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
). Once the valid Smart Reset input levels and setup
SRC
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t ).
REC
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
) causes hard reset of
SRC
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
) options of 2 s, 6 s and 10 s
SRC
(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state
logic. The delayed setup period ignores switch closures shorter than t
unwanted resets.
, thus preventing
SRC
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without internal pull-up resistor or push-pull as output options, with factory-
programmed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V drops below the specified threshold. The
CC
reset output remains asserted for the reset timeout period (t
voltage goes above the specified threshold.
) after the monitored supply
REC
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Description
STM6513
Figure 1.
Logic diagram
V
CC
SR1
TREC
RST1
RST2
ADJ
STM6513
SR0
TSR
V
SS
AM00372
Figure 2.
Pin connections
RST1
1
8
7
V
CC
V
2
SR0
SS
STM
6513
SR1
3
4
6
5
TREC
TSR
ADJ
RST2
AM00373
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STM6513
Device overview
2
Device overview
Table 1.
Symbol
Signal names
Input/output
Description
RST1
RST2
SR0
Output
Output
Input
First reset output, active-high, push-pull.
Second reset output, active-low, open-drain.
Primary push-button Smart Reset input. Active-low.
SR1
Input
Secondary push-button Smart Reset input. Active-low.
A Three-state Smart Reset input delay setup control. When connected
to ground, t
= 2 s; when left open, t
= 6 s; when connected to
SRC
SRC
V
, t
= 10 s (all times are minimum). TSR is a DC-type input,
CC SRC
TSR
Input
Input
intended to be either permanently grounded, permanently connected
to V or permanently left open. If left open, for improved system glitch
CC
immunity it is strongly recommended to connect a 0.1 µF decoupling
ceramic capacitor between the TSR and V pins.
SS
Input pin for t
reset pulse duration adjustment. Connect an
REC1
TREC
external capacitor C
to this pin to determine t
; t
is factory-
ADJ
tREC
REC1 REC2
programmed.
Positive supply voltage input. Power supply for the device and an input
for the monitored supply voltage. A 0.1 µF decoupling ceramic
V
V
Supply
Supply
CC
capacitor is recommended to be connected between V and V
CC
SS
pins.
Ground
SS
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Pin descriptions
STM6513
3
Pin descriptions
3.1
Power supply (VCC)
This pin is used to provide the power to the Smart Reset device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
V
and V pins.
CC
SS
3.2
3.3
Ground (VSS)
This is the ground for the device and all supplies.
Smart Reset inputs (SR0, SR1)
Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at
least t
to activate the reset outputs. When only one Smart Reset input is used, connect
SRC
the unused one permanently to V
.
SS
3.4
User-programmable Smart Reset delay (TSR pin)
Used to allow the user to program the setup time before the push-buttons action is validated
by reset output. Controlled by different voltage levels on the TSR pin: when connected to
ground, t
= 2 s; when left open, t
= 6 s; when connected to V , t
= 10 s
SRC
SRC
CC SRC
(all times are minimum). TSR is a DC-type input, intended to be either permanently
grounded, permanently connected to V or permanently left open. If left open, for improved
CC
system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and V pins.
SS
3.5
3.6
Reset outputs (RST1, RST2)
Reset outputs, RST1 active-high, push-pull type, RST2 active-low, open-drain.
Adjustable output reset timeout period input pin (TRECADJ
)
The output reset timeout period (t
) on RST1 is adjustable by connecting an external
REC1
capacitor C
to the TREC
pin. Calculated t
and C
examples are given in
tREC
ADJ
REC
tREC
Table 2. Refer also to Table 5.
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STM6513
Pin descriptions
Closest common
Table 2.
t
programmed by an ideal external capacitor
REC1
(1)(2)
t
(ms)
REC1
C
value (µF)
tREC
C
value (µF)
tREC
Min.
Typ.
Max.
0.001
0.002
0.01
10
20
15
30
20
40
0.001
0.0022
0.01
100
140
280
560
1120
150
210
420
840
200
280
560
1120
2240
0.014
0.028
0.056
0.112
0.015
0.027
0.056
0.12
1680
1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external tREC programming capacitor
(CtREC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
used and placed as close as possible to the TRECADJ pin. Also an adequate low-leakage PCB
environment should be ensured to prevent tREC accuracy from being affected. A recommended minimum
value of CtREC is 0.001 µF.
2. In case of repeated activations of the internal tREC timer, an interval of 10 ms min. is needed between tREC
intervals to fully discharge CtREC, so that the next tREC1 is as specified.
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Block diagram
STM6513
4
Block diagram
Figure 3.
Block diagram
V
t
CC
RST2
REC2
+
–
t
RST1
REC1
V
REF
I
REF
TREC
ADJ
SR1
SR0
t
SR logic
SRC
Three-state
selector
TSR
Oscillator
AM00374V2
10/29
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STM6513
Block diagram
STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the
microprocessor reset initiated by the STM6513 Smart Reset device:
Figure 4.
Typical application diagram
V
CC
PMU
V
REG
LD00
...
MCU
LD07
Seq.
logic
(PU resistor)
RST_n
PWR
RST
PS_hold
SW
POWER
KEY
PS_hold
100 kΩ
V
REG
GPIO1
GPIOn
RST1 (PP)
RST2 (OD)
Forces PS_hold
high during
reset period
STM6513
TSR
TREC
SR0
SR1
ADJ
KEYn
C
tREC
KEY1
AM00375a
Figure 5.
Timing waveforms
POR initiated
Smart Reset™ initiated
t
SRC
SR0, SR1
t
(210 ms)
t
(210 ms)
REC2
REC2
RST2 (OD)
Factory -
programmed
RST1 (PP)
by C
tREC
t
t
(~1 s)
(~1 s)
REC1
REC1
AM00376V2
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Typical operating characteristics
STM6513
5
Typical operating characteristics
Figure 6.
Smart Reset delay t
vs. temperature and supply voltage V
,
CC
SRC
TSR = V
SS
3
2.9
2.8
2.7
2.6
2.5
[s]
t
SRC
2.4
2.3
2.2
2.1
2
–60
–40
–20
0
20
40
Temperature [˚C]
5.5 V 3.3 V
60
80
100
120
140
AM00632
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STM6513
Typical operating characteristics
vs. temperature and supply voltage
Figure 7.
Output reset timeout period t
REC2
V
(t
option E)
CC REC
280
260
240
220
200
180
160
[ms]
t
REC2
140
–20
–60
–40
0
20
40
Temperature [˚C]
5.5 V 3.3 V
60
80
100
120
140
AM00633
Figure 8.
Supply current I vs. temperature and supply voltage V
CC
CC
6
5
4
3
2
1
I
[µA]
CC
0
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
5.5 V
3.3 V
AM00634
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Typical operating characteristics
STM6513
Figure 9.
Reset voltage V
(falling) vs. temperature
RST
(threshold option S, 2.925 V typ.)
2.96
2.95
2.94
2.93
V
,
falling [V]
RST
2.92
2.91
2.9
2.89
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
AM00635
Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply
voltage V
CC
10
8
6
4
2
I
,
[µA]
–60
LI(TSR) LO
0
–40
–20
0
20
40
60
80
100
120
140
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V 3.3 V
2 V
AM00636
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STM6513
Typical operating characteristics
Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply
voltage V
CC
10
8
6
4
2
[µA]
–60
I
,
0
LI(TSR) HI
–40
–20
0
20
40
60
80
100
120
140
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V 3.3 V
2 V
AM00637
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Maximum rating
STM6513
6
Maximum rating
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
T
Storage temperature (V off)
–55 to +150
260
°C
°C
STG
(1)
CC
T
Lead solder temperature for 10 seconds
Thermal resistance (junction to ambient)
Input or output voltage
SLD
TDFN8
149.0
°C/W
V
θ
JA
(2)
V
–0.3 to 5.5
IO
V
Supply voltage
–0.3 to 7
V
CC
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 s.
2. For RST1 –0.3 to VCC +0.3 V only.
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STM6513
DC and AC parameters
7
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the Table 5: DC and AC characteristics that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4.: Operating and measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and measurement conditions
Parameter Value
supply voltage
Unit
V
1.0 to 5.5
–40 to +85
≤ 5
V
°C
ns
V
CC
Ambient operating temperature (T )
A
Input rise and fall times
Input pulse voltages
0.2 to 0.8 V
0.3 to 0.7 V
CC
CC
Input and output timing ref. voltages
V
Figure 12. AC testing input/output waveforms
0.8 V
CC
0.7 V
CC
0.2 V
0.3 V
CC
CC
AM00478
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DC and AC parameters
STM6513
Units
Table 5.
Symbol
DC and AC characteristics
(1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Reset output valid - active-low
1.0
1.2
5.5
5.5
5
V
V
V
Supply voltage range
CC
Reset output valid - active-high
(3)
V
V
V
V
V
V
V
V
= 3.0 V, TSR left open
= 5.0 V, TSR left open
≥ 4.5 V, sinking 3.2 mA
≥ 3.3 V, sinking 2.5 mA
≥ 1.0 V, sinking 0.1 mA
3
4
µA
µA
V
CC
CC
CC
CC
CC
CC
CC
CC
I
Supply current (V
)
CC
CC
6
0.3
0.3
0.3
Reset output voltage
low
V
V
OL
V
≥ 4.5 V, I
≥ 2.7 V, I
≥ 1.2 V, I
= 0.8 mA
0.8 V
V
SOURCE
SOURCE
SOURCE
CC
Reset output voltage
high, RST1
V
= 0.5 mA
0.8 V
0.8 V
V
OH
CC
CC
= 0.05 mA
V
Fixed voltage trip
–40 to +85 °C
V
V
–2.5%
V
V
V
V
+2.5%
RST
V
RST
RST
point for V
CC
V
RST
monitoring (refer to
Table 6)
25 °C
–2.0%
+2.0%
RST
V
RST
RST
L, M
0.5%
1%
V
Hysteresis of V
RST
HYST
T, S, R, Z, Y, W, V
V
to (V
falling from (V
+ 100 mV)
RST
(4)
CC
V
to reset delay
20
µs
CC
- 100 mV) at 10 mV/µs
RST
Output reset timeout Option E
period on RST2,
factory-programmed
140
210
360
280
ms
ms
t
t
REC2
Option F
240
480
User-adjustable
output reset timeout
period on RST1
Refer to Table 2.
10 000 x
15 000 x
20 000 x
ms
REC1
C
(µF)
C
(µF)
C
(µF)
tREC
tREC
tREC
18/29
Doc ID 16490 Rev 2
STM6513
DC and AC parameters
Table 5.
Symbol
DC and AC characteristics (continued)
(1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Units
Smart Reset inputs (SRx)
TSR = V
2
6
2.5
7.5
3
9
s
s
s
SS
t
Smart Reset delay
TSR = floating
SRC
TSR = V
10
12.5
15
CC
SR0, SR1 input
voltage low
V
V
–0.3
0.3 V
CC
V
V
s
IL
SS
SR0, SR1 input
voltage high
V
0.7 V
5.5
IH
CC
Input glitch
Corresponds to the actual t
t
(5)
SRC
SRC
immunity
Input leakage
current (SR0, SR1
pins)
I
–1
–5
1
µA
µA
LI(SR)
Input leakage
current (TSR pin)
I
7
LI(TSR)
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 V to 5.5 V (except where noted).
2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.
3. For devices with VRST < 3.0 V.
4. Guaranteed by design.
5. Input glitch immunity is equal to tSRC (when both SR inputs are low), otherwise infinite.
Table 6.
Possible V voltage thresholds
CC
2.5% (–40 °C to +85 °C)
2.0% (25 °C)
V
monitoring
CC
Typ.
Unit
threshold V
RST
Min.
Max.
Min.
Max.
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
4.509
4.266
2.998
2.852
2.559
2.255
2.133
1.623
1.536
4.741
4.484
3.152
2.998
2.691
2.371
2.243
1.707
1.614
4.533
4.288
3.014
2.867
2.573
2.267
2.144
1.632
1.544
4.718
4.463
3.137
2.984
2.678
2.359
2.232
1.698
1.607
V
V
V
V
V
V
V
V
V
Doc ID 16490 Rev 2
19/29
Package mechanical data
STM6513
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch
D
A
B
PIN 1 INDEX AREA
E
2x
C
0.10
0.10 C 2x
TOP VIEW
0.10
C
A
C
A1
SEATING
PLANE
SIDE VIEW
e
0.08
C
b
PIN 1 INDEX AREA
0.10
C A B
1
4
Pin#1 ID
L
5
8
BOTTOM VIEW
TDFN-8L
20/29
Doc ID 16490 Rev 2
STM6513
Package mechanical data
Table 7.
Symbol
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data
Dimension (mm)
Dimension (inches)
Min.
Nom.
Max.
Min.
Nom.
Max.
A
A1
b
0.70
0.00
0.15
0.75
0.02
0.20
0.80
0.05
0.25
0.028
0.000
0.006
0.030
0.001
0.008
0.031
0.002
0.010
D
1.9
1.9
2.00
2.00
2.1
2.1
0.075
0.075
0.079
0.079
0.083
0.083
BSC
E
BSC
e
L
0.50
0.55
0.020
0.022
0.45
0.65
0.018
0.026
Doc ID 16490 Rev 2
21/29
Package footprint
STM6513
9
Package footprint
Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E
E1
L
b
AM00441
Table 8.
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Description
Parameter
Min.
Nom.
Max.
L
b
Contact length
1.05
0.25
—
1.15
0.30
—
—
—
Contact width
E
Max. land pattern Y-direction
Contact gap spacing
Max. land pattern X-direction
Contact pitch
2.85
0.65
1.75
0.5
E1
D
P
—
—
—
—
—
—
22/29
Doc ID 16490 Rev 2
STM6513
Tape and reel information
10
Tape and reel information
Figure 15. Carrier tape
P
0
D
P
2
T
E
A
0
F
Top cover
tape
W
B
0
Center lines
of cavity
K
0
P
1
User direction of feed
AM03073v2
Table 9.
Package
Carrier tape dimensions
Bulk
qty.
W
D
E
P
P
F
A
B
K
P
1
T
Unit
0
2
0
0
0
8.00
+0.30 +0.10/
–0.10 –0.00
1.50
1.75
0.10
4.00
0.10
2.00
0.10
3.50
0.05
2.30
0.05
2.30
0.05
1.00
0.05
4.00 0.250
0.10 0.05
TDFN8
mm 3000
Doc ID 16490 Rev 2
23/29
Tape and reel information
STM6513
Figure 16. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
AM00443
Table 10.
Tape sizes
Reel dimensions
A max.
B min.
C
D min.
N min.
G
T max.
8 mm
180 (7 inches)
1.50
13.0 +/– 0.20
20.20
60
8.4 +2/–0 14.40
24/29
Doc ID 16490 Rev 2
STM6513
Tape and reel information
Figure 17. Tape trailer/leader
End
Start
Top
cover
tape
No components
Components
100 mm min. No components
T RA IL ER
L EA D ER
400 mm min.
160 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 18. Pin 1 orientation
User direction of feed
AM00442
Note:
1
2
Drawings are not to scale.
All dimensions are in mm, unless otherwise noted.
Doc ID 16490 Rev 2
25/29
Part numbering
STM6513
11
Part numbering
Table 11.
Ordering information scheme
Example:
STM6513
V
E
I
E
DG
6
F
Device type
STM6513
Reset (V monitoring threshold) voltage V
CC
RST
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset setup delay (t
);
SRC
presence of internal input pull-up on all Smart Reset inputs (SR0, SR1)
E = 2 or 6 or 10 s min., user-programmed (three-state); no input pull-up
Outputs type
I = RST1 active-high, push-pull, RST2 active-low, open-drain, no pull-up
Reset timeout period (t
)
REC
E = t
F = t
user-programmable (external capacitor), t
factory-programmed (210 ms typ.)
factory-programmed (360 ms typ.)
REC1
REC1
REC2
REC2
user-programmable (external capacitor), t
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
®
F = ECOPACK package, tape and reel
For other options, voltage threshold values etc. or for more information on any aspect of this device,
please contact the ST sales office nearest you.
26/29
Doc ID 16490 Rev 2
STM6513
Package marking information
12
Package marking information
Table 12.
Package marking
t
Smart
Reset
RST1
output
type
SRC
t
RST2 output
type
t
REC2
option
REC1
Full part number
delay
control inputs type
V
Topmark
RST
programming
STM6513VEIEDG6F
STM6513SEIEDG6F
STM6513REIEDG6F
TSR
TSR
TSR
AL, NPU
AL, NPU
AL, NPU
V
S
R
AH, PP
AH, PP
AH, PP
C
C
C
AL, OD, NPU
AL, OD, NPU
AL, OD, NPU
E
E
E
9AH
9SH
9RH
tREC
tREC
tREC
Note:
AL = active-low, AH = active-high; PP = push-pull, OD = open-drain, PU = internal pull-up
resistor, NPU = no internal pull-up resistor.
Figure 19. Package marking area, top view
A
B
E
C
D
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
Doc ID 16490 Rev 2
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Revision history
STM6513
13
Revision history
Table 13.
Date
Document revision history
Revision
Changes
22-Oct-2009
1
Initial release.
Updated title, Features, Applications, replaced “smart reset” by
“Smart Reset™” and “Smart Reset”, updated Section 1, Table 1,
Section 3, Table 2, Figure 3, Figure 5, Figure 6, Table 3, Table 5 to
Table 8, Table 11 and Table 12.
21-Jun-2010
2
28/29
Doc ID 16490 Rev 2
STM6513
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