STM704M6F_技术文档

STM690A, STM692A, STM703

STM704, STM802, STM805, STM817/8/9

5V Supervisor with Battery Switchover

FEATURES SUMMARY

■

5V OPERATING VOLTAGE

Figure 1. Packages

■

NVRAM SUPERVISOR FOR EXTERNAL

LPSRAM

■

CHIP-ENABLE GATING (STM818 only) FOR

EXTERNAL LPSRAM (7ns max PROP

DELAY)

8

■

RST AND RST OUTPUTS

200ms (TYP) t

rec

1

WATCHDOG TIMER - 1.6sec (TYP)

AUTOMATIC BATTERY SWITCHOVER

LOW BATTERY SUPPLY CURRENT - 0.4µA

(TYP)

SO8 (M)

■

POWER-FAIL COMPARATOR (PFI/PFO)

LOW SUPPLY CURRENT - 40µA (TYP)

GUARANTEED RST (RST) ASSERTION

DOWN TO V = 1.0V

CC

TSSOP8 3x3 (DS)*

■

OPERATING TEMPERATURE:

–40°C to 85°C (Industrial Grade)

RoHS COMPLIANCE

Lead-free components are compliant with the

RoHS Directive.

Table 1. Device Options

Active-

Low

Active-

High

Manual

Reset

Input

Battery

Switch-

over

Chip-

Enable

Gating

Battery

Freshness

Seal

Watchdog

Input

Power-fail

Comparator

(1)

RST

STM690A

STM692A

STM703

■

STM704

STM802L/M

STM805L

■

STM817L/M

STM818L/M

STM819L/M

■

Note: 1. All RST and RST outputs are push-pull.

* Contact local ST sales office for availability.

January 2006

Rev 7.0

1/37

STM690A/692A/703/704/802/805/817/818/819

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5. STM690A/692A/802/805/817 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. STM703/704/819 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 8. Block Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog Input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable Input (STM818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.Power-fail Comparator Waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . 13

Using a SuperCap™ as a Backup Power Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Negative-Going V Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Battery Freshness Seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.V -to-V

On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUT

CC

Figure 19.V

-to-V

On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUT

BAT

2/37

STM690A/692A/703/704/802/805/817/818/819

Figure 20.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 21.Battery Current vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 22.V

Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PFI

Figure 23.Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819) 17

Figure 24.Reset Comparator Propagation Delay vs. Temperature (V =3.0V; STM817/818/819)18

BAT

Figure 25.Power-up t vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

rec

Figure 26.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 27.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 28.E to E

On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CON

Figure 29.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 30.Output Voltage vs. Load Current (V = 5V; V

= 2.8V; T = 25°C). . . . . . . . . . . . . . 21

A

CC

BAT

Figure 31.Output Voltage vs. Load Current (V = 0V; V

= 2.8V; T = 25°C). . . . . . . . . . . . . . 21

A

CC

Figure 32.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 33.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 34.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 35.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 36.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 37.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 38.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 25

Figure 39.E to E

Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CON

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 40.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 41.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 42.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 43.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 44.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 32

Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 32

Figure 45.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 33

Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 33

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3/37

STM690A/692A/703/704/802/805/817/818/819

SUMMARY DESCRIPTION

The STM690A/692A/703/704/802/805/817/818/

819 Supervisors are self-contained devices which

provide microprocessor supervisory functions with

the ability to non-volatize and write-protect exter-

nal LPSRAM. A precision voltage reference and

offer a watchdog timer (except for STM703/704/

819) as well as a power-fail comparator (except for

STM818) to provide the system with an early

warning of impending power failure.

These devices are available in a standard 8-pin

SOIC package or a space-saving 8-pin TSSOP

package.

comparator monitors the V

tolerance condition. When an invalid V

input for an out-of-

CC

condi-

CC

tion occurs, the reset output (RST) is forced low

(or high in the case of RST). These devices also

Figure 2. Logic Diagram (STM690A/692A/802/

805/817)

Figure 4. Logic Diagram (STM818)

V

BAT

CC

V

BAT

CC

V

OUT

WDI

E

V

OUT

RST

STM818

WDI

PFI

STM690A/

692A/802/

805/817

(1)

RST(RST)

E

CON

PFO

V

SS

AI07896

V

SS

AI07894

Note: 1. For STM805, reset output is active-high.

Table 2. Signal Names

MR

WDI

RST

Push-button Reset Input

Watchdog Input

Figure 3. Logic Diagram (STM703/704/819)

V

BAT

Active-Low Reset Output

Active-High Reset Output

Chip Enable Input

CC

(1)

E

V

OUT

MR

PFI

STM703/

704/819

(1)

Conditioned Chip Enable Output

E

CON

RST

PFO

V

Supply Voltage Output

Supply Voltage

OUT

V

CC

V

Back-up Supply Voltage

Power-fail Input

Power-fail Output

Ground

BAT

V

SS

AI07895

PFI

PFO

V

SS

Note: 1. STM818

4/37

STM690A/692A/703/704/802/805/817/818/819

Figure 5. STM690A/692A/802/805/817

Connections

Figure 6. STM703/704/819 Connections

SO8/TSSOP8

V

BAT

OUT

1

2

3

4

8

7

6

5

V

BAT

V

OUT

1

2

3

4

8

7

6

5

RST

MR

CC

(1)

V

RST(RST)

WDI

V

CC

SS

V

SS

PFI

PFO

PFI

PFO

AI07890

AI07889

Note: 1. For STM805, reset output is active-high.

Figure 7. STM818 Connections

SO8/TSSOP8

V

BAT

OUT

1

2

3

4

8

7

6

5

V

CC

RST

WDI

E

V

SS

E

CON

AI07892

5/37

STM690A/692A/703/704/802/805/817/818/819

Pin Descriptions

MR. A logic low on /MR asserts the reset output.

Reset remains asserted as long as MR is low and

V

. When V is above the switchover voltage

OUT CC

(V ), V

is connected to V

through a P-

SO

OUT

CC

for t after MR returns high. This active-low input

channel MOSFET switch. When V

falls below

CC

rec

has an internal pull-up. It can be driven from a TTL

or CMOS logic line, or shorted to ground with a

switch. Leave open if unused.

V

, V

SO BAT

connects to V

. Connect to V if no

OUT CC

battery is used.

V

. When V

BAT

falls below V , V

switches

OUT

CC

SO

WDI. If WDI remains high or low for 1.6sec, the in-

ternal watchdog timer runs out and reset is trig-

gered. The internal watchdog timer clears while

reset is asserted or when WDI sees a rising or fall-

ing edge.

from V

hysteresis, V

ceed V . Connect to V if no battery is used.

E. The input to the chip-enable gating circuit. Con-

to V

. When V

reconnects to V . V

rises above V

+

CC

BAT

CC

SO

may ex-

OUT

CC BAT

CC

nect to ground if unused.

The watchdog function can be disabled by allow-

ing the WDI pin to float.

E

. E

goes low only when E is low and re-

CON

set is not asserted. If E

is low when reset is as-

CON

RST. Pulses low for t when triggered, and stays

serted, E

will remain low for 15µs or until E

rec

CON

low whenever V

is below the reset threshold or

goes high, whichever occurs first. In the disabled

CC

when MR is a logic low. It remains low for t after

mode, E is pulled up to V

.

OUT

rec

CON

either V

rises above the reset threshold, the

CC

PFI. When PFI is less than V

or when V falls

CC

PFI

watchdog triggers a reset, or MR goes from low to

high.

below 2.4V (or V ), PFO goes low; otherwise,

SO

PFO remains high. Connect to ground if unused.

RST. Pulses high for t

stays high whenever V

when triggered, and

is above the reset

rec

CC

PFO. When PFI is less than V , or V falls be-

PFI

CC

low 2.4V (or V ), PFO goes low; otherwise, PFO

SO

threshold or when MR is a logic high. It remains

high for t after either V falls below the reset

remains high. Leave open if unused.

rec

CC

threshold, the watchdog triggers a reset, or MR

goes from high to low.

Table 3. Pin Description

Name

Function

STM690A

STM692A

STM802

STM817

STM703

STM704

STM819

STM818

STM805

–

6

7

–

1

2

8

4

5

–

3

–

6

7

–

1

2

8

–

4

5

3

6

–

7

–

1

2

8

–

4

5

3

–

6

–

7

1

2

8

–

4

5

3

MR

Push-button Reset Input

WDI Watchdog Input

RST Active-Low Reset Output

RST Active-High Reset Output

V

OUT

Supply Output for External LPSRAM

Supply Voltage

V

CC

V

Backup-Battery Input

BAT

E

Chip Enable Input

E

CON

Conditioned Chip Enable Output

PFI Power-fail Input

PFI

PFO PFO Power-fail Output

V

SS

Ground

6/37

STM690A/692A/703/704/802/805/817/818/819

Figure 8. Block Diagram (STM690A/692A/802/805/817)

V_CC

V_OUT

V_BAT

COMPARE

V_SO

V_RST

t_rec

Generator

RST(RST)⁽¹⁾

WATCHDOG

TIMER

WDI

PFI

V_PFI

COMPARE

PFO

AI07897

Note: 1. For STM805, reset output is active-high.

Figure 9. Block Diagram (STM703/704/819)

V_CC

V_OUT

V_BAT

COMPARE

V_SO

COMPARE

V_RST

t_rec

Generator

RST

MR

PFI

V_PFI

COMPARE

PFO

AI07898

7/37

STM690A/692A/703/704/802/805/817/818/819

Figure 10. Block Diagram (STM818)

V_CC

V_OUT

V_BAT

COMPARE

V_SO

V_RST

t_rec

Generator

WATCHDOG

TIMER

RST

WDI

E_CONOUTPUT

CONTROL

E

E_CON

AI07899a

Figure 11. Hardware Hookup

Regulator

V_INV_CC

Unregulated

Voltage

V_CC

V_OUT

V_CC

LPSRAM

STM690A/692A/

703/704/802/805/

817/818/819

0.1µF

E

0.1µF

WDI⁽¹⁾

From Microprocessor

E⁽²⁾

(2)

E_CON

R1

R2

PFI⁽³⁾

MR⁽⁴⁾

V_BAT

PFO⁽³⁾

RST

To Microprocessor NMI

To Microprocessor Reset

Push-Button

AI07893

Note: 1. For STM690A/692A/802/805/817/818.

2. For STM818 only.

3. Not available on STM818.

4. For STM703/704/819.

8/37

STM690A/692A/703/704/802/805/817/818/819

OPERATION

Reset Output

The STM690A/692A/703/704/802/805/817/818/

819 Supervisor asserts a reset signal to the MCU

not required. If MR is driven from long cables or

the device is used in a noisy environment, connect

a 0.1µF capacitor from MR to GND to provide ad-

ditional noise immunity. MR may float, or be tied to

whenever V

goes below the reset threshold

CC

(V ), a watchdog time-out occurs, or when the

RST

Push-button Reset Input (MR) is taken low. RST is

guaranteed to be a logic low (logic high for

V

when not used.

CC

Watchdog Input (NOT available on STM703/

704/819)

The watchdog timer can be used to detect an out-

of-control MCU. If the MCU does not toggle the

Watchdog Input (WDI) within t

reset is asserted. The internal watchdog timer is

cleared by either:

STM805) for 0V < V

< V

if V

is greater

CC

RST

BAT

than 1V. Without a back-up battery, RST is guar-

anteed valid down to V =1V.

CC

During power-up, once V

exceeds the reset

CC

(1.6sec typ), the

WD

threshold an internal timer keeps RST low for the

reset time-out period, t . After this interval RST

rec

returns high.

1. a reset pulse, or

If V drops below the reset threshold, RST goes

CC

2. by toggling WDI (high-to-low or low-to-high),

which can detect pulses as short as 50ns. If

WDI is tied high or low, a reset pulse is

low. Each time RST is asserted, it stays low for at

least the reset time-out period (t ). Any time V

rec

CC

goes below the reset threshold the internal timer

triggered every 1.8sec (t

+ t ).

WD

rec

clears. The reset timer starts when V

above the reset threshold.

returns

CC

The timer remains cleared and does not count for

as long as reset is asserted. As soon as reset is re-

leased, the timer starts counting (see Figure

43., page 28).

Note: The watchdog function may be disabled by

floating WDI or tri-stating the driver connected to

WDI. When tri-stated or disconnected, the maxi-

mum allowable leakage current is 10uA and the

maximum allowable load capacitance is 200pF.

Push-button Reset Input (STM703/704/819)

A logic low on MR asserts reset. Reset remains

asserted while MR is low, and for t (see Figure

rec

42., page 28) after it returns high. The MR input

has an internal 40kΩ pull-up resistor, allowing it to

be left open if not used. This input can be driven

with TTL/CMOS-logic levels or with open-drain/

collector outputs. Connect a normally open mo-

mentary switch from MR to GND to create a man-

ual reset function; external debounce circuitry is

Note: Input frequency greater than 20ns (50MHz)

will be filtered.

9/37

STM690A/692A/703/704/802/805/817/818/819

Back-up Battery Switchover

Chip-Enable Gating (STM818 only)

In the event of a power failure, it may be necessary

to preserve the contents of external SRAM

Internal gating of the chip enable (E) signal pre-

vents erroneous data from corrupting the external

CMOS RAM in the event of an undervoltage con-

dition. The STM818 uses a series transmission

through V

. With a backup battery installed with

, the devices automatically switch the

OUT

voltage V

BAT

SRAM to the back-up supply when V falls.

Note: If back-up battery is not used, connect both

gate from E to E

(see Figure 12., page 11).

CC

CON

During normal operation (reset not asserted), the

E transmission gate is enabled and passes all E

transitions. When reset is asserted, this path be-

comes disabled, preventing erroneous data from

corrupting the CMOS RAM. The short E propaga-

V

and V

to V

.

BAT

OUT

CC

This family of Supervisors does not always con-

nect V to V when V is greater than V

.

CC

BAT

OUT

BAT

V

connects to V

CC

(through a 100Ω switch)

BAT

OUT

RST

tion delay from E to E

enables the STM818 to

CON

when V is below V

and V

. This is done to

BAT

be used with most µPs. If E is low when reset as-

serts, E remains low for typically 15µs to per-

allow the back-up battery (e.g., a 3.6V lithium cell)

to have a higher voltage than V

CON

.

CC

mit the current WRITE cycle to complete. Connect

Assuming V

> 2.0V, switchover at V ensures

SO

BAT

E to V if unused.

SS

that battery back-up mode is entered before V

gets too close to the 2.0V minimum required to re-

liably retain data in most external SRAMs. When

OUT

Chip Enable Input (STM818 only)

The chip-enable transmission gate is disabled and

E is high impedance (disabled mode) while reset

is asserted. During a power-down sequence when

V

recovers, hysteresis is used to avoid oscilla-

CC

tion around the V

point. V

is connected to

SO

OUT

V

passes the reset threshold, the chip-enable

CC

V

through a 3Ω PMOS power switch.

CC

transmission gate disables and E immediately be-

comes high impedance if the voltage at E is high.

If E is low when reset asserts, the chip-enable

transmission gate will disable 15µs after reset as-

serts (see Figure 13., page 11). This permits the

current WRITE cycle to complete during power-

down.

Note: The back-up battery may be removed while

is valid, assuming V is adequately decou-

pled (0.1µF typ), without danger of triggering a re-

set.

V

CC

BAT

Table 4. I/O Status in Battery Back-up

Any time a reset is generated, the chip-enable

transmission gate remains disabled and E remains

high impedance (regardless of E activity) for the

reset time-out period. When the chip enable trans-

mission gate is enabled, the impedance of E ap-

pears as a 40Ω resistor in series with the load at

Status

V

OUT

Connected to V

through internal switch

BAT

V

Disconnected from V

Disabled

CC

PFI

PFO

E

OUT

E

. The propagation delay through the chip-en-

CON

Logic low

able transmission gate depends on V , the

CC

source impedance of the drive connected to E,

High impedance

Logic high

and the loading on E

. The chip enable propa-

CON

E

CON

gation delay is production tested from the 50%

point on E to the 50% point on E using a 50Ω

CON

WDI

Watchdog timer is disabled

driver and a 50pF load capacitance (see Figure

40., page 28). For minimum propagation delay,

WDO Logic low

minimize the capacitive load at E

low-output impedance driver.

and use a

CON

MR

RST

Disabled

Logic low

Chip Enable Output (STM818 only)

When the chip-enable transmission gate is en-

abled, the impedance of E is equivalent to a

Logic high

Connected to V

CON

V

BAT

OUT

40Ω resistor in series with the source driving E. In

the disabled mode, the transmission gate is off

and an active pull-up connects E

to V

(see

CON

OUT

Figure 12., page 11). This pull-up turns off when

the transmission gate is enabled.

10/37

STM690A/692A/703/704/802/805/817/818/819

Figure 12. Chip-Enable Gating

V_CC

t_rec

Generator

RST

COMPARE

V_RST

V_OUT

E_CONOUTPUT

CONTROL

E

E_CON

AI08802

Figure 13. Chip Enable Waveform

V_CC

V_RST

V_BAT

E_CON

trec

15µs

trec

RST

E

AI08803b

11/37

STM690A/692A/703/704/802/805/817/818/819

Power-fail Input/Output (NOT available on STM818)

The Power-fail Input (PFI) is compared to an inter-

During battery back-up, the power-fail comparator

turns off and PFO goes (or remains) low (see Fig-

ure 14 and Figure 15., page 13). This occurs after

nal reference voltage (independent from the V

RST

comparator). If PFI is less than the power-fail

threshold (V ), the Power-Fail Output (PFO) will

V

drops below 2.4V (or V ). When power re-

PFI

CC SO

go low. This function is intended for use as an un-

dervoltage detector to signal a failing power sup-

ply. Typically PFI is connected through an external

voltage divider (see Figure 11., page 8) to either

the unregulated DC input (if it is available) or the

turns, PFO is forced high (STM817/819 only), irre-

spective of V for the WRITE protect time (t ).

At the end of this time, the power-fail comparator

is enabled and PFO follows PFI. If the comparator

PFI

rec

is unused, PFI should be connected to V

and

SS

regulated output of the V regulator. The voltage

divider can be set up such that the voltage at PFI

PFO left unconnected. PFO may be connected to

MR on the STM703/704/818 so that a low voltage

on PFI will generate a reset output.

CC

falls below V

several milliseconds before the

PFI

regulated V

input to the STM690A/692A/703/

CC

Applications Information

These Supervisor circuits are not short-circuit pro-

704/802/805/817/818/819 Supervisor or the mi-

croprocessor drops below the minimum operating

voltage.

tected. Shorting V

to ground - excluding pow-

OUT

er-up transients such as charging a decoupling

capacitor - destroys the device. Decouple both

V

and V

pins to ground by placing 0.1µF ca-

BAT

CC

pacitors as close to the device as possible.

Figure 14. Power-fail Comparator Waveform (STM817/818/819)

V_CC

V_RST

V_SO(or 2.4V)

trec

PFO

(STM817/819)

PFO follows PFI

RST to E_CONDelay (STM818)

RST

E_CON(STM818)

AI08804a

12/37

STM690A/692A/703/704/802/805/817/818/819

Figure 15. Power-fail Comparator Waveform (STM690A/692A/703/704/802/805)

V_CC

V_RST

2.4V (or V_SO

)

trec

PFO

PFO follows PFI

RST

AI08832a

13/37

STM690A/692A/703/704/802/805/817/818/819

Using a SuperCap™ as a Backup Power

Source

Use the same procedure for the STM818, but

ground E instead of PFO. Once the battery

freshness seal is enabled (disconnecting the

back-up battery from internal circuitry and any-

CON

SuperCaps™ are capacitors with extremely high

capacitance values (e.g., order of 0.47F) for their

size. Figure 16 shows how to use a SuperCap as

a back-up power source. The SuperCap may be

connected through a diode to the 5V input. Since

thing connected to V

), it remains enabled until

OUT

V

is brought above V

.

CC

RST

V

can exceed V while V is above the reset

BAT

CC CC

Figure 16. Using a SuperCap™

threshold, there are no special precautions when

using these supervisors with a SuperCap.

5V

Negative-Going V Transients

CC

The STM690A/692A/703/704/802/805/817/818/

819 Supervisor are relatively immune to negative-

V_CC

V_OUT

To external SRAM

going

V

transients

(glitches).

Figure

CC

38., page 25 shows typical transient duration ver-

sus reset comparator overdrive (for which the

STM690A/692A/703/704/802/805/817/818/819

will NOT generate a reset pulse). The graph was

STMXXX

V_BAT

RST

To µP

generated using a negative pulse applied to V

,

CC

GND

starting at V

+ 0.3V and ending below the reset

RST

threshold by the magnitude indicated (comparator

overdrive). The graph indicates the maximum

AI08805

pulse width a negative V

transient can have

CC

without causing a reset pulse. As the magnitude of

the transient increases (further below the thresh-

old), the maximum allowable pulse width decreas-

es. Any combination of duration and overdrive

which lies under the curve will NOT generate a re-

Figure 17. Freshness Seal Enable Waveform

set signal. Typically, a V

100mV below the reset threshold and lasts 40µs or

less will not cause a reset pulse. A 0.1µF bypass

capacitor mounted as close as possible to the V

pin provides additional transient immunity.

transient that goes

CC

V_RST

V_CC

CC

trec

Battery Freshness Seal (STM817/818/819)

RST

The battery freshness seal disconnects the back-

up battery from internal circuitry and V until it is

needed. This allows an OEM to ensure that the

E_CONout state latched

OUT

at 1/2 t_rec

,

Freshness

(Externally held at 0V)

Seal enabled

E_CON

back-up battery connected to V will be fresh

BAT

(STM818)

PFO out state latched

when the final product is put to use. To enable the

freshness seal:

at 1/2 t_rec

,

Freshness

Seal Enabled

(Externally held at 0V)

PFO

1. Connect a battery to V

2. Ground PFO;

;

BAT

(STM817/819)

AI08806

3. Bring V above the reset threshold and hold

CC

it there until reset is deasserted following the

reset timeout period; and

4. Bring V down again (Figure 17).

CC

14/37

STM690A/692A/703/704/802/805/817/818/819

TYPICAL OPERATING CHARACTERISTICS

Note: Typical values are at T = 25°C

A

Figure 18. V -to-V

On-Resistance vs. Temperature

OUT

CC

5.0

4.0

3.0

2.0

1.0

V

= 3.0V

= 4.5V

= 5.5V

CC

0.0

0

20

40

60

80

100

120

–40

–20

Temperature (°C)

AI10498

Figure 19. V

-to-V

BAT

On-Resistance vs. Temperature

OUT

160

140

120

100

80

60

V

= 2.0V

BAT

= 3.0V

= 3.3V

= 3.6V

40

20

0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09140b

15/37

STM690A/692A/703/704/802/805/817/818/819

Figure 20. Supply Current vs. Temperature (no load)

30

25

20

15

10

5

V

= 2.7V

= 3.0V

= 3.6V

= 4.5V

= 5.5V

CC

0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09141b

Figure 21. Battery Current vs. Temperature

1000

100

10

V

= 2.0V

BAT

= 3.0V

= 3.6V

1

0.1

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI10499

16/37

STM690A/692A/703/704/802/805/817/818/819

Figure 22. V

Threshold vs. Temperature

PFI

1.270

1.265

1.260

1.255

1.250

1.245

1.240

1.235

1.230

1.225

V

= 3.0V

= 4.5V

= 4.75V

= 5.5V

CC

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09142c

Figure 23. Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819)

30

28

26

24

22

20

18

16

14

12

10

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09143b

17/37

STM690A/692A/703/704/802/805/817/818/819

Figure 24. Reset Comparator Propagation Delay vs. Temperature (V

=3.0V; STM817/818/819)

BAT

350

1v/ms

300

250

200

150

100

50

10V/ms

0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI11100

Figure 25. Power-up t

vs. Temperature

rec

240

235

230

225

220

215

210

V

= 3.0V

= 4.5V

= 5.5V

CC

V

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09144b

18/37

STM690A/692A/703/704/802/805/817/818/819

Figure 26. Normalized Reset Threshold vs. Temperature

1.004

1.002

1.000

0.998

0.996

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09145b

Figure 27. Watchdog Time-out Period vs. Temperature

1.90

1.85

1.80

1.75

1.70

1.65

1.60

V

= 3.0V

CC

= 4.5V

= 5.5V

CC

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09146b

19/37

STM690A/692A/703/704/802/805/817/818/819

Figure 28. E to E

On-Resistance vs. Temperature

CON

60

50

40

30

20

10

V

= 3.0V

= 4.5V

= 5.5V

CC

0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09147b

Figure 29. PFI to PFO Propagation Delay vs. Temperature

4.0

V

= 3.0V

= 3.6V

= 4.5V

= 5.5V

CC

3.0

2.0

1.0

0.0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09148b

20/37

STM690A/692A/703/704/802/805/817/818/819

Figure 30. Output Voltage vs. Load Current (V = 5V; V

= 2.8V; T = 25°C)

A

CC

BAT

5.00

4.98

4.96

4.94

0

10

20

30

40

50

I

(mA)

OUT

AI10496

Figure 31. Output Voltage vs. Load Current (V = 0V; V

= 2.8V; T = 25°C)

A

CC

BAT

2.80

2.78

2.76

2.74

2.72

2.70

2.68

2.66

0.0

0.2

0.4

0.6

0.8

1.0

I

(mA)

OUT

AI10497

21/37

STM690A/692A/703/704/802/805/817/818/819

Figure 32. RST Output Voltage vs. Supply Voltage

5

4

3

2

1

0

V

RST

CC

4

3

2

1

0

500ms/div

AI09149b

Figure 33. RST Output Voltage vs. Supply Voltage

5

4

3

2

1

5

V

RST

CC

4

3

2

1

0

500ms/div

AI09150b

22/37

STM690A/692A/703/704/802/805/817/818/819

Figure 34. RST Response Time (Assertion)

5V

1V/div

4V

V

CC

5V

4V

RST

1V/div

0V

5µs/div

AI09151b

23/37

STM690A/692A/703/704/802/805/817/818/819

Figure 35. RST Response Time (Assertion)

5V

4V

V

CC

1V/div

4V

RST

1V/div

0V

5µs/div

AI09152b

Figure 36. Power-fail Comparator Response Time (Assertion)

5V

1V/div

PFO

0V

1.3V

PFI

500mV/div

0V

500ns/div

AI09153b

24/37

STM690A/692A/703/704/802/805/817/818/819

Figure 37. Power-fail Comparator Response Time (De-Assertion)

5V

1V/div

PFO

0V

1.3V

PFI

500mV/div

0V

500ns/div

AI09154b

Figure 38. Maximum Transient Duration vs. Reset Threshold Overdrive

6000

5000

4000

Reset occurs

above the curve.

3000

2000

1000

0

0.001

0.01

0.1

1

10

Reset Comparator Overdrive, V

– V (V)

CC

RST

AI09156b

25/37

STM690A/692A/703/704/802/805/817/818/819

Figure 39. E to E

Propagation Delay vs. Temperature

CON

4.0

3.0

2.0

1.0

V

= 3.0V

= 4.5V

= 5.5V

CC

0.0

–40

–20

0

20

40

60

80

100

120

Temperature (°C)

AI09157b

26/37

STM690A/692A/703/704/802/805/817/818/819

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings” table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 5. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

T

Storage Temperature (V Off)

–55 to 150

°C

STG

CC

Lead Solder Temperature for 10 seconds

Input or Output Voltage

Supply Voltage

(1)

260

°C

V

T

SLD

V

–0.3 to V +0.3

IO

CC

V

/V

–0.3 to 6.0

20

V

CC BAT

I

O

Output Current

mA

mW

P

Power Dissipation

320

D

Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150

seconds).

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 6, Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 6. Operating and AC Measurement Conditions

Parameter

STM690A/692A/703/704/802/

Unit

805/817/818/819

V

/V

Supply Voltage

1.0 to 5.5

–40 to 85

≤ 5

V

°C

ns

V

CC BAT

Ambient Operating Temperature (T )

A

Input Rise and Fall Times

0.2 to 0.8V

Input Pulse Voltages

CC

0.3 to 0.7V

Input and Output Timing Ref. Voltages

V

CC

27/37

STM690A/692A/703/704/802/805/817/818/819

Figure 40. E to ECON Propagation Delay Test Circuit

V_CC

V_BAT

3.6V

STMXXX

25Ω Equivalent

Source Impedance

E

E_CON

50Ω

50Ω Cable

(1)

50pF C_L

50Ω

GND

AI08854

Note: 1. C includes load capacitance and scope probe capacitance.

L

Figure 41. AC Testing Input/Output Waveforms

0.8V

CC

0.7V

0.3V

CC

0.2V

CC

AI02568

Figure 42. MR Timing Waveform

MR

tMLRL

RST ⁽¹⁾

trec

tMLMH

AI07837a

Note: 1. RST for STM805.

Figure 43. Watchdog Timing

V_CC

trec

RST

tWD

WDI

AI07891

28/37

STM690A/692A/703/704/802/805/817/818/819

Table 7. DC and AC Characteristics

Alter-

(1)

Sym

Description

Min

Typ

Max

Unit

Test Condition

native

V

,

CC

(2)

(3)

T = –40 to +85°C

Operating Voltage

5.5

60

35

V

A

1.2

V

BAT

V

Supply Current

Excluding I

(V < 5.5V)

CC

25

µA

CC

OUT

I

CC

(V

BAT

= 2.3V,

Supply Current in

OUT

CC

V

= 2.0V, MR = V

)

Battery Back-up Mode

CC

V

Supply Current in

BAT

(4)

Excluding I

(V

= 3.6V)

0.4

1.0

µA

V

I

OUT

BAT

Battery Back-up Mode

V

0.03

–

V

CC

–

CC

(5)

I

= 5mA

OUT1

0.015

V

0.3

–

V

0.15

–

CC

V

Voltage (Active)

Voltage (Battery

I

= 75mA

V

OUT1

OUT

OUT1

V

CC

–

V

CC

–

(5)

V

I

= 250µA, V > 2.5V

CC

OUT1

0.0015 0.0006

V

BAT

–

V

BAT

–

I

= 250µA, V

= 1mA, V

= 2.3V

BAT

V

OUT2

0.1

0.034

OUT

V

OUT2

Back-up)

V

BAT

–

I

= 2.3V

BAT

V

OUT2

0.14

V

to V

On-resistance

3

4

Ω

CC

OUT

to V

On-resistance

100

125

2

BAT

OUT

4.5V < V < 5.5V

Input Leakage Current (MR)

Input Leakage Current (PFI)

75

300

+25

160

µA

nA

µA

V

CC

0V = V = V

–25

IN

CC

I

LI

WDI = V , time average

120

–15

CC

Input Leakage Current

(6)

(WDI)

WDI = GND, time average

–20

2.0

V

4.5V < V < 5.5V

Input High Voltage (MR)

Input High Voltage (WDI)

Input Low Voltage (MR)

Input Low Voltage (WDI)

IH

CC

V

(max) < V < 5.5V

0.7V

CC

V

IH

RST

CC

V

4.5V < V < 5.5V

0.8

V

IL

CC

V

(max) < V < 5.5V

0.3V

CC

V

RST

CC

V

= V

(max), I

3.2mA

=

Output Low Voltage (PFO,

RST, RST)

CC

RST

SINK

0.3

V

OL

V

CC

= V (max),

RST

Output Low Voltage (E

)

0.2V

CON

CC

I

= 1.6mA, E = 0V

OUT

I

= 50µA, V = 1.0V,

CC

= V , T = 0°C to 85°C

CC A

SINK

0.3

V

BAT

V

OL

Output Low Voltage (RST)

I

= 100µA, V

V

= 1.2V,

SINK

CC

= V

BAT

CC

29/37

STM690A/692A/703/704/802/805/817/818/819

Alter-

native

(1)

Sym

Description

Min

2.4

Typ

Max

Unit

V

Test Condition

I

= 1mA,

(max)

Output High Voltage (RST,

RST)

SOURCE

V

CC

= V

RST

V

= V

(max),

CC

RST

V

OH

Output High Voltage (E

)

0.8V

CC

V

CON

I

= 1.6mA, E = V

CC

OUT

I

V

= 75µA,

SOURCE

0.8V

Output High Voltage (PFO)

Output High Voltage

V

CC

= V

(max)

CC

RST

I

V

= 4µA, V

= 1.1V,

CC

SOURCE

0.8

0.9

V

= V , T = 0°C to 85°C

CC A

BAT

V

OH

I

= 4µA, V

= 1.2V,

CC

SOURCE

V

= V

CC

BAT

I

= 100µA,

V

RST)

Battery Back-up (RST,

SOURCE

OH

0.8V

V

BAT

V

= 0, V

= 2.8V

CC

BAT

V

OHB

I

= 75µA,

SOURCE

V

OH

Battery Back-up (E )

CON

0.8V

V

= 0, V

= 2.8V

BAT

CC

Power-fail Comparator (NOT available on STM818)

All other

versions

1.20

1.25

1.250

2

1.30

V

PFI Falling

(V = 5V)

V

PFI Input Threshold

PFI

CC

STM802

1.225

1.275

PFI to PFO Propagation

Delay

t

µs

PFD

PFO Output Short to

GND Current

I

V = 5V, V

CC PFO

= 0V

0.1

0.75

2.0

mA

SC

Battery Switchover

V

RST

V

RST

V

RST

V

RST

> V

< V

> V

< V

V

BAT

Power-down

Power-up

Battery Back-up

V

RST

(7,8)

Switchover Voltage

V

SO

V

BAT

V

(V < V

& V < V

)

CC

BAT

CC

RST

V

RST

Hysteresis

40

mV

Reset Thresholds

STM690A/703, STM8XXL

STM692A/704, STM8XXM

4.50

4.25

4.65

4.40

25

4.75

4.50

V

(9)

V

Reset Threshold

RST

Reset Threshold Hysteresis

to RST Delay (from

mV

V

CC

STM817/818/819

100

200

µs

V

, V falling at 10V/ms)

RST CC

t

RST Pulse Width

140

280

ms

rec

30/37

STM690A/692A/703/704/802/805/817/818/819

Alter-

native

(1)

Sym

Description

Min

Typ

Max

Unit

Test Condition

Push-button Reset Input (STM703/704/819)

STM703/704

STM819

150

1

ns

µs

ns

kΩ

t

MR

MR Pulse Width

MLMH

STM703/704

STM819

250

t

MRD

MR to RST Output Delay

MLRL

120

100

63

MR Glitch Immunity

MR Pull-up Resistor

STM819

MR = 0V, V = 5V

45

85

CC

Watchdog Timer (NOT available on STM703/704/819)

t

V

(max) < V < 5.5V

Watchdog Timeout Period

WDI Pulse Width

1.12

50

1.60

2.24

s

WD

RST

CC

V

RST

(max) < V < 5.5V

ns

CC

Chip-Enable Gating (STM818 only)

E-to-E Resistance

V

= V

(max)

40

2

150

7

Ω

CON

CC

RST

E-to-E

Propagation Delay

4.5V < V < 5.5V

ns

µs

CON

CC

Reset-to-E

High Delay

(Power-down)

15

CON

V

= 5V, Disable Mode,

CC

E

CON

Short Circuit Current

0.1

0.75

2.0

mA

E = Logic high, E

= 0V

CON

Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.75V to 5.5V for “L” versions; V = 4.5V to 5.5V for “M” ver-

A

CC

sions; and V

= 2.8V (except where noted).

BAT

2. V supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and

CC

RST tested at V

= 3.6V, and V = 5.5V. The state of RST or RST and PFO is tested at V = V (min). Either V or V

BAT

CC CC CC CC BAT

can go to 0V if the other is greater than 2.0V.

3. V (min) = 1.0V for T = 0°C to +85°C.

CC

A

4. Tested at V

= 3.6V, V = 3.5V and 0V.

BAT

CC

5. Guaranteed by design.

6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output device

must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be able

to source and sink at least 200µA when active.

7. When V

8. When V

> V > V

, V

remains connected to V until V drops below V

.

BAT

RST

CC

RST

OUT

CC

RST

> V > V

, V

remains connected to V until V drops below the battery voltage (V

) – 75mV.

BAT

CC

BAT OUT

CC

9. For V falling.

CC

31/37

STM690A/692A/703/704/802/805/817/818/819

PACKAGE MECHANICAL

Figure 44. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing

h x 45˚

A2

A

C

B

ddd

e

D

8

1

E

H

A1

α

L

SO-A

Note: Drawing is not to scale.

Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

mm

Min

1.35

0.10

0.33

0.19

4.80

–

inches

Min

Symb

Typ

–

Max

1.75

0.25

0.51

0.25

5.00

0.10

4.00

–

Typ

Max

0.069

0.010

0.020

0.010

0.197

0.004

0.157

–

A

A1

B

–

0.053

0.004

0.013

0.007

0.189

–

C

–

D

–

ddd

E

–

3.80

–

0.150

–

e

1.27

–

0.050

H

5.80

0.25

0.40

0°

6.20

0.50

0.90

8°

–

0.228

0.010

0.016

0°

0.244

0.020

0.035

8°

h

–

L

–

α

–

N

8

32/37

STM690A/692A/703/704/802/805/817/818/819

Figure 45. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline

D

8

1

5

4

c

E1

E

α

A1

L

A

A2

L1

CP

b

e

TSSOP8BM

Note: Drawing is not to scale.

Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data

mm

Min

–

inches

Min

–

Symb

Typ

–

Max

1.10

0.15

0.95

0.40

0.23

0.10

3.10

–

Typ

–

Max

0.043

0.006

0.037

0.016

0.009

0.004

0.122

–

A

A1

A2

b

–

0.05

0.75

0.25

0.13

–

0.002

0.030

0.010

0.005

–

0.85

–

0.034

–

c

–

CP

D

–

3.00

0.65

4.90

3.00

0.55

0.95

–

2.90

–

0.118

0.026

0.193

0.118

0.022

0.037

–

0.114

–

e

E

4.65

2.90

0.40

–

5.15

3.10

0.70

–

0.183

0.114

0.016

–

0.203

0.122

0.030

–

E1

L

L1

α

0°

6°

0°

6°

N

8

33/37

STM690A/692A/703/704/802/805/817/818/819

PART NUMBERING

Table 10. Ordering Information Scheme

Example:

STM690A

M

6

E

Device Type

STM690A/692A/703/704/802/805/817/818/819

Reset Threshold Voltage

STM690A/703: blank = V

= 4.50V to 4.75V

RST

STM8xxL: L = V

= 4.50V to 4.75V

RST

STM692A/704: blank = V

= 4.25V to 4.50V

RST

STM8xxM: M = V

= 4.25V to 4.50V

RST

Package

M = SO8

(1)

DS = TSSOP8

Temperature Range

6 = –40 to 85°C

Shipping Method

E = ECOPACK Package, Tubes

F = ECOPACK Package, Tape & Reel

Note: 1. Contact local ST sales office for availability.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office

nearest you.

34/37

STM690A/692A/703/704/802/805/817/818/819

Table 11. Marking Description

Part Number

STM690A

STM692A

STM703

Reset Threshold

Package

SO8

Topside Marking

4.65V

4.40V

4.65V

4.40V

4.65V

4.40V

4.65V

690A

692A

703

SO8

STM704

SO8

704

STM802L

STM802M

STM805L

SO8

802L

802M

805L

SO8

STM817L

STM817M

STM818L

STM818M

STM819L

STM819M

4.65V

4.40V

4.65V

4.40V

4.65V

4.40V

817L

817M

818L

818M

819L

819M

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

SO8

TSSOP8

35/37

STM690A/692A/703/704/802/805/817/818/819

REVISION HISTORY

Table 12. Document Revision History

Date

Version

1.0

Revision Details

October 2003

31-Oct-03

First Issue

1.1

Update DC Characteristics (Table 7)

Reformatted; updated characteristics (Figure 1, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15,

17; Table 3, 4, 7, 9, 11)

22-Dec-03

2.0

Add Typical Characteristics (Figure 19, 20, 22, 23, 25, 26, 27, 28, 29, 32, 33, 34,

35, 36, 37, 38, 39)

16-Jan-04

08-Apr-04

25-May-04

2.1

2.2

3.0

Update characteristics (Figure 13, 23, 29, 33, 34, 35, 38; Table 1,7)

Remove references to ‘Open Drain’ (Figure 2, 5, 8; Table 2); update characteristics

(Table 3, 7)

Update package availability, pin description; promote document (Figure 1, 14, 15;

Table 3. 7, 10)

05-Jul-04

29-Sep-04

01-Mar-05

20-Jan-05

4.0

5.0

6.0

7.0

Clarify root part numbers, pin descriptions (Figure 11, 13, 40; Table 7, 10)

Update characteristics (Figure 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,

32, 33, 34, 35, 36, 37, 38, 39)

Correct marking, update Lead-free text (Table 10, 11)

36/37

STM690A/692A/703/704/802/805/817/818/819

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

37/37


型号：	STM704M6F
厂家：	ST
描述：	5V Supervisor with Battery Switchover 5V监控器电池切换电池监控
文件：	总37页 (文件大小：775K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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