STM8AF5198TDY [STMICROELECTRONICS]
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, ROHS COMPLIANT, LQFP-48;
| 型号： | STM8AF5198TDY |
| 厂家： | 
ST |
| 描述： | 8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP48, 7 X 7 MM, ROHS COMPLIANT, LQFP-48 |
| 文件： | 总110页 (文件大小：1617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8AF5xxx STM8AF6x69/7x/8x/9x/Ax
Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,
10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 to 5.5 V
Datasheet −production data
Features
■ Core
– Max f
: 24 MHz
CPU
LQFP48 7x7
LQFP64 10x10
LQFP80 14x14
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
10 MIPS at 16 MHz f
standard benchmark
for industry
CPU
LQFP32 7x7
VFQFPN32 5x5
■ Communication interfaces
■ Memories
– High speed 1 Mbit/s CAN 2.0B interface
– USART with clock output for synchronous
operation - LIN master mode
– LINUART LIN 2.1 compliant, master/slave
modes with automatic resynchronization
– Program memory: 32 to 128 Kbytes Flash
program; data retention 20 years at 55 °C
– Data memory: up to 2 Kbytes true data
EEPROM; endurance 300 kcycles
– RAM: 2 Kbytes to 6 Kbytes
– SPI interface up to 10 Mbit/s or f
– I C interface up to 400 Kbit/s
/2
MASTER
2
■ Clock management
– Low-power crystal resonator oscillator with
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
■ Analog to digital converter (ADC)
– 10-bit resolution, 2 LSB TUE, 1 LSB
linearity and up to 16 multiplexed channels
■ Operating temperature up to 150 °C
■ Qualification conforms to AEC-Q100 rev G
■ Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Low consumption power-on and power-
down reset
(1)
Table 1.
Device summary
Part numbers: STM8AF52xx (with CAN)
STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A,
STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268
■ Interrupt management
Part numbers: STM8AF6269/8x/Ax
– Nested interrupt controller with 32 vectors
– Up to 37 external interrupts on 5 vectors
STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A,
STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269,
STM8AF62A6,
■ Timers
Part numbers: STM8AF51xx (with CAN)(2)
– 2 general purpose 16-bit timers with up to 3
CAPCOM channels each (IC, OC, PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A,
STM8AF5199, STM8AF5198, STM8AF518A, STM8AF5189,
STM8AF5188, STM8AF5179, STM8AF5178, STM8AF5169,
STM8AF5168
(2)
Part numbers: STM8AF6169/7x/8x/9x/Ax
STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,
STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,
STM8AF6188, STM8AF6186, STM8AF6179, STM8AF6178,
STM8AF6176, STM8AF6169
– Window and independent watchdog timers
■ I/Os
1. In the order code, ‘F’ applies to devices with Flash program
memory and data EEPROM while ‘H’ refers to devices with
Flash program memory only. ‘F’ is replaced by ‘P’ for devices
with FASTROM (see Tables 2, 3, 4, and 5, and Figure 52).
– Up to 68 user pins (11 high sink I/Os)
– Highly robust I/O design, immune against
current injection
2. Not recommended for new design.
July 2012
Doc ID 14395 Rev 9
1/110
This is information on a product in full production.
www.st.com
1
Contents
STM8AF52/62xx, STM8AF51/61xx
Contents
1
2
3
4
5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
STM8A central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1
5.1.2
5.1.3
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 16
5.2.1
5.2.2
SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
5.4
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Flash program and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4.1
5.4.2
5.4.3
5.4.4
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Protection of user boot code (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . 18
128 kHz low-speed internal RC oscillator (LSI) . . . . . . . . . . . . . . . . . . . 19
24 MHz high-speed external crystal oscillator (HSE) . . . . . . . . . . . . . . 19
External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
5.7
Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7.1
5.7.2
5.7.3
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
5.7.4
5.7.5
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . 21
Basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.8
5.9
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.9.1
5.9.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 23
Universal asynchronous receiver/transmitter with LIN support
(LINUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.3
5.9.4
5.9.5
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
Inter integrated circuit (I C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Controller area network interface (beCAN) . . . . . . . . . . . . . . . . . . . . . . 27
5.10 Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
7
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
6.2
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1
7.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9
10
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
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Contents
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10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.8 TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 77
10.3.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2
10.3.10 I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.4.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 88
11
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8AF52xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8AF62xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM8AF/H/P51xx product line-up with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM8AF/H/P61xx product line-up without CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Peripheral clock gating bits (CLK_PCKENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Peripheral clock gating bits (CLK_PCKENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Advanced control and general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ADC naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Legend/abbreviation for the pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory model 128K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Temporary memory unprotection registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM8A interrupt table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Operating lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Total current consumption in Run, Wait and Slow mode. General conditions
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
for V apply, T = -40 °C to 150 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DD
A
Table 29.
Total current consumption in Halt and Active-halt modes. General conditions for V
DD
applied. T = -40 °C to 55 °C unless otherwise stated . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Oscillator current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Programming current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical peripheral current consumption V = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DD
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TIM 1, 2, 3, and 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy for V
= 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DDA
Doc ID 14395 Rev 9
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List of tables
STM8AF52/62xx, STM8AF51/61xx
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LQFP 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 90
LQFP 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 93
LQFP 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 95
VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 57.
6/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash memory organization of STM8A products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LQFP/VFQFPN 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
f
versus V
CPUmax
DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 11. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
EXT
Figure 12. Typ. I
Figure 13. Typ. I
Figure 14. Typ. I
Figure 15. Typ. I
Figure 16. Typ. I
Figure 17. Typ. I
vs. V @f
= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64
DD(RUN)HSE
DD(RUN)HSE
DD(RUN)HSI
DD(WFI)HSE
DD(WFI)HSE
DD
CPU
vs. f
@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . 64
CPU
DD
vs. V @ f
= 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64
= 16 MHz, peripherals = on . . . . . . . . . . . . . . . . . . . . . . 64
DD
CPU
vs. V @ f
DD
CPU
vs. f
@ V = 5.0 V, peripherals = on . . . . . . . . . . . . . . . . . . . . . . . . 64
CPU
DD
vs. V @ f = 16 MHz, peripherals = off . . . . . . . . . . . . . . . . . . . . . . 64
DD(WFI)HSI
DD
CPU
Figure 18. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 19. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DD
Figure 21. Typical LSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DD
Figure 22. Typical V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
IL
IH
DD
Figure 23. Typical pull-up resistance R vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 72
PU
DD
(1)
Figure 24. Typical pull-up current I vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 73
pu
DD
Figure 25. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 26. Typ. V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 27. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 28. Typ. V @ V = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
OL
DD
Figure 29. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
OL
DD
Figure 30. Typ. V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
OL
DD
Figure 31. Typ. V - V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
OH
DD
Figure 32. Typ. V - V @ V = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
OH
DD
Figure 33. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
OH
DD
Figure 34. Typ. V - V @ V = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DD
OH
DD
Figure 35. Typical NRST V and V vs V @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IL
IH
DD
Figure 36. Typical NRST pull-up resistance R vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PU
DD
Figure 37. Typical NRST pull-up current I vs V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
pu
DD
Figure 38. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 39. SPI timing diagram in slave mode and with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40. SPI timing diagram in slave mode and with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 41. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 43. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 44. LQFP 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 45. LQFP 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 46. LQFP 64-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 47. LQFP 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 48. LQFP 48-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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List of figures
STM8AF52/62xx, STM8AF51/61xx
Figure 49. LQFP 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 50. LQFP 32-pin recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5). . . . . . . . . . . . . . . 97
(1)
Figure 52. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Introduction
1
Introduction
This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx
products with 32 to 128 Kbytes of program memory.
In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’
to product versions with Flash only, and ‘P’ to product versions with FASTROM. The
identifiers ‘F’, ‘H’, and ‘P’ do not coexist in a given order code.
The datasheet contains the description of family features, pinout, electrical characteristics,
mechanical data and ordering information.
●
For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8S and STM8A microcontroller families reference
manual (RM0016).
●
●
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S and STM8A Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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Description
STM8AF52/62xx, STM8AF51/61xx
2
Description
The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit
microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non
volatile memory and integrated true data EEPROM. They are referred to as high density
STM8A devices in the STM8S and STM8A microcontroller families reference manual
(RM0016).
The STM8AF51xx and STM8AF52xx series feature a CAN interface.
All devices of the STM8A product line provide the following benefits: reduced system cost,
performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular
peripherals. Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8A family thanks to their advanced core which is
made in a state-of-the art technology for automotive applications with 3.3 V to 5.5 V
operating supply.
All STM8A and ST7 microcontrollers are supported by the same tools including
STVD/STVP development environment, the STice emulator and a low-cost, third party in-
circuit debugging tool.
10/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Product line-up
3
Product line-up
..
Table 2.
STM8AF52xx product line-up with CAN
High
density
Flash
program (bytes)
memory
Data
EEPROM
(bytes)
10-bit
A/D
chan.
I/0
wakeup
pins
RAM
Timers
(IC/OC/PWM) interfaces
Serial
Order code
Package
(bytes)
STM8AF/P52AA
STM8AF/P528A
STM8AF/P52A9
STM8AF/P5289
STM8AF/P5269
STM8AF/P52A8
STM8AF/P5288
STM8AF/P5268
128 K
64 K
LQFP80
(14x14)
68/37
52/36
2 K
128 K
16
10
CAN,
1x8-bit: TIM4
LIN(UART)
3x16-bit: TIM1,
, SPI,
LQFP64
(10x10)
64 K
6 K
32 K
TIM2, TIM3
USART,
1 K
2 K
1K
(9/9/9)
I²C
128 K
64 K
32 K
LQFP48
(7x7)
38/35
Table 3.
STM8AF62xx product line-up without CAN
High
density
Flash
program (bytes)
memory
Data
EEPROM
(bytes)
10-bit
A/D
chan.
I/0
wakeup
pins
RAM
Timers
(IC/OC/PWM) interfaces
Serial
Order code
Package
(bytes)
STM8AF/P62AA
STM8AF/P628A
STM8AF/P62A9
STM8AF/P6289
STM8AF/P6269
STM8AF/P62A8
STM8AF/P6288
128 K
64 K
LQFP80
(14x14)
68/37
52/36
38/35
2 K
128 K
64 K
16
1x8-bit: TIM4
LIN(UART),
3x16-bit: TIM1,
SPI,
LQFP64
(10x10)
2 K
1 K
TIM2, TIM3
USART, I²C
(9/9/9)
32 K
6 K
128 K
LQFP48
(7x7)
10
7
64 K
LQFP32
(7x7)
2 K
1x8-bit: TIM4
3x16-bit: TIM1, LIN(UART),
STM8AF/P6286
STM8AF/P62A6
25/23
TIM2, TIM3
(8/8/8)
SPI, I²C
VFQFPN32
(5x5)
128 K
Doc ID 14395 Rev 9
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Product line-up
STM8AF52/62xx, STM8AF51/61xx
.
Table 4.
STM8AF/H/P51xx product line-up with CAN
High
density
Flash
program (bytes)
memory
Data
EEPROM
(bytes)
10-bit
A/D
chan.
I/0
wakeup
pins
RAM
Timers
(IC/OC/PWM) interfaces
Serial
Order code
Package
(bytes)
STM8AF/H/P51AA
STM8AF/H/P519A
STM8AF/H/P518A
STM8AF/H/P51A9
STM8AF/H/P5199
STM8AF/H/P5189
STM8AF/H/P5179
STM8AF/H/P5169
STM8AF/H/P51A8
STM8AF/H/P5198
STM8AF/H/P5188
STM8AF/H/P5178
STM8AF/H/P5168
128 K
96 K
LQFP80
(14x14)
68/37
52/36
64 K
128 K
96 K
64 K
48 K
32 K
128 K
96 K
64 K
48 K
32 K
6 K
2 K
16
LQFP64
(10x10)
CAN,
1x8-bit: TIM4
LIN(UART)
3x16-bit: TIM1,
, SPI,
4 K
3 K
2 K
1.5 K
1 K
TIM2, TIM3
USART,
(9/9/9)
I²C
6 K
2 K
LQFP48
(7x7)
4 K
3 K
2 K
10
38/35
1.5 K
1K
12/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Product line-up
²
Table 5.
STM8AF/H/P61xx product line-up without CAN
High
density
Flash
program (bytes)
memory
Data
EEPROM A/D
(bytes)
10-bit
I/0
Serial
RAM
Timers
Order code
Package
wakeup
(IC/OC/PWM) interfaces
chan.
pins
(bytes)
STM8AF/H/P61AA
STM8AF/H/P619A
STM8AF/H/P618A
STM8AF/H/P61A9
STM8AF/H/P6199
STM8AF/H/P6189
STM8AF/H/P6179
STM8AF/H/P6169
STM8AF/H/P61A8
STM8AF/H/P6198
STM8AF/H/P6188
STM8AF/H/P6178
STM8AF/H/P6186
128 K
96 K
LQFP80
(14x14)
68/37
64 K
128 K
96 K
64 K
48 K
32 K
128 K
96 K
64 K
48 K
64 K
6 K
2 K
16
1x8-bit: TIM4
LQFP64
(10x10)
3x16-bit:
TIM1, TIM2,
TIM3
LIN(UART),
SPI,
USART, I²C
4 K
3 K
2 K
52/36
1.5 K
1 K
(9/9/9)
6 K
2 K
LQFP48
(7x7)
10
7
38/35
25/23
4 K
3 K
4 K
1.5 K
1x8-bit: TIM4
3x16-bit:
TIM1, TIM2,
TIM3 (8/8/8)
LQFP32
(7x7)/
LIN(UART),
SPI, I²C
STM8AF/H/P6176
48 K
3 K
Doc ID 14395 Rev 9
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Block diagram
STM8AF52/62xx, STM8AF51/61xx
4
Block diagram
Figure 1.
STM8A block diagram
Reset block
Reset
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
Clock controller
Detector
Reset
POR
BOR
Clock to peripherals and core
Window WDG
IWDG
STM8A CORE
Single wire
debug interf.
Up to 128 Kbyte
high density program
Flash
Debug/SWIM
LINUART
Master/slave
automatic
resynchronization
Up to 2 Kbytes
data EEPROM
400 Kbit/s
10 Mbit/s
2
Up to 6 Kbytes
RAM
I C
Boot ROM
SPI
16-bit advanced control
LIN master
SPI emul.
timer (TIM1)
USART
beCAN
Up to
9 CAPCOM
channels
16-bit general purpose
(TIM2, TIM3)
1 Mbit/s
8-bit AR timer
(TIM4)
Up to
16 channels
10-bit ADC
AWU timer
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
Window WDG: Window watchdog
14/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Product overview
5
Product overview
This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to the STM8S and STM8A
microcontroller families reference manual (RM0016).
5.1
STM8A central processing unit (CPU)
The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each execution
context), 20 addressing modes including indexed indirect and relative addressing and 80
instructions.
5.1.1
Architecture and registers
●
●
●
●
Harvard architecture
3-stage pipeline
32-bit wide program memory bus with single cycle fetching for most instructions
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
●
●
●
8-bit accumulator
24-bit program counter with 16-Mbyte linear memory space
16-bit stack pointer with access to a 64 Kbyte stack
8-bit condition code register with seven condition flags for the result of the last
instruction.
5.1.2
5.1.3
Addressing
●
●
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
Instruction set
●
●
●
●
●
●
●
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 14395 Rev 9
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Product overview
STM8AF52/62xx, STM8AF51/61xx
5.2
Single wire interface module (SWIM) and debug module (DM)
5.2.1
SWIM
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
●
●
●
R/W of RAM and peripheral registers in real-time
R/W for all resources when the application is stopped
Breakpoints on all program-memory instructions (software breakpoints), except the
interrupt vector table
●
Two advanced breakpoints and 23 predefined breakpoint configurations
5.3
5.4
Interrupt controller
●
●
●
●
Nested interrupts with three software priority levels
24 interrupt vectors with hardware priority
Five vectors for external interrupts (up to 37 depending on the package)
Trap and reset interrupts
Flash program and data EEPROM
●
●
●
32 Kbytes to 128 Kbytes of high density single voltage Flash program memory
Up to 2 Kbytes true (not emulated) data EEPROM
Read while write: writing in the data memory is possible while executing code in the
Flash program memory.
The whole Flash program memory and data EEPROM are factory programmed with 0x00.
5.4.1
Architecture
●
●
●
●
The memory is organized in blocks of 128 bytes each
Read granularity: 1 word = 4 bytes
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
Writing, erasing, word and block management is handled automatically by the memory
interface.
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Product overview
5.4.2
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the
memory. The write protection can be removed temporarily by executing a specific sequence
in the user software.
5.4.3
Protection of user boot code (UBC)
If the user chooses to update the Flash program memory using a specific boot code to
perform in application programming (IAP), this boot code needs to be protected against
unwanted modification.
In the STM8A a memory area of up to 128 Kbytes can be protected from overwriting at user
option level. Other than the standard write protection, the UBC protection can exclusively be
modified via the debug interface, the user software cannot modify the UBC protection status.
The UBC memory area contains the reset and interrupt vectors and its size can be adjusted
in increments of 512 bytes by programming the UBC and NUBC option bytes
(see Section 9: Option bytes on page 51).
Figure 2.
Flash memory organization of STM8A products
Data memory area
Option bytes
Data
EEPROM
memory
Programmable area from 1 Kbyte
(first two pages) up to program memory
end - maximum 128 Kbytes
UBC area
Remains write protected during IAP
Flash
program
memory
Program memory area
Write access possible for IAP
5.4.4
Read-out protection (ROP)
The STM8A provides a read-out protection of the code and data memory which can be
activated by an option byte setting (see the ROP option byte in section 10).
The read-out protection prevents reading and writing Flash program memory, data memory
and option bytes via the debug module and SWIM interface. This protection is active in all
device operation modes. Any attempt to remove the protection by overwriting the ROP
option byte triggers a global erase of the program and data memory.
The ROP circuit may provide a temporary access for debugging or failure analysis. The
temporary read access is protected by a user defined, 8-byte keyword stored in the option
byte area. This keyword must be entered via the SWIM interface to temporarily unlock the
device.
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Product overview
STM8AF52/62xx, STM8AF51/61xx
If desired, the temporary unlock mechanism can be permanently disabled by the user
through OPT6/NOPT6 option bytes.
5.5
Clock controller
The clock controller distributes the system clock coming from different oscillators to the core
and the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness.
5.5.1
Features
●
Clock sources
–
–
–
–
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
1-24 MHz high-speed external crystal (HSE)
Up to 24 MHz high-speed user-external clock (HSE user-ext)
●
●
Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock
(16 MHz/8). The clock source and speed can be changed by the application program
as soon as the code execution starts.
Safe clock switching: Clock sources can be changed safely on the fly in Run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Wakeup: In case the device wakes up from low-power modes, the internal RC
oscillator (16 MHz/8) is used for quick startup. After a stabilization time, the device
switches to the clock source that was selected before Halt mode was entered.
●
●
Clock security system (CSS): The CSS permits monitoring of external clock sources
and automatic switching to the internal RC (16 MHz/8) in case of a clock failure.
Configurable main clock output (CCO): This feature permits to outputs a clock signal
for use by the application.
5.5.2
16 MHz high-speed internal RC oscillator (HSI)
●
●
Default clock after reset 2 MHz (16 MHz/8)
Fast wakeup time
User trimming
The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign
permits frequency tuning by the application program. The adjustment range covers all
possible frequency variations versus supply voltage and temperature. This trimming does
not change the initial production setting.
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Product overview
5.5.3
128 kHz low-speed internal RC oscillator (LSI)
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).
5.5.4
24 MHz high-speed external crystal oscillator (HSE)
The external high-speed crystal oscillator can be selected to deliver the main clock in
normal Run mode. It operates with quartz crystals and ceramic resonators.
●
●
●
Frequency range: 1 MHz to 24 MHz
Crystal oscillation mode: preferred fundamental
I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT
5.5.5
5.5.6
External clock input
An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).
Table 6.
Peripheral clock gating bits (CLK_PCKENR1)
Control bit
Peripheral
PCKEN17
PCKEN16
PCKEN15
PCKEN14
PCKEN13
PCKEN12
PCKEN11
PCKEN10
TIM1
TIM3
TIM2
TIM4
LINUART
USART
SPI
I2C
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Product overview
STM8AF52/62xx, STM8AF51/61xx
Table 7.
Peripheral clock gating bits (CLK_PCKENR2)
Control bit
Peripheral
PCKEN27
PCKEN26
PCKEN25
PCKEN24
PCKEN23
PCKEN22
PCKEN21
PCKEN20
CAN
Reserved
Reserved
Reserved
ADC
AWU
Reserved
Reserved
5.6
Low-power operating modes
For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
●
Wait mode
In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.
●
Active-halt mode with regulator on
In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Active-
halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.
●
●
Active-halt mode with regulator off
This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.
Halt mode
CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.
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Product overview
5.7
Timers
5.7.1
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
option bits, the watchdog is automatically enabled at power-on, and generates a reset
unless the key register is written by software before the counter reaches the end of count.
5.7.2
Auto-wakeup counter
This counter is used to cyclically wakeup the device in Active-halt mode. It can be clocked by
the internal 128 kHz internal low-frequency RC oscillator or external clock.
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration.
5.7.3
5.7.4
Beeper
This function generates a rectangular signal in the range of 1, 2 or 4 kHz which can be
output on a pin. This is useful when audible sounds without interference need to be
generated for use in the application.
Advanced control and general purpose timers
STM8A devices described in this datasheet, contain up to three 16-bit advanced control and
general purpose timers providing nine CAPCOM channels in total. A CAPCOM channel can
be used either as input compare, output compare or PWM channel. These timers are
named TIM1, TIM2 and TIM3.
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Product overview
STM8AF52/62xx, STM8AF51/61xx
Table 8.
Timer
Advanced control and general purpose timers
Counter Counter Prescaler
Inverted Repetition trigger External Break
Channels
width
type
factor
outputs
counter
unit
trigger
input
TIM1
TIM2
16-bit
Up/down 1 to 65536
4
3
3
Yes
Yes
Yes
Yes
2n
16-bit
16-bit
Up
None
None
No
No
No
No
No
No
No
No
n = 0 to 15
2n
TIM3
Up
2
n = 0 to 15
TIM1 - advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and bridge driver.
●
16-bit up, down and up/down AR (auto-reload) counter with 16-bit fractional prescaler.
●
Four independent CAPCOM channels configurable as input capture, output compare,
PWM generation (edge and center aligned mode) and single pulse mode output
●
Trigger module which allows the interaction of TIM1 with other on-chip peripherals. In
the present implementation it is possible to trigger the ADC upon a timer event.
●
●
●
●
External trigger to change the timer behavior depending on external signals
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers
●
●
●
●
16-bit auto-reload up-counter
15-bit prescaler adjustable to fixed power of two ratios 1…32768
Timers with three or two individually configurable CAPCOM channels
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
5.7.5
Basic timer
The typical usage of this timer (TIM4) is the generation of a clock tick.
Table 9.
Timer
TIM4
Counter Counter Prescaler
width
Inverted Repetition trigger External Break
Channels
type
factor
outputs
counter
unit
trigger
input
2n
TIM4
8-bit
Up
0
None
No
No
No
No
n = 0 to 7
●
●
●
8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128
Clock source: master clock
Interrupt source: 1 x overflow/update
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Product overview
5.8
Analog to digital converter (ADC)
The STM8A products described in this datasheet contain a 10-bit successive approximation
ADC with up to 16 multiplexed input channels, depending on the package.
The ADC name differs between the datasheet and the STM8A/S reference manual (see
Table 10).
Table 10. ADC naming
Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)
ADC
ADC2
ADC features
●
●
●
●
●
●
●
●
●
10-bit resolution
Single and continuous conversion modes
Programmable prescaler: f
divided by 2 to 18
MASTER
Conversion trigger on timer events, and external events
Interrupt generation at end of conversion
Selectable alignment of 10-bit data in 2 x 8 bit result registers
Shadow registers for data consistency
ADC input range: V
≤V ≤V
IN DDA
SSA
Schmitt-trigger on analog inputs can be disabled to reduce power consumption
5.9
Communication interfaces
The following sections give a brief overview of the communication peripheral. Some
peripheral names differ between the datasheet and the STM8A/S reference manual (see
Table 11).
Table 11. Communication peripheral naming correspondence
Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)
USART
UART1
UART3
LINUART
5.9.1
Universal synchronous/asynchronous receiver transmitter (USART)
The devices covered by this datasheet contain one USART interface. The USART can
operate in standard SCI mode (serial communication interface, asynchronous) or in SPI
emulation mode. It is equipped with a 16 bit fractional prescaler. It features LIN master
support.
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Product overview
Detailed feature list:
STM8AF52/62xx, STM8AF51/61xx
●
●
●
Full duplex, asynchronous communications
NRZ standard format (mark/space)
High-precision baud rate generator system
–
Common programmable transmit and receive baud rates up to f
/16
MASTER
●
●
●
Programmable data word length (8 or 9 bits)
Configurable stop bits: Support for 1 or 2 stop bits
LIN master mode:
–
–
LIN break and delimiter generation
LIN break and delimiter detection with separate flag and interrupt source for
readback checking.
●
●
●
Transmitter clock output for synchronous communication
Separate enable bits for transmitter and receiver
Transfer detection flags:
–
–
–
Receive buffer full
Transmit buffer empty
End of transmission flags
●
●
Parity control:
–
–
Transmits parity bit
Checks parity of received data byte
Four error detection flags:
–
–
–
–
Overrun error
Noise error
Frame error
Parity error
●
Six interrupt sources with flags:
–
–
–
–
–
–
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Parity error
LIN break and delimiter detection
●
Two interrupt vectors:
–
–
Transmitter interrupt
Receiver interrupt
●
●
●
Reduced power consumption mode
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
–
–
Address bit (MSB)
Idle line
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Product overview
5.9.2
Universal asynchronous receiver/transmitter with LIN support
(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
communication interface which supports extensive LIN functions tailored for LIN slave
applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1.
Detailed feature list:
LIN mode
Master mode
●
LIN break and delimiter generation
●
LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Slave mode
●
●
●
●
Autonomous header handling – one single interrupt per valid header
Mute mode to filter responses
Identifier parity error checking
LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
●
●
Break detection at any time, even during a byte reception
Header errors detection:
–
–
–
–
–
Delimiter too short
Synch field error
Deviation error (if automatic resynchronization is enabled)
Framing error in synch field or identifier field
Header time-out
UART mode
●
●
Full duplex, asynchronous communications - NRZ standard format (mark/space)
High-precision baud rate generator
A common programmable transmit and receive baud rates up to f
–
/16
MASTER
●
●
●
●
●
●
●
Programmable data word length (8 or 9 bits) – 1 or 2 stop bits – parity control
Separate enable bits for transmitter and receiver
Error detection flags
Reduced power consumption mode
Multi-processor communication - enter mute mode if address match does not occur
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
–
–
Address bit (MSB)
Idle line
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Product overview
STM8AF52/62xx, STM8AF51/61xx
5.9.3
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
●
●
●
●
●
●
●
Maximum speed: 8 Mbit/s or f
/2 both for master and slave
MASTER
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
●
●
●
●
●
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
–
–
CRC value can be transmitted as last byte in Tx mode
CRC error checking for last received byte
2
5.9.4
Inter integrated circuit (I C) interface
2
The devices covered by this datasheet contain one I C interface. The interface is available
on all the supported packages.
2
●
I C master features:
–
Clock generation
–
Start and stop generation
2
●
I C slave features:
2
–
–
Programmable I C address detection
Stop bit detection
●
●
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
–
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
●
●
Status flags:
–
–
–
Transmitter/receiver mode flag
End-of-byte transmission flag
2
I C busy flag
Error flags:
–
–
–
–
Arbitration lost condition for master mode
Acknowledgement failure after address/data transmission
Detection of misplaced start or stop condition
Overrun/underrun if clock stretching is disabled
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Product overview
●
Interrupt:
–
–
–
Successful address/data communication
Error condition
Wakeup from Halt
●
Wakeup from Halt on address detection in slave mode
5.9.5
Controller area network interface (beCAN)
The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It is equipped with a receive FIFO and a very versatile
filter bank. Together with a filter match index, this allows a very efficient message handling in
today’s car network architectures. The CPU is significantly unloaded. The maximum
transmission speed is 1 Mbit/s.
Transmission
●
●
Three transmit mailboxes
Configurable transmit priority by identifier or order request
Reception
●
●
●
●
●
●
●
11- and 29-bit ID
1 receive FIFO (3 messages deep)
Software-efficient mailbox mapping at a unique address space
FMI (filter match index) stored with message for quick message association
Configurable FIFO overrun
Time stamp on SOF reception
6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID.
●
Filtering modes (mixable):
–
–
Mask mode permitting ID range filtering
ID list mode
Interrupt management
●
●
Maskable interrupt
Software-efficient mailbox mapping at a unique address space
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Product overview
STM8AF52/62xx, STM8AF51/61xx
5.10
Input/output specifications
The product features four I/O types:
●
●
●
●
Standard I/O 2 MHz
Fast I/O up to 10 MHz
High sink 8 mA, 2 MHz
2
True open drain (I C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum
slew rate. The rise and fall times are similar to those of standard I/Os.
The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt-
trigger input stage on the analog I/Os can be disabled in order to reduce the device standby
consumption.
STM8A I/Os are designed to withstand current injection. For a negative injection current of
4 mA, the resulting leakage current in the adjacent input does not exceed 1 µA. Thanks to
this feature, external protection diodes against current injection are no longer required.
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Pinouts and pin description
6
Pinouts and pin description
6.1
Package pinouts
Figure 3.
LQFP 80-pin pinout
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
NRST
OSCIN/PA1
OSCOUT/PA2
PI3
PI2
PI1
PI0
V
SSIO_1
V
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7/SPI_MISO
PC6/SPI_MOSI
SS
VCAP
V
DD
(1)
V
DDIO_1
(1)
9
TIM2_CH3/PA3
10
11
12
13
14
15
16
17
18
19
20
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
(HS) PH0
V
V
DDIO_2
SSIO_2
(HS) PH1
PC5/SPI_SCK
PH2
PH3
AIN15/PF7
AIN14/PF6
AIN13/PF5
AIN12/PF4
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PC0/ADC_ETR
PE5/SPI_NSS
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2. (HS) stands for high sink capability.
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Pinouts and pin description
Figure 4. LQFP 64-pin pinout
STM8AF52/62xx, STM8AF51/61xx
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PI0
PG4
PG3
PG2
PG1/CAN_RX
PG0/CAN_TX
PC7/SPI_MISO
PC6/SPI_MOSI
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
7
8
9
V
SSIO_1
(1)
V
SS
(1)
VCAP
V
DD
V
DDIO_1
V
TIM2_CH3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
DDIO_2
V
10
11
12
SSIO_2
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
AIN15/PF7 13
AIN14/PF6
14
AIN13/PF5 15
AIN12/PF4 16
1718 1920212223242526272829303132
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2. HS stands for high sink capability.
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Figure 5. LQFP 48-pin pinout
Pinouts and pin description
48 47 46 45 4443424140393837
36
NRST
OSCIN/PA1
PG1/CAN_Rx
PG0/CAN_Tx
35
1
2
OSCOUT/PA2
3
4
34 PC7/SPI_MISO
33 PC6/SPI_MOSI
V
SSIO_1
V
32
31
30
29
28
27
26
25
5
6
7
8
9
10
11
V
V
SS
DDIO_2
VCAP
SSIO_2
V
PC5/SPI_SCK
DD
V
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
DDIO_1
TIM2_CH3/PA3
USART_RX/PA4
USART_TX/PA5
USART_CK/PA6
12
24
1314 15161718192021 2223
1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines.
2. HS stands for high sink capability.
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Pinouts and pin description
Figure 6. LQFP/VFQFPN 32-pin pinout
STM8AF52/62xx, STM8AF51/61xx
32 31 30 29 28 27 26 25
24
NRST
OSCIN/PA1
OSCOUT/PA2
1
2
3
4
5
6
7
8
PC7/SPI_MISO
PC6/SPI_MOSI
PC5/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1
PE5/SPI_NSS
23
22
21
20
19
18
17
V
SS
VCAP
V
DD
V
DDIO
AIN12/PF4
9 101112 13141516
1. HS stands for high sink capability.
Table 12. Legend/abbreviation for the pin description table
Type
I= input, O = output, S = power supply
Input
CM = CMOS (standard for all I/Os)
HS = high sink (8 mA)
Level
Output
O1 = Standard (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Output speed
Input
float = floating, wpu = weak pull-up
Port and control
configuration
Output
T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
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Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Pinouts and pin description
Table 13. STM8A microcontroller family pin description
Pin number
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
reset)
1
2
1
2
1
2
1
2
NRST
I/O
-
X
—
—
—
—
—
—
X
—
X
Reset
—
—
Resonator/
crystal in
PA1/OSCIN(1) I/O
X
X
O1
Port A1
Port A2
Resonator/
crystal out
3
3
3
3
PA2/OSCOUT I/O
X
X
X
—
O1
X
X
—
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
-
VSSIO_1
VSS
S
S
S
S
S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O ground
Digital ground
—
—
—
—
—
4
5
6
7
VCAP
VDD
— 1.8 V regulator capacitor
—
—
Digital power supply
I/O power supply
VDDIO_1
Timer 2 -
Port A3
TIM3_CH1
[AFR1]
9
9
9
-
-
-
PA3/TIM2_CH3 I/O
PA4/USART_RX I/O
PA5/USART_TX I/O
X
X
X
X
X
X
X
X
X
—
—
—
O1
O3
O3
X
X
X
X
X
X
channel 3
USART
Port A4
10 10 10
11 11 11
—
—
receive
USART
Port A5
transmit
USART
Port A6 synchronous
clock
12 12 12
-
PA6/USART_CK I/O
X
X
X
—
O3
X
X
—
13
14
15
16
-
-
-
-
-
-
-
-
-
-
-
-
PH0
PH1
PH2
PH3
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
—
—
—
—
HS O3
HS O3
X
X
X
X
X
X
X
X
Port H0
Port H1
Port H2
Port H3
—
—
—
—
—
—
—
—
—
—
O1
O1
Analog
input 15
17 13
18 14
19 15
20 16
21 17
-
-
-
-
-
-
-
PF7/AIN15
PF6/AIN14
PF5/AIN13
PF4/AIN12
PF3/AIN11
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
Port F7
Port F6
Port F5
Port F4
Port F3
—
—
—
—
—
Analog
input 14
Analog
input 13
-
Analog
input 12
8
-
Analog
input 11
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Pinouts and pin description
STM8AF52/62xx, STM8AF51/61xx
Table 13. STM8A microcontroller family pin description (continued)
Pin number
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
reset)
ADC positive reference
voltage
22 18
-
-
VREF+
S
—
—
—
—
—
—
—
—
23 19 13
9
VDDA
VSSA
S
S
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Analog power supply
Analog ground
—
—
24 20 14 10
ADC negative reference
voltage
25 21
26 22
-
-
-
-
-
-
VREF-
S
—
X
X
X
X
X
X
X
X
X
X
—
X
X
X
X
X
X
X
X
X
X
—
—
X
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
—
X
X
X
X
X
X
X
X
X
X
—
—
—
—
Analog
Port F0
PF0/AIN10
PB7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
PB3/AIN3
PB2/AIN2
PB1/AIN1
PB0/AIN0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O1
O1
O1
O1
O1
O1
O1
O1
O1
O1
input 10
Analog input
27 23 15
28 24 16
Port B7
7
Analog input
X
Port B6
6
Analog input
I2C_SDA
[AFR6]
29 25 17 11
30 26 18 12
31 27 19 13
32 28 20 14
33 29 21 15
34 30 22 16
X
Port B5
5
Analog input
I2C_SCL
[AFR6]
X
Port B4
4
Analog input TIM1_ETR
X
Port B3
Port B2 Analog input
3
[AFR5]
TIM1_CH3N
[AFR5]
X
Analog input TIM1_CH2N
[AFR5]
X
Port B1
Port B0
Port H4
1
Analog input TIM1_CH1N
X
0
[AFR5]
Timer 1 -
trigger input
35
36
-
-
-
-
-
-
PH4/TIM1_ETR I/O
—
—
Timer 1 -
inverted
channel 3
PH5/
I/O
X
X
X
X
X
X
—
—
—
—
—
—
O1
O1
O1
X
X
X
X
X
X
Port H5
Port H6
Port H7
—
—
—
TIM1_CH3N
Timer 1 -
inverted
channel 2
PH6/
I/O
37
38
-
-
-
-
-
-
TIM1_CH2N
Timer 1 -
inverted
PH7/
I/O
TIM1_CH1N
channel 2
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Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Pinouts and pin description
Table 13. STM8A microcontroller family pin description (continued)
Pin number
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
reset)
Analog input
8
39 31 23
40 32 24
-
PE7/AIN8
PE6/AIN9
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
X
X
X
X
X
X
X
—
—
—
—
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port E7
Port E7
Port E5
Port C0
Port C1
Port C2
Port C3
—
—
—
—
—
—
—
—
Analog input
9
SPI master/
slave select
41 33 25 17 PE5/SPI_NSS I/O
42 PC0/ADC_ETR I/O
ADC trigger
input
-
-
-
Timer 1 -
channel 1
43 34 26 18 PC1/TIM1_CH1 I/O
44 35 27 19 PC2/TIM1_CH2 I/O
45 36 28 20 PC3/TIM1_CH3 I/O
HS O3
HS O3
HS O3
HS O3
Timer 1-
channel 2
Timer 1 -
channel 3
Timer 1 -
channel 4
46 37 29 21 PC4/TIM1_CH4 I/O
47 38 30 22 PC5/SPI_SCK I/O
Port C4
Port C5
X
X
X
—
—
—
O3
—
X
X
SPI clock
—
—
—
48 39 31
49 40 32
-
-
VSSIO_2
VDDIO_2
S
S
—
—
—
—
—
—
—
—
—
—
I/O ground
—
I/O power supply
SPI master
50 41 33 23 PC6/SPI_MOSI I/O
51 42 34 24 PC7/SPI_MISO I/O
X
X
X
X
X
X
—
—
O3
O3
X
X
X
X
Port C6
out/
slave in
—
—
SPI master
in/ slave out
Port C7
52 43 35
53 44 36
-
-
-
-
-
-
-
-
-
PG0/CAN_Tx I/O
PG1/CAN_Rx I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O1
O1
O1
O1
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port G0 CAN transmit
Port G1 CAN receive
—
—
—
—
—
—
—
—
—
54 45
55 46
56 47
57 48
-
-
-
-
-
-
-
PG2
PG3
PG4
PI0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port G2
Port G3
Port G4
Port I0
Port I1
Port I2
Port I3
—
—
—
—
—
—
—
58
59
60
-
-
-
PI1
PI2
PI3
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Pinouts and pin description
STM8AF52/62xx, STM8AF51/61xx
Table 13. STM8A microcontroller family pin description (continued)
Pin number
Input
Output
Main
function
(after
Alternate
function
after remap
[option bit]
Default
alternate
function
Pin name
reset)
61
62
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI4
PI5
I/O
I/O
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
X
—
—
—
—
—
—
O1
O1
O1
O1
O1
O1
X
X
X
X
X
X
X
X
X
X
X
X
Port I4
Port I5
—
—
—
—
—
—
—
—
—
—
—
—
63 49
64 50
65 51
66 52
PG5
PG6
PG7
PE4
Port G5
Port G6
Port G7
Port E4
Timer 1 -
break input
67 53 37
-
PE3/TIM1_BKIN I/O
X
X
X
—
O1
X
X
Port E3
—
68 54 38
69 55 39
-
-
PE2/I2C_SDA I/O
PE1/I2C_SCL I/O
X
X
—
—
X
X
—
—
O1 T(2)
O1 T(2)
-
-
Port E2
Port E1
I2C data
I2C clock
—
—
Configurable
clock output
70 56 40
-
PE0/CLK_CCO I/O
X
X
X
—
O3
X
X
Port E0
—
71
72
-
-
-
-
-
-
PI6
PI7
I/O
I/O
X
X
X
X
—
—
—
—
O1
O1
X
X
X
X
Port I6
Port I7
—
—
—
—
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
Timer 3 -
channel 2
73 57 41 25 PD0/TIM3_CH2 I/O
X
X
X
HS O3
X
X
Port D0
SWIM data
interface
74 58 42 26
PD1/SWIM(3)
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS O4
HS O3
HS O3
HS O3
X
X
X
X
X
X
X
X
X
X
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
—
Timer 3 -
channel 1
TIM2_CH3
[AFR1]
75 59 43 27 PD2/TIM3_CH1 I/O
Timer 2 -
channel 2
ADC_ETR
[AFR0]
76 60 44 28 PD3/TIM2_CH2 I/O
PD4/TIM2_CH1/
Timer 2 -
channel 1
BEEPoutput
[AFR7]
77 61 45 29
I/O
BEEP
PD5/
LINUART_TX
LINUART
data transmit
78 62 46 30
I/O
—
—
—
O1
O1
O1
—
—
LINUART
data receive
X
X
X
PD6/
LINUART_RX
79 63 47 31
80 64 48 32
I/O
I/O
X
X
X
X
X
X
X
X
Top level
interrupt
PD7/TLI(4)
Port D7
—
36/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Pinouts and pin description
1. In Halt/Active-halt mode, this pin behaves as follows:
- The input/output path is disabled.
- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.
- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are
not implemented)
3. The PD1 pin is in input pull-up during the reset phase and after reset release.
4. If this pin is configured as interrupt pin, it will trigger the TLI.
6.2
Alternate function remapping
As shown in the rightmost column of Table 13, some alternate functions can be remapped at
different I/O ports by programming one of eight AFR (alternate function remap) option bits.
Refer to Section 9: Option bytes on page 51. When the remapping option is active, the
default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the STM8S and STM8A microcontroller families reference manual,
RM0016).
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Memory and register map
STM8AF52/62xx, STM8AF51/61xx
7
Memory and register map
7.1
Memory map
Figure 7.
Register and memory map
00 0000
Up to 6 Kbytes RAM
Stack
RAM end address
Reserved
00 4000
00 4800
Up to 2 Kbytes data EEPROM
Option bytes
Reserved
00 4900
00 5000
HW registers
00 5800
00 6000
00 6800
00 7F00
00 8000
00 8080
Reserved
2 Kbytes boot ROM
CPU/SWIM/Debug/ITC registers
IT vectors
Up to 128 Kbytes
Flash program memory
Memory end address
Table 14. Memory model 128K
Flash program
Flash program
RAM end
address
Stack roll-over
address
memory end
RAM size
memory size
address
128K
96K
64K
48K
32K
0x00 27FFF
0x00 1FFFF
0x00 17FFF
0x00 13FFF
0x00 0FFFF
0x00 17FF
0x00 17FF
0x00 17FF
0x00 0BFF
0x00 17FF
0x00 1400
0x00 1400
0x00 1400
n/a(1)
6K
3K
6K
0x00 1400
1. If the device contains the super set silicon (salestype contains SSS), the roll-over address is the same as
on the 128K device. For more information on stack handling refer to the “Memory and register map” section
in the reference manual RM0016. For more information on salestype composition, refer to section 13 in the
present document.
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Memory and register map
7.2
Register map
In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.
Table 15. I/O port hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX(1)
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
0x00
Port A control register 2
0x00
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00
0xXX(1)
Port B
Port C
Port D
Port E
Port F
0x00
0x00
Port B control register 2
0x00
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
0x00
0xXX(1)
0x00
0x00
Port C control register 2
0x00
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX(1)
0x00
0x02
Port D control register 2
0x00
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00
0xXX(1)
0x00
0x00
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX(1)
0x00
0x00
Port F control register 2
0x00
Doc ID 14395 Rev 9
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Memory and register map
Address
STM8AF52/62xx, STM8AF51/61xx
Table 15. I/O port hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
0x00
0xXX(1)
0x00
Port G
0x00
Port G control register 2
0x00
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
0x00
0xXX(1)
Port H
0x00
0x00
Port H control register 2
0x00
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
0x00
0xXX(1)
Port I
PI_DDR
PI_CR1
PI_CR2
0x00
0x00
Port I control register 2
0x00
1. Depends on the external circuitry.
Table 16. General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 505A
0x00 505B
0x00 505C
0x00 505D
FLASH_CR1
FLASH_CR2
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
FLASH_NCR2 Flash complementary control register 2
FLASH_FPR
Flash protection register
Flash
Flash complementary protection
register
0x00 505E
0x00 505F
FLASH_NFPR
0xFF
0x40
Flash in-application programming
status register
FLASH_IAPSR
0x00 5060 to
0x005061
Reserved area (2 bytes)
Flash Program memory unprotection
register
0x00 5062
Flash
Flash
FLASH_PUKR
FLASH_DUKR
0x00
0x00
0x00 5063
0x00 5064
Reserved area (1 byte)
Data EEPROM unprotection register
0x00 5065 to
0x00 509F
Reserved area (59 bytes)
40/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
0x00 50A2 to
0x00 50B2
Reserved area (17 bytes)
Reset status register
0x00 50B3
RST
CLK
RST_SR
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 bytes)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
Reserved area (1 byte)
0x01
0x00
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
CLK
CLK_CCOR
CLK_PCKENR2
CLK_HSITRIMR HSI clock calibration trimming register
0x00
0bXXXX
XXX0
0x00 50CD
CLK_SWIMCCR
SWIM clock control register
0x00 50CE
to 0x0050D0
Reserved area (3 bytes)
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
IWDG
0x0050D3to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX(2)
0x00
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
0x00 50F2
AWU_CSR1
AWU_APR
AWU_TBR
AWU control/status register 1
0x00
0x3F
0x00
AWU asynchronous prescaler buffer
register
AWU
AWU timebase selection register
Doc ID 14395 Rev 9
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Memory and register map
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 50F3
BEEP
BEEP_CSR
BEEP control/status register
0x1F
Reserved area (12 bytes)
0x00 50F4 to
0x00 50FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
Reserved area (8 bytes)
0x00 5208 to
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C frequency register
I2C own address register low
I2C own address register high
I2C_DR
I2C_SR1
I2C data register
I2C status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
I2C
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
0x00 521E to
0x00 522F
Reserved area (18 bytes)
42/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
UART1_SR
UART1_DR
USART status register
USART data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
USART baud rate register 1
USART baud rate register 2
USART control register 1
USART control register 2
USART control register 3
USART control register 4
USART control register 5
USART guard time register
USART prescaler register
USART
0x00 523B to
0x00 523F
Reserved area (5 bytes)
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5246
0x00 5247
0x00 5248
0x00 5249
UART3_SR
UART3_DR
LINUART status register
LINUART data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
UART3_BRR1
UART3_BRR2
UART3_CR1
UART3_CR2
UART3_CR3
UART3_CR4
LINUART baud rate register 1
LINUART baud rate register 2
LINUART control register 1
LINUART control register 2
LINUART control register 3
LINUART control register 4
Reserved
LINUART
UART3_CR6
LINUART control register 6
0x00
0x00 524A to
0x00 524F
Reserved area (6 bytes)
Doc ID 14395 Rev 9
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Memory and register map
Address
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1 status register 2
TIM1 event generation register
TIM1_CCMR1 TIM1 capture/compare mode register 1
TIM1_CCMR2 TIM1 capture/compare mode register 2
TIM1_CCMR3 TIM1 capture/compare mode register 3
TIM1_CCMR4 TIM1 capture/compare mode register 4
TIM1 capture/compare enable register
0x00 525C
0x00 525D
TIM1_CCER1
1
0x00
0x00
TIM1 capture/compare enable register
TIM1_CCER2
2
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter high
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1
TIM1 counter low
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
44/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 5270 to
0x00 52FF
Reserved area (147 bytes)
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
TIM2_CR1
TIM2_IER
TIM2 control register 1
TIM2 interrupt enable register
TIM2 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register
1
0x00 5308
0x00 5309
TIM2_CCER1
TIM2_CCER2
0x00
0x00
TIM2 capture/compare enable register
2
TIM2
0x00 530A
0x00 530B
00 530C0x
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM2 counter high
TIM2 counter low
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
Reserved area (11 bytes)
0x00 5315 to
0x00 531F
Doc ID 14395 Rev 9
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Memory and register map
Address
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5326
TIM3_CR1
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM3 status register 2
TIM3 event generation register
TIM3_CCMR1 TIM3 capture/compare mode register 1
TIM3_CCMR2 TIM3 capture/compare mode register 2
TIM3 capture/compare enable register
0x00 5327
TIM3_CCER1
1
0x00
TIM3
0x00 5328
0x00 5329
0x00 532A
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3 counter high
TIM3 counter low
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
TIM3 prescaler register
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
Reserved area (15 bytes)
0x00 5331 to
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
TIM4_CR1
TIM4_IER
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM4_SR
TIM4
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
46/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Memory and register map
Reset
Address
Block
Register label
Register name
status
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
0x00
0x00
0x00
0x00
0xXX
0xXX
ADC
ADC data register low
ADC Schmitt trigger disable register
high
0x00 5406
0x00 5407
ADC_TDRH
ADC_TDRL
0x00
0x00
ADC Schmitt trigger disable register
low
0x00 5408 to
0x00 541F
Reserved area (24 bytes)
0x00 5420
0x00 5421
0x00 5422
0x00 5423
0x00 5424
0x00 5425
0x00 5426
0x00 5427
0x00 5428
0x00 5429
0x00 542A
0x00 542B
0x00 542C
0x00 542D
0x00 542E
0x00 542F
0x00 5430
0x00 5431
0x00 5432
0x00 5433
0x00 5434
0x00 5435
0x00 5436
CAN_MCR
CAN_MSR
CAN_TSR
CAN_TPR
CAN_RFR
CAN_IER
CAN_DGR
CAN_FPSR
CAN_P0
CAN_P1
CAN_P2
CAN_P3
CAN_P4
CAN_P5
CAN_P6
CAN_P7
CAN_P8
CAN_P9
CAN_PA
CAN_PB
CAN_PC
CAN_PD
CAN_PE
CAN master control register
CAN master status register
CAN transmit status register
CAN transmit priority register
CAN receive FIFO register
CAN interrupt enable register
CAN diagnosis register
CAN page selection register
CAN paged register 0
CAN paged register 1
CAN paged register 2
CAN paged register 3
CAN paged register 4
CAN paged register 5
CAN paged register 6
CAN paged register 7
CAN paged register 8
CAN paged register 9
CAN paged register A
CAN paged register B
CAN paged register C
CAN paged register D
CAN paged register E
0x02
0x02
0x00
0x0C
0x00
0x00
0x0C
0x00
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
0xXX(3)
beCAN
Doc ID 14395 Rev 9
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Memory and register map
STM8AF52/62xx, STM8AF51/61xx
Table 16. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 5437
beCAN
CAN_PF
CAN paged register F
0xXX(3)
0x00 5438 to
0x00 57FF
Reserved area (968 bytes)
1. Depends on the previous reset source.
2. Write only register.
3. If the bootloader is enabled, it is initialized to 0x00.
Table 17. CPU/SWIM/debug module/interrupt controller registers
Reset
status
Address
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x80
0x00
0x00
0x00
0x00
0x00
0x17(2)
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CC
Stack pointer low
Condition code register
0x00 7F0B
to 0x00
7F5F
Reserved area (85 bytes)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F78
to
Reserved area (2 bytes)
0x00 7F79
0x00 7F80
SWIM
SWIM_CSR
SWIM control status register
0x00
48/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Memory and register map
Table 17. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Address
Block
Register label
Register name
0x00 7F81
to
Reserved area (15 bytes)
0x00 7F8F
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B
to 0x00
7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
2. Product dependent value, see Figure 7: Register and memory map.
Table 18. Temporary memory unprotection registers
Reset
status
Address
Block
Register label
Register name
0x00 5800
0x00 5801
0x00 5802
0x00 5803
0x00 5804
0x00 5805
0x00 5806
0x00 5807
TMU_K1
TMU_K2
TMU_K3
TMU_K4
TMU_K5
TMU_K6
TMU_K7
TMU_K8
Temporary memory unprotection key register 1
Temporary memory unprotection key register 2
Temporary memory unprotection key register 3
Temporary memory unprotection key register 4
Temporary memory unprotection key register 5
Temporary memory unprotection key register 6
Temporary memory unprotection key register 7
Temporary memory unprotection key register 8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TMU
Temporary memory unprotection control and status
register
0x00 5808
TMU_CSR
0x00
Doc ID 14395 Rev 9
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Interrupt table
STM8AF52/62xx, STM8AF51/61xx
8
Interrupt table
(1)
Table 19. STM8A interrupt table
Interrupt vector
address
Wakeup
Priority Source block
Description
Comments
from Halt
—
—
0
Reset
TRAP
TLI
Reset
0x00 6000
0x00 8004
0x00 8008
0x00 800C
Yes
—
Reset vector in ROM
SW interrupt
—
—
—
External top level interrupt
Auto-wakeup from Halt
—
1
AWU
Yes
Clock
controller
2
Main clock controller
0x00 8010
—
—
3
4
MISC
MISC
MISC
MISC
MISC
CAN
CAN
SPI
External interrupt E0
External interrupt E1
External interrupt E2
External interrupt E3
External interrupt E4
CAN interrupt Rx
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
Yes
Yes
Yes
Yes
Yes
Yes
—
Port A interrupts
Port B interrupts
Port C interrupts
Port D interrupts
Port E interrupts
—
5
6
7
8
9
CAN interrupt TX/ER/SC
End of transfer
—
10
Yes
—
Update/overflow/
trigger/break
11
Timer 1
0x00 8034
—
—
12
13
14
15
16
17
18
19
20
21
22
23
Timer 1
Timer 2
Timer 2
Timer 3
Timer 3
USART
USART
I2C
Capture/compare
Update/overflow
Capture/compare
Update/overflow
Capture/compare
Tx complete
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
—
—
—
—
—
—
—
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive data full reg.
I2C interrupts
LINUART
LINUART
ADC
Tx complete/error
Receive data full reg.
End of conversion
Update/overflow
Timer 4
End of programming/
write in not allowed area
24
EEPROM
0x00 8068
—
—
1. All unused interrupts must be initialized with ‘IRET’ for robust programming.
50/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Option bytes
9
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 20: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be changed in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 20. Option bytes
Option
Option
name
Option bits
Factory
default
setting
Addr.
byte
no.
7
6
5
4
3
2
1
0
Read-out
protection
(ROP)
0x00
4800
OPT0
ROP[7:0]
0x00
0x00
4801
OPT1
NOPT1
OPT2
UBC[7:0]
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
User boot
code
(UBC)
0x00
4802
NUBC[7:0]
0x00
4803
Alternate
function
remapping
(AFR)
AFR7 AFR6 AFR5 AFR4 AFR3
AFR2
AFR1
AFR0
0x00
4804
NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0
0x00
4805
LSI_
EN
IWDG
_HW
WWD
G _HW _HALT
WWDG
OPT3
NOPT3
OPT4
Reserved
Reserved
Reserved
Reserved
Watchdog
option
0x00
4806
NLSI_ NIWD
EN
NWWD NWWG
G_HW
G_HW
_HALT
0x00
4807
EXT
CLK
CKAW
USEL
PRSC1 PRSC0
Clock
option
0x00
4808
NEXT NCKAW
CLK
NPRSC
NOPT4
OPT5
NPRSC1
0
USEL
0x00
4809
HSECNT[7:0]
HSE clock
startup
0x00
480A
NOPT5
NHSECNT[7:0]
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Option bytes
STM8AF52/62xx, STM8AF51/61xx
Table 20. Option bytes (continued)
Option
Option
name
Option bits
Factory
default
setting
Addr.
byte
no.
7
6
5
4
3
2
1
0
0x00
480B
OPT6
NOPT6
OPT7
TMU[3:0]
0x00
TMU
0x00
480C
NTMU[3:0]
0xFF
0x00
0xFF
0x00
480D
WAIT
STATE
Reserved
Flash wait
states
0x00
480E
NWAIT
STATE
NOPT7
Reserved
0x00
480F
Reserved
0x00
4810
OPT8
OPT9
TMU_KEY 1 [7:0]
TMU_KEY 2 [7:0]
TMU_KEY 3 [7:0]
TMU_KEY 4 [7:0]
TMU_KEY 5 [7:0]
TMU_KEY 6 [7:0]
TMU_KEY 7 [7:0]
TMU_KEY 8 [7:0]
TMU_MAXATT [7:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xC7
0x00
4811
0x00
4812
OPT10
OPT11
OPT12
OPT13
OPT14
OPT15
OPT16
0x00
4813
0x00
4814
TMU
0x00
4815
0x00
4816
0x00
4817
0x00
4818
0x00
4819
to
Reserved
487D
0x00
487E
OPT17
BL [7:0]
0x00
0xFF
Boot-
loader(1)
0x00
487F
NOPT
17
NBL [7:0]
1. This option consists of two bytes that must have a complementary value in order to be valid. If the option is invalid, it has no
effect on EMC reset.
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Option bytes
Table 21. Option byte description
Option byte no.
Description
ROP[7:0]: Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM memory readout protection for
details.
OPT0
UBC[7:0]: User boot code area
0x00: No UBC, no write-protection
0x01: Page 0 to 1 defined as UBC, memory write-protected
0x02: Page 0 to 3 defined as UBC, memory write-protected
0x03 to 0xFF: Pages 4 to 255 defined as UBC, memory write-protected
Note: Refer to the STM8A microcontroller family reference manual
(RM0016) section on Flash/EEPROM write protection for more details.
OPT1
AFR7: Alternate function remapping option 7
0: Port D4 alternate function = TIM2_CH1
1: Port D4 alternate function = BEEP
AFR6: Alternate function remapping option 6
0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4
1: Port B5 alternate function = I2C_SDA, port B4 alternate function =
I2C_SCL.
AFR5: Alternate function remapping option 5
0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2,
port B1 alternate function = AIN1, port B0 alternate function = AIN0.
1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =
TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate
function = TIM1_CH1N.
AFR4: Alternate function remapping option 4
0: Port D7 alternate function = TLI
1: Reserved
OPT2
AFR3: Alternate function remapping option 3
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = TIM1_BKIN
AFR2: Alternate function remapping option 2
0: Port D0 alternate function = TIM3_CH2
1: Port D0 alternate function = CLK_CCO
Note: AFR2 option has priority over AFR3 if both are activated
AFR1: Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3, port D2 alternate function
TIM3_CH1.
1: Port A3 alternate function = TIM3_CH1, port D2 alternate function
TIM2_CH3.
AFR0: Alternate function remapping option 0
0: Port D3 alternate function = TIM2_CH2
1: Port D3 alternate function = ADC_ETR
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Option bytes
Table 21. Option byte description (continued)
STM8AF52/62xx, STM8AF51/61xx
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
OPT3
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto-wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
OPT4
PRSC[1:0]: AWU clock prescaler
00: 24 MHz to 128 kHz prescaler
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilization time to 0.5, 8, 128, and 2048 HSE
cycles with corresponding option byte values of 0xE1, 0xD2, 0xB4, and
0x00.
OPT5
OPT6
TMU[3:0]: Enable temporary memory unprotection
0101: TMU disabled (permanent ROP).
Any other value: TMU enabled.
WAIT STATE: Wait state configuration
This option configures the number of wait states inserted when reading
from the Flash/data EEPROM memory.
0: No wait state
OPT7
1: One wait state
TMU_KEY 1 [7:0]: Temporary unprotection key 0
OPT8
OPT9
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 2 [7:0]: Temporary unprotection key 1
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 3 [7:0]: Temporary unprotection key 2
OPT10
OPT11
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 4 [7:0]: Temporary unprotection key 3
Temporary unprotection key: Must be different from 0x00 or 0xFF
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Table 21. Option byte description (continued)
Option bytes
Option byte no.
Description
TMU_KEY 5 [7:0]: Temporary unprotection key 4
OPT12
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 6 [7:0]: Temporary unprotection key 5
OPT13
OPT14
OPT15
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 7 [7:0]: Temporary unprotection key 6
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_KEY 8 [7:0]: Temporary unprotection key 7
Temporary unprotection key: Must be different from 0x00 or 0xFF
TMU_MAXATT [7:0]: TMU access failure counter
TMU_MAXATT can be initialized with the desired value only if TMU is
disabled (TMU[3:0]=0101 in OPT6 option byte).
OPT16
OPT17
When TMU is enabled, any attempt to temporary remove the readout
protection by using wrong key values increments the counter.
When the option byte value reaches 0x08, the Flash memory and data
EEPROM are erased.
BL[7:0]: Bootloader enable
If this option byte is set to 0x55 (complementary value 0xAA) the
bootloader program is activated also in case of a programmed code
memory (for more details, see the bootloader user manual, UM0560).
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
10
Electrical characteristics
10.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
10.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = -40 °C, T = 25 °C, and
A
A
T = T
(given by the selected temperature range).
A
Amax
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
10.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are
A
DD
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.
10.1.3
10.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
Figure 8.
Pin loading conditions
STM8A pin
50 pF
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Electrical characteristics
10.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 9. Pin input voltage
STM8A pin
V
IN
10.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 22. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
(1)
V
DDx - VSS Supply voltage (including VDDA and VDDIO
)
-0.3
VSS - 0.3
VSS - 0.3
—
6.5
6.5
V
Input voltage on true open drain pins (PE1, PE2)(2)
Input voltage on any other pin(2)
VIN
V
VDD + 0.3
50
|VDDx - VDD| Variations between different power pins
mV
|VSSx - VSS| Variations between all the different ground pins
—
50
see Absolute maximum ratings
(electrical sensitivity) on
page 85
VESD
Electrostatic discharge voltage
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Table 23. Current characteristics
Symbol
Ratings
Max.
Unit
IVDDIO
IVSSIO
Total current into VDDIO power lines (source)(1)(2)(3)
Total current out of VSS IO ground lines (sink)(1)(2)(3)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on any pin
100
100
20
IIO
mA
-20
10
(4)
IINJ(PIN)
IINJ(TOT)
Sum of injected currents
50
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
2. The total limit applies to the sum of operation and injected currents.
3. VDDIO includes the sum of the positive injection currents. VSSIO includes the sum of the negative injection
currents.
4. This condition is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the
injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >
VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive
injection current allowed and the corresponding VIN maximum must always be respected.
Table 24. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to 150
160
°C
Maximum junction temperature
(1)
Table 25. Operating lifetime
Symbol
Ratings
Value
Unit
−40 to 125 °C
−40 to 150 °C
Grade 1
Grade 0
OLF
Conforming to AEC-Q100 rev G
1. For detailed mission profile analysis, please contact your local ST Sales Office.
58/110
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Electrical characteristics
10.3
Operating conditions
Table 26. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
1 wait state
TA = -40 °C to 150 °C
16
24
fCPU
Internal CPU clock frequency
MHz
0 wait state
TA = -40 °C to 150 °C
0
16
5.5
VDD/VDDIO Standard operating voltage
-
3.0
470
V
CEXT: capacitance of external
capacitor
3300
nF
(1)
VCAP
ESR of external capacitor
ESL of external capacitor
-
-
0.3
15
Ω
at 1 MHz(2)
nH
Suffix A
Suffix B
Suffix C
Suffix D
Suffix A
Suffix B
Suffix C
Suffix D
85
105
125
150
90
TA
Ambient temperature
- 40
°C
110
130
155
TJ
Junction temperature range
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
Figure 10. f
versus V
DD
CPUmax
fCPU [MHz]
24
16
Functionality guaranteed
Functionality
not guaranteed
in this area
@ T -40 to 150 °C at 1 waitstate
A
12
8
Functionality guaranteed
@ T -40 to 150 °C at 0 waitstate
A
4
0
3.0
4.0
5.0
5.5
Supply voltage [V]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Table 27. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
VDD fall time rate
—
—
2(1)
2(1)
—
—
—
3
tVDD
µs/V
Reset release delay
Reset generation delay
VDD rising
—
—
ms
µs
tTEMP
V
DD falling
—
3
Power-on reset
threshold(2)
VIT+
VIT-
—
2.65
2.58
—
2.8
2.95
2.88
V
Brown-out reset
threshold
—
—
2.73
70(1)
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production.
2. If VDD is below 3 V, the code execution is guaranteed above the VIT- and VIT+ thresholds. RAM content is
kept. The EEPROM programming sequence must not be initiated.
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 26. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 11. External capacitor C
EXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 56 and Figure 9 on
page 57.
If not explicitly stated, general conditions of temperature and voltage apply.
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Electrical characteristics
Table 28. Total current consumption in Run, Wait and Slow mode. General conditions
for V apply, T = −40 °C to 150 °C
DD
A
Symbol
Parameter
Conditions
fCPU = 24 MHz 1 ws
Typ
Max
Unit
8.7
7.4
16.8(2)
All peripherals
clocked, code
fCPU = 16 MHz
fCPU = 8 MHz
fCPU = 4 MHz
fCPU = 2 MHz
fCPU = 24 MHz
fCPU = 16 MHz
14
Supply current in executed from Flash
Run mode
(1)
IDD(RUN)
4.0
7.4(2)
4.1(2)
2.5
program memory,
HSE external clock
(without resonator)
2.4
1.5
4.4
6.0(2)
All peripherals
clocked, code
3.7
5.0
Supply current in
Run mode
IDD(RUN)
executed from RAM,
HSE external clock
(without resonator)
f
CPU = 8 MHz
2.2
3.0(2)
2.0(2)
1.5
(1)
fCPU = 4 MHz
fCPU = 2 MHz
fCPU = 24 MHz
fCPU = 16 MHz
1.4
mA
1.0
2.4
3.1(2)
1.65
1.15
0.90
0.80
2.5
CPU stopped, all
peripherals off, HSE
external clock
Supply current in
Wait mode
IDD(WFI)
fCPU = 8 MHz
1.9(2)
1.6(2)
1.5
(1)
fCPU = 4 MHz
fCPU = 2 MHz
External clock 16 MHz
fCPU = 125 kHz
fCPU scaled down,
Supply current in all peripherals off,
1.50
1.50
1.95
(1)
IDD(SLOW)
Slow mode
code executed from
RAM
LSI internal RC
fCPU = 128 kHz
1.80(2)
1. The current due to I/O utilization is not taken into account in these values.
2. Values not tested in production. Design guidelines only.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Table 29. Total current consumption in Halt and Active-halt modes. General conditions for V
DD
applied. T = −40 °C to 55 °C unless otherwise stated
A
Conditions
Main
Symbol
Parameter
Typ
Max
Unit
voltage
regulator
(MVR)(1)
Flash
Clock source and
temperature condition
mode(2)
Clocks stopped
5
5
35(3)
25
Supply current in
Halt mode
Power-
down
IDD(H)
Off
On
Off
Clocks stopped,
TA = 25 °C
External clock 16 MHz
fMASTER = 125 kHz
900(3)
Supply current in
Active-halt mode
with regulator on
770
Power-
down
µA
LSI clock 128 kHz
LSI clock 128 kHz
150
25
230(3)
42(3)
IDD(AH)
Supply current in
Active-halt mode
with regulator off
Power-
down
LSI clock 128 kHz,
TA = 25 °C
25
10
30
Wakeup time from
Active-halt mode
with regulator on
On
Off
30(3)
Operating
mode
tWU(AH)
TA =−40 to 150 °C
µs
Wakeup time from
Active-halt mode
with regulator off
50
80(3)
1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
3. Data based on characterization results. Not tested in production.
Current consumption for on-chip peripherals
Table 30. Oscillator current consumption
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
Quartz or
ceramic
resonator,
CL = 33 pF
VDD = 5 V
f
f
OSC = 24 MHz
1
2.0(3)
—
HSE oscillator current
consumption(2)
OSC = 16 MHz
fOSC = 8 MHz
0.6
IDD(OSC)
0.57
—
mA
Quartz or
ceramic
resonator,
CL = 33 pF
VDD = 3.3 V
fOSC = 24 MHz
fOSC = 16 MHz
0.5
1.0(3)
—
HSE oscillator current
consumption(2)
0.25
IDD(OSC)
fOSC = 8 MHz
0.18
—
1. During startup, the oscillator current consumption may reach 6 mA.
2. The supply current of the oscillator can be further optimized by selecting a high quality resonator with small Rm value. Refer
to crystal manufacturer for more details
3. Informative data.
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Electrical characteristics
Table 31. Programming current consumption
Symbol
Parameter
Conditions
Typ
Max
Unit
VDD = 5 V, -40 °C to 150 °C, erasing
and programming data or Flash
program memory
IDD(PROG) Programming current
1.0
1.7
mA
(1)
Table 32. Typical peripheral current consumption V = 5.0 V
DD
Typ.
= 2 MHz f
Typ.
Typ.
= 16 MHz f =24 MHz
master
Symbol
Parameter
Unit
f
master
master
IDD(TIM1)
IDD(TIM2)
IDD(TIM3)
IDD(TIM4)
TIM1 supply current(2)
TIM2 supply current (2)
TIM3 supply current(2)
TIM4 supply current(2)
0.03
0.02
0.01
0.004
0.03
0.03
0.01
0.02
0.06
0.003
0.22
0.23
0.12
0.1
0.34
0.19
0.16
0.05
0.15
0.18
0.07
0.91
0.40
0.05
2.4
0.03
0.09
0.11
0.04
0.06
0.30
0.02
1
IDD(USART) USART supply current(2)
IDD(LINUART) LINUART supply current(2)
mA
IDD(SPI)
IDD(I C)
IDD(CAN)
IDD(AWU)
SPI supply current(2)
I2C supply current(2)
CAN supply current(3)
AWU supply current(2)
2
IDD(TOT_DIG) All digital peripherals on
ADC supply current when
IDD(ADC)
0.93
0.95
0.96
converting(4)
1. Typical values not tested in production. Since the peripherals are powered by an internally regulated, constant digital
supply voltage, the values are similar in the full supply voltage range.
2. Data based on a differential IDD measurement between no peripheral clocked and a single active peripheral. This
measurement does not include the pad toggling consumption.
3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data
transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption.
4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Current consumption curves
Figure 12 to Figure 17 show typical current consumption measured with code executing in
RAM.
Figure 12. Typ. I
vs. V
Figure 13. Typ. I
vs. f
DD(RUN)HSE
DD
DD(RUN)HSE CPU
@f
= 16 MHz, peripherals = on
@ V = 5.0 V, peripherals = on
CPU
DD
10
10
25°C
85°C
12 5°C
25°C
85°C
12 5°C
9
8
9
8
7
7
6
6
5
5
4
3
4
3
2
1
2
1
0
0
2.5
3
3.5
4
4.5
5
5.5
6
0
5
10
15
20
25
30
VDD [V]
fcpu [MHz]
Figure 14. Typ. I
vs. V
Figure 15. Typ. I
vs. V
DD(RUN)HSI
DD
DD(WFI)HSE DD
@ f
= 16 MHz, peripherals = off
@ f
= 16 MHz, peripherals = on
CPU
CPU
6
5
4
3
2
1
0
4
3
2
1
0
25°C
85°C
125°C
25°C
85°C
125°C
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VDD [V]
VDD [V]
Figure 16. Typ. I
vs. f
Figure 17. Typ. I
vs. V
DD(WFI)HSE
CPU
DD(WFI)HSI DD
@ V = 5.0 V, peripherals = on
@ f
= 16 MHz, peripherals = off
DD
CPU
2.5
2
6
5
4
1.5
3
2
1
0
1
0.5
0
25°C
85°C
12 5°C
25°C
85°C
12 5°C
2.5
3
3.5
4
4.5
5
5.5
6
0
5
10
15
20
25
30
VDD [V]
fcpu [MHz]
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Electrical characteristics
10.3.3
External clock sources and timing characteristics
HSE external clock
An HSE clock can be generated by feeding an external clock signal of up to 24 MHz to the
OSCIN pin.
Clock characteristics are subject to general operating conditions for V and T .
DD
A
Table 33. HSE external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
TA = -40 °C to 150 °C
0(1)
—
—
—
24
—
MHz
VHSEdHL Comparator hysteresis
—
—
0.1 x VDD
0.7 x VDD
OSCIN high-level input pin
voltage
VHSEH
VDD
V
OSCIN low-level input pin
voltage
VHSEL
—
VSS
-1
—
—
0.3 x VDD
+1
ILEAK_HSE OSCIN input leakage current
VSS < VIN < VDD
µA
1. If CSS is used, the external clock must have a frequency above 500 kHz.
Figure 18. HSE external clock source
V
V
HSEH
HSEL
f
HSE
External clock
source
OSCIN
STM8A
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz.
All the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Table 34. HSE oscillator characteristics
Symbol
Parameter
Feedback resistor
Conditions
Min
Typ
Max
Unit
RF
—
—
—
—
—
5
220
—
—
20
—
kΩ
pF
(1)
CL1/CL2
gm
Recommended load capacitance
Oscillator trans conductance
—
mA/V
V
DD is
(2)
tSU(HSE)
Startup time
—
2.8
—
ms
stabilized
1. The oscillator needs two load capacitors, CL1 and CL2, to act as load for the crystal. The total load capacitance (CLoad) is
(CL1 * CL2)/(CL1 + CL2). If CL1 = CL2, Cload = CL1/2. Some oscillators have built-in load capacitors, CL1 and CL2
.
2. This value is the startup time, measured from the moment it is enabled (by software) until a stabilized 24 MHz oscillation is
reached. It can vary with the crystal type that is used.
Figure 19. HSE oscillator circuit diagram
f
to core
HSE
R
m
R
F
C
O
L
m
C
L1
OSCIN
C
m
g
m
Resonator
Current control
Resonator
STM8A
OSCOUT
C
L2
HSE oscillator critical gm formula
The crystal characteristics have to be checked with the following formula:
Equation 1
g
m » gmcrit
where g
can be calculated with the crystal parameters as follows:
mcrit
Equation 2
f
gmcrit = (2 × Π × HSE)2 × Rm(2Co + C)2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C
= C = C: Grounded external capacitance
L1
L2
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STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
10.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T .
DD
A
High-speed internal RC oscillator (HSI)
Table 35. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
—
—
16
—
MHz
Trimmed by the application
for any VDD and TA
conditions
HSI oscillator user
trimming accuracy
-1
—
1
ACCHS
%
HSI oscillator accuracy
(factory calibrated)
VDD = 3.0 V ≤ VDD ≤ 5.5 V,
-40 °C ≤ TA ≤ 150 °C
-5
—
—
5
tsu(HSI) HSI oscillator wakeup time
—
—
2(1)
µs
1. Guaranteed by characterization, not tested in production
Figure 20. Typical HSI frequency vs V
DD
3%
2%
-40°C
25°C
85°C
125°C
1%
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Low-speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 36. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
—
—
112
—
128
—
144
7(1)
kHz
µs
tsu(LSI) LSI oscillator wakeup time
1. Data based on characterization results, not tested in production.
Figure 21. Typical LSI frequency vs V
DD
3%
2%
1%
25°C
0%
-1%
-2%
-3%
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
10.3.5
Memory characteristics
Flash program memory/data EEPROM memory
General conditions: T = -40 °C to 150 °C.
A
Table 37. Flash program memory/data EEPROM memory
Symbol
Parameter
Conditions
Min(1) Typ Max
Unit
f
CPU is 16 to 24 MHz
with 1 ws
Operating voltage
(all modes, execution/write/erase)
VDD
3.0
—
5.5
fCPU is 0 to 16 MHz
with 0 ws
V
fCPU is 16 to 24 MHz
with 1 ws
fCPU is 0 to 16 MHz
with 0 ws
VDD
Operating voltage (code execution)
2.6
—
—
6
5.5
6.6
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
—
tprog
ms
ms
Fast programming time for 1 block
(128 bytes)
—
—
—
—
3
3
3.3
3.3
terase Erase time for 1 block (128 bytes)
1. Guaranteed by characterization, not tested in production.
Table 38. Flash program memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
—
-40
150
—
°C
Flash program memory endurance
(erase/write cycles)(1)
NWE
TA = 25 °C
1000
cycles
TA = 25 °C
TA = 55 °C
40
20
—
—
tRET
Data retention time
years
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Table 39. Data memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
—
-40
150
—
°C
Data memory endurance(1)
(erase/write cycles)
TA = 25 °C
300 k
NWE
cycles
years
TA = -40°C to 125 °C
TA = 25 °C
100 k(2)
40(2)(3)
20(2)(3)
—
—
tRET
Data retention time
TA = 55 °C
—
1. The physical granularity of the memory is four bytes, so cycling is performed on four bytes even when a
write/erase operation addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is
available in a separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
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Electrical characteristics
10.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 40. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Low-level input voltage
High-level input voltage
-0.3 V
0.3 x VDD
VIH
0.7 x VDD
VDD + 0.3 V
—
0.1 x
VDD
Vhys
Hysteresis(1)
—
—
—
—
—
Standard I/0, VDD = 5 V,
I = 3 mA
V
DD - 0.5 V
—
—
VOH
High-level output voltage
Standard I/0, VDD = 3 V,
I = 1.5 mA
V
DD - 0.4 V
High sink and true open
drain I/0, VDD = 5 V
I = 8 mA
—
—
—
—
0.5
0.6
VOL
Low-level output voltage
Pull-up resistor
Standard I/0, VDD = 5 V
I = 3 mA
V
Standard I/0, VDD = 3 V
I = 1.5 mA
—
35
—
—
50
—
0.4
65
Rpu
VDD = 5 V, VIN = VSS
kΩ
Fast I/Os
Load = 50 pF
35(2)
Standard and high sink I/Os
Load = 50 pF
—
—
125(2)
20(2)
50(2)
1
Rise and fall time
(10% - 90%)
tR, tF
ns
Fast I/Os
Load = 20 pF
Standard and high sink I/Os
Load = 20 pF
Digital input pad leakage
current
Ilkg
VSS ≤ VIN ≤ VDD
—
—
—
—
—
—
—
—
—
—
µA
nA
VSS ≤ VIN ≤ VDD
-40 °C < TA < 125 °C
250
500
1(3)
60
Analog input pad leakage
current
Ilkg ana
VSS ≤ VIN ≤ VDD
-40 °C < TA < 150 °C
Leakage current in
adjacent I/O(3)
Ilkg(inj)
IDDIO
Injection current 4 mA
µA
Total current on either
Including injection currents
mA
VDDIO or VSSIO
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
Doc ID 14395 Rev 9
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
2. Guaranteed by design.
3. Data based on characterization results, not tested in production.
Figure 22. Typical V and V vs V @ four temperatures
IL
IH
DD
6
5
4
3
2
1
0
-40°C
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 23. Typical pull-up resistance R vs V @ four temperatures
PU
DD
60
55
50
45
40
35
30
-40°C
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
(1)
Figure 24. Typical pull-up current I vs V @ four temperatures
pu
DD
140
120
100
80
-40°C
25°C
85°C
125°C
60
40
20
0
0
1
2
3
4
5
6
VDD [V]
1. The pull-up is a pure resistor (slope goes through 0).
Typical output level curves
Figure 25 to Figure 34 show typical output level curves measured with output on a single pin.
Figure 25. Typ. V @ V = 3.3 V (standard
Figure 26. Typ. V @ V = 5.0 V (standard
OL DD
OL
DD
ports)
ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
1.5
1.25
1
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
I
OL [mA]
IOL [mA]
Figure 27. Typ. V @ V = 3.3 V (true open Figure 28. Typ. V @ V = 5.0 V (true open
OL
DD
OL
DD
drain ports)
drain ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOL [mA]
IOL [mA]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 29. Typ. V @ V = 3.3 V (high sink
Figure 30. Typ. V @ V = 5.0 V (high sink
OL DD
OL
DD
ports)
ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
1.5
1.25
1
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOL [mA]
IOL [mA]
Figure 31. Typ. V
V
@ V = 3.3 V
Figure 32. Typ. V
V
@ V = 5.0 V
DD - OH
DD
DD - OH DD
(standard ports)
(standard ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
0
2
4
6
8
10
12
IOH [mA]
IOH [mA]
Figure 33. Typ. V
V
@ V = 3.3 V (high Figure 34. Typ. V
V
@ V = 5.0 V (high
DD - OH
DD
DD - OH DD
sink ports)
sink ports)
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
2
1.75
1.5
1.25
1
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
0
5
10
15
20
25
IOH [mA]
IOH [mA]
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Electrical characteristics
10.3.7
Reset pin characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 41. NRST pin characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST low-level input voltage(1)
VIH(NRST) NRST high-level input voltage(1)
—
—
VSS
—
—
—
40
—
0.3 x VDD
VDD
—
0.7 x VDD
VOL(NRST) NRST low-level output voltage(1) IOL = 3 mA
0.6
V
RPU(NRST) NRST pull-up resistor
—
—
30
85
60
kΩ
ns
tIFP
NRST input filtered pulse(1)
315
NRST Input not filtered pulse
duration(2)
tIFP(NRST)
500
ns
1. Data based on characterization results, not tested in production.
2. Data guaranteed by design, not tested in production.
Figure 35. Typical NRST V and V vs V @ four temperatures
IL
IH
DD
-40°C
6
5
4
3
2
1
0
25°C
85°C
125°C
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 36. Typical NRST pull-up resistance R vs V
PU
DD
-40°C
25°C
85°C
125°C
60
55
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 37. Typical NRST pull-up current I vs V
pu
DD
140
120
100
80
60
-40°C
25°C
85°C
125°C
40
20
0
0
1
2
3
4
5
6
VDD [V]
The reset network shown in Figure 38 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below V max (see Table 41:
IL(NRST)
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is 10 nF.
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Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Figure 38. Recommended reset pin protection
Electrical characteristics
STM8A
VDD
RPU
External
reset
NRST
Internal reset
Filter
circuit
(optional)
0.1µF
10.3.8
TIM 1, 2, 3, and 4 electrical specifications
Subject to general operating conditions for V , f
and T .
A
DD MASTER
Table 42. TIM 1, 2, 3, and 4 electrical specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fEXT
Timer external clock frequency(1)
—
—
—
24
MHz
1. Not tested in production.
Doc ID 14395 Rev 9
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
SPI interface
10.3.9
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, f frequency, and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
Slave mode
0
0
0
10
fSCK
1/tc(SCK)
SPI clock frequency
VDD < 4.5 V
VDD = 4.5 V to 5.5 V
6(1)
8(1)
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
—
25(2)
(3)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 * tMASTER
70
—
—
(3)
th(NSS)
(3)
(3)
tw(SCKH)
tw(SCKL)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15
tSCK/2 + 15
(3)
(3)
(3)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
5
—
—
—
—
tsu(MI)
tsu(SI)
(3)
5
(3)
7
th(MI)
th(SI)
ns
Data input hold time
(3)
10
—
25
—
—
—
31
12
(3)(4)
ta(SO)
Data output access time
Data output disable time
3* tMASTER
(3)(5)
tdis(SO)
VDD < 4.5 V
75
53
30
—
—
Slave mode
(after enable edge)
(3)
(3)
tv(SO)
Data output valid time
Data output valid time
Data output hold time
V
DD = 4.5 V to 5.5 V
tv(MO)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
(3)
th(SO)
(3)
th(MO)
1. fSCK < fMASTER/2.
2. The pad has to be configured accordingly (fast mode).
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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Electrical characteristics
Figure 39. SPI timing diagram in slave mode and with CPHA = 0
NSS input
t
t
t
SU(NSS)
c(SCK)
h(NSS)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
Figure 40. SPI timing diagram in slave mode and with CPHA = 1
NSS input
t
t
t
SU(NSS)
t
c(SCK)
h(NSS)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
Figure 41. SPI timing diagram - master mode
(IGH
.33 INPUT
T
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#0/,ꢄꢅ
#0(!ꢄꢀ
#0/,ꢄꢀ
T
T
T
T
Wꢆ3#+(ꢇ
Wꢆ3#+,ꢇ
Rꢆ3#+ꢇ
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T
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T
T
Vꢆ-/ꢇ
Hꢆ-/ꢇ
AIꢀꢁꢀꢂꢃ
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
80/110
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Electrical characteristics
2
10.3.10 I C interface characteristics
2
Table 44. I C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
—
—
—
—
1.3
0.6
—
—
µs
250
0(3)
100
0(4)
—
th(SDA)
SDA data hold time
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
(VDD 3 V to 5.5 V)
ns
—
—
1000
300
—
—
300
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
(VDD 3 V to 5.5 V)
th(STA)
START condition hold time
4.0
4.7
4.0
—
—
—
0.6
0.6
0.6
—
—
—
µs
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
µs
µs
pF
STOP to START condition time
tw(STO:STA)
(bus free)
4.7
—
1.3
—
—
Cb
Capacitive load for each bus line
—
400
400
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
Doc ID 14395 Rev 9
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
10.3.11 10-bit ADC characteristics
Subject to general operating conditions for V
specified.
, f
and T unless otherwise
DDA MASTER
A
Table 45. ADC characteristics
Symbol
Parameter
Conditions
Min
111 kHz
3
Typ
—
Max
Unit
fADC
ADC clock frequency
—
—
—
—
4 MHz kHz/MHz
VDDA Analog supply
—
5.5
VREF+ Positive reference voltage
VREF- Negative reference voltage
2.75
—
VDDA
VSSA
VSSA
—
—
0.5
V
VDDA
—
Conversion voltage range(1)
Devices with
external VREF+
VAIN
/
VREF-
—
VREF+
VREF- pins
Csamp Internal sample and hold capacitor
—
—
—
—
—
—
1.5
0.75
7
3
pF
µs
fADC = 2 MHz
—
—
—
Sampling time
(3 x 1/fADC
(1)
tS
)
f
f
ADC = 4 MHz
ADC = 2 MHz
tSTAB Wakeup time from standby
fADC = 4 MHz
fADC = 2 MHz
3.5
7
Total conversion time including
tCONV sampling time
—
—
—
—
—
fADC = 4 MHz
—
3.5
—
(14 x 1/fADC
)
Rswitch Equivalent switch resistance
30
kΩ
1. During the sample time, the sampling capacitance, Csamp (3 pF typ), can be charged/discharged by the
external source. The internal resistance of the analog source must allow the capacitance to reach its final
voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no
effect on the conversion result.
Figure 42. Typical application with ADC
VDD
STM8A
VT
Rswitch
0.6V
RAIN
AINx
10-bit A/D
conversion
VAIN
Ts
CAIN
VT
0.6V
IL
Csamp
1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
82/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
Table 46. ADC accuracy for V
= 5 V
DDA
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
|ET|
|EO|
|EG|
|ED|
|EL|
|ET|
|EO|
|EG|
|ED|
|EL|
Total unadjusted error(2)
Offset error(2)
1.4
0.8
3(3)
3
Gain error(2)
fADC = 2 MHz
0.1
2
Differential linearity error(2)
Integral linearity error(2)
Total unadjusted error(2)
Offset error(2)
0.9
1
0.7
1.5
4(4)
4(4)
3(4)
2(4)
1.5(4)
LSB
1.9(4)
1.3(4)
0.6(4)
1.5(4)
1.2(4)
Gain error(2)
fADC = 4 MHz
Differential linearity error(2)
Integral linearity error(2)
1. Max value is based on characterization, not tested in production.
2. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
3. TUE 2LSB can be reached on specific salestypes on the whole temperature range.
4. Target values.
Figure 43. ADC accuracy characteristics
EG
1023
V
– V
1022
1021
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
ET
(3)
7
6
5
4
3
2
1
(1)
EO
EL
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
1021102210231024
VSSA
V
DDA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
E
E
E
O = Offset error: Deviation between the first actual transition and the first ideal one.
G = Gain error: Deviation between the last ideal transition and the last actual one.
D = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.
Doc ID 14395 Rev 9
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Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
10.3.12 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 47. EMS data
Symbol
Parameter
Conditions
Level/class
VDD = 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VFESD
3B
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD= 3.3 V, TA= 25 °C,
fMASTER = 16 MHz (HSI clock),
Conforms to IEC 1000-4-4
4A
84/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 48. EMI data
Conditions
(1)
Max fCPU
Symbol
Parameter
Unit
General
Monitored
8
16
24
conditions
frequency band
MHz MHz MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
—
15
18
-1
2
17
22
3
22
16
5
VDD = 5 V,
TA = 25 °C,
Peak level
SEMI
LQFP80 package
conforming to SAE
J 1752/3
dBµV
SAE EMI level
2.5
2.5
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 49. ESD absolute maximum ratings
Maximum Uni
Symbol
Ratings
Conditions
Class
value(1)
t
Electrostatic discharge voltage
(human body model)
TA = 25 °C, conforming to
VESD(HBM)
VESD(CDM)
VESD(MM)
3A
3
4000
JESD22-A114
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming to
500
200
V
JESD22-C101
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming to
B
JESD22-A115
1. Data based on characterization results, not tested in production
Doc ID 14395 Rev 9
85/110
Electrical characteristics
Static latch-up
STM8AF52/62xx, STM8AF51/61xx
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
●
A supply overvoltage (applied to each power supply pin) and
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
●
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50. Electrical sensitivities
Symbol
Parameter
Conditions
Class(1)
TA = 25 °C
TA = 85 °C
TA = 125 °C
TA = 150 °C
LU
Static latch-up class
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
86/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Electrical characteristics
10.4
Thermal characteristics
In case the maximum chip junction temperature (T
) specified in Table 26: General
Jmax
operating conditions is exceeded, the functionality of the device cannot be guaranteed.
T
, in degrees Celsius, may be calculated using the following equation:
Jmax
Equation 3
T
= T
+ (P
x Θ )
Dmax JA
Jmax
Amax
where:
T
is the maximum ambient temperature in °C
Amax
Θ
is the package junction-to-ambient thermal resistance in ° C/W
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
INTmax
DD
DD
internal power.
P
represents the maximum power dissipation on output pins
I/Omax
where:
Equation 4
P
= Σ (V * I ) + Σ((V - V ) * I
)
OH
I/Omax
OL
OL
DD
OH
taking into account the actual V / I and V / I of the I/Os at low- and high-level in the
OL OL
OH OH
application.
(1)
Table 51. Thermal characteristics
Symbol
Parameter
Value
Unit
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
Θ
38
°C/W
JA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
Θ
46
57
59
25
°C/W
°C/W
°C/W
°C/W
JA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
Θ
JA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
Θ
JA
Thermal resistance junction-ambient
VFQFPN 32 - 5 x 5 mm
Θ
JA
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
Doc ID 14395 Rev 9
87/110
Electrical characteristics
STM8AF52/62xx, STM8AF51/61xx
10.4.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 52: Ordering information scheme(1) on page 98).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
–
–
–
–
–
Maximum ambient temperature T
= 82 °C (measured according to JESD51-2)
Amax
I
= 8 mA
DDmax
V
= 5 V
DD
maximum 20 I/Os used at the same time in output at low-level with I = 8 mA
OL
V
= 0.4 V
OL
Equation 5
P
= 8 mA x 5 V = 400 mW
INTmax
Equation 6
P
= 20 x 8 mA x 0.4 V = 64 mW
64 mW:
IOmax
This gives:
P
= 400 mW and P
INTmax
IOmax
Equation 7
P
= 400 mW + 64 mW
Dmax
Thus:
P
= 464 mW.
Dmax
Using the values obtained in Table 51: Thermal characteristics on page 87 T
is
Jmax
calculated as follows:
For LQFP64 46 °C/W
Equation 8
T
= 82 °C + (46 °C/W x 464 mW) = 82 °C + 21 °C = 103 ° C
jmax
This is within the range of the suffix B version parts (-40 °C < T < 105 ° C).
j
Parts must be ordered at least with the temperature range suffix B.
88/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
11
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 14395 Rev 9
89/110
Package characteristics
STM8AF52/62xx, STM8AF51/61xx
11.1
Package mechanical data
Figure 44. LQFP 80-pin low profile quad flat package (14 x 14)
D
ccc
C
D1
D3
A
A2
41
60
40
61
b
L1
E3 E1
E
L
A1
K
80
Pin 1
identification
1
c
1S_ME
Table 52. LQFP 80-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.220
0.090
15.800
13.800
—
—
—
1.600
0.150
1.450
0.380
0.200
16.200
14.200
—
—
0.0020
0.0531
0.0087
0.0035
0.6220
0.5433
—
—
0.0630
0.0059
0.0571
0.0150
0.0079
0.6378
0.5591
—
—
1.400
0.320
—
0.0551
0.0126
—
c
D
16.000
14.000
12.350
16.000
14.000
12.350
0.650
0.600
1.000
—
0.6299
0.5512
0.4862
0.6299
0.5512
0.4862
0.0256
0.0236
0.0394
—
D1
D3
E
15.800
13.800
—
16.200
14.200
—
0.6220
0.5433
—
0.6378
0.5591
—
E1
E3
e
—
—
—
—
L
0.450
—
0.750
—
0.0177
—
0.0295
—
L1
ccc
k
—
0.100
7°
—
0.0039
7°
0°
3.5°
0°
3.5°
1. Values in inches are converted from mm and rounded to 4 decimal digits
90/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 45. LQFP 64-pin low profile quad flat package (10 x 10)
D
ccc
C
D1
D3
A
A2
33
48
32
49
b
L1
E3
E1 E
L
A1
K
64
17
Pin 1
identification
1
16
c
5W_ME
Table 53. LQFP 64-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.170
0.090
11.800
9.800
—
—
—
1.600
0.150
1.450
0.270
0.200
12.200
10.200
—
—
0.0020
0.0531
0.0067
0.0035
0.4646
0.3858
—
—
0.0630
0.0059
0.0571
0.0106
0.0079
0.4803
0.4016
—
—
1.400
0.220
—
0.0551
0.0087
—
c
D
12.000
10.000
7.500
12.000
10.000
7.500
0.500
3.5°
0.4724
0.3937
0.2953
0.4724
0.3937
0.2953
0.0197
3.5°
D1
D3
E
11.800
9.800
—
12.200
10.200
—
0.4646
0.3858
—
0.4803
0.4016
—
E1
E3
e
—
—
—
—
θ
0°
7°
0°
7°
L
0.450
—
0.600
1.000
—
0.750
—
0.0177
—
0.0236
0.0394
—
0.0295
—
L1
ccc
—
0.080
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
91/110
Package characteristics
Figure 46. LQFP 64-pin recommended footprint
STM8AF52/62xx, STM8AF51/61xx
ꢁꢈ
ꢂꢂ
ꢅꢌꢂ
ꢁꢊ
ꢂꢉ
ꢅꢌꢍ
ꢀꢉꢌꢋ
ꢀꢅꢌꢂ
ꢀꢅꢌꢂ
ꢃꢁ
ꢀꢋ
ꢀꢌꢉ
ꢀ
ꢀꢃ
ꢋꢌꢈ
ꢀꢉꢌꢋ
ꢍ7?&0
1. Drawing is not to scale. Dimensions are in millimeters.
92/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 47. LQFP 48-pin low profile quad flat package (7 x 7)
D
ccc
C
D1
D3
A
A2
25
36
24
37
L1
b
E3
E1 E
48
L
13
A1
K
Pin 1
identification
1
12
c
5B_ME
Table 54. LQFP 48-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.170
0.090
8.800
6.800
—
—
1.600
0.150
1.450
0.270
0.200
9.200
7.200
—
—
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
—
—
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
—
—
—
1.400
0.220
—
0.0551
0.0087
—
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
3.5°
D1
D3
E
8.800
6.800
—
9.200
7.200
—
0.3465
0.2677
—
0.3622
0.2835
—
E1
E3
e
—
—
—
—
θ
0°
7°
0°
7°
L
0.450
—
0.600
1.000
—
0.750
—
0.0177
—
0.0236
0.0394
—
0.0295
—
L1
ccc
—
0.080
—
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
93/110
Package characteristics
Figure 48. LQFP 48-pin recommended footprint
STM8AF52/62xx, STM8AF51/61xx
ꢅꢌꢍꢅ
ꢀꢌꢉꢅ
ꢅꢌꢂꢅ
ꢉꢍ
ꢂꢃ
ꢂꢋ
ꢉꢁ
ꢅꢌꢉꢅ
ꢋꢌꢂꢅ
ꢊꢌꢋꢅ ꢍꢌꢈꢅ
ꢋꢌꢂꢅ
ꢁꢈ
ꢀꢂ
ꢀꢉ
ꢀ
ꢀꢌꢉꢅ
ꢍꢌꢈꢅ
ꢊꢌꢋꢅ
ꢍ"?&0
1. Drawing is not to scale. Dimensions are in millimeters.
94/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Figure 49. LQFP 32-pin low profile quad flat package (7 x 7)
Package characteristics
ccc
C
D
D1
D3
A
A2
24
17
16
25
32
L1
b
E3
E1 E
9
L
Pin 1
identification
A1
K
1
8
c
5V_ME
Table 55. LQFP 32-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A2
b
—
0.050
1.350
0.300
0.090
8.800
6.800
—
—
1.600
0.150
1.450
0.450
0.200
9.200
7.200
—
—
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
—
—
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
—
—
—
1.400
0.370
—
0.0551
0.0146
—
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
3.5°
D1
D3
E
8.800
6.800
—
9.200
7.200
—
0.3465
0.2677
—
0.3622
0.2835
—
E1
E3
e
—
—
—
—
θ
0°
7°
0°
7°
L
0.450
—
0.600
1.000
—
0.750
—
0.0177
—
0.0236
0.0394
—
0.0295
—
L1
ccc
—
0.100
—
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 14395 Rev 9
95/110
Package characteristics
Figure 50. LQFP 32-pin recommended footprint
STM8AF52/62xx, STM8AF51/61xx
ꢊꢌꢁꢅ
ꢋꢌꢋꢅ
ꢅꢌꢍꢁ
ꢊꢌꢁꢅ
ꢅꢌꢈꢅ
ꢍ6?&0
1. Drawing is not to scale. Dimensions are in millimeters.
96/110
Doc ID 14395 Rev 9
STM8AF52/62xx, STM8AF51/61xx
Package characteristics
Figure 51. VFQFPN 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
b
E
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
42_ME
Table 56. VFQFPN 32-lead very thin fine pitch quad flat no-lead package
mechanical data
mm
Typ
inches(1)
Dim.
Min
Max
Min
Typ
Max
A
A1
A3
b
0.800
0.000
—
0.900
0.020
0.200
0.250
5.000
3.450
5.000
3.450
0.500
0.400
—
1.000
0.050
—
0.0315
0.000
—
0.0354
0.0008
0.0079
0.0098
0.1969
0.1358
0.1969
0.1358
0.0197
0.0157
—
0.0394
0.0020
—
0.180
4.850
3.400
4.850
3.400
—
0.300
5.150
3.500
5.150
3.500
—
0.0071
0.1909
0.1339
0.1909
0.1339
—
0.0118
0.2028
0.1378
0.2028
0.1378
—
D
D2
E
E2
e
L
0.300
—
0.500
0.080
0.0118
—
0.0197
0.0031
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Ordering information
STM8AF52/62xx, STM8AF51/61xx
12
Ordering information
(1)
Figure 52. Ordering information scheme
XXX(2)
Y
Example:
STM8A
F
62
A
A
T
D
Product class
8-bit automotive microcontroller
Program memory type
F = Flash + EEPROM
P = FASTROM
H = Flash no EEPROM(3)
Device family
51 = Silicon rev X, CAN/LIN(3)
61 = Silicon rev X, LIN only(3
52 = Silicon rev U and rev T, CAN/LIN
62 = Silicon rev U and rev T, LIN only
Program memory size
6 = 32 Kbytes
7 = 48 Kbytes(3)
8 = 64 Kbytes
9 = 96 Kbytes(3)
A= 128 Kbytes
Pin count
6 = 32 pins
8 = 48 pins
9= 64 pins
A = 80 pins
Package type
T = LQFP
U = VFQFPN
Temperature range
A = -40 to 85 °C
B = -40 to 105 °C(3)
C = -40 to 125 °C
D = -40 to 150 °C(4)
Packing
Y = Tray
U = Tube
X = Tape and reel compliant with EIA 481-C
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest
to you.
2. Customer specific FASTROM code or custom device configuration. This field shows ‘SSS’ if the device
contains a super set silicon, usually equipped with bigger memory and more I/Os. This silicon is supposed
to be replaced later by the target silicon.
3. Not recommended for new design.
4. Available on STM8AFx2xx devices.
98/110
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STM8 development tools
13
STM8 development tools
Development tools for the STM8A microcontrollers include the
●
STice emulation system offering tracing and code profiling
●
STVD high-level language debugger including assembler and visual development
environment - seamless integration of third party C compilers
●
STVP Flash programming software
In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
13.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the STice emulation system offering a complete range of
emulation and in-circuit debugging features on a platform that is designed for versatility and
cost-effectiveness. In addition, STM8A application development is supported by a low-cost
in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including tracing, profiling and code coverage
analysis to help detect execution bottlenecks and dead code.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
13.1.1
STice key features
●
●
●
●
●
●
●
●
●
●
●
Program and data trace recording up to 128 K records
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Real-time read/write of all device resources during emulation
Occurrence and time profiling and code coverage analysis (new features)
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
USB 2.0 high-speed interface to host PC
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8 development tools
STM8AF52/62xx, STM8AF51/61xx
13.2
Software tools
STM8 development tools are supported by a complete, free software package from STMi-
croelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer
(STVP) software interface. STVD provides seamless integration of the Cosmic and Raiso-
nance C compilers for STM8.
13.2.1
STM8 toolset
The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
●
●
●
●
●
●
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)
Easy-to-use, unlimited graphical interface allowing read, write and verification of the STM8A
microcontroller’s Flash memory. STVP also offers project mode for saving programming
configurations and automating programming sequences.
13.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface. Available toolchains include:
C compiler for STM8
All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.
STM8 assembler linker
Free assembly toolchain included in the STM8 toolset, which allows you to assemble and
link your application source code.
100/110
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STM8 development tools
13.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8A Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8A.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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Revision history
STM8AF52/62xx, STM8AF51/61xx
14
Revision history
Table 57. Document revision history
Date
Revision
Changes
31-Jan-2008
Rev 1
Initial release
Added ‘H’ products to the datasheet (Flash no EEPROM).
Features on page 1: Updated Memories, Reset and supply
management, Communication interfaces and I/Os; reduced wakeup
pins by 1.
Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166,
STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and
STM8AF5166.
Section 1, Section 5, Section 6.2, Table 21, and Section 9: Updated
reference documentation: RM0009, PM0047, and UM0470.
Section 2: Added information about peak performance.
Section 3: Removed STM8A common features table.
Table 4: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T,
and STM8AF5166T.
Table 5: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T,
and STM8AF6146T.
Section 5: Made minor content changes and improved readability
and layout.
Section 5.5.3: Major modification, TMU included.
Section 5.5.2: User trimming updated.
Section 5.5.3: LSI as CPU clock added.
Section 5.5.4 , Section 5.5.5: Maximum frequency conditional 32
Kbyte/128 Kbyte.
Section 5.8: Scan for 128 Kbyte removed.
22-Aug-2008
Rev 2
Section 5.9, Section 5.9.3: SPI 10 Mb/s.
Figure 3, Figure 4, and Figure 5: Amended footnote 1.
Table 12: HS output changed from 20 mA to 8 mA.
Section 7: Corrected Figure 7: Register and memory map; removed
address list; added Table 14.
Section 10.3.2 Note on typical/WC values added.
Table 18: Replaced the source blocks ‘simple USART’, ‘very low-end
timer (timer 4)’, and ‘EEPROM’ with ‘LINUART’, ‘timer4’ and
‘reserved’ respectively, added TMU registers.
Table 20: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL)
Table 21: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4
PRSC [1:0], and OPT6, added OPT7 to 16 (TMU).
Table 23: Amended footnotes.
Table 26: Added parameter ‘voltage and current operating
conditions’.
Table 27: Amended footnotes.
Table 28: Replaced.
Table 29: Amended maximum data and footnotes.
Table 21: Replaced.
Table 22: Added and amended IDD(RUN) data; amended IDD(WFI)
data; amended footnotes.
Table 32: Filled in, amended maximum data and footnotes.
Figure 12 to Figure 17: info on peripheral activity added.
Table 33: Modified fHSE_ext data and added VHSEdhl data.
102/110
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Table 57. Document revision history (continued)
Revision history
Date
Revision
Changes
Table 35: Removed ACCHSI parameters and replaced with ACCHS
parameters; amended data and footnotes.
Amended data of ‘RAM and hardware registers’ table.
Table 37: Updated names and data of NRW and tRET parameters.
Table 40: Added VOH and VOL parameters; Updated Ilkg ana
parameter.
Removed: Output driving current (standard ports), Output driving
current (true open drain ports), and Output driving current (high sink
ports).
Table 45: Updated fADC, tS, and tCONV data.
ADC accuracy for VDDA = 3.3 V table: Removed the 4-MHz condition
from all parameters.
Rev 2
cont’d
22-Aug-2008
Table 46: Removed the 4-MHz condition from all parameters;
updated footnote 1 and removed footnote 2.
Table 50: Added data for TA = 145 °C.
Figure 52: Updated memory size, pin count and package type
information.
Replaced the salestype ‘STM8H61xx’ with ‘STM8AH61xx on the first
page.
Added ‘part numbers’ to heading rows of Table 1: Device summary.
Updated the 80-pin package silhouette on page 1 in line with POA
0062342-revD.
Table 18: Renamed ‘TMU key registers 0-7 [7:0]’ as ‘TMU key
registers 1-8 [7:0]’
Section 9: Updated introductory text concerning option bytes which
do not need to be saved in a complementary form.
Table 18: Renamed the option bits ‘TMU[0:3]’, ‘NTMU[0:3]’, and
‘TMU_KEY 0-7 [7:0]’ as ‘TMU[3:0]’, ‘NTMU[3:0]’, and ‘TMU_KEY 1-8
[7:0]’ respectively.
16-Sep-2008
Rev 3
Table 21: Updated values of option byte 5 (HSECNT[7:0]); inverted
the description of option byte 6 (TMU[3:0]); renamed option bytes 8
to 15 ‘TMU_KEY 0-7 [7:0]’, as ‘TMU_KEY 1-8 [7:0]’.
Updated 80-pin package information in line with POA 0062342-revD
in Figure 44 and Table 52.
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Revision history
Table 57. Document revision history (continued)
STM8AF52/62xx, STM8AF51/61xx
Date
Revision
Changes
Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header.
Updated Features on page 1 (memories, timers, operating
temperature, ADC and I/Os).
Updated Table 1: Device summary.
Updated Kbytes value of program memory in Chapter 1: Introduction
Chapter 2: Description
– Changed the first two lines from the top.
Updated Figure 1: STM8A block diagram
Updated Chapter 5: Product overview
In Figure 5: LQFP 48-pin pinout, added USART function to pins 10,
11, and 12; added CAN Tx and CAN Rx functions to pins 35 and 36
respectively.
Section 6.2: Pin description
– Deleted text below the Table 12: Legend/abbreviation for the pin
description table
Table 13: STM8A microcontroller family pin description
– 68th, 69th pin (LQFP80): replaced X with a dash for PP output
– Added a table footnote
Updated Figure 7: Register and memory map
Table 14: Memory model 128K
– Updated footnote
Deleted the table “Stack and RAM partitioning“
Table 19: STM8A interrupt table.
01-Jul-2009
Rev 4
– Updated priorities 13, 15, 17, 20 and 24
– Changed table footnote
Updated Chapter 7.2: Register map
Updated Table 39: Data memory, Table 40: I/O static characteristics,
and Table 41: NRST pin characteristics.
Section 10.1.1: Minimum and maximum values.
– Added ambient temperature TA = -40 °C
Updated Table 22: Voltage characteristics
Updated Table 23: Current characteristics
Updated Table 24: Thermal characteristics
UpdatedTable 26: General operating conditions
UpdatedTable 27: Operating conditions at power-up/power-down.
Figure 10: fCPUmax versus VDD.
– Updated temperature ranges in functional area
– Added a figure footnote
Removed ‘total current consumption’ and ‘note on the run-current
typical values’.
Replaced Table 28: Total current consumption in Run, Wait and Slow
mode. General conditions for VDD apply, TA = -40 °C to 150 °C
Replaced Table 29: Total current consumption in Halt and Active-halt
modes. General conditions for VDD applied. TA = -40 °C to 55 °C
unless otherwise stated.
Removed Table 21: Total current consumption in run, wait and slow
mode. General conditions for VDD apply. TA = -40 °C to 145 °C
104/110
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Table 57. Document revision history (continued)
Revision history
Date
Revision
Changes
Removed Table 22: Total current consumption and timing in halt, fast
active halt and slow active halt modes at VDD = 3.3 V.
Added Table 30: Oscillator current consumption
Added Table 31: Programming current consumption.
Updated Table 32: Typical peripheral current consumption VDD = 5.0
V
Changed Section : HSE external clock title from “HSE user external
clock“
Updated Table 33: HSE external clock characteristics
Updated Table 34: HSE oscillator characteristics.
Figure 19: HSE oscillator circuit diagram.
– Changed ‘consumption control’ to ‘current control’
HSE oscillator critical gm formula.
– Clarified formula
Updated Table 35: HSI oscillator characteristics.
Removed ‘RAM and hardware registers’
Removed Table 29: RAM and hardware registers.
Updated Table 37: Flash program memory/data EEPROM memory.
Added Table 38: Flash program memory
Added Table 39: Data memory.
Updated Table 40: I/O static characteristics
Updated Table 41: NRST pin characteristics
Updated Table 42: TIM 1, 2, 3, and 4 electrical specifications
Section 10.3.9: SPI interface
01-Jul-2009
Rev 4
Changed title from “SPI serial peripheral interface“
Updated Table 43: SPI characteristics.
Figure 39: SPI timing diagram in slave mode and with CPHA = 0
– Changed title
– Added footnote 1.
Figure 40: SPI timing diagram in slave mode and with CPHA = 1
– Changed title
Updated Table 45: ADC characteristics.
Updated Figure 42: Typical application with ADC and added legend.
Removed Table 36: ADC accuracy for VDDA = 3.3 V
Updated Table 46: ADC accuracy for VDDA = 5 V
Updated Table 48: EMI data
Updated Table 50: Electrical sensitivities
Added Section : In order to meet environmental requirements, ST
offers these devices in different grades of ECOPACK® packages,
depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at:
www.st.com. ECOPACK® is an ST trademark..
Figure 45: LQFP 64-pin low profile quad flat package (10 x 10)
– Deleted footnote
Updated Figure 52: Ordering information scheme(1).
Added Chapter 13: STM8 development tools.
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Revision history
Table 57. Document revision history (continued)
STM8AF52/62xx, STM8AF51/61xx
Changes
Date
Revision
Updated Table 1: Device summary:
22-Oct-2009
Rev 5
– Added STM8AF5178, STM8AF519A and STM8AF619A.
Updated title on cover page.
Modified cover page header to clarify the part numbers covered by
the datasheets. Updated Note 1 below Table 1: Device summary to
add ‘P’ order codes.
Changed definition of ‘P’ order codes.
‘Q’ order codes (FASTROM and EEPROM) removed.
Content of Section 5: Product overview reorganized. Table 13:
STM8A microcontroller family pin description: updated PD7/TLI
alternate function, removed caution note for PD6/ LINUART_RX, and
added Note 1 to PA1/OSCIN.
Renamed Section 7 Memory and register map, and content merged
with section 9. Register map. Updated Figure 7: Register and
memory map.
13-Apr-2010
Rev 6
Renamed BL_EN and NBL_EN, BL and NBL, respectively, in
Table 20: Option bytes.
Updated AFR4 definition in Table 21: Option byte description.Added
CEXT in Table 26: General operating conditions, and Section 10.3.1:
VCAP external capacitor.
Update tVDD in Table 27: Operating conditions at power-up/power-
down.
Moved Table 32: Typical peripheral current consumption VDD = 5.0 V
to Section : Current consumption for on-chip peripherals.
Removed VESD(MM) from Table 49: ESD absolute maximum ratings.
Updated Section 12: Ordering information to the devices supported
by the datasheet.
Updated Section 13: STM8 development tools.
Added STM8AF5168 and STM8AF518A part number in Figure 4,
and STM8AF618A in Figure 5. Added STM8AF52xx, STM8AF6269,
STM8AF628x, and STM8AF62Ax.
Updated D temperature range to -40 to 150°C.
Updated number of I/Os on cover page.
Added Table 25: Operating lifetime.
Restored VESD(MM) from Table 49: ESD absolute maximum ratings.
Table 26: General operating conditions: updated VCAP information.
ESL parameter, and range D maximum junction temperature (TJ).
08-Jul-2010
Rev 7
Added STM8AF52xx and STM8AF62xx, and Note 3 in Section 12:
Ordering information.
Updated Section 13: STM8 development tools: added Table 54:
Product evolution summary, and split the beCAN time triggered
communication mode limitation into Section 13.7.3 and
Section 13.7.4.
106/110
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Table 57. Document revision history (continued)
Revision history
Date
Revision
Changes
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of high density Flash program memory.
Updated number of I/Os for devices in 80-, 64-, and 48-pin packages
in Table 2: STM8AF52xx product line-up with CAN, Table 3:
STM8AF62xx product line-up without CAN, Table 4:
STM8AF/H/P51xx product line-up with CAN, and Table 5:
STM8AF/H/P61xx product line-up without CAN.
Added TMU brief description in Section 5.4: Flash program and data
EEPROM, updated TMU_MAXATT description in Table 21: Option
byte description, and TMU_MAWATT reset value in Table 20: Option
bytes.
Updated clock sources in clock controller features (Section 5.5.1).
Added Table 7: Peripheral clock gating bits (CLK_PCKENR2) in
Section 5.5.6.
3&-Jan-2011
Rev 8
Added calibration using TIM3 in Section 5.7.2: Auto-wakeup counter.
Added Table 10: ADC naming and Table 11: Communication
peripheral naming correspondence.
Updated SPI data rate to fMASTER/2 in Section 5.9.3: Serial
peripheral interface (SPI).
Added reset state in Table 12: Legend/abbreviation for the pin
description table.
Table 13: STM8A microcontroller family pin description: modified
Note 2, added Note 3 related to PD1/SWIM, corrected wpu input for
PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to
TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register map: Removed CAN register CLK_CANCCR.
Removed I2C_PECR register.
Added Note 1 for Px_IDR registers in Table 15: I/O port hardware
register map. Updated register reset values for Px_IDR and PD_CR1
registers.
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, TMU, clock
controller, interrupt controller, timers, communication interfaces, and
ADC, by Table 16: General hardware register map. Added debug
module register map.
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Revision history
Table 57. Document revision history (continued)
STM8AF52/62xx, STM8AF51/61xx
Changes
Date
Revision
Renamed Fast Active Halt mode to Active-halt mode with regulator
on, and Slow Active Halt mode to Active-halt mode with regulator off,
updated Section 5.6: Low-power operating modes, and Table 29:
Total current consumption in Halt and Active-halt modes. General
conditions for VDD applied. TA = -40 °C to 55 °C unless otherwise
stated. IDD(FAH) and IDD(SAH) renamed IDD(AH); WU(FAH)
t
and tWU(SAH)
renamed tWU(AH)
.
Removed note 1 in Table 26: General operating conditions, and note
1 below Figure 10: fCPUmax versus VDD.
Removed note 3 in Table 28: Total current consumption in Run, Wait
and Slow mode. General conditions for VDD apply, TA = -40 °C to
150 °C.
Removed note 2 in Table 33: HSE external clock characteristics and
Table 37: Flash program memory/data EEPROM memory.
Removed note 1 in Table 39: Data memory. Modified TWE maximum
value in Table 38: Flash program memory and Table 39: Data
memory.
Rev 8
(continued)
3&-Jan-2011
Added tIFP(NRST) and renamed VF(NRST) IFP
t
in Table 41: NRST pin
characteristics.
Added recommendation concerning NRST pin level, and power
consumption sensitive applications, above Figure 38:
Recommended reset pin protection, and updated external capacitor
value.
Update Note 1 in Table 42: TIM 1, 2, 3, and 4 electrical
specifications.
Updated Note 1 in Table 43: SPI characteristics.
Moved know limitations to separate errata sheet.
Added “not recommended for new design” note to device family 51,
memory size 7 and 9, and temperature range B, in Figure 52:
Ordering information scheme(1).
Added Raisonance compiler in Section 13.2: Software tools.
Updated wildcards of document part numbers.
Added VFQFPN package.
Added STM8AF62A6 part number.
Table 1: Device summary: updated footnote 1 and added footnote 2.
Table 2: STM8AF52xx product line-up with CAN and Table 3:
STM8AF62xx product line-up without CAN: added “P” version for all
order codes; updated size of data EEPROM for 64K devices to 2K
instead of 1.5K; updated RAM.
Figure 1: STM8A block diagram: updated POR, BOR and WDG;
removed PDR; added legend.
18-Jul-2012
Rev 9
Section 5.4: Flash program and data EEPROM: removed
nonrelevant bullet points and added a sentence about the factory
programme.
Added Table 6: Peripheral clock gating bits (CLK_PCKENR1) and
updated Table 7: Peripheral clock gating bits (CLK_PCKENR2).
ADC features: updated ADC input range.
Table 14: Memory model 128K: updated RAM size, RAM end
addresses, and stack roll-over addresses; updated footnote 1.
108/110
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Table 57. Document revision history (continued)
Revision history
Date
Revision
Changes
Table 20: Option bytes: updated factory default setting for NOPT17;
updated footnote 1.
Table 22: Voltage characteristics: updated VDDX - VDD to VDDX - VSS
.
Table 26: General operating conditions: updated VCAP
.
Table 28: Total current consumption in Run, Wait and Slow mode.
General conditions for VDD apply, TA = -40 °C to 150 °C: updated
conditions for IDD(RUN)
.
Table 40: I/O static characteristics: added new condition and new
max values for rise and fall time; updated footnote 2.
Section 10.3.7: Reset pin characteristics: updated text below
Figure 37: Typical NRST pull-up current Ipu vs VDD.
Figure 38: Recommended reset pin protection: updated unit of
capacitor.
Table 43: SPI characteristics: updated SCK high and low time
conditions and values.
Figure 41: SPI timing diagram - master mode: replaced ‘SCK input’
signals with ‘SCK output’ signals.
Rev 9
(continued)
18-Jul-2012
Updated Table 52: LQFP 80-pin low profile quad flat package
mechanical data, Table 53: LQFP 64-pin low profile quad flat
package mechanical data, Table 54: LQFP 48-pin low profile quad
flat package mechanical data, Table 55: LQFP 32-pin low profile
quad flat package mechanical data, and Table 56: VFQFPN 32-lead
very thin fine pitch quad flat no-lead package mechanical data.
Replaced Figure 45: LQFP 64-pin low profile quad flat package (10 x
10), Figure 47: LQFP 48-pin low profile quad flat package (7 x 7),
and Figure 49: LQFP 32-pin low profile quad flat package (7 x 7).
Added Figure 46: LQFP 64-pin recommended footprint, Figure 48:
LQFP 48-pin recommended footprint, and Figure 50: LQFP 32-pin
recommended footprint.
Updated Figure 51: VFQFPN 32-lead very thin fine pitch quad flat
no-lead package (5 x 5).
Updated Figure 52: Ordering information scheme(1).
Section 13.2.2: C and assembly toolchains: added www.iar.com.
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STM8AF52/62xx, STM8AF51/61xx
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Doc ID 14395 Rev 9
相关型号：
STM8AF5199
Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROMWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TAXXXX
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TAXXXY
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TBU
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TBX
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TBXXXX
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TBXXXY
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TBY
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TCR
MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TCU
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TCXXXU
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
STM8AF5199TCXXXY
8-BIT, FLASH, 24MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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STMICROELECTR
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