STM8AF6223 [STMICROELECTRONICS]
Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, IC, 3 to 5.5 V;
| 型号： | STM8AF6223 |
| 厂家： | 
ST |
| 描述： | Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, IC, 3 to 5.5 V 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总106页 (文件大小：1934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STM8AF6213 STM8AF6223
STM8AF6223A STM8AF6226
Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM,
10-bit ADC, timers, LIN, SPI, I²C, 3 to 5.5 V
Datasheet - production data
Features
Core
– Max f
: 16 MHz
CPU
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
LQFP32 7x7 mm
TSSOP20 (6.4x4.4 mm)
I/Os
Memories
– Up to 28 I/Os on a 32-pin package
including 21 high sink outputs
– Highly robust I/O design, immune against
current injection
– Program memory: 4 to 8 Kbyte Flash
program; data retention 20 years at 55 °C
after 1 kcycle
– Data memory: 640 byte true data
EEPROM; endurance 300 kcycle
– RAM: 1 Kbyte
Communication interfaces
– LINUART LIN 2.2 compliant, master/slave
modes with automatic resynchronization
Clock management
– SPI interface up to 8 Mbit/s or f
/2
MASTER
– Low-power crystal resonator oscillator with
2
– I C interface up to 400 Kbit/s
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
Analog to digital converter (ADC)
– 10-bit, ± 1 LSB ADC with up to 7 muxed
channels + 1 internal channel, scan mode
and analog watchdog
Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Low-consumption power-on and power-
down reset
– Internal reference voltage measurement
Operating temperature up to 150 °C
Qualification conforms to AEC-Q100 rev G
Interrupt management
– Nested interrupt controller with 32
interrupts
– Up to 28 external interrupts on 7 vectors
Timers
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 16-bit general purpose timer with 3
CAPCOM channels each (IC, OC, PWM)
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers
June 2015
DocID025118 Rev 5
1/106
This is information on a product in full production.
www.st.com
Contents
STM8AF6213/23/23A/26
Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1
4.1.2
4.1.3
Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
4.2.1
4.2.2
SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3
4.4
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.1
4.4.2
Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6
4.7
4.8
4.9
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 TIM5 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12 TIM6 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.1 LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14.2 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
4.14.3 Inter integrated circuit (I C) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Contents
5
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
5.3
TSSOP20 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LQFP32 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
6.2
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1
6.2.2
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 43
7
8
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.1
8.2
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM8AF6213/23/23A/26 alternate function remapping bits . . . . . . . . . . . 49
9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2
9.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2
I C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DocID025118 Rev 5
3/106
4
Contents
STM8AF6213/23/23A/26
9.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.2 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.3.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 98
11
12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 101
12.1.1 STice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
STM8AF6213/23/23A/26 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Legend/abbreviations for pinout tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8AF6213/STM8AF6223 TSSOP20 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM8AF6223A TSSOP20 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8AF6226 LQFP32 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory model for the devices covered in this datasheet. . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM8AF6226 alternate function remapping bits [7:2] for 32-pin packages . . . . . . . . . . . . 49
STM8AF6213 and STM8AF6223 alternate function remapping bits [7:2]
for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM8AF6223A alternate function remapping bits [7:2] for 20-pin packages . . . . . . . . . . . 50
STM8AF6226 alternate function remapping bits [1:0] for 32-pin packages . . . . . . . . . . . . 51
STM8AF6213/STM8AF6223 alternate function remapping bits [1:0]
Table 18.
Table 19.
Table 20.
for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM8AF6223A alternate function remapping bits [1:0] for 20-pin packages . . . . . . . . . . . 52
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Operating lifetime (OLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Total current consumption with code execution in run mode at V = 5 V. . . . . . . . . . . . . 58
DD
Total current consumption with code execution in run mode at V = 3.3 V . . . . . . . . . . . 59
DD
Total current consumption in wait mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in wait mode at V = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DD
Total current consumption in active halt mode at V = 5 V . . . . . . . . . . . . . . . . . . . . . . . 61
DD
Total current consumption in active halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61
DD
Total current consumption in halt mode at V = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
Total current consumption in halt mode at V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DD
Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DocID025118 Rev 5
5/106
6
List of tables
STM8AF6213/23/23A/26
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2
I C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC accuracy with RAIN < 10 kΩ, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DD
ADC accuracy with RAIN < 10 kΩ, V = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DD
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 62.
TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 63.
Table 64.
6/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
STM8AF6213/23/23A/26 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STM8AF6213/STM8AF6223 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8AF6223A TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM8AF6226 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
f
versus V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CPUmax
DD
Figure 10. External capacitor C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
EXT
Figure 11. Typ I
Figure 12. Typ I
Figure 13. Typ I
Figure 14. Typ I
Figure 15. Typ I
Figure 16. Typ I
vs. V HSE user external clock, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . 64
DD(RUN)
DD(RUN)
DD(RUN)
DD(WFI)
DD(WFI)
DD(WFI)
DD
CPU
vs. f
HSE user external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 64
CPU
DD
vs. V HSEI RC osc., f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CPU
DD
vs. V HSE user external clock, f
= 16 MHz . . . . . . . . . . . . . . . . . . . . . 65
DD
CPU
vs. f
HSE user external clock, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 66
CPU
DD
vs. V HSI RC osc., f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CPU
DD
Figure 17. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 18. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 19. Typical V and V vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
IL
IH
DD
Figure 20. Typical pull-up resistance R vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 73
PU
DD
Figure 21. Typical pull-up current I vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
pu
DD
Figure 22. Typ. V @ V = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
OL
DD
Figure 23. Typ. V @ V = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
OL
DD
Figure 24. Typ. V @ V = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 25. Typ. V @ V = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 26. Typ. V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
OL
DD
Figure 27. Typ. V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
OL
DD
Figure 28. Typ. V - V @ V = 5 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 29. Typ. V - V @ V = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DD
OH
DD
Figure 30. Typ. V - V @ V = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DD
OH
DD
Figure 31. Typ. V - V @ V = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DD
OH
DD
Figure 32. Typical NRST V and V vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IL
IH
DD
Figure 33. Typical NRST pull-up resistance vs V @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 80
DD
Figure 34. Typical NRST pull-up current vs V @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 80
DD
Figure 35. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 36. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 37. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
(1)
Figure 38. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 39. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 41. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 42. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 92
Figure 43. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 44. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 45. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 46. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
DocID025118 Rev 5
7/106
8
List of figures
STM8AF6213/23/23A/26
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 47. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
(1) (2)
Figure 48. STM8AF6213/23/23A/26 ordering information scheme
. . . . . . . . . . . . . . . . . . . . . . 100
8/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Introduction
1
Introduction
The datasheet contains the description of STM8AF6213, STM8AF6223, STM8AF6223A
and STM8AF6226 features, pinout, electrical characteristics, mechanical data and ordering
information.
For complete information on the STM8A microcontroller memory, registers and
peripherals, please refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016).
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8 Flash programming manual (PM0051).
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
DocID025118 Rev 5
9/106
103
Description
STM8AF6213/23/23A/26
2
Description
The STM8AF6213, STM8AF6223, STM8AF6223A and STM8AF6226 automotive 8-bit
microcontrollers offer 4 to 8 Kbyte of Flash program memory, plus integrated true data
EEPROM. The STM8S series and STM8AF series 8-bit microcontrollers reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
performance, robustness and reduced system cost.
Device performance and robustness are ensured by advanced core and peripherals made
in a state-of-the-art technology, a 16 MHz clock frequency, robust I/Os, independent
watchdogs with separate clock source, and a clock security system.
The system cost is reduced thanks to an integrated true data EEPROM for up to
300 kwrite/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
²
Table 1. STM8AF6213/23/23A/26 features
Device
STM8AF6226
STM8AF6223 STM8AF6223A STM8AF6213
Pin count
32
20
28 including 21
high-sink I/Os
Max. number of GPIOs
16 including 12 high-sink I/Os
16
Ext. interrupt pins
28
6
Timer CAPCOM channels
7
1
6
2
7
7
1
Timer complementary
outputs
3
7
A/D converter channels
5
5
Low-density Flash program
memory (byte)
8 K
4 K
Data EEPROM (byte)
RAM (byte)
640(1)
1 K
Multipurpose timer (TIM1), SPI, I2C, LINUART, window WDG,
independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6)
Peripheral set
1. No read-while-write (RWW) capability
10/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Block diagram
3
Block diagram
Figure 1. STM8AF6213/23/23A/26 block diagram
5HVHWꢀEORFN
5HVHW
;7$/ꢀꢁꢂꢀꢁꢃꢀ0+]
5&ꢀLQWꢄꢀꢁꢃꢀ0+]
5&ꢀLQWꢄꢀꢁꢅꢆꢀN+]
&ORFNꢀFRQWUROOHU
'HWHFWRU
5HVHW
325
%25
&ORFNꢀWRꢀSHULSKHUDOVꢀDQGꢀFRUH
:LQGRZꢀ:'*
670ꢆꢀFRUH
,QGHSHQGHQWꢀ:'*
6LQJOHꢀZLUH
'HEXJꢇ6:,0
8SꢀWRꢀꢆꢀ.E\WH
SURJUDPꢀ)ODVK
GHEXJꢀLQWHUIDFH
ꢃꢊꢋꢀE\WH
GDWDꢀ((3520
ꢁꢀ.E\WHꢀ5$0
ꢊꢋꢋꢀ.ELWꢇV
ꢆꢀ0ELWꢇV
,ꢅ&
63,
8SꢀWRꢀ
ꢊꢀ&$3&20
FKDQQHOVꢀꢏꢀ
ꢍꢀFRPSOHPHQWDU\ꢀ
RXWSXWV
ꢁꢃꢂELWꢀDGYDQFHGꢀFRQWURO
WLPHUꢀꢈ7,0ꢁꢉ
/,1
63,ꢀHPXOꢄ
/,18$57
8SꢀWR
ꢍꢀ&$3&20
FKDQQHOV
ꢁꢃꢂELWꢀJHQHUDOꢀSXUSRVH
WLPHUVꢀꢈ7,0ꢌꢉ
8SꢀWRꢀꢎꢀFKDQQHOV
ꢁꢇꢅꢇꢊꢀN+]ꢀEHHS
$'&ꢁ
ꢆꢂELWꢀEDVLFꢀWLPHU
ꢈ7,0ꢃꢉ
%HHSHU
$:8ꢀWLPHU
06ꢍꢆꢍꢊꢍ9ꢁ
DocID025118 Rev 5
11/106
103
Block diagram
STM8AF6213/23/23A/26
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent window watchdog
LINUART: Local interconnect network universal asynchronous receiver transmitter
POR: Power on reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
Window WDG: Window watchdog
12/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Product overview
4
Product overview
The following section intends to give an overview of the basic features of the products
covered by this datasheet.
For more detailed information on each feature please refer to STM8S series and STM8AF
series 8-bit microcontrollers reference manual (RM0016).
4.1
Central processing unit (CPU)
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
4.1.1
Architecture and registers
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction.
4.1.2
4.1.3
Addressing
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
DocID025118 Rev 5
13/106
103
Product overview
STM8AF6213/23/23A/26
4.2
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module together with an integrated debug module permit non-
intrusive, real-time in-circuit debugging and fast memory programming.
4.2.1
SWIM
Single wire interface module for direct access to the debug mode and memory
programming. The interface can be activated in all device operation modes.The maximum
data transmission speed is 145 byte/ms.
4.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined breakpoint configurations
4.3
Interrupt controller
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 28 external interrupts on 7 vectors including TLI
Trap and reset interrupts
4.4
Flash program and data EEPROM memory
Up to 8 Kbyte of Flash program single voltage Flash memory
640 byte true data EEPROM
User option byte area
4.4.1
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option byte.
To perform in-application programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to write to
data EEPROM, modify the contents of main program memory or the device option byte.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to the figure below.
14/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Product overview
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
Main program memory: up to 8 Kbyte minus UBC
User-specific boot code (UBC): configurable up to 8 Kbyte
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually
the IAP and communication routines.
Figure 2. Flash memory organization
'DWDꢀPHPRU\ꢀDUHDꢀꢈꢀꢃꢊꢋꢀE\WHꢉ
'DWD
((3520
PHPRU\
2SWLRQꢀE\WHV
3URJUDPPDEOHꢀDUHD
ꢈIURPꢀꢃꢊꢀE\WHꢀꢈꢁꢀSDJHꢉ
WRꢀXSꢀWRꢀꢆꢀ.E\WH
ꢈLQꢀꢁꢀSDJHꢀVWHSVꢉ
8%&ꢀDUHD
5HPDLQVꢀZULWHꢀSURWHFWHGꢀGXULQJꢀ,$3
/RZꢂGHQVLW\
)ODVKꢀSURJUDP
PHPRU\
ꢈXSꢀWRꢀꢆ.E\WHꢉ
)ODVKꢀSURJUDPꢀPHPRU\ꢀDUHD
:ULWHꢀDFFHVVꢀSRVVLEOHꢀIRUꢀ,$3
06ꢍꢆꢍꢊꢊ9ꢁ
4.4.2
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
DocID025118 Rev 5
15/106
103
Product overview
STM8AF6213/23/23A/26
4.5
Clock controller
The clock controller distributes the system clock (f
) coming from different oscillators
MASTER
to the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness.
4.5.1
Features
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
Safe clock switching: Clock sources can be changed safely on the fly in Run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock sources: four different clock sources can be used to drive the master
clock:
–
–
–
–
1-16 MHz high-speed external crystal (HSE)
Up to 16 MHz high-speed user-external clock (HSE user-ext)
16 MHz high-speed internal RC oscillator (HSI)
128 kHz low-speed internal RC (LSI)
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Periphera
l clock
Peripheral
clock
Peripheral
clock
Peripheral
clock
Bit
Bit
Bit
Bit
PCKEN17
PCKEN16
TIM1
TIM5
PCKEN13 LINUART PCKEN27 Reserved PCKEN23
PCKEN12 Reserved PCKEN26 Reserved PCKEN22
ADC
AWU
PCKEN15 Reserved PCKEN11
PCKEN14 TIM6 PCKEN10
SPI
I2C
PCKEN25 Reserved PCKEN21 Reserved
PCKEN24 Reserved PCKEN20 Reserved
16/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Product overview
4.6
Power management
For efficient power management, the application can be put in one of four different low-
power modes. Users can configure each mode to obtain the best compromise between
lowest power consumption, fastest start-up time and available wakeup sources.
Wait mode: in this mode, the CPU is stopped but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
Active-halt mode with regulator on: in this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in Active-halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
Active-halt mode with regulator off: this mode is the same as Active-halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
Halt mode: in this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window.
A reset is generated in two situations:
1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: the downcounter is refreshed before its value is lower than the
one stored in the window register.
DocID025118 Rev 5
17/106
103
Product overview
STM8AF6213/23/23A/26
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure.
The IWDG time base spans from 60 µs to 1 s
4.8
4.9
Auto wakeup counter
Used for auto wakeup from active halt mode
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
16-bit up, down and up/down auto-reload counter with 16-bit fractional prescaler.
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output.
Synchronization module to control the timer with external signals or to synchronise with
TIM5 or TIM6
Break input to force the timer outputs into a defined state
Three complementary outputs with adjustable dead time
Encoder mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
18/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Product overview
4.11
TIM5 - 16-bit general purpose timer
16-bit autoreload (AR) up-counter
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
3 individually configurable capture/compare channels
PWM mode
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
Synchronization module to control the timer with external signals or to synchronize with
TIM1 or TIM6
4.12
TIM6 - 8-bit basic timer
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
Clock source: CPU clock
Interrupt source: 1 x overflow/update
Synchronization module to control the timer with external signals or to synchronize with
TIM1 or TIM5.
Table 3. TIM timer features
Timer
Counter
size (bits)
Counting
mode
CAPCOM Complemen
channels tary outputs
synchroniz
ation/
Timer
Prescaler
Ext. trigger
chaining
Any integer
from 1 to
65536
TIM1
TIM5
TIM6
16
16
8
Up/down
Up
4
3
0
3
0
0
Yes
No
No
Any power
of 2 from 1
to 32768
Yes
Any power
of 2 from 1
to 128
Up
DocID025118 Rev 5
19/106
103
Product overview
STM8AF6213/23/23A/26
4.13
Analog-to-digital converter (ADC1)
The STM8AF6213, STM8AF6223, STM8AF6223A and STM8AF6226 products contain a
10-bit successive approximation A/D converter (ADC1) with up to 7 external and 1 internal
multiplexed input channels and the following main features:
Input voltage range: 0 to V
Input voltage range: 0 to V
DD
DDA
Conversion time: 14 clock cycles
Single and continuous and buffered continuous conversion modes
Buffer size (n x 10 bits) where n = number of input channels
Scan mode for single and continuous conversion of a sequence of channels
Analog watchdog capability with programmable upper and lower thresholds
Internal reference voltage on channel AIN7
Analog watchdog interrupt
External trigger input
Trigger from TIM1 TRGO
End of conversion (EOC) interrupt
Note:
Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog.
Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.
Internal bandgap reference voltage
Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal
bandgap reference is constant and can be used, for example, to monitor V . It is
DD
independent of variations in V and ambient temperature T .
DD
A
4.14
Communication interfaces
The following communication interfaces are implemented:
LINUART: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.2 capability
SPI: full and half-duplex, 8 Mbit/s
I²C: up to 400 Kbit/s
Some peripheral names differ between the datasheet and STM8S series and STM8AF
series 8-bit microcontrollers reference manual, RM0016 (see Table 4).
Table 4. Communication peripheral naming correspondence
Peripheral name in reference manual
Peripheral name in datasheet
(RM0016)
LINUART
UART4
20/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Product overview
4.14.1
LINUART
Main features
1 Mbit/s full duplex SCI
SPI emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
LIN mode
Single wire half duplex mode
LIN mode
Master mode:
LIN break and delimiter generation
LIN break and delimiter detection with separate flag and interrupt source for read back
checking.
Slave mode:
Autonomous header handling – one single interrupt per valid header
Mute mode to filter responses
Identifier parity error checking
LIN automatic resynchronization, allowing operation with internal RC oscillator (HSI)
clock source
Break detection at any time, even during a byte reception
Header errors detection:
–
–
–
–
–
Delimiter too short
Synch field error
Deviation error (if automatic resynchronization is enabled)
Framing error in synch field or identifier field
Header time-out
DocID025118 Rev 5
21/106
103
Product overview
STM8AF6213/23/23A/26
Asynchronous communication (UART mode)
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
/16) and capable of
CPU
–
–
Address bit (MSB)
Idle line (interrupt)
Transmission error detection with interrupt generation
Parity control
Synchronous communication
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
/16)
CPU
4.14.2
Serial peripheral interface (SPI)
Maximum speed: 8 Mbit/s (f
/2) both for master and slave
MASTER
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave /master selection input pin
2
4.14.3
Inter integrated circuit (I C) interface
2
I C master features:
–
–
Clock generation
Start and stop generation
2
I C slave features:
2
–
–
Programmable I C address detection
Stop bit detection
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
–
–
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
22/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
5
Pinout and pin description
The following table presents the meaning of the abbreviations in use in the pin description
tables in this section.
Table 5. Legend/abbreviations for pinout tables
Type
I= input, O = output, S = power supply
Level
Input
CM = CMOS (standard for all I/Os)
HS = High sink
Output
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control
configuration
Input
float = floating, wpu = weak pull-up
Output
T = true open drain, OD = open drain, PP = push pull
Bold X (pin state after internal reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase and
after the internal reset release.
5.1
TSSOP20 pinouts and pin descriptions
Figure 3. STM8AF6213/STM8AF6223 TSSOP20 pinout
>/,18$57B&.@ꢀ7,0ꢌB&+ꢁꢇ%((3ꢇꢈ+6ꢉꢀ3'ꢊ
$,1ꢌꢇ/,18$57B7;ꢇꢈ+6ꢉꢀ3'ꢌ
3'ꢍꢀꢈ+6ꢉꢇ$,1ꢊꢇ7,0ꢌB&+ꢅꢇ$'&B(75
3'ꢅꢀꢈ+6ꢉꢇ$,1ꢍꢀ>7,0ꢌB&+ꢍ@
ꢁ
ꢅ
ꢍ
ꢊ
ꢌ
ꢃ
ꢎ
ꢆ
ꢐ
ꢁꢋ
ꢅꢋ
ꢁꢐ
ꢁꢆ
ꢁꢎ
ꢁꢃ
ꢁꢌ
ꢁꢊ
ꢁꢍ
ꢁꢅ
ꢁꢁ
3'ꢁꢀꢈ+6ꢉꢇ6:,0
$,1ꢃꢇ/,18$57B5;ꢇꢈ+6ꢉꢀ3'ꢃ
3&ꢎꢀꢈ+6ꢉꢇ63,B0,62ꢀ>7,0ꢁB&+ꢅ@
3&ꢃꢀꢈ+6ꢉꢇ63,B026,ꢀ>7,0ꢁB&+ꢁ@
3&ꢌꢀꢈ+6ꢉꢇ63,B6&.ꢀ>7,0ꢌB&+ꢁ@
3&ꢊꢀꢈ+6ꢉꢇ7,0ꢁB&+ꢊꢇ&/.B&&2ꢇ$,1ꢅꢀ>7,0ꢁB&+ꢅ1@
3&ꢍꢀꢈ+6ꢉꢇ7,0ꢁB&+ꢍꢀ>7/,@>7,0ꢁB&+ꢁ1@
3%ꢊꢀꢈ7ꢉꢇ,ꢅ&B6&/ꢀ>$'&B(75@
1567
26&,1ꢇ3$ꢁ
26&287ꢇ3$ꢅ
966
9&$3
9''
>63,B166@ꢀ7,0ꢌB&+ꢍꢇꢈ+6ꢉꢀ3$ꢍ
3%ꢌꢀꢈ7ꢉꢇ,ꢅ&B6'$ꢀ>7,0ꢁB%.,1@
06ꢍꢆꢍꢊꢌ9ꢁ
1. (HS) high sink capability.
2. (T) true open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
DocID025118 Rev 5
23/106
103
Pinout and pin description
STM8AF6213/23/23A/26
Figure 4. STM8AF6223A TSSOP20 pinout
>/,18$57B&.@ꢀ7,0ꢌB&+ꢁꢇ%((3ꢇꢈ+6ꢉꢀ3'ꢊ
3'ꢍꢀꢈ+6ꢉꢇ$,1ꢊꢇ7,0ꢌB&+ꢅꢇ$'&B(75
ꢁ
ꢅ
ꢍ
ꢊ
ꢌ
ꢃ
ꢎ
ꢆ
ꢐ
ꢁꢋ
ꢅꢋ
ꢁꢐ
ꢁꢆ
ꢁꢎ
ꢁꢃ
ꢁꢌ
ꢁꢊ
ꢁꢍ
ꢁꢅ
ꢁꢁ
$,1ꢌꢇ/,18$57B7;ꢇꢈ+6ꢉꢀ3'ꢌ
3'ꢅꢀꢈ+6ꢉꢇ$,1ꢍꢀ>7,0ꢌB&+ꢍ@
3'ꢁꢀꢈ+6ꢉꢇ6:,0
$,1ꢃꢇ/,18$57B5;ꢇꢈ+6ꢉꢀ3'ꢃ
3&ꢎꢀꢈ+6ꢉꢇ63,B0,62ꢀ>7,0ꢁB&+ꢅ@
3&ꢃꢀꢈ+6ꢉꢇ63,B026,ꢀ>7,0ꢁB&+ꢁ@
3&ꢌꢀꢈ+6ꢉꢇ63,B6&.ꢀ>7,0ꢌB&+ꢁ@
3&ꢊꢀꢈ+6ꢉꢇ7,0ꢁB&+ꢊꢇ&/.B&&2ꢇ$,1ꢅꢀ>7,0ꢁB&+ꢅ1@
3%ꢋꢀꢈ+6ꢉꢇ7,0ꢁB&+ꢁ1ꢇ$,1ꢋ
1567
26&,1ꢇ3$ꢁ
26&287ꢇ3$ꢅ
966
9&$3
9''
3%ꢁꢀꢈ+6ꢉꢇ7,0ꢁB&+ꢅ1ꢇ$,1ꢁ
>7,0ꢌB%.,1@ꢀ,ꢅ&B6'$ꢇꢈ7ꢉꢀ3%ꢌ
3%ꢊꢀꢈ7ꢉꢇ,ꢅ&B6&/ꢀ>$'&B(75@
06ꢍꢆꢍꢊꢃ9ꢁ
1. (HS) high sink capability.
2. (T) true open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description
Input
Output
Alternate
function
afterremap
[option bit]
Main
function
(afterreset)
Default
alternate
function
Pin name
Type
Timer 5 -
channel
1/BEEP
output
PD4/ TIM5_CH1/
BEEP
[LINUART_CK]
LINUART
clock
[AFR2]
1
2
3
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
X
X
X
X
X
X
Port D4
Port D5
Port D6
Analog
input 5/
LINUART
data
PD5/ AIN5/
LINUART_TX
HS O3
HS O3
-
-
transmit
Analog
input 6/
LINUART
datareceive
PD6/ AIN6/
LINUART_RX
4
5
NRST
I/O
I/O
-
X
-
-
-
-
-
-
Reset
Resonator/
crystal in
PA1/ OSCIN(2)
X
X
X
O1
X
X
Port A1
Port A2
-
-
Resonator/
crystal out
6
PA2/ OSCOUT
I/O
X
X
X
O1
X
X
7
8
9
VSS
VCAP
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital ground
1.8 V regulator capacitor
Digital power supply
24/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description (continued)
Input
Output
Alternate
Default
Main
function
(afterreset)
function
Pin name
Type
alternate
function
afterremap
[option bit]
SPI master/
slave select
[AFR1]
PA3/ TIM5_CH3
[SPI_NSS]
Timer 5
channel 3
10
I/O
I/O
X
X
X
-
X
X
HS O3
X
X
-
Port A3
Port B5
Timer 1 -
break input
[AFR4]
PB5/ I2C_SDA
11
-
-
O1 T(3)
I2C data
I2C clock
[TIM1_BKIN]
ADC
external
trigger
PB4/ I2C_SCL
[ADC_ETR]
12
I/O
I/O
X
X
-
X
X
O1 T(3)
-
Port B4
Port C3
[AFR4]
Top level
interrupt
[AFR3]
Timer 1
inverted
channel 1
[AFR7]
PC3/
13 TIM1_CH3/[TLI]/[
TIM1_CH1N]
Timer 1 -
channel 3
X
HS O3
X
X
X
Analog
input 2
[AFR2]Time
r 1 inverted
channel 2
[AFR7]
Timer 1 -
channel 4
/configurabl
e clock
PC4/ TIM1_CH4/
14 CLK_CCO/AIN2/[
TIM1_CH2N]
I/O
X
X
X
HS O3
X
Port C4
output
Timer 5
channel 1
[AFR0]
PC5/SPI_SCK
[TIM5_CH1]
15
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C5
Port C6
SPI clock
Timer 1
channel 1
[AFR0]
PC6/ SPI_MOSI
[TIM1_CH1]
PI master
out/slave in
16
Timer 1
channel
2[AFR0]
PC7/ SPI_MISO
[TIM1_CH2]
SPI master
in/ slave out
17
I/O
I/O
X
X
X
X
X
X
HS O3
HS O4
X
X
X
X
Port C7
Port D1
SWIM data
interface
18
PD1/ SWIM(4)
-
DocID025118 Rev 5
25/106
103
Pinout and pin description
STM8AF6213/23/23A/26
Table 6. STM8AF6213/STM8AF6223 TSSOP20 pin description (continued)
Input
Output
Alternate
Default
Main
function
(afterreset)
function
Pin name
Type
alternate
afterremap
function
[option bit]
Analog
input 3
PD2/AIN3
[TIM5_CH3]
[AFR2]
Timer 52 -
channel 3
[AFR1]
19
20
I/O
I/O
X
X
X
X
X
X
HS O3
X
X
X
X
Port D2
Port D3
-
Analog
input 4
Timer 52 -
channel
2/ADC
external
trigger
PD3/ AIN4/
TIM5_CH2/
ADC_ETR
HS O3
-
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Section: Absolute maximum ratings).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented)
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Table 7. STM8AF6223A TSSOP20 pin description
Input
Output
Alternate
function
afterremap
[option bit]
Main
function
(afterreset)
Default
alternate
function
Pin name
Type
Timer 5 -
channel
1/BEEP
output
PD4/ TIM5_CH1/
BEEP/SPI_NSS
[LINUART_CK]
LINUART
clock
[AFR2]
1
2
I/O
I/O
X
X
X
X
X
X
HS O3
X
X
X
X
Port D4
Port D5
Analog
input 5/
LINUART
data
PD5/ AIN5/
LINUART_TX
HS O3
-
transmit
26/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
Table 7. STM8AF6223A TSSOP20 pin description (continued)
Input
Output
Alternate
Main
function
(afterreset)
Default
alternate
function
function
afterremap
[option bit]
Pin name
Type
Analog
input 6/
LINUART
datareceive
PD6/ AIN6/
LINUART_RX
3
I/O
X
X
X
HS O3
X
X
Port D6
-
4
5
NRST
I/O
I/O
-
X
-
-
-
-
-
-
Reset
-
-
Resonator/
crystal in
PA1/ OSCIN(2)
X
X
X
O1
X
X
Port A1
Port A2
Resonator/
crystal out
6
PA2/ OSCOUT
I/O
X
X
X
-
O1
X
X
-
7
8
9
VSS
VCAP
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital ground
-
-
-
1.8 V regulator capacitor
Digital power supply
Timer 1 -
break input
[AFR4]
PB5/ I2C_SDA
[TIM1_BKIN]
10
11
I/O
I/O
X
X
X
-
X
X
-
O1 T(3)
X
-
Port A5
Port B4
I2C data
I2C clock
ADC
external
trigger
PB4/ I2C_SCL
[ADC_ETR]
-
O1 T(3)
[AFR4]
Timer 1 -
inverted
channel
2/Analog
input 1
PB1/
TIM1_CH2N/
AIN1
12
13
I/O
I/O
X
X
X
X
X
X
HS O3
X
X
X
X
Port B1
Port B0
-
-
Timer 1 -
inverted
channel
1/Analog
input 0
PB0/
TIM1_CH1N/AIN0
HS O3
Timer 1 -
channel 4
Analog
input 2
PC4/ TIM1_CH4/
14 CLK_CCO/AIN2/[
TIM1_CH2]
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port C4
Port C5
/configurabl [AFR2]Time
e clock
output
r 1 channel
2 [AFR7]
Timer 5
channel 1
[AFR0]
PC5/SPI_SCK
15
SPI clock
[TIM5_CH1]
DocID025118 Rev 5
27/106
103
Pinout and pin description
STM8AF6213/23/23A/26
Table 7. STM8AF6223A TSSOP20 pin description (continued)
Input
Output
Alternate
Default
Main
function
(afterreset)
function
Pin name
Type
alternate
afterremap
function
[option bit]
Timer 1
PI master
PC6/ SPI_MOSI
[TIM1_CH1]
16
I/O
X
X
X
HS O3
X
X
Port C6
channel 1
out/slave in
[AFR0]
Timer 1
SPI master
PC7/ SPI_MISO
[TIM1_CH2]
17
18
I/O
I/O
X
X
X
X
X
X
HS O3
HS O4
X
X
X
X
Port C7
Port D1
channel
in/ slave out
2[AFR0]
SWIM data
-
PD1/ SWIM(4)
interface
Analog
input 3
PD2/AIN3/
TLI[TIM5_CH3]
[AFR2]
Timer 5 -
channel 3
[AFR1]
19
20
I/O
I/O
X
X
X
X
X
X
HS O3
X
X
X
X
Port D2
Port D3
-
Analog
input 4
Timer 52 -
channel
2/ADC
external
trigger
PD3/ AIN4/
TIM5_CH2/
ADC_ETR
HS O3
-
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Section: Absolute maximum ratings).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if
Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
28/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
5.2
LQFP32 pinout and pin description
Figure 5. STM8AF6226 LQFP32 pinout
ꢍꢅꢍꢁꢍꢋꢅꢐꢅꢆꢅꢎꢅꢃꢅꢌ
ꢅꢊ
ꢁ
ꢅ
ꢍ
ꢊ
ꢌ
ꢃ
ꢎ
ꢆ
1567
26&,1ꢇ3$ꢁ
26&287ꢇ3$ꢅ
966
3&ꢎꢀꢈ+6ꢉꢇ63,B0,62ꢀ>7,0ꢁB&+ꢅ@
ꢅꢍ
ꢅꢅ
ꢅꢁ
ꢅꢋ
ꢁꢐ
ꢁꢆ
ꢁꢎ
3&ꢃꢀꢈ+6ꢉꢇ63,B026,ꢀ>7,0ꢁB&+ꢁ@
3&ꢌꢀꢈ+6ꢉꢇ63,B6&.ꢀ>7,0ꢌB&+ꢁ@
3&ꢊꢈ+6ꢉ7,0ꢁB&+ꢊꢇ&/.B&&2ꢀ>$,1ꢅ@ꢀ>7,0ꢁB&+ꢅ1@ꢀ
3&ꢍꢈ+6ꢉꢇ7,0ꢁB&+ꢍꢀ>7/,@ꢀ>7,0ꢁB&+ꢁ1@ꢀ
3&ꢅꢈ+6ꢉꢇ7,0ꢁB&+ꢅꢀ>7,0ꢁB&+ꢍ1@ꢀ
3&ꢁꢈ+6ꢉꢇ7,0ꢁB&+ꢁꢇ/,18$57B&.>7,0ꢀ B&+ꢅ1@ꢀ
3(ꢌꢇ63,B166ꢀ>7,0ꢁB&+ꢁ1@
9&$3
9''
>/,18$57B7;@>63,B166@ꢀ7,0ꢌB&+ꢍꢇꢈ+6ꢉꢀ3$ꢍ
>/,18$57B5;@ꢀ3)ꢊ
ꢐ ꢁꢋꢁꢁꢁꢅꢁꢍꢁꢊꢁꢌꢁꢃ
06ꢍꢆꢍꢊꢎ9ꢁ
1. (HS) high sink capability.
2. (T) true open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Table 8. STM8AF6226 LQFP32 pin description
Input
Output
Alternate
function
after remap
[option bit]
Main
function
(after reset)
Default
alternate
function
Pin name
Type
1
2
NRST
I/O
I/O
-
X
-
-
-
-
-
-
Reset
-
-
Resonator/
crystal in
PA1/ OSCIN(2)
X
X
X
O1
X
X
Port A1
Port A2
Resonator/
crystal out
3
PA2/ OSCOUT
I/O
X
X
X
-
O1
X
X
-
DocID025118 Rev 5
29/106
103
Pinout and pin description
STM8AF6213/23/23A/26
Table 8. STM8AF6226 LQFP32 pin description (continued)
Input
Output
Alternate
Default
Main
function
(after reset)
function
Pin name
Type
alternate
after remap
function
[option bit]
4
5
6
VSS
VCAP
VDD
S
S
S
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Digital ground
-
-
-
1.8 V regulator capacitor
Digital power supply
SPI master/
slave select
[AFR1]/
LINUART
data transmit
[AFR1:0]
PA3/
TIM5_CH3
[SPI_NSS]
[LINUART_TX]
Timer 52
Port A3
7
8
I/O
X
X
X
HS O3
X
X
channel 3
LINUART
PF4
[LINUART_RX]
I/O
X
X
-
-
O1
O1
O1
X
X
Port F4
data receive
[AFR1:0]
-
9
PB7
PB6
I/O
I/O
X
X
X
X
X
X
-
-
X
X
X
X
Port B7
Port B6
-
-
-
-
10
Timer 1 -
break input
[AFR4]
PB5/ I2C_SDA
[TIM1_BKIN]
11
12
I/O
I/O
X
X
-
-
X
X
-
-
O1 T(3)
-
-
Port B5
Port B4
I2C data
I2C clock
ADC
external
trigger
PB4/ I2C_SCL
[ADC_ETR]
O1 T(3)
[AFR4]
Analog input
3/ Timer 1
external
PB3/
AIN3/TIM1_ET
R
13
14
15
16
I/O
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
X
X
X
HS O3
HS O3
HS O3
HS O3
X
X
X
X
X
X
X
X
Port B3
Port B2
Port B1
Port B0
-
-
-
-
trigger
Analog input
2/ Timer 1 -
inverted
PB2/ AIN2/
TIM1_CH3N
channel 3
Analog input
1/ Timer 1 -
inverted
PB1/ AIN1/
TIM1_CH2N
channel 2
Analog input
0/ Timer 1 -
inverted
PB0/ AIN0/
TIM1_CH1N
channel 1
30/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
Table 8. STM8AF6226 LQFP32 pin description (continued)
Input
Output
Alternate
Default
Main
function
(after reset)
function
Pin name
Type
alternate
after remap
function
[option bit]
Timer 1 -
PE5/ SPI_NSS
17
SPI master/
slave select
inverted
channel 1
[AFR1:0]
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
X
X
X
X
X
X
Port E5
Port C1
Port C2
[TIM1_CH1N]
PC1/
Timer 1 -
channel 1
LINUART
clock
Timer 1 -
inverted
channel 2
[AFR1:0]
TIM1_CH1/
LINUART_CK
18
HS O3
HS O3
[TIM1_CH2N]
Timer 1 -
inverted
channel 3
[AFR1:0]
PC2/
Timer 1 -
channel 2
19
TIM1_CH2
[TIM1_CH3N]
Top level
interrupt
[AFR3]Timer
1 inverted
channel 1
[AFR7]
PC3/
Timer 1 -
channel 3
20 TIM1_CH3/[TLI]
[TIM1_CH1N]
I/O
I/O
X
X
X
X
X
X
HS O3
X
X
X
X
Port C3
Port C4
Analog input
2
[AFR2]Timer
1 inverted
channel 2
[AFR7]
PC4/
TIM1_CH4/
CLK_CCO/[AIN
2][TIM1_CH2N]
Timer 1 -
channel 4
/configurable
clock output
21
HS O3
Timer 5
channel 1
[AFR0]
PC5/SPI_SCK
22
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
HS O3
HS O3
X
X
X
X
X
X
Port C5
Port C6
Port C7
SPI clock
[TIM5_CH1]
PC6/
Timer 1
channel 1
[AFR0]
PI master
out/slave in
23
24
SPI_MOSI
[TIM1_CH1]
PC7/
SPI_MISO
[TIM1_CH2]
Timer 1
channel
2[AFR0]
SPI master
in/ slave out
PD0/
TIM1_BKIN
[CLK_CCO]
Configurable
clock output
[AFR5]
Timer 1 -
break input
25
26
I/O
I/O
X
X
X
X
HS O3
HS O4
X
X
X
X
Port D0
Port D1
SWIM data
interface
PD1/ SWIM(4)
X
X
-
DocID025118 Rev 5
31/106
103
Pinout and pin description
STM8AF6213/23/23A/26
Table 8. STM8AF6226 LQFP32 pin description (continued)
Input
Output
Alternate
Default
Main
function
(after reset)
function
Pin name
Type
alternate
after remap
function
[option bit]
Analog input
3 [AFR2]
Timer 52 -
channel 3
[AFR1]
PD2/[AIN3]
[TIM5_CH3]
27
I/O
X
X
X
HS O3
X
X
Port D2
-
Analog input
4 Timer 52 -
channel
2/ADC
external
PD3/ AIN4/
TIM5_CH2/
ADC_ETR
28
29
I/O
I/O
X
X
X
X
X
X
HS O3
HS O3
X
X
X
X
Port D3
Port D4
-
trigger
PD4/
TIM5_CH1/
BEEP
Timer 5 -
channel
1/BEEP
output
LINUART
clock [AFR2]
[LINUART_CK]
Analog input
5/ LINUART
data transmit
PD5/ AIN5/
LINUART_TX
30
31
32
I/O
I/O
I/O
X
X
X
X
X
X
X
X
X
HS O3
HS O3
HS O3
X
X
X
X
X
X
Port D5
Port D6
Port D7
-
-
Analog input
6/ LINUART
data receive
PD6/ AIN6/
LINUART_RX
Timer 1 -
channel 4
[AFR6]
PD7/ TLI
[TIM1_CH4]
Top level
interrupt
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings (see Section: Absolute maximum ratings).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented).
4. The PD1 pin is in input pull-up during the reset phase and after internal reset release.
32/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Pinout and pin description
5.3
Alternate function remapping
As shown in the rightmost column of Table 6, Table 7 and Table 8 some alternate functions
can be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping
option is active, the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of STM8S series and STM8AF series 8-bit microcontrollers reference manual,
RM0016).
DocID025118 Rev 5
33/106
103
Memory and register map
STM8AF6213/23/23A/26
6
Memory and register map
6.1
Memory map
Figure 6. Memory map
ꢋ[ꢋꢋꢀꢋꢋꢋꢋ
5$0
ꢈꢁꢀ.E\WHꢉ
ꢀꢌꢁꢍꢀE\WHꢀVWDFN
5HVHUYHG
ꢋ[ꢋꢋꢀꢋꢍ))ꢀ
ꢋ[ꢋꢋꢀꢋꢆꢋꢋ
ꢋ[ꢋꢋꢀꢍ)))
ꢋ[ꢋꢋꢀꢊꢋꢋꢋ
ꢃꢊꢋꢀE\WHꢀGDWDꢀ((3520
5HVHUYHG
ꢋ[ꢋꢋꢀꢊꢅꢎ)
ꢋ[ꢋꢋꢀꢊꢅꢆꢋ
ꢋ[ꢋꢋꢀꢊꢎ))
ꢋ[ꢋꢋꢀꢊꢆꢋꢋ
ꢋ[ꢋꢋꢀꢊꢆꢋ$
ꢋ[ꢋꢋꢀꢊꢆꢋ%
ꢋ[ꢋꢋꢀꢊꢆꢃꢊ
ꢋ[ꢋꢋꢀꢊꢆꢃꢌ
2SWLRQꢀE\WHV
5HVHUYHG
8QLTXHꢀ,'
ꢋ[ꢋꢋꢀꢊꢆꢎꢋ
ꢋ[ꢋꢋꢀꢊꢆꢎꢁ
5HVHUYHG
ꢋ[ꢋꢋꢀꢊ)))
ꢋ[ꢋꢋꢀꢌꢋꢋꢋ
*3,2ꢀDQGꢀSHULSKHUDOꢀUHJLVWHUV
ꢋ[ꢋꢋꢀꢌꢎ))
ꢋ[ꢋꢋꢀꢌꢆꢋꢋ
5HVHUYHG
ꢋ[ꢋꢋꢀꢎ())
ꢋ[ꢋꢋꢀꢎ)ꢋꢋ
&38ꢇ6:,0ꢇGHEXJꢇ,7&
UHJLVWHUV
ꢋ[ꢋꢋꢀꢎ)))
ꢋ[ꢋꢋꢀꢆꢋꢋꢋ
ꢍꢅꢀLQWHUUXSWꢀYHFWRUV
ꢋ[ꢋꢋꢀꢆꢋꢎ)
ꢋ[ꢋꢋꢀꢆꢋꢆꢋ
)ODVKꢀSURJUDPꢀPHPRU\
ꢈꢆꢀ.E\WHꢉ
ꢋ[ꢋꢋꢀꢐ)))
ꢋ[ꢋꢋꢀ$ꢋꢋꢋ
ꢀ
5HVHUYHG
ꢋ[ꢋꢅꢀꢎ)))
06ꢍꢆꢍꢊꢆ9ꢁ
34/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Memory and register map
Table 9. Memory model for the devices covered in this datasheet
Flash program
memory end
address
Flash program
memory size
RAM end
address
Stack roll-over
address
RAM size
8 K
4 K
0x00 9FFF
0x00 8FFF
1 K
0x00 03FF
0x00 0200
6.2
Register map
6.2.1
I/O port hardware register map
Table 10. I/O port hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX(1)
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
0x00
Port A control register 2
0x00
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
0x00
0xXX(1)
Port B
Port C
Port D
0x00
0x00
Port B control register 2
0x00
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
0x00
0xXX(1)
0x00
0x00
Port C control register 2
0x00
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX(1)
0x00
0x02
Port D control register 2
0x00
DocID025118 Rev 5
35/106
103
Memory and register map
Address
STM8AF6213/23/23A/26
Table 10. I/O port hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
0x00
0xXX(1)
0x00
Port E
0x00
Port E control register 2
0x00
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
0x00
0xXX(1)
Port F
0x00
0x00
Port F control register 2
0x00
1. Depends on the external circuitry.
Table 11. General hardware register map
Reset
status
Address
Block
Register label
Register name
0x00 501E to
0x00 5069
Reserved area (60 byte)
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH_FPR
Flash control register 1
Flash control register 2
0x00
0x00
0xFF
0x00
0xFF
Flash complementary control register 2
Flash protection register
Flash
FLASH_NFPR Flash complementary protection register
Flash in-application programming status
FLASH_IAPSR
0x00 505F
0x40
register
0x00 5060 to
0x00 5061
Reserved area (2 byte)
Flash Program memory unprotection
FLASH_PUKR
0x00 5062
Flash
Flash
0x00
0x00
register
0x00 5063
0x00 5064
Reserved area (1 byte)
FLASH_DUKR
Data EEPROM unprotection register
Reserved area (59 byte)
0x00 5065 to
0x00 509F
0x00 50A0
0x00 50A1
EXTI_CR1
EXTI_CR2
External interrupt control register 1
External interrupt control register 2
0x00
0x00
ITC
0x00 50A2 to
0x00 50B2
Reserved area (17 byte)
36/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Memory and register map
Table 11. General hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 50B3
RST
RST_SR
Reset status register
0xXX(1)
0x00 50B4 to
0x00 50BF
Reserved area (12 byte)
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 50CC
CLK_ICKR
CLK_ECKR
Internal clock control register
External clock control register
0x01
0x00
CLK
Reserved area (1 byte)
CLK_CMSR
CLK_SWR
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
CLK_CCOR
CLK_PCKENR2
CLK_HSITRIMR
CLK_SWIMCCR
HSI clock calibration trimming register
0x00
CLK
0bXXXX
XXX0
0x00 50CD
SWIM clock control register
Reserved area (3 byte)
0x00 50CE
to 0x00 50D0
0x00 50D1
0x00 50D2
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D3 to
0x00 50DF
Reserved area (13 byte)
IWDG key register
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
0xXX(2)
0x00
IWDG
IWDG prescaler register
IWDG reload register
0xFF
0x00 50E3 to
0x00 50EF
Reserved area (13 byte)
0x00 50F0
0x00 50F1
AWU_CSR1
AWU_APR
AWU control/status register 1
0x00
0x3F
AWU asynchronous prescaler buffer
register
AWU
0x00 50F2
0x00 50F3
AWU_TBR
BEEP_CSR
AWU timebase selection register
BEEP control/status register
0x00
0x1F
BEEP
0x00 50F4 to
0x00 50FF
Reserved area (12 byte)
DocID025118 Rev 5
37/106
103
Memory and register map
Address
STM8AF6213/23/23A/26
Table 11. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI_CR1
SPI_CR2
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
0x00
0x00
0x00
0x02
0x00
0x07
0xFF
0xFF
SPI_ICR
SPI_SR
SPI
SPI_DR
SPI data register
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
0x00 5208 to
0x00 520F
Reserved area (8 byte)
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C_CR1
I2C_CR2
I2C control register 1
I2C control register 2
0x00
0x00
0x00
0x00
0x00
I2C_FREQR
I2C_OARL
I2C_OARH
I2C frequency register
I2C own address register low
I2C own address register high
Reserved area (1 byte)
I2C data register
I2C_DR
I2C_SR1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
I2C
I2C status register 1
I2C_SR2
I2C status register 2
I2C_SR3
I2C status register 3
I2C_ITR
I2C interrupt control register
I2C clock control register low
I2C clock control register high
I2C TRISE register
I2C_CCRL
I2C_CCRH
I2C_TRISER
I2C_PECR
I2C packet error checking register
0x00 521F to
0x00 522F
Reserved area (17 byte)
38/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Address
Memory and register map
Table 11. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
0x00 523B
UART4_SR
UART4_DR
LINUART status register
LINUART data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
UART4_BRR1
UART4_BRR2
UART4_CR1
UART4_CR2
UART4_CR3
UART4_CR4
LINUART baud rate register 1
LINUART baud rate register 2
LINUART control register 1
LINUART control register 2
LINUART control register 3
LINUART control register 4
Reserved
LINUART
UART4_CR6
UART4_GTR
UART4_PSCR
LINUART control register 6
LINUART guard time register
LINUART prescaler
0x00
0x00
0x00
0x00 523C to
0x00 523F
Reserved area (20 byte)
DocID025118 Rev 5
39/106
103
Memory and register map
Address
STM8AF6213/23/23A/26
Table 11. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
TIM1_CR1
TIM1_CR2
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SMCR
TIM1_ETR
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 status register 2
TIM1_EGR
TIM1 event generation register
TIM1 capture/compare mode register 1
TIM1 capture/compare mode register 2
TIM1 capture/compare mode register 3
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register 1
TIM1 capture/compare enable register 2
TIM1 counter high
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
TIM1
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1 output idle state register
0x00 5270 to
0x00 52FF
Reserved area (147 byte)
40/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Address
Memory and register map
Table 11. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
00 530C0x
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
TIM5_CR1
TIM5_CR2
TIM5 control register 1
TIM5 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM5_SMCR
TIM5_IER
TIM5 slave mode control register
TIM5 interrupt enable register
TIM5 status register 1
TIM5_SR1
TIM5_SR2
TIM5 status register 2
TIM5_EGR
TIM5 event generation register
TIM5 capture/compare mode register 1
TIM5 capture/compare mode register 2
TIM5 capture/compare mode register 3
TIM5 capture/compare enable register 1
TIM5 capture/compare enable register 2
TIM5 counter high
TIM5_CCMR1
TIM5_CCMR2
TIM5_CCMR3
TIM5_CCER1
TIM5_CCER2
TIM5_CNTRH
TIM5_CNTRL
TIM5_PSCR
TIM5_ARRH
TIM5_ARRL
TIM5_CCR1H
TIM5_CCR1L
TIM5_CCR2H
TIM5_CCR2L
TIM5_CCR3H
TIM5_CCR3L
TIM5
TIM5 counter low
TIM5 prescaler register
TIM5 auto-reload register high
TIM5 auto-reload register low
TIM5 capture/compare register 1 high
TIM5 capture/compare register 1 low
TIM5 capture/compare reg. 2 high
TIM5 capture/compare register 2 low
TIM5 capture/compare register 3 high
TIM5 capture/compare register 3 low
0x00 5317 to
0x00 533F
Reserved area (43 byte)
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
TIM6_CR1
TIM6_CR2
TIM6_SMCR
TIM6_IER
TIM6 control register 1
TIM6 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM6 slave mode control register
TIM6 interrupt enable register
TIM6 status register
TIM6
TIM6_SR
TIM6_EGR
TIM6_CNTR
TIM6_PSCR
TIM6_ARR
TIM6 event generation register
TIM6 counter
TIM6 prescaler register
TIM6 auto-reload register
DocID025118 Rev 5
41/106
103
Memory and register map
Address
STM8AF6213/23/23A/26
Table 11. General hardware register map (continued)
Reset
status
Block
Register label
Register name
0x00 5349 to
0x00 53DF
Reserved area (153 byte)
ADC data buffer registers
Reserved area (12 byte)
0x00 53E0 to
0x00 53F3
ADC1
ADC _DBxR
0x00
0x00 53F4 to
0x00 53FF
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 5408
0x00 5409
0x00 540A
0x00 540B
0x00 540C
0x00 540D
0x00 540E
0x00 540F
ADC _CSR
ADC_CR1
ADC control/status register
ADC configuration register 1
0x00
0x00
0x00
0x00
0xXX
0xXX
0x00
0x00
0xFF
0x03
0x00
0x00
0x00
0x00
0x00
0x00
ADC_CR2
ADC configuration register 2
ADC_CR3
ADC configuration register 3
ADC_DRH
ADC data register high
ADC_DRL
ADC data register low
ADC_TDRH
ADC_TDRL
ADC _HTRH
ADC_HTRL
ADC _LTRH
ADC_LTRL
ADC _AWSRH
ADC_AWSRL
ADC _AWCRH
ADC _AWCRL
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
ADC high threshold register high
ADC high threshold register low
ADC low threshold register high
ADC low threshold register low
ADC watchdog status register high
ADC watchdog status register low
ADC watchdog control register high
ADC watchdog control register low
ADC1
0x00 5410 to
0x00 57FF
Reserved area (1008 byte)
1. Depends on the previous reset source.
2. Write only register.
42/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Memory and register map
6.2.2
CPU/SWIM/debug module/interrupt controller registers
Table 12. CPU/SWIM/debug module/interrupt controller registers
Reset
status
Address
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 byte)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
ITC
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00 7F78 to
0x00 7F79
Reserved area (2 byte)
SWIM control status register
Reserved area (15 byte)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81 to
0x00 7F8F
DocID025118 Rev 5
43/106
103
Memory and register map
STM8AF6213/23/23A/26
Table 12. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Address
Block
Register label
Register name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B to
0x00 7F9F
Reserved area (5 byte)
1. Accessible by debug module only
44/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Interrupt vector mapping
7
Interrupt vector mapping
Table 13. Interrupt mapping
Wakeup from
active-halt
mode
Source
block
Wakeup from
Description
Interruptvector
address
Priority
halt mode
—
—
0
Reset
Reset
Yes
Yes
0x00 8000
0x00 8004
0x00 8008
0x00 800C
TRAP
TLI
Software interrupt
-
-
-
-
-
External top level interrupt
Auto-wakeup from Halt
1
AWU
Yes
Clock
controller
2
Clock controller
-
-
0x00 8010
3
4
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
Reserved
SPI
Port A external interrupts
Port B external interrupts
Port C external interrupts
Port D external interrupts
Port E external interrupts
Port F
Yes(1)
Yes
Yes
Yes
Yes
-
Yes(1)
Yes
Yes
Yes
Yes
-
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
5
6
7
8
9
-
-
-
10
End of transfer
Yes
Yes
TIM1 update/overflow/
underflow/trigger/break
11
12
13
TIM1
TIM1
TIM5
-
-
-
-
-
-
0x00 8034
0x00 8038
0x00 803C
TIM1 capture/compare
TIM5
update/overflow/trigger
14
15
16
17
TIM5
TIM5 capture/compare
-
-
-
-
-
-
-
-
0x00 8040
0x00 8044
0x00 8048
0x00 804C
Reserved
Reserved
LINUART
-
-
Tx complete
Receive register DATA
FULL
18
LINUART
-
-
0x00 8050
19
20
21
I2C
I2C interrupts
Yes
Yes
0x00 8054
0x00 8058
0x00 805C
Reserved
Reserved
-
-
-
-
-
-
ADC1 end of
22
ADC1
conversion/analog
watchdog interrupt
-
-
0x00 8060
DocID025118 Rev 5
45/106
103
Interrupt vector mapping
STM8AF6213/23/23A/26
Table 13. Interrupt mapping (continued)
Wakeup from
Wakeup from
active-halt
Source
block
Interruptvector
address
Priority
Description
halt mode
mode
TIM6
23
24
TIM6
Flash
-
-
-
-
0x00 8064
0x00 8068
update/overflow/trigger
EOP/WR_PG_DIS
1. Except PA1.
46/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. Except for the ROP (read-out protection) byte, each option byte has
to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for
redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 14: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be modified in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 14. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
protection
(ROP)
0x00
4800
OPT0
ROP[7:0]
0x00
0x00
4801
OPT1
NOPT1
OPT2
UBC[7:0]
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
User boot
code (UBC)
0x00
4802
NUBC[7:0]
0x00
4803
Alternate
function
remapping
(AFR)
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x00
4804
NOPT2
OPT3
NAFR7
NAFR6
NAFR 5
NAFR 4
NAFR 3
NAFR 2
NAFR 1
NAFR 0
0x00
4805
HSI
TRIM
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
Reserved
Reserved
Miscell.
option
0x00
4806
NHSI
TRIM
NLSI
_EN
NIWDG
_HW
NWWDG
_HW
NWWG
_HALT
NOPT3
OPT4
0x00
4807
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
Reserved
Clock option
0x00
4808
NEXT
CLK
NCKAWU
SEL
NPRS
C1
NPRS
C0
NOPT4
OPT5
Reserved
0x00
4809
HSECNT[7:0]
HSE clock
startup
0x00
480A
NOPT5
NHSECNT[7:0]
DocID025118 Rev 5
47/106
103
Option bytes
STM8AF6213/23/23A/26
8.1
Option byte description
Table 15. Option byte description
Description
Option byte no.
ROP[7:0]: Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016) section on Flash/EEPROM memory
readout protection for details.
OPT0
UBC[7:0]: User boot code area
0x00: No UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Page 0 to 1 defined as UBC, memory write-protected
Pages 0 and 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Page 0 to 127 defined as UBC, memory write-protected.
OPT1
Note: Refer to STM8S series and STM8AF series 8-bit microcontrollers
reference manual (RM0016) section on Flash/EEPROM write protection
for more details.
AFR[7:0]
OPT2
Refer to the following sections for the alternate function remapping
descriptions of bits [7:2] and [1:0] respectively.
HSITRIM: high-speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: low-speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3
0: IWDG independent watchdog activated by software
1: IWDG independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on Halt
0: No reset generated on Halt if WWDG active
1: Reset generated on Halt if WWDG active
48/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Option bytes
Table 15. Option byte description (continued)
Description
Option byte no.
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto-wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for AWU
OPT4
PRSC[1:0]: AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
OPT5
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
8.2
STM8AF6213/23/23A/26 alternate function remapping bits
Table 16. STM8AF6226 alternate function remapping bits [7:2] for 32-pin packages
Option byte number
Description(1)
AFR7: Alternate function remapping option 7
0: AFR7 remapping option inactive: default alternate function (2)
1: Port C3 alternate function = = TIM1_CH1N;
port C4 alternate function = TIM1_CH2N
AFR6: Alternate function remapping option 6
0: AFR6 remapping option inactive: default alternate function (2)
1: Port D7 alternate function = TIM1_CH4.
AFR5: Alternate function remapping option 5
0: AFR5 remapping option inactive: default alternate function (2).
1: Port D0 alternate function = CLK_CCO.
OPT2
AFR4: Alternate function remapping option 4
0: AFR4 remapping option inactive: default alternate function (2).
1: Port B4 alternate function = ADC_ETR; port B5 alternate function =
TIM1_BKIN.
AFR3: Alternate function remapping option 3
0: AFR3 remapping option inactive: default alternate function (2)
1: Port C3 alternate function = TLI
AFR2: Alternate function remapping option 2
0: AFR2 remapping option inactive: default alternate function (2)
1: Port C4 alternate function = AIN2; port D2 alternate function = AIN3;
port D4 alternate function = LINUART_CK
1. Do not use more than one remapping option in the same port.
2. Refer to the pin description.
DocID025118 Rev 5
49/106
103
Option bytes
STM8AF6213/23/23A/26
Table 17. STM8AF6213 and STM8AF6223 alternate function remapping bits [7:2]
for 20-pin packages
Option byte number
Description(1)
AFR7: Alternate function remapping option 7
0: AFR7 remapping option inactive: default alternate function (2)
1: Port C3 alternate function = = TIM1_CH1N;
port C4 alternate function = TIM1_CH2N
AFR6: Alternate function remapping option 6
Reserved
AFR5: Alternate function remapping option 5
Reserved
AFR4: Alternate function remapping option 4
OPT2
0: AFR4 remapping option inactive: default alternate function (2).
1: Port B4 alternate function = ADC_ETR; port B5 alternate function =
TIM1_BKIN.
AFR3: Alternate function remapping option 3
0: AFR3 remapping option inactive: default alternate function (2)
1: Port C3 alternate function = TLI
AFR2: Alternate function remapping option 2
0: AFR2 remapping option inactive: default alternate function (2)
1: Port D4 alternate function = LINUART_CK
1. Do not use more than one remapping option in the same port.
2. Refer to the pin description.
Table 18. STM8AF6223A alternate function remapping bits [7:2] for 20-pin packages
Option byte number
Description(1)
AFR7: Alternate function remapping option 7
0: AFR7 remapping option inactive: default alternate function (2)
1: Port C4 alternate function = TIM1_CH2N
AFR6: Alternate function remapping option 6
Reserved
AFR5: Alternate function remapping option 5
Reserved
AFR4: Alternate function remapping option 4
OPT2
0: AFR4 remapping option inactive: default alternate function (2).
1: Port B4 alternate function = ADC_ETR; port B5 alternate function =
TIM1_BKIN.
AFR3: Alternate function remapping option 3
Reserved.
AFR2: Alternate function remapping option 2
0: AFR2 remapping option inactive: default alternate function (2)
1: Port D4 alternate function = LINUART_CK
1. Do not use more than one remapping option in the same port.
2. Refer to the pin description.
50/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Option bytes
Table 19. STM8AF6226 alternate function remapping bits [1:0] for 32-pin packages
Alternate function
AFR1 option bit value AFR0 option bit value
I/O port
mapping
AFR1 and AFR0 remapping options inactive:
Default alternate functions(1)
0
0
0
1
PC5
PC6
PC7
PA3
PD2
PD2
PC5
PC6
PC7
PC2
PC1
PE5
PA3
PF4
TIM5_CH1
TIM1_CH1
TIM1_CH2
SPI_NSS
1
0
TIM5_CH3
TIM5_CH3
TIM5_CH1
TIM1_CH1
TIM1_CH2
TIM1_CH3N
TIM1_CH2N
TIM1_CH1N
LINUART_TX
LINUART_RX
1(2)
1(2)
1. Refer to the pin descriptions.
2. If both AFR1 and AFR0 option bits are set, the SPI hardware NSS management feature is no more
available. If this remapping option is selected and the SPI is enabled, the SSM bit must be configured in the
SPI_CR2 register to select software NSS management.
Table 20. STM8AF6213/STM8AF6223 alternate function remapping bits [1:0]
for 20-pin packages
Alternate function
AFR1 option bit value AFR0 option bit value
I/O port
mapping
AFR1 and AFR0 remapping options inactive:
Default alternate functions(1)
0
0
0
1
PC5
PC6
PC7
PA3
PD2
TIM5_CH1
TIM1_CH1
TIM1_CH2
SPI_NSS
1
0
TIM5_CH3
DocID025118 Rev 5
51/106
103
Option bytes
STM8AF6213/23/23A/26
Table 20. STM8AF6213/STM8AF6223 alternate function remapping bits [1:0]
for 20-pin packages (continued)
Alternate function
AFR1 option bit value AFR0 option bit value
I/O port
mapping
PD2
PC5
PC6
PC7
PC2
PC1
PE5
PA3
PF4
TIM5_CH3
TIM5_CH1
TIM1_CH1
TIM1_CH2
Not available
Not available
Not available
SPI_NSS
1
1
Not available
1. Refer to the pin descriptions.
Table 21. STM8AF6223A alternate function remapping bits [1:0] for 20-pin packages
Alternate function
AFR1 option bit value AFR0 option bit value
I/O port
mapping
AFR1 and AFR0 remapping options inactive:
Default alternate functions(1)
0
0
0
1
PC5
PC6
PC7
PA3
PD2
PD2
PC5
PC6
PC7
PC2
PC1
PE5
PA3
PF4
TIM5_CH1
TIM1_CH1
TIM1_CH2
Not available
TIM5_CH3
TIM5_CH3
TIM5_CH1
TIM1_CH1
TIM1_CH2
Not available
Not available
Not available
Not available
Not available
1
0
1(2)
1(2)
1. Refer to the pin descriptions.
2. If both AFR1 and AFR0 option bits are set, the SPI hardware NSS management feature is no more
available. If this remapping option is selected and the SPI is enabled, the SSM bit must be configured in the
SPI_CR2 register to select software NSS management.
52/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
9
Electrical characteristics
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = -40 °C, T = 25 °C, and
A
A
T = T
(given by the selected temperature range).
A
Amax
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
9.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 5.0 V. They are
A
DD
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range.
9.1.3
9.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
Figure 7. Pin loading conditions
670ꢆ$ꢀ3,1
ꢌꢋꢀS)
06Yꢍꢎꢎꢐꢃ9ꢁ
DocID025118 Rev 5
53/106
103
Electrical characteristics
STM8AF6213/23/23A/26
9.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
Figure 8. Pin input voltage
670ꢆ$ꢀ3,1
9,1
06Yꢍꢎꢎꢐꢎ9ꢁ
9.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 22. Voltage characteristics
Symbol
Ratings
Min
Max
6.5
Unit
(1)
V
DDx - VSS
Supply voltage (including VDDA and VDDIO
Input voltage on true open drain pins (2)
Input voltage on any other pin(2)
)
-0.3
V
VSS - 0.3
6.5
VIN
V
VSS - 0.3 VDD + 0.3
|VDDx - VDD
|
Variations between different power pins
-
-
50
50
mV
|VSSx - VSS
|
Variations between all the different ground pins
see Absolute maximum ratings
(electrical sensitivity) on
page 90
VESD
Electrostatic discharge voltage
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
54/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Symbol
Electrical characteristics
Table 23. Current characteristics
Ratings
Max.(1)
Unit
IVDD
IVSS
Total current into VDD power lines (source)(2)
Total current out of VSS ground lines (sink)(2)
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin
Injected current on RST pin
100
80
20
IIO
-20
mA
±4
(3) (4)
IINJ(PIN)
Injected current on OSCIN pin
±4
±4
Injected current on any other pin(5)
(3)
∑IINJ(TOT)
Total injected current (sum of all I/O and control pins)(5)
±20
1. Data based on characterization results, not tested in production.
2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected.
4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
∑IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of
the positive and negative injected currents (instantaneous values). These results are based on
characterization with ∑IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 24. Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
TJ
Storage temperature range
-65 to 150
150
°C
Maximum junction temperature
Table 25. Operating lifetime (OLF)
Symbol
Ratings
Value
Unit
OLF
Conforming to AEC-Q100
-40 to 150
°C
DocID025118 Rev 5
55/106
103
Electrical characteristics
STM8AF6213/23/23A/26
9.3
Operating conditions
Table 26. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fCPU
VDD
Internal CPU clock frequency
Standard operating voltage
-
-
0
16
MHz
V
3.0
5.5
CEXT: capacitance of external
capacitor
-
470
3300
nF
(1)
VCAP
ESR of external capacitor
ESL of external capacitor
-
-
-
0.3
15
45
Ω
at 1 MHz(2)
TSSOP20
LQFP32
nH
Power dissipation at
TA = 85 °C for suffix A version,
TA = 125 °C for suffix C version,
TA = 150 °C for suffix D version
(3)
PD
mW
-
83
Ambient temperature for suffix A
version
-40
-40
-40
85
Ambient temperature for suffix C
version
Maximum power
dissipation
TA
125
150
Ambient temperature for suffix D
version
°C
Suffix A
Suffix C
Suffix D
-40
-40
-40
90
TJ
Junction temperature range
130
155
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
3. See Section 10.3: Thermal characteristics.
56/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 9. f
versus V
DD
CPUmax
I&38ꢀꢈ0+]ꢉ
ꢅꢊ
)XQFWLRQDOLW\ꢀ
QRWꢀ
JXDUDQWHHGꢀLQꢀ
WKLVꢀDUHD
ϭϲ
ϭϮ
ϴ
)XQFWLRQDOLW\ꢀJXDUDQWHHG
#7$ꢀꢂꢊꢋꢀWRꢀꢁꢌꢋꢀ&ꢀꢀ
ϰ
Ϭ
ꢊꢄꢋ
6XSSO\ꢀYROWDJHꢀꢈ9ꢉ
ꢍꢄꢋ
ꢌꢄꢋ
ꢌꢄꢌ
06Yꢍꢎꢎꢐꢆ9ꢁ
Table 27. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Max
Unit
Typ
2(1)
VDD rise time rate
VDD fall time rate(2)
Reset release delay
-
-
-
-
tVDD
µs/V
ms
2(1)
-
-
tTEMP
VIT+
VDD rising
1.7
Power-on reset
threshold(3)
2.6(1)
2.5
-
-
-
-
2.7
2.85
V
Brown-out reset
threshold
2.8(1)
-
VIT-
2.65
70(1)
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production
2. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum operating voltage (VDD min) when the tTEMP delay has elapsed.
3. There is inrush current into VDD present after device power on to charge CEXT capacitor. This inrush energy
depends from CEXT capacitor value. For example, a CEXT of 1μF requires Q=1 μF x 1.8V = 1.8 μC.
DocID025118 Rev 5
57/106
103
Electrical characteristics
STM8AF6213/23/23A/26
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 26. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 10. External capacitor C
EXT
(6/
&
(65
5/HDN
06Yꢍꢃꢊꢆꢆ9ꢁ
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
9.3.2
Supply current characteristics
The current consumption is measured as described in Section 4.3: Interrupt controller.
Total current consumption in run mode
The MCU is placed under the following conditions:
All I/O pins in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled (clock stopped by peripheral clock gating registers) except
if explicitly mentioned.
Subject to general operating conditions for V and T .
DD
A
Unless otherwise specified, data are based on characterization results, and not tested in
production.
Table 28. Total current consumption with code execution in run mode at V = 5 V
DD
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Max
Unit
2.3
2
-
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
2.35
2(1)
-
1.7
0.86
0.7
Supply current
in run mode,
code executed
from RAM
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
IDD(RUN)
mA
fCPU = fMASTER/128= 125 kHz
0.87
fCPU = fMASTER/128=
15.625 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.41
0.58
0.55
fCPU = fMASTER = 28 kHz
58/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Table 28. Total current consumption with code execution in run mode at V = 5 V (continued)
DD
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Max
Unit
4.5
4.3
-
Supply current
in run mode,
code executed
from Flash
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
4.75
4.5(1)
2(1)
3.7
fCPU = fMASTER = 2 MHz
HSI RC osc. (16 MHz/8)(2)
0.84
0.72
IDD(RUN)
mA
Supply current
in run mode,
code executed
from Flash
fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz)
0.9
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)
15.625 kHz
0.46
0.42
0.58
0.57
f
CPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
1. Tested in production.
2. Default clock configuration measured with all peripherals off.
Table 29. Total current consumption with code execution in run mode at V = 3.3 V
DD
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ Max(1) Unit
1.8
2
-
2.3
2
fCPU = fMASTER =16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.5
0.81
0.7
Supply current
in run mode,
code executed
from RAM
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
-
fCPU = fMASTER/128 = 125 kHz
0.87
fCPU = fMASTER/ 128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
0.46
0.58
fCPU = fMASTER =128 kHz
fCPU = fMASTER = 16 MHz
fCPU = fMASTER =2 MHz
LSI RC osc. (128 kHz)
0.41
4
0.55
-
IDD(RUN)
mA
HSE crystal osc. (16 MHz)
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
3.9
4.7
4.5
1.05
0.9
3.7
Supply current
in run mode,
code executed
from Flash
HSI RC osc. (16 MHz/8)(2)
0.84
0.72
f
CPU = fMASTER/ 128 = 125 kHz HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
LSI RC osc. (128 kHz)
0.46
0.42
0.58
0.57
f
CPU = fMASTER =128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
DocID025118 Rev 5
59/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Total current consumption in wait mode
Unless otherwise specified, data based are on characterization results, and not tested in
production.
Table 30. Total current consumption in wait mode at V = 5 V
DD
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ
Max
Unit
1.6
1.1
-
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.3
0.89
0.7
1.5(1)
Supply current
in wait mode
IDD(WFI)
mA
fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz)
0.88
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)(2)
15.625 kHz
0.45
0.4
0.57
0.54
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
1. Tested in production.
2. Default clock configuration measured with all peripherals off.
Table 31. Total current consumption in wait mode at V = 3.3 V
DD
Symbol
Parameter
Conditions
HSE crystal osc. (16 MHz)
Typ Max(1) Unit
1.1
1.1
-
fCPU = fMASTER = 16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
1.3
1.1
0.88
0.89
0.7
Supply current
in wait mode
IDD(WFI)
mA
f
CPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz)
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
LSI RC osc. (128 kHz)
0.45
0.4
0.57
0.54
fCPU = fMASTER = 128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
60/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Total current consumption in active halt mode
Table 32. Total current consumption in active halt mode at V = 5 V
DD
Conditions
Max
at
85°C 125°C
Max
at
Main
Maxat
150°C
Symbol
Parameter
Typ
Unit
voltage
regulator
(MVR)(1)
Flash
Clock source
mode(2)
HSE crystal
osc. (16 MHz)
1030
200
970
150
66
-
-
-
Operating
mode
LSI RC osc.
(128 kHz)
260
-
300
-
-
On
HSE crystal
osc. (16 MHz)
-
Supply current in
active halt mode
Power-down
mode
IDD(AH)
µA
LSI RC osc.
(128 kHz)
200
85
20
230
140
40
-
200
-
Operating
mode
LSI RC osc.
(128 kHz)
Off
Power-down LSI RC osc.
mode (128 kHz)
10
1. Configured by the REGAH bit in the CLK_ICKR register.
2. Configured by the AHALT bit in the FLASH_CR1 register.
Table 33. Total current consumption in active halt mode at V = 3.3 V
DD
Conditions
Main
Max at
Max at
125°C
voltage
regulato
r
Symbol
Parameter
Typ
Unit
85°C(1)
Flash
Clock source
mode(3)
(MVR)(2)
HSE crystal
osc. (16 MHz)
550
200
970
150
66
-
-
Operating
mode
LSI RC osc.
(128 kHz)
260
-
290
-
On
HSE crystal
osc. (16 MHz)
Supply current in
active halt mode
Power-
down mode
IDD(AH)
µA
LSI RC osc.
(128 kHz)
200
80
18
230
105
35
Operating
mode
LSI RC osc.
(128 kHz)
Off
Power-
LSI RC osc.
down mode (128 kHz)
10
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
DocID025118 Rev 5
61/106
103
Electrical characteristics
STM8AF6213/23/23A/26
3. Configured by the AHALT bit in the FLASH_CR1 register.
Total current consumption in halt mode
Table 34. Total current consumption in halt mode at V = 5 V
DD
Max at
85°C
Max at
125°C
Max at
150°C
Symbol
Parameter
Conditions
Typ
Unit
Flash in operating mode,
HSI clock after wakeup
63
75
105
-
Supply current in halt
mode
IDD(H)
µA
Flash in power-down mode,
HSI clock after wakeup
6.0
20(1)
55(1)
80(1)
1. Tested in production.
Table 35. Total current consumption in halt mode at V = 3.3 V
DD
Max at
Max at
Symbol
Parameter
Conditions
Typ
Unit
85°C(1)
125°C(1)
Flash in operating mode,
HSI clock after wakeup
60
75
100
Supply current in halt
mode
IDD(H)
µA
Flash in power-down mode,
HSI clock after wakeup
4.5
17
30
1. Data based on characterization results, not tested in production.
Low-power mode wakeup times
Table 36. Wakeup times
Conditions
Symbol
Parameter
Typ
Max(1)
See (3)
-
Unit
Wakeup time
0 to 16 MHz
-
tWU(WFI) from wait mode
to run mode(2)
fCPU= fMASTER= 16 MHz
0.56
1(6)
3(6)
2(6)
MVR voltage
regulator on(4)
Wakeup time
tWU(AH) active halt mode
to run mode(2)
Flash in
-
-
-
-
HSI (after
wakeup)
operating
µs
48(6)
50(6)
52
mode(5)
MVR voltage
regulator off
Wakeup time
tWU(H) from halt mode to
run mode(2)
Flash in operating mode(5)
Flash in power-down mode(5)
54
-
1. Data guaranteed by design, not tested in production.
2. Measured from interrupt event to interrupt vector fetch.
3. tWU(WFI) = 2 x 1/fMASTER+ 67 x 1/fCPU
.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
62/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Total current consumption and timing in forced reset state
Table 37. Total current consumption and timing in forced reset state
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
VDD= 5 V
400
300
-
-
IDD(R)
Supply current in reset state(2)
µA
VDD= 3.3 V
Reset pin release to vector
fetch
tRESETBL
-
-
150
µs
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS
.
Current consumption for on-chip peripherals
Subject to general operating conditions for V and T .
DD
A
HSI internal RC/f
= f
= 16 MHz, V = 5 V
CPU
MASTER DD
Table 38. Peripheral current consumption
Parameter
Symbol
Typ
210
130
50
Unit
IDD(TIM1) TIM1 supply current(1)
TIM5 supply current(1)
TIM6 supply current(1)
IDD(TIM5)
IDD(TIM6)
IDD(UART1) LINUART supply current(2)
120
45
µA
SPI supply current(2)
I2C supply current(2)
ADC1 supply current(3)
IDD(SPI)
IDD(I2C)
65
IDD(ADC1)
1000
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
DocID025118 Rev 5
63/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Current consumption curves
The following figures show typical current consumption measured with code executing in
RAM.
Figure 11. Typ I
vs. V HSE user external clock, f
= 16 MHz
CPU
DD(RUN)
DD
Figure 12. Typ I
vs. f
HSE user external clock, V = 5 V
CPU DD
DD(RUN)
64/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 13. Typ I
vs. V HSEI RC osc., f
= 16 MHz
DD(RUN)
DD
CPU
Figure 14. Typ I
vs. V HSE user external clock, f
= 16 MHz
DD(WFI)
DD
CPU
DocID025118 Rev 5
65/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 15. Typ I
vs. f
HSE user external clock, V = 5 V
CPU DD
DD(WFI)
Figure 16. Typ I
vs. V HSI RC osc., f = 16 MHz
CPU
DD(WFI)
DD
66/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
9.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for V and T .
DD
A
Table 39. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
User external clock source
frequency
fHSE_ext
-
0
-
16
MHz
OSCIN input pin high level
voltage
(1)
VHSEH
-
0.7 x VDD
VSS
-
-
-
VDD + 0.3 V
0.3 x VDD
+1
V
OSCIN input pin low level
voltage
(1)
VHSEL
-
OSCIN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
-1
µA
1. Data based on characterization results, not tested in production.
Figure 17. HSE external clock source
9
9
+6(+
+6(/
I
+6(
([WHUQDOꢀFORFN
VRXUFH
26&,1
670ꢆ
06ꢍꢃꢊꢆꢐ9ꢁ
DocID025118 Rev 5
67/106
103
Electrical characteristics
STM8AF6213/23/23A/26
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 40. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
External high-speed oscillator
frequency
fHSE
RF
-
-
-
1
-
-
220
-
16
-
MHz
k
Feedback resistor
Recommended load
capacitance(2)
C(1)
-
20
pF
6 (startup)
1.6 (stabilized)(3)
C = 20 pF,
fOSC = 16 MHz
-
-
HSE oscillator power
consumption
IDD(HSE)
mA
6 (startup)
C = 10 pF,
fOSC = 16 MHz
-
5
-
-
-
1.2 (stabilized)(3)
gm
Oscillator transconductance
Startup time
-
-
-
mA/V
ms
VDD is
stabilized
(4)
tSU(HSE)
1
1. C is approximately equivalent to 2 x crystal CLOAD
.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to the crystal manufacturer for more details.
3. Data based on characterization results, not tested in production.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) until a stabilized 16 MHz oscillation is
reached. The value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
5
P
I+6(ꢀWRꢀꢀFRUH
&
2
5)
/
P
P
&
&
/ꢁ
&
26&,1
J
P
5HVRQDWRU
&XUUHQWꢀFRQWURO
5HVRQDWRU
26&287
/ꢅ
670ꢆ
06Yꢍꢎꢎꢐꢐ9ꢁ
68/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
HSE oscillator critical gm formula
The crystal characteristics have to be checked with the following formula:
g
m » gmcrit
where g
can be calculated with the crystal parameters as follows:
mcrit
gmcrit = 2 fHSE2 Rm2Co + C2
R : Notional resistance (see crystal specification)
m
L : Notional inductance (see crystal specification)
m
C : Notional capacitance (see crystal specification)
m
Co: Shunt capacitance (see crystal specification)
C
= C = C: Grounded external capacitance
L1
L2
9.3.4
Internal clock sources and timing characteristics
Subject to general operating conditions for V and T .
DD
A
High speed internal RC oscillator (HSI)
Table 41. HSI oscillator characteristics
Symbol
Parameter
Frequency
Conditions
Min
Typ
Max
Unit
fHSI
-
-
16
-
-
MHz
Trimmed by the application
for any VDD and TA
conditions
-1(1)
1(1)
HSI oscillator user
trimming accuracy
-0.5(1)
-
-
0.5(1)
ACCHS
3.0 V VDD 5.5 V,
-40 °C TA 150 °C
%
-5
5
HSI oscillator accuracy
(factory calibrated)
3.0 V VDD 5.5 V,
-40 °C TA 125 °C
-3(2)
-
-
3(2)
2(3)
HSI oscillator wakeup
time
tsu(HSI)
-
-
-
-
µs
HSI oscillator power
consumption
IDD(HSI)
170
250(4)
µA
1. Depending on option byte setting (OPT3 and NOPT3)
2. These values are guaranteed for STM8AF62xxIxx order codes only.
3. Guaranteed by characterization, not tested in production
4. Data based on characterization results, not tested in production.
DocID025118 Rev 5
69/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for V and T .
DD
A
Table 42. LSI oscillator characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSI
Frequency
-
-
-
110(1)
128
150(1)
kHz
µs
tsu(LSI) LSI oscillator wakeup time
IDD(LSI) LSI oscillator power consumption
1. Tested in production.
-
-
-
7
-
5
µA
9.3.5
Memory characteristics
RAM and hardware registers
Table 43. RAM and hardware registers
Symbol
Parameter
Data retention mode(1)
Conditions
Min
Unit
(2)
VRM
Halt mode (or reset)
VIT-max
V
1. Minimum supply voltage without losing the data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to the operating conditions for the value of VIT-max
Flash program memory/data EEPROM memory
General conditions: T = -40 to 150 °C.
A
Table 44. Flash program memory/data EEPROM memory
Symbol
Parameter
Conditions
Min Typ Max
Unit
Operating voltage
(all modes, execution/write/erase)
3.0
2.6
-
-
5.5
5.5
f
CPU is 0 to 16 MHz
VDD
V
with 0 ws
Operating voltage
(code execution)
Standard programming time (including
erase) for byte/word/block
(1 byte/4 byte/64 byte)
-
-
6.0
6.6
tprog
ms
Fast programming time for 1 block
(64 byte)
-
-
-
-
3.0
3.0
3.3
3.3
tERASE Erase time for 1 block (64 byte)
70/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Table 45. Flash program memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
-
-40
150
°C
Flash program memory endurance
(erase/write cycles)(1)
NWE
TA = 25 °C
1000
-
cycles
years
TA = 25 °C
TA = 55 °C
40
20
-
-
tRET
Data retention time
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a
write/erase operation addresses a single byte.
Table 46. Data memory
Symbol
Parameter
Condition
Min
Max
Unit
TWE
Temperature for writing and erasing
-
-40
150
°C
Data memory endurance(1)
(erase/write cycles)
TA = 25 °C
300 k
-
-
-
-
NWE
cycles
years
TA = -40°C to 125 °C 100 k(2)
TA = 25 °C
TA = 55 °C
40(3)
tRET
Data retention time
20(2)(3)
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a
write/erase operation addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is
available in a separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
DocID025118 Rev 5
71/106
103
Electrical characteristics
STM8AF6213/23/23A/26
9.3.6
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 47. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH
Input low level voltage
Input high level voltage
Hysteresis(1)
-0.3 V
-
-
0.3 x VDD
V
-
0.7 x VDD
VDD + 0.3 V
Vhys
Rpu
-
700
55
-
mV
Pull-up resistor
VDD = 5 V, VIN = VSS
35
80
k
Fast I/Os
Load = 50 pF
-
-
-
-
35(2)
125(2)
20(2)
Standard and high sink I/Os
Load = 50 pF
Rise and fall time
(10% - 90%)
tR, tF
ns
Fast I/Os
Load = 20 pF
Standard and high sink I/Os
Load = 20 pF
50(2)
Digital input pad leakage
current
Ilkg
VSS VIN VDD
-
-
-
-
-
-
-
-
±1(3)
µA
nA
µA
VSS VIN VDD
-40 °C < TA < 125 °C
±250(3)
±500(3)
±1(3)
Analog input pad leakage
current
Ilkg ana
VSS VIN VDD
-40 °C < TA < 150 °C
Leakage current in
adjacent I/O(2)
Ilkg(inj)
Injection current ±4 mA
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
2. Data based on characterization results, not tested in production.
3. Guaranteed by design.
72/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 19. Typical V and V vs V @ 4 temperatures
IL
IH
DD
Figure 20. Typical pull-up resistance R vs V @ 4 temperatures
PU
DD
DocID025118 Rev 5
73/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 21. Typical pull-up current I vs V @ 4 temperatures
pu
DD
Table 48. Output driving current (standard ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8
pins sunk
IIO= 10 mA,
VDD = 5 V
-
2.0
VOL
Output low level with 4
pins sunk
IIO = 4 mA,
VDD = 3.3 V
-
1.0(1)
V
Output high level with 8 IIO = 10 mA,
2.8
-
-
pins sourced
VDD = 5 V
VOH
Output high level with 4
pins sourced
IIO = 4 mA,
VDD = 3.3 V
2.1(1)
1. Data based on characterization results, not tested in production.
Table 49. Output driving current (true open drain ports)
Symbol
Parameter
Conditions
Max
Unit
IIO= 10 mA, VDD = 5 V
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
1.0
VOL
Output low level with 2 pins sunk
1.5(1)
2.0(1)
V
1. Data based on characterization results, not tested in production.
74/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Table 50. Output driving current (high sink ports)
Symbol
Parameter
Conditions
Min
Max
Unit
Output low level with 8
pins sunk
IIO= 10 mA, VDD = 5 V
-
-
0.8
VOL
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
1.0(1)
1.5(1)
Output low level with 4
pins sunk
V
Output high level with
8 pins sourced
I
IO = 10 mA, VDD = 5 V
4.0
-
VOH
IIO = 10 mA, VDD = 3.3 V
IIO = 20 mA, VDD = 5 V
2.1(1)
3.3(1)
-
-
Output high level with
4 pins sourced
1. Data based on characterization results, not tested in production.
Figure 22. Typ. V @ V = 5 V (standard ports)
OL
DD
Figure 23. Typ. V @ V = 3.3 V (standard ports)
OL
DD
DocID025118 Rev 5
75/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 24. Typ. V @ V = 5 V (true open drain ports)
OL
DD
Figure 25. Typ. V @ V = 3.3 V (true open drain ports)
OL
DD
Figure 26. Typ. V @ V = 5 V (high sink ports)
OL
DD
76/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 27. Typ. V @ V = 3.3 V (high sink ports)
OL
DD
Figure 28. Typ. V - V @ V = 5 V (standard ports)
DD
OH
DD
Figure 29. Typ. V - V @ V = 3.3 V (standard ports)
DD
OH
DD
DocID025118 Rev 5
77/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 30. Typ. V - V @ V = 5 V (high sink ports)
DD
OH
DD
Figure 31. Typ. V - V @ V = 3.3 V (high sink ports)
DD
OH
DD
78/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
9.3.7
Reset pin characteristics
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 51. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST) NRST input low level voltage(1)
-
-0.3
-
0.3 x VDD
VDD + 0.3
VIH(NRST) NRST input high level voltage(1) IOL= 2 mA
-
-
0.7 x VDD
V
VOL(NRST) NRST output low level voltage(1)
RPU(NRST) NRST pull-up resistor(2)
-
-
-
-
30
-
0.5
80
75
55
-
k
ns
µs
tIFP(NRST) NRST input filtered pulse(3)
NRST Input not filtered pulse
tINFP(NRST)
duration(3)
-
-
500
20
-
-
-
-
tOP(NRST) NRST output pulse(3)
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor.
3. Data guaranteed by design, not tested in production.
Figure 32. Typical NRST V and V vs V @ 4 temperatures
IL
IH
DD
DocID025118 Rev 5
79/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 33. Typical NRST pull-up resistance vs V @ 4 temperatures
DD
Figure 34. Typical NRST pull-up current vs V @ 4 temperatures
DD
The reset network shown in Figure 35 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below V
max (see Table 51:
IL(NRST)
NRST pin characteristics), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external
circuitry, attention must be taken to the charge/discharge time of the external capacitor to
fulfill the external devices reset timing conditions. Minimum recommended capacity is
100 nF.
80/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 35. Recommended reset pin protection
670ꢆ$
9''
538
([WHUQDOꢀ
UHVHWꢀFLUFXLWꢀ
ꢈRSWLRQDOꢉ
,QWHUQDOꢀUHVHW
1567
)LOWHU
ꢋꢄꢁꢀȝ)
06Yꢍꢆꢍꢎꢁ9ꢁ
SPI serial peripheral interface
9.3.8
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
MASTER
DD
conditions. t
= 1/f
.
MASTER
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 52. SPI characteristics
Symbol
Parameter
Conditions(1)
Min
Max
Unit
Master mode
0
0
8
6
fSCK
1/tc(SCK)
SPI clock frequency
MHz
Slave mode
tr(SCK
tf(SCK)
)
Capacitive load:
C = 30 pF
SPI clock rise and fall time
-
25
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 * tMASTER
70
-
-
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
SCK high and low time
Data input setup time
Master mode
tSCK/2 - 15 tSCK/2 + 15
(2)
(2)
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
5
5
-
tsu(MI)
tsu(SI)
(2)
-
ns
(2)
7
-
th(MI)
th(SI)
Data input hold time
(2)
10
-
-
(2)(3)
ta(SO)
Data output access time
Data output disable time
3* tMASTER
-
(2)(4)
tdis(SO)
25
Slave mode
(after enable edge)
(2)
(2)
tv(SO)
Data output valid time
Data output valid time
-
-
65
36
Master mode
(after enable edge)
tv(MO)
DocID025118 Rev 5
81/106
103
Electrical characteristics
Symbol
STM8AF6213/23/23A/26
Table 52. SPI characteristics (continued)
Parameter Min
Conditions(1)
Slave mode
Max
Unit
(2)
th(SO)
27
-
(after enable edge)
Data output hold time
ns
Master mode
(after enable edge)
(2)
th(MO)
11
-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z.
Figure 36. SPI timing diagram - slave mode and CPHA = 0
166ꢀLQSXW
W68ꢈ166ꢉ
WKꢈ166ꢉ
WFꢈ6&.ꢉ
&3+$ ꢋ
&32/ ꢋ
WZꢈ6&.+ꢉ
WZꢈ6&./ꢉ
&3+$ ꢋ
&32/ ꢁ
WUꢈ6&.ꢉ
W9ꢈ62ꢉ
WKꢈ62ꢉ
WGLVꢈ62ꢉ
WIꢈ6&.ꢉ
WDꢈ62ꢉ
0,62
287387
06%ꢀ287
%,7ꢃꢀ287
/6%ꢀ287
WVXꢈ6,ꢉ
026,
,1387
06%ꢀ,1
%,7ꢁꢀ,1
/6%ꢀ,1
WKꢈ6,ꢉ
DLꢁꢊꢁꢍꢊF
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD
.
82/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 37. SPI timing diagram - slave mode and CPHA = 1
166ꢀLQSXW
W68ꢈ166ꢉ
WKꢈ166ꢉ
WFꢈ6&.ꢉ
&3+$ ꢁ
&32/ ꢋ
&3+$ ꢁ
&32/ ꢁ
WZꢈ6&.+ꢉ
WZꢈ6&./ꢉ
WUꢈ6&.ꢉ
WGLVꢈ62ꢉ
WKꢈ62ꢉ
WYꢈ62ꢉ
WDꢈ62ꢉ
WIꢈ6&.ꢉ
0,62
06%ꢀ287
06%ꢀ,1
%,7ꢃꢀ287
/6%ꢀ287
287387
WKꢈ6,ꢉ
WVXꢈ6,ꢉ
026,
,1387
/6%ꢀ,1
%,7ꢀꢁꢀ,1
DLꢁꢊꢁꢍꢌE
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
(1)
Figure 38. SPI timing diagram - master mode
+LJK
166ꢀLQSXW
W
Fꢈ6&.ꢉ
&3+$ ꢋ
&32/ ꢋ
&3+$ ꢋ
&32/ ꢁ
&3+$ ꢁ
&32/ ꢋ
&3+$ ꢁ
&32/ ꢁ
W
W
W
W
Zꢈ6&.+ꢉ
Zꢈ6&./ꢉ
Uꢈ6&.ꢉ
Iꢈ6&.ꢉ
W
VXꢈ0,ꢉ
0,62
,1387
%,7ꢃꢀ,1
/6%ꢀ,1
06%ꢀ,1
W
Kꢈ0,ꢉ
026,
287387
%,7ꢁꢀ287
/6%ꢀ287
06%ꢀ287
W
W
Kꢈ02ꢉ
Yꢈ02ꢉ
DLꢁꢊꢁꢍꢃF
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD
.
DocID025118 Rev 5
83/106
103
Electrical characteristics
2
STM8AF6213/23/23A/26
9.3.9
I C interface characteristics
2
Table 53. I C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min(2)
Max(2)
Min(2) Max(2)
tw(SCLL) SCL clock low time
tw(SCLH) SCL clock high time
tsu(SDA) SDA setup time
4.7
4.0
-
1.3
0.6
-
-
-
µs
-
-
250
100
0(3)
0(4)
900(3)
th(SDA)
SDA data hold time
3450
tr(SDA)
tr(SCL)
ns
µs
SDA and SCL rise time
-
1000
300
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
-
300
th(STA)
START condition hold time
4.0
4.7
4.0
-
-
-
0.6
0.6
0.6
-
-
-
tsu(STA) Repeated START condition setup time
tsu(STO) STOP condition setup time
STOP to START condition time
tw(STO:STA)
(bus free)
4.7
-
1.3
-
Pulse width of spikes suppressed by
the input filter
tSP
0
-
50(5)
400
0
-
50
ns
Cb
Capacitive load for each bus line
400
pF
1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)
Data based on standard I2C protocol requirement, not tested in production
2.
The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
3.
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
5. The minimum width of the spikes filtered by the analog filter is above tSP(max)
84/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Figure 39. Typical application with I2C bus and timing diagram
9
9
''
''
ꢊꢄꢎꢀN
670ꢆ
ꢊꢄꢎꢀN
ꢁꢋꢋꢀ
ꢁꢋꢋꢀ
6'$
6&/
,ð&ꢀEXV
67$57ꢀ5(3($7('
67$57
67$57
W
VXꢈ67$ꢉ
6'$
W
Uꢈ6'$ꢉ
W
W
Iꢈ6'$ꢉ
VXꢈ6'$ꢉ
W
VXꢈ67$ꢑ672ꢉ
6723
W
W
W
Zꢈ6&//ꢉ
Kꢈ6'$ꢉ
Kꢈ67$ꢉ
6&/
W
W
W
VXꢈ672ꢉ
Uꢈ6&/ꢉ
W
Iꢈ6&/ꢉ
Zꢈ6&/+ꢉ
DLꢁꢎꢊꢐꢋ9ꢅ
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
.
DocID025118 Rev 5
85/106
103
Electrical characteristics
STM8AF6213/23/23A/26
9.3.10
10-bit ADC characteristics
Subject to general operating conditions for V , f
, and T unless otherwise
A
DD MASTER
specified.
Table 54. ADC characteristics
Symbol
Parameter
Conditions
Min
Max
4
Unit
Typ
V
DD = 3 to 5.5 V
1
1
-
-
fADC
ADC clock frequency
MHz
VDD = 4.5 to 5.5 V
-
6
Conversion voltage
range(1)
VSS
VDD
VAIN
VBGREF
CADC
-
1.22
3
V
V
Internal bandgap
reference voltage
1.19(2)
-
1.25(2)
-
V
DD = 3 to 5.5 V
Internal sample and hold
capacitor
-
pF
fADC = 4MHz
-
-
-
0.75
0.5
7
-
-
-
(1)
tS
Minimum sampling time
fADC = 6 MHz
-
µs
tSTAB Wakeup time from standby
f
ADC = 4 Hz
3.5
2.33
14
Minimum total conversion
tCONV time including sampling
time, 10-bit resolution
µs
fADC = 6 MHz
-
1/fADC
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
2. Tested in production.
86/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Table 55. ADC accuracy with RAIN < 10 kΩ, V = 5 V
DD
Max(1)
3.5
4
Symbol
Parameter
Conditions
Typ
Unit
fADC = 2 MHz
fADC = 4 MHz
fADC = 6 MHz
fADC = 2 MHz
1.6
2.2
2.4
1.1
1.5
1.8
1.5
2.1
2.2
0.7
0.7
0.7
0.6
0.8
0.8
|ET|
Total unadjusted error(2)
4.5
2.5
3
Offset error(2)
f
f
ADC = 4 MHz
ADC = 6 MHz
|EO|
|EG|
|ED|
|EL|
3
fADC = 2 MHz
ADC = 4 MHz
3
Gain error(2)
3
LSB
f
fADC = 6 MHz
fADC = 2 MHz
4
1.5
1.5
1.5
1.5
2
Differential linearity error(2)
Integral linearity error(2)
f
f
ADC = 4 MHz
ADC = 6 MHz
fADC = 2 MHz
ADC = 4 MHz
fADC = 6 MHz
f
2
1. Max value is based on characterization, not tested in production.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
Table 56. ADC accuracy with RAIN < 10 kΩ, V = 3.3 V
DD
Max(1)
3.5
4
Symbol
Parameter
Conditions
Typ
Unit
f
f
f
f
ADC = 2 MHz
ADC = 4 MHz
ADC = 2 MHz
ADC = 4 MHz
1.6
1.9
1
|ET|
Total unadjusted error
2.5
2.5
3
|EO|
|EG|
|ED|
|EL|
Offset error
1.5
1.3
2
fADC = 2 MHz
Gain error
LSB
f
f
f
f
f
ADC = 4 MHz
ADC = 2 MHz
ADC = 4 MHz
ADC = 2 MHz
ADC = 4 MHz
3
0.7
0.7
0.6
0.8
1
Differential linearity error
Integral linearity error
1.5
1.5
2
1. Max value is based on characterization, not tested in production.
DocID025118 Rev 5
87/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Figure 40. ADC accuracy characteristics
E
G
1023
1022
1021
V
– V
DDA
SSA
1LSB
= ----------------------------------------
IDEAL
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
(1)
E
O
E
L
E
D
1 LSB
IDEAL
7
0
V
1
2
3
4
5
6
1021102210231024
V
DDA
SSA
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves.
E
O = Offset error: Deviation between the first actual transition and the first ideal one.
EG = Gain error: Deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: Maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation
line.
Figure 41. Typical application with ADC
9''
^dDϴꢀ
97
ꢋꢄꢃꢀ9
9$,1
5$,1
ꢀ/Edž
ꢁꢋꢂELWꢀ$ꢇ'
FRQYHUVLRQ
97
ꢋꢄꢃꢀ9
&
&
$,1
, ꢀꢁꢀ$
/ꢀꢀꢀ
$'&
06Yꢍꢆꢍꢎꢅ9ꢁ
1. Legend: RAIN = external resistance, CAIN = capacitors, Csamp = internal sample and hold capacitor.
88/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
9.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
FESD: Functional electrostatic discharge (positive and negative) is applied on all pins
of the device until a functional disturbance occurs. This test conforms with the IEC
61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
DD
SS
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see the application note reference AN1015).
Table 57. EMS data
Symbol
Parameter
Conditions
Level/class
VDD 3.3 V, TA25 °C,
fMASTER 16 MHz (HSI clock),
Conforms to IEC 61000-4-2
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
2/B(1)
VFESD
VDD3.3 V, TA25 °C,
Fast transient voltage burst limits to be
VEFTB applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
fMASTER 16 MHz (HSI clock),
Conforms to IEC 61000-4-4
4/A
1. Data obtained with HSI clock configuration, after applying hardware recommendations described in
AN2860 (EMC guidelines for STM8S microcontrollers).
DocID025118 Rev 5
89/106
103
Electrical characteristics
STM8AF6213/23/23A/26
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC 61967-2 which specifies the board and the loading of each pin.
Table 58. EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol
Parameter
Unit
Monitored
frequency band
General conditions
16 MHz/ 16 MHz/
8 MHz 16 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
—
5
4
5
5
VDD 5 V,
TA 25 °C,
LQFP32 package
conforming to
IEC 61967-2
Peak level
EMI level
dBµV
level
SEMI
5
5
2.5
2.5
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, DLU and LU) using specific measurement methods,
the product is stressed to determine its performance in terms of electrical sensitivity. For
more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (one positive then one negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model
can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A
standard. For more details, refer to the application note AN1181.
Table 59. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Class
Unit
value(1)
Electrostatic discharge voltage TA 25°C, conforming to
VESD(HBM)
VESD(CDM)
VESD(MM)
3A
3
4000
(Human body model)
JESD22-A114
Electrostatic discharge voltage
(Charge device model)
TA 25°C, conforming to
500
200
V
JESD22-C101
Electrostatic discharge voltage
(Machine model)
TA 25°C, conforming to
B
JESD22-A115
1. Data based on characterization results, not tested in production
90/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage (applied to each power supply pin),
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 60. Electrical sensitivities
Class(1)
Symbol
Parameter
Conditions
TA 25 °C
TA 85 °C
TA 125 °C
TA 150 °C
LU
Static latch-up class
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
DocID025118 Rev 5
91/106
103
Package information
STM8AF6213/23/23A/26
10
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
10.1
LQFP32 package information
Figure 42. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢉꢊꢆꢈ MM
'!5'% 0,!.%
CCC
#
+
$
$ꢀ
$ꢁ
,
,ꢀ
ꢆꢇ
ꢀꢅ
ꢀꢄ
ꢆꢈ
ꢁꢆ
ꢃ
0). ꢀ
)$%.4)&)#!4)/.
ꢀ
ꢂ
E
ꢀ7@.&@7ꢁ
1. Drawing is not to scale.
92/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Package information
Table 61. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data
millimeters
inches(1)
Symbol
Min
Typ
Max
Min
Typ
Max
A
A1
A2
b
-
0.050
1.350
0.300
0.090
8.800
6.800
-
-
1.600
0.150
1.450
0.450
0.200
9.200
7.200
-
-
0.0020
0.0531
0.0118
0.0035
0.3465
0.2677
-
-
0.0630
0.0059
0.0571
0.0177
0.0079
0.3622
0.2835
-
-
-
1.400
0.370
-
0.0551
0.0146
-
c
D
9.000
7.000
5.600
9.000
7.000
5.600
0.800
0.600
1.000
3.5°
0.3543
0.2756
0.2205
0.3543
0.2756
0.2205
0.0315
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID025118 Rev 5
93/106
103
Package information
STM8AF6213/23/23A/26
Figure 43. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
ꢉꢊꢂꢉ
ꢀꢊꢆꢉ
ꢁꢇ
ꢂꢆ
ꢁꢀ
ꢂꢅ
ꢉꢊꢈꢉ
ꢋꢄꢍꢋ
ꢅꢊꢁꢉ
ꢄꢊꢀꢉ
ꢃꢊꢅꢉ
ꢅꢊꢁꢉ
ꢈꢁ
ꢄ
ꢃ
ꢂ
ꢀꢊꢆꢉ
ꢄꢊꢀꢉ
ꢃꢊꢅꢉ
ꢈ6?&0?6ꢆ
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 44. LQFP32 marking example (package top view)
3URGXFWꢀ
LGHQWLILFDWLRQ ꢈꢁꢉ
999999
999999
'DWHꢀFRGH
6WDQGDUGꢀ67ꢀORJR
:
88
5HYLVLRQꢀFRGH
3LQꢀꢁꢀLGHQWLILHU
06ꢍꢎꢎꢆꢐ9ꢁ
94/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Package information
10.2
TSSOP20 package information
Figure 45.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline
$
ꢆꢉ
ꢀꢀ
ꢀꢉ
C
%ꢀ
%
3%!4).'
0,!.%
ꢉꢊꢆꢈ MM
'!'% 0,!.%
#
ꢀ
0). ꢀ
)$%.4)&)#!4)/.
K
AAA
#
!ꢀ
,
!
!ꢆ
,ꢀ
B
E
9!?-%?6ꢁ
1. Drawing is not to scale.
Table 62. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
-
-
1.200
0.150
1.050
0.300
0.200
6.600
6.600
4.500
-
-
-
0.0472
0.0059
0.0413
0.0118
0.0079
0.2598
0.2598
0.1772
-
0.050
0.800
0.190
0.090
6.400
6.200
4.300
-
-
0.0020
0.0315
0.0075
0.0035
0.2520
0.2441
0.1693
-
-
1.000
-
0.0394
-
c
-
-
D(2)
6.500
6.400
4.400
0.650
0.600
1.000
0.2559
0.2520
0.1732
0.0256
0.0236
0.0394
E
E1(3)
e
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
DocID025118 Rev 5
95/106
103
Package information
STM8AF6213/23/23A/26
Table 62. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
millimeters
Typ.
inches(1)
Symbol
Min.
Max.
Min.
Typ.
Max.
k
0°
-
-
-
8°
0°
-
-
-
8°
aaa
0.100
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 46. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint
ꢋꢄꢅꢌ
ꢃꢄꢅꢌ
ꢅꢋ
ꢁꢁ
ꢁꢄꢍꢌ
ꢋꢄꢅꢌ
ꢎꢄꢁꢋ ꢊꢄꢊꢋ
ꢁꢄꢍꢌ
ꢁ
ꢁꢋ
ꢋꢄꢊꢋ
ꢋꢄꢃꢌ
9!?&0?6ꢀ
1. Dimensions are expressed in millimeters.
96/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 47. TSSOP20 marking example (package top view)
6WDQGDUGꢀ67ꢀORJR
3URGXFWꢀ
LGHQWLILFDWLRQꢈꢁꢉ
999999999
'DWHꢀFRGH
5HYLVLRQꢀFRGH
3LQꢀꢁꢀLGHQWLILHU
:
88
06ꢍꢆꢍꢎꢍ9ꢁ
DocID025118 Rev 5
97/106
103
Package information
STM8AF6213/23/23A/26
10.3
Thermal characteristics
The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Table 26: General operating conditions.
T
, in degrees Celsius, may be calculated using the following equation:
Jmax
T
= T
+ (P
x )
Dmax JA
Jmax
Amax
Where:
–
–
–
–
T
is the maximum ambient temperature in C
Amax
is the package junction-to-ambient thermal resistance in C/W
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum
INTmax
DD
DD
chip internal power.
–
P
represents the maximum power dissipation on output pins
I/Omax
Where:
P
= (V *I ) + ((V -V )*I ),
I/Omax
OL OL
DD OH OH
taking into account the actual V /I and V /I of the I/Os at low and high level
OL OL
OH OH
in the application.
(1)
Table 63. Thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
TSSOP20 - 4 x 4 mm
110
°C/W
JA
Thermal resistance junction-ambient
60
°C/W
LQFP 32 - 7 x 7 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.3.1
10.3.2
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Section 11: Ordering information).
The following example shows how to calculate the temperature range needed for a given
application.
98/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Package information
Assuming the following application conditions:
Maximum ambient temperature T = 75 °C (measured according to JESD51-2),
Amax
I
= 8 mA, V = 5 V
DDmax
DD
Maximum 20 I/Os used at the same time in output at low level with:
= 8 mA, V = 0.4 V
I
OL
OL
P
P
= 8 mA x 5 V= 400 mW
INTmax
= 20 x 8 mA x 0.4 V = 64 mW
IOmax
This gives: P
= 400 mW and P
64 mW:
IOmax
INTmax
P
= 400 mW + 64 mW
Dmax
Thus: P
= 464 mW.
Dmax
Using the values obtained in Table 63: Thermal characteristics on page 98 T
is
Jmax
calculated as follows:
For LQFP32 60 °C/W
T
= 75 °C + (60 °C/W x464 mW) = 75 °C + 27.8 °C = 102.8 °C
Jmax
This is within the range of the suffix C version parts (-40 < T < 125 °C).
J
Parts must be ordered at least with the temperature range suffix C.
DocID025118 Rev 5
99/106
103
Ordering information
STM8AF6213/23/23A/26
11
Ordering information
(1) (2)
Figure 48. STM8AF6213/23/23A/26 ordering information scheme
Example:
STM8A
F
62
2
3
I
P
C
A
U
Product class
8-bit automotive microcontroller
Program memory type
F = Flash + EEPROM
Device family
62 = LIN only
Program memory size
1 = 4 Kbyte
2 = 8 Kbyte
Pin count
3 = 20 pins
6 = 32 pins
HSI accuracy
Blank = ± 5%
I = ± 3%
Package type
T = LQFP
P = TSSOP
Temperature range
A = -40 to 85 °C
C = -40 to 125 °C
D = -40 to 150 °C
Number of ADC analog inputs
Blank = 5 analog inputs
A = 7 analog inputs
Packing
Y = Tray
U = Tube
X = Tape and reel compliant with EIA 481-C
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the nearest ST Sales Office.
2. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
100/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
STM8 development tools
12
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, the
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full-featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including coverage to help detect and eliminate
bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers
via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of
an application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
12.1.1
STice key features
Occurrence and time profiling and code coverage analysis (new features)
Advanced breakpoints with up to 4 levels of conditions
Data breakpoints
Program and data trace recording up to 128 KB records
Read/write on-the-fly of memory during emulation
In-circuit debugging/programming via SWIM protocol
8-bit probe analyzer
1 input and 2 output triggers
Power supply follower managing application voltages between 1.62 to 5.5 V
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements.
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
DocID025118 Rev 5
101/106
103
STM8 development tools
STM8AF6213/23/23A/26
12.2
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual
programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8.
12.2.1
STM8 toolset
The STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com. This package includes:
ST visual develop
Full-featured integrated development environment from STMicroelectronics, featuring:
Seamless integration of C and ASM toolsets
Full-featured debugger
Project management
Syntax highlighting editor
Integrated programming interface
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP)
Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8
microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers
project mode for saving programming configurations and automating programming
sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of the
application directly from an easy-to-use graphical interface.
Available toolchains include:
Cosmic C compiler for STM8
All compilers are available in free version with a limited code size depending on the
compiler. For more information, refer to www.cosmic-software.com, www.raisonance.com,
and www.iar.com.
STM8 assembler linker
Free assembly toolchain included in the STM8 toolset, which allows the users to assemble
and link your application source code.
102/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
STM8 development tools
12.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on the user application board via the SWIM protocol. Additional tools include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming the STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
DocID025118 Rev 5
103/106
103
Revision history
STM8AF6213/23/23A/26
13
Revision history
Table 64. Document revision history
Date
Revision
Changes
11-Oct-2013
1
Initial release.
Changed the document status to Production data.
Updated Figure: STM8AF6223PxAx TSSOP20 pinout to
add SPI_NSS to PD4, TLI to PD2, and change remap
function on PB5 from TIM5_BKIn to TIM1_BKIN.
Updated Table: STM8AF6223PxAx TSSOP20 pin
description to add SPI_NSS to PD4 and TLI to PD2.
Updated Table: STM8AF6223 TSSOP20 pin description
and Table: LQFP32 pin description.
Updated AFR2 definition in Table: STM8AF6223PxAx
alternate function remapping bits [7:2] for 20-pin
packages.
Removed the remapping option on PA3 for AFR[1:0]=10
in Table: STM8AF6223PxAx alternate function
remapping bits [1:0] for 20-pin packages.
16-Dec-2013
2
Added note and removed remapping option on PA3 for
AFR[1:0]=11 in Table: STM8AF6223 alternate function
remapping bits [1:0] for 20-pin packages. Updated AFR2
definition in STM8AF6223 alternate function remapping
bits [7:2] for 20-pin packages.
Added the note below Table: STM8AF6226T alternate
function remapping bits [1:0] for 32-pin packages.
Updated Table: I2C characteristics to modify th(SDA) and
add tSP
.
Updated Section: C assembly toolchains.
Replaced STM8AF6226T by STM8AF6226 part number.
Added STM8AF6223A part number to cover
STM8AF6223PxAx order codes.
Removed LINUART alternate function for PA3 in Table:
STM8AF6223PxAx TSSOP20 pin description.
Removed note 3 for IDD(AH) in Table: Total current
consumption in active halt mode at VDD = 5 V.
Updated the remapping option on PA3 for AFR[1:0]=11
in Table: STM8AF6223 alternate function remapping bits
[1:0] for 20-pin packages.
03-Apr-2014
3
Updated notes related to tRET minimum value in Table:
Data memory.
Updated Table: ESD absolute maximum ratings.
Added notes related to protrusions and gate burrs for D
and E1 dimensions in Table: 20-pin, 4.40 mm body, 0.65
mm pitch mechanical data.
104/106
DocID025118 Rev 5
STM8AF6213/23/23A/26
Date
Revision history
Table 64. Document revision history (continued)
Revision
Changes
Extended the applicability to STM8AF6213 devices.
Updated the program memory feature, the power
management, and the clock management features on
the cover page.
10-Jul-2014
4
Added the table in Section: Memory map.
Updated the Figure: fCPUmax versus VDD in Section:
Operating conditions.
Updated Section: Ordering information.
Added:
– the footnote about the inrush current below Table 27:
Operating conditions at power-up/power-down,
– Figure 44: LQFP32 marking example (package top
view),
– Figure 47: TSSOP20 marking example (package top
view).
Updated
– LIN standard version,
– the register label for LINUART block in Table 11:
General hardware register map,
26-Jun-2015
5
– the power dissipation in Table 26: General operating
conditions,
– Table 41: HSI oscillator characteristics for HSI
oscillator accuracy,
– the standard for EMI in Electromagnetic interference
(EMI),
– Figure 48: STM8AF6213/23/23A/26 ordering
information scheme(1) (2) to add HSI accuracy.
Moved Section 10.3: Thermal characteristics to
Section 10: Package information.
DocID025118 Rev 5
105/106
105
STM8AF6213/23/23A/26
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
106/106
DocID025118 Rev 5
相关型号：
STM8AF6223A
Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, IC, 3 to 5.5 V
STMICROELECTR
STM8AF6226
Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V
STMICROELECTR
STM8AF6226TAX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32
STMICROELECTR
STM8AF6226TBX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32
STMICROELECTR
STM8AF6226TCX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32
STMICROELECTR
STM8AF6246
Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V
STMICROELECTR
STM8AF6246TBX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP32, 7 X 7 MM, ROHS COMPLIANT, LQFP-32
STMICROELECTR
STM8AF6246UBX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, QCC32, 5 X 5 MM, ROHS COMPLIANT, VFQFPN-32
STMICROELECTR
STM8AF6246UBY
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, QCC32, 5 X 5 MM, ROHS COMPLIANT, VFQFPN-32
STMICROELECTR
STM8AF6246UCU
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, QCC32, 5 X 5 MM, ROHS COMPLIANT, VFQFPN-32
STMICROELECTR
STM8AF6248
Automotive 8-bit MCU, with up to 32 Kbytes Flash, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V
STMICROELECTR
STM8AF6248TAX
8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP48, 7 X 7 MM, ROHS COMPLIANT, LQFP-48
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明