STM8L152M8 [STMICROELECTRONICS]
8-bit ultralow power MCU, up to 64 KB Flash 2 KB data EEPROM;型号: | STM8L152M8 |
厂家: | ST |
描述: | 8-bit ultralow power MCU, up to 64 KB Flash 2 KB data EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总134页 (文件大小:1850K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STM8L151x8 STM8L152x8
STM8L151R6 STM8L152R6
8-bit ultralow power MCU, up to 64 KB Flash + 2 KB data EEPROM,
RTC, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, comparators
Datasheet - production data
Features
• Operating conditions
LQFP80
LQFP64
LQFP48
UFQFPN48
– Operating power supply: 1.65 to 3.6 V
(without BOR), 1.8 to 3.6 V (with BOR)
• Memories
– Temp. range: -40 to 85, 105 or 125 °C
– Up to 64 KB of Flash memory with up to 2
KB of data EEPROM with ECC and RWW
• Low power features
– 5 low power modes: Wait, Low power run
(5.9 µA), Low power wait (3 µA), Active-halt
with full RTC (1.4 µA), Halt (400 nA)
– Flexible write/read protection modes
– Up to 4 KB of RAM
• 2x12-bit DAC (dual mode) with output buffer
– Consumption: 200 µA/MHz+330 µA
– Fast wake up from Halt mode (4.7 µs)
– Ultra low leakage per I/0: 50 nA
• 2 ultralow power comparators
– 1 with fixed threshold and 1 rail to rail
– Wakeup capability
• Advanced STM8 core
• Timers
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
– Three 16-bit timers with 2 channels (IC,
OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
• Reset and supply management
– Low power, ultrasafe BOR reset with 5
programmable thresholds
– One 8-bit timer with 7-bit prescaler
– 1 Window and 1 independent watchdog
– Beeper timer with 1, 2 or 4 kHz frequencies
– Ultralow power POR/PDR
– Programmable voltage detector (PVD)
• Communication interfaces
• Clock management
– Two synchronous serial interface (SPI)
– 32 kHz and 1-16 MHz crystal oscillators
2
– Fast I C 400 kHz SMBus and PMBus
– Internal 16 MHz factory-trimmed RC and
38 kHz low consumption RC
– Three USARTs (ISO 7816 interface + IrDA)
• Up to 67 I/Os, all mappable on interrupt vectors
– Clock security system
• Up to 16 capacitive sensing channels
supporting touchkey, proximity, linear touch
and rotary touch sensors
• Low power RTC
– BCD calendar with alarm interrupt,
– Digital calibration with +/- 0.5ppm accuracy
– Advanced anti-tamper detection
• Fast on-chip programming and non-intrusive
debugging with SWIM, Bootloader using
USART
• DMA
2
– 4 ch. for ADC, DACs, SPIs, I C, USARTs,
• 96-bit unique ID
Timers, 1 ch. for memory-to-memory
Table 1. Device summary
• LCD: 8x40 or 4x44 w/ step-up converter
Reference
Part number
• 12-bit ADC up to 1 Msps/28 channels
STM8L151x8
STM8L152x8
STM8L151C8, STM8L152C8, STM8L151R8,
STM8L152R8, STM8L151M8, STM8L152M8
– Temp. sensor and internal ref. voltage
STM8L151R6
STM8L152R6
STM8L151R6, STM8L152R6
July 2013
DocID17943 Rev 6
1/134
This is information on a product in full production.
www.st.com
Contents
STM8L15xx8, STM8L15xR6
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
STM8L Ultralow power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . . . 10
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1
3.2.2
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1
3.3.2
3.3.3
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
3.5
3.6
3.7
3.8
3.9
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 21
3.13 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 22
3.14.3 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Contents
3.15.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
3.17.2 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.18 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4
5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1
5.2
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
7
8
9
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2
9.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Embedded reset and power control block characteristics . . . . . . . . . . 70
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Contents
STM8L15xx8, STM8L15xR6
9.3.8
9.3.9
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9.3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.12 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.13 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9.3.14 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
10
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11
12
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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List of tables
List of tables
Table 1.
Table 2.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
High density and medium+ density STM8L15xx low power device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
High density and medium+ density STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . 28
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 70
Total current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V . 79
Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 81
Total current consumption and timing in Active-halt mode
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 85
Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 86
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 99
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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List of tables
STM8L15xx8, STM8L15xR6
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 115
R
max for f
= 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
AIN
ADC
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP80, 14 x 14 mm, 80-pin low profile quad flat package mechanical data . . . . . . . . . 123
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 125
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 127
UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 129
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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STM8L15xx8, STM8L15xR6
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
High density and medium+ density STM8L15xx device block diagram . . . . . . . . . . . . . . 13
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM8L151M8 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L152M8 80-pin package pinout (with LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151R8 and STM8L151R6 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . 26
STM8L152R8 and STM8L152R6 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L151C8 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8L152C8 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 13. Typical I
from RAM vs. V (HSI clock source), f
=16 MHz . . . . . . . . . . . . . . 75
= 16 MHz . . . . . . . . . . . . . 75
= 16 MHz . . . . . . . . . . . . . . 78
DD(RUN)
DD(RUN)
DD(Wait)
DD(Wait)
DD(LPR)
DD(LPW)
DD
CPU
Figure 14. Typical I
Figure 15. Typical I
Figure 16. Typical I
Figure 17. Typical I
Figure 18. Typical I
from Flash vs. V (HSI clock source), f
DD
CPU
from RAM vs. V (HSI clock source), f
DD
CPU
from Flash (HSI clock source), f
= 16 MHz . . . . . . . . . . . . . . . . . . . . 78
CPU
vs. V (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 80
DD
vs. V (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . 82
DD
Figure 19. Typical IDD(AH) vs. V (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DD
Figure 20. Typical IDD(Halt) vs. V (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 86
DD
Figure 21. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 22. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 23. Typical HSI frequency vs. V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
DD
Figure 24. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 25. Typical VIL and VIH vs. VDD (standard I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 26. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 27. Typical pull-up resistance R vs. V with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PU
DD
Figure 28. Typical pull-up current I vs. V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
pu
DD
Figure 29. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 30. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 31. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 32. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 34. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 35. Typical NRST pull-up resistance R vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PU
DD
Figure 36. Typical NRST pull-up current I vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
pu
DD
Figure 37. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 38. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 39. SPI1 timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 40. SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 41. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 42. ADC1 accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 43. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 44. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 45. Power supply and reference decoupling (V not connected to V ). . . . . . . . . . . . . 118
REF+
DDA
Figure 46. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . 118
Figure 47. LQFP80, 14 x 14 mm, 80-pin low profile quad flat package . . . . . . . . . . . . . . . . . . . . . . . 123
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8
List of figures
STM8L15xx8, STM8L15xR6
Figure 48. LQFP80 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 49. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 125
Figure 50. LQFP64 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 51. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 127
Figure 52. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 53. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 54. UFQFPN48 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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STM8L15xx8, STM8L15xR6
Introduction
1
Introduction
This document describes the features, pinout, mechanical data and ordering information for:
•
High density STM8L15xxx devices: STM8L151x8 and STM8L152x8 microcontrollers
with a Flash memory density of 64 Kbytes.
•
Medium+ density STM8L15xxx devices: STM8L151R6 and STM8L152R6
microcontrollers with Flash memory density of 32 Kbytes.
For further details on the STMicroelectronics Ultralow power family please refer to
Section 2.3: Ultralow power continuum on page 12.
For detailed information on device operation and registers, refer to the reference manual
(RM0031).
For information on to the Flash program memory and data EEPROM, refer to the
programming manual (PM0054).
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).
2
Description
The high density and medium+ density STM8L15xx Ultralow power devices feature an
enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at
16 MHz) while maintaining the advantages of a CISC architecture with improved code
density, a 24-bit linear addressing space and an optimized architecture for low power
operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All high density and medium+ density STM8L15xx microcontrollers feature embedded data
EEPROM and low power low-voltage single-supply program Flash memory.
The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, two DACs, two comparators, a real-time clock, four 16-bit timers, one 8-bit timer, as
2
well as standard communication interfaces such as two SPIs, an I C interface, and three
USARTs. A 8x40 or 4x44-segment LCD is available on the STM8L152x8 devices. The
modular design of the peripheral set allows the same peripherals to be found in different ST
microcontroller families including 32-bit families. This makes any transition to a different
family very easy, and simplified even more by the use of a common set of development
tools.
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61
Description
STM8L15xx8, STM8L15xR6
2.1
STM8L Ultralow power 8-bit family benefits
High density and medium+ density STM8L15xx devices are part of the STM8L Ultralow
power family providing the following benefits:
•
Integrated system
–
–
–
–
–
Up to 64 Kbytes of high-density embedded Flash program memory
Up to 2 Kbytes of data EEPROM
Up to 4 Kbytes of RAM
Internal high-speed and low-power low speed RC.
Embedded reset
•
Ultralow power consumption
–
–
–
1 µA in Active-halt mode
Clock gated system and optimized power management
Capability to execute from RAM for Low power wait mode and Low power run
mode
•
•
Advanced features
–
–
Up to 16 MIPS at 16 MHz CPU clock frequency
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Wide choice of development tools
STM8L Ultralow power microcontrollers can operate either from 1.8 to 3.6 V (down to 1.65 V
at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to
+125 °C temperature ranges.
These features make the STM8L Ultralow power microcontroller families suitable for a wide
range of applications:
•
•
•
•
•
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, wired and wireless sensors
Metering
The devices are offered in four different packages from 48 to 80 pins. Different sets of
peripherals are included depending on the device. Refer to Section 3 for an overview of the
complete range of peripherals proposed in this family.
All STM8L Ultralow power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Figure 1 shows the block diagram of the High density and medium+ density STM8L15xx
families.
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Description
2.2
Device overview
Table 2. High density and medium+ density STM8L15xx low power device features and
peripheral counts
Features
STM8L15xC8 STM8L15xR8
STM8L15xM8
STM8L15xR6
Flash (Kbytes)
Data EEPROM (Kbytes)
RAM (Kbytes)
LCD
64
64
64
32
2
1
4
4
4
2
8x24 or 4x28(1)
8x36 or 4x40(1)
8x40 or 4x44(1)
8x36 or 4x40(1)
1
1
1
1
Basic
(8-bit)
(8-bit)
(8-bit)
(8-bit)
3
3
3
3
Timers
General purpose
(16-bit)
(16-bit)
(16-bit)
(16-bit)
1
1
1
1
Advanced control
(16-bit)
(16-bit)
(16-bit)
(16-bit)
SPI
2
1
2
1
2
1
2
1
Communication
interfaces
I2C
USART
3
3
3
3
GPIOs
41(2)
54(2)
68(2)
54(2)
12-bit synchronized ADC
(number of channels)
1
(25)
1
(28)
1
(28)
1
(28)
12-Bit DAC
2
2
2
2
2
2
2
2
Number of channels
Comparators (COMP1/COMP2)
Others
2
2
2
2
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator
CPU frequency
16 MHz
1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
1.65 to 3.6 V without BOR
Operating voltage
Operating temperature
Packages
−40 to +85 °C / −40 to +105 °C / −40 to +125 °C
UFQFPN48
LQFP64
LQFP80
LQFP64
LQFP48
1. STM8L152xx versions only.
2. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
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61
Description
STM8L15xx8, STM8L15xR6
2.3
Ultralow power continuum
The Ultralow power STM8L151xx and STM8L152xx are fully pin-to-pin, software and
feature compatible. Besides the full compatibility within the family, the devices are part of
STMicroelectronics microcontrollers UltraLow power strategy which also includes
STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of
performance, peripherals, system architecture, and features.
They are all based on STMicroelectronics 0.13 µm Ultralow leakage process.
Note:
1
2
The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.
The STM32L family is pin-to-pin compatible with the general purpose STM32F family.
Please refer to STM32L15xx documentation for more information on these devices.
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs.
Shared peripherals
STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy
migration from one family to another:
•
•
Analog peripherals: ADC1, DAC1/DAC2, and comparators COMP1/COMP2
Digital peripherals: RTC and some communication interfaces
Common system strategy
To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx devices use
a common architecture:
•
Same power supply range from 1.65 to 3.6 V. For STM8L101xx and medium density
STM8L15xx, the power supply must be above 1.8 V at power-on, and go below 1.65 V
at power-down.
•
Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
•
•
•
Fast startup strategy from low power modes
Flexible system clock
Ultrasafe reset: same reset strategy for both STM8L15xx and STM32L15xx including
power-on reset, power-down reset, brownout reset and programmable voltage
detector.
Features
ST UtraLow power continuum also lies in feature compatibility:
•
•
More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 128 Kbytes
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Functional overview
3
Functional overview
Figure 1. High density and medium+ density STM8L15xx device block diagram
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1. Legend:
AF: alternate function
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
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61
Functional overview
STM8L15xx8, STM8L15xR6
LCD: Liquid crystal display
POR/PDR: Power on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
3.1
Low power modes
The high density and medium+ density STM8L15xx devices support five low power modes
to achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
•
Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset can be used to exit the microcontroller from Wait mode
(WFE or WFI mode).
•
Low power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in Ultralow power mode.
The microcontroller enters Low power run mode by software and can exit from this
mode by software or by a reset.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
•
Low power wait mode: This mode is entered when executing a Wait for event in Low
power run mode. It is similar to Low power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low power run mode.
All interrupts must be masked. They cannot be used to exit the microcontroller from this
mode.
•
•
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
can be triggered by RTC interrupts, external interrupts or reset.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Functional overview
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
•
•
•
•
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•
•
•
•
8-bit accumulator
24-bit program counter - 16 Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•
•
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
•
•
•
•
•
•
•
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
3.2.2
Interrupt controller
The high density and medium+ density STM8L15xxdevices feature a nested vectored
interrupt controller:
•
•
•
•
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
DocID17943 Rev 6
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61
Functional overview
STM8L15xx8, STM8L15xR6
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (V ). The external power
DD
supply pins must be connected as follows:
•
V
, V
, V
, V
, V
, V
, V
, V
= 1.65 to 3.6 V: external power supply
SS1 DD1
SS2 DD2
SS3 DD3
SS4 DD4
for I/Os and for the internal regulator. Provided externally through V pins, the
DD
corresponding ground pin is V . V
/V
/V
/V
and V /V /V /V
SS
SS1 SS2 SS3 SS4
DD1 DD2 DD3 DD4
must not be left unconnected.
•
V
, V
= 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
DDA
SSA
voltage to be applied to V
is 1.8 V when the ADC1 is used). V
and V
must
DDA
DDA
SSA
be connected to V and V , respectively.
DD
SS
•
•
V
, V
(for ADC1): external reference voltage for ADC1. Must be provided
REF-
REF+
externally through V
and V
pin.
REF+
REF-
V
(for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
REF+
externally through V
.
REF+
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR). For the device sales types without the “D” option (see Section 11: Ordering
information scheme), it is coupled with a brownout reset (BOR) circuitry. It that case the
device operates between 1.8 and 3.6 V, BOR is always active and ensures proper operation
starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading
process starts, either to confirm or modify default thresholds, or to disable BOR permanently
(in which case, the V min. value at power-down is 1.65 V).
DD
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains in
reset state when V is below a specified threshold, V
or V
, without the need for
DD
POR/PDR
BOR
any external reset circuit.
Note:
For device sales types with the “D” option (see Section 11: Ordering information scheme)
BOR is permanently disabled and the device operates between 1.65 and 3.6 V. In this case
it is not possible to enable BOR through the option bytes.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
/V
power supply and compares it to the V
threshold. This PVD offers 7 different
DD DDA
PVD
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V /V drops below the V threshold and/or when
DD DDA
PVD
V
/V
is higher than the V
threshold. The interrupt service routine can then generate
DD DDA
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
16/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Functional overview
3.3.3
Voltage regulator
The high density and medium+ density STM8L15xx devices embed an internal voltage
regulator for generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
•
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
•
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and
Low power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
•
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•
•
•
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
System clock sources: 4 different clock sources can be used to drive the system
clock:
–
–
–
–
1-16 MHz High speed external crystal (HSE)
16 MHz High speed internal RC oscillator (HSI)
32.768 Low speed external crystal (LSE)
38 kHz Low speed internal RC (LSI)
•
•
RTC and LCD clock sources: the above four sources can be chosen to clock the RTC
and the LCD, whatever the system clock.
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
•
•
Clock security system (CSS): This feature can be enabled by software. If a HSE
clock failure occurs, the system clock is automatically switched to HSI.
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID17943 Rev 6
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61
Functional overview
STM8L15xx8, STM8L15xR6
Figure 2. Clock tree diagram
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3.5
Low power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically. The subsecond field can also be read in binary format.
The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a
synchronization to a master clock.
The RTC offers a digital calibration which allows an accuracy of +/-0.5 ppm.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
•
Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach
36 hours
•
Periodic alarms based on the calendar can also be generated from LSE period to every
year
A clock security system detects a failure on LSE, and can provide an interrupt with wakeup
capability. The RTC clock can automatically switch to LSI in case of LSE failure.
The RTC also provides 3 anti-tamper detection pins. This detection embeds a
programmable filter and can wakeup the MCU.
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Functional overview
3.6
LCD (Liquid crystal display)
The LCD is only available on STM8L152xx devices.
The liquid crystal display drives up to 8 common terminals and up to 40 segment terminals
to drive up to 320 pixels. It can also be configured to drive up to 4 common and 44
segments (up to 176 pixels).
•
•
•
•
•
•
Internal step-up converter to guarantee contrast control whatever V
.
DD
Static 1/2, 1/3, 1/4, 1/8 duty supported.
Static 1/2, 1/3, 1/4 bias supported.
Phase inversion to reduce power consumption and EMI.
Up to 8 pixels which can programmed to blink.
The LCD controller can operate in Halt mode.
Note:
Unnecessary segments and common pins can be used as general I/O pins.
3.7
Memories
The high density and medium+ density STM8L15xx devices have the following main
features:
•
•
Up to 4 Kbytes of RAM
The non-volatile memory is divided into three arrays:
–
–
–
Up to 64 Kbytes of medium-density embedded Flash program memory
Up to 2 Kbytes of Data EEPROM
Option bytes.
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8
DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, DAC1,DAC2, I2C1, SPI1, SPI2, USART1,
USART2, USART3, and the 5 Timers.
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61
Functional overview
STM8L15xx8, STM8L15xR6
3.9
Analog-to-digital converter
•
12-bit analog-to-digital converter (ADC1) with 28 channels (including 4 fast channel),
temperature sensor and internal reference voltage
•
•
•
•
•
•
Conversion time down to 1 µs with f
= 16 MHz
SYSCLK
Programmable resolution
Programmable sampling time
Single and continuous mode of conversion
Scan capability: automatic conversion performed on a selected group of analog inputs
Analog watchdog: interrupt generation when the converted voltage is outside the
programmed threshold
•
Triggered by timer
Note:
ADC1 can be served by DMA1.
3.10
Digital-to-analog converter
•
12-bit DAC with 2 buffered outputs (two digital signals can be converted into two analog
voltage signal outputs)
•
•
•
•
•
•
•
Synchronized update capability using timers
DMA capability for each channel
External triggers for conversion
Noise-wave generation
Triangular-wave generation
Dual DAC channels with independent or simultaneous conversions
Input reference voltage V
for better resolution
REF+
Note:
DAC can be served by DMA1.
3.11
Ultralow power comparators
The high density and medium+ density STM8L15xx devices embed two comparators
(COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage
reference can be internal or external (coming from an I/O).
•
•
One comparator with fixed threshold (COMP1).
One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one
of the following:
–
–
–
DAC output
External I/O
Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)
The two comparators can be used together to offer a window function. They can wake up
from Halt mode.
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Functional overview
3.12
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1, COMP1, COMP2, DAC1 and the internal reference voltage V
. It also
REFINT
provides a set of registers for efficiently managing the charge transfer acquisition sequence
(see Section 3.13: Touch sensing).
3.13
Touch sensing
The high density and medium+ density STM8L15xx devices provide a simple solution for
adding capacitive sensing functionality to any application. Capacitive sensing technology is
able to detect finger presence near an electrode which is protected from direct touch by a
dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any
conductive object) is measured using a proven implementation based on a surface charge
transfer acquisition principle. It consists of charging the electrode capacitance and then
transferring a part of the accumulated charges into a sampling capacitor until the voltage
across this capacitor has reached a specific threshold. In the high density and medium+
density STM8L15xx devices, the acquisition sequence is managed by software and it
involves analog I/O groups and the routing interface.
Reliable touch sensing solution can be quickly and easily implemented using the free STM8
touch sensing firmware library.
3.14
Timers
The high density and medium+ density STM8L15xx devices contain one advanced control
timer (TIM1), three 16-bit general purpose timers (TIM2,TIM3 and TIM5) and one 8-bit basic
timer (TIM4).
All the timers can be served by DMA1.
Table 3 compares the features of the advanced control, general-purpose and basic timers.
Table 3. Timer feature comparison
DMA1
Counter Counter
Capture/compare Complementary
Timer
Prescaler factor
request
resolution
type
channels
outputs
generation
Any integer
from 1 to 65536
TIM1
3 + 1
3
TIM2
TIM3
TIM5
16-bit
8-bit
up/down
up
Any power of 2
from 1 to 128
Yes
2
0
None
Any power of 2
from 1 to 32768
TIM4
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Functional overview
STM8L15xx8, STM8L15xR6
3.14.1
16-bit advanced control timer (TIM1)
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
•
•
16-bit up, down and up/down autoreload counter with 16-bit prescaler
3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
•
•
•
•
•
•
1 additional capture/compare channel which is not connected to an external I/O
Synchronization module to control the timer with external signals
Break input to force timer outputs into a defined state
3 complementary outputs with adjustable dead time
Encoder mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
3.14.2
16-bit general purpose timers (TIM2, TIM3, TIM5)
•
•
•
•
•
•
16-bit autoreload (AR) up/down-counter
7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
2 individually configurable capture/compare channels
PWM mode
Interrupt capability on various events (capture, compare, overflow, break, trigger)
Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
3.14.3
8-bit basic timer (TIM4)
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. It can be used for timebase generation with interrupt generation on timer overflow
or for DAC trigger generation.
3.15
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.15.1
Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.15.2
Independent watchdog timer
The independent watchdog peripheral (IWDG) can be used to resolve processor
malfunctions due to hardware or software failures.
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STM8L15xx8, STM8L15xR6
Functional overview
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.16
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
3.17
Communication interfaces
3.17.1
SPI
The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial
communication with external devices.
•
•
•
•
•
•
Maximum speed: 8 Mbit/s (f
/2) both for master and slave
SYSCLK
Full duplex synchronous transfers
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
Hardware CRC calculation
Slave/master selection input pin
Note:
SPI1 and SPI2 can be served by the DMA1 Controller.
2
3.17.2
I C
2
The I C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-
specific sequencing, protocol, arbitration and timing.
•
•
•
•
•
Master, slave and multi-master capability
Standard mode up to 100 kHz and fast speed modes up to 400 kHz.
7-bit and 10-bit addressing modes.
SMBus 2.0 and PMBus support
Hardware CRC calculation
2
Note:
I C1 can be served by the DMA1 Controller.
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61
Functional overview
STM8L15xx8, STM8L15xR6
3.17.3
USART
The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous
communications with external devices requiring an industry standard NRZ asynchronous
serial data format. It offers a very wide range of baud rates.
•
•
•
•
•
•
1 Mbit/s full duplex SCI
SPI1 emulation
High precision baud rate generator
Smartcard emulation
IrDA SIR encoder decoder
Single wire half duplex mode
Note:
USART1, USART2 and USART3 can be served by the DMA1 Controller.
3.18
Infrared (IR) interface
The high density and medium+ density STM8L15xx devices contain an infrared interface
which can be used with an IR LED for remote control functions. Two timer output compare
channels are used to generate the infrared remote control signals.
3.19
Development support
Development tools
Development tools for the STM8 microcontrollers include:
•
•
The STice emulation system offering tracing and code profiling
The STVD high-level language debugger including C compiler, assembler and
integrated development environment
•
The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation can also be monitored in real-
time by means of shadow registers.
Bootloader
A bootloader is available to reprogram the Flash memory using the USART1, USART2,
USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces. The reference
document for the bootloader is UM0560: STM8 bootloader user manual.
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STM8L15xx8, STM8L15xR6
Pin description
4
Pin description
Figure 3. STM8L151M8 80-pin package pinout (without LCD)
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0$ꢅ
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0&ꢅ
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0"ꢉ
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0!ꢂ
0!ꢉ
0!ꢆ
0!ꢍ ꢀꢑ
0!ꢅ ꢀꢀ
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ꢀꢉ
ꢀꢆ
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AIꢀꢁꢃꢉꢉ
1. The above figure shows the package top view.
DocID17943 Rev 6
25/134
61
Pin description
STM8L15xx8, STM8L15xR6
Figure 5. STM8L151R8 and STM8L151R6 64-pin pinout (without LCD)
ꢅꢆ ꢅꢉ ꢅꢂ ꢅꢀ ꢅꢑ ꢍꢓ ꢍꢃ ꢍꢁ ꢍꢅ ꢍꢍ ꢍꢆ ꢍꢉ ꢍꢂ ꢍꢀ ꢍꢑ ꢆꢓ
ꢀ
ꢂ
ꢉ
ꢆ
ꢍ
ꢅ
ꢁ
ꢃ
ꢓ
ꢀꢑ
ꢆꢃ
ꢆꢁ
ꢆꢅ
ꢆꢍ
ꢆꢆ
ꢆꢉ
ꢆꢂ
ꢆꢀ
ꢆꢑ
ꢉꢓ
ꢉꢃ
ꢉꢁ
ꢉꢅ
ꢉꢍ
ꢉꢆ
ꢉꢉ
0$ꢁ
0$ꢅ
0$ꢍ
0$ꢆ
0&ꢁ
0&ꢅ
0&ꢍ
0&ꢆ
0&ꢀ
0&ꢑ
0"ꢁ
0"ꢅ
0!ꢑ
.234ꢎ0!ꢀ
0!ꢂ
0!ꢉ
0!ꢆ
0!ꢍ
0!ꢅ
0!ꢁ
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633ꢀ
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ꢀꢂ
ꢀꢉ
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0"ꢆ
0"ꢉ
0"ꢂ
0'ꢑ
0'ꢀ ꢀꢍ
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AIꢀꢁꢃꢉꢀ
1. Pin 18 is reserved and must be tied to VDD
.
2. The above figure shows the package top view.
Figure 6. STM8L152R8 and STM8L152R6 64-pin pinout (with LCD)
ꢅꢆ ꢅꢉ ꢅꢂ ꢅꢀ ꢅꢑ ꢍꢓ ꢍꢃ ꢍꢁ ꢍꢅ ꢍꢍ ꢍꢆ ꢍꢉ ꢍꢂ ꢍꢀ ꢍꢑ ꢆꢓ
ꢀ
ꢆꢃ
ꢆꢁ
ꢆꢅ
ꢆꢍ
ꢆꢆ
ꢆꢉ
ꢆꢂ
ꢆꢀ
ꢆꢑ
ꢉꢓ
ꢉꢃ
ꢉꢁ
ꢉꢅ
ꢉꢍ
ꢉꢆ
ꢉꢉ
0$ꢁ
0$ꢅ
0$ꢍ
0$ꢆ
0&ꢁ
0&ꢅ
0&ꢍ
0&ꢆ
0&ꢀ
0&ꢑ
0"ꢁ
0"ꢅ
0!ꢑ
.234ꢎ0!ꢀ
0!ꢂ
ꢂ
ꢉ
ꢆ
0!ꢉ
0!ꢆ
0!ꢍ
0!ꢅ
ꢍ
ꢅ
ꢁ
0!ꢁ
ꢃ
633!ꢎ62%&ꢇ
ꢓ
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ꢀꢂ
ꢀꢉ
ꢀꢆ
62%&ꢏ
0"ꢍ
0"ꢆ
0"ꢉ
0"ꢂ
0'ꢑ
0'ꢀ ꢀꢍ
0'ꢂ ꢀꢅ
ꢀꢁ ꢀꢃ ꢀꢓ ꢂꢑ ꢂꢀ ꢂꢂ ꢂꢉ ꢂꢆ ꢂꢍ ꢂꢅ ꢂꢁ ꢂꢃ ꢂꢓ ꢉꢑ ꢉꢀ ꢉꢂ
AIꢀꢁꢃꢉꢍ
1. The above figure shows the package top view.
26/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Figure 7. STM8L151C8 48-pin pinout (without LCD)
ꢆꢃ ꢆꢁ ꢆꢅ ꢆꢍ ꢆꢆ ꢆꢉ ꢆꢂ ꢆꢀ ꢆꢑ ꢉꢓ ꢉꢃ ꢉꢁ
ꢀ
ꢉꢅ
ꢉꢍ
ꢉꢆ
ꢉꢉ
ꢉꢂ
ꢉꢀ
ꢉꢑ
ꢂꢓ
ꢂꢃ
ꢂꢁ
ꢂꢅ
ꢂꢍ
0$ꢁ
0$ꢅ
0$ꢍ
0$ꢆ
0&ꢑ
0"ꢁ
0"ꢅ
0"ꢍ
0"ꢆ
0"ꢉ
0"ꢂ
0"ꢀ
0!ꢑ
.234ꢎ0!ꢀ
0!ꢂ
ꢂ
ꢉ
ꢆ
0!ꢉ
0!ꢆ
0!ꢍ
0!ꢅ
ꢍ
ꢅ
ꢁ
0!ꢁ
ꢃ
6
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ꢓ
6$$ꢀ
6$$!
62%&ꢏ
ꢀꢑ
ꢀꢀ
ꢀꢂ
ꢀꢉ ꢀꢆ ꢀꢍ ꢀꢅ ꢀꢁ ꢀꢃ ꢀꢓ ꢂꢑ ꢂꢀ ꢂꢂ ꢂꢉ ꢂꢆ
AIꢀꢁꢃꢉꢂ
1. Pin 13 is reserved and must be tied to VDD
.
2. The above figure shows the package top view.
Figure 8. STM8L152C8 48-pin pinout (with LCD)
ꢆꢃ ꢆꢁ ꢆꢅ ꢆꢍ ꢆꢆ ꢆꢉ ꢆꢂ ꢆꢀ ꢆꢑ ꢉꢓ ꢉꢃ ꢉꢁ
ꢀ
ꢉꢅ
ꢉꢍ
ꢉꢆ
ꢉꢉ
ꢉꢂ
ꢉꢀ
ꢉꢑ
ꢂꢓ
ꢂꢃ
ꢂꢁ
ꢂꢅ
ꢂꢍ
0$ꢁ
0$ꢅ
0$ꢍ
0$ꢆ
0&ꢑ
0"ꢁ
0"ꢅ
0"ꢍ
0"ꢆ
0"ꢉ
0"ꢂ
0"ꢀ
0!ꢑ
.234ꢎ0!ꢀ
0!ꢂ
ꢂ
ꢉ
ꢆ
0!ꢉ
0!ꢆ
0!ꢍ
0!ꢅ
ꢍ
ꢅ
ꢁ
0!ꢁ
ꢃ
6
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6$$ꢀ
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ꢀꢑ
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AIꢀꢁꢃꢉꢆ
1. The above figure shows the package top view.
DocID17943 Rev 6
27/134
61
Pin description
STM8L15xx8, STM8L15xR6
Table 4. Legend/abbreviation
I= input, O = output, S = power supply
FT: Five-volt tolerant
Type
Level
Output
Input
HS = high sink/source (20 mA)
float = floating, wpu = weak pull-up
T = true open drain, OD = open drain, PP = push pull
Port and control
configuration
Output
Bold X (pin state after reset release).
Reset state
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Table 5. High density and medium+ density STM8L15x pin description
Pin
number
Input
Output
Pin name
Default alternate function
1
-
-
-
PH0/LCD SEG 36 (3)
PH1/LCD SEG 37 (3)
PH2/LCD SEG 38 (3)
PH3/LCD SEG 39 (3)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
X
X
X
X
X Port H0 LCD segment 36
2
3
4
6
-
-
-
HS
HS
HS
HS
X Port H1 LCD segment 37
X Port H2 LCD segment 38
X Port H3 LCD segment 39
X Reset PA1
-
-
2
2 NRST/PA1(1)
PA2/OSC_IN/
3 [USART1_TX](2)
[SPI1_MISO] (2)
HSE oscillator input /
X Port A2 [USART1 transmit] / [SPI1
master in- slave out] /
7
8
3
4
/
I/O
I/O
X
X
X
X
X
X
HS
HS
X
X
PA3/OSC_OUT/
HSE oscillator output /
X Port A3 [USART1 receive]/ [SPI1
master out/slave in]/
4 [USART1_RX](2)/[
SPI1_MOSI](2)
PA4/TIM2_BKIN/
Timer 2 - break input /
/[Timer 2 - trigger] /
LCD COM 0 / ADC1 input 2/
[Comparator 1 positive input]
[TIM2_ETR](2)
9
5
6
5
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
X Port A4
LCD_COM0(3)/ADC1_IN2
[COMP1_INP]
PA5/TIM3_BKIN/
Timer 3 - break input / [Timer
3 - trigger] / LCD_COM 1 /
ADC1 input 1/ [Comparator
[TIM3_ETR](2)
/
10
6
I/O FT(5)
X Port A5
LCD_COM1(3)/ADC1_IN1/
1 positive input]
[COMP1_INP]
28/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PA6/ADC1_TRIG/
ADC1 - trigger / LCD_COM2
X Port A6 / ADC1 input 0/
11
12
7
8
7 LCD_COM2(3)/ADC1_IN0/ I/O FT(5)
X
X
X
X
X
X
HS
X
X
[COMP1_INP]
[Comparator 1 positive input]
PA7/LCD_SEG0(3)
TIM5_CH1
/
LCD segment 0 /
TIM5 channel 1
8
I/O FT(5)
HS
HS
X Port A7
X Port B0
Timer 2 - channel 1
/LCD segment 10/
ADC1_IN18/
PB0(4)/TIM2_CH1/
39 31 24 LCD_SEG10(3)/ADC1_IN18 I/O FT(5)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
/ [COMP1_INP]
[Comparator 1 positive input]
Timer 3 - channel 1
/ LCD segment 11 /
ADC1_IN17/
PB1/TIM3_CH1/
40 32 25 LCD_SEG11(3)/ADC1_IN17 I/O FT(5)
/ [COMP1_INP]
HS
HS
HS
HS
X Port B1
X Port B2
X Port B3
X Port B4
[Comparator 1 positive input]
Timer 2 - channel 2
/ LCD segment 12 /
ADC1_IN16/ [Comparator 1
positive input]
PB2/
41 33 26 TIM2_CH2/LCD_SEG12(3)/ I/O FT(5)
ADC1_IN16/[COMP1_INP]
Timer 2 - trigger
/ LCD segment 13
/ADC1_IN15/
PB3/TIM2_ETR/
42 34 27 LCD_SEG13(3)/ADC1_IN15 I/O FT(5)
/[COMP1_INP]
[Comparator 1 positive input]
SPI1 master/slave select /
LCD segment 14 /
ADC1_IN14/
PB4(4)/SPI1_NSS/
43 35
-
LCD_SEG14(3)/ADC1_IN14 I/O FT(5)
/[COMP1_INP]
[Comparator 1 positive input]
SPI1 master/slave select /
LCD segment 14 /
X Port B4 ADC1_IN14 /
DAC channel 2 output/
PB4(4)/SPI1_NSS/
LCD_SEG14(3)/ADC1_IN14
-
-
28
-
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
/DAC_OUT2/
[COMP1_INP]
[Comparator 1 positive input]
PB5/SPI1_SCK/
SPI1 clock / LCD segment
X Port B5 15 / ADC1_IN13/
44 36
LCD_SEG15(3)/ADC1_IN13 I/O FT(5)
/ [COMP1_INP]
[Comparator 1 positive input]
DocID17943 Rev 6
29/134
61
Pin description
STM8L15xx8, STM8L15xR6
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PB5/SPI1_SCK/
[SPI1 clock] / LCD segment
15 / ADC1_IN13
/ DAC channel 2 output/
LCD_SEG15(3)/ADC1_IN13
/DAC_OUT2/
-
-
29
I/O FT(5)
X
X
X
X
X
X
HS
X
X
X Port B5
[COMP1_INP]
[Comparator 1 positive input]
SPI1 master out/slave in/
LCD segment 16 /
ADC1_IN12/
PB6/SPI1_MOSI/
45 37
-
LCD_SEG16(3)/ADC1_IN12 I/O FT(5)
HS
HS
HS
X Port B6
/[COMP1_INP]
[Comparator 1 positive input]
SPI1 master out/
slave in / LCD segment 16 /
X Port B6 ADC1_IN12 / DAC channel
2 output/[Comparator 1
positive input]
PB6/SPI1_MOSI/
-
-
30 LCD_SEG16(3)/ADC1_IN12 I/O FT(5)
X
X
X
X
X
X
X
X
/DAC_OUT2/[COMP1_INP]
SPI1 master in- slave out/
LCD segment 17 /
ADC1_IN11/[Comparator 1
PB7/SPI1_MISO/
46 38 31 LCD_SEG17(3)
/
I/O FT(5)
X Port B7
ADC1_IN11/[COMP1_INP]
positive input]
Port C0 I2C1 data
Port C1 I2C1 clock
65 53 37 PC0/I2C1_SDA
I/O FT(5)
I/O FT(5)
X
X
X
X
T(6)
T(6)
66 54 38 PC1/I2C1_SCL
USART1 receive /
LCD segment 22 /
X Port C2 ADC1_IN6/ [Comparator 1
positive input] /Internal
PC2/USART1_RX/
69 57 41 LCD_SEG22/ADC1_IN6/
[COMP1_INP] /VREFINT
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
reference voltage output
PC3/USART1_TX/
USART1 transmit /
X Port C3 LCD segment 23 /
ADC1_IN5
-
-
42 LCD_SEG23(3)
ADC1_IN5
/
USART1 transmit /
LCD segment 23 /
ADC1_IN5 /
PC3/USART1_TX/
LCD_SEG23(3)/ ADC1_IN5/
[COMP2_INM] /
70 58
-
I/O FT(5)
X
X
X
HS
X
X Port C3
[Comparator 2 negative
[COMP1_INP]
input] /[Comparator 1 input
positive]
30/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
USART1 synchronous clock
/ I2C1_SMB / [Configurable
clock output] / LCD segment
PC4/USART1_CK/
I2C1_SMB/ [CCO](2)
/
71 59
-
LCD_SEG24(3)
/
I/O FT(5)
X
X
X
X
X
X
HS
X
X
X Port C4 24 / ADC1_IN4 /
ADC1_IN4/[COMP2_INM]
/[COMP1_INP]
[Comparator 2 negative
input] / [Comparator 1
positive input]
USART1 synchronous clock
/ I2C1_SMB / [Configurable
clock output] / LCD segment
24 / ADC1_IN4 /
PC4/USART1_CK/
I2C1_SMB/[CCO](2)
/
LCD_SEG24(3)/ADC1_IN4/
[COMP2_INM] /
-
-
43
I/O FT(5)
HS
X Port C4
[Comparator 2 negative
input] / [Comparator 1
positive input] /
[COMP1_INP] /
[LCD_COM4]
[LCD_COM4](3)
PC5/OSC32_IN
LSE oscillator input / [SPI1
X Port C5 master/slave select] /
72 60 44 /[SPI1_NSS](2)
/
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
[USART1_TX](2)
[USART1 transmit]
PC6/OSC32_OUT/
LSE oscillator output / [SPI1
X Port C6
73 61 45 [SPI1_SCK](2)
/
clock] / [USART1 receive]
[USART1_RX](2)
LCD segment 25
/ADC1_IN3/ [Comparator 2
negative input] /
[Comparator 1 positive input]
PC7/LCD_SEG25(3)
/
74 62
-
ADC1_IN3/[COMP2_INM] I/O FT(5)
/ [COMP1_INP]
X
X
X
X
X
X
HS
HS
X
X
X Port C7
LCD segment 25
/ADC1_IN3/ USART3
synchronous clock/
PC7/LCD_SEG25(3)
ADC1_IN3/USART3_CK/
46 [COMP2_INM] /
[COMP1_INP] /
[LCD_COM5]
/
-
-
I/O FT(5)
X Port C7
[Comparator 2 negative
input] / [Comparator 1
positive input]/
[LCD_COM5](3)
DocID17943 Rev 6
31/134
61
Pin description
STM8L15xx8, STM8L15xR6
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PD0/TIM3_CH2/
Timer 3 - channel 2 /
[ADC1_Trigger] / LCD
segment 7 / ADC1_IN22 /
[Comparator 2 positive input]
[ADC1_TRIG](2)
/
29 25 20
30 26 21
I/O FT(5)
X
X
X
X
X
X
HS
X
X
X Port D0
LCD_SEG7(3)/ADC1_IN22/
[COMP2_INP]
Timer 3 - trigger /
LCD_COM3 / ADC1_IN21 /
X Port D1 [Comparator 1 positive input]
/[Comparator 2 positive
input]
PD1/TIM3_ETR/
LCD_COM3(3)/ADC1_IN21/
[COMP1_INP]//
I/O FT(5)
HS
[COMP2_INP]
PD2/TIM1_CH1
Timer 1 - channel 1 / LCD
X Port D2 segment 8 / ADC1_IN20/
[Comparator 1 positive input]
31 27 22 /LCD_SEG8(3)/ADC1_IN20/ I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
[COMP1_INP]
PD3/ TIM1_ETR/
Timer 1 - trigger /
LCD_SEG9(3)
ADC1_IN19/
/
LCD segment 9 /
ADC1_IN19/ [Comparator 1
32 28 23
I/O FT(5)
I/O FT(5)
X Port D3
[COMP1_INP]
positive input]
PD4/TIM1_CH2
Timer 1 - channel 2 / LCD
X Port D4 segment 18 / ADC1_IN10/
[Comparator 1 positive input]
/LCD_SEG18(3)
ADC1_IN10/
/
57 45
-
X
X
X
X
X
X
HS
HS
X
X
[COMP1_INP]
Timer 1 - channel 2 / LCD
segment 18 /
X Port D4 ADC1_IN10/SPI2 master
in/slave out/ [Comparator 1
positive input]
PD4/TIM1_CH2
/LCD_SEG18(3)
/
-
-
33
I/O FT(5)
ADC1_IN10/SPI2_MISO/
[COMP1_INP]
PD5/TIM1_CH3
Timer 1 - channel 3 / LCD
X Port D5 segment 19 / ADC1_IN9/
[Comparator 1 positive input]
/LCD_SEG19(3)
ADC1_IN9/
/
58 46
-
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
[COMP1_INP]
PD5/TIM1_CH3
Timer 1 - channel 3 / LCD
/LCD_SEG19(3)
/
segment 19 / ADC1_IN9/
SPI2 master out/slave in/
-
-
34
X Port D5
ADC1_IN9/SPI2_MOSI/
[COMP1_INP]
[Comparator 1 positive input]
32/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
X Port D6 RTCcalibration/[Comparator
1 positive input]/Internal
PD6/TIM1_BKIN
/LCD_SEG20(3)
/
59 47
I/O FT(5)
X
X
X
X
X
X
HS
X
X
ADC1_IN8/RTC_CALIB/
[COMP1_INP]/VREFINT
reference voltage output
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
RTC calibration/SPI2 clock/
[Comparator 1 positive
input]/Internal reference
PD6/TIM1_BKIN
/LCD_SEG20(3)
/
-
-
35 ADC1_IN8/RTC_CALIB/
SPI2_SCK/[COMP1_INP]/
VREFINT
I/O FT(5)
HS
HS
X Port D6
voltage output
Timer 1 - inverted channel 1/
LCD segment 21 /
ADC1_IN7 / RTC
alarm/[Comparator 1
positive input]/Internal
PD7/TIM1_CH1N
/LCD_SEG21(3)
/
60 48
-
I/O FT(5)
X
X
X
X
X
X
X
X
X Port D7
ADC1_IN7/RTC_ALARM/
[COMP1_INP]/VREFINT
reference voltage output
Timer 1 - inverted channel 1/
LCD segment 21 /
ADC1_IN7 / RTC alarm
X Port D7 /SPI2 master/slave
select/[Comparator 1
PD7/TIM1_CH1N
/LCD_SEG21(3)
/
ADC1_IN7/RTC_ALARM
/SPI2_NSS/[COMP1_INP]/
-
-
36
I/O FT(5)
HS
positive input]/Internal
VREFINT
reference voltage output
PG4/LCD_SEG32/
SPI2_NSS
LCD segment 32 /
X Port G4
61 49
62 50
63 51
64 52
-
-
-
-
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
X
X
X
X
X
X
HS
HS
HS
HS
X
X
X
X
SPI2 master/slave select
PG5/LCD_SEG33/
SPI2_SCK
LCD segment 33 /
X Port G5
SPI2 clock
PG6/LCD_SEG34/
SPI2_MOSI
LCD segment 34 /
X Port G6
SPI2 master out- slave in
PG7/LCD_SEG35/
SPI2_MISO
LCD segment 35 /
X Port G7
SPI2 master in- slave out
DocID17943 Rev 6
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61
Pin description
STM8L15xx8, STM8L15xR6
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PE0/LCD_SEG1(3)
TIM5_CH2
/
LCD segment 1/
Timer 5 channel 2
23 19 14
24 20 15
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
X
X
X Port E0
PE1/TIM1_CH2N
/LCD_SEG2(3)
Timer 1 - inverted channel 2
/ LCD segment 2
HS
HS
X Port E1
Timer 1 - inverted channel 3
X Port E2 / LCD segment 3 /
[Configurable clock output]
PE2/TIM1_CH3N
25 21 16
I/O FT(5)
X
X
X
X
/LCD_SEG3(3)/ [CCO](2)
26
-
-
-
PE3/LCD_SEG4(3)
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
X Port E3 LCD segment 4
PE3/LCD_SEG4(3)
USART2_RX
/
LCD segment 4/
X Port E3
22 17
USART2 receive
PE4/LCD_SEG5(3)
DAC_TRIG1
/
LCD segment 5/
X Port E4
27
-
-
-
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
DAC 1 trigger
LCD segment 5/
X Port E4 DAC 2 trigger/
USART2 transmit
PE4/LCD_SEG5(3)
/
23 18
DAC_TRIG2/USART2_TX
LCD segment 6 /
ADC1_IN23/ [Comparator 1
positive input] /[Comparator
2 positive input]
PE5/LCD_SEG6(3)
/
28
-
-
ADC1_IN23/[COMP1_INP]/ I/O FT(5)
X
X
X
X
X
X
X
X
X
HS
HS
HS
X
X
X
X Port E5
[COMP2_INP]
LCD segment 6 /
ADC1_IN23/ [Comparator 1
X Port E5 positive input] / [Comparator
2 positive input] /USART2
synchronous clock
PE5/LCD_SEG6(3)
/
ADC1_IN23/[COMP1_INP]/
[COMP2_INP] /
USART2_CK
-
24 19
I/O FT(5)
PE6/LCD_SEG26(3)
/
LCD segment 26 /PVD_IN
X Port E6 /TIM5 break input / USART3
transmit/[LCD_COM6](3)
PVD_IN/TIM5_BKIN/
USART3_TX/
-
-
47
I/O FT(5)
[LCD_COM6](3)
PE6/LCD_SEG26(3)
PVD_IN/TIM5_BKIN
/
LCD segment 26 /PVD_IN
X Port E6
75 63
76 64
-
-
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
/TIM5 break input
PE7/LED_SEG27/
TIM5_ETR
LCD segment 27/
X Port E7
TIM5 trigger
34/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
LCD segment 27/
TIM5 trigger/
PE7/LED_SEG27/
-
-
-
48 TIM5_ETR/USART3_RX/
I/O FT(5)
I/O FT(5)
X
X
X
X
X
HS
X
X
X Port E7
USART3 receive/
[LCD_COM7](3)
[LCD_COM7](3)
RTC tamper 1 input
X Port I0 [SPI2 master/slave select]
PI0/RTC_TAMP1/
[SPI2_NSS]/[TIM3_CH3]
77
-
HS
[TIM3 channel 3]
PI1/RTC_TAMP2/
[SPI2_SCK]
RTC tamper 2 input
X Port I1
78
79
-
-
-
I/O FT(5)
I/O FT(5)
X
X
X
X
HS
HS
X
X
[SPI2 clock]
PI2/RTC_TAMP3/
[SPI2_MOSI]
RTC tamper 3 input
X Port I2
-
[SPI2 master out- slave in]
TIM5 Channel 1
[SPI2 master in- slave out]
[TIM3 channel 2]
PI3/TIM5_CH1/
[SPI2_MISO]/[TIM3_CH2]
80
-
-
I/O FT(5)
X
X
HS
X
X Port I3
PF0/ADC1_IN24/
32
-
-
-
I/O
I/O
X
X
X
X
X
X
HS
HS
X
X
X Port F0 ADC1_IN24 / DAC 1 output
DAC_OUT1
PF0/ADC1_IN24/
ADC1_IN24 / DAC 1 output/
X Port F0
39
-
[USART3 transmit]
DAC_OUT1/[USART3_TX]
PF0/ADC1_IN24/
DAC_OUT1/
[USART3_TX]/[SPI1_MISO]
ADC1_IN24 / DAC 1 output/
X Port F0 [USART3 transmit]
[SPI1 master in- slave out]
49
50
-
-
-
-
I/O
I/O
X
X
X
X
X
X
HS
HS
X
X
PF1/ADC1_IN25/
DAC_OUT2/
[USART3_RX]/
[SPI1_MOSI]
ADC1_IN25/
DAC channel 2 output/
[USART3 receive]
X Port F1
[SPI1 master out- slave in]
PF1/ADC1_IN25/
DAC_OUT2/
[USART3_RX]
ADC1_IN25/
X Port F1 DAC channel 2 output/
[USART3 receive]
-
40
-
-
-
I/O
I/O
X
X
X
X
X
X
HS
HS
X
X
PF2/ADC1_IN26/
[SPI2_SCK]/
[USART3_SCK]
ADC1_IN26
X Port F2 [SPI2 clock]
[USART3 clock]
51
DocID17943 Rev 6
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61
Pin description
STM8L15xx8, STM8L15xR6
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PF3/ADC1_IN27/
[SPI1_NSS]
ADC1_IN27
[SPI1 master/slave select]
52
-
41
-
-
I/O
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HS
X
X
X
X
X
X
X
X
X
X Port F3
PF4/LCD_SEG36/
LCD segment 36/
-
53
-
-
-
-
-
-
-
-
-
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
I/O FT(5)
HS
HS
HS
HS
HS
HS
HS
HS
X Port F4
X Port F4
X Port F5
X Port F5
X Port F6
X Port F6
X Port F7
X Port F7
[LCD _COM4](9)
[LCD_COM4](9)
PF4/LCD_SEG40/
[LCD_COM4]
LCD segment 40/
[LCD_COM4](9)
PF5/LCD_SEG37/
LCD segment 37/
42
-
[LCD_COM5](9)
[LCD COM5](9)
PF5/LCD_SEG41/
[LCD_COM5]
LCD segment 41/
54
-
[LCD COM5](9)
PF6/LCD_SEG38
LCD segment 38/
43
-
/[LCD_COM6](9)
[LCD COM6](9)
PF6/LCD_SEG42/
[LCD_COM6]
LCD segment 42/
55
-
[LCD COM6](9)
PF7/LCD_SEG39/
LCD segment 39/
44
[LCD_COM7](9)
[LCD COM7](9)
PF7/LCD_SEG43/
[LCD_COM7]
LCD segment 43/
56
-
[LCD COM7](9)
22 18 13 VLCD(7)
S
S
LCD booster external capacitor
Digital power supply
I/O ground
15 11 10 VDD1
14 10
- VSS1
16 12 11 VDDA
S
S
Analog supply voltage
ADC1 and DAC1/2 positive voltage
reference
17 13 12 VREF+/VREF+_DAC
PG0/LCD SEG28(3)
LCD segment 28/
X Port G0 USART3 receive /
[Timer 2 - break input]
18 14
-
/USART3_RX/
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
[TIM2_BKIN]
PG1/LCD SEG29(3)
/USART3_TX/
[TIM3_BKIN]
LCD segment 29/
X Port G1 USART3 transmit /
[Timer 3 -break input]
19 15
-
36/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Pin description
Table 5. High density and medium+ density STM8L15x pin description (continued)
Pin
number
Input
Output
Pin name
Default alternate function
PG2/LCD_SEG30(3)
USART3_CK
/
LCD segment 30/
USART 3 synchronous clock
20 16
21 17
-
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
X
X
X Port G2
X Port G3
PG3/LCD SEG 31 (3)
[TIM3_ETR]
/
LCD segment 31/
[Timer 3 - trigger]
-
HS
33
34
PH4/USART2_RX
PH5/USART2_TX
I/O FT(5)
I/O FT(5)
X
X
X
X
X
X
HS
HS
X
X
X Port H4 USART2 receive
X Port H5 USART2 transmit
PH6/USART2_CK/
TIM5_CH1
USART2 synchronous
X Port H6
35
36
-
I/O FT(5)
I/O FT(5)
S
X
X
X
X
X
X
HS
HS
X
X
clock/ Timer 5 - channel 1
PH7/TIM5_CH2
X Port H7 Timer 5 - channel 2
I/O ground / Analog ground voltage /
ADC1 negative voltage reference
9 VSS /VSSA /VREF-
Analog ground voltage /
ADC1 negative voltage reference
13
9
-
VSSA /VREF-
S
37 29
38 30
-
-
VDD3
VSS3
S
S
IOs supply voltage
IOs ground voltage
[USART1 synchronous
PA0(8)/[USART1_CK](2)
/
clock](2)/ SWIM input and
X Port A0
5
1
1
I/O
X
X
X
HS
X
SWIM/BEEP/IR_TIM (9)
output / Beep output / Infra-
red Timer output
IOs ground voltage
IOs supply voltage
IOs ground voltage
IOs supply voltage
68 56 40 VSS2
67 55 39 VDD2
48
47
-
-
-
-
VSS4
VDD4
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output push-pull, not as output open-drain nor as a general purpose input. Refer to Section Configuring
NRST/PA1 pin as general purpose output in the STM8L15xx and STM8L16xx reference manual (RM0031).
2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
3. Available on STM8L152xx devices only.
4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
DocID17943 Rev 6
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61
Pin description
STM8L15xx8, STM8L15xR6
5. In the 5 V tolerant I/Os, the protection diode to VDD is not implemented.
6. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
7. Available on STM8L152xx devices only. On STM8L151xx devices it is reserved and must be tied to VDD
8. The PA0 pin is in input pull-up during the reset phase and after reset release.
9. High Sink LED driver capability available on PA0.
.
Note:
Slope control of all GPIO pins can be programmed except true open drain pins and by
default is limited to 2 MHz.
System configuration options
As shown in Table 5: High density and medium+ density STM8L15x pin description, some
alternate functions can be remapped on different I/O ports by programming one of the two
remapping registers described in the “Routing interface (RI) and system configuration
controller” section in the STM8L05xx, STM8L15xx and STM8L16xx reference manual
(RM0031).
38/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
5
Memory and register map
5.1
Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
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2ESET AND INTERRUPT VECTORS
2)
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1. Refer to Table 9 for an overview of hardware register mapping, to Table 8 for details on I/O port hardware
registers, and to Table 10 for information on CPU/SWIM/debug module controller registers.
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 6. Flash and RAM boundary addresses
Memory area
Size
Start address
0x00 0000
End address
0x00 07FF
0x00 0FFF
2 Kbytes
4 Kbytes
RAM
0x00 0000
32 Kbytes
64 Kbytes
0x00 8000
0x00 8000
0x00 FFFF
0x01 7FFF
Flash program memory
5.2
Register map
Table 7. Factory conversion registers
Reset
status
Address
Block
Register label
Register name
VREFINT_Factory_
CONV(1)
Internal reference voltage factory
0x00 4910
0x00 4911
-
-
0xXX
0xXX
conversion
TS_Factory_CONV_
V90(2)
Temperature sensor output voltage
1. The VREFINT_Factory_CONV byte represents the 8 LSB of the result of the VREFINT 12-bit ADC conversion performed in
factory. The 2 MSB have a fixed value: 0x6.
2. The TS_Factory_CONV_V90 byte represents the 8 LSB of the result of the V90 12-bit ADC conversion performed in factory.
The 2 MSB have a fixed value: 0x3.
Table 8. I/O port hardware register map
Reset
Address
Block
Register label
Register name
status
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
PA_ODR
PA_IDR
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
0x00
0xXX
0x00
0x01
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
Port A
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C
Port C control register 2
40/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 8. I/O port hardware register map (continued)
Reset
status
Address
Block
Register label
Register name
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
0x00
0xXX
0x00
0x00
0x00
Port D
Port D control register 2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E
Port F
Port G
Port H
Port I
Port E control register 2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
Port F control register 2
Port F data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
Port G control register 2
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
Port H control register 2
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
PI_DDR
PI_CR1
PI_CR2
Port I control register 2
DocID17943 Rev 6
41/134
61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map
Register label
Address
Block
Register name
Reset status
0x00 502E
to
Reserved area (28 bytes)
0x00 5049
0x00 5050
0x00 5051
FLASH_CR1
FLASH_CR2
Flash control register 1
0x00
0x00
Flash control register 2
Flash program memory unprotection key
register
0x00 5052
0x00 5053
0x00 5054
FLASH _PUKR
FLASH _DUKR
FLASH _IAPSR
0x00
0x00
0x00
Flash
Data EEPROM unprotection key register
Flash in-application programming status
register
0x00 5055
to
Reserved area (27 bytes)
0x00 506F
DMA1 global configuration & status
register
0x00 5070
0x00 5071
DMA1_GCSR
DMA1_GIR1
0xFC
0x00
DMA1 global interrupt register 1
Reserved area (3 bytes)
0x00 5072 to
0x00 5074
0x00 5075
0x00 5076
DMA1_C0CR
DMA1 channel 0 configuration register
DMA1 channel 0 status & priority register
0x00
0x00
DMA1_C0SPR
DMA1 number of data to transfer register
(channel 0)
0x00 5077
0x00 5078
DMA1_C0NDTR
DMA1_C0PARH
DMA1_C0PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 0)
DMA1 peripheral address low register
(channel 0)
0x00 5079
0x00 507A
0x00 507B
DMA1
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 0)
DMA1_C0M0ARH
DMA1_C0M0ARL
0x00
0x00
DMA1 memory 0 address low register
(channel 0)
0x00 507C
0x00 507D to
0x00 507E
Reserved area (2 bytes)
0x00 507F
0x00 5080
DMA1_C1CR
DMA1 channel 1 configuration register
DMA1 channel 1 status & priority register
0x00
0x00
DMA1_C1SPR
DMA1 number of data to transfer register
(channel 1)
0x00 5081
0x00 5082
0x00 5083
DMA1_C1NDTR
DMA1_C1PARH
DMA1_C1PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 1)
DMA1 peripheral address low register
(channel 1)
DMA1
42/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reserved area (1 byte)
Reset status
0x00 5084
DMA1 memory 0 address high register
(channel 1)
0x00 5085
0x00 5086
DMA1_C1M0ARH
DMA1_C1M0ARL
0x00
0x00
DMA1
DMA1 memory 0 address low register
(channel 1)
0x00 5087
0x00 5088
Reserved area (2 bytes)
0x00 5089
0x00 508A
DMA1_C2CR
DMA1 channel 2 configuration register
DMA1 channel 2 status & priority register
0x00
0x00
DMA1_C2SPR
DMA1 number of data to transfer register
(channel 2)
0x00 508B
0x00 508C
DMA1_C2NDTR
DMA1_C2PARH
DMA1_C2PARL
0x00
0x52
0x00
DMA1 peripheral address high register
(channel 2)
DMA1
DMA1 peripheral address low register
(channel 2)
0x00 508D
0x00 508E
0x00 508F
Reserved area (1 byte)
DMA1 memory 0 address high register
(channel 2)
DMA1_C2M0ARH
DMA1_C2M0ARL
0x00
0x00
DMA1 memory 0 address low register
(channel 2)
0x00 5090
0x00 5091
0x00 5092
Reserved area (2 bytes)
0x00 5093
0x00 5094
DMA1_C3CR
DMA1 channel 3 configuration register
DMA1 channel 3 status & priority register
0x00
0x00
DMA1_C3SPR
DMA1 number of data to transfer register
(channel 3)
0x00 5095
0x00 5096
0x00 5097
0x00 5098
0x00 5099
0x00 509A
DMA1_C3NDTR
0x00
0x40
0x00
0x00
0x00
0x00
DMA1_C3PARH_
C3M1ARH
DMA1 peripheral address high register
(channel 3)
DMA1_C3PARL_
C3M1ARL
DMA1 peripheral address low register
(channel 3)
DMA1
DMA channel 3 memory 0 extended
address register
DMA_C3M0EAR
DMA1_C3M0ARH
DMA1_C3M0ARL
DMA1 memory 0 address high register
(channel 3)
DMA1 memory 0 address low register
(channel 3)
0x00 509B to
0x00 509C
Reserved area (3 bytes)
DocID17943 Rev 6
43/134
61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 509D
0x00 509E
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2
0x00 50A3
0x00 50A4
0x00 50A5
0x00 50A6
0x00 50A7
0x00 50A8
0x00 50A9
0x00 50AA
0x00 50AB
SYSCFG_RMPCR3
Remapping register 3
Remapping register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
SYSCFG SYSCFG_RMPCR1
SYSCFG_RMPCR2
EXTI_CR1
Remapping register 2
External interrupt control register 1
External interrupt control register 2
External interrupt control register 3
External interrupt status register 1
External interrupt status register 2
External interrupt port select register 1
WFE control register 1
EXTI_CR2
EXTI_CR3
ITC - EXTI
EXTI_SR1
EXTI_SR2
EXTI_CONF1
WFE_CR1
WFE_CR2
WFE
WFE control register 2
WFE_CR3
WFE control register 3
WFE_CR4
WFE control register 4
EXTI_CR4
ITC - EXTI
External interrupt control register 4
External interrupt port select register 2
EXTI_CONF2
0x00 50A9
to
Reserved area (7 bytes)
0x00 50AF
0x00 50B0
0x00 50B1
0x00 50B2
0x00 50B3
RST_CR
Reset control register
Reset status register
0x00
0x01
0x00
0x00
RST
RST_SR
PWR_CSR1
PWR
Power control and status register 1
Power control and status register 2
PWR_CSR2
0x00 50B4
to
Reserved area (12 bytes)
0x00 50BF
0x00 50C0
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
CLK_CKDIVR
CLK_CRTCR
CLK_ICKCR
Clock master divider register
Clock RTC register
0x03
0x00(1)
0x11
Internal clock control register
Peripheral clock gating register 1
Peripheral clock gating register 2
Configurable clock control register
External clock control register
System clock status register
System clock switch register
Clock switch control register
CLK_PCKENR1
0x00
0x00
0x00
0x00
0x01
0x01
0xX0
CLK_PCKENR2
CLK
CLK_CCOR
CLK_ECKCR
CLK_SCSR
CLK_SWR
CLK_SWCR
44/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 50CA
0x00 50CB
0x00 50CC
0x00 50CD
0x00 50CE
0x00 50CF
0x00 50D0
CLK_CSSR
CLK_CBEEPR
CLK_HSICALR
CLK_HSITRIMR
CLK_HSIUNLCKR
CLK_REGCSR
CLK_PCKENR3
Clock security system register
Clock BEEP register
0x00
0x00
HSI calibration register
0xXX
CLK
HSI clock calibration trimming register
HSI unlock register
0x00
0x00
Main regulator control status register
Peripheral clock gating register 3
0bxx11 100X
0x00
0x00 50D1
to
Reserved area (2 bytes)
0x00 50D2
0x00 50D3
0x00 50D4
WWDG_CR
WWDG_WR
WWDG control register
WWDR window register
0x7F
0x7F
WWDG
0x00 50D5
to
Reserved area (11 bytes)
00 50DF
0x00 50E0
0x00 50E1
0x00 50E2
IWDG_KR
IWDG_PR
IWDG_RLR
IWDG key register
IWDG prescaler register
IWDG reload register
0xXX
0x00
0xFF
IWDG
0x00 50E3
to
Reserved area (13 bytes)
0x00 50EF
0x00 50F0
BEEP_CSR1
BEEP_CSR2
BEEP control/status register 1
Reserved area (2 bytes)
0x00
0x1F
0x00 50F1
0x00 50F2
BEEP
0x00 50F3
BEEP control/status register 2
Reserved area (76 bytes)
0x00 50F4
to0x00 513F
0x00 5140
0x00 5141
0x00 5142
0x00 5143
0x00 5144
0x00 5145
0x00 5146
0x00 5147
RTC_TR1
RTC_TR2
RTC_TR3
Time register 1
Time register 2
0x00
0x00
0x00
RTC
RTC
Time register 3
Reserved area (1 byte)
Date register 1
RTC_DR1
RTC_DR2
RTC_DR3
0x01
0x21
0x00
Date register 2
Date register 3
Reserved area (1 byte)
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5148
0x00 5149
0x00 514A
0x00 514B
0x00 514C
0x00 514D
RTC_CR1
RTC_CR2
RTC_CR3
Control register 1
Control register 2
0x00(1)
0x00(1)
0x00(1)
Control register 3
RTC
Reserved area (1 byte)
Initialization and status register 1
Initialization and Status register 2
RTC_ISR1
RTC_ISR2
0x01
0x00
0x00 514E
0x00 514F
Reserved area (2 bytes)
0x00 5150
0x00 5151
0x00 5152
0x00 5153
0x00 5154
0x00 5155
0x00 5156
0x00 5157
0x00 5158
0x00 5159
0x00 5158
0x00 5159
0x00 515A
0x00 515B
0x00 515C
0x00 515D
0x00 515E
0x00 515F
RTC_SPRERH
RTC_SPRERL
RTC_APRER
Synchronous prescaler register high
Synchronous prescaler register low
Asynchronous prescaler register
Reserved area (1 byte)
Wakeup timer register high
Wakeup timer register low
Reserved area (1 byte)
Subsecond register low
Subsecond register high
Write protection register
Subsecond register high
Write protection register
Shift register high
0x00(1)
0xFF(1)
0x7F(1)
RTC
RTC
RTC_WUTRH
RTC_WUTRL
0xFF(1)
0xFF(1)
RTC_SSRL
RTC_SSRH
0x00
0x00
RTC_WPR
0x00
RTC_SSRH
0x00
RTC_WPR
0x00
RTC
RTC_SHIFTRH
RTC_SHIFTRL
RTC_ALRMAR1
RTC_ALRMAR2
RTC_ALRMAR3
RTC_ALRMAR4
0x00
Shift register low
0x00
Alarm A register 1
0x00(1)
0x00(1)
0x00(1)
0x00(1)
Alarm A register 2
Alarm A register 3
Alarm A register 4
0x00 5160 to
0x00 5163
Reserved area (4 bytes)
0x00 5164
0x00 5165
RTC_ALRMASSRH
RTC_ALRMASSRL
Alarm A subsecond register high
Alarm A subsecond register low
0x00(1)
0x00(1)
RTC
RTC_ALRMASSMS
KR
0x00 5166
Alarm A masking register
Reserved area (3 bytes)
0x00(1)
0x00 5167 to
0x00 5169
46/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 516A
0x00 516B
0x00 516C
0x00 516D
RTC_CALRH
RTC_CALRL
RTC_TCR1
RTC_TCR2
Calibration register high
Calibration register low
Tamper control register 1
Tamper control register 2
0x00(1)
0x00(1)
0x00(1)
0x00(1)
RTC
0x00 516E to
0x00 518A
Reserved area
0x00 5190
CSSLSE
CSSLSE_CSR
CSS on LSE control and status register
Reserved area
0x00(1)
0x00 519A to
0x00 51FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
SPI1_CR1
SPI1_CR2
SPI1 control register 1
SPI1 control register 2
SPI1 interrupt control register
SPI1 status register
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
SPI1_ICR
SPI1_SR
SPI1
SPI1_DR
SPI1 data register
SPI1_CRCPR
SPI1_RXCRCR
SPI1_TXCRCR
SPI1 CRC polynomial register
SPI1 Rx CRC register
SPI1 Tx CRC register
0x00 5208
to
Reserved area (8 bytes)
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E
I2C1_CR1
I2C1_CR2
I2C1 control register 1
I2C1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0X
0x00
0x00
0x00
0x02
0x00
I2C1_FREQR
I2C1_OARL
I2C1_OARH
I2C1_OARH
I2C1_DR
I2C1 frequency register
I2C1 own address register low
I2C1 own address register high
I2C1 own address register for dual mode
I2C1 data register
I2C1
I2C1_SR1
I2C1 status register 1
I2C1_SR2
I2C1 status register 2
I2C1_SR3
I2C1 status register 3
I2C1_ITR
I2C1 interrupt control register
I2C1 clock control register low
I2C1 clock control register high
I2C1 TRISE register
I2C1_CCRL
I2C1_CCRH
I2C1_TRISER
I2C1_PECR
I2C1 packet error checking register
DocID17943 Rev 6
47/134
61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 521F
to
Reserved area (17 bytes)
0x00 522F
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5237
0x00 5238
0x00 5239
0x00 523A
USART1_SR
USART1_DR
USART1 status register
USART1 data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
USART1_BRR1
USART1_BRR2
USART1_CR1
USART1_CR2
USART1_CR3
USART1_CR4
USART1_CR5
USART1_GTR
USART1_PSCR
USART1 baud rate register 1
USART1 baud rate register 2
USART1 control register 1
USART1 control register 2
USART1 control register 3
USART1 control register 4
USART1 control register 5
USART1 guard time register
USART1 prescaler register
USART1
0x00 523B
to
Reserved area (21 bytes)
0x00 524F
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
TIM2_CR1
TIM2_CR2
TIM2 control register 1
TIM2 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
TIM2_SMCR
TIM2_ETR
TIM2 Slave mode control register
TIM2 external trigger register
TIM2 DMA1 request enable register
TIM2 interrupt enable register
TIM2 status register 1
TIM2_DER
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2 status register 2
TIM2_EGR
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare enable register 1
TIM2 counter high
TIM2
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCER1
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
48/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_BKR
TIM2 capture/compare register 1 low
TIM2 capture/compare register 2 high
TIM2 capture/compare register 2 low
TIM2 break register
0x00
0x00
0x00
0x00
0x00
TIM2
TIM2_OISR
TIM2 output idle state register
0x00 5267 to
0x00 527F
Reserved area (25 bytes)
0x00 5280
0x00 5281
0x00 5282
0x00 5283
0x00 5284
0x00 5285
0x00 5286
0x00 5287
0x00 5288
0x00 5289
0x00 528A
0x00 528B
0x00 528C
0x00 528D
0x00 528E
0x00 528F
0x00 5290
0x00 5291
0x00 5292
0x00 5293
0x00 5294
0x00 5295
0x00 5296
TIM3_CR1
TIM3_CR2
TIM3 control register 1
TIM3 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM3_SMCR
TIM3_ETR
TIM3 Slave mode control register
TIM3 external trigger register
TIM3 DMA1 request enable register
TIM3 interrupt enable register
TIM3 status register 1
TIM3_DER
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3 status register 2
TIM3_EGR
TIM3 event generation register
TIM3 Capture/Compare mode register 1
TIM3 Capture/Compare mode register 2
TIM3 Capture/Compare enable register 1
TIM3 counter high
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM3_BKR
TIM3
TIM3 counter low
TIM3 prescaler register
TIM3 Auto-reload register high
TIM3 Auto-reload register low
TIM3 Capture/Compare register 1 high
TIM3 Capture/Compare register 1 low
TIM3 Capture/Compare register 2 high
TIM3 Capture/Compare register 2 low
TIM3 break register
TIM3_OISR
TIM3 output idle state register
0x00 5297 to
0x00 52AF
Reserved area (25 bytes)
DocID17943 Rev 6
49/134
61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 52B0
0x00 52B1
0x00 52B2
0x00 52B3
0x00 52B4
0x00 52B5
0x00 52B6
0x00 52B7
0x00 52B8
0x00 52B9
0x00 52BA
0x00 52BB
0x00 52BC
0x00 52BD
0x00 52BE
0x00 52BF
0x00 52C0
0x00 52C1
0x00 52C2
0x00 52C3
0x00 52C4
0x00 52C5
0x00 52C6
0x00 52C7
0x00 52C8
0x00 52C9
0x00 52CA
0x00 52CB
0x00 52CC
0x00 52CD
0x00 52CE
0x00 52CF
0x00 52D0
0x00 52D1
TIM1_CR1
TIM1_CR2
TIM1 control register 1
TIM1 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM1_SMCR
TIM1_ETR
TIM1 Slave mode control register
TIM1 external trigger register
TIM1_DER
TIM1 DMA1 request enable register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1 status register 2
TIM1_EGR
TIM1 event generation register
TIM1 Capture/Compare mode register 1
TIM1 Capture/Compare mode register 2
TIM1 Capture/Compare mode register 3
TIM1 Capture/Compare mode register 4
TIM1 Capture/Compare enable register 1
TIM1 Capture/Compare enable register 2
TIM1 counter high
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1 counter low
TIM1
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 Auto-reload register high
TIM1 Auto-reload register low
TIM1 Repetition counter register
TIM1 Capture/Compare register 1 high
TIM1 Capture/Compare register 1 low
TIM1 Capture/Compare register 2 high
TIM1 Capture/Compare register 2 low
TIM1 Capture/Compare register 3 high
TIM1 Capture/Compare register 3 low
TIM1 Capture/Compare register 4 high
TIM1 Capture/Compare register 4 low
TIM1 break register
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1 dead-time register
TIM1_OISR
TIM1_DCR1
TIM1 output idle state register
DMA1 control register 1
50/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 52D2
0x00 52D3
TIM1_DCR2
TIM1 DMA1 control register 2
0x00
0x00
TIM1
TIM1_DMA1R
TIM1 DMA1 address for burst mode
0x00 52D4
to
Reserved area (12 bytes)
0x00 52DF
0x00 52E0
0x00 52E1
0x00 52E2
0x00 52E3
0x00 52E4
0x00 52E5
0x00 52E6
0x00 52E7
0x00 52E8
0x00 52E9
TIM4_CR1
TIM4_CR2
TIM4_SMCR
TIM4_DER
TIM4_IER
TIM4 control register 1
TIM4 control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TIM4 Slave mode control register
TIM4 DMA1 request enable register
TIM4 Interrupt enable register
TIM4 status register 1
TIM4
TIM4_SR1
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
TIM4 Event generation register
TIM4 counter
TIM4 prescaler register
TIM4 Auto-reload register
0x00 52EA
to
Reserved area (21 bytes)
0x00 52FE
0x00 52FF
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
0x00 530F
IRTIM
IR_CR
Infrared control register
TIM5 control register 1
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
TIM5_CR1
TIM5_CR2
TIM5 control register 2
TIM5_SMCR
TIM5_ETR
TIM5 Slave mode control register
TIM5 external trigger register
TIM5 DMA1 request enable register
TIM5 interrupt enable register
TIM5 status register 1
TIM5_DER
TIM5_IER
TIM5_SR1
TIM5_SR2
TIM5 status register 2
TIM5
TIM5_EGR
TIM5_CCMR1
TIM5_CCMR2
TIM5_CCER1
TIM5_CNTRH
TIM5_CNTRL
TIM5_PSCR
TIM5_ARRH
TIM5 event generation register
TIM5 Capture/Compare mode register 1
TIM5 Capture/Compare mode register 2
TIM5 Capture/Compare enable register 1
TIM5 counter high
TIM5 counter low
TIM5 prescaler register
TIM5 Auto-reload register high
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5310
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315
0x00 5316
TIM5_ARRL
TIM5_CCR1H
TIM5_CCR1L
TIM5_CCR2H
TIM5_CCR2L
TIM5_BKR
TIM5 Auto-reload register low
TIM5 Capture/Compare register 1 high
TIM5 Capture/Compare register 1 low
TIM5 Capture/Compare register 2 high
TIM5 Capture/Compare register 2 low
TIM5 break register
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
TIM5
TIM5_OISR
TIM5 output idle state register
0x00 5317
to
Reserved area
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347
0x00 5348
0x00 5349
0x00 534A
0x00 534B
0x00 534C
0x00 534D
0x00 534E
0x00 534F
0x00 5350
0x00 5351
ADC1_CR1
ADC1_CR2
ADC1 configuration register 1
ADC1 configuration register 2
ADC1 configuration register 3
ADC1 status register
0x00
0x00
0x1F
0x00
0x00
0x00
0x0F
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADC1_CR3
ADC1_SR
ADC1_DRH
ADC1_DRL
ADC1 data register high
ADC1 data register low
ADC1_HTRH
ADC1_HTRL
ADC1_LTRH
ADC1_LTRL
ADC1_SQR1
ADC1_SQR2
ADC1_SQR3
ADC1_SQR4
ADC1_TRIGR1
ADC1_TRIGR2
ADC1_TRIGR3
ADC1_TRIGR4
ADC1 high threshold register high
ADC1 high threshold register low
ADC1 low threshold register high
ADC1 low threshold register low
ADC1 channel sequence 1 register
ADC1 channel sequence 2 register
ADC1 channel sequence 3 register
ADC1 channel sequence 4 register
ADC1 trigger disable 1
ADC1
ADC1 trigger disable 2
ADC1 trigger disable 3
ADC1 trigger disable 4
0x00 5352 to
0x00 537F
Reserved area (46 bytes)
0x00 5380
0x00 5381
0x00 5382
0x00 5383
0x00 5384
0x00 5385
DAC_CH1CR1
DAC_CH1CR2
DAC_CH2CR1
DAC_CH2CR2
DAC_SWTRIG
DAC_SR
DAC channel 1 control register 1
DAC channel 1 control register 2
DAC channel 2 control register 1
DAC channel 2 control register 2
DAC software trigger register
DAC status register
0x00
0x00
0x00
0x00
0x00
0x00
DAC
52/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5386 to
0x00 5387
Reserved area (2 bytes)
DAC channel 1 right aligned data holding
register high
0x00 5388
0x00 5389
DAC_CH1RDHRH
DAC_CH1RDHRL
0x00
0x00
DAC
DAC channel 1 right aligned data holding
register low
0x00 538A to
0x00 538B
Reserved area (2 bytes)
DAC channel 1 left aligned data holding
register high
0x00 538C
0x00 538D
DAC
DAC
DAC_CH1LDHRH
DAC_CH1LDHRL
0x00
0x00
DAC channel 1 left aligned data holding
register low
0x00 538E
to 0x00 538F
Reserved area (2 bytes)
0x00 5390
DAC
DAC
DAC_CH1DHR8
DAC channel 1 8-bit data holding register
Reserved area (3 bytes)
0x00
0x00 5391 to
0x00 5393
DAC channel 2 right aligned data holding
register high
0x00 5394
0x00 5395
DAC_CH2RDHRH
DAC_CH2RDHRL
0x00
0x00
DAC channel 2 right aligned data holding
register low
0x00 5396 to
0x00 5397
Reserved area (2 bytes)
DAC channel 2 left aligned data holding
register high
0x00 5398
0x00 5399
DAC_CH2LDHRH
DAC_CH2LDHRL
0x00
0x00
DAC
DAC
DAC
DAC channel 2 left aligned data holding
register low
0x00 539A
to 0x00 539B
Reserved area (2 bytes)
0x00 539C
DAC_CH2DHR8
DAC channel 2 8-bit data holding register
Reserved area (3 bytes)
0x00
0x00 539D
to 0x00 539F
DAC channel 1 right aligned data holding
register high
0x00 53A0
0x00 53A1
DAC_DCH1RDHRH
DAC_DCH1RDHRL
0x00
0x00
DAC channel 1 right aligned data holding
register low
0x00 53A2
to 0x00 53AB
Reserved area (3 bytes)
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 53AC
0x00 53AD
DAC_DORH
DAC_DORL
DAC data output register high
DAC data output register low
0x00
0x00
DAC channel 2 right aligned data holding
register high
0x00 53A2
0x00 53A3
0x00 53A4
0x00 53A5
0x00 53A6
0x00 53A7
0x00 53A8
0x00 53A9
DAC_DCH2RDHRH
DAC_DCH2RDHRL
DAC_DCH1LDHRH
DAC_DCH1LDHRL
DAC_DCH2LDHRH
DAC_DCH2LDHRL
DAC_DCH1DHR8
DAC_DCH2DHR8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DAC channel 2 right aligned data holding
register low
DAC channel 1left aligned data holding
register high
DAC channel 1left aligned data holding
register low
DAC
DAC channel 2 left aligned data holding
register high
DAC channel 2 left aligned data holding
register low
DAC channel 1 8-bit mode data holding
register
DAC channel 2 8-bit mode data holding
register
0x00 53AA to
0x00 53AB
Reserved area (2 bytes)
DAC_CH1DORH
Reset value
0x00 53AC
0x00 53AD
DAC channel 1 data output register high
DAC channel 1 data output register low
Reserved area (2 bytes)
0x00
0x00
DAC
DAC
DAC_CH1DORL
Reset value
0x00 53AE
to 0x00 53AF
DAC_CH2DORH
Reset value
0x00 53B0
0x00 53B1
DAC channel 2 data output register high
DAC channel 2 data output register low
Reserved area
0x00
0x00
DAC_CH2DORL
Reset value
0x00 53B2
to 0x00 53BF
0x00 53C0
0x00 53C1
0x00 53C2
0x00 53C3
0x00 53C4
0x00 53C5
0x00 53C6
0x00 53C7
SPI2_CR1
SPI2_CR2
SPI2 control register 1
SPI2 control register 2
SPI2 interrupt control register
SPI2 status register
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
SPI2_ICR
SPI2_SR
SPI2
SPI2_DR
SPI2 data register
SPI2_CRCPR
SPI2_RXCRCR
SPI2_TXCRCR
SPI2 CRC polynomial register
SPI2 Rx CRC register
SPI2 Tx CRC register
54/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 53C8 to
0x00 53DF
Reserved area
0x00 53E0
0x00 53E1
0x00 53E2
0x00 53E3
0x00 53E4
0x00 53E5
0x00 53E6
0x00 53E7
0x00 53E8
0x00 53E9
0x00 53EA
USART2_SR
USART2_DR
USART2 status register
USART2 data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
USART2_BRR1
USART2_BRR2
USART2_CR1
USART2_CR2
USART2_CR3
USART2_CR4
USART2_CR5
USART2_GTR
USART2_PSCR
USART2 baud rate register 1
USART2 baud rate register 2
USART2 control register 1
USART2 control register 2
USART2 control register 3
USART2 control register 4
USART2 control register 5
USART2 guard time register
USART2 prescaler register
USART2
0x00 53EB to
0x00 53EF
Reserved area
0x00 53F0
0x00 53F1
0x00 53F2
0x00 53F3
0x00 53F4
0x00 53F5
0x00 53F6
0x00 53F7
0x00 53F8
0x00 53F9
0x00 53FA
USART3_SR
USART3_DR
USART3 status register
USART3 data register
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
USART3_BRR1
USART3_BRR2
USART3_CR1
USART3_CR2
USART3_CR3
USART3_CR4
USART3_CR5
USART3_GTR
USART3_PSCR
USART3 baud rate register 1
USART3 baud rate register 2
USART3 control register 1
USART3 control register 2
USART3 control register 3
USART3 control register 4
USART3 control register 5
USART3 guard time register
USART3 prescaler register
USART3
0x00 53FB to
0x00 53FF
Reserved area
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
0x00 5408
0x00 5409
LCD_CR1
LCD_CR2
LCD_CR3
LCD_FRQ
LCD_PM0
LCD_PM1
LCD_PM2
LCD_PM3
LCD_PM4
LCD_PM5
LCD control register 1
LCD control register 2
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LCD control register 3
LCD frequency selection register
LCD Port mask register 0
LCD Port mask register 1
LCD Port mask register 2
LCD Port mask register 3
LCD Port mask register 4
LCD Port mask register 5
LCD
0x00 540A to
0x00 540B
Reserved area (2 bytes)
0x00 540C
0x00 540D
0x00 540E
0x00 540F
0x00 5410
0x00 5411
0x00 5412
0x00 5413
0x00 5414
0x00 5415
0x00 5416
0x00 5417
0x00 5418
0x00 5419
0x00 541A
0x00 541B
0x00 541C
0x00 541D
0x00 541E
0x00 541F
0x00 5420
0x00 5421
LCD_RAM0
LCD_RAM1
LCD_RAM2
LCD_RAM3
LCD_RAM4
LCD_RAM5
LCD_RAM6
LCD_RAM7
LCD_RAM8
LCD_RAM9
LCD_RAM10
LCD_RAM11
LCD_RAM12
LCD_RAM13
LCD_RAM14
LCD_RAM15
LCD_RAM16
LCD_RAM17
LCD_RAM18
LCD_RAM19
LCD_RAM20
LCD_RAM21
LCD display memory 0
LCD display memory 1
LCD display memory 2
LCD display memory 3
LCD display memory 4
LCD display memory 5
LCD display memory 6
LCD display memory 7
LCD display memory 8
LCD display memory 9
LCD display memory 10
LCD display memory 11
LCD display memory 12
LCD display memory 13
LCD display memory 14
LCD display memory 15
LCD display memory 16
LCD display memory 17
LCD display memory 18
LCD display memory 19
LCD display memory 20
LCD display memory 21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
LCD
LCD
56/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 9. General hardware register map (continued)
Address
Block
Register label
Register name
Reset status
0x00 5422 to
0x00 542E
Reserved area
0x00 542F
0x00 5430
0x00 5431
0x00 5432
0x00 5433
0x00 5434
0x00 5435
0x00 5436
0x00 5437
0x00 5438
0x00 5439
0x00 543A
0x00 543B
0x00 543C
0x00 543D
0x00 543E
0x00 543F
0x00 5440
0x00 5441
0x00 5442
0x00 5443
0x00 5444
LCD
LCD_CR4
LCD control register 4
Reserved area (1 byte)
0x00
0x00
0x00
0x00
0xXX
0xXX
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x3F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RI_ICR1
RI_ICR2
Timer input capture routing register 1
Timer input capture routing register 2
I/O input register 1
RI_IOIR1
RI_IOIR2
I/O input register 2
RI_IOIR3
I/O input register 3
RI_IOCMR1
RI_IOCMR2
RI_IOCMR3
RI_IOSR1
I/O control mode register 1
I/O control mode register 2
I/O control mode register 3
I/O switch register 1
RI
RI_IOSR2
I/O switch register 2
RI_IOSR3
I/O switch register 3
RI_IOGCR
RI_ASCR1
RI_ASCR2
RI_RCR
I/O group control register
Analog switch register 1
Analog switch register 2
Resistor control register 1
COMP_CSR1
COMP_CSR2
COMP_CSR3
COMP_CSR4
COMP_CSR5
Comparator control and status register 1
Comparator control and status register 2
Comparator control and status register 3
Comparator control and status register 4
Comparator control and status register 5
COMP1/
COMP2
1. These registers are not impacted by a system reset. They are reset at power-on.
DocID17943 Rev 6
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61
Memory and register map
STM8L15xx8, STM8L15xR6
Table 10. CPU/SWIM/debug module/interrupt controller registers
Reset
status
Address
Block
Register label
Register name
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
A
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
0xFF
0x28
PCE
PCH
PCL
XH
CPU(1)
XL
YH
YL
SPH
SPL
CCR
Stack pointer low
Condition code register
0x00 7F0B to
0x00 7F5F
Reserved area (85 bytes)
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
CPU
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
Global configuration register
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Interrupt Software priority register 1
Interrupt Software priority register 2
Interrupt Software priority register 3
Interrupt Software priority register 4
Interrupt Software priority register 5
Interrupt Software priority register 6
Interrupt Software priority register 7
Interrupt Software priority register 8
ITC-SPR
0x00 7F78
to
0x00 7F79
Reserved area (2 bytes)
SWIM control status register
Reserved area (15 bytes)
0x00 7F80
SWIM
SWIM_CSR
0x00
0x00 7F81
to
0x00 7F8F
58/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Memory and register map
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Reset
status
Address
Block
Register label
Register name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM Debug module control register 1
DM Debug module control register 2
DM Debug module control/status register 1
DM Debug module control/status register 2
DM enable function register
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
DM
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
0x00 7F9B
to
Reserved area (5 bytes)
0x00 7F9F
1. Accessible by debug module only
DocID17943 Rev 6
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61
Interrupt vector mapping
STM8L15xx8, STM8L15xR6
6
Interrupt vector mapping
Table 11. Interrupt mapping
Wakeup
Wakeup
Wakeup
from Wait from Wait
(WFI
mode)
Wakeup
Vector
IRQ
No.
Source
block
from
Description
from Halt
Active-halt
mode
(WFE
address
mode
mode)(1)
RESET
TRAP
TLI(2)
Reset
Yes
Yes
Yes
-
Yes
-
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
Software interrupt
-
-
-
-
-
-
-
-
-
-
0
1
2
3
External Top level Interrupt
EOP/WR_PG_DIS
-
-
FLASH
Yes
Yes
Yes
Yes(3)
Yes(3)
Yes(3)
DMA1 0/1 DMA1 channels 0/1
DMA1 2/3 DMA1 channels 2/3
RTC/LSE_ RTC alarm interrupt/LSE
4
5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0x00 8018
0x00 801C
CSS
CSS interrupt
EXTI
PortE/F interrupt/PVD
Yes(3)
E/F/PVD(4) interrupt
6
EXTIB/G External interrupt port B/G
EXTID/H External interrupt port D/H
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes(3)
Yes
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
7
8
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
EXTI6
EXTI7
LCD
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
LCD interrupt
9
10
11
12
13
14
15
16
CLK/
TIM1/
DAC
System clock switch/CSS
interrupt/TIM1 break/DAC
17
18
-
-
Yes
Yes
Yes
0x00 804C
0x00 8050
COMP1/
COMP2
ADC1
Comparator 1 and 2
interrupt/ADC1
Yes
Yes
Yes(3)
TIM2 update
/overflow/trigger/break/
TIM2/
USART2 transmission
19
-
-
Yes
Yes(3)
0x00 8054
USART2 complete/transmit data
register empty
interrupt
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STM8L15xx8, STM8L15xR6
Interrupt vector mapping
Table 11. Interrupt mapping (continued)
Wakeup
Wakeup
from Halt
mode
Wakeup
from Wait from Wait
(WFI
mode)
Wakeup
Vector
IRQ
No.
Source
block
from
Active-halt
mode
Description
(WFE
address
mode)(1)
TIM2/
USART2 2 interrupt
Capture/Compare/USART
20
21
-
-
Yes
Yes(3)
0x00 8058
0x00 805C
TIM3 Update
/Overflow/Trigger/Break/
USART3 transmission
TIM3/
-
-
Yes
Yes(3)
USART3 complete/transmit data
register empty
interrupt
TIM3 Capture/Compare/
USART3 Receive register
TIM3/
22
23
data full/overrun/idle line
USART3
-
-
-
-
Yes
-
Yes(3)
Yes(3)
0x00 8060
0x00 8064
detected/parity error/
interrupt
Update /overflow/trigger/
TIM1
COM
24
25
26
TIM1
TIM4
SPI1
Capture/Compare
Update/overflow/trigger
End of Transfer
-
-
-
-
-
Yes(3)
Yes(3)
Yes(3)
0x00 8068
0x00 806C
0x00 8070
Yes
Yes
Yes
Yes
USART1 transmission
complete/transmit data
register empty/
TIM5 update/overflow/
trigger/break
USART 1/
TIM5
27
-
-
Yes
Yes(3)
0x00 8074
USART1 Receive register
data full/overrun/idle line
detected/parity error/
USART 1/
TIM5
28
29
-
-
Yes
Yes
Yes(3)
Yes(3)
0x00 8078
0x00 807C
TIM5 capture/compare
I2C1 interrupt(5)
SPI2
/
I2C1/SPI2
Yes
Yes
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.
2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.
3. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
4. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
5. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
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61
Option bytes
STM8L15xx8, STM8L15xR6
7
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 12 for details on option byte addresses.
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8L15x/STM8L16x Flash programming manual (PM0054) and STM8 SWIM
and debug manual (UM0470) for information on SWIM programming procedures.
Table 12. Option byte addresses
Option
byte
No.
Option bits
3
Factory
default
setting
Address Option name
7
6
5
4
2
1
0
Read-out
protection
(ROP)
00 4800
OPT0
ROP[7:0]
0xAA
UBC (User
Boot code size)
00 4802
00 4807
OPT1
OPT2
UBC[7:0]
0x00
0x00
PCODESIZE
PCODE[7:0]
Independent
watchdog
option
OPT3
[3:0]
WWDG WWDG IWDG IWDG
_HALT _HW _HALT _HW
00 4808
Reserved
0x00
Number of
stabilization
00 4809 clock cycles for OPT4
HSE and LSE
Reserved
Reserved
LSECNT[1:0]
HSECNT[1:0]
0x00
0x00
oscillators
Brownout reset OPT5
00 480A
BOR_
ON
BOR_TH
(BOR)
[3:0]
00 480B
00 480C
Bootloader
option bytes
(OPTBL)
0x00
0x00
OPTBL
[15:0]
OPTBL[15:0]
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Option bytes
Table 13. Option byte description
Option description
Option
byte no.
ROP[7:0] Memory readout protection (ROP)
OPT0
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L reference manual (RM0031).
UBC[7:0] Size of the user boot code area
UBC[7:0] Size of the user boot code area
0x00: No UBC
OPT1
0x01: Page 0 reserved for the UBC and write protected.
...
0xFF: Page 0 to 254 reserved for the UBC and write-protected.
Refer to User boot code section in the STM8L reference manual (RM0031).
PCODESIZE[7:0] Size of the proprietary code area
0x00: No proprietary code area
0x01: Page 0 reserved for the proprietary code and read/write protected.
...
OPT2
0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.
Refer to Proprietary code area (PCODE) section in the STM8L reference manual
(RM0031) for more details.
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent watchdog off in Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
OPT3
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
OPT4
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
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64
Option bytes
STM8L15xx8, STM8L15xR6
Table 13. Option byte description (continued)
Option description
Option
byte no.
BOR_ON:
0: Brownout reset off
1: Brownout reset on
OPT5
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds
according to the value of BOR_TH bits.
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on the content of
OPTBL addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the
bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.
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STM8L15xx8, STM8L15xR6
Unique ID
8
Unique ID
STM8 devices feature a 96-bit unique device identifier which provides a reference number
that is unique for any device and in any context. The 96 bits of the identifier can never be
altered by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited:
•
•
For use as serial numbers
For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
•
To activate secure boot processes
Table 14. Unique ID registers (96 bits)
Unique ID bits
Content
Address
description
7
6
5
4
3
2
1
0
0x4926
0x4927
0x4928
0x4929
0x492A
0x492B
0x492C
0x492D
0x492E
0x492F
0x4930
0x4931
U_ID[7:0]
X co-ordinate on
the wafer
U_ID[15:8]
U_ID[23:16]
U_ID[31:24]
U_ID[39:32]
U_ID[47:40]
U_ID[55:48]
U_ID[63:56]
U_ID[71:64]
U_ID[79:72]
U_ID[87:80]
U_ID[95:88]
Y co-ordinate on
the wafer
Wafer number
Lot number
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65
Electrical parameters
STM8L15xx8, STM8L15xR6
9
Electrical parameters
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to V
.
SS
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by
A
A
A
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
9.1.2
Typical values
Unless otherwise specified, typical data are based on T = 25 °C, V = 3 V. They are given
A
DD
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
9.1.3
9.1.4
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
34-ꢃ, 0).
ꢍꢑ P&
MS32617V1
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STM8L15xx8, STM8L15xR6
Electrical parameters
9.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
34-ꢃ, 0).
6
).
MS32618V1
9.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15. Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External supply voltage
VDD- VSS
- 0.3
4.0
(1)
(including VDDA
)
Input voltage on true open-drain pins
(PC0 and PC1)
VSS - 0.3
VDD + 4.0
(2)
VIN
Input voltage on five-volt tolerant (FT)
pins
VSS - 0.3
VSS - 0.3
VDD + 4.0
4.0
V
Input voltage on any other pin
see Absolute maximum
ratings (electrical sensitivity)
on page 120
VESD
Electrostatic discharge voltage
1. All power (VDD1, VDD2, VDD3, VDD4, VDDA) and ground (VSS1, VSS2, VSS3, VSS4, VSSA) pins must always
be connected to the external power supply.
2. VIN maximum must always be respected. Refer to Table 16. for maximum allowed injected current values.
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121
Electrical parameters
Symbol
STM8L15xx8, STM8L15xR6
Table 16. Current characteristics
Ratings
Max.
Unit
IVDD
IVSS
Total current into VDD power line (source)
Total current out of VSS ground line (sink)
80
80
Output current sunk by IR_TIM pin
(with high sink LED driver capability)
80
IIO
Output current sunk by any other I/O and control pin
Output current sourced by any I/Os and control pin
25
- 25
mA
Injected current on true open-drain pins (PC0 and PC1)(1)
Injected current on five-volt tolerant (FT) pins(1)
Injected current on any other pin (2)
- 5 / +0
IINJ(PIN)
- 5 / +0
- 5 / +5
± 25
Total injected current (sum of all I/O and control pins) (3)
ΣIINJ(PIN)
1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 17. Thermal characteristics
Symbol
Ratings
Storage temperature range
Maximum junction temperature
Value
Unit
TSTG
TJ
-65 to +150
150
° C
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STM8L15xx8, STM8L15xR6
Electrical parameters
9.3
Operating conditions
Subject to general operating conditions for V and T .
DD
A
9.3.1
General operating conditions
Table 18. General operating conditions
Conditions
Symbol
Parameter
System clock
Min.
Max.
Unit
(1)
f
1.65 V ≤VDD < 3.6 V
0
16
MHz
SYSCLK
VDD
frequency
BOR detector disabled
(D suffix version)
1.65
1.8(2)
1.65
Standard operating
voltage
3.6
V
BOR detector enabled
ADC and DAC
3.6
3.6
V
V
not used
Analog operating
voltage
Must be at the same
VDDA
potential as VDD
ADC or DAC
1.8
used
LQFP80
LQFP64
288
288
288
288
131
104
156
77
Power dissipation at
TA= 85 °C for suffix 6
devices
UFQFPN48
LQFP48
(3)
PD
mW
LQFP80
Power dissipation at
TA= 125 °C for suffix 3
devices and at
TA= 105 °C for suffix 7
devices
LQFP64
UFQFPN48
LQFP48
1.65 V ≤VDD < 3.6 V (6 suffix version)
1.65 V ≤VDD < 3.6 V (7 suffix version)
1.65 V ≤VDD < 3.6 V (3 suffix version)
-40
-40
-40
85
TA
Temperature range
105
125
-40 °C ≤TA < 85 °C
-40
-40
-40
105
°C
(6 suffix version)
Junction temperature
range
-40 °C ≤ TA < 105 °C
(7 suffix version)
TJ
110(4)
130(4)
-40 °C≤ TA < 125 °C
(3 suffix version)
1. fSYSCLK = fCPU
2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled by option byte
3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in “Thermal characteristics”
table.
4. TJmax is given by the test limit. Above this value the product behavior is not guaranteed.
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Electrical parameters
STM8L15xx8, STM8L15xR6
9.3.2
Embedded reset and power control block characteristics
Table 19. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min.
0(1)
Max.
Unit
Typ.
BOR detector
enabled
(1)
µs/V
∞
VDD rise time rate
BOR detector
disabled
0(1)
1(1)
ms/V
µs/V
tVDD
BOR detector
enabled
20(1)
∞
(1)
VDD fall time rate
BOR detector
disabled
Reset below voltage functional range
3
VDD rising
BOR detector
enabled
tTEMP
Reset release delay
ms
VDD rising
1
BOR detector
disabled
VPOR
VPDR
Power-on reset threshold
Rising edge
1.3(2)
1.3(2)
1.67
1.69
1.87
1.96
2.22
2.31
2.45
2.54
2.68
2.78
1.5
1.5
1.65
1.65
1.74
1.80
1.97
2.07
2.35
2.44
2.60
2.7
Power-down reset threshold Falling edge
Falling edge
1.7
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
VBOR0
VBOR1
VBOR2
VBOR3
VBOR4
Rising edge
1.75
1.93
2.04
2.3
Falling edge
Brown-out reset threshold 1
(BOR_TH[2:0]=001)
Rising edge
V
Falling edge
Brown-out reset threshold 2
(BOR_TH[2:0]=010)
Rising edge
2.41
2.55
2.66
2.80
2.90
Falling edge
Brown-out reset threshold 3
(BOR_TH[2:0]=011)
Rising edge
Falling edge
2.85
2.95
Brown-out reset threshold 4
(BOR_TH[2:0]=100)
Rising edge
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STM8L15xx8, STM8L15xR6
Electrical parameters
Table 19. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Falling edge
Min.
Max.
Unit
Typ.
1.80
1.88
1.98
2.08
2.2
1.84
1.94
2.04
2.14
2.24
2.34
2.44
2.54
2.64
2.74
2.83
2.94
3.05
3.15
40
1.88
1.99
2.09
2.18
2.28
2.38
2.48
2.58
2.69
2.79
2.88
2.99
3.09
3.20
VPVD0
PVD threshold 0
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
BOR0 threshold
VPVD1
VPVD2
VPVD3
VPVD4
VPVD5
VPVD6
PVD threshold 1
PVD threshold 2
PVD threshold 3
PVD threshold 4
PVD threshold 5
PVD threshold 6
2.28
2.39
2.47
2.57
2.68
2.77
2.87
2.97
3.08
V
All BOR and PVD
thresholds
Vhyst
Hysteresis voltage
mV
100
excepting BOR0
1. Data guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 12. Power supply thresholds
VDD/VDDA
100 mV
hysteresis
VPVD
100 mV
hysteresis
VBOR
VPOR
V
/
PDR
IT enabled
PVD output
BOR reset
(NRST)
BOR/PDR reset
(NRST)
POR/PDR reset
(NRST)
(Note 1)
(Note 2)
(Note 3)
PVD
BOR always active
BOR disabled by option byte
POR/PDR (BOR not available) (Note 4)
ai17211b
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STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.3
Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
•
•
All I/O pins in input mode with a static value at V or V (no load)
DD SS
All peripherals are disabled except if explicitly mentioned.
In the following table, data are based on characterization results, unless otherwise
specified.
Subject to general operating conditions for V and T .
DD
A
Table 20. Total current consumption in Run mode
Max.
Para
meter
Conditions(1)
Typ.
Symbol
Unit
85 °C 105 °C 125 °C
55°C
(2)
(3)
(4)
fCPU = 125 kHz
0.22 0.28
0.32 0.38
0.59 0.65
0.93 0.99
0.39
0.49
0.76
1.1
0.47
0.57
0.84
1.18
0.51
0.61
0.88
1.22
fCPU = 1 MHz
fCPU = 4 MHz
fCPU = 8 MHz
HSI RC osc.
(16 MHz)(6)
1.62 1.68 1.79(7) 1.87(7) 1.91(7)
All
fCPU = 16 MHz
fCPU = 125 kHz
peripherals
OFF,
code
executed
from RAM,
VDD from
0.21 0.25
0.3 0.34
0.35
0.44
0.71
1.09
0.44
0.53
0.8
0.49
0.58
0.85
1.23
Supply
current
in run
mode
(5)
HSE
external
clock
(fCPU=fHSE
(8)
fCPU = 1 MHz
fCPU = 4 MHz
fCPU = 8 MHz
fCPU = 16 MHz
IDD(RUN)
mA
0.57 0.61
0.95 0.99
)
1.18
1.65 V to
3.6 V
1.73 1.77 1.87(7) 1.96(7) 2.01(7)
LSI RC osc.
(typ. 38 kHz)
fCPU = fLSI
0.029 0.035 0.039
0.028 0.034 0.038
0.044
0.042
0.055
0.054
LSE external
clock
fCPU = fLSE
(32.768 kHz)
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Table 20. Total current consumption in Run mode (continued)
Max.
Para
Symbol
Conditions(1)
Typ.
Unit
meter
85 °C 105 °C 125 °C
55°C
(2)
(3)
0.51
0.7
(4)
fCPU = 125 kHz
CPU = 1 MHz
fCPU = 4 MHz
0.35 0.46
0.54 0.65
1.16 1.27
1.97 2.08
3.54 3.65
0.35 0.44
0.53 0.62
1.13 1.22
0.48
0.67
1.29
2.1
0.59
0.78
1.4
f
HSI RC
osc.(9)
1.32
2.13
3.7
f
CPU = 8 MHz
CPU = 16 MHz
2.21
3.78
0.58
0.76
1.36
2.23
3.92
0.180
f
3.67
0.46
0.64
1.24
2.11
3.8
All
peripherals
fCPU = 125 kHz
0.49
0.67
1.27
2.14
3.83
0.138
OFF, code
executed
from Flash,
VDD from
Supply
current
in Run
mode
HSE
external
clock
f
CPU = 1 MHz
CPU = 4 MHz
IDD(RUN)
mA
f
(fCPU=fHSE
)
1.65 V to
3.6 V
fCPU = 8 MHz
2
2.09
(8)
f
CPU = 16 MHz
CPU = fLSI
3.69 3.78
f
LSI RC osc.
0.110 0.123 0.130
LSE external
clock
(32.768
fCPU = fLSE
0.100 0.101 0.104
0.119
0.163
kHz)(10)
1. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc., fCPU=fSYSCLK
2. For devices with suffix 6
3. For devices with suffix 7
4. For devices with suffix 3
5. CPU executing typical data processing
6. The run from RAM consumption can be approximated with the linear formula:
IDD(run_from_RAM) = Freq. * 95 µA/MHz + 250 µA
7. Tested in production.
8. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 31.
9. The run from Flash consumption can be approximated with the linear formula:
IDD(run_from_Flash) = Freq. * 200 µA/MHz + 330 µA
10. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 32
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Electrical parameters
Figure 13. Typical I
from RAM vs. V (HSI clock source), f =16 MHz
CPU
DD(RUN)
DD
2
1.8
1.6
1.4
1.2
1
25°C
85°C
0.8
0.6
0.4
0.2
0
105°C
125°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
6$$ ꢂ6ꢃ
-3ꢀꢓꢀꢑꢓ6ꢀ
1. Typical current consumption measured with code executed from RAM.
Figure 14. Typical I
from Flash vs. V (HSI clock source), f
= 16 MHz
DD(RUN)
DD
CPU
4
3.5
3
25°C
85°C
105°C
125°C
-40°C
2.5
2
1.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
6$$ ꢂ6ꢃ
-3ꢀꢓꢀꢀꢂ6ꢀ
1. Typical current consumption measured with code executed from Flash.
DocID17943 Rev 6
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Electrical parameters
STM8L15xx8, STM8L15xR6
In the following table, data are based on characterization results, unless otherwise
specified.
Table 21. Total current consumption in Wait mode
Max
Conditions(1)
Symbol Parameter
Typ
Unit
85 °C 105 °C 125 °C
55°C
(2)
(3)
(4)
fCPU = 125 kHz
CPU = 1 MHz
fCPU = 4 MHz
0.21 0.29
0.25 0.33
0.33
0.37
0.44
0.36
0.4
0.43
0.47
0.54
0.64
f
HSI
0.32
0.4
0.47
0.56
f
CPU = 8 MHz
CPU = 16 MHz
0.42 0.496 0.54
CPU not
0.66 0.736 0.78(6) 0.8(6) 0.88(6)
clocked,
all peripherals
OFF,
code
executedfrom
RAM
f
fCPU = 125 kHz
0.19 0.21
0.3
0.35
0.36
0.43
0.53
0.41
0.43
0.5
HSE
external
clock
(fCPU=fHSE
(7)
f
CPU = 1 MHz
CPU = 4 MHz
0.2
0.23
0.3
0.32
0.39
0.49
Supply
IDD(Wait) current in
Wait mode
mA
f
0.27
0.37
with Flash in
IDDQ mode,(5)
)
fCPU = 8 MHz
fCPU = 16 MHz
fCPU = fLSI
0.4
0.6
0.63 0.66 0.75(6) 0.79(6) 0.86(6)
0.028 0.037 0.039 0.044 0.054
VDD from
1.65 V to
3.6 V
LSI
LSE(8)
external
clock
fCPU = fLSE
0.027 0.035 0.038 0.042 0.051
(32.768
kHz)
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STM8L15xx8, STM8L15xR6
Symbol Parameter
Electrical parameters
Table 21. Total current consumption in Wait mode (continued)
Max
Conditions(1)
Typ
Unit
85 °C 105 °C 125 °C
55°C
(2)
(3)
(4)
fCPU = 125 kHz
fCPU = 1 MHz
fCPU = 4 MHz
0.27 0.36
0.29 0.38
0.37 0.46
0.45 0.55
0.69 0.79
0.23 0.29
0.24 0.31
0.32 0.39
0.42 0.49
0.42
0.44
0.52
0.61
0.85
0.32
0.34
0.42
0.51
0.79
0.46
0.48
0.56
0.65
0.89
0.4
0.51
0.53
0.61
0.7
HSI
f
CPU = 8 MHz
CPU = 16 MHz
f
CPU not
clocked,
all peripherals
0.94
0.47
0.48
0.56
0.66
0.94
fCPU = 125 kHz
HSE(7)
external
clock
OFF,
code
executedfrom
Flash,
f
CPU = 1 MHz
CPU = 4 MHz
0.41
0.49
0.59
0.87
Supply
IDD(Wait) current in
Wait mode
mA
f
(fCPU
=
fCPU = 8 MHz
VDD from
HSE)
1.65 V to
3.6 V
f
CPU = 16 MHz
CPU = fLSI
0.7
0.77
f
LSI
0.037 0.085 0.105 0.123 0.153
LSE(8)
external
clock
fCPU = fLSE
0.036 0.082 0.095 0.119 0.133
(32.768
kHz)
1. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc., fCPU = fSYSCLK
2. For devices with suffix 6.
3. For devices with suffix 7.
4. For devices with suffix 3.
5. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
6. Tested in production.
7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 31.
8. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD HSE) must be added. Refer to Table 32
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Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 15. Typical I
from RAM vs. V (HSI clock source), f
= 16 MHz
CPU
DD(Wait)
DD
0.8
0.7
0.6
0.5
0.4
0.3
0.2
25°C
85°C
-
40°C
1.8
2
2.2
2.4
2.6
2.8
VDD (V)
3
3.2
3.4
3.6
MS19113V1
1. Typical current consumption measured with code executed from RAM.
Figure 16. Typical I
from Flash (HSI clock source), f
= 16 MHz
DD(Wait)
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
25°C
85°C
105°C
125°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDD (V)
-3ꢀꢓꢀꢑꢃ6ꢀ
1. Typical current consumption measured with code executed from Flash.
78/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
In the following table, data are based on characterization results, unless otherwise
specified.
Table 22. Total current consumption and timing in Low power run mode at V = 1.65 V to 3.6 V
DD
Conditions(1)
Symbol
Parameter
Typ.
Max.
Unit
TA = -40 °C
to 25 °C
5.86
6.38
TA = 55 °C
TA = 85 °C
6.52
7.68
7.06
8.7
all peripherals OFF
TA = 105 °C 10.14 11.77
TA = 125 °C 14.4
18.27
6.73
LSI RC osc.
(at 38 kHz)
TA = -40 °C
6.2
to 25 °C
TA = 55 °C
TA = 85 °C
6.86
9.71
7.41
with TIM2 active(2)
10.81
TA = 105 °C 13.17 15.39
TA = 125 °C 16.72
21.1
5.94
Supply current in Low
power run mode
IDD(LPR)
μA
TA = -40 °C
5.42
to 25 °C
TA = 55 °C
TA = 85 °C
5.9
6.52
6.8
all peripherals OFF
6.14
TA = 105 °C 7.46
8.2
LSE (3) external
clock
(32.768 kHz)
TA = 125 °C 10.25 12.81
TA = -40 °C
5.87
6.48
to 25 °C
TA = 55 °C
TA = 85 °C
6.44
6.7
6.95
7.65
9.15
with TIM2 active (2)
TA = 105 °C 8.01
TA = 125 °C 10.62 16.09
1. No floating I/Os
2. Timer 2 clock enabled and counter running
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 32
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Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 17. Typical I
vs. V (LSI clock source), all peripherals OFF
DD(LPR)
DD
0.02
0.015
0.01
0.005
0
25°C
85°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDD(V)
MS19110V1
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DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
In the following table, data are based on characterization results, unless otherwise
specified.
Table 23. Total current consumption in Low power wait mode at V = 1.65 V to 3.6 V
DD
Conditions(1)
Symbol
Parameter
Typ. Max. Unit
TA = -40 °C to 25 °C
3.03 3.41
3.38 3.78
TA = 55 °C
all peripherals OFF
TA = 85 °C
4.6
5.34
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
7.25 8.84
11.89 16.18
3.78 4.21
4.13 4.57
5.29 6.08
7.54 9.13
12.47 15.56
2.46 2.89
2.58 3.07
3.32 4.05
4.63 6.17
7.52 11.68
2.88 3.29
2.97 3.42
3.69 4.55
5.09 6.78
7.91 12.15
LSI RC osc.
(at 38 kHz)
TA = 55 °C
with TIM2 active(2)
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
Supply current in
Low power wait
mode
IDD(LPW)
μA
TA = 55 °C
all peripherals OFF
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
LSE external
clock(3)
(32.768 kHz)
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
with TIM2 active (2)
1. No floating I/Os.
2. Timer 2 clock enabled and counter is running.
3. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 32.
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Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 18. Typical I
vs. V (LSI clock source), all peripherals OFF
DD(LPW)
DD
25°C
0.02
0.015
0.01
0.005
0
85°C
105°C
125°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
.4ꢄꢅꢄꢄꢁ7ꢄ
6$$ ꢂ6ꢃ
1. Typical current consumption measured with code executed from RAM.
82/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
In the following table, data are based on characterization results, unless otherwise
specified.
Table 24. Total current consumption and timing in Active-halt mode
at V = 1.65 V to 3.6 V
DD
Conditions(1)
Symbol
Parameter
Typ. Max. Unit
TA = -40 °C to 25 °C
0.92 2.25
1.32 3.44
1.63 3.87
TA = 55 °C
LCD OFF(2)
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
3
7.94
5.6 13.8
1.56 3.6
1.64 3.8
2.12 5.03
3.34 8.2
5.83 14.4
1.92 4.56
2.1 4.97
2.6 6.14
3.62 8.49
6.1 15.92
4.2 9.88
4.39 10.32
4.84 11.5
LCD ON
(static duty/
external
TA = 55 °C
TA = 85 °C
(3)
VLCD
)
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
Supply current in
Active-halt mode
LSI RC
(at 38 kHz)
IDD(AH)
μA
LCD ON
(1/4 duty/
external
TA = 55 °C
TA = 85 °C
(4)
VLCD
)
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
LCD ON
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
(1/4 duty/
internal
(5)
VLCD
)
5.98
15
7.21 18.07
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Electrical parameters
STM8L15xx8, STM8L15xR6
Table 24. Total current consumption and timing in Active-halt mode
at V = 1.65 V to 3.6 V (continued)
DD
Conditions(1)
Symbol
Parameter
Typ. Max. Unit
TA = -40 °C to 25 °C
0.54 1.35
0.61 1.44
0.91 2.27
2.24 5.42
TA = 55 °C
LCD OFF(7)
TA = 85 °C
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
5.03
12
0.91 2.13
1.05 2.55
1.42 3.65
2.63 6.35
5.24 13.15
1.6 2.84
1.76 4.37
2.14 5.23
3.37 8.5
5.92 15.19
3.89 9.15
3.89 9.15
4.25 10.49
5.42 16.31
6.58 16.6
LCD ON
(static duty/
external
TA = 55 °C
TA = 85 °C
(3)
VLCD
)
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
LSE external
clock
(32.768 kHz)
(6)
Supply current in
Active-halt mode
IDD(AH)
μA
LCD ON
(1/4 duty/
external
TA = 55 °C
TA = 85 °C
(4)
VLCD
)
TA = 105 °C
TA = 125 °C
TA = -40 °C to 25 °C
LCD ON
TA = 55 °C
TA = 85 °C
TA = 105 °C
TA = 125 °C
(1/4 duty/
internal
(5)
VLCD
)
Supply current during
wakeup time from
Active-halt mode
(using HSI)
IDD(WUFAH)
2.4
mA
Wakeup time from
Active-halt mode to
Run mode (using HSI)
(8)(9)
4.7
7
μs
μs
tWU_HSI(AH)
Wakeup time from
Active-halt mode to
Run mode (using LSI)
(8)(9)
150
tWU_LSI(AH)
1. No floating I/O, unless otherwise specified.
2. RTC enabled. Clock source = LSI
3. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
4. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
5. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 32
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Electrical parameters
7. RTC enabled. Clock source = LSE
8. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
.
9. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE
external crystal
Symbol
Parameter
Condition(1)
Typ.
Unit
LSE
LSE/32(3)
LSE
1.2
0.9
1.4
1.1
1.6
1.3
V
DD = 1.8 V
Supply current in Active-halt
mode
(2)
V
DD = 3 V
µA
IDD(AH)
LSE/32(3)
LSE
VDD = 3.6 V
LSE/32(3)
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
Figure 19. Typical I
vs. V (LSI clock source)
DD(AH)
DD
0.02
0.015
0.01
0.005
0
25°C
85°C
105°C
125°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
6$$ ꢂ6ꢃ
-3ꢀꢓꢀꢀꢁ6ꢀ
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
In the following table, data are based on characterization results, unless otherwise
specified.
Table 26. Total current consumption and timing in Halt mode at V = 1.65 to 3.6 V
DD
Symbol
Parameter
Condition(1)
Typ.
Max.
Unit
1600(2)
2400
TA = -40 °C to 25 °C
TA = 55 °C
400
810
Supply current in Halt mode
nA
4500(2)
7700(2)
18(2)
TA = 85 °C
1600
IDD(Halt)
(Ultra low power ULP bit =1 in
the PWR_CSR2 register)
TA = 105 °C
TA = 125 °C
2900
5.6
µA
Supply current during wakeup
time from Halt mode (using
HSI)
IDD(WUHalt)
2.4
mA
Wakeup time from Halt to Run
mode (using HSI)
(3)(4)
4.7
7
µs
µs
tWU_HSI(Halt)
Wakeup time from Halt mode
to Run mode (using LSI)
(3)(4)
150
tWU_LSI(Halt)
1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified
2. Tested in production
3. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register
4. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU
Figure 20. Typical I
vs. V (internal reference voltage OFF)
DD(Halt)
DD
0.02
25°C
0.018
0.016
0.014
0.012
0.01
85°C
105°C
125°C
-40°C
0.008
0.006
0.004
0.002
0
1.8
2
2.2
2.4
2.6
6$$ ꢂ6ꢃ
2.8
3
3.2
3.4
3.6
-3ꢀꢓꢀꢀꢓ6ꢀ
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STM8L15xx8, STM8L15xR6
Electrical parameters
Current consumption of on-chip peripherals
Table 27. Peripheral current consumption
Parameter
Typ.
Unit
Symbol
VDD = 3.0 V
TIM1 supply current(1)
IDD(TIM1)
IDD(TIM2)
IDD(TIM3)
IDD(TIM5)
IDD(TIM4)
IDD(USART1)
IDD(USART2)
IDD(USART3)
IDD(SPI1)
10
7
TIM2 supply current (1)
TIM3 supply current (1)
TIM5 supply current (1)
TIM4 timer supply current (1)
USART1 supply current (2)
USART2 supply current (2)
USART3 supply current (2)
SPI1 supply current (2)
SPI2 supply current (2)
I2C1 supply current (2)
DMA1 supply current(2)
WWDG supply current(2)
Peripherals ON(3)
7
7
3
5
5
µA/MHz
5
3
IDD(SPI2)
3
IDD(I2C1)
4
IDD(DMA1)
IDD(WWDG)
IDD(ALL)
3
1
63
1500
370
ADC1 supply current(4)
DAC supply current(5)
IDD(ADC1)
IDD(DAC)
Comparator 1 supply current(6)
IDD(COMP1)
0.160
Slow mode
Fast mode
2
5
Comparator 2 supply current(6)
IDD(COMP2)
µA
Power voltage detector and brownout Reset unit supply
current (7)
IDD(PVD/BOR)
IDD(BOR)
2.6
2.4
Brownout Reset unit supply current (7)
including LSI supply
current
0.45
IDD(IDWDG)
Independent watchdog supply current
excluding LSI
supply current
0.05
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1,
SPI2, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
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STM8L15xx8, STM8L15xR6
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD /2. Floating DAC output.
6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7. Including supply current of internal reference voltage.
Table 28. Current consumption under external reset
Symbol
Parameter
Conditions
Typ.
Unit
VDD = 1.8 V
DD = 3 V
VDD = 3.6 V
48
80
95
Supply current under
external reset (1)
PB1/PB3/PA5 pins are
externally tied to VDD
IDD(RST)
V
µA
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
9.3.4
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V and T .
DD
A
Table 29. HSE external clock characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
External clock source
frequency
(1)
1
16
MHz
fHSE_ext
VHSEH
VHSEL
OSC_IN input pin high level
voltage
0.7 x VDD
VSS
VDD
V
OSC_IN input pin low level
voltage
0.3 x VDD
(1)
OSC_IN input capacitance
2.6
pF
µA
Cin(HSE)
OSC_IN input leakage
current
ILEAK_HSE
VSS < VIN < VDD
±1
1. Guaranteed by design, not tested in production.
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STM8L15xx8, STM8L15xR6
Electrical parameters
LSE external clock (LSEBYP=1 in CLK_ECKCR)
The LSE is available on STM8L151xx and STM8L152xx devices only.
Subject to general operating conditions for V and T .
DD
A
Table 30. LSE external clock characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
External clock source frequency
OSC32_IN input pin high level voltage
OSC32_IN input pin low level voltage
OSC32_IN input capacitance
32.768
kHz
fLSE_ext
(2)
0.7 x VDD
VSS
VDD
VLSEH
V
(2)
0.3 x VDD
VLSEL
(1)
0.6
pF
µA
Cin(LSE)
ILEAK_LSE
OSC32_IN input leakage current
±1
1. Guaranteed by design, not tested in production.
2. Data based on characterization results, not tested in production.
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 31. HSE oscillator characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
High speed external oscillator
frequency
fHSE
1
16
MHz
RF
Feedback resistor
200
20
kΩ
C(1)(2)
Recommended load capacitance
pF
C = 20 pF,
OSC = 16 MHz
2.5 (startup)
f
0.7 (stabilized)(3)
IDD(HSE) HSE oscillator power consumption
mA
C = 10 pF,
2.5 (startup)
fOSC =16 MHz
0.46 (stabilized)(3)
gm
Oscillator transconductance
Startup time
3.5(3)
mA/V
ms
(4)
tSU(HSE)
VDD is stabilized
1
1. C=
C =CL2 is approximately equivalent to 2 x crystal CLOAD.
L1
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Guaranteed by design. Not tested in production.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
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Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 21. HSE oscillator circuit diagram
fHSE to core
Rm
RF
CO
Lm
CL1
OSC_IN
Cm
g
m
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
#
L2
.4ꢆꢇꢈꢇꢆ7ꢄ
HSE oscillator critical g formula
m
gmcrit = (2 × Π × fHSE)2 × Rm(2Co + C)2
R : Motional resistance (see crystal specification), L : Motional inductance (see crystal specification),
m
m
C : Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
m
C
=C =C: Grounded external capacitance
L1
L2
g
>> g
m
mcrit
LSE crystal/ceramic resonator oscillator
The LSE is available on STM8L151xx and STM8L152xx devices only.
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 32. LSE oscillator characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Low speed external oscillator
frequency
fLSE
32.768
kHz
RF
Feedback resistor
ΔV = 200 mV
1.2
8
MΩ
C(1)(2)
Recommended load capacitance
pF
VDD = 1.8 V
450
600
750
IDD(LSE) LSE oscillator power consumption
VDD = 3 V
nA
VDD = 3.6 V
gm
Oscillator transconductance
Startup time
3(3)
µA/V
s
(4)
tSU(LSE)
VDD is stabilized
1
1. C=
C =CL2 is approximately equivalent to 2 x crystal CLOAD.
L1
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Guaranteed by design. Not tested in production.
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Electrical parameters
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 22. LSE oscillator circuit diagram
fLSE
Rm
RF
CO
Lm
CL1
OSC_IN
Cm
gm
Resonator
Consumption
control
Resonator
STM8
OSC_OUT
CL2
MS32624V1
Internal clock sources
Subject to general operating conditions for V , and T .
DD
A
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 33. HSI oscillator characteristics
Conditions(1)
Symbol
Parameter
Frequency
Min.
Typ.
Max.
Unit
fHSI
VDD = 3.0 V
16
MHz
%
VDD = 3.0 V, TA = 25 °C
-1 (2)
-1.5
-2
1 (2)
1.5
2
VDD = 3.0 V, 0 °C ≤TA ≤ 55 °C
%
V
DD = 3.0 V, -10 °C ≤TA ≤ 70 °C
%
Accuracy of HSI
oscillator (factory
calibrated)
ACCHSI
VDD = 3.0 V, -10 °C ≤TA ≤ 85 °C
VDD = 3.0 V, -10 °C ≤TA ≤ 125 °C
-2.5
-4.5
2
%
2
%
1.65 V ≤VDD ≤ 3.6 V,
-40 °C ≤TA ≤ 125 °C
-4.5
3
%
Trimming code ≠ multiple of 16
0.4
0.7
%
%
HSI user trimming
step(3)
TRIM
Trimming code = multiple of 16
± 1.5
HSI oscillator setup
time (wakeup time)
tsu(HSI)
3.7
6 (4)
µs
HSI oscillator power
consumption
IDD(HSI)
100
140(4)
µA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Tested in production.
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
3. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
4. Guaranteed by design, not tested in production
Figure 23. Typical HSI frequency vs. V
DD
ꢀꢃꢋꢑ
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ꢀꢁꢋꢑ
ꢀꢅꢋꢍ
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ꢀꢍꢋꢍ
ꢀꢍꢋꢑ
ꢀꢆꢋꢍ
ꢀꢆꢋꢑ
ꢀꢉꢋꢍ
ꢀꢉꢋꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢋꢅꢍ ꢀꢋꢃ ꢀꢋꢓꢍ ꢂꢋꢀ ꢂꢋꢂꢍ ꢂꢋꢆ ꢂꢋꢍꢍ ꢂꢋꢁ ꢂꢋꢃꢍ
6$$ ;6=
ꢉ
ꢉꢋꢀꢍ ꢉꢋꢉ ꢉꢋꢆꢍ ꢉꢋꢅ
AIꢀꢃꢂꢀꢃ
Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production.
Table 34. LSI oscillator characteristics
Conditions(1)
Symbol
Parameter
Frequency
Min.
Typ.
Max.
Unit
fLSI
26
38
56
kHz
µs
tsu(LSI) LSI oscillator wakeup time
200(2)
LSI oscillator frequency
D(LSI)
drift(3)
0 °C ≤TA ≤ 85 °C
-12
11
%
1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.
2. Guaranteed by Design, not tested in production.
3. This is a deviation for an individual part, once the initial frequency has been measured.
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Electrical parameters
Figure 24. Typical LSI clock source frequency vs. V
DD
0.04
0.038
0.036
0.034
0.032
0.03
25°C
85°C
105°C
125°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
6$$ ꢂ6ꢃ
-3ꢀꢓꢀꢀꢅ6ꢀ
9.3.5
Memory characteristics
T = -40 to 125 °C unless otherwise specified.
A
Table 35. RAM and hardware registers
Conditions Min. Typ.
Halt mode (or Reset) 1.65
Symbol
Parameter
Max.
Unit
VRM
Data retention mode (1)
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization, not tested in production.
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Electrical parameters
STM8L15xx8, STM8L15xR6
Flash memory
Table 36. Flash program and data EEPROM memory
Max.
Symbol
Parameter
Conditions
Min. Typ.
Unit
(1)
Operating voltage
(all modes, read/write/erase)
VDD
fSYSCLK = 16 MHz
1.65
3.6
V
Programming time for 1 or 128 bytes (block)
erase/write cycles (on programmed byte)
6
tprog
ms
Programming time for 1 to 128 bytes (block)
write cycles (on erased byte)
3
TA=+25 °C, VDD = 3.0 V
TA=+25 °C, VDD = 1.8 V
Iprog
Programming/ erasing consumption
0.7
mA
Data retention (program memory) after 10000
erase/write cycles at TA=−40 το +85 °C
(6 suffix)
TRET=+85 °C
TRET=+125 °C
TRET=+85 °C
TRET=+125 °C
30(1)
Data retention (program memory) after 10000
erase/write cycles at TA=−40 το +125 °C
(3 suffix)
5(1)
(2)
tRET
years
Data retention (data memory) after 300000
erase/write cycles at TA=−40 το +85 °C
(6 suffix)
30(1)
Data retention (data memory) after 300000
erase/write cycles at TA=−40 το +125 °C
(3 suffix)
5(1)
Erase/write cycles (program memory)
TA=−40 το +85 °C
(6 suffix),
10(1)
TA=−40 το +105 °C
(7 suffix) or
TA=−40 το +125 °C
(3 suffix)
(3)
300(1)
NRW
kcycles
Erase/write cycles (data memory)
(4)
1. Data based on characterization results, not tested in production.
2. Conforming to JEDEC JESD22a117
3. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation
addresses a single byte.
4. Data based on characterization performed on the whole data memory.
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STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.6
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V or
SS
above V (for standard pins) should be avoided during normal product operation.
DD
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 37. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Unit
Negative
injection
Positive
injection
Injected current on true open-drain pins
Injected current on all 5 V tolerant (FT) pins
Injected current on any other pin
-5
-5
-5
+0
+0
+5
IINJ
mA
9.3.7
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V and T unless otherwise specified. All
DD
A
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Table 38. I/O static characteristics
Conditions(1)
Min.
Symbol
Parameter
Max.
Unit
Typ.
Input voltage on true
0.3 x VDD
open-drain pins (PC0
and PC1)
Vss-0.3
Input low level voltage(2)
VIL
Input voltage on five-
volt tolerant (FT) pins
V
0.3 x VDD
0.3 x VDD
Vss-0.3
Vss-0.3
Input voltage on any
other pin
Input voltage on true
open-drain pins (PC0
and PC1)
5.2
with VDD < 2 V
0.70 x VDD
Input voltage on true
open-drain pins (PC0
and PC1)
5.5
5.2
with VDD ≥ 2 V
Input high level voltage (2)
VIH
V
Input voltage on five-
volt tolerant (FT) pins
with VDD < 2 V
0.70 x VDD
0.70 x VDD
Input voltage on five-
volt tolerant (FT) pins
with VDD ≥ 2 V
5.5
Input voltage on any
other pin
VDD+0.3
Standard I/Os
200
200
Schmitt trigger voltage hysteresis (3)
Vhys
mV
nA
True open drain I/Os
VSS≤VIN≤VDD
Standard I/Os
-
-
-
-
50 (5)
VSS≤VIN≤VDD
True open drain I/Os
200(5)
Ilkg
Input leakage current (4)
VSS≤VIN≤VDD
PA0 with high sink LED
driver capability
-
-
200(5)
60
Weak pull-up equivalent
resistor(2)(6)
RPU
CIO
VIN=VSS
30
45
5
kΩ
I/O pin capacitance
pF
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Not tested in production.
6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 28).
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STM8L15xx8, STM8L15xR6
Electrical parameters
Figure 25. Typical V and V vs. V (standard I/Os)
IL
IH
DD
ꢉ
ꢂꢋꢍ
ꢂ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢋꢍ
ꢀ
ꢑꢋꢍ
ꢑ
ꢀꢋꢅ
ꢂꢋꢀ
ꢂꢋꢅ
6$$ ;6=
ꢉꢋꢀ
ꢉꢋꢅ
AIꢀꢃꢂꢂꢑ
Figure 26. Typical V and V vs. V (true open drain I/Os)
IL
IH
DD
ꢉ
ꢂꢋꢍ
ꢂ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢋꢍ
ꢀ
ꢑꢋꢍ
ꢑ
ꢀꢋꢅ
ꢂꢋꢀ
ꢂꢋꢅ
$$ ;6=
ꢉꢋꢀ
ꢉꢋꢅ
6
AIꢀꢃꢂꢂꢀ
Figure 27. Typical pull-up resistance R vs. V with V =V
SS
PU
DD
IN
ꢅꢑ
ꢍꢍ
ꢍꢑ
ꢆꢍ
ꢆꢑ
ꢉꢍ
ꢉꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢋꢅ
ꢀꢋꢃ
ꢂ
ꢂꢋꢂ
ꢂꢋꢆ
ꢂꢋꢅ
6$$ ;6=
ꢂꢋꢃ
ꢉ
ꢉꢋꢂ
ꢉꢋꢆ
ꢉꢋꢅ
AIꢀꢃꢂꢂꢂ
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 28. Typical pull-up current I vs. V with V =V
SS
pu
DD
IN
ꢀꢂꢑ
ꢀꢑꢑ
ꢃꢑ
ꢅꢑ
ꢆꢑ
ꢂꢑ
ꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
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6$$ ;6=
ꢉ
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AIꢀꢃꢂꢂꢉ
Output driving current
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 39. Output driving current (high sink ports)
I/O
Type
Symbol
Parameter
Conditions
Min.
Max. Unit
0.45
IIO = +2 mA,
VDD = 3.0 V
IIO = +2 mA,
VDD = 1.8 V
(1)
Output low level voltage for an I/O pin
0.45
VOL
I
IO = +10 mA,
0.7
VDD = 3.0 V
V
IIO = -2 mA,
VDD = 3.0 V
VDD-0.45
IIO = -1 mA,
VDD = 1.8 V
(2)
VDD-0.45
VDD-0.7
Output high level voltage for an I/O pin
VOH
I
IO = -10 mA,
VDD = 3.0 V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 16 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD
.
98/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
Table 40. Output driving current (true open drain ports)
I/O
Symbol
Type
Parameter
Conditions
Min.
Max. Unit
IIO = +3 mA,
VDD = 3.0 V
0.45
V
(1)
Output low level voltage for an I/O pin
VOL
IIO = +1 mA,
VDD = 1.8 V
0.45
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
Table 41. Output driving current (PA0 with high sink LED driver capability)
I/O
Type
Symbol
Parameter
Conditions
Min.
Max. Unit
IIO = +20 mA,
VDD = 2.0 V
(1)
Output low level voltage for an I/O pin
0.45
V
VOL
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS
.
Figure 29. Typical V @ V = 3.0 V (high sink Figure 30. Typical V @ V = 1.8 V (high sink
OL
DD
OL
DD
ports)
ports)
ꢀ
ꢑꢋꢁꢍ
ꢑꢋꢍ
ꢑꢋꢁ
ꢑꢋꢅ
ꢑꢋꢍ
ꢑꢋꢆ
ꢑꢋꢉ
ꢑꢋꢂ
ꢑꢋꢀ
ꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢓꢑ #
ꢀꢉꢑ #
ꢑꢋꢂꢍ
ꢑ
ꢑ
ꢂ
ꢆ
ꢅ
ꢃ
ꢀꢑ
ꢀꢂ
ꢀꢆ
ꢀꢅ
ꢀꢃ
ꢂꢑ
)
/, ;M!=
ꢑ
ꢀ
ꢂ
ꢉ
ꢆ
ꢍ
ꢅ
ꢁ
ꢃ
)
;M!=
/,
AIꢀꢃꢂꢂꢅ
AIꢀꢃꢂꢂꢁ
Figure 31. Typical V @ V = 3.0 V (true open Figure 32. Typical V @ V = 1.8 V (true open
OL
DD
OL
DD
drain ports)
drain ports)
ꢑꢋꢍ
ꢑꢋꢆ
ꢑꢋꢉ
ꢑꢋꢂ
ꢑꢋꢀ
ꢑ
ꢑꢋꢍ
ꢑꢋꢆ
ꢑꢋꢉ
ꢑꢋꢂ
ꢑꢋꢀ
ꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢇꢆꢑ #
ꢓꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢉꢑ #
ꢑ
ꢀ
ꢂ
ꢉ
ꢆ
ꢍ
ꢅ
ꢁ
ꢑ
ꢀ
ꢂ
ꢉ
ꢆ
ꢍ
ꢅ
ꢁ
)
/, ;M!=
)/, ;M!=
BJꢄꢀꢇꢇꢅ
AIꢀꢃꢂꢂꢃ
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 33. Typical V
V
@ V = 3.0 V (high Figure 34. Typical V
V
@ V = 1.8 V (high
DD - OH
DD
DD - OH DD
sink ports)
sink ports)
ꢂ
ꢀꢋꢁꢍ
ꢀꢋꢍ
ꢀꢋꢂꢍ
ꢀ
ꢑꢋꢍ
ꢑꢋꢆ
ꢑꢋꢉ
ꢑꢋꢂ
ꢑꢋꢀ
ꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢉꢑ #
ꢑꢋꢁꢍ
ꢑꢋꢍ
ꢑꢋꢂꢍ
ꢑ
ꢑ
ꢂ
ꢆ
ꢅ
ꢃ
ꢀꢑ
ꢀꢂ
ꢀꢆ
ꢀꢅ
ꢀꢃ
ꢂꢑ
)
/( ;M!=
ꢑ
ꢀ
ꢂ
ꢉ
ꢆ
ꢍ
ꢅ
ꢁ
)
/( ;M!=
AIꢀꢂꢃꢉꢑ
BJꢄꢀꢇꢆꢄ
NRST pin
Subject to general operating conditions for V and T unless otherwise specified.
DD
A
Table 42. NRST pin characteristics
Symbol
VIL(NRST)
VIH(NRST)
Parameter
Conditions
Min.
VSS
1.4
Max.
Unit
Typ.
NRST input low level voltage (1)
NRST input high level voltage (1)
0.8
VDD
IOL = 2 mA
V
for 2.7 V ≤VDD ≤ 3.6 V
NRST output low level voltage (1)
VOL(NRST)
0.4
IOL = 1.5 mA
for VDD < 2.7 V
10%VDD
NRST input hysteresis(3)
VHYST
mV
(2)
NRST pull-up equivalent
resistor(1)
RPU(NRST)
30
45
60
50
kΩ
NRST input filtered pulse (3)
VF(NRST)
ns
NRST input not filtered pulse (3)
VNF(NRST)
300
1. Data based on characterization results, not tested in production.
2. 200 mV min.
3. Data guaranteed by design, not tested in production.
100/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
Figure 35. Typical NRST pull-up resistance R vs. V
PU
DD
ꢅꢑ
ꢍꢍ
ꢍꢑ
ꢆꢍ
ꢆꢑ
ꢉꢍ
ꢉꢑ
ꢇꢆꢑ #
ꢂꢍ #
ꢓꢑ #
ꢀꢉꢑ #
ꢀꢋꢅ
ꢀꢋꢃ
ꢂ
ꢂꢋꢂ
ꢂꢋꢆ
ꢂꢋꢅ
6$$ ;6=
ꢂꢋꢃ
ꢉ
ꢉꢋꢂ
ꢉꢋꢆ
ꢉꢋꢅ
AIꢀꢃꢂꢂꢆ
Figure 36. Typical NRST pull-up current I vs. V
pu
DD
ꢀꢂꢑ
ꢇꢆꢑ #
ꢀꢑꢑ
ꢂꢍ #
ꢓꢑ #
ꢃꢑ
ꢀꢉꢑ #
ꢅꢑ
ꢆꢑ
ꢂꢑ
ꢑ
ꢀꢋꢅꢍ ꢀꢋꢃ ꢀꢋꢓꢍ ꢂꢋꢀ ꢂꢋꢂꢍ ꢂꢋꢆ ꢂꢋꢍꢍ ꢂꢋꢁ ꢂꢋꢃꢍ
6$$ ;6=
ꢉ
ꢉꢋꢀꢍ ꢉꢋꢉ ꢉꢋꢆꢍ ꢉꢋꢅ
AIꢀꢃꢂꢂꢍ
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V max. level specified in
IL
Table 42. Otherwise the reset is not taken into account internally. For power consumption-
sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF.
Figure 37. Recommended NRST pin configuration
6
$$
205
EXTERNAL
RESET
CIRCUIT
RSTIN
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STM8L
&ILTER
0.1MF
MS32619V1
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
9.3.8
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, f frequency and V supply voltage
SYSCLK
DD
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 43. SPI1 characteristics
Symbol
Parameter
Conditions(1)
Min.
Max.
Unit
MHz
ns
Master mode
0
0
8
8
fSCK
1/tc(SCK)
SPI1 clock frequency
Slave mode
tr(SCK)
tf(SCK)
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF
-
30
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
4 x 1/fSYSCLK
80
-
-
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
SCK high and low time
Data input setup time
105
145
(2)
(2)
Master mode
30
3
-
tsu(MI)
tsu(SI)
(2)
Slave mode
-
(2)
Master mode
15
0
-
th(MI)
th(SI)
Data input hold time
(2)
Slave mode
-
(2)(3)
ta(SO)
Data output access time
Data output disable time
Data output valid time
Slave mode
-
3x 1/fSYSCLK
(2)(4)
tdis(SO)
Slave mode
30
-
-
(2)
(2)
(2)
(2)
tv(SO)
tv(MO)
th(SO)
th(MO)
Slave mode (after enable edge)
60
Master mode (after enable
edge)
Data output valid time
-
15
1
20
-
Slave mode (after enable edge)
Data output hold time
Master mode (after enable
edge)
-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
102/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
Figure 38. SPI1 timing diagram - slave mode and CPHA=0
NSS input
t
t
t
h(NSS)
SU(NSS)
c(SCK)
CPHA=0
CPOL=0
t
t
w(SCKH)
w(SCKL)
CPHA=0
CPOL=1
t
t
t
t
t
dis(SO)
v(SO)
r(SCK)
f(SCK)
h(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
BIT1 IN
LSB OUT
t
su(SI)
MOSI
M SB IN
LSB IN
INPUT
t
h(SI)
ai14134
Figure 39. SPI1 timing diagram - slave mode and CPHA=1
NSS input
t
t
t
h(NSS)
SU(NSS)
t
c(SCK)
CPHA=1
CPOL=0
w(SCKH)
CPHA=1
CPOL=1
t
w(SCKL)
t
t
r(SCK)
f(SCK)
t
t
t
v(SO)
h(SO)
dis(SO)
t
a(SO)
MISO
OUT PUT
MSB O UT
BI T6 OUT
LSB OUT
t
t
su(SI)
h(SI)
MOSI
M SB IN
BIT1 IN
LSB IN
INPUT
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 40. SPI1 timing diagram - master mode
(IGH
.33 INPUT
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD
.
104/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
I2C - Inter IC control interface
Subject to general operating conditions for V
, and T unless otherwise specified.
, f
DD
A
SYSCLK
2
2
The STM8L I C interface (I2C1) meets the requirements of the Standard I C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 44. I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Unit
Min.(2)
4.7
Max. (2)
Min. (2) Max. (2)
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
SCL clock low time
1.3
0.6
μs
SCL clock high time
SDA setup time
4.0
250
0
100
SDA data hold time
0
900
300
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
ns
SDA and SCL rise time
1000
300
SDA and SCL fall time
300
th(STA)
tsu(STA)
tsu(STO)
tw(STO:STA)
Cb
START condition hold time
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
μs
Repeated START condition setup
time
STOP condition setup time
μs
μs
pF
STOP to START condition time (bus
free)
Capacitive load for each bus line
400
400
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
Data based on standard I2C protocol requirement, not tested in production.
2.
Note:
For speeds around 200 kHz, the achieved speed can have a 5% tolerance.
For other speed ranges, the achieved speed can have a 2% tolerance.
The above variations depend on the accuracy of the external components used.
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Typical application with I C bus and timing diagram
2
Figure 41.
6
6
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t
t
w(STO:STA)
su(STA)
START
SDA
t
t
r(SDA)
f(SDA)
STOP
T
T
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SCL
t
t
t
t
t
su(STO)
t
h(STA)
w(SCLH)
w(SCLL)
r(SCL)
f(SCL)
MS32620V1
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
106/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.9
LCD controller (STM8L152xx only)
In the following table, data are guaranteed by Design, not tested in production.
Table 45. LCD characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VLCD5
VLCD6
VLCD7
CEXT
LCD external voltage
3.6
LCD internal reference voltage 0
LCD internal reference voltage 1
LCD internal reference voltage 2
LCD internal reference voltage 3
LCD internal reference voltage 4
LCD internal reference voltage 5
LCD internal reference voltage 6
LCD internal reference voltage 7
VLCD external capacitance
2.6
2.7
2.8
3.0
3.1
3.2
3.4
3.5
1
V
0.1
2
µF
µA
Supply current(1) at VDD = 1.8 V
Supply current(1) at VDD = 3 V
3
IDD
3
(2)
RHN
High value resistive network (low drive)
Low value resistive network (high drive)
Segment/Common higher level voltage
Segment/Common 3/4 level voltage
Segment/Common 2/3 level voltage
Segment/Common 1/2 level voltage
Segment/Common 1/3 level voltage
Segment/Common 1/4 level voltage
Segment/Common lowest level voltage
6.6
240
MΩ
kΩ
(3)
RLN
V33
V34
V23
V12
V13
V14
V0
VLCDx
3/4VLCDx
2/3VLCDx
1/2VLCDx
1/3VLCDx
1/4VLCDx
V
0
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.
VLCD external capacitor (STM8L152xx only)
The application can achieve a stabilized LCD reference voltage by connecting an external
capacitor C
to the V
pin. C
is specified in Table 45.
EXT
LCD
EXT
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
9.3.10
Embedded reference voltage
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 46. Reference voltage characteristics
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Internal reference voltage
consumption
IREFINT
1.4
µA
ADC sampling time when reading the
internal reference voltage
(1)(2)
TS_VREFINT
5
10
25
µs
µA
V
Internal reference voltage buffer
consumption (used for ADC)
(1)
IBUF
13.5
1.224
1.202
1.242
VREFINT out
Reference voltage output
(3)
(3)
Internal reference voltage low power
buffer consumption (used for
comparators or output)
(1)
ILPBUF
730 1200
nA
(1)(4)
IREFOUT
Buffer output current
1
µA
pF
CREFOUT
Reference voltage output load
50
Internal reference voltage startup
time
(1)
tVREFINT
2
3
ms
µs
Internal reference voltage buffer
startup time once enabled
(1)(2)
tBUFEN
10
± 5
Accuracy of VREFINT stored in the
VREFINT_Factory_CONV byte
(5)
ACCVREFINT
mV
Stability of VREFINT over temperature -40 °C ≤TA ≤ 125 °C
20
50
20
ppm/°C
ppm/°C
ppm
STABVREFINT
STABVREFINT
Stability of VREFINT over temperature
Stability of VREFINT after 1000 hours
0 °C ≤TA ≤ 50 °C
1000
1. Guaranteed by design, not tested in production
2. Defined when ADC output reaches its final value ±1/2LSB
3. Tested in production at VDD = 3 V ±10 mV.
4. To guarantee less than 1% VREFOUT deviation
5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.
108/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.11
Temperature sensor
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 47. TS characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
V90
Sensor reference voltage at 90°C ±5 °C,
VSENSOR linearity with temperature
Average slope
0.580
0.597
±1
0.614
±2
V
°C
TL
Avg_slope(2)
1.59
1.62
3.4
1.65
6
mV/°C
µA
(2)
IDD(TEMP)
Consumption
(2)(3)
TSTART
Temperature sensor startup time
10
µs
ADC sampling time when reading the
temperature sensor
(2)
TS_TEMP
5
10
µs
1. Tested in production at VDD = 3 V ±10 mV. The 8 LSB of the V90 ADC conversion result are stored in the
TS_Factory_CONV_V90 byte.
2. Guaranteed by design, not tested in production.
3. Defined for ADC output reaching its final value ±1/2LSB.
9.3.12
Comparator characteristics
In the following tables, data are guaranteed by design, not tested in production.
Table 48. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1) Typ
Max(1)
Unit
VDDA
R400K
R10K
Analog supply voltage
R400K value
1.65
400
10
3.6
V
kΩ
R10K value
Comparator 1 input
voltage range
VIN
0.6
VDDA
V
tSTART
td
Comparator startup time
Propagation delay(2)
Comparator offset
7
3
3
10
10
10
µs
Voffset
mV
VDDA = 3.6 V
VIN+ = 0 V
Comparator offset
dVoffset/dt variation in worst voltage
stress conditions
0
1.5
10
mV/1000 h
nA
VIN- = VREFINT
TA = 25 °C
ICOMP1
Current consumption(3)
160
260
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
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121
Electrical parameters
Symbol
STM8L15xx8, STM8L15xR6
Table 49. Comparator 2 characteristics
Parameter
Conditions
Min Typ Max(1) Unit
VDDA
VIN
Analog supply voltage
1.65
0
3.6
VDDA
20
25
3.5
6
V
V
Comparator 2 input voltage range
Fast mode
15
20
1.8
2.5
0.8
1.2
4
tSTART
Comparator startup time
Slow mode
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
1.65 V ≤ VDDA ≤ 2.7 V
2.7 V ≤ VDDA ≤ 3.6 V
td slow
Propagation delay(2) in slow mode
µs
2
td fast
Propagation delay(2) in fast mode
Comparator offset error
4
Voffset
20
mV
VDDA = 3.3V
TA = 0 to 50 °C
V- = VREF+, 3/4
dThreshold/ Threshold voltage temperature
ppm
/°C
15
30
dt
coefficient
VREF+
,
1/2 VREF+, 1/4 VREF+
.
Fast mode
3.5
0.5
5
2
ICOMP2
Current consumption(3)
µA
Slow mode
1. Based on characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
110/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.13
12-bit DAC characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 50. DAC characteristics
Symbol
Parameter
Analog supply voltage
Reference supply voltage
Conditions
Min.
1.8
Typ.
Max.
Unit
VDDA
3.6
V
VDDA
VREF+
1.8
VREF+ = 3.3 V, no load,
middle code (0x800)
130
220
210
320
220
350
320
Current consumption on VREF+
supply
IVREF
VREF+ = 3.3 V, no load,
worst code (0x000)
µA
VDDA = 3.3 V, no load,
middle code (0x800)
Current consumption on VDDA
supply
IVDDA
VDDA = 3.3 V, no load,
520
125
worst code (0x000)
TA
Temperature range
Resistive load
-40
5
°C
kΩ
kΩ
pF
V
(1) (2)
RL
DACOUT buffer ON
DACOUT buffer OFF
RO
Output impedance
Capacitive load
8
7
10
50
(3)
CL
DACOUT buffer ON
DACOUT buffer OFF
0.2
0
VDDA - 0.2
VREF+ -1 LSB
DAC_OUT
DAC_OUT voltage
(4)
V
Settling time (full scale: for a 12-
bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value ±1LSB)
RL ≥ 5 kΩ, CL≤ 50 pF
RL ≥ 5 kΩ, CL ≤50 pF
tsettling
12
1
µs
Max frequency for a correct
DAC_OUT (@95%) change
when small variation of the input
code (from code i to i+1LSB).
Update rate
Msps
Wakeup time from OFF state.
RL ≥ 5 kΩ, CL≤50 pF
RL≥ 5 kΩ, CL≤50 pF
tWAKEUP Input code between lowest and
highest possible codes.
9
15
µs
Power supply rejection ratio (to
PSRR+
-60
-35
dB
VDDA) (static DC measurement)
1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
In the following table, data based on characterization results, not tested in production.
Table 51. DAC accuracy
Symbol
Parameter
Conditions
Typ.
Max.
Unit
RL ≥5 kΩ, C ≤50 pF
DACOUT buffer ON(2)
L
1.5
3
DNL
Differential non linearity(1)
No load
DACOUT buffer OFF
1.5
2
3
4
RL ≥5 kΩ, C ≤ 50 pF
L
DACOUT buffer ON(2)
INL
Integral non linearity(3)
12-bit
LSB
No load
DACOUT buffer OFF
2
4
RL ≥5 kΩ, C ≤ 50 pF
DACOUT buffer ON(2)
L
±10
±25
Offset
Offset1
Offset error(4)
No load
DACOUT buffer OFF
±5
±8
±5
Offset error at Code 1 (5)
Gain error(6)
DACOUT buffer OFF
±1.5
RL ≥5 kΩ, C ≤ 50 pF
L
+0.1/-0.2 +0.2/-0.5
DACOUT buffer ON(2)
Gain error
%
No load
DACOUT buffer OFF
+0/-0.2
+0/-0.4
RL ≥5 kΩ, C ≤ 50 pF
DACOUT buffer ON(2)
L
12
8
30
12
12-bit
LSB
TUE
Total unadjusted error
No load -DACOUT buffer OFF
1. Difference between two consecutive codes - 1 LSB.
2. In 48-pin package devices the DAC2 output buffer must be kept off and no load must be applied on the DAC_OUT2 output.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
4. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF
when buffer is ON, and from Code giving 0.2 V and (VDDA -0.2) V when buffer is OFF.
In the following table, data are guaranteed by design, not tested in production.
(1)
Table 52. DAC output on PB4-PB5-PB6
Symbol
Parameter
Conditions
2.7 V < VDD < 3.6 V
2.4 V < VDD < 3.6 V
2.0 V < VDD < 3.6 V
1.8 V < VDD < 3.6 V
Max
1.4
1.6
3.2
8.2
Unit
Internal resistance
between DAC output and
PB4-PB5-PB6 output
Rint
kΩ
1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
112/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.14
12-bit ADC1 characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 53. ADC1 characteristics
Symbol
Parameter
Conditions
Min.
1.8
Typ.
Max.
Unit
VDDA
Analog supply voltage
3.6
2.4 V ≤VDDA≤ 3.6 V
1.8 V≤VDDA≤ 2.4 V
VDDA
2.4
Reference supply
voltage
VREF+
V
VDDA
VSSA
VREF-
IVDDA
Lower reference voltage
Current on the VDDA
input pin
1000
1450
700
(peak)(1)
µA
Current on the VREF+
input pin
IVREF+
400
450
(average)(1)
Conversion voltage
range
0(2)
-40
VAIN
TA
VREF+
125
Temperature range
°C
on PF0/1/2/3 fast
channels
External resistance on
VAIN
50(3)
kΩ
RAIN
on all other channels
on PF0/1/2/3 fast
channels
Internal sample and hold
capacitor
CADC
16
pF
on all other channels
2.4 V≤VDDA≤3.6 V
without zooming
0.320
0.320
16
8
ADC sampling clock
frequency
fADC
1.8 V≤VDDA≤2.4 V
with zooming
MHz
kHz
V
AIN on PF0/1/2/3 fast
1(3)(4)
channels
fCONV
12-bit conversion rate
VAIN on all other
channels
760(3)(4)
External trigger
frequency
fTRIG
tLAT
tconv
3.5
1/fADC
External trigger latency
1/fSYSCLK
DocID17943 Rev 6
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121
Electrical parameters
STM8L15xx8, STM8L15xR6
Table 53. ADC1 characteristics (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VAIN PF0/1/2/3 fast
channels
0.43(3)(4)
VDDA < 2.4 V
V
AIN PF0/1/2/3 fast
channels
0.22(3)(4)
tS
Sampling time
µs
2.4 V ≤VDDA≤ 3.6 V
VAIN on slow channels
VDDA < 2.4 V
0.86(3)(4)
0.41(3)(4)
VAIN on slow channels
2.4 V ≤VDDA≤ 3.6 V
12 + tS
1(3)
1/fADC
µs
tconv
12-bit conversion time
16 MHz
Wakeup time from OFF
state
tWKUP
3
µs
s
Time before a new
conversion
(5)
∞
tIDLE
Internal reference
voltage startup time
refer to
Table 46
tVREFINT
ms
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- must be tied to ground.
3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 kΩ..
4. Value obtained for continuous conversion on fast channel.
5. The time between 2 conversions, or between ADC ON and the first conversion must be lower than tIDLE.
114/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
In the following three tables, data are guaranteed by characterization result, not tested in
production.
Table 54. ADC1 accuracy with V
= 3.3 V to 2.5 V
DDA
Symbol
Parameter
Conditions
fADC = 16 MHz
Typ.
Max.
Unit
1
1.6
1.6
1.5
2
DNL
Differential non linearity fADC = 8 MHz
fADC = 4 MHz
1
1
fADC = 16 MHz
1.2
1.2
1.2
2.2
1.8
1.8
1.5
1
INL
TUE
Integral non linearity
Total unadjusted error
Offset error
f
ADC = 8 MHz
1.8
1.7
3.0
2.5
2.3
2
fADC = 4 MHz
fADC = 16 MHz
f
ADC = 8 MHz
fADC = 4 MHz
ADC = 16 MHz
LSB
f
Offset
Gain
fADC = 8 MHz
fADC = 4 MHz
1.5
1.2
0.7
f
ADC = 16 MHz
Gain error
fADC = 8 MHz
fADC = 4 MHz
1
1.5
Table 55. ADC1 accuracy with V
Parameter
= 2.4 V to 3.6 V
DDA
Symbol
Typ.
Max.
Unit
DNL
INL
Differential non linearity
Integral non linearity
Total unadjusted error
Offset error
1
2
3
4
2
3
1.7
2
TUE
Offset
Gain
LSB
1
Gain error
1.5
+
Table 56. ADC1 accuracy with V
Parameter
= V
= 1.8 V to 2.4 V
Max.
DDA
REF
Symbol
Typ.
Unit
DNL
INL
Differential non linearity
Integral non linearity
Total unadjusted error
Offset error
1
2
3
2
2
2
3
5
3
3
TUE
Offset
Gain
LSB
Gain error
DocID17943 Rev 6
115/134
121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 42. ADC1 accuracy characteristics
VREF+
VDDA
4096
[1LSBIDEAL
=
(or
depending on package)]
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
4095
4094
4093
(3) End point correlation line
(2)
ET=Total Unadjusted Error: maximum deviation
ET
between the actual and the ideal transfer curves.
(3)
7
6
5
4
3
2
1
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
(1)
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
EO
EL
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
ED
1 LSBIDEAL
0
1
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
VSSA
ai14395b
Figure 43. Typical connection diagram using the ADC
34-ꢃ,ꢀꢍXXX
6
$$
3AMPLE AND HOLD !$#
CONVERTER
6
ꢑꢋꢅ 6
4
ꢈꢀꢊ
#
2
2
!).
!$#
!).X
ꢀꢂꢇBIT
CONVERTER
6
4
6
!).
ꢑꢋꢅ 6
#
ꢈꢀꢊ
!$#
PARASITIC
) ꢍꢑ N!
,
AIꢀꢁꢑꢓꢑC
1. Refer to Table 53 for the values of RAIN and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
116/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
supply pin during ADC
Figure 44. Maximum dynamic current consumption on V
REF+
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
Iref+
700μA
300μA
MS32625V1
(1)
Table 57. R
max for f
= 16 MHz
AIN
ADC
RAIN max (kohm)
Ts
(cycles)
Ts
(µs)
Slow channels
Fast channels
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V
4
9
0.25
Not allowed
0.8
Not allowed
Not allowed
0.8
0.7
2.0
Not allowed
1.0
0.5625
16
24
48
96
192
384
1
1.5
3
2.0
4.0
3.0
3.0
1.8
6.0
4.5
6.8
4.0
15.0
30.0
50.0
50.0
10.0
6
15.0
32.0
50.0
10.0
20.0
12
24
25.0
40.0
50.0
50.0
1. Guaranteed by design, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 45 or Figure 46,
depending on whether V is connected to V or not. Good quality ceramic 10 nF
REF+
DDA
capacitors should be used. They should be placed as close as possible to the chip.
DocID17943 Rev 6
117/134
121
Electrical parameters
STM8L15xx8, STM8L15xR6
Figure 45. Power supply and reference decoupling (V
not connected to V
)
DDA
REF+
STM8L
V
REF+
DDA
1 µF // 10 nF
V
V
1 µF // 10 nF
/V
SSA REF-
ai17031
Figure 46. Power supply and reference decoupling (V
connected to V
)
DDA
REF+
STM8L
V
/V
REF+ DDA
1 µF // 10 nF
V
/V
REF– SSA
ai17032
118/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
9.3.15
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
•
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 61000 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
DD
SS
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 58. EMS data
Conditions
VDD = 3.3 V, TA = +25 °C,
Level/
Class
Symbol
Parameter
Voltage limits to be applied on
VFESD
any I/O pin to induce a functional fCPU= 16 MHz,
2B
disturbance
conforms to IEC 61000
Fast transient voltage burst limits
to be applied through 100 pF on
VDD and VSS pins to induce a
Using HSI
Using HSE
4A
2B
VDD = 3.3 V, TA = +25 °C,
fCPU = 16 MHz,
conforms to IEC 61000
VEFTB
functional disturbance
DocID17943 Rev 6
119/134
121
Electrical parameters
STM8L15xx8, STM8L15xR6
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
(1)
Table 59. EMI data
Max vs.
Monitored
Symbol
Parameter
Conditions
Unit
frequency band
16 MHz
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
10
4
VDD = 3.6 V,
TA = +25 °C,
LQFP80
conforming to
IEC61967-2
dBμV
SEMI
Peak level
1
1.5
-
1. Not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and charge device model. This test conforms to the
JESD22-A114A/A115A standard.
Table 60. ESD absolute maximum ratings
Maximum
Symbol
Ratings
Conditions
Unit
value (1)
Electrostatic discharge voltage
(human body model)
VESD(HBM)
2000
TA = +25 °C
V
Electrostatic discharge voltage
(charge device model)
VESD(CDM)
750
1. Data based on characterization results, not tested in production.
Static latch-up
•
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
120/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Electrical parameters
Table 61. Electrical sensitivities
Parameter
Symbol
Class
LU
Static latch-up class
II
9.4
Thermal characteristics
The maximum chip junction temperature (T
) must never exceed the values given in
Jmax
Table 18: General operating conditions on page 69.
The maximum chip-junction temperature, T
the following equation:
, in degree Celsius, may be calculated using
Jmax
T
= T
+ (P
x Θ )
Jmax
Amax
Dmax JA
Where:
•
•
•
•
T
is the maximum ambient temperature in °C
is the package junction-to-ambient thermal resistance in °C/W
Amax
Θ
JA
P
is the sum of P
and P
(P
= P
+ P
)
I/Omax
Dmax
INTmax
I/Omax
Dmax
INTmax
P
is the product of I and V , expressed in Watts. This is the maximum chip
INTmax
DD
DD
internal power.
•
P
represents the maximum power dissipation on output pins
I/Omax
Where:
P
= Σ (V *I ) + Σ((V -V )*I ),
I/Omax
OL OL
DD OH
OH
taking into account the actual V /I and V /I of the I/Os at low and high level in
OL OL
OH OH
the application.
(1)
Table 62. Thermal characteristics
Parameter
Symbol
Value
Unit
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
Θ
65
°C/W
JA
Thermal resistance junction-ambient
UFQFPN 48 - 7 x 7mm
Θ
32
48
38
°C/W
°C/W
°C/W
JA
Thermal resistance junction-ambient
LQFP 64 - 10 x 10 mm
Θ
JA
Thermal resistance junction-ambient
LQFP 80 - 14 x 14 mm
Θ
JA
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
DocID17943 Rev 6
121/134
121
Package characteristics
STM8L15xx8, STM8L15xR6
10
Package characteristics
10.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
122/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Package characteristics
Figure 47. LQFP80, 14 x 14 mm, 80-pin low profile quad flat package
#
ꢑꢋꢂꢍ MM
'!5'% 0,!.%
CCC
#
,
K
$
,ꢀ
$ꢀ
$ꢉ
ꢅꢑ
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ꢆꢑ
ꢅꢀ
ꢃꢑ
ꢂꢀ
0). ꢀ
)$%.4)&)#!4)/.
ꢀ
ꢂꢑ
E
ꢀ3?-%
Table 63. LQFP80, 14 x 14 mm, 80-pin low profile quad flat package mechanical data
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.380
0.200
16.200
14.200
-
-
-
0.0630
0.0059
0.0571
0.0150
0.0079
0.6378
0.5591
-
0.050
1.350
0.220
0.090
15.800
13.800
-
-
0.0020
0.0531
0.0087
0.0035
0.6220
0.5433
-
-
1.400
0.320
-
0.0551
0.0126
-
c
D
16.000
14.000
12.350
16.000
14.000
12.350
0.6299
0.5512
0.4862
0.6299
0.5512
0.4862
D1
D3
E
15.800
13.800
-
16.200
14.200
-
0.6220
0.5433
-
0.6378
0.5591
-
E1
E3
DocID17943 Rev 6
123/134
133
Package characteristics
STM8L15xx8, STM8L15xR6
Table 63. LQFP80, 14 x 14 mm, 80-pin low profile quad flat package mechanical data (continued)
mm
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
e
L
-
0.450
-
0.650
0.600
1.000
3.5°
-
-
-
0.0256
0.0236
0.0394
3.5°
-
0.750
-
0.0177
0.0295
-
L1
k
0.0°
-
7.0°
0.100
0.0°
-
7.0°
ccc
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal places.
Figure 48. LQFP80 recommended footprint
ꢈꢂ
ꢁꢄ
ꢈꢄ
ꢁꢂ
ꢂꢉꢈꢋ
ꢇꢄ
ꢀꢂ
ꢄꢉꢇ
ꢇꢂ
ꢄ
ꢄꢇꢉꢊꢋ
ꢄꢈꢉꢊ
ꢄ4@'1
1. Dimensions are in millimeters.
124/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Package characteristics
Figure 49. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢑꢋꢂꢍ MM
'!5'% 0,!.%
CCC
#
,
$
,ꢀ
$ꢀ
$ꢉ
ꢉꢉ
ꢆꢃ
ꢉꢂ
ꢆꢓ
B
ꢅꢆ
ꢀꢁ
ꢀꢅ
ꢀ
0). ꢀ
)$%.4)&)#!4)/.
E
ꢍ7?-%?6ꢂ
1. Drawing is not to scale.
Table 64. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
0.05
1.35
0.17
0.09
-
-
1.60
0.15
1.45
0.27
0.20
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
-
-
0.0020
-
1.40
0.22
-
0.0531
0.0551
0.0087
-
0.0067
c
0.0035
D
12.00
10.00
12.00
-
-
-
0.4724
0.3937
0.4724
D1
E
-
-
-
-
-
-
DocID17943 Rev 6
125/134
133
Package characteristics
STM8L15xx8, STM8L15xR6
Table 64. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data (continued)
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
E1
e
-
-
10.00
0.50
3.5°
-
-
-
0.3937
0.0197
3.5°
-
-
-
K
0°
0.45
-
7°
0.75
-
0°
0.0177
-
7°
0.0295
-
L
0.60
1.00
0.0236
0.0394
L1
Number of pins
64
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. LQFP64 Recommended footprint
ꢆꢃ
ꢉꢉ
ꢑꢋꢉ
ꢑꢋꢍ
ꢆꢓ
ꢉꢂ
ꢀꢂꢋꢁ
ꢀꢑꢋꢉ
ꢀꢑꢋꢉ
ꢁꢋꢃ
ꢀꢁ
ꢅꢆ
ꢀꢋꢂ
ꢀꢅ
ꢀ
ꢀꢂꢋꢁ
AIꢀꢆꢓꢑꢓC
1. Dimensions are in millimeters.
126/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Package characteristics
Figure 51. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline
3%!4).'
0,!.%
#
ꢑꢋꢂꢍ MM
'!5'% 0,!.%
CCC
#
$
,
$ꢀ
$ꢉ
,ꢀ
ꢉꢅ
ꢂꢍ
ꢉꢁ
ꢂꢆ
B
ꢆꢃ
ꢀꢉ
0). ꢀ
)$%.4)&)#!4)/.
ꢀ
ꢀꢂ
E
ꢍ"?-%?6ꢂ
1. Drawing is not to scale.
Table 65. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
A2
b
-
-
1.600
0.150
1.450
0.270
0.200
9.200
7.200
-
-
-
0.0630
0.0059
0.0571
0.0106
0.0079
0.3622
0.2835
-
0.050
1.350
0.170
0.090
8.800
6.800
-
-
0.0020
0.0531
0.0067
0.0035
0.3465
0.2677
-
-
1.400
0.220
-
0.0551
0.0087
-
c
D
9.000
7.000
5.500
9.000
7.000
5.500
0.500
0.600
1.000
3.5°
0.3543
0.2756
0.2165
0.3543
0.2756
0.2165
0.0197
0.0236
0.0394
3.5°
D1
D3
E
8.800
6.800
-
9.200
7.200
-
0.3465
0.2677
-
0.3622
0.2835
-
E1
E3
e
-
-
-
-
L
0.450
-
0.750
-
0.0177
-
0.0295
-
L1
k
0°
7°
0°
7°
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID17943 Rev 6
127/134
133
Package characteristics
STM8L15xx8, STM8L15xR6
Figure 52. LQFP48 recommended footprint
ꢑꢋꢍꢑ
ꢀꢋꢂꢑ
ꢑꢋꢉꢑ
ꢀꢉ
ꢂꢆ
ꢀꢂ
ꢂꢍ
ꢁꢋꢉꢑ
ꢑꢋꢂꢑ
ꢍꢋꢃꢑ
ꢓꢋꢁꢑ
ꢁꢋꢉꢑ
ꢀ
ꢉꢅ
ꢆꢃ
ꢉꢁ
ꢀꢋꢂꢑ
ꢍꢋꢃꢑ
ꢓꢋꢁꢑ
ꢍ"?&0?6ꢂ
1. Dimensions are in millimeters.
128/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Package characteristics
Figure 53. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
0IN ꢀ INDENTIFIER
LASER MARKING AREA
$
!
%
9
%
3EATING
PLANE
4
DDD
!ꢀ
B
E
$ETAIL 9
$
%XPOSED PAD
AREA
$ꢂ
ꢀ
,
ꢆꢃ
# ꢑꢋꢍꢑꢑXꢆꢍ
PINꢀ CORNER
2 ꢑꢋꢀꢂꢍ TYPꢋ
$ETAIL :
%ꢂ
ꢀ
ꢆꢃ
:
!ꢑ"ꢓ?-%?6ꢉ
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
Table 66. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data
millimeters
Typ
inches(1)
Symbol
Min
Max
Min
Typ
Max
A
A1
D
0.500
0.000
6.900
6.900
5.500
5.500
0.300
-
0.550
0.020
7.000
7.000
5.600
5.600
0.400
0.152
0.250
0.500
0.080
0.600
0.050
7.100
7.100
5.700
5.700
0.500
-
0.0197
0.0000
0.2717
0.2717
0.2165
0.2165
0.0118
-
0.0217
0.0008
0.2756
0.2756
0.2205
0.2205
0.0157
0.0060
0.0098
0.0197
0.0031
0.0236
0.0020
0.2795
0.2795
0.2244
0.2244
0.0197
-
E
D2
E2
L
T
b
0.200
-
0.300
-
0.0079
-
0.0118
-
e
ddd
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID17943 Rev 6
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133
Package characteristics
STM8L15xx8, STM8L15xR6
Figure 54. UFQFPN48 Recommended footprint
ꢁꢋꢉꢑ
ꢅꢋꢂꢑ
ꢆꢃ
ꢉꢁ
ꢀ
ꢉꢅ
ꢍꢋꢅꢑ
ꢑꢋꢂꢑ
ꢁꢋꢉꢑ
ꢍꢋꢃꢑ
ꢅꢋꢂꢑ
ꢍꢋꢅꢑ
ꢑꢋꢉꢑ
ꢀꢂ
ꢂꢍ
ꢀꢉ
ꢂꢆ
ꢑꢋꢁꢍ
ꢑꢋꢍꢑ
ꢑꢋꢍꢍ
ꢍꢋꢃꢑ
!ꢑ"ꢓ?&0?6ꢂ
1. Dimmensions are in millimeters.
130/134
DocID17943 Rev 6
STM8L15xx8, STM8L15xR6
Ordering information scheme
11
Ordering information scheme
Table 67. Ordering information scheme
STM8 L 152 C
Example:
8
T
6
D xx
Device family
STM8 microcontroller
Product type
L = Low power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
C = 48 pins
R = 64 pins
M = 80 pins
Program memory size
8 = 64 Kbytes of Flash memory
6 = 32 Kbytes
Package
T = LQFP
U= UFQFPN
Temperature range
3 = Industrial temperature range, – 40 to 125 °C
7 = Industrial temperature range, – 40 to 105 °C
6 = Industrial temperature range, – 40 to 85 °C
Option
Blank = VDD range from 1.8 to 3.6 V and BOR enabled
D = VDD range from 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the ST
Sales Office nearest to you.
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Revision history
STM8L15xx8, STM8L15xR6
12
Revision history
Table 68. Document revision history
Changes
Date
Revision
13-Sep-2010
1
Initial release.
Updated Section 9.3.3: Supply current characteristics
Updated Section 9.3.2: Embedded reset and power control block
characteristics.
Updated Section 9.3.3: Supply current characteristics
Updated Section 9.3.13: 12-bit DAC characteristics
Updated Section 9.3.14: 12-bit ADC1 characteristics
Updated Section 9.3.15: EMC characteristics
20-Dec-2010
17-Jan-2011
2
3
Removed references to STM8L150M8 devices.
Updated Table 1: Device summary.
Table 5: High density and medium+ density STM8L15x pin description:
updated PB4/43&35, PB4/28, PC1, PI3, and pins 33 to 36 of LQFP80;
updated footnotes.
TIMx_TRIG changed to TIMx_ETR and “Standard port” changed to
“high sink port”.
Table 15: Voltage characteristics: updated
Table 16: Current characteristics: updated
11-Mar-2011
4
Table 35: RAM and hardware registers: updated VRM data min.
retention.
Added Table 9.3.6: I/O current injection characteristics.
Table 38: I/O static characteristics: updated
Table 45: LCD characteristics: updated
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Revision history
Table 68. Document revision history (continued)
Revision Changes
Date
Updated capacitive sensing channels and “Dynamic consumption” in
Features
Updated LCD feature in Table 2: High density and medium+ density
STM8L15xx low power device features and peripheral counts
Updated Halt mode definition in Section 3.1: Low power modes
Added Bootloader
Updated Section 3.12: System configuration controller and routing
interface
Added Section 3.13: Touch sensing
Table 5: High density and medium+ density STM8L15x pin description:
updated NRST/PA1, PI0, PI1, PI2, PE0, PE1, PE2, PF4, PF5, PF6,
PF7, footnote 1. and added Note:
Updated ‘0x00 502E to 0x00 5049’ reserved area in Table 9: General
hardware register map
03-Apr-2013
5
Updated reference to SWIM/DEBUG manual in Section 7: Option bytes
Updated BOR factory default settings to 0x00 in Table 12: Option byte
addresses
Corrected ROP option byte value in Table 12: Option byte addresses
Added Figure 44: Maximum dynamic current consumption on VREF+
supply pin during ADC conversion
Updated STABVREFINT max value in Table 46: Reference voltage
characteristics
Updated Figure 40: SPI1 timing diagram - master mode
Added Table 57: RAIN max for fADC = 16 MHz
Updated Max DAC_OUT in Table 50: DAC characteristics
Updated Section 9.3.12: Comparator characteristics
Added ‘Top view’ footnotes under the pinout figures in Section 4: Pin
description
Updated the PF4-PF7 pins for the LQFP80 in Table 5: High density and
medium+ density STM8L15x pin description
Updated all packages:
31-Jul-2013
6
Updated Figure 53: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
outline and Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
mechanical data
Added Figure 48: LQFP80 recommended footprint
Added ‘tape and reel’ in Table 67: Ordering information scheme
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