STM8L152R6T3STM8L152R6T3

STM8L151M8/R8/C8 STM8L151R6

STM8L152M8/R8/C8 STM8L152R6

8-bit ultralow power MCU, up to 64 KB Flash, up to 2KB data EEPROM

RTC, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, comparators

Preliminary data

Features

■ Operating conditions

– Operating power supply: 1.65 to 3.6 V

UFQFPN48

(without BOR), 1.8 to 3.6 V (with BOR)

LQFP80

LQFP64

LQFP48

– Temperature range: −40 to 85 or 125 °C

■ Low power features

■ DMA

– 4 channels supporting ADC, DACs, SPIs,

2

– 5 low power modes: Wait, Low power run,

Low power wait, Active-halt with RTC, Halt

I C, USARTs, timers

– 1 channel for memory-to-memory

– Ultralow leakage per I/0: 50 nA

– Fast wakeup from Halt: 5 µs

■ 2x12-bit DAC (dual mode) with output buffer

■ 12-bit ADC up to 1 Msps/28 channels

■ Advanced STM8 core

– Temp. sensor and internal ref. voltage

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

■ 2 ultralow power comparators

– 1 with fixed threshold and 1 rail to rail

– Wakeup capability

■ Reset and supply management

■ Timers

– Low power, ultrasafe BOR reset with 5

selectable thresholds

– Ultralow power POR/PDR

– Three 16-bit timers with 2 channels (IC,

OC, PWM), quadrature encoder

– One 16-bit advanced control timer with 3

channels, supporting motor control

– Programmable voltage detector (PVD)

■ Clock management

– One 8-bit timer with 7-bit prescaler

– 1 Window and 1 independent watchdog

– Beeper timer with 1, 2 or 4 kHz frequencies

– 32 kHz and 1-16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

■ Communication interfaces

– Two synchronous serial interface (SPI)

■ Low power RTC

2

– Fast I C 400 kHz SMBus and PMBus

– Three USARTs (ISO 7816 interface + IrDA)

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5ppm accuracy

– LSE security system

■ Up to 67 I/Os, all mappable on interrupt vectors

■ Up to 16 capacitive sensing channels with free

– Auto-wakeup from Halt w/ periodic interrupt

– Advanced anti-tamper detection

firmware

■ Development support

■ LCD: 8x40 or 4x44 w/ step-up converter

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

■ Memories

– Up to 64 KB of Flash program memory plus

up to 2 KB of data EEPROM with ECC and

RWW

■ 96-bit unique ID

– Flexible write/read protection modes

– Up to 4 KB of RAM

September 2010

Doc ID 17943 Rev 1

1/122

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

STM8L15xx8, STM8L15xR6

Contents

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

STM8L Ultralow power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . . . . 9

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1

3.2

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.1

3.2.2

Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3

Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.1

3.3.2

3.3.3

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4

3.5

3.6

3.7

3.8

3.9

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10 Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.11 Ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 19

3.13 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.13.1 16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.13.2 16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 20

3.13.3 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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Contents

3.15 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.16.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2

3.16.2 I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.16.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.17 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4

5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.1

5.2

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6

7

8

9

Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9.2

9.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.3.7

9.3.8

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 71

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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Contents

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9.3.9

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

9.3.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.3.11 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.3.12 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

9.4

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

10.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11

12

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

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List of tables

Table 1.

High density and medium+ density STM8L15xx low power device features and

peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

High density and medium+ density STM8L15x pin description . . . . . . . . . . . . . . . . . . . . . 26

Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Factory conversion regiserst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Total current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Total current consumption and timing in Low power run mode at VDD = 1.65 V to

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . 78

Total current consumption and timing in Active-halt mode

Table 22.

Table 23.

at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 81

Total current consumption and timing in Halt mode at VDD = 2 V . . . . . . . . . . . . . . . . . . . 81

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 93

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

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List of tables

STM8L15xx8, STM8L15xR6

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 109

EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 117

LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 118

UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm

pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 64.

6/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

High density and medium+ density STM8L15xx device block diagram . . . . . . . . . . . . . . 12

Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

STM8L151M8 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM8L152M8 80-pin package pinout (with LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STM8L151R8 and STM8L151R6 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . 24

STM8L152R8 and STM8L152R6 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 24

STM8L151C8 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STM8L152C8 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 12. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 13. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 14. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 15. Typical HSI frequency vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

DD

Figure 16. Typical LSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 17. Typical VIL and VIH vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 18. Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 19. Typical pull-up resistance R vs V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

PU

DD

Figure 20. Typical pull-up current I vs V with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

pu

DD

Figure 21. Typ. VOL @ VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 22. Typ. VOL @ VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 23. Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 24. Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 25. Typ. VDD - VOH @ VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 26. Typ. VDD - VOH @ VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 27. Typical NRST pull-up resistance R vs V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PU

DD

Figure 28. Typical NRST pull-up current I vs V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

pu

DD

Figure 29. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 30. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

(1)

Figure 31. SPI1 timing diagram - slave mode and CPHA=1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

(1)

Figure 32. SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 33. Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 34. ADC1 accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 36. Power supply and reference decoupling (V

not connected to V

). . . . . . . . . . . . . 111

REF+

DDA

Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . 111

Figure 38. 80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 117

(1)

Figure 40. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 41. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

(1)

Figure 42. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

(1)

Figure 44. Recommended footprint (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Doc ID 17943 Rev 1

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Introduction

STM8L15xx8, STM8L15xR6

1

Introduction

This document describes the features, pinout, mechanical data and ordering information for:

High density STM8L15xx devices: STM8L151x8 and STM8L152x8 microcontrollers with a

Flash memory density of 64 Kbytes.

Medium+ density STM8L15xx devices: STM8L151R6 and STM8L152R6 microcontrollers

with Flash memory density of 32 Kbytes.

For further details on the STMicroelectronics Ultralow power family please refer to

Section 2.3: Ultralow power continuum on page 11.

For detailed information on device operation and registers, refer to the reference manual

(RM0031).

For information on to the Flash program memory and data EEPROM, refer to the

programming manual (PM0054).

For information on the debug module and SWIM (single wire interface module), refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 core, refer to the STM8 CPU programming manual (PM0044).

2

Description

The high density and medium+ density STM8L15xx Ultralow power devices feature an

enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at

16 MHz) while maintaining the advantages of a CISC architecture with improved code

density, a 24-bit linear addressing space and an optimized architecture for low power

operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive in-application debugging and ultrafast Flash programming.

All high density and medium+ density STM8L15xx microcontrollers feature embedded data

EEPROM and low power low-voltage single-supply program Flash memory.

The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit

ADC, two DACs, two comparators, a real-time clock, four 16-bit timers, one 8-bit timer, as

2

well as standard communication interfaces such as two SPIs, an I C interface, and three

USARTs. A 8x40 or 4x44-segment LCD is available on the STM8L152x8 devices. The

modular design of the peripheral set allows the same peripherals to be found in different ST

microcontroller families including 32-bit families. This makes any transition to a different

family very easy, and simplified even more by the use of a common set of development

tools.

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STM8L15xx8, STM8L15xR6

Description

2.1

STM8L Ultralow power 8-bit family benefits

High density and medium+ density STM8L15xxdevicesare part of the STM8L Ultralow

power family providing the following benefits:

Integrated system

●

–

Up to 64 Kbytes of high-density embedded Flash program memory

Up to 2 Kbytes of data EEPROM

Up to 4 Kbytes of RAM

Internal high-speed and low-power low speed RC.

Embedded reset

●

Ultralow power consumption

–

1 µA in Active-halt mode

Clock gated system and optimized power management

Capability to execute from RAM for Low power wait mode and Low power run

mode

●

Advanced features

–

Up to 16 MIPS at 16 MHz CPU clock frequency

Direct memory access (DMA) for memory-to-memory or peripheral-to-memory

access.

Short development cycles

–

Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals.

–

Wide choice of development tools

STM8L Ultralow power microcontrollers can operate either from 1.8 to 3.6 V (down to 1.65 V

at power-down) or from 1.65 to 3.6 V. They are available in the −40 to +85 °C and −40 to

+125 °C temperature ranges.

These features make the STM8L Ultralow power microcontroller families suitable for a wide

range of applications:

●

Medical and handheld equipment

Application control and user interface

PC peripherals, gaming, GPS and sport equipment

Alarm systems, wired and wireless sensors

Metering

The devices are offered in four different packages from 48 to 80 pins. Different sets of

peripherals are included depending on the device. Refer to Section 3 for an overview of the

complete range of peripherals proposed in this family.

All STM8L Ultralow power products are based on the same architecture with the same

memory mapping and a coherent pinout.

Figure 1 shows the block diagram of the High density and medium+ density STM8L15xx

families.

Doc ID 17943 Rev 1

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Description

STM8L15xx8, STM8L15xR6

2.2

Device overview

Table 1.

High density and medium+ density STM8L15xx low power device features and

peripheral counts

Features

STM8L15xC8

STM8L15xR8

STM8L15xM8

STM8L15xR6

Flash (Kbytes)

Data EEPROM (Kbytes)

RAM (Kbytes)

LCD

64

32

2

1

4

2

8x28 or 4x32⁽¹⁾

8x36 or 4x40⁽¹⁾

8x40 or 4x44⁽¹⁾

8x36 or 4x40⁽¹⁾

1

Basic

(8-bit)

3

Timers

General purpose

(16-bit)

1

Advanced control

(16-bit)

SPI

2

1

2

1

2

1

2

1

Communicatio

n interfaces

I2C

USART

3

GPIOs

41⁽²⁾

54⁽²⁾

68⁽²⁾

54⁽²⁾

12-bit synchronized ADC

(number of channels)

1

(25)

1

(28)

1

(28)

1

(28)

12-Bit DAC

2

Number of channels

Comparators (COMP1/COMP2)

Others

2

RTC, window watchdog, independent watchdog,

16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external oscillator

CPU frequency

16 MHz

1.8 to 3.6 V (down to 1.65 V at power-down) with BOR

1.65 to 3.6 V without BOR

Operating voltage

Operating temperature

Packages

−40 to +85 °C / −40 to +125 °C

UFQFPN48

LQFP64

LQFP80

LQFP64

LQFP48

1. STM8L152xx versions only.

2. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as

general purpose output only (PA1).

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Description

2.3

Ultralow power continuum

The Ultralow power STM8L151xx and STM8L152xx are fully pin-to-pin, software and feature

compatible. Besides the full compatibility within the family, the devices are part of

STMicroelectronics microcontrollers UltraLow power strategy which also includes

STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of

performance, peripherals, system architecture, and features.

They are all based on STMicroelectronics 0.13 µm Ultralow leakage process.

Note:

1

2

The STM8L151xx and STM8L152xx are pin-to-pin compatible with STM8L101xx devices.

The STM32L family is pin-to-pin compatible with the general purpose STM32F family.

Please refer to STM32L15xx documentation for more information on these devices.

Performance

All families incorporate highly energy-efficient cores with both Harvard architecture and

pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core

for STM32L family. In addition specific care for the design architecture has been taken to

optimize the mA/DMIPS and mA/MHz ratios.

This allows the Ultralow power performance to range from 5 up to 33.3 DMIPs.

Shared peripherals

STM8L151xx/152xx and STM32L15xx share identical peripherals which ensure a very easy

migration from one family to another:

●

Analog peripherals: ADC1, DAC1/DAC2, and comparators COMP1/COMP2

Digital peripherals: RTC and some communication interfaces

●

Common system strategy

To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx devices use

a common architecture:

●

Same power supply range from 1.65 to 3.6 V. For STM8L101xx and medium density

STM8L15xx, the power supply must be above 1.8 V at power-on, and go below 1.65 V

at power-down.

●

Architecture optimized to reach ultralow consumption both in low power modes and

Run mode

●

Fast startup strategy from low power modes

Flexible system clock

Ultrasafe reset: same reset strategy for both STM8L15xx and STM32L15xx including

power-on reset, power-down reset, brownout reset and programmable voltage detector.

Features

ST UtraLow power continuum also lies in feature compatibility:

●

More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm

Memory density ranging from 4 to 128 Kbytes

●

Doc ID 17943 Rev 1

11/122

Functional overview

STM8L15xx8, STM8L15xR6

3

Functional overview

Figure 1.

High density and medium+ density STM8L15xx device block diagram

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1. Legend:

AF: alternate function

ADC: Analog-to-digital converter

BOR: Brownout reset

DMA: Direct memory access

DAC: Digital-to-analog converter

I²C: Inter-integrated circuit multimaster interface

IWDG: Independent watchdog

12/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Functional overview

LCD: Liquid crystal display

POR/PDR: Power on reset / power-down reset

RTC: Real-time clock

SPI: Serial peripheral interface

SWIM: Single wire interface module

USART: Universal synchronous asynchronous receiver transmitter

WWDG: Window watchdog

3.1

Low power modes

The High density and medium+ density STM8L15xxdevices support five low power modes

to achieve the best compromise between low power consumption, short startup time and

available wakeup sources:

●

Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal

or external interrupt or a Reset can be used to exit the microcontroller from Wait mode

(WFE or WFI mode).

Low power run mode: The CPU and the selected peripherals are running. Execution

is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data

EEPROM are stopped and the voltage regulator is configured in Ultralow power mode.

The microcontroller enters Low power run mode by software and can exit from this

mode by software or by a reset.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

●

Low power wait mode: This mode is entered when executing a Wait for event in Low

power run mode. It is similar to Low power run mode except that the CPU clock is

stopped. The wakeup from this mode is triggered by a Reset or by an internal or

external event (peripheral event generated by the timers, serial interfaces, DMA

controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an

event, the system goes back to Low power run mode.

All interrupts must be masked. They cannot be used to exit the microcontroller from this

mode.

●

Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup

can be triggered by RTC interrupts, external interrupts or reset.

Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.

The wakeup is triggered by an external interrupt or reset. A few peripherals have also a

wakeup from Halt capability. Switching off the internal reference voltage reduces power

consumption. Through software configuration it is also possible to wake up the device

without waiting for the internal reference voltage wakeup time to have a fast wakeup

time of 5 µs.

3.2

Central processing unit STM8

3.2.1

Advanced STM8 Core

The 8-bit STM8 core is designed for code efficiency and performance with an Harvard

architecture and a 3-stage pipeline.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing, and 80 instructions.

Doc ID 17943 Rev 1

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Functional overview

STM8L15xx8, STM8L15xR6

Architecture and registers

●

Harvard architecture

3-stage pipeline

32-bit wide program memory bus - single cycle fetching most instructions

X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

●

8-bit accumulator

24-bit program counter - 16 Mbyte linear memory space

16-bit stack pointer - access to a 64 Kbyte level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

●

20 addressing modes

Indexed indirect addressing mode for lookup tables located anywhere in the address

space

●

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

●

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct memory-to-memory transfers

3.2.2

Interrupt controller

The high density and medium+ density STM8L15xxdevices feature a nested vectored

interrupt controller:

●

Nested interrupts with 3 software priority levels

32 interrupt vectors with hardware priority

Up to 40 external interrupt sources on 11 vectors

Trap and reset interrupts

3.3

Reset and supply management

3.3.1

Power supply scheme

The device requires a 1.65 V to 3.6 V operating supply voltage (V ). The external power

DD

supply pins must be connected as follows:

●

V

, V

= 1.65 to 3.6 V: external power supply

SS1 DD1 SS2 DD2

SS3

DD3

SS4 DD4

for I/Os and for the internal regulator. Provided externally through V pins, the

DD

14/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

corresponding ground pin is V . V

Functional overview

/V /V /V

/V

and V

SS

SS1 SS2 SS3 SS4 DD1 DD2 DD3 DD4

must not be left unconnected.

V , V = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum

SSA

●

DDA

voltage to be applied to V

is 1.8 V when the ADC1 is used). V

and V

must be

DDA

SSA

connected to V and V , respectively.

DD

SS

●

V

, V

(for ADC1): external reference voltage for ADC1. Must be provided

REF-

REF+

externally through V

and V

pin.

REF+

REF-

V

(for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided

REF+

externally through V

.

REF+

3.3.2

Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates

between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from

1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,

either to confirm or modify default thresholds, or to disable BOR permanently (in which

case, the V min value at power-down is 1.65 V).

DD

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Halt mode, it is possible to automatically switch off the

internal reference voltage (and consequently the BOR) in Halt mode. The device remains in

reset state when V is below a specified threshold, V

or V

, without the need for

DD

POR/PDR

BOR

any external reset circuit.

Note:

When the microcontroller operates between 1.65 and 3.6 V, BOR is permanently disabled.

The device features an embedded programmable voltage detector (PVD) that monitors the

V

/V

power supply and compares it to the V

threshold. This PVD offers 7 different

DD DDA

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when V /V drops below the V threshold and/or when

DD DDA

PVD

V

/V

is higher than the V

threshold. The interrupt service routine can then generate

DD DDA

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3

Voltage regulator

The high density and medium+ density STM8L15xxdevices embed an internal voltage

regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes:

●

Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event

(WFE) modes.

Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low

power wait modes.

When entering Halt or Active-halt modes, the system automatically switches from the MVR

to the LPVR in order to reduce current consumption.

3.4

Clock management

The clock controller distributes the system clock (SYSCLK) coming from different oscillators

to the core and the peripherals. It also manages clock gating for low power modes and

ensures clock robustness.

Doc ID 17943 Rev 1

15/122

Functional overview

Features

STM8L15xx8, STM8L15xR6

●

Clock prescaler: to get the best compromise between speed and current consumption

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

●

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register.

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

System clock sources: 4 different clock sources can be used to drive the system

clock:

–

1-16 MHz High speed external crystal (HSE)

16 MHz High speed internal RC oscillator (HSI)

32.768 Low speed external crystal (LSE)

38 kHz Low speed internal RC (LSI)

●

RTC and LCD clock sources: the above four sources can be chosen to clock the RTC

and the LCD, whatever the system clock.

Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the

application program as soon as the code execution starts.

●

Clock security system (CSS): This feature can be enabled by software. If a HSE clock

failure occurs, the system clock is automatically switched to HSI.

Configurable main clock output (CCO): This outputs an external clock for use by the

application.

Figure 2.

Clock tree diagram

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16/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Functional overview

3.5

Low power real-time clock

The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.

Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,

year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31

day months are made automatically. The subsecond field can also be read in binary format.

The calendar can be corrected from 1 to 32767 RTC clock pulses. This allows to make a

synchronization to a master clock.

The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm.

It provides a programmable alarm and programmable periodic interrupts with wakeup from

Halt capability.

●

Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is

from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time can reach

36 hours

Periodic alarms based on the calendar can also be generated from LSE period to every

year

A clock security system detects a failure on LSE, and can provide an interrupt with wakeup

capability. The RTC clock can automatically switch to LSI in case of LSE failure.

The RTC also provides 3 anti-tamper detection pins. This detection embeds a

programmable filter and can wakeup the MCU.

3.6

LCD (Liquid crystal display)

The liquid crystal display drives up to 8 common terminals and up to 40 segment terminals

to drive up to 320 pixels. It can also be configured to drive up to 4 common and 44 segments

(up to 176 pixels).

●

Internal step-up converter to guarantee contrast control whatever V

.

DD

Static 1/2, 1/3, 1/4, 1/8 duty supported.

Static 1/2, 1/3, 1/4 bias supported.

Phase inversion to reduce power consumption and EMI.

Up to 8 pixels which can programmed to blink.

The LCD controller can operate in Halt mode.

Note:

Unnecessary segments and common pins can be used as general I/O pins.

3.7

Memories

The high density and medium+ density STM8L15xxdevices have the following main

features:

●

Up to 4 Kbytes of RAM

●

The non-volatile memory is divided into three arrays:

–

Up to 64 Kbytes of medium-density embedded Flash program memory

Up to 2 Kbytes of Data EEPROM

Option bytes.

Doc ID 17943 Rev 1

17/122

Functional overview

STM8L15xx8, STM8L15xR6

The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-

write (RWW): it is possible to execute the code from the program matrix while

programming/erasing the data matrix.

The option byte protects part of the Flash program memory from write and readout piracy.

3.8

3.9

DMA

A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and

peripherals-from/to-memory transfer capability. The 4 channels are shared between the

following IPs with DMA capability: ADC1, DAC1,DAC2, I2C1, SPI1, SPI2, USART1,

USART2, USART3, and the 5 Timers.

Analog-to-digital converter

●

12-bit analog-to-digital converter (ADC1) with 28 channels (including 4 fast channel),

temperature sensor and internal reference voltage

●

Conversion time down to 1 µs with f

= 16 MHz

SYSCLK

Programmable resolution

Programmable sampling time

Single and continuous mode of conversion

Scan capability: automatic conversion performed on a selected group of analog inputs

Analog watchdog: interrupt generation when the converted voltage is outside the

programmed threshold

●

Triggered by timer

Note:

ADC1 can be served by DMA1.

3.10

Digital-to-analog converter

●

12-bit DAC with 2 buffered outputs (two digital signals can be converted into two analog

voltage signal outputs)

●

Synchronized update capability using timers

DMA capability for each channel

External triggers for conversion

Noise-wave generation

Triangular-wave generation

Dual DAC channels with independent or simultaneous conversions

Input reference voltage V

for better resolution

REF+

Note:

DAC can be served by DMA1.

18/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Functional overview

3.11

Ultralow power comparators

The high density and medium+ density STM8L15xxdevices embed two comparators

(COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage

reference can be internal or external (coming from an I/O).

●

One comparator with fixed threshold (COMP1).

●

One comparator rail to rail with fast or slow mode (COMP2). The threshold can be one

of the following:

–

DAC output

External I/O

Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)

The two comparators can be used together to offer a window function. They can wake up

from Halt mode.

3.12

3.13

System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate

functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.

The highly flexible routing interface allows application software to control the routing of

different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog

signals to ADC1, COMP1, COMP2, DAC1 and the internal reference voltage V

.

REFINT

Finally, it provides a set of registers for efficiently managing a set of dedicated I/Os

TM

supporting up to 16 capacitive sensing channels using the ProxSense technology.

Timers

The high density and medium+ density STM8L15xxdevices contain one advanced control

timer (TIM1), three 16-bit general purpose timers (TIM2,TIM3 and TIM5) and one 8-bit basic

timer (TIM4).

All the timers can be served by DMA1.

Table 2 compares the features of the advanced control, general-purpose and basic timers.

Table 2.

Timer

Timer feature comparison

DMA1

Counter Counter

Capture/compare Complementary

Prescaler factor

request

resolution

type

channels

outputs

generation

Any integer

from 1 to 65536

TIM1

3 + 1

3

TIM2

TIM3

TIM5

16-bit

8-bit

up/down

up

Any power of 2

from 1 to 128

Yes

2

0

None

Any power of 2

from 1 to 32768

TIM4

Doc ID 17943 Rev 1

19/122

Functional overview

STM8L15xx8, STM8L15xR6

3.13.1

16-bit advanced control timer (TIM1)

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and half-bridge driver.

●

16-bit up, down and up/down autoreload counter with 16-bit prescaler

●

3 independent capture/compare channels (CAPCOM) configurable as input capture,

output compare, PWM generation (edge and center aligned mode) and single pulse

mode output

●

1 additional capture/compare channel which is not connected to an external I/O

Synchronization module to control the timer with external signals

Break input to force timer outputs into a defined state

3 complementary outputs with adjustable dead time

Encoder mode

Interrupt capability on various events (capture, compare, overflow, break, trigger)

3.13.2

16-bit general purpose timers (TIM2, TIM3, TIM5)

●

16-bit autoreload (AR) up/down-counter

7-bit prescaler adjustable to fixed power of 2 ratios (1…128)

2 individually configurable capture/compare channels

PWM mode

Interrupt capability on various events (capture, compare, overflow, break, trigger)

Synchronization with other timers or external signals (external clock, reset, trigger and

enable)

3.13.3

8-bit basic timer (TIM4)

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable

prescaler. It can be used for timebase generation with interrupt generation on timer overflow

or for DAC trigger generation.

3.14

Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the applications.

3.14.1

Window watchdog timer

The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

3.14.2

Independent watchdog timer

The independent watchdog peripheral (IWDG) can be used to resolve processor

malfunctions due to hardware or software failures.

20/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Functional overview

It is clocked by the internal LSI RC clock source, and thus stays active even in case of a

CPU clock failure.

3.15

Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in

the range of 1, 2 or 4 kHz.

3.16

Communication interfaces

3.16.1

SPI

The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial

communication with external devices.

●

Maximum speed: 8 Mbit/s (f

/2) both for master and slave

SYSCLK

Full duplex synchronous transfers

Simplex synchronous transfers on 2 lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

Hardware CRC calculation

Slave/master selection input pin

Note:

SPI1 and SPI2 can be served by the DMA1 Controller.

2

3.16.2

I C

2

The I C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-

specific sequencing, protocol, arbitration and timing.

●

2

Master, slave and multi-master capability

Standard mode up to 100 kHz and fast speed modes up to 400 kHz.

7-bit and 10-bit addressing modes.

SMBus 2.0 and PMBus support

Hardware CRC calculation

Note:

I C1 can be served by the DMA1 Controller.

3.16.3

USART

The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous

communications with external devices requiring an industry standard NRZ asynchronous

serial data format. It offers a very wide range of baud rates.

●

1 Mbit/s full duplex SCI

SPI1 emulation

High precision baud rate generator

Smartcard emulation

IrDA SIR encoder decoder

Single wire half duplex mode

Doc ID 17943 Rev 1

21/122

Functional overview

STM8L15xx8, STM8L15xR6

Note:

USART1, USART2 and USART3 can be served by the DMA1 Controller.

3.17

Infrared (IR) interface

The high density and medium+ density STM8L15xxdevices contain an infrared interface

which can be used with an IR LED for remote control functions. Two timer output compare

channels are used to generate the infrared remote control signals.

3.18

Development support

Development tools

Development tools for the STM8 microcontrollers include:

●

The STice emulation system offering tracing and code profiling

●

The STVD high-level language debugger including C compiler, assembler and

integrated development environment

●

The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit

debugging/programming tools.

Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time

in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory

programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured

emulator. Beside memory and peripherals, CPU operation can also be monitored in real-

time by means of shadow registers.

Bootloader

A bootloader is available to reprogram the Flash memory using the USART1, USART2,

USART3 (USARTs in asynchronous mode), SPI1 or SPI2 interfaces.

22/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

4

Pin description

Figure 3. STM8L151M8 80-pin package pinout (without LCD)

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Doc ID 17943 Rev 1

23/122

Pin description

Figure 5.

STM8L15xx8, STM8L15xR6

STM8L151R8 and STM8L151R6 64-pin pinout (without LCD)

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Figure 6.

STM8L152R8 and STM8L152R6 64-pin pinout (with LCD)

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AIꢀꢁꢃꢉꢍ

24/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Figure 7. STM8L151C8 48-pin pinout (without LCD)

Pin description

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ꢀ

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ꢉꢉ

ꢉꢂ

ꢉꢀ

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ꢂꢃ

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ꢂꢅ

ꢂꢍ

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0&ꢐ

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0"ꢅ

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0"ꢆ

0"ꢉ

0"ꢂ

0"ꢀ

0!ꢐ

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0!ꢂ

ꢂ

ꢉ

ꢆ

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0!ꢆ

0!ꢍ

0!ꢅ

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AIꢀꢁꢃꢉꢂ

1. Pin 13 is reserved and must be tied to V_DD

.

Figure 8.

STM8L152C8 48-pin pinout (with LCD)

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ꢀ

ꢉꢅ

ꢉꢍ

ꢉꢆ

ꢉꢉ

ꢉꢂ

ꢉꢀ

ꢉꢐ

ꢂꢒ

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0!ꢂ

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0$ꢍ

0$ꢆ

0&ꢐ

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0"ꢅ

0"ꢍ

0"ꢆ

0"ꢉ

0"ꢂ

0"ꢀ

ꢉ

ꢆ

0!ꢉ

0!ꢆ

0!ꢍ

0!ꢅ

ꢍ

ꢅ

ꢁ

0!ꢁ

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AIꢀꢁꢃꢉꢆ

Doc ID 17943 Rev 1

25/122

Pin description

STM8L15xx8, STM8L15xR6

Table 3.

Legend/abbreviation

Type

I= input, O = output, S = power supply

Input

CM = CMOS

Level

Output

Input

HS = high sink/source (20 mA)

float = floating, wpu = weak pull-up

Port and control

configuration

Output

T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e.

“under reset”) and after internal reset release (i.e. at reset state).

Table 4.

High density and medium+ density STM8L15x pin description

number

Input

Output

Pin name

Default alternate function

1

2

3

4

6

-

PH0/LCD SEG 36 ⁽³⁾

PH1/LCD SEG 37 ⁽³⁾

PH2/LCD SEG 38 ⁽³⁾

PH3/LCD SEG 39 ⁽³⁾

I/O

X

HS

X

X Port H0 LCD segment 36

HS

X Port H1 LCD segment 37

X Port H2 LCD segment 38

X Port H3 LCD segment 39

-

2

2 NRST/PA1⁽¹⁾

X Reset

PA1

PA2/OSC_IN/

3 [USART1_TX]⁽²⁾

[SPI1_MISO] ⁽²⁾

HSE oscillator input /

X Port A2 [USART1 transmit] / [SPI1

7

8

3

4

/

I/O

X

HS

X

master in- slave out] /

HSE oscillator output /

X Port A3 [USART1 receive]/ [SPI1

master out/slave in]/

PA3/OSC_OUT/[USART1

4

_RX]⁽²⁾/[SPI1_MOSI]⁽²⁾

Timer 2 - break input /

/[Timer 2 - trigger] /

X Port A4 LCD COM 0 / ADC1 input

2/Comparator 1 positive

input

PA4/TIM2_BKIN/

[TIM2_TRIG]⁽²⁾

9

5

I/O FT

X

HS

X

LCD_COM0⁽³⁾/ADC1_IN2

COMP1_INP

Timer 3 - break input /

[Timer 3 - trigger] /

X Port A5 LCD_COM 1 /

ADC1 input 1/Comparator 1

positive input

PA5/TIM3_BKIN/

[TIM3_TRIG]⁽²⁾

/

10

11

6

7

6

X

HS

X

LCD_COM1⁽³⁾/ADC1_IN1/

COMP1_INP

PA6/ADC1_TRIG/

ADC1 - trigger / LCD_COM2

X Port A6 / ADC1 input 0/Comparator

1 positive input

7 LCD_COM2⁽³⁾/ADC1_IN0/ I/O Ft

COMP1_INP

26/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

PA7/LCD_SEG0⁽³⁾

TIM5_CH1

/

LCD segment 0 / TIM5

channel 1

12

8

I/O FT

X

HS

X

X Port A7

X Port B0

PB0⁽⁴⁾/TIM2_CH1/

Timer 2 - channel 1 / LCD

segment 10 /

ADC1_IN18/Comparator 1

positive input

LCD_SEG10⁽³⁾

ADC1_IN18/

/

39 31 24

40 32 25

41 33 26

HS

COMP1_INP

PB1/TIM3_CH1/

Timer 3 - channel 1 / LCD

segment 11 /

ADC1_IN17/Comparator 1

positive input

LCD_SEG11⁽³⁾

ADC1_IN17/

/

I/O FT

X

X Port B1

COMP1_INP

PB2/ TIM2_CH2/

Timer 2 - channel 2 / LCD

segment 12 /

ADC1_IN16/Comparator 1

positive input

LCD_SEG12⁽³⁾

ADC1_IN16/

/

I/O FT

X

HS

X

X Port B2

X Port B3

X Port B4

COMP1_INP

Timer 2 - trigger / LCD

segment 13

/ADC1_IN15/Comparator 1

positive input

PB3/TIM2_TRIG/

42 34 27 LCD_SEG13⁽³⁾

/

ADC1_IN15/COMP1_INP

SPI1 master/slave select /

LCD segment 14 /

ADC1_IN14/Comparator 1

positive input

PB4⁽³⁾/SPI1_NSS/

43 35

-

LCD_SEG14⁽³⁾

/

ADC1_IN14/COMP1_INP

SPI1 master/slave select /

LCD segment 14 /

ADC1_IN14 /

DAC channel 2

output/Comparator 1

positive input

PB4⁽³⁾/SPI1_NSS/

LCD_SEG14⁽³⁾

/

-

28

I/O FT

X

HS

X

X Port B4

X Port B5

ADC1_IN14/DAC_OUT2/

COMP1_INP

PB5/SPI1_SCK/

SPI1 clock / LCD segment

15 /

ADC1_IN13/Comparator 1

positive input

LCD_SEG15⁽³⁾

ADC1_IN13

/

44 36

-

I/O FT

X

HS

X

COMP1_INP

[SPI1 clock] / LCD segment

15 / ADC1_IN13 / DAC

X Port B5 channel 2

output/Comparator 1

positive input

PB5/SPI1_SCK/

LCD_SEG15⁽³⁾

/

-

29

ADC1_IN13/DAC_OUT2/

COMP1_INP

Doc ID 17943 Rev 1

27/122

Pin description

STM8L15xx8, STM8L15xR6

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

SPI1 master out/slave in/

LCD segment 16 /

ADC1_IN12/Comparator 1

positive input

PB6/SPI1_MOSI/

45 37

-

LCD_SEG16⁽³⁾

/

I/O FT

X

HS

X

X Port B6

ADC1_IN12/COMP1_INP

SPI1 master out/

slave in / LCD segment 16 /

X Port B6 ADC1_IN12 / DAC channel

2 output/Comparator 1

PB6/SPI1_MOSI/

LCD_SEG16⁽³⁾

/

-

30

HS

ADC1_IN12/DAC_OUT2/

COMP1_INP

positive input

SPI1 master in- slave out/

LCD segment 17 /

ADC1_IN11/Comparator 1

PB7/SPI1_MISO/

46 38 31 LCD_SEG17⁽³⁾

/

X Port B7

ADC1_IN11/COMP1_INP

positive input

Port C0 I2C1 data

Port C1 I2C1 clock

USART1 receive /

65 53 37 PC0/I2C1_SDA

I/O FT

X

T⁽⁵⁾

T⁽⁴⁾

66 54 38 PC1/I2C1_SCL

PC2/USART1_RXI/

69 57 41 LCD_SEG22/ADC1_IN6/ I/O FT

COMP1_INP

LCD segment 22 /

ADC1_IN6/Comparator 1

positive input

X

HS

X

X Port C2

PC3/USART1_TXI/

USART1 transmit /

X Port C3 LCD segment 23 /

ADC1_IN5

-

42 LCD_SEG23⁽³⁾

ADC1_IN5

/

I/O FT

PC3/USART1_TX/

LCD_SEG23⁽³⁾

USART1 transmit /

LCD segment 23 /

X Port C3 ADC1_IN5 /

Comparator 2 negative input

/Comparator 1 input positive

/

ADC1_IN5/COMP_IN3M/

COMP2_INM/

70 58

-

X

HS

X

COMP1_INP

USART1 synchronous clock

/ I2C1_SMB / Configurable

clock output / LCD segment

24 / ADC1_IN4 /

Comparator 2 negative input

/ Comparator 1 positive input

PC4/USART1_CK]/

I2C1_SMB/CCO/

71 59 43 LCD_SEG24⁽³⁾

/

I/O FT

X

HS

X

X Port C4

ADC1_IN4/COMP2_INM/

COMP1_INP

PC5/OSC32_IN

LSE oscillator input / [SPI1

X Port C5 master/slave select] /

[USART1 transmit]

72 60 44 /[SPI1_NSS]⁽²⁾

/

[USART1_TX]⁽²⁾

28/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

PC6/OSC32_OUT/

LSE oscillator output / [SPI1

clock] / [USART1 receive]

73 61 45 [SPI1_SCK]⁽²⁾

/

I/O FT

X

HS

X

X Port C6

X Port C7

[USART1_RX]⁽²⁾

LCD segment 25

PC7/LCD_SEG25⁽³⁾

/

/ADC1_IN3/ Comparator

negative input / Comparator

1 positive input

74 62

-

ADC1_IN3/COMP2_INM I/O FT

HS

⁽⁶⁾/COMP1_INP

LCD segment 25

/ADC1_IN3/ USART3

synchronous clock/

PC7/LCD_SEG25⁽³⁾

ADC1_IN3/USART3_CK/

/

-

46

I/O FT

X

X Port C7

COMP2_INM/

Comparator 2 negative input

/ Comparator 1 positive input

COMP1_INP

Timer 3 - channel 2 /

[ADC1_Trigger] / LCD

X Port D0 segment 7 / ADC1_IN22 /

PD0/TIM3_CH2/

[ADC1_TRIG]⁽²⁾

/

29 25 20

30 26 21

HS

LCD_SEG7⁽³⁾

/

Comparator 2 positive input

2

ADC1_IN22/COMP2_INP

PD1/TIM3_TRIG/

Timer 3 - trigger /

LCD_COM3 / ADC1_IN21 /

comparator 1 positive input/

comparator 2 positive input

LCD_COM3⁽³⁾

/

I/O FT

X

HS

X

X Port D1

ADC1_IN21/COMP1_INP/

COMP2_INP

Timer 1 - channel 1 / LCD

PD2/TIM1_CH1

segment 8 /

X Port D2

31 27 22 /LCD_SEG8⁽³⁾

/

ADC1_IN20/Comparator 1

ADC1_IN20/COMP1_INP

positive input

PD3/ TIM1_TRIG/

Timer 1 - trigger / LCD

segment 9 /

ADC1_IN19/Comparator 1

positive input

LCD_SEG9⁽³⁾

ADC1_IN19/

COMP1_INP

/

32 28 23

X Port D3

PD4/TIM1_CH2

Timer 1 - channel 2 / LCD

segment 18 /

ADC1_IN10/Comparator 1

positive input

/LCD_SEG18⁽³⁾

ADC1_IN10/

COMP1_INP

/

57 45

-

X Port D4

Timer 1 - channel 2 / LCD

segment 18 /

X Port D4 ADC1_IN10/SPI2 master

in/slave out/Comparator 1

positive input

PD4/TIM1_CH2

/LCD_SEG18⁽³⁾

/

-

33

I/O FT

X

HS

X

ADC1_IN10/SPI2_MISO/

COMP1_INP

Doc ID 17943 Rev 1

29/122

Pin description

STM8L15xx8, STM8L15xR6

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

PD5/TIM1_CH3

Timer 1 - channel 3 / LCD

segment 19 /

ADC1_IN9/Comparator 1

positive input

/LCD_SEG19⁽³⁾

ADC1_IN9/

/

58 46

-

I/O FT

X

HS

X

X Port D5

COMP1_INP

Timer 1 - channel 3 / LCD

segment 19 / ADC1_IN9/

X Port D5 SPI2 master out/slave

in/Comparator 1 positive

input

PD5/TIM1_CH3

/LCD_SEG19⁽³⁾

/

-

34

HS

ADC1_IN9/SPI2_MOSI/

COMP1_INP

PD6/TIM1_BKIN

Timer 1 - break input / LCD

segment 20 / ADC1_IN8 /

RTC calibration/Comparator

1 positive input

/LCD_SEG20⁽³⁾

/

59 47

X Port D6

ADC1_IN8/RTC_CALIB/C

OMP1_INP

Timer 1 - break input / LCD

segment 20 / ADC1_IN8 /

X Port D6 RTC calibration/SPI2

clock/Comparator 1 positive

input

PD6/TIM1_BKIN

/LCD_SEG20⁽³⁾

/

-

35

ADC1_IN8/RTC_CALIB/

SPI2_SCK/COMP1_INP

Timer 1 - inverted channel 1/

LCD segment 21 /

X Port D7 ADC1_IN7 / RTC

alarm/Comparator 1 positive

input

PD7/TIM1_CH1N

/LCD_SEG21⁽³⁾

/

60 48

-

I/O FT

X

HS

X

ADC1_IN7/RTC_ALARM/

COMP1_INP

Timer 1 - inverted channel 1/

LCD segment 21 /

ADC1_IN7 / RTC alarm

/SPI2 master/slave

select/Comparator 1 positive

input

PD7/TIM1_CH1N

/LCD_SEG21⁽³⁾

/

-

36

X Port D7

ADC1_IN7/RTC_ALARM/

SPI2_NSS/COMP1_INP

PG4/LCD_SEG32/

SPI2_NSS

LCD segment 32 / SPI2

X Port G4

61 49

62 50

63 51

64 52

-

I/O FT

X

HS

X

master/slave select

PG5/LCD_SEG33/

SPI2_SCK

LCD segment 33 / SPI2

clock

X Port G5

PG6/LCD_SEG34/

SPI2_MOSI

LCD segment 34 / SPI2

X Port G6

master out- slave in

PG7/LCD_SEG35/

SPI2_MISO

LCD segment 35 / SPI2

X Port G7

master in- slave out

30/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

PE0/LCD_SEG1⁽³⁾

TIM5_CH2

/

LCD segment 1 /Timer 5

channel 2

23

-

I/O FT

X

HS

X

X Port E0

X Port E1

PE0/LCD_SEG1⁽³⁾

/

LCD segment 1 /Timer 5

channel 2 / RTC tamper 1

19 14

HS

TIM5_CH2/RTC_TAMP1

PE1/TIM1_CH2N

/LCD_SEG2⁽³⁾

Timer 1 - inverted channel 2

/ LCD segment 2

24

-

PE1/TIM1_CH2N

Timer 1 - inverted channel 2

X Port E1 / LCD segment 2 /

-

25

-

20 15 /LCD_SEG2⁽³⁾

RTC_TAMP2

/

I/O FT

X

HS

X

RTC tamper 2

PE2/TIM1_CH3N

/LCD_SEG3⁽³⁾

Timer 1 - inverted channel 3

/ LCD segment 3

-

X Port E2

PE2/TIM1_CH3N

Timer 1 - inverted channel 3

X Port E2 / LCD segment 3 /

21 16 /LCD_SEG3⁽³⁾

/

RTC_TAMP3

RTC tamper 3

26

-

PE3/LCD_SEG4⁽³⁾

I/O FT

X

HS

X

X Port E3 LCD segment 4

PE3/LCD_SEG4⁽³⁾

USART2_RX

/

LCD segment 4/

X Port E3

22 17

USART2 receive

PE4/LCD_SEG5⁽³⁾

DAC_TRIG1

/

LCD segment 5/

X Port E4

27

-

I/O FT

X

HS

X

DAC 1 trigger

LCD segment 5/

X Port E4 DAC 2 trigger/

USART2 transmit

PE4/LCD_SEG5⁽³⁾

/

23 18

DAC_TRIG2/USART2_TX

LCD segment 6 /

ADC1_IN23/Comparator 1

positive input/Comparator 2

positive input

PE5/LCD_SEG6⁽³⁾

ADC1_IN23/COMP1_INP/ I/O FT

COMP2_INP

/

28

-

X

HS

X

X Port E5

LCD segment 6 /

ADC1_IN23/ Comparator 1

X Port E5 positive input/ Comparator 2

positive input/USART2

PE5/LCD_SEG6⁽³⁾

/

ADC1_IN23/COMP1_INP/

COMP2_INP/

USART2_CK

-

24 19

I/O FT

synchronous clock

PE6/LCD_SEG26⁽³⁾

/

LCD segment 26 /PVD_IN

X Port E6 /TIM5 break input / USART3

transmit

-

47 PVD_IN/TIM5_BKIN/

USART3_TX

I/O FT

X

HS

X

PE6/LCD_SEG26⁽³⁾

PVD_IN/TIM5_BKIN

/

LCD segment 26 /PVD_IN

X Port E6

75 63

-

/TIM5 break input

Doc ID 17943 Rev 1

31/122

Pin description

STM8L15xx8, STM8L15xR6

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

PE7/LED_SEG27/

TIM5_TRIG

LCD segment 27/

TIM5 trigger

76 64

-

I/O FT

X

HS

X

X Port E7

PE7/LED_SEG27/

48 TIM5_TRIG/

USART3_RX

LCD segment 27/TIM5 trig-

ger/USART3 receive

-

HS

X Port E7

X Port I0

RTC tamper 1 output

[SPI2 master/slave select]

[TIM3 channel 3]

PI0/RTC_TAMP1/

[SPI2_NSS]/[TIM3_CH3]

77

-

I/O FT

X

PI1/RTC_TAMP2/

[SPI2_SCK]

RTC tamper 2 output

[SPI2 clock]

78

79

-

I/O FT

X

HS

X

X Port I1

X Port I2

PI2/RTC_TAMP3/

[SPI2_MOSI]

RTC tamper 3 output

[SPI2 master out- slave in]

-

TIM5 Channel 1

[SPI2 master out- slave in]

[TIM3 channel 2]

PI3/TIM5_CH1/

[SPI2_MOSI]/[TIM3_CH2]

80

-

I/O FT

I/O

X

HS

X

X Port I3

PF0/ADC1_IN24/

32

X Port F0 ADC1_IN24 / DAC 1 output

DAC_OUT1

PF0/ADC1_IN24/

DAC_OUT1

[USART3_TX]

ADC1_IN24 /

X Port F0 DAC 1 output/

[USART3 transmit]

-

39

-

I/O

PF0/ADC1_IN24/

DAC_OUT1/

[USART3_TX]/[SPI1_MIS

O]

ADC1_IN24 / DAC 1 output/

X Port F0 [USART3 transmit]

[SPI1 master in- slave out]

49

-

I/O

X

HS

X

PF1/ADC1_IN25/

DAC_OUT2/

[USART3_RX]/

[SPI1_MOSI]

ADC1_IN25/

DAC channel 2 output/

[USART3 receive]

[SPI1 master out- slave in]

50

-

I/O

X

HS

X

X Port F1

PF1/ADC1_IN25/

DAC_OUT2/

[USART3_RX]

ADC1_IN25/

X Port F1 DAC channel 2 output/

[USART3 receive]

40

PF2/ADC1_IN26/

ADC1_IN26

X Port F2 [SPI2 clock]

[USART3 clock]

51

52

-

I/O

X

HS

X

[SPI2_SCK]/

[USART3_SCK]

PF3/ADC1_IN27/

ADC1_IN26

X Port F3

[SPI1 master/slave select]

[SPI1_NSS]

32/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

Table 4.

High density and medium+ density STM8L15x pin description (continued)

number

Input

Output

Pin name

Default alternate function

53 41

54 42

55 43

56 44

-

PF4/LCD_COM4

PF5/LCD_COM5

PF6/LCD_COM6

PF7/LCD_COM7

I/O FT

S

X

HS

X

X Port F4 LCD COM4

-

HS

X Port F5 LCD COM5

X Port F6 LCD COM6

X Port F7 LCD COM7

LCD booster external capacitor

Digital power supply

22 18 13 VLCD⁽⁷⁾

15 11 10 V_DD1

S

14 10

-

V_SS1

I/O ground

16 12 11 V_DDA

S

Analog supply voltage

ADC1 and DAC1/2 positive voltage

reference

17 13 12 V_REF+/V_{REF+_DAC}

PG0/LCD SEG

LCD segment 28/

X Port G0 USART3 receive /

[Timer 2 - break input]

18 14

19 15

-

28⁽³⁾/USART3_RX/

I/O FT

X

HS

X

[TIM2_BKIN]

PG1/LCD SEG

29⁽³⁾/USART3_TX/

[TIM3_BKIN]

LCD segment 29/

X Port G1 USART3 transmit /

[Timer 3 -break input]

LCD segment 30/

X Port G2 USART 3 synchronous

clock

PG2/LCD_SEG 30⁽³⁾

USART3_CK

/

20 16

21 17

-

I/O FT

X

HS

X

PG3/LCD SEG 31 ⁽³⁾

[TIM3_TRIG]

LCD segment 31/

X Port G3

[Timer 3 - trigger]

33

34

PH4/USART2_RX

PH5/USART2_TX

I/O FT

X

HS

X

X Port H3

PH6/USART2_CK/

TIM5_CH1

35

36

-

I/O FT

S

X

HS

X

X Port H3

PH7/TIM5_CH2

I/O ground / Analog ground voltage /

ADC1 negative voltage reference

9 V_SS/V_SSA/V_REF-

Analog ground voltage /

ADC1 negative voltage reference

13

9

-

V_SSA/V_REF-

S

37 29

38 30

-

V_DD3

V_SS3

S

IOs supply voltage

IOs ground voltage

Doc ID 17943 Rev 1

33/122

Pin description

STM8L15xx8, STM8L15xR6

High density and medium+ density STM8L15x pin description (continued)

Input Output

Table 4.

number

Pin name

Default alternate function

[USART1 synchronous

clock]⁽²⁾/ SWIM input and

X Port A0 output /

PA0⁽⁸⁾/[USART1_CK]⁽²⁾

/

HS

5

1

I/O

X

(7)

SWIM/BEEP/IR_TIM ⁽⁹⁾

Beep output / Infrared Timer

output

68 56 40 V_SS2

67 55 39 V_DD2

IOs ground voltage

IOs supply voltage

IOs ground voltage

IOs supply voltage

48

47

-

V_SS4

V_DD4

1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be

configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1

pin as general purpose output in the STM8L15xx and STM8L16xx reference manual (RM0031).

2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a

duplication of the function).

3. Available on STM8L152xx devices only.

4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.

5. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to V_DDare not

implemented).

6. Not in 64-pin version.

7. Available on STM8L152xx devices only. On STM8L151xx devices it is reserved and must be tied to V_DD

8. The PA0 pin is in input pull-up during the reset phase and after reset release.

9. High Sink LED driver capability available on PA0.

.

34/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Pin description

System configuration options

As shown in Table 4: High density and medium+ density STM8L15x pin description, some

alternate functions can be remapped on different I/O ports by programming one of the two

remapping registers described in the “ Routing interface (RI) and system configuration

controller” section in the STM8L15xx and STM8L16xx reference manual (RM0031).

Doc ID 17943 Rev 1

35/122

Memory and register map

STM8L15xx8, STM8L15xR6

5

Memory and register map

5.1

Memory mapping

The memory map is shown in Figure 9.

Figure 9.

Memory map

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2ESET AND INTERRUPT VECTORS

2)

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1. Refer to Table 8 for an overview of hardware register mapping, to Table 7 for details on I/O port hardware

registers, and to Table 9 for information on CPU/SWIM/debug module controller registers.

36/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Memory and register map

Table 5.

Flash and RAM boundary addresses

Memory area

Size

Start address

0x00 0000

End address

0x00 07FF

0x00 0FFF

2 Kbytes

4 Kbytes

RAM

0x00 0000

32 Kbytes

64 Kbytes

0x00 8000

0x00 FFFF

0x01 7FFF

Flash program memory

5.2

Register map

Table 6.

Factory conversion regiserst

Reset

status

Address

Block

Register label

Register name

VREFINT_Factory_

CONV

Value of the internal reference voltage

measured during the factory phase

0x00 4910

-

0xXX

Value of the temperature sensor output

voltage measured during the factory

phase

TS_Factory_CONV_

V90

0x00 4911

-

0xXX

Table 7.

I/O port hardware register map

Reset

status

Address

Block

Register label

Register name

0x00 5000

0x00 5001

0x00 5002

0x00 5003

0x00 5004

0x00 5005

0x00 5006

0x00 5007

0x00 5008

0x00 5009

0x00 500A

0x00 500B

0x00 500C

0x00 500D

0x00 500E

PA_ODR

PA_IDR

Port A data output latch register

Port A input pin value register

Port A data direction register

Port A control register 1

0x00

0xXX

0x00

0x01

0x00

0xXX

0x00

0xXX

0x00

Port A

PA_DDR

PA_CR1

PA_CR2

PB_ODR

PB_IDR

PB_DDR

PB_CR1

PB_CR2

PC_ODR

PB_IDR

PC_DDR

PC_CR1

PC_CR2

Port A control register 2

Port B data output latch register

Port B input pin value register

Port B data direction register

Port B control register 1

Port B

Port B control register 2

Port C data output latch register

Port C input pin value register

Port C data direction register

Port C control register 1

Port C

Port C control register 2

Doc ID 17943 Rev 1

37/122

Memory and register map

Table 7. I/O port hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 500F

0x00 5010

0x00 5011

0x00 5012

0x00 5013

0x00 5014

0x00 5015

0x00 5016

0x00 5017

0x00 5018

0x00 5019

0x00 501A

0x00 501B

0x00 501C

0x00 501D

0x00 501E

0x00 501F

0x00 5020

0x00 5021

0x00 5022

0x00 5023

0x00 5024

0x00 5025

0x00 5026

0x00 5027

0x00 5028

0x00 5029

0x00 502A

0x00 502B

0x00 502C

PD_ODR

PD_IDR

PD_DDR

PD_CR1

PD_CR2

PE_ODR

PE_IDR

PE_DDR

PE_CR1

PE_CR2

PF_ODR

PF_IDR

PF_DDR

PF_CR1

PF_CR2

PG_ODR

PG_IDR

PG_DDR

PG_CR1

PG_CR2

PH_ODR

PH_IDR

PH_DDR

PH_CR1

PH_CR2

PI_ODR

PI_IDR

Port D data output latch register

Port D input pin value register

Port D data direction register

Port D control register 1

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

0xXX

0x00

Port D

Port D control register 2

Port E data output latch register

Port E input pin value register

Port E data direction register

Port E control register 1

Port E

Port F

Port G

Port H

Port I

Port E control register 2

Port F data output latch register

Port F input pin value register

Port F data direction register

Port F control register 1

Port F control register 2

Port F data output latch register

Port G input pin value register

Port G data direction register

Port G control register 1

Port G control register 2

Port H data output latch register

Port H input pin value register

Port H data direction register

Port H control register 1

Port H control register 2

Port I data output latch register

Port I input pin value register

Port I data direction register

Port I control register 1

PI_DDR

PI_CR1

PI_CR2

Port I control register 2

38/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Memory and register map

Reset

Table 8.

General hardware register map

Address

Block

Register label

Register name

status

0x00 502E

to

0x00 5049

Reserved area (44 bytes)

Flash control register 1

0x00 5050

0x00 5051

FLASH_CR1

FLASH_CR2

0x00

Flash control register 2

Flash program memory unprotection key

register

0x00 5052

0x00 5053

0x00 5054

FLASH _PUKR

FLASH _DUKR

FLASH _IAPSR

0x00

Flash

Data EEPROM unprotection key register

Flash in-application programming status

register

0x00 5055

to

Reserved area (27 bytes)

0x00 506F

Doc ID 17943 Rev 1

39/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

DMA1 global configuration & status

register

0x00 5070

0x00 5071

DMA1_GCSR

DMA1_GIR1

0xFC

0x00

DMA1 global interrupt register 1

Reserved area (3 bytes)

0x00 5072 to

0x00 5074

0x00 5075

0x00 5076

DMA1_C0CR

DMA1 channel 0 configuration register

DMA1 channel 0 status & priority register

0x00

DMA1_C0SPR

DMA1 number of data to transfer register

(channel 0)

0x00 5077

0x00 5078

DMA1_C0NDTR

DMA1_C0PARH

DMA1_C0PARL

0x00

0x52

0x00

DMA1 peripheral address high register

(channel 0)

DMA1 peripheral address low register

(channel 0)

0x00 5079

0x00 507A

0x00 507B

Reserved area (1 byte)

DMA1

DMA1 memory 0 address high register

(channel 0)

DMA1_C0M0ARH

DMA1_C0M0ARL

0x00

DMA1 memory 0 address low register

(channel 0)

0x00 507C

0x00 507D to

0x00 507E

Reserved area (2 bytes)

0x00 507F

0x00 5080

DMA1_C1CR

DMA1 channel 1 configuration register

DMA1 channel 1 status & priority register

0x00

DMA1_C1SPR

DMA1 number of data to transfer register

(channel 1)

0x00 5081

0x00 5082

0x00 5083

DMA1_C1NDTR

DMA1_C1PARH

DMA1_C1PARL

0x00

0x52

0x00

DMA1 peripheral address high register

(channel 1)

DMA1 peripheral address low register

(channel 1)

40/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5084

0x00 5085

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 1)

DMA1_C1M0ARH

DMA1_C1M0ARL

0x00

DMA1 memory 0 address low register

(channel 1)

0x00 5086

0x00 5087

0x00 5088

Reserved area (2 bytes)

0x00 5089

0x00 508A

DMA1_C2CR

DMA1 channel 2 configuration register

DMA1 channel 2 status & priority register

0x00

DMA1_C2SPR

DMA1 number of data to transfer register

(channel 2)

0x00 508B

0x00 508C

DMA1_C2NDTR

DMA1_C2PARH

DMA1_C2PARL

0x00

0x52

0x00

DMA1 peripheral address high register

(channel 2)

DMA1 peripheral address low register

(channel 2)

0x00 508D

0x00 508E

0x00 508F

Reserved area (1 byte)

DMA1 memory 0 address high register

(channel 2)

DMA1_C2M0ARH

DMA1_C2M0ARL

0x00

DMA1 memory 0 address low register

(channel 2)

DMA1

0x00 5090

0x00 5091

0x00 5092

Reserved area (2 bytes)

0x00 5093

0x00 5094

DMA1_C3CR

DMA1 channel 3 configuration register

DMA1 channel 3 status & priority register

0x00

DMA1_C3SPR

DMA1 number of data to transfer register

(channel 3)

0x00 5095

0x00 5096

0x00 5097

0x00 5098

0x00 5099

0x00 509A

DMA1_C3NDTR

0x00

0x40

0x00

DMA1_C3PARH_

C3M1ARH

DMA1 peripheral address high register

(channel 3)

DMA1_C3PARL_

C3M1ARL

DMA1 peripheral address low register

(channel 3)

DMA channel 3 memory 0 extended

address register

DMA_C3M0EAR

DMA1_C3M0ARH

DMA1_C3M0ARL

DMA1 memory 0 address high register

(channel 3)

DMA1 memory 0 address low register

(channel 3)

0x00 509B to

0x00 509C

Reserved area (3 bytes)

Doc ID 17943 Rev 1

41/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 509D

0x00 509E

0x00 509F

0x00 50A0

0x00 50A1

0x00 50A2

0x00 50A3

0x00 50A4

0x00 50A5

0x00 50A6

0x00 50A7

0x00 50A8

0x00 50A9

0x00 50AA

0x00 50AB

SYSCFG_RMPCR3

Remapping register 3

Remapping register 1

0x00

SYSCFG SYSCFG_RMPCR1

SYSCFG_RMPCR2

EXTI_CR1

Remapping register 2

External interrupt control register 1

External interrupt control register 2

External interrupt control register 3

External interrupt status register 1

External interrupt status register 2

External interrupt port select register 1

WFE control register 1

EXTI_CR2

EXTI_CR3

ITC - EXTI

EXTI_SR1

EXTI_SR2

EXTI_CONF1

WFE_CR1

WFE_CR2

WFE

WFE control register 2

WFE_CR3

WFE control register 3

WFE_CR4

WFE control register 4

EXTI_CR4

ITC - EXTI

External interrupt control register 4

External interrupt port select register 2

EXTI_CONF2

0x00 50A9

to

Reserved area (7 bytes)

0x00 50AF

0x00 50B0

0x00 50B1

0x00 50B2

0x00 50B3

RST_CR

Reset control register

Reset status register

0x00

0x01

0x00

RST

RST_SR

PWR_CSR1

PWR

Power control and status register 1

Power control and status register 2

PWR_CSR2

0x00 50B4

to

Reserved area (12 bytes)

0x00 50BF

42/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 50C0

0x00 50C1

0x00 50C2

0x00 50C3

0x00 50C4

0x00 50C5

0x00 50C6

0x00 50C7

0x00 50C8

0x00 50C9

0x00 50CA

0x00 50CB

0x00 50CC

0x00 50CD

0x00 50CE

0x00 50CF

0x00 50D0

CLK_CKDIVR

CLK_CRTCR

CLK_ICKCR

Clock master divider register

Clock RTC register

0x03

0x00⁽¹⁾

0x11

Internal clock control register

Peripheral clock gating register 1

Peripheral clock gating register 2

Configurable clock control register

External clock control register

System clock status register

System clock switch register

Clock switch control register

Clock security system register

Clock BEEP register

CLK_PCKENR1

CLK_PCKENR2

CLK_CCOR

0x00

CLK_ECKCR

CLK_SCSR

0x00

0x01

CLK

CLK_SWR

0x01

CLK_SWCR

0xX0

CLK_CSSR

0x00

CLK_CBEEPR

CLK_HSICALR

CLK_HSITRIMR

CLK_HSIUNLCKR

CLK_REGCSR

CLK_PCKENR3

0x00

HSI calibration register

0xXX

0x00

HSI clock calibration trimming register

HSI unlock register

0x00

Main regulator control status register

Peripheral clock gating register 3

0bxx11 100X

0x00

0x00 50D1

to

Reserved area (2 bytes)

0x00 50D2

0x00 50D3

0x00 50D4

WWDG_CR

WWDG_WR

WWDG control register

WWDR window register

0x7F

WWDG

IWDG

0x00 50D5

to

00 50DF

Reserved area (11 bytes)

0x00 50E0

0x00 50E1

0x00 50E2

IWDG_KR

IWDG_PR

IWDG_RLR

IWDG key register

IWDG prescaler register

IWDG reload register

0x01

0x00

0xFF

0x00 50E3

to

Reserved area (13 bytes)

0x00 50EF

0x00 50F0

BEEP_CSR1

BEEP_CSR2

BEEP control/status register 1

Reserved area (2 bytes)

0x00

0x1F

0x00 50F1

0x00 50F2

BEEP

0x00 50F3

BEEP control/status register 2

Reserved area (76 bytes)

0x00 50F4

to0x00 513F

Doc ID 17943 Rev 1

43/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 5140

0x00 5141

0x00 5142

0x00 5143

0x00 5144

0x00 5145

0x00 5146

0x00 5147

0x00 5148

0x00 5149

0x00 514A

0x00 514B

0x00 514C

0x00 514D

RTC_TR1

RTC_TR2

RTC_TR3

Time register 1

Time register 2

0x00

Time register 3

Reserved area (1 byte)

Date register 1

RTC_DR1

RTC_DR2

RTC_DR3

0x01

0x21

0x00

Date register 2

Date register 3

Reserved area (1 byte)

Control register 1

RTC_CR1

RTC_CR2

RTC_CR3

0x00⁽¹⁾

Control register 2

Control register 3

Reserved area (1 byte)

Initialization and status register 1

Initialization and Status register 2

RTC_ISR1

RTC_ISR2

0x01

0x00

0x00 514E

0x00 514F

Reserved area (2 bytes)

0x00 5150

0x00 5151

0x00 5152

0x00 5153

0x00 5154

0x00 5155

0x00 5156

0x00 5157

0x00 5158

0x00 5159

0x00 5158

0x00 5159

0x00 515A

0x00 515B

0x00 515C

0x00 515D

0x00 515E

0x00 515F

RTC_SPRERH

RTC_SPRERL

RTC_APRER

Synchronous prescaler register high

Synchronous prescaler register low

Asynchronous prescaler register

Reserved area (1 byte)

Wakeup timer register high

Wakeup timer register low

Reserved area (1 byte)

Subsecond register low

Subsecond register high

Write protection register

Subsecond register high

Write protection register

Shift register high

0x00⁽¹⁾

0xFF⁽¹⁾

0x7F⁽¹⁾

RTC

RTC_WUTRH

RTC_WUTRL

0xFF⁽¹⁾

RTC_SSRL

RTC_SSRH

0x00

RTC_WPR

0x00

RTC_SSRH

0x00

RTC_WPR

0x00

RTC_SHIFTRH

RTC_SHIFTRL

RTC_ALRMAR1

RTC_ALRMAR2

RTC_ALRMAR3

RTC_ALRMAR4

0x00

Shift register low

0x00

Alarm A register 1

0x00⁽¹⁾

Alarm A register 2

Alarm A register 3

Alarm A register 4

44/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5160 to

0x00 5163

Reserved area (4 bytes)

0x00 5164

0x00 5165

RTC_ALRMASSRH

RTC_ALRMASSRL

Alarm A subsecond register high

Alarm A subsecond register low

0x00⁽¹⁾

RTC

RTC_ALRMASSMS

KR

0x00 5166

Alarm A masking register

Reserved area (3 bytes)

0x00⁽¹⁾

0x00 5167 to

0x00 5169

0x00 516A

0x00 516B

0x00 516C

0x00 516D

RTC_CALRH

RTC_CALRL

RTC_TCR1

RTC_TCR2

Calibration register high

Calibration register low

Tamper control register 1

Tamper control register 2

0x00⁽¹⁾

RTC

0x00 516E to

0x00 518A

Reserved area

0x00 5190

CSSLSE_CSR

CSS on LSE control and status register

Reserved area

0x00⁽¹⁾

0x00 519A to

0x00 51FF

0x00 5200

0x00 5201

0x00 5202

0x00 5203

0x00 5204

0x00 5205

0x00 5206

0x00 5207

SPI1_CR1

SPI1_CR2

SPI1 control register 1

SPI1 control register 2

SPI1 interrupt control register

SPI1 status register

0x00

0x02

0x00

0x07

0x00

SPI1_ICR

SPI1_SR

SPI1

SPI1_DR

SPI1 data register

SPI1_CRCPR

SPI1_RXCRCR

SPI1_TXCRCR

SPI1 CRC polynomial register

SPI1 Rx CRC register

SPI1 Tx CRC register

0x00 5208

to

Reserved area (8 bytes)

0x00 520F

Doc ID 17943 Rev 1

45/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 5210

0x00 5211

0x00 5212

0x00 5213

0x00 5214

0x00 5215

0x00 5216

0x00 5217

0x00 5218

0x00 5219

0x00 521A

0x00 521B

0x00 521C

0x00 521D

0x00 521E

I2C1_CR1

I2C1_CR2

I2C1 control register 1

I2C1 control register 2

0x00

0x0X

0x00

0x02

0x00

I2C1_FREQR

I2C1_OARL

I2C1_OARH

I2C1_DR

I2C1 frequency register

I2C1 own address register low

I2C1 own address register high

I2C1 own address register for dual mode

I2C1 data register

I2C1

I2C1_SR1

I2C1 status register 1

I2C1_SR2

I2C1 status register 2

I2C1_SR3

I2C1 status register 3

I2C1_ITR

I2C1 interrupt control register

I2C1 clock control register low

I2C1 clock control register high

I2C1 TRISE register

I2C1_CCRL

I2C1_CCRH

I2C1_TRISER

I2C1_PECR

I2C1 packet error checking register

0x00 521F

to

Reserved area (17 bytes)

0x00 522F

0x00 5230

0x00 5231

0x00 5232

0x00 5233

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238

0x00 5239

0x00 523A

USART1_SR

USART1_DR

USART1 status register

USART1 data register

0xC0

0xXX

0x00

USART1_BRR1

USART1_BRR2

USART1_CR1

USART1_CR2

USART1_CR3

USART1_CR4

USART1_CR5

USART1_GTR

USART1_PSCR

USART1 baud rate register 1

USART1 baud rate register 2

USART1 control register 1

USART1 control register 2

USART1 control register 3

USART1 control register 4

USART1 control register 5

USART1 guard time register

USART1 prescaler register

USART1

0x00 523B

to

Reserved area (21 bytes)

0x00 524F

46/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5250

0x00 5251

0x00 5252

0x00 5253

0x00 5254

0x00 5255

0x00 5256

0x00 5257

0x00 5258

0x00 5259

0x00 525A

0x00 525B

0x00 525C

0x00 525D

0x00 525E

0x00 525F

0x00 5260

0x00 5261

0x00 5262

0x00 5263

0x00 5264

0x00 5265

0x00 5266

TIM2_CR1

TIM2_CR2

TIM2 control register 1

TIM2 control register 2

0x00

0xFF

0x00

TIM2_SMCR

TIM2_ETR

TIM2 Slave mode control register

TIM2 external trigger register

TIM2 DMA1 request enable register

TIM2 interrupt enable register

TIM2 status register 1

TIM2_DER

TIM2_IER

TIM2_SR1

TIM2_SR2

TIM2 status register 2

TIM2_EGR

TIM2 event generation register

TIM2 capture/compare mode register 1

TIM2 capture/compare mode register 2

TIM2 capture/compare enable register 1

TIM2 counter high

TIM2_CCMR1

TIM2_CCMR2

TIM2_CCER1

TIM2_CNTRH

TIM2_CNTRL

TIM2_PSCR

TIM2_ARRH

TIM2_ARRL

TIM2_CCR1H

TIM2_CCR1L

TIM2_CCR2H

TIM2_CCR2L

TIM2_BKR

TIM2

TIM2 counter low

TIM2 prescaler register

TIM2 auto-reload register high

TIM2 auto-reload register low

TIM2 capture/compare register 1 high

TIM2 capture/compare register 1 low

TIM2 capture/compare register 2 high

TIM2 capture/compare register 2 low

TIM2 break register

TIM2_OISR

TIM2 output idle state register

0x00 5267 to

0x00 527F

Reserved area (25 bytes)

Doc ID 17943 Rev 1

47/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 5280

0x00 5281

0x00 5282

0x00 5283

0x00 5284

0x00 5285

0x00 5286

0x00 5287

0x00 5288

0x00 5289

0x00 528A

0x00 528B

0x00 528C

0x00 528D

0x00 528E

0x00 528F

0x00 5290

0x00 5291

0x00 5292

0x00 5293

0x00 5294

0x00 5295

0x00 5296

TIM3_CR1

TIM3_CR2

TIM3 control register 1

TIM3 control register 2

0x00

0xFF

0x00

TIM3_SMCR

TIM3_ETR

TIM3 Slave mode control register

TIM3 external trigger register

TIM3 DMA1 request enable register

TIM3 interrupt enable register

TIM3 status register 1

TIM3_DER

TIM3_IER

TIM3_SR1

TIM3_SR2

TIM3 status register 2

TIM3_EGR

TIM3 event generation register

TIM3 Capture/Compare mode register 1

TIM3 Capture/Compare mode register 2

TIM3 Capture/Compare enable register 1

TIM3 counter high

TIM3_CCMR1

TIM3_CCMR2

TIM3_CCER1

TIM3_CNTRH

TIM3_CNTRL

TIM3_PSCR

TIM3_ARRH

TIM3_ARRL

TIM3_CCR1H

TIM3_CCR1L

TIM3_CCR2H

TIM3_CCR2L

TIM3_BKR

TIM3

TIM3 counter low

TIM3 prescaler register

TIM3 Auto-reload register high

TIM3 Auto-reload register low

TIM3 Capture/Compare register 1 high

TIM3 Capture/Compare register 1 low

TIM3 Capture/Compare register 2 high

TIM3 Capture/Compare register 2 low

TIM3 break register

TIM3_OISR

TIM3 output idle state register

0x00 5297 to

0x00 52AF

Reserved area (25 bytes)

48/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 52B0

0x00 52B1

0x00 52B2

0x00 52B3

0x00 52B4

0x00 52B5

0x00 52B6

0x00 52B7

0x00 52B8

0x00 52B9

0x00 52BA

0x00 52BB

0x00 52BC

0x00 52BD

0x00 52BE

0x00 52BF

0x00 52C0

0x00 52C1

0x00 52C2

0x00 52C3

0x00 52C4

0x00 52C5

0x00 52C6

0x00 52C7

0x00 52C8

0x00 52C9

0x00 52CA

0x00 52CB

0x00 52CC

0x00 52CD

0x00 52CE

0x00 52CF

0x00 52D0

0x00 52D1

TIM1_CR1

TIM1_CR2

TIM1 control register 1

TIM1 control register 2

0x00

0xFF

0x00

TIM1_SMCR

TIM1_ETR

TIM1 Slave mode control register

TIM1 external trigger register

TIM1_DER

TIM1 DMA1 request enable register

TIM1 Interrupt enable register

TIM1 status register 1

TIM1_IER

TIM1_SR1

TIM1_SR2

TIM1 status register 2

TIM1_EGR

TIM1 event generation register

TIM1 Capture/Compare mode register 1

TIM1 Capture/Compare mode register 2

TIM1 Capture/Compare mode register 3

TIM1 Capture/Compare mode register 4

TIM1 Capture/Compare enable register 1

TIM1 Capture/Compare enable register 2

TIM1 counter high

TIM1_CCMR1

TIM1_CCMR2

TIM1_CCMR3

TIM1_CCMR4

TIM1_CCER1

TIM1_CCER2

TIM1_CNTRH

TIM1_CNTRL

TIM1_PSCRH

TIM1_PSCRL

TIM1_ARRH

TIM1_ARRL

TIM1_RCR

TIM1 counter low

TIM1

TIM1 prescaler register high

TIM1 prescaler register low

TIM1 Auto-reload register high

TIM1 Auto-reload register low

TIM1 Repetition counter register

TIM1 Capture/Compare register 1 high

TIM1 Capture/Compare register 1 low

TIM1 Capture/Compare register 2 high

TIM1 Capture/Compare register 2 low

TIM1 Capture/Compare register 3 high

TIM1 Capture/Compare register 3 low

TIM1 Capture/Compare register 4 high

TIM1 Capture/Compare register 4 low

TIM1 break register

TIM1_CCR1H

TIM1_CCR1L

TIM1_CCR2H

TIM1_CCR2L

TIM1_CCR3H

TIM1_CCR3L

TIM1_CCR4H

TIM1_CCR4L

TIM1_BKR

TIM1_DTR

TIM1 dead-time register

TIM1_OISR

TIM1_DCR1

TIM1 output idle state register

DMA1 control register 1

Doc ID 17943 Rev 1

49/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 52D2

0x00 52D3

TIM1_DCR2

TIM1 DMA1 control register 2

0x00

TIM1_DMA1R

TIM1 DMA1 address for burst mode

0x00 52D4

to

Reserved area (12 bytes)

0x00 52DF

0x00 52E0

0x00 52E1

0x00 52E2

0x00 52E3

0x00 52E4

0x00 52E5

0x00 52E6

0x00 52E7

0x00 52E8

0x00 52E9

TIM4_CR1

TIM4_CR2

TIM4_SMCR

TIM4_DER

TIM4_IER

TIM4 control register 1

TIM4 control register 2

0x00

TIM4 Slave mode control register

TIM4 DMA1 request enable register

TIM4 Interrupt enable register

TIM4 status register 1

TIM4

TIM4_SR1

TIM4_EGR

TIM4_CNTR

TIM4_PSCR

TIM4_ARR

TIM4 Event generation register

TIM4 counter

TIM4 prescaler register

TIM4 Auto-reload register

0x00 52EA

to

0x00 52FE

Reserved area (21 bytes)

Infrared control register

0x00 52FF

IRTIM

IR_CR

0x00

50/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307

0x00 5308

0x00 5309

0x00 530A

0x00 530B

0x00 530C

0x00 530D

0x00 530E

0x00 530F

0x00 5310

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315

0x00 5316

TIM5_CR1

TIM5_CR2

TIM5 control register 1

TIM5 control register 2

0x00

0xFF

0x00

TIM5_SMCR

TIM5_ETR

TIM5 Slave mode control register

TIM5 external trigger register

TIM5 DMA1 request enable register

TIM5 interrupt enable register

TIM5 status register 1

TIM5_DER

TIM5_IER

TIM5_SR1

TIM5_SR2

TIM5 status register 2

TIM5_EGR

TIM5 event generation register

TIM5 Capture/Compare mode register 1

TIM5 Capture/Compare mode register 2

TIM5 Capture/Compare enable register 1

TIM5 counter high

TIM5_CCMR1

TIM5_CCMR2

TIM5_CCER1

TIM5_CNTRH

TIM5_CNTRL

TIM5_PSCR

TIM5_ARRH

TIM5_ARRL

TIM5_CCR1H

TIM5_CCR1L

TIM5_CCR2H

TIM5_CCR2L

TIM5_BKR

TIM5

TIM5 counter low

TIM5 prescaler register

TIM5 Auto-reload register high

TIM5 Auto-reload register low

TIM5 Capture/Compare register 1 high

TIM5 Capture/Compare register 1 low

TIM5 Capture/Compare register 2 high

TIM5 Capture/Compare register 2 low

TIM5 break register

TIM5_OISR

TIM5 output idle state register

0x00 5317

to

Reserved area

0x00 533F

Doc ID 17943 Rev 1

51/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 5340

0x00 5341

0x00 5342

0x00 5343

0x00 5344

0x00 5345

0x00 5346

0x00 5347

0x00 5348

0x00 5349

0x00 534A

0x00 534B

0x00 534C

0x00 534D

0x00 534E

0x00 534F

0x00 5350

0x00 5351

ADC1_CR1

ADC1_CR2

ADC1 configuration register 1

ADC1 configuration register 2

ADC1 configuration register 3

ADC1 status register

0x00

0x1F

0x00

0x0F

0xFF

0x00

ADC1_CR3

ADC1_SR

ADC1_DRH

ADC1_DRL

ADC1 data register high

ADC1 data register low

ADC1_HTRH

ADC1_HTRL

ADC1_LTRH

ADC1_LTRL

ADC1_SQR1

ADC1_SQR2

ADC1_SQR3

ADC1_SQR4

ADC1_TRIGR1

ADC1_TRIGR2

ADC1_TRIGR3

ADC1_TRIGR4

ADC1 high threshold register high

ADC1 high threshold register low

ADC1 low threshold register high

ADC1 low threshold register low

ADC1 channel sequence 1 register

ADC1 channel sequence 2 register

ADC1 channel sequence 3 register

ADC1 channel sequence 4 register

ADC1 trigger disable 1

ADC1

ADC1 trigger disable 2

ADC1 trigger disable 3

ADC1 trigger disable 4

0x00 5352 to

0x00 537F

Reserved area (46 bytes)

0x00 5380

0x00 5381

0x00 5382

0x00 5383

0x00 5384

0x00 5385

DAC_CH1CR1

DAC_CH1CR2

DAC_CH2CR1

DAC_CH2CR2

DAC_SWTRIG

DAC_SR

DAC channel 1 control register 1

DAC channel 1 control register 2

DAC channel 2 control register 1

DAC channel 2 control register 2

DAC software trigger register

DAC status register

0x00

DAC

0x00 5386 to

0x00 5387

Reserved area (2 bytes)

DAC channel 1 right aligned data holding

register high

0x00 5388

0x00 5389

DAC_CH1RDHRH

DAC_CH1RDHRL

0x00

DAC

DAC channel 1 right aligned data holding

register low

0x00 538A to

0x00 538B

Reserved area (2 bytes)

DAC channel 1 left aligned data holding

register high

0x00 538C

DAC_CH1LDHRH

0x00

52/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

DAC channel 1 left aligned data holding

register low

0x00 538D

DAC

DAC_CH1LDHRL

0x00

0x00 538E

to 0x00 538F

Reserved area (2 bytes)

DAC channel 1 8-bit data holding register

Reserved area (3 bytes)

0x00 5390

DAC

DAC_CH1DHR8

0x00

0x00 5391 to

0x00 5393

DAC channel 2 right aligned data holding

register high

0x00 5394

0x00 5395

DAC_CH2RDHRH

DAC_CH2RDHRL

0x00

DAC channel 2 right aligned data holding

register low

0x00 5396 to

0x00 5397

Reserved area (2 bytes)

DAC channel 2 left aligned data holding

register high

0x00 5398

0x00 5399

DAC_CH2LDHRH

DAC_CH2LDHRL

0x00

DAC

DAC channel 2 left aligned data holding

register low

0x00 539A

to 0x00 539B

Reserved area (2 bytes)

DAC channel 2 8-bit data holding register

Reserved area (3 bytes)

0x00 539C

DAC_CH2DHR8

0x00

0x00 539D

to 0x00 539F

Doc ID 17943 Rev 1

53/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

DAC channel 1 right aligned data holding

register high

0x00 53A0

0x00 53A1

DAC_DCH1RDHRH

DAC_DCH1RDHRL

0x00

DAC channel 1 right aligned data holding

register low

0x00

0x00 53A2

to 0x00 53AB

Reserved area (3 bytes)

0x00 53AC

0x00 53AD

DAC_DORH

DAC_DORL

DAC data output register high

DAC data output register low

0x00

DAC channel 2 right aligned data holding

register high

0x00 53A2

0x00 53A3

0x00 53A4

0x00 53A5

0x00 53A6

0x00 53A7

0x00 53A8

0x00 53A9

DAC_DCH2RDHRH

DAC_DCH2RDHRL

DAC_DCH1LDHRH

DAC_DCH1LDHRL

DAC_DCH2LDHRH

DAC_DCH2LDHRL

DAC_DCH1DHR8

DAC_DCH2DHR8

0x00

DAC channel 2 right aligned data holding

register low

DAC

DAC channel 1left aligned data holding

register high

DAC channel 1left aligned data holding

register low

DAC channel 2 left aligned data holding

register high

DAC channel 2 left aligned data holding

register low

DAC channel 1 8-bit mode data holding

register

DAC channel 2 8-bit mode data holding

register

0x00 53AA to

0x00 53AB

Reserved area (2 bytes)

DAC_CH1DORH

Reset value

0x00 53AC

0x00 53AD

DAC channel 1 data output register high

DAC channel 1 data output register low

Reserved area (2 bytes)

0x00

DAC

DAC_CH1DORL

Reset value

0x00 53AE

to 0x00 53AF

DAC_CH2DORH

Reset value

0x00 53B0

0x00 53B1

DAC channel 2 data output register high

DAC channel 2 data output register low

Reserved area

0x00

DAC_CH2DORL

Reset value

0x00 53B2

to 0x00 53BF

54/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 53C0

0x00 53C1

0x00 53C2

0x00 53C3

0x00 53C4

0x00 53C5

0x00 53C6

0x00 53C7

SPI2_CR1

SPI2_CR2

SPI2 control register 1

SPI2 control register 2

SPI2 interrupt control register

SPI2 status register

0x00

0x02

0x00

0x07

0x00

SPI2_ICR

SPI2_SR

SPI2

SPI2_DR

SPI2 data register

SPI2_CRCPR

SPI2_RXCRCR

SPI2_TXCRCR

SPI2 CRC polynomial register

SPI2 Rx CRC register

SPI2 Tx CRC register

0x00 53C8 to

0x00 53DF

Reserved area

0x00 53E0

0x00 53E1

0x00 53E2

0x00 53E3

0x00 53E4

0x00 53E5

0x00 53E6

0x00 53E7

0x00 53E8

0x00 53E9

0x00 53EA

USART2_SR

USART2_DR

USART2 status register

USART2 data register

0xC0

0xXX

0x00

USART2_BRR1

USART2_BRR2

USART2_CR1

USART2_CR2

USART2_CR3

USART2_CR4

USART2_CR5

USART2_GTR

USART2_PSCR

USART2 baud rate register 1

USART2 baud rate register 2

USART2 control register 1

USART2 control register 2

USART2 control register 3

USART2 control register 4

USART2 control register 5

USART2 guard time register

USART2 prescaler register

USART2

0x00 53EB to

0x00 53EF

Reserved area

0x00 53F0

0x00 53F1

0x00 53F2

0x00 53F3

0x00 53F4

0x00 53F5

0x00 53F6

0x00 53F7

0x00 53F8

0x00 53F9

0x00 53FA

USART3_SR

USART3_DR

USART3 status register

USART3 data register

0xC0

0xXX

0x00

USART3_BRR1

USART3_BRR2

USART3_CR1

USART3_CR2

USART3_CR3

USART3_CR4

USART3_CR5

USART3_GTR

USART3_PSCR

USART3 baud rate register 1

USART3 baud rate register 2

USART3 control register 1

USART3 control register 2

USART3 control register 3

USART3 control register 4

USART3 control register 5

USART3 guard time register

USART3 prescaler register

USART3

Doc ID 17943 Rev 1

55/122

Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 53FB to

0x00 53FF

Reserved area

LCD control register 1

0x00 5400

0x00 5401

0x00 5402

0x00 5403

0x00 5404

0x00 5405

0x00 5406

0x00 5407

0x00 5408

0x00 5409

LCD_CR1

LCD_CR2

LCD_CR3

LCD_FRQ

LCD_PM0

LCD_PM1

LCD_PM2

LCD_PM3

LCD_PM4

LCD_PM5

0x00

LCD control register 2

LCD control register 3

LCD frequency selection register

LCD Port mask register 0

LCD Port mask register 1

LCD Port mask register 2

LCD Port mask register 3

LCD Port mask register 4

LCD Port mask register 5

LCD

56/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 8. General hardware register map (continued)

Address

Memory and register map

Reset

Block

Register label

Register name

status

0x00 540A to

0x00 540B

Reserved area (2 bytes)

0x00 540C

0x00 540D

0x00 540E

0x00 540F

0x00 5410

0x00 5411

0x00 5412

0x00 5413

0x00 5414

0x00 5415

0x00 5416

0x00 5417

0x00 5418

0x00 5419

0x00 541A

0x00 541B

0x00 541C

0x00 541D

0x00 541E

0x00 541F

0x00 5420

0x00 5421

LCD_RAM0

LCD_RAM1

LCD_RAM2

LCD_RAM3

LCD_RAM4

LCD_RAM5

LCD_RAM6

LCD_RAM7

LCD_RAM8

LCD_RAM9

LCD_RAM10

LCD_RAM11

LCD_RAM12

LCD_RAM13

LCD_RAM14

LCD_RAM15

LCD_RAM16

LCD_RAM17

LCD_RAM18

LCD_RAM19

LCD_RAM20

LCD_RAM21

LCD display memory 0

LCD display memory 1

LCD display memory 2

LCD display memory 3

LCD display memory 4

LCD display memory 5

LCD display memory 6

LCD display memory 7

LCD display memory 8

LCD display memory 9

LCD display memory 10

LCD display memory 11

LCD display memory 12

LCD display memory 13

LCD display memory 12

LCD display memory 13

LCD display memory 11

LCD display memory 12

LCD display memory 13

LCD display memory 12

LCD display memory 13

0x00

LCD

0x00 5422 to

0x00 542F

Reserved area

Doc ID 17943 Rev 1

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Memory and register map

Table 8. General hardware register map (continued)

Address

STM8L15xx8, STM8L15xR6

Reset

Block

Register label

Register name

status

0x00 5430

0x00 5431

0x00 5432

0x00 5433

0x00 5434

0x00 5435

0x00 5436

0x00 5437

0x00 5438

0x00 5439

0x00 543A

0x00 543B

0x00 543C

0x00 543D

0x00 543E

0x00 543F

0x00 5440

0x00 5441

0x00 5442

0x00 5443

0x00 5444

Reserved area (1 byte)

0x00

0xXX

0x00

0x3F

0x00

RI_ICR1

RI_ICR2

Timer input capture routing register 1

Timer input capture routing register 2

I/O input register 1

RI_IOIR1

RI_IOIR2

I/O input register 2

RI_IOIR3

I/O input register 3

RI_IOCMR1

RI_IOCMR2

RI_IOCMR3

RI_IOSR1

I/O control mode register 1

I/O control mode register 2

I/O control mode register 3

I/O switch register 1

RI

RI_IOSR2

I/O switch register 2

RI_IOSR3

I/O switch register 3

RI_IOGCR

RI_ASCR1

RI_ASCR2

RI_RCR

I/O group control register

Analog switch register 1

Analog switch register 2

Resistor control register 1

Comparator control and status register 1

Comparator control and status register 2

Comparator control and status register 3

Comparator control and status register 4

Comparator control and status register 5

COMP_CSR1

COMP_CSR2

COMP_CSR3

COMP_CSR4

COMP_CSR5

COMP1/

COMP2

1. These registers are not impacted by a system reset. They are reset at power-on.

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 9. CPU/SWIM/debug module/interrupt controller registers

Address

Memory and register map

Reset

status

Block

Register label

Register name

0x00 7F00

0x00 7F01

0x00 7F02

0x00 7F03

0x00 7F04

0x00 7F05

0x00 7F06

0x00 7F07

0x00 7F08

0x00 7F09

0x00 7F0A

A

Accumulator

0x00

PCE

PCH

PCL

XH

Program counter extended

Program counter high

Program counter low

X index register high

X index register low

Y index register high

Y index register low

Stack pointer high

0x00

0x03

0xFF

0x28

CPU⁽¹⁾

XL

YH

YL

SPH

SPL

CCR

Stack pointer low

Condition code register

0x00 7F0B to

0x00 7F5F

Reserved area (85 bytes)

CPU

0x00 7F60

0x00 7F70

0x00 7F71

0x00 7F72

0x00 7F73

0x00 7F74

0x00 7F75

0x00 7F76

0x00 7F77

CFG_GCR

ITC_SPR1

ITC_SPR2

ITC_SPR3

ITC_SPR4

ITC_SPR5

ITC_SPR6

ITC_SPR7

ITC_SPR8

Global configuration register

0x00

0xFF

Interrupt Software priority register 1

Interrupt Software priority register 2

Interrupt Software priority register 3

Interrupt Software priority register 4

Interrupt Software priority register 5

Interrupt Software priority register 6

Interrupt Software priority register 7

Interrupt Software priority register 8

ITC-SPR

0x00 7F78

to

0x00 7F79

Reserved area (2 bytes)

SWIM control status register

Reserved area (15 bytes)

0x00 7F80

SWIM

SWIM_CSR

0x00

0x00 7F81

to

0x00 7F8F

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Memory and register map

Table 9.

Address

STM8L15xx8, STM8L15xR6

CPU/SWIM/debug module/interrupt controller registers (continued)

Reset

status

Block

Register label

Register name

0x00 7F90

0x00 7F91

0x00 7F92

0x00 7F93

0x00 7F94

0x00 7F95

0x00 7F96

0x00 7F97

0x00 7F98

0x00 7F99

0x00 7F9A

DM_BK1RE

DM_BK1RH

DM_BK1RL

DM_BK2RE

DM_BK2RH

DM_BK2RL

DM_CR1

DM breakpoint 1 register extended byte

DM breakpoint 1 register high byte

DM breakpoint 1 register low byte

DM breakpoint 2 register extended byte

DM breakpoint 2 register high byte

DM breakpoint 2 register low byte

DM Debug module control register 1

DM Debug module control register 2

DM Debug module control/status register 1

DM Debug module control/status register 2

DM enable function register

0xFF

0x00

0x10

0x00

0xFF

DM

DM_CR2

DM_CSR1

DM_CSR2

DM_ENFCTR

0x00 7F9B

to

Reserved area (5 bytes)

0x00 7F9F

1. Accessible by debug module only

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STM8L15xx8, STM8L15xR6

Interrupt vector mapping

6

Interrupt vector mapping

Table 10. Interrupt mapping

Wakeup

from

Active-halt

mode

Wakeup

from Wait from Wait

(WFI

mode)

Wakeup

from Halt

mode

Vector

IRQ

No.

Source

block

Description

(WFE

address

mode)⁽¹⁾

RESET

TRAP

TLI⁽²⁾

Reset

Yes

-

Yes

-

0x00 8000

0x00 8004

0x00 8008

0x00 800C

0x00 8010

0x00 8014

Software interrupt

-

0

1

2

3

External Top level Interrupt

EOP/WR_PG_DIS

-

FLASH

Yes

Yes⁽³⁾

DMA1 0/1 DMA1 channels 0/1

DMA1 2/3 DMA1 channels 2/3

RTC/LSE_ RTC alarm interrupt/LSE

4

5

Yes

0x00 8018

0x00 801C

CSS

CSS interrupt

EXTI

PortE/F interrupt/PVD

Yes⁽³⁾

E/F/PVD⁽⁴⁾interrupt

6

EXTIB/G External interrupt port B/G

EXTID/H External interrupt port D/H

Yes

-

Yes

-

Yes

Yes⁽³⁾

Yes

0x00 8020

0x00 8024

0x00 8028

0x00 802C

0x00 8030

0x00 8034

0x00 8038

0x00 803C

0x00 8040

0x00 8044

0x00 8048

7

8

EXTI0

EXTI1

EXTI2

EXTI3

EXTI4

EXTI5

EXTI6

EXTI7

LCD

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

LCD interrupt

9

10

11

12

13

14

15

16

CLK/

TIM1/

DAC

System clock switch/CSS

interrupt/TIM1 break/DAC

17

18

-

Yes

0x00 804C

0x00 8050

COMP1/

COMP2

ADC1

Comparator 1 and 2

interrupt/ADC1

Yes

Yes⁽³⁾

TIM2 update

/overflow/trigger/break/

TIM2/

USART2 transmission

19

-

Yes

Yes⁽³⁾

0x00 8054

USART2 complete/transmit data

register empty

interrupt

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Interrupt vector mapping

STM8L15xx8, STM8L15xR6

Table 10. Interrupt mapping (continued)

Wakeup

from

Active-halt

mode

Wakeup

from Wait from Wait

(WFI

mode)

Wakeup

from Halt

mode

Vector

IRQ

No.

Source

block

Description

(WFE

address

mode)⁽¹⁾

TIM2/

USART2 2 interrupt

Capture/Compare/USART

20

21

-

Yes

Yes⁽³⁾

0x00 8058

0x00 805C

TIM3 Update

/Overflow/Trigger/Break/

USART3 transmission

TIM3/

-

USART3 complete/transmit data

register empty

interrupt

TIM3 Capture/Compare/

USART3 Receive register

TIM3/

22

23

-

Yes

-

Yes⁽³⁾

0x00 8060

0x00 8064

data full/overrun/idle line

USART3

detected/parity error/

interrupt

Update /overflow/trigger/

TIM1

COM

24

25

26

TIM1

TIM4

SPI1

Capture/Compare

Update/overflow/trigger

End of Transfer

-

Yes⁽³⁾

0x00 8068

0x00 806C

0x00 8070

Yes

USART1 transmission

complete/transmit data

register empty/

USART 1/

TIM5

27

-

Yes

Yes⁽³⁾

0x00 8074

TIM5 update/overflow/

trigger/break

USART1 Receive register

data full/overrun/idle line

detected/parity error/

USART 1/

TIM5

28

29

-

Yes

Yes⁽³⁾

0x00 8078

0x00 807C

TIM5 capture/compare

I²C1 interrupt⁽⁵⁾

SPI2

/

I²C1/SPI2

Yes

1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.

2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.

3. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes

back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.

4. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port

E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).

5. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.

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STM8L15xx8, STM8L15xR6

Option bytes

7

Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated memory block.

All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM

address. See Table 11 for details on option byte addresses.

The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for

the ROP, UBC and PCODESIZE values which can only be taken into account when they are

modified in ICP mode (with the SWIM).

Refer to the STM8L15x/STM8L16x Flash programming manual (PM0054) and STM8 SWIM

and Debug Manual (UM0320) for information on SWIM programming procedures.

Table 11. Option byte addresses

Option

Option bits

3

Factory

default

setting

Addr.

Option name

byte

No.

7

6

5

4

2

1

0

Read-out

protection

(ROP)

00 4800

OPT0

ROP[7:0]

0x00

UBC (User

Boot code size)

00 4802

00 4807

OPT1

OPT2

UBC[7:0]

0x00

PCODESIZE

PCODE[7:0]

Independent

watchdog

option

OPT3

[3:0]

WWDG WWDG IWDG IWDG

_HALT _HW _HALT _HW

00 4808

Reserved

0x00

Number of

stabilization

00 4809 clock cycles for OPT4

HSE and LSE

Reserved

LSECNT[1:0]

HSECNT[1:0]

0x00

0x01

oscillators

Brownout reset

(BOR)

OPT5

[3:0]

BOR_

ON

00 480A

BOR_TH

00 480B

00 480C

Bootloader

option bytes

(OPTBL)

0x00

OPTBL

[15:0]

OPTBL[15:0]

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Option bytes

STM8L15xx8, STM8L15xR6

Table 12. Option byte description

Option

byte

Option description

No.

ROP[7:0] Memory readout protection (ROP)

OPT0

OPT1

0xAA: Disable readout protection (write access via SWIM protocol)

Refer to Readout protection section in the STM8L reference manual (RM0031).

UBC[7:0] Size of the user boot code area

0x00: No UBC

0x01: Page 0 reserved for the UBC and write protected.

0xFF: Page 0 to 254 reserved for the UBC and write-protected.

Refer to User boot code section in the STM8L reference manual (RM0031).

PCODESIZE[7:0] Size of the proprietary code area

0x00: No proprietary code area

0x01: Page 0 reserved for the proprietary code and read/write protected.

0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.

Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0031) for more

details.

OPT2

IWDG_HW: Independent watchdog

0: Independent watchdog activated by software

1: Independent watchdog activated by hardware

IWDG_HALT: Independent window watchdog reset on Halt/Active-halt

0: Independent watchdog continues running in Halt/Active-halt mode

1: Independent watchdog stopped in Halt/Active-halt mode

OPT3

WWDG_HW: Window watchdog

0: Window watchdog activated by software

1: Window watchdog activated by hardware

WWDG_HALT: Window window watchdog reset on Halt/Active-halt

0: Window watchdog stopped in Halt mode

1: Window watchdog generates a reset when MCU enters Halt mode

HSECNT: Number of HSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

OPT4

LSECNT: Number of LSE oscillator stabilization clock cycles

0x00 - 1 clock cycle

0x01 - 16 clock cycles

0x10 - 512 clock cycles

0x11 - 4096 clock cycles

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Option bytes

Table 12. Option byte description (continued)

Option

Option description

byte

No.

BOR_ON:

0: Brownout reset off

1: Brownout reset on

OPT5

BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 18 for details on the thresholds according to

the value of BOR_TH bits.

OPTBL[15:0]:

This option is checked by the boot ROM code after reset. Depending on

OPTBL content of addresses 00 480B, 00 480C and 0x8000 (reset vector) the

CPU jumps to the bootloader or to the reset vector.

Refer to the UM0560 bootloader user manual for more details.

Doc ID 17943 Rev 1

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Unique ID

STM8L15xx8, STM8L15xR6

8

Unique ID

devices feature a 96-bit unique device identifier which provides a reference number that is

unique for any device and in any context. The 96 bits of the identifier can never be altered by

the user.

The unique device identifier can be read in single bytes and may then be concatenated

using a custom algorithm.

The unique device identifier is ideally suited:

●

For use as serial numbers

●

For use as security keys to increase the code security in the program memory while

using and combining this unique ID with software crytograhic primitives and protocols

before programming the internal memory.

●

To activate secure boot processes

Table 13. Unique ID registers (96 bits)

Unique ID bits

Content

Address

description

7

6

5

4

3

2

1

0

0x4926

0x4927

0x4928

0x4929

0x492A

0x492B

0x492C

0x492D

0x492E

0x492F

0x4930

0x4931

U_ID[7:0]

X co-ordinate on

the wafer

U_ID[15:8]

U_ID[23:16]

U_ID[31:24]

U_ID[39:32]

U_ID[47:40]

U_ID[55:48]

U_ID[63:56]

U_ID[71:64]

U_ID[79:72]

U_ID[87:80]

U_ID[95:88]

Y co-ordinate on

the wafer

Wafer number

Lot number

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

9

Electrical parameters

9.1

Parameter conditions

Unless otherwise specified, all voltages are referred to V

.

SS

9.1.1

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean 3Σ).

9.1.2

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 3 V. They are given

A

DD

only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean 2Σ).

9.1.3

9.1.4

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Figure 10. Pin loading conditions

STM8L PIN

50 pF

Doc ID 17943 Rev 1

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Electrical parameters

STM8L15xx8, STM8L15xR6

9.1.5

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 11. Pin input voltage

STM8L PIN

V

IN

9.2

Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 14. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

External supply voltage (including V_DDA

V_DD- V_SS

- 0.3

4.0

(1)

and V_DD2

)

Input voltage on true open-drain pins

(PC0 and PC1)⁽²⁾

V_SS- 0.3

V_DD+ 4.0

V

V_IN

Input voltage on FT pins ⁽²⁾

V_SS- 0.3

V_DD+ 4.0

4.0

Input voltage on any other pin ⁽³⁾

see Absolute maximum

ratings (electrical sensitivity)

on page 113

V_ESD

Electrostatic discharge voltage

1. All power (V_DD1, V_DD2, V_DDA) and ground (V_SS1, V_SS2, V_SSA) pins must always be connected to the

external power supply.

2. Positive injection is not possible on these I/Os. V_INmaximum must always be respected. I_INJ(PIN)must

never be exceeded. A negative injection is induced by V_IN<V_SS

.

3. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS

.

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

Table 15. Current characteristics

Symbol

Ratings

Max.

Unit

I_VDD

I_VSS

Total current into V_DDpower line (source)

Total current out of V_SSground line (sink)

80

Output current sunk by IR_TIM pin (with high sink LED

driver capability)

80

I_IO

Output current sunk by any other I/O and control pin

Output current sourced by any I/Os and control pin

25

- 25

- 5

mA

Injected current on true open-drain pins (PC0 and PC1)⁽¹⁾

Injected current on FT pins⁽¹⁾

I_INJ(PIN)

- 5

5

Injected current on any other pin ⁽²⁾

Total injected current (sum of all I/O and control pins) ⁽³⁾

25

ΣI_INJ(PIN)

1. Positive injection is not possible on these I/Os. V_INmaximum must always be respected. I_INJ(PIN)must

never be exceeded. A negative injection is induced by V_IN<V_SS

.

2. I_INJ(PIN)must never be exceeded. This is implicitly insured if V_INmaximum is respected. If V_INmaximum

cannot be respected, the injection current must be limited externally to the I_INJ(PIN)value. A positive

injection is induced by V_IN>V_DDwhile a negative injection is induced by V_IN<V_SS

.

3. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with ΣI_INJ(PIN)maximum current injection on four I/O port pins of the device.

Table 16. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

-65 to +150

150

° C

Doc ID 17943 Rev 1

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Electrical parameters

STM8L15xx8, STM8L15xR6

9.3

Operating conditions

Subject to general operating conditions for V and T .

DD

A

9.3.1

General operating conditions

Table 17. General operating conditions

Symbol Parameter

System clock

Conditions

Min

Max

Unit

(1)

f

1.65 V ≤V_DD< 3.6 V

0

16

MHz

SYSCLK

frequency

BOR detector disabled

1.65

(D suffix version)

BOR detector enabled

ADC not used

Standard operating

voltage

V_DD

3.6

V

1.8⁽²⁾

1.65⁽²⁾

1.8

3.6

V

Analog operating

voltage

Must be at the same

potential as V_DD

V_DDA

ADC used

LQFP80

288

131

104

156

77

Power dissipation at

T_A= 85 °C for suffix 6

devices

LQFP64

UFQFPN48

LQFP48

(3)

P_D

mW

LQFP80

Power dissipation at

T_A= 125 °C for suffix 3

devices

LQFP64

UFQFPN48

LQFP48

1.65 V ≤V_DD< 3.6 V (6 suffix version)

1.65 V ≤V_DD< 3.6 V (3 suffix version)

-40

85

T_A

T_J

Temperature range

125

-40 °C ≤T_A< 85 °C

(6 suffix version)

°C

-40

105

130

Junction temperature

range

-40 °C≤ T_A< 125 °C

(3 suffix version)

1. f_SYSCLK= f_CPU

2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled by option byte

3. To calculate P_Dmax(T_A), use the formula P_Dmax=(T_Jmax-T_A)/Θ_JAwith T_Jmaxin this table and Θ_JAin “Thermal characteristics”

table.

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

9.3.2

Power-up / power-down operating conditions

Table 18. Operating conditions at power-up / power-down

Symbol⁽¹⁾

Parameter⁽¹⁾

Conditions⁽¹⁾

Typ

Min

Max

Unit

0⁽²⁾

V_DDrise time rate

∞

t_VDD

µs/V

ms

V_DDfall time rate

V

_DDrising

t_TEMP

V_POR

V_PDR

Reset release delay

3

Power-on reset threshold

Rising edge

TBD

1.5

TBD

Power-down reset threshold Falling edge

1.5

Falling edge

1.7

Brown-out reset threshold 0

(BOR_TH[2:0]=000)

V_BOR0

V_BOR1

V_BOR2

V_BOR3

V_BOR4

V_PVD0

V_PVD1

V_PVD2

V_PVD3

V_PVD4

V_PVD5

V_PVD6

Rising edge

1.75

1.93

2.04

2.3

Falling edge

Brown-out reset threshold 1

(BOR_TH[2:0]=001)

Rising edge

Falling edge

Brown-out reset threshold 2

(BOR_TH[2:0]=010)

Rising edge

2.41

2.55

2.66

2.80

2.90

1.84

1.94

2.04

2.14

2.24

2.34

2.44

2.54

2.64

2.74

2.83

2.94

3.05

3.15

40

Falling edge

Brown-out reset threshold 3

(BOR_TH[2:0]=011)

Rising edge

Falling edge

Brown-out reset threshold 4

(BOR_TH[2:0]=100)

Rising edge

Falling edge

PVD threshold 0

V

Rising edge

Falling edge

PVD threshold 1

Rising edge

Falling edge

PVD threshold 2

Rising edge

Falling edge

PVD threshold 3

Rising edge

Falling edge

PVD threshold 4

Rising edge

Falling edge

PVD threshold 5

Rising edge

Falling edge

PVD threshold 6

Rising edge

BOR0 threshold

All BOR and PVD

thresholds

Vhyst

Hysteresis voltage

mV

100

excepting BOR0

Doc ID 17943 Rev 1

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Electrical parameters

STM8L15xx8, STM8L15xR6

1. Based on characterization results, unless otherwise specified.

2. Guaranteed by design, not tested in production.

Figure 12. Power supply thresholds

V_DD/V_DDA

100 mV

hysteresis

V_PVD

100 mV

hysteresis

V_BOR

V_POR

V

/

PDR

IT enabled

PVD output

BOR reset

(NRST)

BOR/PDR reset

(NRST)

POR/PDR reset

(NRST)

(Note 1)

(Note 2)

(Note 3)

PVD

BOR always active

BOR disabled by option byte

POR/PDR (BOR not available) (Note 4)

ai17211b

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Electrical parameters

9.3.3

Supply current characteristics

Total current consumption

The MCU is placed under the following conditions:

●

All I/O pins in input mode with a static value at V or V (no load)

DD SS

●

All peripherals are disabled except if explicitly mentioned.

Subject to general operating conditions for V and T .

DD

A

Table 19. Total current consumption in Run mode

Para

Max

Conditions⁽¹⁾⁽²⁾

meter

Symbol

Typ

Unit

105 °C

85 °C

(3)

125 °C

(4)

(1)

55°C

(4)

f_CPU= 125 kHz

_CPU= 1 MHz

0.26 TBD

0.35 TBD

0.63 TBD

1.01 TBD

TBD

f

HSI RC osc.

(16 MHz)⁽⁶⁾

f_CPU= 4 MHz

f_CPU= 8 MHz

TBD

All

1.76 TBD TBD⁽⁸⁾

TBD⁽⁸⁾

TBD

peripherals

OFF,

code

f_CPU= 16 MHz

Supply

current

f_CPU= 125 kHz

TBD TBD

TBD

in run

mode

(5)

I_DD(RUN)

executed

from RAM,

V_DDfrom

mA

HSE

external

clock

f_CPU= 1 MHz

f_CPU= 4 MHz

f_CPU= 8 MHz

TBD

(f_CPU=f_HSE

)

1.65 V to

3.6 V

TBD

(7)

TBD⁽⁸⁾

f_CPU= 16 MHz

f_CPU= f_LSI

LSI RC osc.

(typ. 38 kHz)

0.037 TBD

0.036 TBD

TBD

LSE external

clock

f_CPU= f_LSE

(32.768 kHz)

Doc ID 17943 Rev 1

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Electrical parameters

STM8L15xx8, STM8L15xR6

Table 19. Total current consumption in Run mode (continued)

Para

Max

Conditions⁽¹⁾⁽²⁾

meter

(1)

Symbol

Typ

Unit

105 °C

85 °C

(3)

125 °C

(4)

55°C

(4)

f_CPU= 125 kHz

_CPU= 1 MHz

f_CPU= 4 MHz

0.33 TBD

0.52 TBD

1.19 TBD

2.08 TBD

3.94 TBD

TBD TBD

TBD

f

HSI RC

osc.⁽⁹⁾

f

_CPU= 8 MHz

_CPU= 16 MHz

f

All

peripherals

OFF, code

executed

from Flash,

V_DDfrom

f_CPU= 125 kHz

Supply

current

in Run

mode

HSE

external

clock

(f_CPU=f_HSE

(7)

f

_CPU= 1 MHz

_CPU= 4 MHz

mA

I_DD(RUN)

f

)

1.65 V to

3.6 V

f_CPU= 8 MHz

f

_CPU= 16 MHz

_CPU= f_LSI

f

LSI RC osc.

LSE external

clock

(32.768

f_CPU= f_LSE

TBD TBD

TBD

kHz)⁽¹⁰⁾

1. Based on characterization results, unless otherwise specified

2. All peripherals OFF, V_DDfrom 1.65 V to 3.6 V, HSI internal RC osc. , f_CPU=f_SYSCLK

3. For devices with suffix 6

4. For devices with suffix 3

5. CPU executing typical data processing

6. The run from RAM consumption can be approximated with the linear formula:

I_DD(run_from_RAM) = Freq * 95 µA/MHz + 250 µA

7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

(I_{DD HSE}) must be added. Refer to Table 30.

8. Design guaranteed, each individual device tested in production

9. The run from Flash consumption can be approximated with the linear formula:

I_DD(run_from_Flash) = Freq * 200 µA/MHz + 330 µA

10. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(I_{DD LSE}) must be added. Refer to Table 31

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Electrical parameters

(1)

Table 20. Total current consumption in Wait mode

Max

Conditions⁽²⁾

105

°C

Symbol Parameter

Typ

Unit

125

°C

85 °C

(3)

55°C

(4)

f_CPU= 125 kHz

0.25 TBD TBD TBD TBD

0.27 TBD TBD TBD TBD

0.35 TBD TBD TBD TBD

0.46 TBD TBD TBD TBD

f

_CPU= 1 MHz

_CPU= 4 MHz

_CPU= 8 MHz

HSI

TBD

TBD⁽

f

_CPU= 16 MHz

0.65 TBD

TBD

(6)

6)

CPU not

clocked,

all peripherals

OFF,

code executed

from RAM

with Flash in I_DDQ(f_CPU=f_HSE

mode,⁽⁵⁾

V_DDfrom

1.65 V to 3.6 V

f_CPU= 125 kHz

TBD TBD TBD TBD TBD

f

_CPU= 1 MHz

_CPU= 4 MHz

_CPU= 8 MHz

HSE

external

clock

Supply

I_DD(Wait)current in

Wait mode

mA

)

(7)

TBD

(6)

f

_CPU= 16 MHz

TBD TBD

TBD

(6)

f_CPU= f_LSI

LSI

TBD TBD TBD TBD

0.034

0.033

LSE⁽⁸⁾

external

clock

(32.768

kHz)

f_CPU= f_LSE

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Electrical parameters

STM8L15xx8, STM8L15xR6

Max

(1)

Table 20. Total current consumption in Wait mode

(continued)

Typ

Conditions⁽²⁾

105

°C

Symbol Parameter

Unit

125

°C

85 °C

(3)

55°C

(4)

f_CPU= 125 kHz

TBD TBD TBD TBD TBD TBD

f

_CPU= 1 MHz

_CPU= 4 MHz

_CPU= 8 MHz

HSI

f_CPU= 16 MHz

CPU not

f

_CPU= 125 kHz

_CPU= 1 MHz

_CPU= 4 MHz

_CPU= 8 MHz

_CPU= 16 MHz

_CPU= f_LSI

clocked,

all peripherals

OFF,

code executed

from Flash,

V_DDfrom

HSE⁽⁷⁾

external

clock

Supply

I_DD(Wait)current in

Wait mode

(f_CPU=HSE)

1.65 V to 3.6 V

LSI

LSE⁽⁸⁾

external

clock

f_CPU= f_LSE

TBD TBD TBD TBD TBD TBD

(32.768

kHz)

1. Based on characterization results, unless specified

2. All peripherals OFF, V_DDfrom 1.65 V to 3.6 V, HSI internal RC osc. , f_CPU= f_SYSCLK

3. For temperature range 6.

4. For temperature range 3.

5. Flash is configured in I_DDQmode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.

6. Design guaranteed, each individual part tested in production

7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption

(I_{DD HSE}) must be added. Refer to Table 30.

8. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(I_{DD HSE}) must be added. Refer to Table 31

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Electrical parameters

Table 21. Total current consumption and timing in Low power run mode at V = 1.65 V to

DD

3.6 V

Parameter⁽¹⁾

Conditions⁽²⁾

Typ⁽¹⁾Max⁽¹⁾

Symbol

Unit

T_A= -40 °C

to 25 °C

TBD

T_A= 55 °C

T_A= 85 °C

TBD

all peripherals OFF

T_A= 105 °C TBD

T_A= 125 °C TBD

LSI RC osc.

(at 38 kHz)

T_A= -40 °C

TBD

to 25 °C

T_A= 55 °C

T_A= 85 °C

TBD

with TIM2 active⁽³⁾

T_A= 105 °C TBD

T_A= 125 °C TBD

Supply current in Low

power run mode

I_DD(LPR)

μA

T_A= -40 °C

TBD

to 25 °C

T_A= 55 °C

T_A= 85 °C

TBD

all peripherals OFF

T_A= 105 °C TBD

T_A= 125 °C TBD

LSE ⁽⁴⁾external

clock

(32.768 kHz)

T_A= -40 °C

TBD

to 25 °C

T_A= 55 °C

T_A= 85 °C

TBD

with TIM2 active ⁽³⁾

T_A= 105 °C TBD

T_A= 125 °C TBD

1. Based on characterization results, unless otherwise specified

2. No floating I/Os

3. Timer 2 clock enabled and counter running

4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(I_{DD LSE}) must be added. Refer to Table 31

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Electrical parameters

STM8L15xx8, STM8L15xR6

Table 22. Total current consumption in Low power wait mode at V = 1.65 V to 3.6 V

DD

Typ Max

(1)(2) (1)(2)

Parameter⁽¹⁾⁽²⁾

Symbol

Conditions

Unit

T_A= -40 °C to 25 °C

TBD TBD

T_A= 55 °C

all peripherals OFF

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LSI RC osc.

(at 38 kHz)

T_A= 55 °C

with TIM2 active⁽³⁾

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

Supply current in

Low power wait mode

I_DD(LPW)

μA

T_A= 55 °C

all peripherals OFF

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LSE external

clock⁽⁴⁾

(32.768 kHz)

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

with TIM2 active ⁽³⁾

1. No floating I/Os.

2. Based on characterization results, unless otherwise specified.

3. Timer 2 clock enabled and counter is running.

4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(I_{DD LSE}) must be added. Refer to Table 31.

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Electrical parameters

Table 23. Total current consumption and timing in Active-halt mode

at V = 1.65 V to 3.6 V

DD

Typ

(1)(2)

Parameter⁽¹⁾⁽²⁾

Symbol

Conditions

Max Unit

T_A= -40 °C to 25 °C

T_A= 55 °C

TBD TBD

LCD OFF⁽³⁾

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LCD ON

(static duty/

external

T_A= 55 °C

T_A= 85 °C

(4)

V_LCD

)

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LSI RC

μA

Supply current in

Active-halt mode

I_DD(AH)

(at 38 kHz)

LCD ON

T_A= 55 °C

(1/4 duty/

external

(5)

T_A= 85 °C

V_LCD

)

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LCD ON

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

(1/4 duty/

internal

(6)

V_LCD

)

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Electrical parameters

STM8L15xx8, STM8L15xR6

Table 23. Total current consumption and timing in Active-halt mode

at V = 1.65 V to 3.6 V (continued)

DD

Typ

(1)(2)

Parameter⁽¹⁾⁽²⁾

Symbol

Conditions

Max Unit

T_A= -40 °C to 25 °C

T_A= 55 °C

TBD TBD

LCD OFF⁽⁸⁾

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

T_A= 55 °C

LCD ON

(static duty)

(4)

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LSE external

clock

(32.768 kHz)

Supply current in

Active-halt mode

I_DD(AH)

μA

(7)

T_A= 55 °C

LCD ON

(1/4 duty) ⁽⁵⁾

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

T_A= -40 °C to 25 °C

LCD ON

(1/4 duty/

internal

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

(6)

V_LCD

)

Supply current during

wakeup time from

Active-halt mode

(using HSI)

I_DD(WUFAH)

TBD

mA

Wakeup time from

Active-halt mode to

Run mode (using HSI)

(9)

t_{WU_HSI(AH)}

TBD TBD

TBD

μs

(10)

Wakeup time from

Active-halt mode to

Run mode (using LSI)

(9)

t_{WU_LSI(AH)}

(10)

1. No floating I/O, unless otherwise specified.

2. Based on characterization results, unless otherwise specified.

3. RTC enabled. Clock source = LSI

4. RTC enabled, LCD enabled with external V_LCD= 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.

5. RTC enabled, LCD enabled with external V_LCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

6. LCD enabled with internal LCD booster V_LCD= 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD

connected.

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Electrical parameters

7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(I_{DD LSE}) must be added. Refer to Table 31

8. RTC enabled. Clock source = LSE

9. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t_WU

.

10. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Table 24. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal

Symbol

Parameter

Condition

Typ

Unit

LSE

LSE/32⁽²⁾

LSE

TBD

V

_DD= 1.8 V

Supply current in Active-halt

mode

(1)

V

_DD= 3 V

µA

I_DD(AH)

LSE/32⁽²⁾

LSE

V_DD= 3.6 V

LSE/32⁽²⁾

1. Based on measurements on bench with 32.768 kHz external crystal oscillator.

2. RTC clock is LSE divided by 32.

Table 25. Total current consumption and timing in Halt mode at V = 2 V

DD

Typ

(1)(2)

Max

(1)(2)

Parameter ⁽¹⁾⁽²⁾

Symbol

Condition

Unit

(3)

T_A= -40 °C to 25 °C

T_A= 55 °C

400

TBD

Supply current in Halt mode

TBD

I_DD(Halt)

nA

(Ultra low power ULP bit =1 in

the PWR_CSR2 register)

T_A= 85 °C

T_A= 105 °C

Supply current during wakeup

time from Halt mode (using

HSI)

I_DD(WUHalt)

TBD

mA

Wakeup time from Halt to Run

mode (using HSI)

(4)(5)

TBD

µs

t_{WU_HSI(Halt)}

Wakeup time from Halt mode

to Run mode (using LSI)

(4)(5)

t_{WU_LSI(Halt)}

1. T_A= -40 to 125 °C, no floating I/O, unless otherwise specified

2. Based on characterization results, unless otherwise specified

3. Data guaranteed, each individual device tested in production

4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register

5. Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after t_WU

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Electrical parameters

STM8L15xx8, STM8L15xR6

Current consumption of on-chip peripherals

Table 26. Peripheral current consumption

Typ.

Symbol

Parameter

Unit

V_DD= 3.0 V

TIM1 supply current⁽¹⁾

TIM2 supply current ⁽¹⁾

TIM3 supply current ⁽¹⁾

TIM5 supply current ⁽¹⁾

TIM4 timer supply current ⁽¹⁾

USART1 supply current ⁽²⁾

USART2 supply current ⁽³⁾

USART3 supply current ⁽⁴⁾

SPI1 supply current ⁽⁴⁾

SPI2 supply current ⁽⁴⁾

I_DD(TIM1)

I_DD(TIM2)

I_DD(TIM3)

I_DD(TIM5)

I_DD(TIM4)

I_DD(USART1)

I_DD(USART2)

I_DD(USART3)

I_DD(SPI1)

10

7

3

5

µA/MHz

5

3

I_DD(SPI2)

3

I²C1 supply current ⁽⁴⁾

DMA1 supply current

WWDG supply current

I_DD(I2C1)

4

I_DD(DMA1)

I_DD(WWDG)

I_DD(ALL)

3

1

Peripherals ON⁽⁵⁾

63

1500

370

ADC1 supply current⁽⁶⁾

DAC supply current⁽⁷⁾

Comparator 1 supply current⁽⁸⁾

I_DD(ADC1)

I_DD(DAC)

I_DD(COMP1)

0.160

Slow mode

Fast mode

2

5

Comparator 2 supply current⁽⁸⁾

I_DD(COMP2)

µA

Power voltage detector and brownout Reset unit supply current

I_DD(PVD/BOR)

I_DD(BOR)

2.6

(9)

Brownout Reset unit supply current ⁽⁹⁾

including LSI supply

current

Independent watchdog supply current

excluding LSI

2.4

0.45

I_DD(IDWDG)

0.05

supply current

1. Data based on a differential I_DDmeasurement between all peripherals OFF and a timer counter running at 16 MHz. The

CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.

2. Data based on a differential I_DDmeasurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins

toggling. Not tested in production.

3. Data based on a differential I_DDmeasurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins

toggling. Not tested in production.

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Electrical parameters

4. Data based on a differential I_DDmeasurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins

toggling. Not tested in production.

5. Peripherals listed above the I_DD(ALL)parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.

6. Data based on a differential I_DDmeasurement between ADC in reset configuration and continuous ADC conversion.

7. Data based on a differential I_DDmeasurement between DAC in reset configuration and continuous DAC conversion of

V

_DD/2. Floating DAC output.

8. Data based on a differential I_DDmeasurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2

enabled with static inputs. Supply current of internal reference voltage excluded.

9. Including supply current of internal reference voltage.

Table 27. Current consumption under external reset

Symbol

Parameter

Conditions

Typ

Unit

V_DD= 1.8 V

_DD= 3 V

V_DD= 3.6 V

48

80

95

Supply current under

external reset ⁽¹⁾

PB1/PB3/PA5 pins are

externally tied to V_DD

I_DD(RST)

V

µA

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.

9.3.4

Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for V and T .

DD

A

Table 28. HSE external clock characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

External clock source

frequency⁽¹⁾

f_{HSE_ext}

1

16

MHz

OSC_IN input pin high level

voltage

(2)

0.7 x V_DD

V_SS

V_DD

V_HSEH

V

OSC_IN input pin low level

voltage

(2)

0.3 x V_DD

V_HSEL

OSC_IN input

capacitance⁽¹⁾

C_in(HSE)

2.6

pF

µA

OSC_IN input leakage

current

I_{LEAK_HSE}

V_SS< V_IN< V_DD

1

1. Guaranteed by design, not tested in production.

2. Data based on characterization results, not tested in production.

LSE external clock (LSEBYP=1 in CLK_ECKCR)

Subject to general operating conditions for V and T .

DD

A

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Electrical parameters

STM8L15xx8, STM8L15xR6

Table 29. LSE external clock characteristics

Symbol

Parameter

Min

Typ

Max

Unit

External clock source frequency⁽¹⁾

f_{LSE_ext}

32.768

kHz

(2)

OSC32_IN input pin high level voltage

0.7 x V_DD

V_SS

V_DD

V_LSEH

V

(2)

OSC32_IN input pin low level voltage

0.3 x V_DD

V_LSEL

OSC32_IN input capacitance⁽¹⁾

OSC32_IN input leakage current

C_in(LSE)

0.6

pF

µA

I_{LEAK_LSE}

1

1. Guaranteed by design, not tested in production.

2. Data based on characterization results, not tested in production.

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Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All

the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Table 30. HSE oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

High speed external oscillator

frequency

f_HSE

1

16

MHz

R_F

Feedback resistor

200

20

kΩ

C⁽¹⁾

pF

Recommended load capacitance ⁽²⁾

C = 20 pF,

_OSC= 16 MHz

2.5 (startup)

f

0.7 (stabilized)⁽³⁾

I_DD(HSE)HSE oscillator power consumption

mA

C = 10 pF,

2.5 (startup)

f_OSC=16 MHz

0.46 (stabilized)⁽³⁾

g_m

Oscillator transconductance

Startup time

3.5

mA/V

ms

(4)

t_SU(HSE)

V_DDis stabilized

1

1. C=

C =C_L2is approximately equivalent to 2 x crystal C_LOAD.

L1

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R_mvalue.

Refer to crystal manufacturer for more details

3. Guaranteed by design. Not tested in production.

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This

value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 13. HSE oscillator circuit diagram

f

to core

HSE

R

m

R

F

C

O

L

m

C

L1

OSC_IN

C

m

g

m

Resonator

Consumption

control

Resonator

STM8

OSC_OUT

C

L2

HSE oscillator critical g formula

m

g_mcrit= (2 × Π × f_HSE)²× R_m(2Co + C)²

R : Motional resistance (see crystal specification), L : Motional inductance (see crystal specification),

m

C : Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),

m

C

=C =C: Grounded external capacitance

L1

L2

g

>> g

m

mcrit

Doc ID 17943 Rev 1

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Electrical parameters

STM8L15xx8, STM8L15xR6

LSE crystal/ceramic resonator oscillator

The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All

the information given in this paragraph is based on characterization results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and startup stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Table 31. LSE oscillator characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Low speed external oscillator

frequency

f_LSE

32.768

kHz

R_F

Feedback resistor

ΔV = 200 mV

1.2

8

MΩ

pF

C⁽¹⁾

Recommended load capacitance ⁽²⁾

1.4⁽³⁾

µA

V

_DD= 1.8 V

450

600

750

I_DD(LSE)LSE oscillator power consumption

V_DD= 3 V

nA

V_DD= 3.6 V

g_m

Oscillator transconductance

Startup time

3

µA/V

s

(4)

t_SU(LSE)

V_DDis stabilized

1

1. C=

C =C_L2is approximately equivalent to 2 x crystal C_LOAD.

L1

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small R_mvalue.

Refer to crystal manufacturer for more details.

3. Guaranteed by design. Not tested in production.

4. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.

This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 14. LSE oscillator circuit diagram

f

LSE

R

m

R

F

C

O

L

m

C

L1

OSC_IN

C

m

g

m

Resonator

Consumption

control

Resonator

STM8

OSC_OUT

C

L2

86/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

Internal clock sources

Subject to general operating conditions for V , and T .

DD

A

High speed internal RC oscillator (HSI)

Table 32. HSI oscillator characteristics

Conditions⁽¹⁾

Symbol

Min

Typ

Max

Unit

Parameter

Frequency

f_HSI

V_DD= 3.0 V

16

MHz

%

V_DD= 3.0 V, T_A= 25 °C

-1

1

1.5

2

V_DD= 3.0 V, 0 °C ≤T_A≤ 55 °C

-1.5

-2

%

V

_DD= 3.0 V, -10 °C ≤T_A≤ 70 °C

%

Accuracy of HSI

oscillator (factory

calibrated)

(2)

ACC_HSI

V_DD= 3.0 V, -10 °C ≤T_A≤ 85 °C

V_DD= 3.0 V, -10 °C ≤T_A≤ 125 °C

-2.5

-4.5

2

%

2

%

1.65 V ≤V_DD≤ 3.6 V,

-40 °C ≤T_A≤ 125 °C

-4.5

3

%

HSI user trim

resolution

1.65 V ≤V_DD≤ 3.6 V,

-40 °C ≤T_A≤ 125 °C

TRIM⁽²⁾

0.4 ⁽²⁾

3.7

0.5⁽²⁾

7.4

HSI oscillator setup

time (wakeup time)

(3)

t_su(HSI)

µs

HSI oscillator power

consumption

(3)

I_DD(HSI)

100

140

µA

1. V_DD= 3.0 V, T_A= -40 to 125 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production

Figure 15. Typical HSI frequency vs V

DD

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6_$$;6=

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AIꢀꢃꢂꢀꢃ

Doc ID 17943 Rev 1

87/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Low speed internal RC oscillator (LSI)

Table 33. LSI oscillator characteristics

Conditions⁽¹⁾

Symbol

Min

Typ

Max

Unit

Parameter

Frequency

f_LSI

26

38

56

kHz

µs

t_su(LSI)LSI oscillator wakeup time

200⁽²⁾

LSI oscillator frequency

D_(LSI)

drift⁽³⁾

0 °C ≤T_A≤ 85 °C

-10

4

%

1. V_DD= 1.8 V to 3.0 V, T_A= -40 to 125 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. This is a deviation for an individual part, once the initial frequency has been measured.

Figure 16. Typical LSI frequency vs. V

DD

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ꢒꢐ #

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ꢉꢋꢀ

ꢉꢋꢅ

6_$$;6=

AIꢀꢃꢂꢀꢒ

88/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

9.3.5

Memory characteristics

T = -40 to 125 °C unless otherwise specified.

A

Table 34. RAM and hardware registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_RM

Data retention mode ⁽¹⁾

Halt mode (or Reset)

1.4

V

1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware

registers (only in Halt mode). Guaranteed by characterization, not tested in production.

Flash memory

Table 35. Flash program and data EEPROM memory

Max

Symbol

Parameter

Conditions

Min

Typ

Unit

(1)

Operating voltage

(all modes, read/write/erase)

V_DD

f_SYSCLK= 16 MHz

1.65

3.6

V

Programming time for 1 or 128 bytes (block)

erase/write cycles (on programmed byte)

6

3

ms

t_prog

Programming time for 1 to 128 bytes (block)

write cycles (on erased byte)

T_A=+25 °C, V_DD= 3.0 V

T_A=+25 °C, V_DD= 1.8 V

I_prog

Programming/ erasing consumption

0.7

mA

Data retention (program memory) after 10000

erase/write cycles at T_A=+85 °C

T_RET=+55 °C

20⁽¹⁾

Data retention (data memory) after 10000

erase/write cycles at T_A=+85 °C

t_RET

years

Data retention (data memory) after 10000

erase/write cycles at T_A=+85 °C

T_RET=+85 °C

See notes ⁽¹⁾⁽²⁾

See notes ⁽¹⁾⁽³⁾

1⁽¹⁾

Erase/write cycles (program memory)

10⁽¹⁾

300⁽¹⁾

N_RW

kcycles

Erase/write cycles (data memory)

(4)

1. Data based on characterization results, not tested in production.

2. Retention guaranteed after cycling is 10 years @ 55 °C.

3. Retention guaranteed after cycling is 1 year @ 55 °C.

4. Data based on characterization performed on the whole data memory.

Doc ID 17943 Rev 1

89/122

Electrical parameters

STM8L15xx8, STM8L15xR6

9.3.6

I/O port pin characteristics

General characteristics

Subject to general operating conditions for V and T unless otherwise specified. All

DD

A

unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or

an external pull-up or pull-down resistor.

Table 36. I/O static characteristics

Parameter⁽¹⁾

Symbol

Conditions⁽¹⁾

Typ

Min

Max

Unit

Input voltage on true

open-drain pins (PC0

and PC1)

V_SS-0.3

0.3 x V_DD

Input low level voltage⁽²⁾

V_IL

Input voltage on FT

pins (PA7 and PE0)

V

V_SS-0.3

0.3 x V_DD

Input voltage on any

other pin

Input voltage on true

open-drain pins (PC0

and PC1)

5.2

with V_DD< 2 V

0.70 x V_DD

Input voltage on true

open-drain pins (PC0

and PC1)

5.5

5.2

with V_DD≥ 2 V

Input high level voltage ⁽²⁾

V_IH

V

Input voltage on FT

pins (PA7 and PE0)

with V_DD< 2 V

0.70 x V_DD

Input voltage on FT

pins (PA7 and PE0)

with V_DD≥ 2 V

5.5

Input voltage on any

other pin

V_DD+0.3

Standard I/Os

200

Schmitt trigger voltage hysteresis ⁽³⁾

V_hys

mV

nA

True open drain I/Os

V_SS≤V_IN≤V_DD

Standard I/Os

-

50 ⁽⁵⁾

V_SS≤V_IN≤V_DD

True open drain I/Os

200⁽⁵⁾

I_lkg

Input leakage current ⁽⁴⁾

V_SS≤V_IN≤V_DD

PA0 with high sink LED

driver capability

-

200⁽⁵⁾

60

Weak pull-up equivalent resistor⁽⁶⁾

I/O pin capacitance

R_PU

V_IN=V_SS

30

45

5

kΩ

(7)

pF

C_IO

1. V_DD= 3.0 V, T_A= -40 to 125 °C unless otherwise specified.

90/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Not tested in production.

6. R_PUpull-up equivalent resistor based on a resistive transistor(corresponding I_PUcurrent characteristics described in

Figure 20).

7. Data guaranteed by Design, not tested in production.

Figure 17. Typical V and V vs V (standard I/Os)

IL

IH

DD

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ꢀ

ꢐꢋꢍ

ꢐ

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ꢂꢋꢅ

ꢉꢋꢀ

ꢉꢋꢅ

6_$$;6=

AIꢀꢃꢂꢂꢐ

Figure 18. Typical V and V vs V (true open drain I/Os)

IL

IH

DD

ꢉ

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ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

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ꢀ

ꢐꢋꢍ

ꢐ

ꢀꢋꢅ

ꢂꢋꢀ

ꢂꢋꢅ

_$$;6=

ꢉꢋꢀ

ꢉꢋꢅ

6

AIꢀꢃꢂꢂꢀ

Doc ID 17943 Rev 1

91/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Figure 19. Typical pull-up resistance R vs V with V =V

PU

DD

IN

SS

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ꢒꢐ #

ꢀꢉꢐ #

ꢀꢋꢅ

ꢀꢋꢃ

ꢂ

ꢂꢋꢂ

ꢂꢋꢆ

ꢂꢋꢅ

6_$$;6=

ꢂꢋꢃ

ꢉ

ꢉꢋꢂ

ꢉꢋꢆ

ꢉꢋꢅ

AIꢀꢃꢂꢂꢂ

Figure 20. Typical pull-up current I vs V with V =V

SS

pu

DD

IN

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ꢆꢐ

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ꢒꢐ #

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_$$;6=

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AIꢀꢃꢂꢂꢉ

6

92/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

Output driving current

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 37. Output driving current (standard ports)

I/O

Symbol

Parameter

Conditions

Min

Max Unit

Type

I_IO= +2 mA,

V_DD= 3.0 V

0.45

0.7

V

I_IO= +2 mA,

V_DD= 1.8 V

(1)

Output low level voltage for an I/O pin

V_OL

I

_IO= +10 mA,

V_DD= 3.0 V

I_IO= -2 mA,

V_DD= 3.0 V

V

_DD-0.45

I

_IO= -1 mA,

(2)

V_DD-0.45

V_DD-0.7

Output high level voltage for an I/O pin

V_OH

V_DD= 1.8 V

I

_IO= -10 mA,

V_DD= 3.0 V

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 15 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

2. The I_IOcurrent sourced must always respect the absolute maximum rating specified in Table 15 and the

sum of I_IO(I/O ports and control pins) must not exceed I_VDD

.

Table 38. Output driving current (true open drain ports)

I/O

Symbol

Parameter

Conditions

Min

Max Unit

Type

I_IO= +3 mA,

V_DD= 3.0 V

0.45

V

(1)

Output low level voltage for an I/O pin

V_OL

I_IO= +1 mA,

V_DD= 1.8 V

0.45

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 15 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

Table 39. Output driving current (PA0 with high sink LED driver capability)

I/O

Symbol

Parameter

Conditions

Min

Max Unit

Type

I_IO= +20 mA,

V_DD= 2.0 V

(1)

Output low level voltage for an I/O pin

0.45

V

V_OL

1. The I_IOcurrent sunk must always respect the absolute maximum rating specified in Table 15 and the sum

of I_IO(I/O ports and control pins) must not exceed I_VSS

.

Doc ID 17943 Rev 1

93/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Figure 21. Typ. V @ V = 3.0 V (standard

Figure 22. Typ. V @ V = 1.8 V (standard

OL DD

OL

DD

ports)

ꢀ

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ꢐꢋꢁ

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ꢐꢋꢍ

ꢐꢋꢆ

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ꢐꢋꢂ

ꢐꢋꢀ

ꢐ

ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢀꢉꢐ #

ꢐꢋꢂꢍ

ꢐ

ꢂ

ꢆ

ꢅ

ꢃ

ꢀꢐ

ꢀꢂ

ꢀꢆ

ꢀꢅ

ꢀꢃ

ꢂꢐ

)

_/,;M!=

ꢐ

ꢀ

ꢂ

ꢉ

ꢆ

ꢍ

ꢅ

ꢁ

ꢃ

)

;M!=

/,

AIꢀꢃꢂꢂꢅ

AIꢀꢃꢂꢂꢁ

Figure 23. Typ. V @ V = 3.0 V (true open Figure 24. Typ. V @ V = 1.8 V (true open

OL

DD

OL

DD

drain ports)

ꢐꢋꢍ

ꢐꢋꢆ

ꢐꢋꢉ

ꢐꢋꢂ

ꢐꢋꢀ

ꢐ

ꢐꢋꢍ

ꢐꢋꢆ

ꢐꢋꢉ

ꢐꢋꢂ

ꢐꢋꢀ

ꢐ

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ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢀꢉꢐ #

ꢒꢐ #

ꢀꢉꢐ #

ꢐ

ꢀ

ꢂ

ꢉ

ꢆ

ꢍ

ꢅ

ꢁ

ꢐ

ꢀ

ꢂ

ꢉ

ꢆ

ꢍ

ꢅ

ꢁ

)

_/,;M!=

)_/,;M!=

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AIꢀꢃꢂꢂꢃ

Figure 25. Typ. V

V

@ V = 3.0 V

Figure 26. Typ. V

V

@ V = 1.8 V

DD - OH

DD

DD - OH DD

(standard ports)

ꢂ

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ꢀꢋꢍ

ꢀꢋꢂꢍ

ꢀ

ꢐꢋꢍ

ꢐꢋꢆ

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ꢐꢋꢂ

ꢐꢋꢀ

ꢐ

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ꢂꢍ #

ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢀꢉꢐ #

ꢐꢋꢁꢍ

ꢐꢋꢍ

ꢐꢋꢂꢍ

ꢐ

ꢂ

ꢆ

ꢅ

ꢃ

ꢀꢐ

ꢀꢂ

ꢀꢆ

ꢀꢅ

ꢀꢃ

ꢂꢐ

)

_/(;M!=

ꢐ

ꢀ

ꢂ

ꢉ

ꢆ

ꢍ

ꢅ

ꢁ

)

_/(;M!=

AIꢀꢂꢃꢉꢐ

BJꢄꢀꢇꢉꢄ

94/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

NRST pin

Electrical parameters

Subject to general operating conditions for V and T unless otherwise specified.

DD

A

Table 40. NRST pin characteristics

Typ ⁽¹⁾

Symbol

V_IL(NRST)

V_IH(NRST)

Parameter

Conditions

Min

V_SS

1.4

Max

Unit

NRST input low level voltage ⁽¹⁾

NRST input high level voltage ⁽¹⁾

0.8

V_DD

I_OL= 2 mA

for 2.7 V ≤V_DD≤ 3.6 V

V

V_OL(NRST)

NRST output low level voltage

0.4

I_OL= 1.5 mA

for V_DD< 2.7 V

10%V_DD

NRST input hysteresis⁽³⁾

V_HYST

mV

(2)

R_PU(NRST)

V_F(NRST)

NRST pull-up equivalent resistor

NRST input filtered pulse ⁽³⁾

NRST input not filtered pulse ⁽³⁾

30

45

60

50

kΩ

ns

V_NF(NRST)

300

1. Data based on characterization results, not tested in production.

2. 200 mV min.

3. Data guaranteed by design, not tested in production.

Figure 27. Typical NRST pull-up resistance R vs V

PU

DD

ꢅꢐ

ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢀꢉꢐ #

ꢍꢍ

ꢍꢐ

ꢆꢍ

ꢆꢐ

ꢉꢍ

ꢉꢐ

ꢀꢋꢅ

ꢀꢋꢃ

ꢂ

ꢂꢋꢂ

ꢂꢋꢆ

ꢂꢋꢅ

6_$$;6=

ꢂꢋꢃ

ꢉ

ꢉꢋꢂ

ꢉꢋꢆ

ꢉꢋꢅ

AIꢀꢃꢂꢂꢆ

Doc ID 17943 Rev 1

95/122

Electrical parameters

Figure 28. Typical NRST pull-up current I vs V

STM8L15xx8, STM8L15xR6

pu

DD

ꢀꢂꢐ

ꢀꢐꢐ

ꢃꢐ

ꢅꢐ

ꢆꢐ

ꢂꢐ

ꢐ

ꢇꢆꢐ #

ꢂꢍ #

ꢒꢐ #

ꢀꢉꢐ #

ꢀꢋꢅꢍ ꢀꢋꢃ ꢀꢋꢒꢍ ꢂꢋꢀ ꢂꢋꢂꢍ ꢂꢋꢆ ꢂꢋꢍꢍ ꢂꢋꢁ ꢂꢋꢃꢍ

6_$$;6=

ꢉ

ꢉꢋꢀꢍ ꢉꢋꢉ ꢉꢋꢆꢍ ꢉꢋꢅ

AIꢀꢃꢂꢂꢍ

The reset network shown in Figure 29 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the V max. level specified in

IL

Table 40. Otherwise the reset is not taken into account internally. For power consumption-

sensitive applications, the capacity of the external reset capacitor can be reduced to limit the

charge/discharge current. If the NRST signal is used to reset the external circuitry, the user

must pay attention to the charge/discharge time of the external capacitor to meet the reset

timing conditions of the external devices. The minimum recommended capacity is 10 nF.

Figure 29. Recommended NRST pin configuration

V

DD

R_PU

EXTERNAL

RESET

CIRCUIT

RSTIN

INTERNAL RESET

STM8L

Filter

0.1 μF

96/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

9.3.7

Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under ambient temperature, f frequency and V supply voltage

SYSCLK

DD

conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on

the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 41. SPI1 characteristics

Symbol

Parameter

Conditions⁽¹⁾

Master mode

Min

Max

Unit

MHz

ns

0

8

f_SCK

1/t_c(SCK)

SPI1 clock frequency

Slave mode

t_r(SCK)

t_f(SCK)

SPI1 clock rise and fall

time

Capacitive load: C = 30 pF

-

30

(2)

t_su(NSS)

NSS setup time

NSS hold time

Slave mode

4 x 1/f_SYSCLK

80

-

(2)

t_h(NSS)

(2)

t_w(SCKH)

t_w(SCKL)

Master mode,

f_MASTER= 8 MHz, f_SCK= 4 MHz

SCK high and low time

Data input setup time

105

145

(2)

Master mode

30

3

-

t_su(MI)

t_su(SI)

(2)

Slave mode

-

(2)

Master mode

15

0

-

t_h(MI)

t_h(SI)

Data input hold time

(2)

Slave mode

-

(2)(3)

t_a(SO)

Data output access time

Data output disable time

Data output valid time

Slave mode

-

3x 1/f_SYSCLK

(2)(4)

t_dis(SO)

Slave mode

30

-

(2)

t_v(SO)

t_v(MO)

t_h(SO)

t_h(MO)

Slave mode (after enable edge)

60

Master mode (after enable

edge)

Data output valid time

-

20

-

Slave mode (after enable edge)

15

1

Data output hold time

Master mode (after enable

edge)

-

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.

Doc ID 17943 Rev 1

97/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Figure 30. SPI1 timing diagram - slave mode and CPHA=0

NSS input

t

SU(NSS)

c(SCK)

h(NSS)

CPHA=0

CPOL=0

t

w(SCKH)

w(SCKL)

CPHA=0

CPOL=1

t

dis(SO)

v(SO)

r(SCK)

f(SCK)

h(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

BIT1 IN

LSB OUT

t

su(SI)

MOSI

M SB IN

LSB IN

INPUT

t

h(SI)

ai14134

(1)

Figure 31. SPI1 timing diagram - slave mode and CPHA=1

NSS input

t

SU(NSS)

t

c(SCK)

h(NSS)

CPHA=1

CPOL=0

w(SCKH)

CPHA=1

CPOL=1

t

w(SCKL)

t

r(SCK)

f(SCK)

t

v(SO)

h(SO)

dis(SO)

t

a(SO)

MISO

OUT PUT

MSB O UT

BI T6 OUT

LSB OUT

t

su(SI)

h(SI)

MOSI

M SB IN

BIT1 IN

LSB IN

INPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

98/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

(1)

Figure 32. SPI1 timing diagram - master mode

High

NSS input

t

c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

t

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

t

su(MI)

MISO

INPUT

MSBIN

BIT6 IN

LSB IN

t

h(MI)

MOSI

M SB OUT

BIT1 OUT

LSB OUT

OUTUT

t

v(MO)

h(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3V_DDand 0.7V_DD

.

Doc ID 17943 Rev 1

99/122

Electrical parameters

STM8L15xx8, STM8L15xR6

I²C - Inter IC control interface

Subject to general operating conditions for V

, and T unless otherwise specified.

, f

DD

A

SYSCLK

2

The STM8L I C interface (I2C1) meets the requirements of the Standard I C communication

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Table 42. I2C characteristics

Standard mode

Fast mode I²C⁽¹⁾

I²C

Symbol

Parameter

Unit

Min⁽²⁾

4.7

Max ⁽²⁾

Min ⁽²⁾

1.3

Max ⁽²⁾

t_w(SCLL)

t_w(SCLH)

t_su(SDA)

t_h(SDA)

SCL clock low time

μs

SCL clock high time

SDA setup time

4.0

0.6

250

0

100

0

SDA data hold time

900

300

t_r(SDA)

t_r(SCL)

ns

SDA and SCL rise time

1000

300

t_f(SDA)

t_f(SCL)

SDA and SCL fall time

300

t_h(STA)

t_su(STA)

t_su(STO)

t_w(STO:STA)

C_b

START condition hold time

4.0

4.7

4.0

4.7

0.6

1.3

μs

Repeated START condition setup

time

STOP condition setup time

μs

pF

STOP to START condition time (bus

free)

Capacitive load for each bus line

400

1. f_SYSCLKmust be at least equal to 8 MHz to achieve max fast I²C speed (400 kHz).

Data based on standard I²C protocol requirement, not tested in production.

2.

Note:

For speeds around 200 kHz, the achieved speed can have a 5% tolerance

For other speed ranges, the achieved speed can have a 2% tolerance

The above variations depend on the accuracy of the external components used.

100/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

2

Typical application with I C bus and timing diagram¹⁾

Figure 33.

V

DD

4.7kΩ

100Ω

SDA

SCL

2

I C BUS

STM8L

REPEATED START

START

t

su(STA)

w(STO:STA)

START

SDA

t

r(SDA)

f(SDA)

STOP

t

h(SDA)

su(SDA)

SCL

t

su(STO)

t

h(STA)

w(SCLH)

w(SCLL)

r(SCL)

f(SCL)

1. Measurement points are done at CMOS levels: 0.3 x V_DDand 0.7 x V_DD

Doc ID 17943 Rev 1

101/122

Electrical parameters

STM8L15xx8, STM8L15xR6

9.3.8

LCD controller (STM8L152xx only)

(1)

Table 43. LCD characteristics

Symbol

Parameter

Min

Typ

Max.

Unit

V_LCD

V_LCD0

V_LCD1

V_LCD2

V_LCD3

V_LCD4

V_LCD5

V_LCD6

V_LCD7

C_EXT

LCD external voltage

3.6

V

LCD internal reference voltage 0

LCD internal reference voltage 1

LCD internal reference voltage 2

LCD internal reference voltage 3

LCD internal reference voltage 4

LCD internal reference voltage 5

LCD internal reference voltage 6

LCD internal reference voltage 7

V_LCDexternal capacitance

2.6

2.7

2.8

3.0

3.1

3.2

3.4

3.5

1

V

0.1

2

µF

µA

Supply current⁽²⁾at V_DD= 1.8 V

Supply current⁽²⁾at V_DD= 3 V

3

I_DD

3

(3)

R_HN

Low drive resistive network

6.6

MΩ

kΩ

(= 3 X R_H)

(4)

R_LN

(= 3 X R_L)

High drive resistive network

240

V₃₃

V₂₃

V₁₂

V₁₃

V₀

Segment/Common higher level voltage

Segment/Common 2/3 level voltage

Segment/Common 1/2 level voltage

Segment/Common 1/3 level voltage

Segment/Common lowest level voltage

V_LCDx

V

2/3V_LCDx

1/2V_LCDx

1/3V_LCDx

0

1. Data guaranteed by Design, not tested in production.

2. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels

active, no LCD connected.

3. R_HNis the total resistive network value. The bridge is made of 3 R_Hserial resistors.

4. R_LNis the total resistive network value. The bridge is made of 3 R_Lserial resistors.

VLCD external capacitor (STM8L152xx only)

The application can achieve a stabilized LCD reference voltage by connecting an external

capacitor C

to the V

pin. C

is specified in Table 43.

EXT

LCD

EXT

102/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

9.3.9

Embedded reference voltage

Based on characterization results, not tested in production, unless otherwise specified.

Table 44. Reference voltage characteristics

Symbol

Parameter

Conditions

Min

Typ Max.

Unit

Internal reference voltage

consumption

I_REFINT

1.4

µA

ADC sampling time when reading

the internal reference voltage⁽²⁾

(1)

T_{S_VREFINT}

5

10

25

µs

Internal reference voltage buffer

consumption (used for ADC)

(1)

I_BUF

13.5

µA

V

V_{REFINT out}

V_{REFINT_DIV1}

V_{REFNT_DIV2}

V_{REFNT_DIV3}

Reference voltage output

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

1.202 1.224 1.242

25

50

75

%V_{REFINT_COMP}

Internal reference voltage low power

buffer consumption (used for

comparators or output)

(1)

I_LPBUF

730 1200

nA

(1)

I_REFOUT

Buffer output current⁽³⁾

1

µA

pF

C_REFOUT

Reference voltage output load

50

Internal reference voltage startup

time

(1)

t_VREFINT

2

3

ms

µs

Internal reference voltage buffer

startup time once enabled ⁽²⁾

(1)

t_BUFEN

10

Accuracy of V_REFINTstored in the

VREFINT_Factory_CONV byte⁽⁴⁾

ACC_VREFINT

STAB_VREFINT

5

mV

Stability of V_REFINTover temperature -40 °C ≤T_A≤ 125 °C

Stability of V_REFINTover temperature 0 °C ≤T_A≤ 50 °C

20

50

20

ppm/°C

ppm

STAB_VREFINTStability of V_REFINTafter 1000 hours

TBD

1. Guaranteed by design, not tested in production

2. Defined when ADC output reaches its final value 1/2LSB

3. To guaranty less than 1% V_REFOUTdeviation

4. Measured at V_DD= 3 V 10 mV. This value takes into account V_DDaccuracy and ADC conversion accuracy.

Doc ID 17943 Rev 1

103/122

Electrical parameters

STM8L15xx8, STM8L15xR6

9.3.10

Temperature sensor

Based on characterization results, not tested in production, unless otherwise specified.

Table 45. TS characteristics

Symbol

Parameter

Min

Typ

Max.

Unit

Sensor reference voltage at 90°C 5 °C,

V₉₀

0.580

0.597

0.614

V

(1)

T_L

V_SENSORlinearity with temperature

Average slope

1

1.62

3.4

2

1.65

6

°C

mV/°C

µA

Avg_slope⁽²⁾

1.59

(2)

IDD_(TEMP)

Consumption

(2)

T_START

Temperature sensor startup time ⁽³⁾

10

µs

ADC sampling time when reading the

temperature sensor

(2)

T_{S_TEMP}

5

10

µs

1. Measured at V_DD= 3 V 10 mV. The 8 LSB of the V₉₀ADC conversion result are stored in the

TS_Factory_CONV_V90 byte.

2. Guaranteed by Design, not tested in production.

3. Defined for ADC output reaching its final value 1/2LSB.

9.3.11

Comparator characteristics

Data guaranteed by design, not tested in production.

Table 46. Comparator 1 characteristics

Symbol

Parameter

Analog supply voltage

Min

Typ

Max

Unit

V_DDA

1.65

-40

300

7.5

3.6

125

V

T_A

R₄₀₀

R₁₀

V_IN

Temperature range

R₄₀₀value

°C

kΩ

V

400

10

500

R₁₀value

12.5

V_DDA

Comparator input voltage range

0.6

Internal reference voltage ⁽¹⁾

Startup time after enable

Propagation delay⁽²⁾

V_REFINT

t_START

1.202

1.225

1.242

V

7

3

10

µs

t_d

V_offset

I_CMP1

Comparator offset error

Consumption⁽³⁾

10

mV

nA

160

260

1. Based on characterization results.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

104/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Data guaranteed by design, not tested in production.

Table 47. Comparator 2 characteristics

Electrical parameters

Symbol

Parameter

Analog supply voltage

Min

Typ

Max

Unit

V_DDA

1.65

-40

0

3.6

125

V

°C

V

T_A

Temperature range

V_IN

V_DDA

Comparator input voltage range

Startup time after enable in fast mode

Startup time after enable in slow mode

Propagation delay in fast mode⁽¹⁾

Propagation delay in slow mode⁽¹⁾

Comparator offset error

20

30

2.5

6

µs

mV

µA

t_START

t_df

t_ds

V_offset

10

5

I_DD(CMP2F)Consumption in fast mode

I_DD(CMP2S)Consumption in slow mode

2

1. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-

inverting input set to the reference.

9.3.12

12-bit DAC characteristics

Data guaranteed by design, not tested in production.

Table 48. DAC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDA

T_A

Analog supply voltage

Temperature range

1.8

-40

3.6

125

550

700

360

V

°C

Middle code

370

500

140

(1)

DAC supply current

µA

I_DD(DAC)

Worst code

I_VREF+

R_L

Current on V_REF+supply

Resistive load^{(2) (3)}

Output impedance

Capacitive load⁽⁴⁾

µA

kΩ

pF

V

DACOUT buffer ON

DACOUT buffer OFF

5

R_O

8

10

50

C_L

DACOUT buffer ON

DACOUT buffer OFF

0.2

0

V_REF+-0.2

V_REF+-1 LSB

DAC_OUT DAC_OUT voltage⁽⁵⁾

V

Settling time (full scale: for a 12-

bit input code transition between

the lowest and the highest input

codes when DAC_OUT reaches

the final value 1LSB)

R_L≥5 kΩ, C_L≤ 50 pF

t_settling

7

12

1

µs

Max frequency for a correct

DAC_OUT (@95%) change when

small variation of the input code

(from code i to i+1LSB).

R_L≥ 5 kΩ, C_L≤50 pF

Update rate

Msps

Doc ID 17943 Rev 1

105/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Table 48. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Wakeup time from OFF state.

t_WAKEUPInput code between lowest and

highest possible codes.

R_L≥5 kΩ, C_L≤50 pF

9

15

µs

Power supply rejection ratio (to

PSRR+

R_L≥ 5 kΩ, C_L≤50 pF

-60

-35

dB

VDDA) (static DC measurement)

1. Includes supply current on V_DDAand V_REF+

2. Resistive load between DACOUT and GNDA

3. Output on PF0 (48-pin package only)

4. Capacitive load at DACOUT pin

5. It gives the output excursion of the DAC

Data based on characterization results, not tested in production.

Table 49. DAC accuracy

Symbol

Parameter

Conditions

Typ

Max

Unit

R_L≥5 kΩ, C ≤50 pF

DACOUT buffer ON⁽²⁾

L

1.5

3

DNL

Differential non linearity⁽¹⁾

No load

DACOUT buffer OFF

1.5

2

3

R_L≥5 kΩ, C ≤ 50 pF

L

4

DACOUT buffer ON⁽²⁾

Integral non linearity⁽³⁾

12-bit

LSB

INL

No load

DACOUT buffer OFF

2

4

R_L≥5 kΩ, C ≤ 50 pF

DACOUT buffer ON⁽²⁾

L

10

25

Offset

Offset1

Offset error⁽⁴⁾

No load

DACOUT buffer OFF

5

8

5

Offset error at Code 1 ⁽⁵⁾

Gain error

DACOUT buffer OFF

1.5

R_L≥5 kΩ, C ≤ 50 pF

L

0.2

0.3

12

8

0.5

30

DACOUT buffer ON⁽²⁾

Gain error

%

No load

DACOUT buffer OFF

R_L≥5 kΩ, C ≤ 50 pF

L

DACOUT buffer ON⁽²⁾

12-bit

LSB

TUE

Total unadjusted error

No load

DACOUT buffer OFF

12

1. Difference between two consecutive codes - 1 LSB.

2. For 48-pin packages only. For 28-pin and 32-pin packages, DAC output buffer must be kept off and no load must be

applied.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.

4. Difference between measured value and ideal value = V_REF/2.

106/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

5. Difference between measured value and ideal value Code 1.

(1)

Table 50. DAC output on PB4-PB5-PB6

Symbol

Parameter

Conditions

Max

1.4

1.6

3.2

8.2

Unit

2.7 V < V_DD< 3.6 V

2.4 V < V_DD< 3.6 V

2.0 V < V_DD< 3.6 V

1.8 V < V_DD< 3.6 V

Internal resistance

between DAC output and

PB4-PB5-PB6 output

R_int

kΩ

1. 32 or 28-pin packages only. The DAC channel can be routed either on PB4, PB5 or PB6 using the routing

interface I/O switch registers.

12-bit ADC1 characteristics

Table 51. ADC1 characteristics

Parameter ⁽¹⁾

Min ⁽¹⁾

1.8

Typ⁽¹⁾

Max⁽¹⁾

Symbol

Conditions

Unit

V_DDA

Analog supply voltage

3.6

V

2.4 V ≤V_DDA≤ 3.6 V

1.8 V≤V_DDA≤ 2.4 V

V_DDA

2.4

Reference supply

voltage

V_REF+

V_DDA

V_SSA

V_REF-

I_VDDA

Lower reference voltage

Current on the VDDA

input pin

1000

1450

µA

700

(peak)⁽²⁾

Current on the VREF+

input pin

I_VREF+

400

450

(average)⁽²⁾

Conversion voltage

range

0⁽³⁾

-40

V_AIN

T_A

V_REF+

125

Temperature range

°C

on PF0 fast channel

on all other channels

on PF0 fast channel

on all other channels

External resistance on

V_AIN

50⁽⁴⁾

kΩ

R_AIN

Internal sample and

hold capacitor

C_ADC

16

pF

2.4 V≤V_DDA≤3.6 V

without zooming

0.320

16

8

MHz

ADC sampling clock

frequency

f_ADC

1.8 V≤V_DDA≤2.4 V

with zooming

Doc ID 17943 Rev 1

107/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Unit

Table 51. ADC1 characteristics (continued)

Parameter ⁽¹⁾

Min ⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Symbol

Conditions

V

_AINon PF0 fast

1⁽⁴⁾⁽⁵⁾

MHz

kHz

channel

f_CONV

12-bit conversion rate

V_AINon all other

channels

760⁽⁴⁾⁽⁵⁾

External trigger

frequency

f_TRIG

t_LAT

t_conv

3.5

1/f_ADC

External trigger latency

1/f_SYSCLK

V_AINon PF0 fast

channel

V_DDA< 2.4 V

0.43⁽⁴⁾⁽⁵⁾

µs

V_AINon PF0 fast

channel

0.22⁽⁴⁾⁽⁵⁾

t_S

Sampling time

2.4 V ≤V_DDA≤ 3.6 V

V_AINon slow channels

V_DDA< 2.4 V

0.86⁽⁴⁾⁽⁵⁾

0.41⁽⁴⁾⁽⁵⁾

µs

V_AINon slow channels

2.4 V ≤V_DDA≤ 3.6 V

12 + t_S

1⁽⁴⁾

1/f_ADC

µs

t_conv

12-bit conversion time

16 MHz

Wakeup time from OFF

state

t_WKUP

3

µs

s

Time before a new

conversion

(6)

∞

t_IDLE

Internal reference

voltage startup time

refer to

Table 44

t_VREFINT

ms

1. Data guaranteed by design, not tested in production.

2. The current consumption through V_REFis composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at

1Msps

3.

V_REF-or V_DDAmust be tied to ground.

4. Minimum sampling and conversion time is reached for maximum Rext = 0.5 kΩ..

5. Value obtained for continuous conversion on fast channel.

6. The time between 2 conversions, or between ADC ON and the first conversion must be lower than t_IDLE.

108/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

Table 52. ADC1 accuracy with V

= 3.3 V to 2.5 V

Conditions

DDA

Max⁽¹⁾

Unit

Symbol

Parameter

Typ

f

_ADC= 16 MHz

1

TBD

DNL

Differential non linearity f_ADC= 8 MHz

f_ADC= 4 MHz

1

f

_ADC= 16 MHz

1.2

2.2

1.8

1.5

1

INL

TUE

Integral non linearity

Total unadjusted error

Offset error

f_ADC= 8 MHz

f_ADC= 4 MHz

TBD

LSB

f

_ADC= 16 MHz

f_ADC= 8 MHz

f_ADC= 4 MHz

f

_ADC= 16 MHz

Offset

Gain

f_ADC= 8 MHz

f

_ADC= 4 MHz

_ADC= 16 MHz

0.7

LSB

Gain error

f_ADC= 8 MHz

_ADC= 4 MHz

1

TBD

f

1. Data based on characterization, not tested in production.

Table 53. ADC1 accuracy with V

Symbol

= 2.4 V to 3.6 V

Parameter

DDA

Max⁽¹⁾

Typ

Unit

DNL

INL

Differential non linearity

Integral non linearity

1

TBD

LSB

1.7

TUE

Offset

Gain

2

1

TBD

LSB

Total unadjusted error

Offset error

Gain error

1.5

1. Data based on characterization, not tested in production.

+

Table 54. ADC1 accuracy with V

Symbol

= V

= 1.8 V to 2.4 V

DDA

REF

Max⁽¹⁾

Parameter

Typ

Unit

DNL

INL

Differential non linearity

Integral non linearity

1

2

3

2

TBD

LSB

TUE

Offset

Gain

Total unadjusted error

Offset error

Gain error

1. Data based on characterization, not tested in production.

Doc ID 17943 Rev 1

109/122

Electrical parameters

Figure 34. ADC1 accuracy characteristics

STM8L15xx8, STM8L15xR6

V_REF+

V_DDA

4096

[1LSB_IDEAL

=

(or

depending on package)]

4096

E_G

(1) Example of an actual transfer curve

(2) The ideal transfer curve

4095

4094

4093

(3) End point correlation line

(2)

E_T=Total Unadjusted Error: maximum deviation

E_T

between the actual and the ideal transfer curves.

(3)

7

6

5

4

3

2

1

E_O=Offset Error: deviation between the first actual

transition and the first ideal one.

(1)

E_G=Gain Error: deviation between the last ideal

transition and the last actual one.

E_O

E_L

E_D=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E_L=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

E_D

1 LSB_IDEAL

0

1

2

3

4

5

6

7

4093 4094 4095 4096

V_DDA

V_SSA

ai14395b

Figure 35. Typical connection diagram using the ADC

34-ꢃ,ꢀꢍXXX

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AIꢀꢁꢐꢒꢐC

1. Refer to Table 51 for the values of R_AINand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 36 or Figure 37,

depending on whether V

is connected to V

or not. Good quality ceramic 10 nF

REF+

DDA

capacitors should be used. They should be placed as close as possible to the chip.

110/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Electrical parameters

Figure 36. Power supply and reference decoupling (V

not connected to V

)

DDA

REF+

STM8L

V

REF+

DDA

1 µF // 10 nF

V

1 µF // 10 nF

/V

SSA REF-

ai17031

Figure 37. Power supply and reference decoupling (V

connected to V

)

REF+

DDA

STM8L

V

/V

REF+ DDA

1 µF // 10 nF

V

/V

REF– SSA

ai17032

9.3.13

EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Doc ID 17943 Rev 1

111/122

Electrical parameters

STM8L15xx8, STM8L15xR6

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),

the product is stressed by two electromagnetic events until a failure occurs (indicated by the

LEDs).

●

ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000 standard.

●

FTB: A burst of fast transient voltage (positive and negative) is applied to V and V

DD

SS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms

with the IEC 61000 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Table 55. EMS data

Level/

Class

Symbol

Parameter

Conditions

V_DD= 3.3 V, T_A= +25 °C,

Voltage limits to be applied on

V_FESD

any I/O pin to induce a functional f_CPU= 16 MHz,

TBD

disturbance

conforms to IEC 61000

Fast transient voltage burst limits

to be applied through 100 pF on

V_DDand V_SSpins to induce a

V_DD= 3.3 V, T_A= +25 °C,

f_CPU= 16 MHz,

conforms to IEC 61000

TBD

Using HSI

Using HSE

V_EFTB

functional disturbance

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O

ports), the product is monitored in terms of emission. This emission test is in line with the

norm IEC61967-2 which specifies the board and the loading of each pin.

112/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Table 56. EMI data

Electrical parameters

(1)

Max vs.

Unit

16 MHz

Monitored

frequency band

Symbol

Parameter

Conditions

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

TBD

V_DD= 3.6 V,

T_A= +25 °C,

LQFP32

conforming to

IEC61967-2

TBD

dBμV

S_EMI

Peak level

-

1. Not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models

can be simulated: human body model and charge device model. This test conforms to the

JESD22-A114A/A115A standard.

Table 57. ESD absolute maximum ratings

Maximum

Symbol

Ratings

Conditions

Unit

value ⁽¹⁾

Electrostatic discharge voltage

(human body model)

V_ESD(HBM)

TBD

T_A= +25 °C

V

Electrostatic discharge voltage

(charge device model)

V_ESD(CDM)

TBD

1. Data based on characterization results, not tested in production.

Static latch-up

●

LU: 3 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

Table 58. Electrical sensitivities

Symbol

Parameter

Class

LU

Static latch-up class

II

Doc ID 17943 Rev 1

113/122

Electrical parameters

STM8L15xx8, STM8L15xR6

9.4

Thermal characteristics

The maximum chip junction temperature (T

) must never exceed the values given in

Jmax

Table 17: General operating conditions on page 70.

The maximum chip-junction temperature, T

the following equation:

, in degree Celsius, may be calculated using

Jmax

T

= T

+ (P

x Θ )

Dmax JA

Jmax

Amax

Where:

●

T

is the maximum ambient temperature in °C

is the package junction-to-ambient thermal resistance in ° C/W

Amax

Θ

JA

P

is the sum of P

and P

(P

= P

+ P

)

I/Omax

Dmax

INTmax

I/Omax

Dmax

INTmax

P

is the product of I and V , expressed in Watts. This is the maximum chip

INTmax

DD

internal power.

●

P

represents the maximum power dissipation on output pins

I/Omax

Where:

P

= Σ (V *I ) + Σ((V -V )*I ),

I/Omax

OL OL

DD OH

OH

taking into account the actual V /I and V /I of the I/Os at low and high level in

OL OL

OH OH

the application.

(1)

Table 59. Thermal characteristics

Symbol

Parameter

Value

Unit

Thermal resistance junction-ambient

LQFP 48- 7 x 7 mm

Θ

65

°C/W

JA

Thermal resistance junction-ambient

UFQFPN 48- 7 x 7mm

Θ

32

48

38

°C/W

JA

Thermal resistance junction-ambient

LQFP 64- 10 x 10 mm

Θ

JA

Thermal resistance junction-ambient

LQFP 80- 14 x 14 mm

Θ

JA

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

114/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Package characteristics

10

Package characteristics

10.1

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Doc ID 17943 Rev 1

115/122

Package characteristics

STM8L15xx8, STM8L15xR6

Figure 38. 80-pin low profile quad flat package (14 x 14 mm)

D

ccc

C

D1

D3

A

A2

41

60

40

61

b

L1

E3 E1

E

L

A1

K

80

Pin 1

identification

1

c

1S_ME

Table 60. 80-pin low profile quad flat package mechanical data

mm

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

-

0.050

1.350

0.220

0.090

15.800

13.800

-

1.600

0.150

1.450

0.380

0.200

16.200

14.200

-

0.0630

0.0059

0.0571

0.0150

0.0079

0.6378

0.5591

-

0.0020

0.0531

0.0087

0.0035

0.6220

0.5433

-

1.400

0.320

-

0.0551

0.0126

-

c

D

16.000

14.000

12.350

16.000

14.000

12.350

0.650

0.600

1.000

3.5°

0.6299

0.5512

0.4862

0.6299

0.5512

0.4862

0.0256

0.0236

0.0394

3.5°

D1

D3

E

15.800

13.800

-

16.200

14.200

-

0.6220

0.5433

-

0.6378

0.5591

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

0.0295

-

L1

k

0.0°

-

7.0°

0.0°

-

7.0°

ccc

-

0.100

-

0.0039

1. Values in inches are converted from mm and rounded to four decimal places.

116/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Package characteristics

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 40. Recommended

(1)

(1)(2)

flat package outline

footprint

D

ccc

C

D1

A

A2

48

33

D3

33

48

0.3

49

32

0.5

32

49

12.7

10.3

b

L1

10.3

64

17

E3 E1

E

1.2

1

16

L

7.8

A1

12.7

64

17

ai14909

1

ntification

1

16

c

5W ME

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 61. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

b

1.60

0.15

1.45

0.27

0.20

0.0630

0.0059

0.0571

0.0106

0.0079

0.05

1.35

0.17

0.09

0.0020

0.0531

0.0067

0.0035

1.40

0.22

0.0551

0.0087

c

D

12.00

10.00

12.00

10.00

0.50

0.4724

0.3937

0.4724

0.3937

0.0197

3.5°

D1

E

E1

e

θ

0°

3.5°

7°

0°

7°

L

0.45

0.60

0.75

0.0177

0.0236

0.0394

0.0295

L1

1.00

Number of pins

N

64

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 17943 Rev 1

117/122

Package characteristics

STM8L15xx8, STM8L15xR6

Figure 41. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat Figure 42. Recommended

(1)

(1)(2)

package outline

footprint

D

ccc

C

D1

D3

25

A

A2

0.50

1.20

36

0.30

36

25

24

37

24

L1

0.20

7.30

b

9.70 5.80

E3

E1

E

7.30

48

13

12

1

48

L

1.20

13

A1

5.80

9.70

n 1

entification

1

12

c

ai14911b

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 62. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data

millimeters

inches⁽¹⁾

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

1.600

0.150

1.450

0.270

0.200

9.200

7.200

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

0.050

1.350

0.170

0.090

8.800

6.800

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

1.400

0.220

0.0551

0.0087

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

9.200

7.200

0.3465

0.2677

0.3622

0.2835

E1

E3

e

L

0.450

0°

0.750

7°

0.0177

0°

0.0295

7°

L1

k

ccc

0.080

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

118/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Package characteristics

Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package Figure 44. Recommended footprint

(1)(2)(3)

(1)

outline

(dimensions in mm)

$ꢂ

,

B

ꢂꢆ

ꢀꢉ

7.30

ꢂꢍ

ꢀꢂ

,

48

37

1

36

6.20

%ꢂ

0.20

%

B

E

7.30

6.20

5.60

5.80

ꢀ

ꢉꢅ

5.60

5.80

0.30

0.55

ꢉꢁ

ꢆꢃ

E

12

25

$

13

24

!ꢉ

!ꢀ

!

0.75

0.50

ai15697

#

!ꢂ

3EATING

PLANE

!ꢐ"ꢒ?-%

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this

back-side pad to PCB ground.

Table 63. UFQFPN48 – ultra thin fine pitch quad flat pack no-lead 7 × 7 mm, 0.5 mm

pitch package mechanical data

millimeters

Min

inches⁽¹⁾

Symbol

Typ

Max

Typ

Min

Max

A

0.550

0.020

0.530

0.150

0.230

7.000

4.700

7.000

4.700

0.500

0.400

0.500

0

0.600

0.050

0.550

0.160

0.300

7.150

5.250

7.150

5.250

0.550

0.500

0.02170

0.0008

0.0209

0.0059

0.0091

0.2756

0.1850

0.2756

0.1850

0.0197

0.0157

0.01970

0

0.0236

0.0020

0.0217

0.0063

0.0118

0.2815

0.2067

0.2815

0.2067

0.0217

0.0197

A1

A2

A3

b

0.500

0.140

0.180

6.850

2.250

6.850

2.250

0.450

0.300

0.080

0.0197

0.0055

0.0071

0.2697

0.0886

0.2697

0.0886

0.0177

0.0118

0.0031

D

D2

E

E2

e

L

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 17943 Rev 1

119/122

Ordering information scheme

STM8L15xx8, STM8L15xR6

11

Ordering information scheme

Table 64. Ordering information scheme

Example:

STM8

L

152

C

8

T

6

D

Device family

STM8 microcontroller

Product type

L = Low power

Device subfamily

151: Devices without LCD

152: Devices with LCD

Pin count

C = 48 pins

R = 64 pins

M = 80 pins

Program memory size

8 = 64 Kbytes of Flash memory

6 = 32 Kbytes

Package

T = LQFP

U= UFQFPN

Temperature range

3 = Industrial temperature range, – 40 to 125 °C

6 = Industrial temperature range, – 40 to 85 °C

Option

Blank = V_DDrange from 1.8 to 3.6 V and BOR enabled

D = V_DDrange from 1.65 to 3.6 V and BOR disabled

For a list of available options (e.g. memory size, package) and orderable part numbers or for

further information on any aspect of this device, please go to www.st.com or contact the ST

Sales Office nearest to you.

120/122

Doc ID 17943 Rev 1

STM8L15xx8, STM8L15xR6

Revision history

12

Revision history

Table 65. Document revision history

Date

Revision

Changes

13-Sep-2010

1

Initial release.

Doc ID 17943 Rev 1

121/122

STM8L15xx8, STM8L15xR6

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122/122

Doc ID 17943 Rev 1


型号：	STM8L152R6T3STM8L152R6T3
厂家：	ST
描述：	8-BIT, FLASH, 16MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件：	总122页 (文件大小：1190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STM8L152R6T3STM8L152R6T3 [STMICROELECTRONICS]

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