STR731FV0T7 [STMICROELECTRONICS]
ARM7TDMI 32-BIT MCU WITH FLASH, 3x CAN, 4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES; ARM7TDMI的32位MCU配备闪光灯, 3倍CAN , 4个UART , 20定时器, ADC , 12 COMM 。 INTERFACES型号: | STR731FV0T7 |
厂家: | ST |
描述: | ARM7TDMI 32-BIT MCU WITH FLASH, 3x CAN, 4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES |
文件: | 总22页 (文件大小:383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
STR73xF
ARM7TDMI™ 32-BIT MCU WITH FLASH, 3x CAN,
4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES
DATA BRIEF
■ Core
– ARM7TDMI 32-bit RISC CPU
– 32 MIPS @ 36 MHz
■ Temperature Range
– Operating temperature range -40 to 105 °C
■ Memories
TQFP100 14 x 14
– Up to 256 Kbytes FLASH program memory
(10,000 cycles endurance, data retention 20
years at 55°C)
TQFP144
20 x 20
– 16 Kbytes RAM
LFBGA144 10 x 10 x 1.7
■ Clock, Reset and Supply Management
– 4.5 - 5.5V application supply and I/O interface
– Embedded 1.8V regulator for core supply
■ DMA
– 4 DMA controllers with 4 channels each
■ Timers
– Embedded oscillator running from external
4-8MHz crystal or ceramic resonator
– 16-bit watchdog timer (WDG)
– Up to 36 MHz CPU freq. with internal PLL
– 6/10 16-bit timers (TIM) each with: 2 input
captures, 2 output compares, PWM and pulse
counter modes
– Internal RC oscillator 32kHz or 2MHz soft-
ware configurable for fast startup and backup
clock
– 6 16-bit PWM modules (PWM)
– Realtime Clock for clock-calendar function
– 3 16-bit timebase timers with 8-bit prescalers
■ 12 Communications Interfaces
– Wakeup Timer driven by internal RC for wake-
up from STOP mode
2
– 5 power saving modes: SLOW, WAIT,
LPWAIT, STOP and HALT modes
■ Nested interrupt controller
– 2 I C interfaces
– 4 UART asynchronous serial communications
interfaces
– Fast interrupt handling with multiple vectors
– 3 BSPI synchronous serial interfaces
– Up to 3 CAN interfaces (2.0B Active)
■ 10-bit A/D Converter
– 12/16 channels
– Conversion time: min 3µs, range: 0 to 5V
■ Development Tools Support
– 64 maskable IRQ with 64 vectors and
16 priority levels
– 2 maskable FIQ sources
– 16 external interrupts and up to 32 wake up
lines
■ Up to 112 I/O ports
– JTAG interface
– 72/112 multifunctional bidirectional I/O lines
Table 1. Device Summary
Features
FLASH memory - bytes
STR730FZx
128K 256K
16K
STR735FZx
128K 256K
STR731FVx
STR736FVx
64K
128K
256K
16K
64K
128K
256K
RAM - bytes
6 TIM Timers, 72 I/Os, 18 Wake-Up lines,
12 ADC channels
10 TIM Timers, 112 I/Os, 32
Wake-Up lines, 16 ADC channels
Peripheral Functions
CAN Peripherals
3
0
3
0
Operating Voltage
Operating Temperature
4.5 to 5.5V (optional 1.8V for core)
-40 to +105°C
T=TQFP144 20 x 20
H=LFBGA144 10 x10
Packages
T=TQFP100 14x14
Rev. 1
July 2005
1/22
This is preliminary information on a new product now in development. Details are subject to change without notice.
1
STR73xF Data Brief
1 INTRODUCTION
This Data Brief provides the STR73xF feature summary, pin description and ordering
Information.
For complete information on the Mechanical and Electrical Device Characteristics please refer
to the Preliminary Datasheet.
For complete information on the STR73xF Microcontroller memory, registers and peripherals.
please refer to the STR73x Reference Manual.
For information on programming, erasing and protection of the internal Flash memory please
refer to the STR7 Flash Programming Reference Manual
For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference
Manual.
1.1 Overview
‚
ARM core with embedded Flash & RAM
™
STR73xF family combines the high performance ARM7TDMI CPU with an extensive range
of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed
single voltage FLASH memory and high-speed RAM. The STR73xF family has an embedded
ARM core and is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs. The range of
development packages includes third-party solutions that come complete with a graphical
development environment and an in-circuit emulator/programmer featuring a JTAG application
interface. These support a range of embedded operating systems (OS), while several
royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
Figure 1 shows the general block diagram of the device family.
Package Choice: Reduced Pin-Count TQFP100 or Feature-Rich 144-pin TQFP or
LFBGA
The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have
the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer
to the Device Summary on Page 1 for a comparison of the I/Os available on each package.
The family includes versions with and without CAN.
2/22
1
STR73xF Data Brief
High Speed Flash Memory
The Flash program memory is organized in 32-bit wide memory cells which can be used for
storing both code and data constants. It is accessed by CPU with zero wait states @ 36 MHz.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years at
55°C.
IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a mi-
crocontroller using JTAG protocol while the device is mounted on the user application board.
The Flash memory can be protected against different types of unwanted access (read/write/
erase). There are two types of protection:
•
•
Sector Write Protection
Flash Debug Protection (locks JTAG access)
Flexible Power Management
To minimize power consumption, you can program the STR73xF to switch to SLOW, WAIT
LPWAIT, STOP or HALT modes depending on the current system activity in the application.
Flexible Clock Control
Two clock sources are used to drive the microcontroller, a main clock driven by an external
crystal or ceramic resonator and an internal backup RC oscillator that operates at 2MHz or 32
kHz. The embedded PLL allows the internal system clock (up to 36 MHz) to be generated
from a main clock frequency of 10 MHz or less. The PLL output frequency can be
programmed using a wide selection of multipliers and dividers.
Voltage Regulators
The STR73xF requires an external 4.5 to 5.5V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply needed by the core and peripherals. The
main VR is switched off and the Low Power VR switched on when the application puts the
STR73xF in Low Power Wait (LPWAIT) mode.
3/22
STR73xF Data Brief
Low Voltage Detectors
The voltage regulator and Flash modules each have an embedded LVD that monitors the
internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the
STR73xF.
Note: An external power-on reset must be provided ensure the microcontroller starts-up
correctly.
On-Chip Peripherals
CAN Interfaces
The three CAN modules are compliant with the CAN specification V2.0 part B (active). The bit
rate can be programmed up to 1 MBaud. These are not available in the STR735 and STR736.
DMA
4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to
memory and memory to peripheral transfers. The DMA requests are connected to TIM timers,
BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be configured to be triggered by a
software request, independently from any peripheral activity.
16-bit Timers (TIM)
Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit
prescaler, up to two input capture/output compare functions, a pulse counter function, and a
PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12 in
100-pin devices) when added with the PWM modules (see next paragraph).
PWM Modules (PWM)
The six 16-bit PWM modules have independently programmable periods and duty-cycles,
with 5+3 bit prescaler factor.
Timebase Timers (TB)
The three 16-bit Timebase Timers with 8-bit prescaler for general purpose time triggering
operations.
Realtime Clock (RTC)
The RTC provides a set of continuously running counters driven by separate clock signal
derived from the main oscillator. The RTC can be used as a general timebase or clock/
calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps running,
powered by the low power voltage regulator.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 625K baud.
4/22
STR73xF Data Brief
Buffered Serial Peripheral Interfaces (BSPI)
Each of the three BSPIs allow full duplex, synchronous communications with external devices,
master or slave communication at up 6 Mb/s (@36 MHz System Clock).
2
I C Interfaces
2
2
The two I C Interfaces provide multi-master and slave functions, support normal and fast I C
mode (400 kHz) and 7 or 10-bit addressing modes.
A/D Converter
The 10-bit Analog to Digital Converter, converts up to 16 channels in single-shot or
continuous conversion modes (12 channels in 100-pin devices). The minimum conversion
time is 3us.
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures and
ensures recovery by generating a reset.
I/O Ports
Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose input/
output or Alternate Function.
External Interrupts and Wake-Up Lines
16 external interrupts lines are available for application use. In addition, up to 32 external
Wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to
wake-up the application from STOP mode.
5/22
STR73xF Data Brief
Figure 1. STR730F/STR735F Block Diagram
RSTIN
PRCCU/PLL
FLASH
M0
M1
TEST
Program Memory
64/128/256K
ARM7TDMI
CPU
RAM
16K
JTDI
JTCK
JTMS
JTRST
JTDO
JTAG
APB
BRIDGE 0
V18
VDD
VSS
POWER SUPPLY
VREG
APB
BRIDGE 1
VDDA
VSSA
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
4 AF
32 AF
8 AF
I2C0-1
OSC
RTC
WAKEUP/INT (WIU)
UART0, 1, 2, 3
INTERRUPT CTL (EIC)
A/D CONVERTER (ADC)
16 AF
12 AF
TIMEBASE TIMER
(TB) 0-2
TIMER (TIM) 2-4
WAKEUP TIMER
(WUT)
12 AF
6 AF
BSPI 0-2
CAN 0-2*
PWM 0-5
8 AF
TIMER (TIM) 0-1
TIMER (TIM) 5-9
20 AF
6 AF
122 ports
GPIO PORTS 0-6
AF: alternate function on I/O port pin
*CAN peripherals not available on STR735F.
6/22
STR73xF Data Brief
Figure 2. STR731F/STR736 Device Block Diagram
RSTIN
PRCCU/PLL
FLASH
M0
M1
TEST
Program Memory
64/128/256K
ARM7TDMI
CPU
RAM
16K
JTDI
JTCK
JTMS
JTRST
JTDO
JTAG
APB
BRIDGE 0
V18
VDD
VSS
POWER SUPPLY
VREG
APB
BRIDGE 1
VDDA
VSSA
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
I2C0-1
CLOCK MGT (CMU)
XTAL1
XTAL2
4 AF
18 AF
8 AF
OSC
RTC
WAKEUP/INT (WIU)
UART0, 1, 2, 3
INTERRUPT CTL (EIC)
A/D CONVERTER (ADC)
12 AF
12 AF
TIMEBASE TIMER
(TB) 0-2
TIMER (TIM) 2-4
WAKEUP TIMER
(WUT)
12 AF
6 AF
BSPI 0-2
CAN 0-2*
PWM 0-5
8 AF
4 AF
TIMER (TIM) 0-1
TIMER (TIM) 5
6 AF
72 ports
GPIO PORTS 0-6
AF: alternate function on I/O port pin
*CAN peripherals not available on STR736F.
7/22
STR73xF Data Brief
1.2 Related Documentation
Available from www.arm.com:
ARM7TDMI Technical Reference Manual
Available from http://www.st.com:
STR7 Flash Programming Reference Manual
STR73x Software Library User Manual
For a list of related application notes refer to http://www.st.com.
8/22
STR73xF Data Brief
1.3 Pin Description
1.3.1
STR730F/STR735F (TQFP144)
Figure 3. STR730F/STR735F Pin Configuration (top view)
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
P4.14 / SS1
P4.13 / ICAPB9
P4.12 / ICAPA9 / WUP21
P4.11 / OCMPB8
P4.10 / ICAPA6 / WUP20
P4.9 / ICAPB6
V
SS
V
DD
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
P4.8 / OCMPA8
P4.7 / SDA1
9
P4.6 / SCL1 / WUP19
P4.5 / CAN2RX / WUP18
P4.4 / CAN2TX
P4.3 / ICAPB8 / WUP27
P4.2 / ICAPA8 / WUP26
P4.1 / ICAPB7 / WUP25
P4.0 / ICAPA7 / WUP24
ICAPB5 / P0.7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
OCMPA6 / P0.8
OCMPB6 / P0.9
OCMPA7 / P0.10
OCMPB7 / P0.11
V
DD
V
V
V
SS
DD
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
SS
JTDO
JTCK
JTMS
JTDI
STR730F/STR735F
JTRST
V
V
SS
ICAPA4 / P1.3
DD
V
P3.15 / AIN15 / INT5
P3.14 / AIN14 / INT4
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.11 / AIN11
P3.10 / AIN10
P3.9 / AIN9
P3.8 / AIN8
SS
V
DD
P1.4
P1.5
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
V
V
DDA
SSA
74
73
P3.7 / AIN7
P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
9/22
STR73xF Data Brief
1.3.2
STR730F/STR735F (LFBGA144)
Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
A1
Name
Ball
B1
Name
P0.4 / OCMPA5
P0.1 / OCMPA2
P6.15 / WUP9
Ball
C1
Name
P0.5 / OCMPB5
P0.2 / ICAPA2
P0.3 / ICAPB2
P6.14 / SSO
Ball
D1
Name
P0.0 / OCMPB2
P6.10 / WUP8
P6.9 / TDO0
V
SS
DD
A2
B2
C2
D2
V
A3
B3
C3
D3
P0.6 / ICAPA5
P0.7 /ICAPB5
A4
P6.12 / MOSI0
P6.6 / WUP6
B4
P6.13 / SCKO / WUP11
P6.7 / WUP7
C4
D4
A5
B5
C5
P6.8 / RDI0 / WUP10
P6.3 / WUP3
D5
P6.11 / MISO0
P6.4 / WUP4 /TDO3
VDD
A6
V
B6
P6.2 / WUP2 / RDI3
P5.14 / INT12
C6
D6
18
A7
P5.15 / INT13
P5.8 / INT6
B7
C7
V
D7
SS
A8
B8
P5.9 / INT7
C8
P5.10 / INT8 / RDI2
P5.4 / SS2
D8
P5.12 / INT10
A9
P5.2 / OCMPA9
P5.7 / MISO2
B9
P5.3 / OCMPB9
P5.0 / MOSI1
C9
D9
P5.5 / SCK2 / WUP23
P4.13 / ICAPB9
A10
A11
A12
B10
B11
B12
C10
C11
C12
P5.1 / MISO1
P4.14 / SS1
D10
P5.6 / MOSI2
P4.15 / SCK1 / WUP22
P4.8 / OCMPA8
D11 P4.12 / ICAPA9 / WUP21
P5.11 / TDO2 / INT9
P4.7 / SDA1
D12
P4.11 / OCMPB8
E1
E2
E3
E4
E5
E6
E7
E8
P0.8 / OCMPA6
P0.9 / OCMPB6
P0.10 / OCMPA7
P0.11 / OCMPB7
P0.12 / ICAPA3
P6.5 / WUP5
F1
F2
F3
F4
F5
F6
F7
F8
F9
V
G1
G2
G3
G4
G5
G6
G7
G8
G9
V
H1
H2
H3
V
DD
DD
SS
P0.13 / ICAPB3
P0.14 / OCMPB3
P0.15 / OCMPA3
P1.0 / OCMPA4
P1.1 / OCMPB4
P6.1 / WUP1
P1.2 / ICAPB4
P1.3 / ICAPA4
P1.8 / OCMPA0 / INT0
P1.9 / OCMPB0 / INT1
V
H4 P1.10 / ICAPB0 / WUP28
SS
P1.5
P2.11 / WUP17
P4.0 / ICAPA7 / WUP24
VDD
H5
H6
H7
H8
H9
XTAL2
P2.10 / WUP16
P2.15 / SDA 0
JTMS
P6.0 / WUP0
1)
P5.13 / INT11
P4.4 / CAN2TX
E9 P4.10 / ICAPA6 / WUP20
P4.3 / ICAPB8 / WUP27
VSS
VSS
10/22
STR73xF Data Brief
Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
E10
Name
Ball
F10
Name
Ball
Name
JTDO
Ball
Name
VDD
P4.9 / ICAPB6
P4.2 / ICAPA8 / WUP26 G10
P4.1 / ICAPB7 / WUP25 G11
H10
H11
E11
P4.6 / SCL1 / WUP19
F11
JTCK
P3.15 / AIN15 / INT5
P4.5 / WUP18 /
CAN2RX
E12
F12
JTDI
G12
nJTRST
H12
P3.14 / AIN14 / INT4
1)
1)
P1.14 / CAN0RX
WUP12
/
J1
P1.4
K1
K2
K3
P1.6 / OCMPB1
L1
L2
L3
P1.7 / OCMPA1
M1
M2
M3
1)
J2 P1.11 / ICAPA0 / WUP29
J3 P1.12 / ICAPA1 / WUP30
P1.13 / ICAPB1 / WUP31
P1.15 / CAN0TX
P2.0 / PWM0
P2.4 / PWM2
P2.5 / PWM3
1)
P2.1 / CAN1RX
WUP13
/
1)
J4
J5
P2.7 / PWM5
K4
K5
P2.6 / PWM4
M1
L4
L5
P2.3 / PWM1
RSTIN
M4
M5
P2.2 / CAN1TX
M0
V
DD
J6
P2.9 / RDI1 / WUP14
P2.14 / SCL 0 / WUP15
P3.1 / AIN1
K6
P2.8 / TDO1
P2.13 / INT15
P3.0 / AIN0
P3.4 / AIN4
L6
V
M6
V
SS
SS
J7
K7
L7
P2.12 / INT14
VBIAS
M7
XTAL1
TST
J8
K8
L8
M8
J9
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.9 / AIN9
K9
L9
P3.3 / AIN3
P3.5 / AIN5
P3.7 / AIN7
P3.10 / AIN10
M9
P3.2 / AIN2
J10
J11
J12
K10
K11
K12
V
L10
L11
L12
M10
M11
M12
V
DDA
SS
DD
V
V
SSA
P3.8 / AIN8
P3.11 / AIN11
P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
11/22
STR73xF Data Brief
1.3.3
STR731F/STR736F (TQFP100)
Figure 4. STR731F/STR736F Pin Configuration (top view)
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4.14 / SS1
P4.10 / ICAPB5 / WUP20
P4.7 / SDA1
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
P4.6 / SCL1 / WUP19
V
DD
V
SS
JTDO
JTCK
JTMS
JTDI
V
DD
9
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
OCMPB1 / P1.6
JTRST
V
SS
STR731F/STR736F
V
DD
P3.15 / AIN11 / INT5
P3.14 / AIN10 / INT4
P3.13 / AIN9 / INT3
P3.12 / AIN8 / INT2
P3.11 / AIN7
P3.10 / AIN6
P3.9 / AIN5
P3.8 / AIN4
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
V
DDA
V
SSA
P3.7 / AIN3
P3.6 / AIN2
Note 1: CAN alternate functions not available on STR736F.
12/22
STR73xF Data Brief
Legend / Abbreviations for Table 3:
Type: I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: T = TTL 0.8V / 2V with input trigger
T
C = CMOS 0.3V /0.7V with input trigger
T
DD
DD
Port and control configuration:
– Input:
pu/pd = with internal 100kΩ weak pull-up or pull down
– Output:
OD = open drain (logic level)
PP = push-pull
Interrupts:
INTx =external interrupt line
WUPx =Wake-Up interrupt line
The reset state of the I/O ports is input floating. To avoid excess power consumption, unused I/O ports
must be tied to ground.
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
1
2
3
4
5
6
7
8
9
A1
B2
C2
C3
D1
D2
B1
C1
D3
1
2
3
4
P0.0/OCMPB2 I/O
P0.1/OCMPA2 I/O
2mA X
X
X
X
X
Port 0.0 TIM2: Output Compare B output
Port 0.1 TIM2: Output Compare A output
Port 0.2 TIM2: Input Capture A input
Port 0.3 TIM2: Input Capture B input
Ground for digital I/O (5V)
T
T
T
T
T
T
T
T
2mA X
2mA X
2mA X
P0.2/ICAPA2
P0.3/ICAPB2
I/O
I/O
S
V
V
SS
DD
S
Supply voltage for digital I/O (5V)
5
6
7
P0.4/OCMPA5 I/O
P0.5/OCMPB5 I/O
2mA X
2mA X
2mA X
2mA X
2mA X
2mA X
X
X
X
X
X
X
Port 0.4 TIM5: Output Compare A output
Port 0.5 TIM5: Output Compare B output
Port 0.6 TIM5: Input Capture A input
Port 0.7 TIM5: Input Capture B input
Port 0.8 TIM6: Output Compare A output
Port 0.9 TIM6: Output Compare B output
T
T
T
T
T
T
T
T
T
T
T
T
P0.6/ICAPA5
P0.7/ICAPB5
I/O
I/O
10 D4
11 E1
12 E2
P0.8/OCMPA6 I/O
P0.9/OCMPB6 I/O
Port
13 E3
14 E4
P0.10/OCMPA7 I/O
P0.11/OCMPB7 I/O
2mA X
2mA X
X
X
TIM7: Output Compare A output
0.10
T
T
T
T
Port
TIM7: Output Compare B output
0.11
15 F1
16 G1
8
9
V
V
S
S
Supply voltage for digital I/O (5V)
Ground for digital I/O (5V)
DD
SS
Port
17 E5 10 P0.12/ICAPA3
18 F2 11 P0.13/ICAPB3
I/O
I/O
2mA X
2mA X
2mA X
X
X
X
TIM3: Input Capture A input
0.12
T
T
T
T
T
T
Port
TIM3: Input Capture B input
0.13
Port
19 F3 12 P0.14/OCMPB3 I/O
TIM3: Output Compare B output
0.14
13/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
Port
0.15
20 F4 13 P0.15/OCMPA3 I/O
2mA X
X
TIM3: Output Compare A output
T
T
21 F5 14 P1.0/OCMPA4 I/O
22 F6 15 P1.1/OCMPB4 I/O
2mA X
2mA X
2mA X
2mA X
X
X
X
X
Port 1.0 TIM4: Output Compare A output
Port 1.1 TIM4: Output Compare B output
Port 1.2 TIM4: Input Capture B input
Port 1.3 TIM4: Input Capture A input
Ground for digital I/O (5V)
T
T
T
T
T
T
T
T
23 G2 16 P1.2/ICAPB4
24 G3 17 P1.3/ICAPA4
I/O
I/O
S
25 G4
26 H1
27 J1
28 G5
V
V
SS
DD
S
Supply voltage for digital I/O (5V)
Port 1.4
P1.4
P1.5
I/O
I/O
2mA X
2mA X
X
X
X
X
X
X
T
T
T
T
T
T
T
T
T
T
T
T
Port 1.5
29 K1 18 P1.6/OCMPB1 I/O
30 L1 19 P1.7/OCMPA1 I/O
31 H2 20 P1.8/OCMPA0 I/O
32 H3 21 P1.9/OCMPB0 I/O
2mA X
Port 1.6 TIM1: Output Compare B output
Port 1.7 TIM1: Output Compare A output
Port 1.8 TIM0: Output Compare A output
Port 1.9 TIM0: Output Compare B output
2mA X
INT0 2mA X
INT1 2mA X
Port
33 H4 22 P1.10/ICAPB0
34 J2 23 P1.11/ICAPA0
35 J3 24 P1.12/ICAPA1
36 K2 25 P1.13/ICAPB1
I/O
I/O
I/O
I/O
WUP28 2mA X
WUP29 2mA X
WUP30 2mA X
WUP31 2mA X
WUP12 2mA X
2mA X
X
X
X
X
X
X
TIM0: Input Capture B input
1.10
T
T
T
T
T
T
T
T
T
T
T
T
Port
TIM0: Input Capture A input
1.11
Port
TIM1: Input Capture A input
1.12
Port
TIM1: Input Capture B input
1.13
Port
37 M1 26 P1.14/CAN0RX I/O
38 L2 27 P1.15/CAN0TX I/O
CAN0: Receive Data input
1.14
Port
CAN0: Transmit Data output
1.15
39 L3 28 P2.0/PWM0
40 K3 29 P2.1/CAN1RX
41 M4 30 P2.2/CAN1TX
42 L4 31 P2.3/PWM1
43 M2 32 P2.4/PWM2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
2mA X
WUP13 2mA X
2mA X
X
X
X
X
X
X
X
X
Port 2.0 PWM0: PWM output
Port 2.1 CAN1: Receive Data input
Port 2.2 CAN1: Transmit Data output
Port 2.3 PWM1: PWM output
Port 2.4 PWM2: PWM output
Port 2.5 PWM3: PWM output
Port 2.6 PWM4: PWM output
Port 2.7 PWM5: PWM output
BOOT: Mode selection 0 input
Reset input
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2mA X
2mA X
44 M3
45 K4
46 J4
P2.5/PWM3
P2.6/PWM4
P2.7/PWM5
2mA X
2mA X
2mA X
47 M5 33 M0
48 L5 34 RSTIN
49 K5 35 M1
pd
pu
pd
I
C
T
I
BOOT: Mode selection 1 input
Supply voltage for digital I/O (5V)
T
T
50 J5 36
V
S
DD
14/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
51 M6 37
V
S
I
Ground for digital I/O (5V)
SS
Oscillator amplifier circuit input and internal
clock generator input.
52 M7 38 XTAL1
53 H5 39 XTAL2
O
S
Oscillator amplifier circuit output.
Ground for digital I/O (5V)
54 L6 40
55 K6 41
V
SS
CAN2: Receive
Data input
P2.8/TDO1/
CAN2RX
UART1: Transmit
Data output
I/O
I/O
2mA X
X
X
Port 2.8
Port 2.9
T
T
T
T
(TQFP100 only)
CAN2: Transmit
Data output
(TQFP100 only)
P2.9/RDI1/
CAN2TX
UART1: Receive
Data input
56 J6 42
WUP14 2mA X
Port
2.10
57 H6
58 G6
59 L7
60 K7
P2.10
P2.11
P2.12
P2.13
I/O
I/O
I/O
I/O
I/O
WUP16 2mA X
WUP17 2mA X
INT14 2mA X
INT15 2mA X
WUP15 2mA X
2mA X
X
X
X
X
X
X
T
T
T
T
T
T
T
T
T
T
T
T
Port
2.11
Port
2.12
Port
2.13
Port
2.14
61 J7 43 P2.14/SCL0
I2C0:Serial Clock
I2C0:Serial Data
Port
2.15
62 H7 44 P2.15/SDA0
63 M8 45 Test
I/O
I
pd
Reserved pin. Must be tied to ground
Internal RC Oscillator bias. A 1.3MΩ external
resistor has to be connected to this pin when a
32kHZ RC oscillator frequency is used.
64 L8 46
V
S
BIAS
65 M10 47
66 M11 48
67 K8
V
V
S
Ground for digital I/O (5V)
SS
DD
S
Supply voltage for digital I/O (5V)
Port 3.0 ADC: Analog input 0
Port 3.1 ADC: Analog input 1
Port 3.2 ADC: Analog input 2
Port 3.3 ADC: Analog input 3
P3.0/AIN0
P3.1/AIN1
P3.2/AIN2
P3.3/AIN3
I/O
I/O
I/O
I/O
2mA X
2mA X
2mA X
2mA X
X
X
X
X
T
T
T
T
T
T
T
T
68 J8
69 M9
70 L9
ADC: Analog input 4
Port 3.4
71 K9 49 P3.4/AIN4
72 L10 50 P3.5/AIN5
73 M12 51 P3.6/AIN6
74 L11 52 P3.7/AIN7
I/O
I/O
I/O
I/O
2mA X
2mA X
2mA X
2mA X
X
X
X
X
T
T
T
T
T
T
T
T
(AIN0 in TQFP100)
ADC: Analog input 5
Port 3.5
(AIN1 in TQFP100)
ADC: Analog input 6
Port 3.6
(AIN2 in TQFP100)
ADC: Analog input 7
Port 3.7
(AIN3 in TQFP100)
15/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
75 K11 53
76 K10 54
V
V
S
S
Reference ground for A/D converter
Reference voltage for A/D converter
SSA
DDA
ADC: Analog input 8
Port 3.8
77 J12 55 P3.8/AIN8
78 J11 56 P3.9/AIN9
79 L12 57 P3.10/AIN10
80 K12 58 P3.11/AIN11
81 J10 59 P3.12/AIN12
82 J9 60 P3.13/AIN13
83 H12 61 P3.14/AIN14
84 H11 62 P3.15/AIN15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2mA X
X
X
X
X
X
X
X
X
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
(AIN4 in TQFP100)
ADC: Analog input 9
Port 3.9
2mA X
2mA X
(AIN5 in TQFP100)
Port
3.10
ADC: Analog input 10
(AIN6 in TQFP100)
Port
3.11
ADC: Analog input 11
(AIN7 in TQFP100)
2mA X
Port
3.12
ADC: Analog input 12
(AIN8 in TQFP100)
INT2 2mA X
INT3 2mA X
INT4 2mA X
INT5 2mA X
Port
3.13
ADC: Analog input 13
(AIN9 in TQFP100)
Port
3.14
ADC: Analog input 14
(AIN10 in TQFP100)
Port
3.15
ADC: Analog input 15
(AIN11 in TQFP100)
85 H10 63
86 H9 64
V
V
S
S
I
Supply voltage for digital I/O (5V)
Ground for digital I/O (5V)
JTAG Reset Input
DD
SS
87 G12 65 JTRST
88 F12 66 JTDI
89 H8 67 JTMS
90 G11 68 JTCK
T
T
T
T
T
I
pu
pu
pd
JTAG Data input
T
T
T
I
JTAG Mode Selection Input
JTAG Clock Input
I
JTAG data output.
Note: Reset state = HiZ
91 G10 69 JTDO
O
4mA
92 G9 70
93 G8 71
94 G7
V
V
S
Ground for digital I/O (5V)
Supply voltage for digital I/O (5V)
Port 4.0 TIM7: Input Capture A input
Port 4.1 TIM7: Input Capture B input
Port 4.2 TIM8: Input Capture A input
Port 4.3 TIM8: Input Capture B input
Port 4.4 CAN2: Transmit Data output
Port 4.5 CAN2: Receive Data input
Port 4.6 I2C1:Serial Clock
SS
DD
S
P4.0/ICAPA7
P4.1/ICAPB7
P4.2/ICAPA8
P4.3/ICAPB8
P4.4/CAN2TX
P4.5/CAN2RX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WUP24 2mA X
WUP25 2mA X
WUP26 2mA X
WUP27 2mA X
2mA X
X
X
X
X
X
X
X
X
X
X
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
95 F11
96 F10
97 F9
98 F8
99 E12
WUP18 2mA X
WUP19 2mA X
2mA X
100 E11 72 P4.6/SCL1
101 C12 73 P4.7/SDA1
Port 4.7 I2C1:Serial Data
102 B12
103 E10
P4.8/OCMPA8 I/O
P4.9/ICAPB6 I/O
2mA X
Port 4.8 TIM8: Output Compare A output
Port 4.9 TIM6: Input Capture B input
2mA X
16/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
TIM6: Input
Capture A input
(144-pin pkg only) (TQFP100 only)
TIM5: Input
Capture B input
P4.10/ICAPA6/
ICAPB5
Port
4.10
104 E9 74
I/O
WUP20 2mA X
X
T
T
Port
4.11
105 D12
106 D11
107 D10
P4.11/OCMPB8 I/O
2mA X
WUP21 2mA X
2mA X
X
X
X
X
X
TIM8: Output Compare B output
T
T
T
T
T
T
T
T
T
T
Port
4.12
P4.12/ICAPA9
P4.13/ICAPB9
I/O
I/O
I/O
I/O
TIM9: Input Capture A input
TIM9: Input Capture B input
BSPI1: Slave Select
Port
4.13
Port
4.14
108 C11 75 P4.14/SS1
109 B11 76 P4.15/SCK1
2mA X
Port
4.15
WUP22 2mA X
BSPI1: Serial Clock
110 B10 77 P5.0/MOSI1
111 C10 78 P5.1/MISO1
I/O
I/O
2mA X
2mA X
2mA X
2mA X
X
X
X
X
Port 5.0 BSPI1: Master Output/Slave input
Port 5.1 BSPI1: Master input/Slave output
Port 5.2 TIM9: Output Compare A output
Port 5.3 TIM9: Output Compare B output
T
T
T
T
T
T
T
T
112 A9
113 B9
P5.2/OCMPA9 I/O
P5.3/OCMPB9 I/O
PWM3: PWM
BSPI2: Slave
P5.4/SS2/
I/O
114 C9 79
2mA X
X
Port 5.4
output
T
T
PWM3
Select
(TQFP100 only)
115 D9 80 P5.5/SCK2
116 A11 81 P5.6/MOSI2
117 A10 82 P5.7/MISO2
118 A8 83 P5.8/PWM4
119 B8 84 P5.9/PWM5
I/O
I/O
I/O
I/O
I/O
WUP23 2mA X
2mA X
X
X
X
X
X
Port 5.5 BSPI2: Serial Clock
T
T
T
T
T
T
T
T
T
T
Port 5.6 BSPI2: Master Output/Slave input
Port 5.7 BSPI2: Master input/Slave output
Port 5.8 PWM4: PWM output (TQFP100 only)
Port 5.9 PWM5: PWM output (TQFP100 only)
2mA X
INT6 2mA X
INT7 2mA X
Port
120 C8 85 P5.10/RDI2
121 A12 86 P5.11/TDO2
122 D8 87 P5.12
I/O
I/O
I/O
I/O
I/O
I/O
S
INT8 2mA X
INT9 2mA X
INT10 2mA X
INT11 2mA X
INT12 2mA X
INT13 2mA X
X
X
X
X
X
X
UART2: Receive Data input
5.10
T
T
T
T
T
T
T
T
T
T
T
T
Port
UART2: Transmit Data output
5.11
Port
5.12
Port
5.13
123 E8
P5.13
P5.14
P5.15
Port
5.14
124 B7
Port
5.15
125 A7
Supply voltage for core provided by
internal voltage regulator
126 A6 88
V
18
127 C7 89
128 D7 90
V
V
S
S
Ground for digital I/O (5V)
SS
DD
Supply voltage for digital I/O (5V)
17/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Pin n°
Input
Output
Main
function
(after
Pin Name
Alternate function
reset)
129 E7 91 P6.0
130 F7 P6.1
131 B6 92 P6.2/RDI3
132 C6 P6.3
133 D6 93 P6.4/TDO3
134 E6 P6.5
135 A5 94 P6.6
136 B5 P6.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WUP0 8mA X
X
X
X
X
X
X
X
X
X
X
Port 6.0
Port 6.1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
WUP1 2mA X
WUP2 2mA X
WUP3 2mA X
WUP4 2mA X
WUP5 2mA X
WUP6 2mA X
WUP7 2mA X
WUP10 2mA X
2mA X
Port 6.2 UART3: Receive Data input
Port 6.3
Port 6.4 UART3: Transmit Data output
Port 6.5
Port 6.6
Port 6.7
137 C5 95 P6.8/RDI0
138 A3 96 P6.9/TDO0
Port 6.8 UART0: Receive Data input
Port 6.9 UART0: Transmit Data output
Port
6.10
139 A2
P6.10
I/O
I/O
I/O
I/O
I/O
I/O
WUP8 2mA X
2mA X
X
X
X
X
X
X
T
T
T
T
T
T
T
T
T
T
T
T
Port
140 D5 97 P6.11/MISO0
141 A4 98 P6.12/MOSI0
142 B4 99 P6.13/SCK0
143 C4 100 P6.14/SS0
BSPI0: Master input/Slave output
6.11
Port
2mA X
BSPI0: Master Output/Slave input
6.12
Port
WUP11 2mA X
2mA X
BSPI0: Serial Clock
6.13
Port
BSPI0: Slave Select
6.14
Port
6.15
144 B3
P6.15
WUP9 2mA X
18/22
STR73xF Data Brief
1.4 Memory Mapping
Figure 5 shows the various memory configurations of the STR73xF system. The system
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure, the
right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM addresses
can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access by
the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector 0x0000_0010).
It is up to the application software to manage these abort exceptions.
19/22
STR73xF Data Brief
Figure 5. Memory Map
Addressable Memory Space
4 Gbytes
APB Memory Space
32 Kbytes
0xFFFF FFFF
0xFFFF FFFF
APB TO ARM7
BRIDGE
32K
EIC
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
0xFFFF 8000
0xFFFF FC00
0xFFFF FBFF
ADC
0xFFFF F800
0xFFFF F7FF
0xFFFF F600
0xFFFF F400
0xFFFF F3FF
7
CMU
RTC
DMA 0-3
TIM 4
FLASH Memory Space
64K/128/256 Kbytes
0xE000 0000
0xDFFF FFFF
0xFFFF F000
0xFFFF EFFF
0xFFFF EC00
0xFFFF EBFF
0x8010 DFFF
TIM 3
System Memory
Flash registers
8K
0xFFFF E800
0xFFFF E7FF
0x8010 C000
0x8010 0017
0x8010 0000
6
TIM 2
20B
0xFFFF E400
0xFFFF E3FF
BSPI 2
BSPI 1
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
BSPI 0
0xFFFF D800
0xFFFF D7FF
5
GP I/O 0-6
PWM 0-5
0xFFFF D400
0xFFFF D3FF
0xA000 3FFF
0xA000 0000
0x9FFF FFFF
RAM
16K
0xFFFF D000
0xFFFF CFFF
(4)
CAN 2
0xFFFF CC00
0xFFFF CBFF
(4)
CAN 1
0xFFFF C800
0xFFFF C7FF
4
(4)
CAN 0
0xFFFF C400
0xFFFF C3FF
0x8010 0017
APB BRIDGE 1 REGS
reserved
WAKEUP
reserved
TIM 5-9
FLASH
64K/128K/256K
0xFFFF C000
0xFFFF BFFF
0x8000 0000
0x7FFF FFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
3
0xFFFF B400
0xFFFF B3FF
0x6000 03FF
PRCCU
1K
0x8003 FFFF
0xFFFF B000
0xFFFF AFFF
0x6000 0000
0x5FFF FFFF
TIM 1
(2)
0xFFFF AC00
0xFFFF ABFF
64K
64K
B0F7
TIM 0
0xFFFF A800
0xFFFF A7FF
0xFFFF A600
0x8003 0000
0x8002 FFFF
2
WAKEUPTIM
WDG
0xFFFF A400
0xFFFF A3FF
UART 3
UART 1
UART 2
UART 0
0x4000 003F
0x4000 0000
0x3FFF FFFF
(2)
0xFFFF A200
1K
1K
B0F6
CONFIG. REGS
64B
16B
0xFFFF A000
0xFFFF 9FFF
0xFFFF 9E00
0x8002 0000
0x8001 FFFF
0xFFFF 9C00
0xFFFF 9BFF
TB 0-2
1K
1K
1K
1K
1K
1K
1K
0xFFFF 9800
0xFFFF 97FF
(3)
1
64K
32K
B0F5
reserved
0xFFFF 9400
0xFFFF 93FF
0x2000 000F
0x2000 0000
0x1FFF FFFF
0x8001 0000
0x8000 FFFF
reserved
reserved
NATIVE ARBITER
0xFFFF 9000
0xFFFF 8FFF
B0F4
0xFFFF 8C00
0xFFFF 8BFF
0x8000 8000
0x8000 7FFF
2
I C 1
B0F3
B0F2
B0F1
B0TF
8K
8K
8K
0xFFFF 8800
0xFFFF 87FF
0x8000 6000
0
0x8000 5FFF
2
0x8000 4000
0x8000 3FFF
I C 0
0xFFFF 8400
0xFFFF 83FF
0x8000 2000
0x0010 0017
0x0000 0000
0x8000 1FFF
APB BRIDGE 0 REGS
FLASH (1)
64K/128K/256K
8K
0x8000 0000
0xFFFF 8000
(1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
(2) Only available in STR73xZ2/V2
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(4) Only available in STR730/STR731
Drawing not to scale
access to gray shaded area will return an ABORT
20/22
STR73xF Data Brief
2 ORDER CODES
Table 4. Order Codes
TIM
CAN
A/D
FLASH
Partnumber
RAM
Kbytes
Wake-up
Lines
I/O
Temp.
Package
Kbytes
Ports Range
Timers Periph. Chan.
STR730FZ1T7
STR730FZ2T7
STR730FZ1H7
STR730FZ2H7
STR735FZ1T7
STR735FZ2T7
STR735FZ1H7
STR735FZ2H7
STR731FV0T7
STR731FV1T7
STR731FV2T7
STR736FV0T7
STR736FV1T7
STR736FV2T7
128
256
128
256
128
256
128
256
64
TQFP144
20x20
3
LFBGA144
10x10
10
16
12
32
18
112
TQFP144
20x20
0
LFBGA144
10x10
-40 to
+105°C
16
TQFP100
14x14
128
256
64
3
0
6
72
TQFP100
14x14
128
256
21/22
STR73xF Data Brief
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
22/22
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