STV0056AF_技术文档

STV0056AF

SATELLITE SOUND AND VIDEO PROCESSOR

SOUND

.

TWO INDEPENDENT SOUND DEMODULATORS

PLL DEMODULATION WITH 5-10MHz FRE-

QUENCY SYNTHESIS

.

PROGRAMMABLE FM

DEMODULATOR

BANDWIDTH ACCOMODATING FM DEVIA-

TIONS FROM ±30kHz TILL ±400kHz

PROGRAMMABLE 50/75µs, J17 OR NO DE-

EMPHASIS

.

WEGENER PANDA SYSTEM

TWO AUXILIARYAUDIO INPUTS AND OUTPUTS

GAIN CONTROLLED AND MUTEABLE

AUDIO OUTPUTS

HIGH IMPEDANCE MODE AUDIO OUTPUTS

FOR TWIN TUNER APPLICATIONS

.

VIDEO

.

COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN

CONTROL

COMPOSITE VIDEO SELECTABLE INVERTER

TWO SELECTABLE VIDEO DE-EMPHASIS

NETWORKS

.

6 x 3 VIDEO MATRIX

BLACK LEVEL ADJUSTABLE OUTPUT FOR

ON-BOARD VIDEOCRYPT DECODER

HIGH IMPEDANCE MODE VIDEO OUTPUTS

FOR TWIN TUNER APPLICATIONS

TQFP64 (10 x 10mm)

(Thin Plastic Quad Flat Pack)

.

ORDER CODE : STV0056AF

MISCELLANEOUS

.

22kHzTONE GENERATIONFOR LNB CONTROL

I C BUS CONTROL

CHIP ADDRESSES = 06_HEXOR 46_HEX

LOW POWER STAND-BY MODE WITH AC-

2

.

TIVE AUDIO AND VIDEO MATRIXES

DESCRIPTION

TheSTV0056AFBICMOSintegratedcircuit realizes

allthe necessarysignalprocessingfromthe tunerto

theAudio/Videoinput andoutputconnectorsregard-

less the satellite system.

1/27

February 1998

STV0056AF

PIN CONNECTIONS

16 15 14 13 12

11 10

9

8

7

6

5

4

3

2

1

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

S2 RTN L

S1 VID OUT

S3 VID OUT

VOL R

S2 RTN R

FM IN

S3 RTN L

S3 RTN R

AGC L

S3 OUT L

S3 OUT R

IO

S3 VID RTN

S1 VID RTN

LEVEL R

PK IN R

FC R

AGND R

FC L

SCL

SDA

PK IN L

HA

LEVEL L

PKOUT L

PKOUT R

I_REF

J17 R

J17 L

XTL

V_DD5V

CPUMP R

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

PIN ASSIGNMENT

Pin Number

Name

GND

Function

1

Connected to the Lead Frame

VCR-Scart 2 Video Output

2

S2 VID OUT

VOL L

3

Volume Controlled Audio Out Left

VCR-Scart 2 Video Return

4

S2 VID RTN

S2 OUT L

CLAMP IN

S2 OUT R

UNCL DEEM

VIDEEM2/22kHz

V 12V

5

6

Fixed Level Audio Output Left (to VCR)

Sync-Tip Clamp Input

7

Fixed Level Audio Output Right (to VCR)

Unclamped Deemphasized Video Output

Video Deemphasis 2 or 22kHz Output

Video 12V Supply

8

9

10 - 11

12

VIDEEM1

V GND

Video Deemphasis 1

13 - 14

15

Video Ground

NC

16

B-BAND IN

S2 RTN L

S2 RTN R

FM IN

Base Band Input

17

Auxiliary Audio Return Left (from VCR)

Auxiliary Audio Return Right (from VCR)

FM Demodulator Input

18

19

20

S3 RTN L

Auxiliary Audio Return Left (from decoder)

2/27

STV0056AF

PIN ASSIGNMENT (continued)

Pin Number

21

Name

S3 RTN R

AGC L

Function

Auxiliary Audio Return Right (from decoder)

AGC Peak Detector Capacitor Left

Auxiliary Audio Output L (to decoder)

Auxiliary Audio Output R (to decoder)

Digital Input/Output or 22kHz Output

I²C Bus Clock

22

23

S3 OUT L

S3 OUT R

I/O/22kHz

SCL

24

25

26

27

SDA

I²C Bus Data

28

HA

Hardware Address

29

J17 R

J17 Deemphasis Time Constant Right

J17 Deemphasis Time Constant Left

4/8MHz Quartz Crystal or Clock Input

Digital 5V Power Supply

30

J17 L

31

XTL

32

V_DD5V

NC

34

Not Connected

33

GND 5V

CPUMP L

DET L

Digital Power Ground

35

FM PLL Charge Pump Capacitor Left

FM PLL Filter Left

36

37

U75 L

Deemphasis Time Constant Left

Amplitude Detector Capacitor Left

AGC Peak Detector Capacitor Right

38

AMPLK L

AGC R

NC

39

40

41 - 42

43

A GND L

V_REF

Audio Ground

2.4V Reference

44 - 45

46

A 12V

Audio 12V Supply

AMPLK R

DET R

Amplitude Detector Capacitor Left

FM PLL Filter Right

47

48

U75 R

Deemphasis Time Constant Right

FM PLL Charge Pump Capacitor Right

Current Reference Resistor

Noise Reduction Peak Detector Output Right

Noise Reduction Peak Detector Output Left

Noise Reduction Level Left

Noise Reduction Peak Detector Input

Audio Roll-off Left

49

CPUMP R

I_REF

50

51

PK OUT R

PK OUT L

LEVEL L

PK IN L

FC L

52

53

54

55

56

A GND R

FC R

Audio Ground

57

Audio Roll-off Right

58

PK IN R

LEVEL R

S1 VID RTN

S3 VID RTN

VOL R

Noise Reduction Peak Detector Input Right

Noise Reduction Level Right

TV-Scart 1 Video Return

59

60

61

Decoder-Scart Video Return

Volume Controlled Audio Out Right

Decoder-Scart Video Output

TV-Scart 1 Video Output

62

63

S3 VID OUT

S1 VID OUT

64

3/27

STV0056AF

PIN DESCRIPTION

1 - Sound Detection

to groundto derive a voltageto pull the VCO to the

target frequency. The output is ±100µA to achieve

lockand±2µA duringlock to providea trackingtime

constant of approximately 10Hz.

FMIN

This is the input to the two FM demodulators. It

feeds two AGC amplifiers with a bandwidth of at

least 5-10MHz. There is one amplifier for each

channelboth with the same input. The AGC ampli-

fiers have a 0dB to +40dB range.

Z_IN= 5kΩ, Min input = 2mV_PPper subcarrier.

Max input = 500mV_PP(max when all inputs are

added together, when their phases coincide).

V_REF

This is the audio processorvoltage referenceused

through out the FM/audio section of the chip. As

such it is essential that it is well decoupled to

ground to reduce as far as possible the risk of

crosstalk and noise injection. This voltage is de-

rived directly from the bandgap reference of 2.4V.

The V_REFoutput can sink up to 500µA in normal

operation and 100µA when in stand-by.

AGC L, AGC R

AGC amplifiers peak detector capacitor connec-

tions. The output current has an attack/decayratio

of 1:32. That is the ramp up current is approxi-

mately 5µA and decay current is approximately

160µA. 11V gives maximum gain. These pins are

also driven by a circuit monitoring the voltage on

AMPLK L and AMPLK R respectively.

I_REF

Thisis a bufferedV_REFoutputto an off-chipresistor

to produce an accurate current reference, within

the chip, for the biasing of amplifiers with current

outputs into filters. It is also required for the Noise

reduction circuit to provide accurate roll-off fre-

quencies. This pin should not be decoupled as it

would inject current noise. The target current is

50µA ±2% thus a 47.5kΩ ±1% is required.

AMPLK L, AMPLK R

The outputs of amplitude detectors LEFT and

RIGHT. Each requires a capacitorand a resistorto

GND. The voltage across this is used to decide

whether there is a signalbeing received by the FM

detector. The level detector output drives a bit in

the detector I²C bus control block.

AMPLK L and AMPLK R drive also respectively

AGC L and AGC R. For instance when the voltage

on AMPLK L is > (V_REF+ 1 V_BE) it sinks current to

V_REFfrom pin AGCL to reduce the AGC gain.

A 12V

Double bonded main power pin for the audio/FM

section of the chip. The two bond connectionsare

to the ESD and to power the circuit and on chip

regulators/references.

A GND L

This ground pin is double bonded :

DET L, DET R

Respectivelythe outputsof the FM phase detector

left and right.

This is for the connection of an external loop filter

for the PLL. The output is a push-pull current

source.

1) to channel LEFT : RF section & VCO,

2) to both AGC amplifiers, channel LEFT and

RIGHT audio filter section.

A GND R

This ground pin is double bonded :

1) to the volume control, noise reduction system,

ESD + Mux + V_REF

2) to channel right : RF section & VCO

CPUMP L, CPUMP R

The output from the frequency synthesizer is a

push-pullcurrent sourcewhich requiresa capacitor

4/27

STV0056AF

PIN DESCRIPTION (continued)

2 - Baseband Audio Processing

U75 L, U75 R

External deemphasis networks for channels left

and right.For eachchannela capacitorand resistor

in parallel of 75µs time constant are connected

betweenhereand V_REFtoprovide75µs de-empha-

sis. Internally selectable is an internalresistor that

can be programmedto be addedin parallelthereby

converting the network to approx 50µs de-empha-

sis (see control block map). The value of the inter-

nal resistors is 54kΩ ±30 %. The amplifier for this

filter is voltage input, current output ; with ±500mV

input the output will be ±55µA.

PK OUT L, PK OUT R, PK OUT

The noise reduction control loop peak detector

output requires a capacitorto ground from this pin,

and a resistor to V_REFpin to give some accurate

decaytimeconstant.An on chip5kΩ ±25% resistor

and external capacitor give the attack time.

PK IN L, PK IN R or PK IN

Eachof thesepins is an inputto a controllooppeak

detector and is connected to the output of the

offchip control loop band pass filter.

LEVEL L, LEVEL R

VOL L, VOL R

Respectively the audio left and right signals of the

FM demodulators are output to level L and level R

pins through an input follower buffer. The off-chip

filters driven by these pins must include AC cou-

pling to the next stage (PK IN L and PK IN R pins

respectively).

The main audio output from the volume control

amplifier the signalto get output signals as high as

2V_RMS(+12dB) on a DC bias of 4.8V. Control is

from +12dB to -26.75dB plus Mute with 1.25dB

steps.Thisamplifierhas shortcircuitprotectionand

is intendedto drivea SCARTconnectordirectlyvia

AC coupling and meets the standardSCART drive

requirements. These outputs feature high imped-

ance mode for parallel connection.

FC L, FC R

The variable bandwidth transconductance ampli-

fier has a current output which is variable depend-

ing on the input signal amplitude as defined by the

control loop of the noise reduction. The output

current is then dumped into an off-chip capacitor

which togetherwith the accurate current reference

define the min/maxrolloff frequencies.A resistor in

serieswith a capacitoris connectedto ground from

these two pins.

S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R

These audio outputs are sourced directly from the

audio MUX, and as a result do not include any

volume control function. They will output a 1V_RMS

signal biased at 4.8V. They are short circuit pro-

tected. These outputs feature high impedance

mode for parallel connection and meet SCART

drive requirement.

J17 L, J17 R

The external J17 de-emphasis networks for chan-

nels left and right. The amplifier for this filter is

voltage input, current output. Output with ±500mV

input will be ±55µA.

To performJ17 de-emphasiswiththe STV0042,an

external circuit is required.

S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R

These pins allow auxiliary audio signals to be con-

nected to the audio processor and hence makes

use of the on-chip volume control. For additional

details please refer to the audio switching table.

5/27

STV0056AF

PIN DESCRIPTION (continued)

3 - Video Processing

on the O/P. Thesignal is video2.0V_PP5.5MHzBW

with sync tip = 1.2V. These pins get signals from

the Video Matrix. The signal selected from the

Video Matrix for output on this pin is controlled by

a control register. This output also feature a high

impedance mode for parallel connection.

B-BAND IN

AC-coupled video input from a tuner.

Z_IN> 10kΩ ±25%. This drives an on-chip video

amplifier. The other input of this amp is AC

grounded by being connected to an internal V_REF

.

The video amplifier has selectable gain from 0dB

to 12.7dB in 63 steps and its output signal can be

selected normal or inverted.

S3 VID OUT

This output can drive for instance a decoder. Also

it is able to pass 10MHz ; Z_OUT< 75Ω. Video on

this pin will be 2V_PP. The black level of the ouput

video signal can be adjusted through I²C bus con-

trol to easily interface with on-board Videocrypt

decoder. This output feature an high impedance

mode for parallel connection.

UNCL DEEM

Deemphasized still unclamped output. It is also an

input of the video matrix.

VIDEEM1

Connected to an external de-emphasis network

(for instance 625 lines PAL de-emphasis).

V 12V

+ 12V doublebonded : ESD+guardrings and video

circuit power.

VIDEEM2 / 22kHz

Connected to an external de-emphasis network

(forinstance525 lines NTSCor othervideo de-em-

phasis).Alternativelya precise22kHz tone maybe

output by I²C bus control.

V GND

Doubled bonded. Clean VID IN GND. Strategically

placed video power ground connection to reduce

video currents getting into the rest of the circuit.

CLAMP IN

This pin clamps the most negative extreme of the

input (the sync tips) to 2.7V_DC(or appropriatevolt-

4 - Control Block

GND 5V

age). The video at the clamp input is only 1V_PP

.

The main power ground connectionfor the control

logic, registers, the I²C bus interface, synthesizer

& watchdog and XTLOSC.

This clamped video which is de-emphasised, fil-

tered and clamped (energy dispersal removed) is

normal, negative syncs, video. This signal drives

the Video Matrix input called Normal Video.

It hasa weak (1.0µA ±15 %) stable current source

pulling the inputtowardsGND. Otherwise the input

impedance is very high at DC to 1kHz Z_IN> 2MΩ.

Video bandwidth through this is -1dB at 5.5MHz.

The CLAMP input DC restore voltage is then used

as a means for getting the correct DC voltage on

the SCART outputs.

V_DD5V

Digital +5V power supply.

SCL

Thisis theI²C busclock line.Clock= DCto100kHz.

Requires external pull up eg. 10kΩ to 5V.

SDA

This is the I²C bus data line. Requires external pull

S3 VID RTN

up eg. 10kΩ to 5V.

This input can be driven for instance by the de-

coder.This input has a DC restorationclamp on its

input. The clamp sink current is 1µA ±15% with the

buffer Z_IN> 1MΩ.

I/O / 22kHz

General purpose input output pin or 22kHz output.

XTL

S2 VID RTN, S1 VID RTN

This pin allowsfor theon-chip oscillatorto be either

used with a crystal to ground of 4MHz or 8MHz, or

to be driven by an external clock source. The

external source can be either 4MHz or 8MHz. A

programmablebit in thecontrol blockremovesa ÷2

block when the 4MHz option is selected.

Externalvideoinput1.0V_ppACcoupled75Ω source

impedance. This input has a DC restoration clamp

on its input. The clamp sink current is 1µA ±15%

withthe buffer Z_IN> 1MΩ. This signalis an input to

the Video Matrix.

HA

S1 VID OUT, S2 VID OUT

Video drivers for SCART 1 and SCART 2. An

external emitter follower buffer is required to drive

a 150Ω load. The average DC voltage to be 1.5V

Hardware address with internal 135µA pull down.

Chip address is 06 when this pin is grouded and

chip address is 46 when connected to V_DD

.

6/27

STV0056AF

GENERAL BLOCK DIAGRAM

B-BAND

Video

Processing

2

4

From Tuner

6 x 3

Video

Matrix

3

From TV,

VCR/Decoder

2

To TV, VCR/Decoder

FM

From Tuner

Demodulation

2 Channels

Audio

Matrix

+

Volume

Wegener

Panda +

Deemphasis

I²C Bus

Interface

22kHz to LNB

Active in Stand-by

STV0056AF

VIDEO PROCESSING BLOCK DIAGRAM

LPF

NTSC

PAL

UNCL DEEM

VIDEEM2/22kHz

VIDEEM1

9

12

8

25

16

I/O/22kHz

22kHz

TONE

Deemphasized

÷ 2

B-BAND IN

CLAMP IN

± 1

G

Baseband

Normal

6

CLAMP

DecoderReturn

VCR Return

TV Return

CLAMP

61

4

S3 VID RTN

S2 VID RTN

S1 VID RTN

60

BLACK LEVEL

ADJUST

STV0056AF

63

64

2

S3 VID OUT

S2 VID OUT

To VCR

To Decoder

To TV

7/27

STV0056AF

AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT)

STV0056AF

K2

a

b

a

b

K1

c

a

AUDIO

DEEMPHASIS

c

ANRS

AUDIO R

MONO

STEREO

K3

b

K4

b

4

a

b c

a

b c

a

K5

K6

6dB

24

6dB

7

-6dB

18

47

21 51 58 59 57

29

48

62

PLL

FILTER

Audio

Decoder Out

Audio

Decoder Return

DECODER

VCR

TV

AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT)

STV0056AF

K2

a

b

a

K1

b

c

a

AUDIO

DEEMPHASIS

c

ANRS

4

AUDIO L

MONO

STEREO

K3

b

K4

b

a

b c

a

b

c

a

K5

K6

6dB

23

6dB

5

-6dB

17

36

20 52 54 53 55

30

37

3

PLL

FILTER

Audio

Decoder Out

Audio

Decoder Return

DECODER

VCR

TV

8/27

STV0056AF

AUDIO SWITCHING

AUDIO

K_1a

K_5b

K_5c

K_5a

K_6c

K₄: a → ANRS input non-scrambled audio

b → ANRS input descrambled audio

DEEMPHASIS

+ ANRS

K₂

K₃

AUDIO PLL

DEC RTN

AUX IN

K_6a

a

b₁

b₂

c

a

No ANRS, No De-emphasis

No ANRS, 50 s

µ

No ANRS, 75 s

µ

No ANRS, J17

K_1b

a

b₁

b₂

c

b

ANRS, No De-emphasis

ANRS, 50µs

ANRS, 75µs

K_6b

ANRS, J17

K_1c

VOL OUT AUX OUT DEC OUT

FM DEMODULATION BLOCK DIAGRAM

47 DET R

Phase

Detect

SW1

FM IN 19

AGC

AUDIO R

FM dev.

Select.

LEVEL

DETECTOR1

Bias

AGC R 39

49 CPUMP R

LEVEL

DETECTOR2

V_REF

Amp. Detect

AMPLK R 46

90

VCO

0

SW2

SW4

WATCHDOG

V_REF

Reg8 b4

SYNTHESIZER

AUDIO L

36 DET L

Phase

Detect

SW3

AGC

FM dev.

Select.

LEVEL

DETECTOR1

Bias

AGC L

22

35

CPUMP L

LEVEL

DETECTOR2

V_REF

Amp. Detect

AMPLK L 38

90

VCO

0

WATCHDOG

V_REF

Reg8 b0

STV0056AF

9/27

STV0056AF

CIRCUIT DESCRIPTION

Video Section

a synchronous amplitude detector, which is also

used for the audio input AGC.

The composite video is first set to a standard level

by means of a 64 step gain controlled amplifier. In

thecasethat themodulationis negative,an inverter

can be switched in.

In order to maintain constant amplitude of the

recovered audio regardless of variations between

satellites or subcarriers, the PLLloop gain may be

programmed from 56 values.

Any frequency deviation can be accomodated

(from ±30kHz till ±400kHz).

One of two different external video de-emphasis

networks (for instance PAL and NTSC) is select-

able by an integrated bus controlled switch.

Two different networks can be permanently con-

nected for either 75µs or J17 de-emphasis. If 50µs

de-emphasisis required,thiscan be insertedby an

internal switch, thus allowing a worldwide applica-

tion.

Then energy dispersal is removed by a sync tip

clamping circuit, which is used on all inputs to a

video switching matrix, thus making sure that no

DC steps occur when switching video sources.

The matrix can be used to feed video to and from

decoders, VCR’s and TV’s.

The STV0056AFis intended to be compatiblewith

Wegener Panda System.

A bus controlled black level adjustment circuit is

provided on the decoder output allowing a direct

connection to an on-board Videocrypt decoder.

Two types of audio outputs are provided : one is a

fixed 1V_RMSand the other is a gain controlled

2V_RMSmax. The control range being from +12dB

to -26.75dBwith 1.25dBsteps.Thisoutputcanalso

be muted.

A matrix is implementedto feed audio to and from

decoders VCR’s and TV’s.

Additionaly all the video outputs are tristate type

(high impedance mode is supported), allowing a

simple parallel connections to the scarts (Twin

tuner applications).

Noise reduction system and de-emphasis can be

inserted or by-passed through bus control.

Audio Section

The two audio channels are totally independent

except for the possibility given to output on both

channelsonly one of theselectedinputaudio chan-

nels.

Also all the audio outputs are tristate-type (high

impedance mode is supported), allowing a simple

parallelconnectionsto the scarts(Twin tuner appli-

cations).

To allow a very cost effective application, each

channel uses PLL demodulation. Neither external

complex filter nor ceramic filters are needed.

Others

A 22kHz tone is generated for LNB control.

The frequency of the demodulated subcarrier is

chosen by a frequencysynthesizer which sets the

frequency of the internal local oscillator by com-

paring its phase with the internally generated

reference. When the frequency is reached, the

microprocessor switches in the PLL and the de-

modulationstarts. Atany momentthe microproces-

sor can read from the device (watchdog registers)

the actual frequency to which the PLL is locked. It

canalsoverifythat a carrierispresentatthe wanted

frequency(by reading AMPLK status bit) thanks to

It is selectable by bus controland availableon one

of the two pins connected to the external video

de-emphasis networks. One general purpose I/O

is also available on the STV0056AF.

By means of the I²C bus there is the possibility to

drive the ICs into a low power consumption mode

with active audio and video matrixes. Inde-

pendantly from the main power mode, each indi-

vidual audio and video outputcan be driven to high

impedance mode.

10/27

STV0056AF

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_CC

V_DD

Supply Voltage

15

7.0

V

P_tot

T_oper

T_stg

Total Power Dissipation

900

mW

^oC

Operating Ambient Temperature

Storage Temperature

0, + 70

-55, + 150

THERMAL DATA

Symbol

Parameter

Thermal Resistance Junction-ambient

Value

Unit

^oC/W

Rth(j-a)

Max.

55

DC AND AC ELECTRICAL CHARACTERISTICS

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

V_CC

V_DD

Sypply Voltage

Supply Current

11.4

4.75

12

12.6

5.25

V

5.0

IQ_CC

IQ_DD

All audio and all video outputs

activated

55

8

70

15

mA

IQLP_CCSupply Current at Low Power Mode

IQLP_DD

All audio and all video outputs

are in high impedance mode

27

6

35

9

mA

AUDIO DEMODULATOR

FMIN

DETH

FM Subcarrier Input Level

(Pin FMIN for AGC action)

VCO locked on carrier at 6MHz

5

500 mV_PP

560k load on AMPLOCK Pins

Ω

180k load on DET Pins

Ω

Detector 1 and 2 (AMPLOCK Pins)

(Threshold for activating Level Detector 2) Carrier without modulation

8mV_PPFMIN 500mV

2.90 3.10 3.30

V

≤

PP

VCOMI VCO Mini Frequency

VCOMA VCO Maxi Frequency

V

_CC: 11.4 to 12.6V,

5

MHz

V_PP

T_amb: 0 to 70^oC

10

AP50

1kHz Audio Level at PLL output

(DET Pins)

0.5V_PP50kHz dev. FM input,

Coarse deviation set to 50kHz

(Reg. 05 = 36_HEX

0.6

1

1.35

)

APA50 1kHz Audio Level at PLL output

(DET Pins)

0.5V_PP50kHz dev. FM input,

Coarse and fine settings used

0.92

0

1

1.08

1

V_PP

dB

FMBW FM Demodulator Bandwidth

Gain at 12kHz versus 1kHz

180kΩ, 82kΩ 22pF on DET Pins

0.3

60

DPCO Digital Phase Comparator Output

Current (CPUMP Pins)

Average sink and source

current to external capacitor

A

µ

AUTOMATIC NOISE REDUCTION SYSTEM

LRS

Output Level (Pins LEVEL)

1V_PPon left and right channel

0.9

4.0

1

1.1

6.8

V_PP

LDOR Level Detector Output Resistance

(Pins PK OUT)

5.4

kΩ

NDFT

Level Detector Fall Time Constant

(Pins PK OUT)

External 22nF to GND and

26.4

ms

1.2M to V

Ω

REF

NDLL

LLCF

Bias Level (Pins PK OUT)

No audio in

2.40

0.85

V

Noise Reduction Cut-off Frequency at

Low Level Audio

100mV_PPon DET Pins, External

capacitor 330pF (FC Pins)

kHz

HLCF

Noise Reduction Cut-off Frequency at

High Level Audio

1V_PPon DET Pins, External

capacitor 330pF (FC Pins)

7

kHz

11/27

STV0056AF

DC AND AC ELECTRICAL CHARACTERISTICS (continued)

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L)

DCOL

AOLN

DC Output Level

4.8

V

Audio Output Level

with Reg 00 = 1A

FM input as for APA50

1.5

2.0

60

1.9 2.34 V_PP

No de-emphasis, No pre-emphasis

No noise reduction

AOL50 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

3.3

3.2

4.0

V_PP

50 s de-emphasis, 27k //2.7nF load

µ

Ω

No pre-emphasis, No noise reduction

AOL75 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

75µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

AOL17 Audio Output Level

with Reg 00 = 1A

FM input as for APA50

J17 de-emphasis, 36k 4.7k 8.2nF load

Ω

No pre-emphasis, No noise reduction

AMA1

MXAT

Audio Output Attenuation

with Mute-on. Reg 00 = 00.

1V_PP- 1kHz from S2 RTN Pins

65

dB

Max Attenuation before Mute.

Reg 00 = 01.

1kHz, from S2 RTN Pins

32.75

MXAG Audio Gain. Reg 00 = 1F.

1kHz, from S2 RTN Pins

1kHz

5

6

7

dB

ASTP

Attenuation of each of the 31

steps

1.25

THDA1 THD with Reg 00 = 1A

THDA2 THD with Reg 00 = 1A

THDFM THD with Reg 00 = 1A

1V_PP-1kHz from S2 RTN Pins

2V_PP-1kHz from S2 RTN Pins

0.15

0.3

%

1

FM input as for APA50

75µs de-emphasis, ANRS ON

0.3

ACS

Audio Channel Separation

1V_PP-1kHz on S2 RTN Pins

60

74

60

dB

ACSFM Audio Channel Separation at 1kHz - 0.5 V_PP- 50kHz deviation FM input on

one channel

- 0.5V_PPno deviation FM input on the

other channel

- Reg 05 = 36_HEX

- 75µs de-emphasis, no ANRS

SNFM

Signal to Noise Ratio

FM input as for APA50,

56

69

dB

75 s de-emphasis,

µ

no ANRS, Unweighted

SNFMNR Signal to Noise Ratio

FM input as for APA50

75 s de-emphasis,

µ

ANRS ON, Unweighted

Z_{OUT L}

Z_{OUT H}

Audio Output Impedance

Low impedance mode

High impedance mode

18

44

Ω

kΩ

30

55

AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L)

DCOLAO DC output level

Aux. input pins open circuit

4.8

2

V

AOLNS Audio Output Level

on S2 and S3

FM input as for APA50

No de-emphasis, No pre-emphasis

No noise reduction

1.55

2.0

-1

2.42 V_PP

AOL50S Audio Output Level

on S2 and S3

FM input as for APA50

50µs de-emphasis, 27kΩ//2.7nF load

No pre-emphasis, No noise reduction

3.4

3.3

0

4.0

+1

V_PP

AOL75S Audio Output Level

on S2 and S3

FM input as for APA50

75 s de-emphasis, 27k //2.7nF load

µ

Ω

No pre-emphasis, No noise reduction

AOL17S Audio Output Level

on S2 and S3

FM input as for APA50

J17 de-emphasis, 36k 4.7k 8.2nF load

Ω

No pre-emphasis, No noise reduction

AGAO

S2 to S3 Audio Gain

and S3 to S2 Audio Gain

1kHz

dB

%

THDA02 THD on S2, Input in S3

12/27

2V_PP- 1kHz from Aux input pins

0.04 0.2

STV0056AF

DC AND AC ELECTRICAL CHARACTERISTICS (continued)

(V_CC= 12V, V_DD= 5V, T_amb= 25^oC unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L) (continued)

THDAOFM THD on S2 or S3

FM input as for APA50

0.3

1

%

75 s de-emphasis, no ANRS

µ

Z_{OUT L}

Z_{OUT H}

Audio Output Impedance

Low impedance mode

High impedance mode

60

44

100

55

Ω

30

k

Ω

I/O

V_IL

V_IH

Low Level Input

High Level Input

0.8

0.4

V

2.4

3.2

V

V_OL

V_OH

Low Level Output

High Level Output

I_sink= 2mA

I_source= 2mA

0.2

4.6

V

LNB_T

LNB_D

Tone Frequency

22.2 22.2 22.2 kHz

Tone Signal Duty Cycle

No load connected on I/O

49

50

51

%

RESET

RTCCU

End of Reset Threshold for V_CCV_DD= 5V, V_CCgoing up

Start of Reset Threshold for V_CCV_DD= 5V, V_CCgoing down

End of Reset Threshold for V_DDV_CC= 12V, V_DDgoing up

Start of Reset Threshold for V_DDV_CC= 12V, V_DDgoing down

8.7

7.9

3.8

3.5

V

RTCCD

RTDDU

RTDDD

COMPOSITE SIGNAL PROCESSING

VIDC

ZVI

VID IN

External load current < 1 A

2.25 2.45 2.65

11 14

V

µ

VID IN Input Impedance

DC Output Level (Pins VIDEEM)

7

k

Ω

V

DEODC

DEOMX

2.25 2.45 2.65

2

Max AC Level before Clipping

(Pins VIDEEM)

GV = 0dB, Reg 01 = 00

V_PP

DGV

INVG

Gain error vs GV @ 100kHz

Inverter Gain

GV = 0 to 12.7dB, Reg 01 = 00

3F

-0.5

-0.9

-1

0

-1

0

0.5

-1.1

1

dB

→

VISOG

Video Input to SCART Outputs

Gain

De-emphasis amplifier mounted in unity

gain, Normal video selected

dB

MHz

%

DEBW

DFG

Bandwidth for 1V_PPinput

measured on Pins VIDEEM

@ - 3dB with GV = 0dB, Reg 01 = 00

10

Differential Gain on Sync Pulses GV = 0dB, 1V_PPCVBS + 0.5V_PP

measured on Pins VIDEEM

1

25Hz sawtooth (input : VID IN)

ITMOD

Intermodulation of FM subcar-

riers with chroma subcarrier

7.02 and 7.2MHz sub-carriers,

12.2dB lower than chroma

-60

dB

CLAMP STAGES (Pins CLAMP IN, S1, S2, S3 VID RTN)

ISKC

ISCC

Clamp Input Sink Current

V

_IN= 3V

_IN= 2V

0.5

40

1

1.5

60

A

µ

Clamp Input Source Current

V

50

VIDEO MATRIX

XTK

BFG

Output Level on any Output

@ 5MHz

TBD

2

dB

when 1V_PPCVBS input is

selected for any other output

Output Buffer Gain (Pins S1 VID

OUT, S2 VID OUT, S2 VID OUT)

@ 100kHz

1.87

16

2.13

DCOLVH DC Output Level

High impedance mode

0

0.2

30

V

Z_{OUT HV}

VCL

Video Output Impedance

High impedance mode

23

k

Ω

Sync Tip Level on Selected

Outputs (Pins S1 VID OUT, S2

VID OUT)

1V_PPCVBS through 10nF on input

1.05 1.3 1.55

V

VCL S3

Sync Tip Level at S3 VID OUT

with Black Level Adjust

Register 4

b6 b7

0

1

0

1

0

1

1.36

1.52

1.67

1.84

V

13/27

STV0056AF

PIN INTERNAL CIRCUITRY

S1 VID RTN, S2 VID RTN, S3 VID RTN,

CLAMP IN

50µA source is active only when VIDIN < 2.7V.

UNCL DEEM

Same as above but with no black level adjustment

and slightly different gain.

Figure 1

Figure 4

60Ω

V_DD9V

V_CC12V

50µA

4

Pins 60 - 4

UNCL DEEM

8

10kΩ

1µA

61 - 6

S1 VID RTN

S2 VID RTN

S3 VID RTN

CLAMP IN

2.3mA

IN

25kΩ

GND 0V

V_REF2.4V

GND 0V

V_DD5V

16.7kΩ

GND 0V

VIDEEM1

Ron of the transistor gate is ≈10kΩ.

S3 VID OUT

I blacklevelis I²C programmablefromsource16µA

to sink 33µA equivalent to an offset voltage of

-150mV to + 300mV. The 60Ω collector resistor is

for short cct. protection.

Figure 5

6µ/2µ

10µ/2µ

12

Figure 2

VIDEEM1

125µA

60Ω

V_CC12V

4

VIDEEM2 / 22kHz

Ron of the transistor gate is ≈10kΩ.

63 S3 VID OUT

2.3mA

10kΩ

VID MUX

Figure 6

25kΩ

GND 0V

V_REF2.4V

6µ/2µ

10µ/2µ

16.7kΩ

I Black Level

9

VIDEEM2/22kHz

125µA

GND 0V

V_DD5V

S1 VID OUT, S2 VID OUT

Same as abovebut with no black level adjustment.

100µ/2µ

60µ/2µ

22kHz

Figure 3

60Ω

V_CC12V

4

VID IN

Figure 7

Pins 64 - 2

S1 VID OUT

S2 VID OUT

2.3mA

10kΩ

V_REF2.4V

VID MUX

20kΩ

GND 0V

V_REF2.4V

6.5kΩ

20kΩ

16

B-BAND_IN

85µA

0.5pF

GND 0V

14/27

STV0056AF

PIN INTERNAL CIRCUITRY (continued)

PK OUT R, PK OUT L

Figure 8

S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R

4.8V bias voltage is the same as the bias level on

the audio outputs.

V_DD9V 3.4V

Clamp

Figure 12

4.8V

Audio

Pins 17 - 18 - 20 - 21

S2 RTN L - S2 RTN R

1

25kΩ

50µA

1

S3 RTN L - S3 RTN R

Pins 51 - 52

PK OUT R

PK OUT L

5kΩ

Peak Detector

FM IN

The otherinputfor eachchannelis internallybiased

FC L, FC R

Ivar is controlled by the peak det audio level max.

±15µA (1V_PPaudio).

in the same way via 10kΩ to the 2.4V V_REF

.

Figure 13

Figure 9

2.4V

19

Left Channel

V

_DD9V

10kΩ

Pin 55 - 57

FC L - FC R

FM IN

50µA

1

10kΩ

50µA

1

Right Channel

Ivar

I_REF

The optimum value if I_REFis 50µA ±2% so an

external resistor of 47.5kΩ ±1% is required.

VOL OUT R, VOL OUT L

Figure 14

Audio output with volume and scart driver with

+12dB of gain for up to 2V_RMS. The opamp has a

push-pulloutput stage.

2.4V

Figure 10

1

I_REF

50

Audio

2.4V Bias

Pins 62 - 3

VOL OUT R

I/O / 22kHz

The input is TTL compatible.

The output is tri-stateable.

VOL OUT L

30kΩ

4.8V

Figure 15

GND 0V

15kΩ

180µ/2µ

10µ/2µ

IIC Reg

91µ/2µ

I/O/22kHz

205Ω

MUX

25

22kHz

ESD

100µ/2µ

S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R

Same as above but with gain fixed at +6dB.

Figure 11

SCL

Thisis theinput to a Schmittinputbuffer made with

a CMOSamplifier.

Pins 5 - 7 - 23 - 24

S2 OUT L

S2 OUT R

S3 OUT L

S3 OUT R

Audio

2.4V Bias

Figure 16

205Ω

20kΩ

SCL

24µ/4µ

26

GND 0V

ESD

15/27

STV0056AF

PIN INTERNAL CIRCUITRY (continued)

SDA

CPUMP L, CPUMP R

Input same as above.

Output pull down only : relies on external resistor

for pull-up.

An offset on the PLL loop filter will cause an offset

in the two 1µA currents that will prevent the PLL

from drifting-off frequency.

Figure 17

Figure 21

SDA

205Ω

24µ/4µ

27

100µA

ESD

600µ/2µ

Pins 35-49

CPUMP L

GND 0V

1µA

CPUMP R

Dig Synth

Loop Filter Tracking

J17 L, J17 R, U75 L, U75 R

I1 - I2 = 2 x audio / 18kΩ. eg 1V_PPaudio : ±55µA.

The are internal switches to match the audio level

of the different standards.

1µA

VCO Input

100µA

Figure 18

I1

Pins 30 - 29

37 - 48

J17 L - J17 R

U75 L - U75 R

DET L, DET R

I2 - I1 = f (phase error).

I2

Figure 22

HA

I2

I1

Input with CMOS levels.

Pins 36 - 47

DET L - DET R

Figure 19

25µ/2µ

205Ω

28

HA

AMPLK L, AMPLK R, AGC L, AGC R

I2 and I1 from the amplitude detecting mixer.

ESD

10µ/2µ

150µA

Figure 23

GND 0V

To VCA

Pin 38

XTL

Pin 22

Pin 39

AGC L

AGC R

Figure 20

I2

5µA

Pin 46

AMPLK L

AMPLK R

2

I1

3

460Ω

10kΩ

2

XTL

31

160µA

5pF

GND 0V

V_REF2.4V

16/27

STV0056AF

PIN INTERNAL CIRCUITRY (continued)

V_REF

V_DD5V, GND 5V

The 400µA source is off during stand-bymode.

Connected to XTL oscillator and the bulk of the

CMOS logic and 5V ESD.

Figure 24

A GND

V_REF(2.4V)

43

Doubled bonded :

Vbg 1.2V

4

- One pad connected to the left VCO, dividers,

mixers and guard ring. the guard connection is

star connecteddirectly to the pad.

- The second pad is connectedto both AGC amps

and the deemphasis amplifiers, frequency syn-

thesis and FM deviation selection circuit for both

channels.

10kΩ

400µA

10kΩ

GND 0V

A 12V

Doubled bonded :

- One pad connected to the ESD and guard ring.

- The second pad is connected to the main power

for all of the audio parts.

LEVEL L, LEVEL R

Figure 25

V_REF2.4V

SW

1

Pins 59 - 53

LEVEL R

LEVEL L

A GND R

Boubled bonded :

Audio

49kΩ

50kΩ

100µA

- One pad connected to the right VCO, dividers,

mixers and guard ring. The guard connection is

star connecteddirectly to the pad.

- The second pad is connected to the bias block,

audio noise reduction, volume, mux and ESD.

PK IN L, PK IN R

Figure 26

A third bond wire on this pin is connected directly

to the die pad (substrate).

V_REF2.4V

Figure 27

1

Pins 58 - 54

PK IN R

To Peak Det

Pins 10 - 11

V 12V

67kΩ

PK IN L

100µA

Video Pads

Pins 13 - 14

V GND

V 12V

Doubledbonded (two bond wires and two padsfor

one package pin) :

- One pad is connected to all of the 12V ESD and

video guard rings.

32

V_DD5V

Vpp

BIP 10vpl

Vmm

205Ω

Digital Pads

DZPN1

- The second pad is connected to power up the

video block.

33

GND 5V

Pins 41 - 42

A GND L

V GND

Doubled bonded :

A 12V

+

- Onepad is connectedto power-upall of the video

mux and I/O.

- The second pad is only as a low noise GND for

the video input.

BIP

12V

-

Audio Pads

Substrate

A GND R 56

17/27

STV0056AF

I²C PROTOCOL

1) WRITING to the chip

S-Start Condition

P-Stop Condition

CHIP ADDR - 7 bits. Programmable 06H or 46H (STV0056AF only) with Pin HA.

W-Write/Read bit is the 8th bit of the chip address.

A-ACKNOWLEDGE after receiving 8 bits of data/adress.

REG ADDR

Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or

don’t care ie only the first 3 bits are used.

DATA

8 bits of databeing written to the register. All 8 bitsmust be writtento atthe same

time.

REG ADDR/A/DATA/A can be repeated, the write process can continue untill terminated with a STOP

REG ADDR

condition. If the

met (ie an A generated).

is higher than 07 then IIC PROTOCOL will still be

Example :

S

06

W

A

00

A

55

A

01

A

8F

A

P

2) READING

from the chip

When reading,thereis an auto-incrementfeature. Thismeans anyread command alwaysstarts by reading

Reg 8 and will continue to read the following registers in order after each acknowledge or until there is no

acknowledge or a stop. This function is cyclic that is it will read the same set of registers without

re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3

registersin a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the11 registers can

be read.

Reg0 bit 7 = L

Start / chip add / R / A / Reg 8 / A/ Reg9 / A / Reg 0A/ A/ Reg 8 / A / Reg 9 / A / Reg 0A

/... / P /

Reg0 bit 7 = H

Start / chip add / R / A / Reg 8 / A/ Reg 9 / A / Reg 0A / A / Reg 7 / A/ Reg 6 / A / Reg 8

/ A/ Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P /

CONTROL REGISTERS

Reg 0

write only

Bit (default 00_HEX

)

0

1

2

3

4

5

6

7

L

Select 5 bits audio volume control 00H = MUTE

Select 5 bits audio volume control 01H = -26.75dB

Select 5 bits audio volume control : : : :

Select 5 bits audio volume control 1.25dB steps up to

Select 5 bits audio volume control 1FH = +12dB

Audio mux switch K4 - ANRS I/P select (L = PLL)

Audio mux switch K3 - ANRSselect (L = no ANRS, H = ANRS)

L = read 3 registers, H = read 5 registers

:

Reg 1

write only

Bit (default 00_HEX

)

0

1

2

3

4

5

6

7

L

Select video gain bits

00H = 0dB

01H = +0.202dB

02H = +0.404dB

n

= + 0.202 dB * n

3FH = + 12.73 dB

Selected video invert (H = inverted, L = non inverted)

Video deemphasis 1 / Video deemphasis2 (L : V_IDDe-em 1)

18/27

STV0056AF

CONTROL REGISTERS (continued)

Reg 2 write only

Bit (default F7_HEX

)

0

1

2

3

4

5

6

7

H

L

H

Select video source for scart 1 O/P

Select 4.000MHz or 8.000MHzclock speed (L = 8MHz)

Select audio source for volume output (Switch K1)

Select Left/Right/Stereofor volume output

Reg 3

write only

Bit (default F7_HEX

)

0

1

2

3

4

5

6

7

H

L

H

Select video source for scart 2 O/P

Video deemphais 2 / 22kHz (H : 22kHz)

Select audio source for Scart 2 output (Switch K5)

Audio deemphasisselect (Switch K2)

Reg 4

write only

Bit (default BF_HEX

)

0

1

2

3

4

5

6

7

H

L

Select source for video decoder O/P

Stand-by or low power mode (H = low power)

Select audio source for Scart 3 output (Switch K6)

Black level adjust on Scart 3 video

H

Black level adjust on Scart 3 video

Reg 5

write only

Bit (default B5_HEX

)

0

1

2

3

4

5

6

7

H

L

FM deviation selection -- default value for 50kHz modulation

FM deviation selection

H

L

H

L

FM deviation selection

FM deviation selection (L = double the FM deviation)

Select 22kHz for I/O (Pin29 / STV0056AF)

Select TP50a (H) or I/O (Pin 29 / STV0056AF). TP50a for test only.

H

Reg 6

write/read

Bit (default 86_HEX

)

0

1

2

3

4

5

6

7

L

Status of I/O

H

L

H

Select data direction of I/O 1 ( H = output)

Select frequency synthesizer 1 OFF/ON (L = OFF)

Select frequency synthesizer 2 OFF/ON (L = OFF)

Select RF source (L = OFF) to FM det 1

Select RF source (L = OFF) to FM det 2

Select frequency for PLL synthesizer- LSB (bit 0) of 10-bit value

Select frequency for PLL synthesizer- bit 1 of 10-bit value

19/27

STV0056AF

CONTROL REGISTERS (continued)

Reg 7

write/read

Bit (default AF_HEX

)

0

1

2

3

4

5

6

7

H

L

H

L

Select frequency for PLL synthesizer- bit 2 of 10-bit value

Select frequency for PLL synthesizer

Select frequency for PLL synthesizer- bit 9, MSB (10th bit) of 10-bit value

H

Reg 8

read only

Bit

0

1

Subcarrier detection (DET 1) (L = No subcarrier)

Not used

2

3

4

5

Read frequencyof watchdog 1 - LSB (bit 0) of 10-bit value

Read frequencyof watchdog 1 - bit 1 of 10-bit value

Subcarrier detection (DET 2) (L = No subcarrier)

Not used

6

7

Read frequencyof watchdog 2 - bit 0 of 10-bit value

Read frequencyof watchdog 2 - bit 1 of 10-bit value

Reg 9

read only

Bit (default AF_HEX

)

0

1

2

3

4

5

6

7

Read frequencyof watchdog 1 - bit 2 of 10-bit value

Read frequencyof watchdog 1

Read frequencyof watchdog 1 - bit 9, MSB (10th bit) of 10-bit

Reg 0A read only

Bit

0

1

2

3

4

5

6

7

Read frequencyof watchdog 2 - bit 2 of 10-bit value

Read frequencyof watchdog 2

Read frequencyof watchdog 2 - bit 9, MSB (10th bit) of 10-bit

20/27

STV0056AF

CONTROL REGISTERS (continued)

Video Mux Truth Tables

Register 2 <0:2>

Register 3 <0:2>

Register 4 <0:2>

Scart 1 video output control

Scart 2 video output control

Scart 3 decoderoutput control

The truth table for the three scart outputs are the same.

Register 2/3/4

Video Output

Bit<2>

Bit<1>

Bit<0>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Baseband video

De-emphasized video

Normal video

Scart 3 return

Scart 2 return

Scart 1 return

Nothing selected

High Z or low power (default)

Register 4

Black Level Adjust on Scart 3

Bit <7>

Bit <6>

0

1

0

1

0

1

-150mV

0 (default)

+150mV

+300mV

Audio Mux Truth Tables

Register 2

Switch K1/Audio Source Selection for Volume Output

Volume Output

Bit <5>

Bit <4>

0

1

0

1

0

1

A

C

B

-

Audio deemphasis (K2 switch O/P)

Scart 2 return

Scart 3 return

High Z or low power (default)

Register 3

Switch K2/Audio Deemphasis

Bit <7>

Bit <6>

Audio Deemphasis

No deemphasis

J17

0

1

0

1

0

1

A

C

B

50 s

µ

75µs (default)

Register 0

Switch K3 & K4

Bit <6>

Bit <5>

ANRS I/O Select

Noise reduction OFF

Noise reduction ON (default)

I/P = PLL

0

1

X

0

1

A

B

A

B

X

I/P = Scart 3 return

Register 3

Switch K5/Audio Source Selection for Scart 2

Bit <5>

Bit <4>

Aux Audio Output

0

1

0

1

0

1

C

A

B

-

PLL output

Scart 3 return

Audio deemphasis (K2 switch O/P)

High Z or low power state (default)

Register 4

Switch K6/Audio Source Selection for Scart 3

Bit <5>

Bit <4>

Audio Decoder Output

PLL output

Audio deemphasis (K2 switch O/P)

Scart 2 return

High Z or low power state (default)

0

1

0

1

0

1

A

C

B

-

21/27

STV0056AF

CONTROL REGISTERS (continued)

Register 2

Left / Right / Stereo on Volume Output

Bit <7>

Bit <6>

0

1

0

1

Mono left / channel 1

Mono right / channel 2

Stereo left & right (default)

Register 5 : FM Deviation Selection

Selected Nominal Carrier Modulation

Bit 5 = 1

4

3

2

1

0

Bit 5 = 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Do not use

Cal. set. (2V)

592kHz

534kHz

484kHz

436kHz

396kHz

358kHz

322kHz

292kHz

266kHz

240kHz

218kHz

196kHz

179kHz

161kHz

146kHz

122kHz

120kHz

109kHz

98kHz

cal : do not use = 0.3373V offset on VCO

cal : do not use = 0.3053V offset on VCO

cal : do not use = 0.2763V offset on VCO

calibration setting (1V offset on VCO)

296kHz modulation

267kHz modulation

242kHz

218kHz

198kHz

179kHz

161kHz

146kHz

133kHz

120kHz

109kHz

98.3kHz

89.7kHz

80.9kHz

73.1kHz

66.0kHz

60.0kHz

54.4kHz = default power up state

49.1kHz

89kHz

44.3kHz

78kHz

39.8kHz

71kHz

35.9kHz

65kHz

32.4kHz

58kHz

29.1kHz

53kHz

26.7kHz

48.6kHz

43.8kHz

39.6kHz

24.3kHz

21.9kHz

19.7kHz

Example : Default power up state 54.4kHz

±54.4kHz.

Register 1

Bit <7>

Register 3

Bit <3>

Video Deemphasis/22kHz

0

1

0

1

0

1

Deemphasis 1 (default)

Deemphasis 1 + 22kHz

Deemphasis 2

Register 5

Digital I/O (STV0056AF pin 29)

Bit <7>

Bit <6>

0

1

0

1

0

1

I/O (refer to Register 6 Bit <0> Bit <1>)

22kHz

Do not use (for test only) (default)

22kHz

22/27

STV0056AF

FM DEMODULATION SOFTWARE ROUTINE

WiththeSTV0056AFcircuit, foreachchannel,three

steps are required to acheive a FM demodulation :

- 1^ststep :To set the demodulationparameters :

• FM deviation selection,

two completesequenceshaveto bedoneone after

the other when demodulatingstereo pairs.

Detailed Description

• Subcarrier frequency selection.

Conventions:

- R = Stands for Register

- B = Stands for Bit

- 2^ndstep : To implement a waiting loop to check

the actual VCO frequency.

- 3^rdstep:To close the demodulationphaselocked

loop (PLL).

Example : R05 B2 = Register 05, Bit 2

Refering to the FM demodulation block diagram

(page 12), the frequency synthesis block is com-

monto bothchannels(leftand right); consequently

For clarity, the explanations are based on the fol-

lowing example : stereo pair 7.02MHz/L

7.20MHz/R, deviation ±50kHz max.

1st STEP (LEFT) : SETTING THE DEMODULATION PARAMETERS

A. The FM deviation is selected by loadingR5 with

the appropriate value. (see R5 truth table).

The Table1 gives the setting for the most common

subcarrier frequencies.

NB : Very wide deviations (up to ±592kHz) can be

accomodatedwhen R5 B5 is low.

Table 1 : Frequency Synthesis Register Setting

for the Most Common Subcarrier Frequencies

Corresponding bandwidth can be calculated as

follows :

Bw ≈ 2 (FM deviation + audio bandwidth)

Bw ≈ 2 (value given in table + audio bandwidth)

Register 6

Subcarrier Frequency

(MHz)

Register 7

(Hex)

Bit 7 Bit 6

In the example :

5.58

5.76

5.8

8B

90

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R5Bits 7

X

6

X

5

1

4

1

3

0

2

1

0

91

B.

The subcarrier frequency is selected by

5.94

6.2

94

launchinga frequencysynthesis(theVCOis driven

to the wanted frequency). This operation requires

two actions :

- To connect the VCO to the frequency synthesis

loop. Referingto the FM blockdiagram(page 12):

• SW4 closed

• SW3 to bias

• SW2 to bias

• SW1 opened

9B

9D

A0

A2

A5

A6

AA

AB

AF

B4

B5

B8

BD

C1

C4

C6

CD

D8

6.3

6.4

6.48

6.5

R6 B2 = H

R6 B4 = L

R6 B3 = L

R6 B5 = L

6.6

6.65

6.8

- To load R7 and R6 B6 B7 with the value corre-

sponding to the left channel frequency. This 10

bits value is calculated as follows :

Subcarrier frequency = coded value x 10kHz

(10kHz is the minimum step of the frequency

synthesis function)

Considering that the tunning range is comprised

between5 to 10MHz,thecoded valueis anumber

between 500 and 1000 (2¹⁰= 1024) then 10 bits

are required.

6.85

7.02

7.20

7.25

7.38

7.56

7.74

7.85

7.92

8.2

Example :

7.02MHz = 702 x 10kHz

702

1010 1111 10

AF + 10

8.65

R7 is loaded with AF and R6 B6 : L, R6 B7 : H.

23/27

STV0056AF

FM DEMODULATION SOFTWARE ROUTINE (continued)

2^ndSTEP (LEFT) :

In practice :

VCO FREQUENCY CHECKING (VCO)

- SW3 closed R6 B4 = H

- SW4 opened R6 B2 = L

This second step is actuallya waitingloop in which

the actual running frequency of the VCO is meas-

ured.

After this sequence of 3 steps for left channel,

a similarsequenceis needed for the right channel.

To exit of this loop is allowed when : Subcarrier

Frequency - 10kHz ≤ MeasuredFrequency ≤ Sub-

carrier Frequency + 10kHz (± 10kHz is the maxi-

mum dispersion of the frequency synthesis

function).

Note :

In the sequence for the right, there is no need to

again select the FM deviation (once is enough for

the pair).

General Remark

In practice, R8 B2 B3 and R9 are read and com-

pared to the value loaded in R6 B6 B7 and R7

±1 bit.

Before to enable the demodulated signal to the

audiooutput, it is recommandedto keepthemuting

and to checkwhether a subcarrier is present at the

wanted frequency.Suchan informationis available

in R8 B0 and R8 B4 which can be read.

Note :

The duration of this step depends on how large is

frequency difference between the start frequency

and the targeted frequency. Typically :

- the rate of change of the VCO frequencyis about

3.75MHz/s (C_pump= 10µF)

- In addition to this settling time, 100ms must be

added to takeinto accountthe samplingperiod of

the watchdog.

Two differentstrategiescan be adoptedwhen ena-

bling the output :

- Either both left and right demodulatedsignals are

simultaneously authorized when both channel

are ready.

- Or while therightchannelsequenceis running,the

alreadyreadyleft signalis sent to the left andright

outputs and the real stereo sound L/R is output

when bothchannelsare ready. This secondoption

gives sound a few hundredsof ms before the first

one.

3^rdSTEP (LEFT)

TheFM demodulationcan be startedby connecting

the VCO to the phase locked loop (PLL).

24/27

STV0056AF

TYPICAL APPLICATION (3 SCARTS, PAL/SECAMEurope Apllication)

C7 2.2µF

C103 2.2µF

C104 2.2µF

C8 2.2µF

C6 2.2µF

C5 2.2µF

C105 2.2µF

C102 2.2µF

Ω

R5 68

R10368Ω

R4 470Ω

R6 75Ω

R100 75Ω

R101 470Ω

R102 75Ω

C56 100nF

R107 4.7kΩ

C108 8.2nF

R105 36kΩ

C38 22pF

+

R33 180kΩ

C39 2.7nF

R34 27kΩ

R39 27kΩ

C46 2.7nF

C58 100nF

R40 180kΩ

R51 560kΩ

R113 560kΩ

C47 22pF

C112 100nF

3 x 1N4148

25/27

STV0056AF

TWIN TUNER APPLICATION

Easy parallel connection of the outputs to the scarts without any additional switching hardware.

This configuration is possible due to the high impedance mode that can be selected for each audio and

video outputs.

Video

64

S

T

TUNER 1

2

V

0

5

6

A

F

TV

SCART

63

Audio

2

62-3

5-7

28

I²C Bus

23-24

Video

VCR

SCART

Audio

2

Video

64

2

S

T

V

0

5

TUNER 2

5V

DECODER

SCART

63

Audio

2

62-3

5-7

28

6

A

F

23-24

26/27

STV0056AF

PACKAGE MECHANICAL DATA

64 PINS - PLASTICQUAD FLAT PACK (THIN) (TQFP)

D

D1

D3

A

A2

A1

48

33

49

32

0.10mm

Seating Plane

17

64

1

16

C

e

K

TQFP64

Millimeters

Inches

Typ.

Dimensions

Min.

Typ.

Max.

1.60

0.15

1.45

0.28

0.20

Min.

Max.

0.063

0.006

0.057

0.011

0.0079

A

A1

A2

B

0.05

1.35

0.18

0.12

0.002

0.053

0.007

0.0047

1.40

0.23

0.055

0.009

0.0063

0.472

0.394

0.295

0.0197

0.472

0.394

0.295

C

0.16

D

12.00

10.00

7.50

D1

D3

e

0.50

E

12.00

10.00

7.50

E1

E3

K

1

0^o(Min.), 7^o(Max.)

L

0.40

0.60

1.00

0.75

0.0157

0.0236

0.0393

0.0295

L1

Information furnishedis believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsibility

for the consequences of use of such information nor for any infringement of patentsor other rights of third parties which may result

from itsuse. No licence is grantedby implication orotherwise underany patent or patent rights of SGS-THOMSON Microelectronics.

Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

information previouslysupplied. SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life

support devices or systems without express written approval of SGS-THOMSON Microelectronics.

Purchase of I²C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips

I²C Patent. Rights to use these components in a I²C system, is granted provided that the system conforms to

the I²C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco

The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

27/27


型号：	STV0056AF
厂家：	ST
描述：	SATELLITE SOUND AND VIDEO PROCESSOR 卫星声音和视频处理器消费电路商用集成电路信息通信管理
文件：	总27页 (文件大小：226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STV0056AF [STMICROELECTRONICS]

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